2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
11 * Johan Lorensson (lateralusx.github@gmail.com)
13 * (C) 2003 Ximian, Inc.
14 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
15 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
16 * Licensed under the MIT license. See LICENSE file in the project root for full license information.
26 #include <mono/metadata/abi-details.h>
27 #include <mono/metadata/appdomain.h>
28 #include <mono/metadata/debug-helpers.h>
29 #include <mono/metadata/threads.h>
30 #include <mono/metadata/profiler-private.h>
31 #include <mono/metadata/mono-debug.h>
32 #include <mono/metadata/gc-internals.h>
33 #include <mono/utils/mono-math.h>
34 #include <mono/utils/mono-mmap.h>
35 #include <mono/utils/mono-memory-model.h>
36 #include <mono/utils/mono-tls.h>
37 #include <mono/utils/mono-hwcap.h>
38 #include <mono/utils/mono-threads.h>
42 #include "mini-amd64.h"
43 #include "cpu-amd64.h"
44 #include "debugger-agent.h"
48 static gboolean optimize_for_xen = TRUE;
50 #define optimize_for_xen 0
53 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
55 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
57 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
60 /* Under windows, the calling convention is never stdcall */
61 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
63 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
66 /* This mutex protects architecture specific caches */
67 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
68 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
69 static mono_mutex_t mini_arch_mutex;
71 /* The single step trampoline */
72 static gpointer ss_trampoline;
74 /* The breakpoint trampoline */
75 static gpointer bp_trampoline;
77 /* Offset between fp and the first argument in the callee */
78 #define ARGS_OFFSET 16
79 #define GP_SCRATCH_REG AMD64_R11
82 * AMD64 register usage:
83 * - callee saved registers are used for global register allocation
84 * - %r11 is used for materializing 64 bit constants in opcodes
85 * - the rest is used for local allocation
89 * Floating point comparison results:
99 mono_arch_regname (int reg)
102 case AMD64_RAX: return "%rax";
103 case AMD64_RBX: return "%rbx";
104 case AMD64_RCX: return "%rcx";
105 case AMD64_RDX: return "%rdx";
106 case AMD64_RSP: return "%rsp";
107 case AMD64_RBP: return "%rbp";
108 case AMD64_RDI: return "%rdi";
109 case AMD64_RSI: return "%rsi";
110 case AMD64_R8: return "%r8";
111 case AMD64_R9: return "%r9";
112 case AMD64_R10: return "%r10";
113 case AMD64_R11: return "%r11";
114 case AMD64_R12: return "%r12";
115 case AMD64_R13: return "%r13";
116 case AMD64_R14: return "%r14";
117 case AMD64_R15: return "%r15";
122 static const char * packed_xmmregs [] = {
123 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
124 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
127 static const char * single_xmmregs [] = {
128 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
129 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
133 mono_arch_fregname (int reg)
135 if (reg < AMD64_XMM_NREG)
136 return single_xmmregs [reg];
142 mono_arch_xregname (int reg)
144 if (reg < AMD64_XMM_NREG)
145 return packed_xmmregs [reg];
154 return mono_debug_count ();
160 static inline gboolean
161 amd64_is_near_call (guint8 *code)
164 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
167 return code [0] == 0xe8;
170 static inline gboolean
171 amd64_use_imm32 (gint64 val)
173 if (mini_get_debug_options()->single_imm_size)
176 return amd64_is_imm32 (val);
180 amd64_patch (unsigned char* code, gpointer target)
185 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
190 if ((code [0] & 0xf8) == 0xb8) {
191 /* amd64_set_reg_template */
192 *(guint64*)(code + 1) = (guint64)target;
194 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
195 /* mov 0(%rip), %dreg */
196 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
198 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
199 /* call *<OFFSET>(%rip) */
200 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
202 else if (code [0] == 0xe8) {
204 gint64 disp = (guint8*)target - (guint8*)code;
205 g_assert (amd64_is_imm32 (disp));
206 x86_patch (code, (unsigned char*)target);
209 x86_patch (code, (unsigned char*)target);
213 mono_amd64_patch (unsigned char* code, gpointer target)
215 amd64_patch (code, target);
218 #define DEBUG(a) if (cfg->verbose_level > 1) a
221 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
223 ainfo->offset = *stack_size;
225 if (*gr >= PARAM_REGS) {
226 ainfo->storage = ArgOnStack;
227 ainfo->arg_size = sizeof (mgreg_t);
228 /* Since the same stack slot size is used for all arg */
229 /* types, it needs to be big enough to hold them all */
230 (*stack_size) += sizeof(mgreg_t);
233 ainfo->storage = ArgInIReg;
234 ainfo->reg = param_regs [*gr];
240 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
242 ainfo->offset = *stack_size;
244 if (*gr >= FLOAT_PARAM_REGS) {
245 ainfo->storage = ArgOnStack;
246 ainfo->arg_size = sizeof (mgreg_t);
247 /* Since the same stack slot size is used for both float */
248 /* types, it needs to be big enough to hold them both */
249 (*stack_size) += sizeof(mgreg_t);
252 /* A double register */
254 ainfo->storage = ArgInDoubleSSEReg;
256 ainfo->storage = ArgInFloatSSEReg;
262 typedef enum ArgumentClass {
270 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
272 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
275 ptype = mini_get_underlying_type (type);
276 switch (ptype->type) {
285 case MONO_TYPE_STRING:
286 case MONO_TYPE_OBJECT:
287 case MONO_TYPE_CLASS:
288 case MONO_TYPE_SZARRAY:
290 case MONO_TYPE_FNPTR:
291 case MONO_TYPE_ARRAY:
294 class2 = ARG_CLASS_INTEGER;
299 class2 = ARG_CLASS_INTEGER;
301 class2 = ARG_CLASS_SSE;
305 case MONO_TYPE_TYPEDBYREF:
306 g_assert_not_reached ();
308 case MONO_TYPE_GENERICINST:
309 if (!mono_type_generic_inst_is_valuetype (ptype)) {
310 class2 = ARG_CLASS_INTEGER;
314 case MONO_TYPE_VALUETYPE: {
315 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
318 for (i = 0; i < info->num_fields; ++i) {
320 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
325 g_assert_not_reached ();
329 if (class1 == class2)
331 else if (class1 == ARG_CLASS_NO_CLASS)
333 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
334 class1 = ARG_CLASS_MEMORY;
335 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
336 class1 = ARG_CLASS_INTEGER;
338 class1 = ARG_CLASS_SSE;
349 * collect_field_info_nested:
351 * Collect field info from KLASS recursively into FIELDS.
354 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
356 MonoMarshalType *info;
360 info = mono_marshal_load_type_info (klass);
362 for (i = 0; i < info->num_fields; ++i) {
363 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
364 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
369 f.type = info->fields [i].field->type;
370 f.size = mono_marshal_type_size (info->fields [i].field->type,
371 info->fields [i].mspec,
372 &align, TRUE, unicode);
373 f.offset = offset + info->fields [i].offset;
374 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
375 /* This can happen with .pack directives eg. 'fixed' arrays */
376 if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
377 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
378 g_array_append_val (fields_array, f);
379 while (f.size + f.offset < info->native_size) {
381 g_array_append_val (fields_array, f);
384 f.size = info->native_size - f.offset;
385 g_array_append_val (fields_array, f);
388 g_array_append_val (fields_array, f);
394 MonoClassField *field;
397 while ((field = mono_class_get_fields (klass, &iter))) {
398 if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
400 if (MONO_TYPE_ISSTRUCT (field->type)) {
401 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
406 f.type = field->type;
407 f.size = mono_type_size (field->type, &align);
408 f.offset = field->offset - sizeof (MonoObject) + offset;
410 g_array_append_val (fields_array, f);
418 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
419 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
422 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
424 gboolean result = FALSE;
426 assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
427 assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
429 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
430 arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
431 arg_info->pair_size [0] = 0;
432 arg_info->pair_size [1] = 0;
435 if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
436 /* Pass parameter in integer register. */
437 arg_info->pair_storage [0] = ArgInIReg;
438 arg_info->pair_regs [0] = int_regs [*current_int_reg];
439 (*current_int_reg) ++;
441 } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
442 /* Pass parameter in float register. */
443 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
444 arg_info->pair_regs [0] = float_regs [*current_float_reg];
445 (*current_float_reg) ++;
449 if (result == TRUE) {
450 arg_info->pair_size [0] = arg_size;
457 static inline gboolean
458 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
460 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
463 static inline gboolean
464 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
466 return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
470 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
471 guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
473 /* Windows x64 value type ABI.
475 * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
477 * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
478 * Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
479 * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
480 * Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
482 * Return values: https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
484 * Integers/Float types smaller than or equal to 8 bytes
485 * Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
486 * Properly sized struct/unions (1,2,4,8)
487 * Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
488 * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
489 * Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
492 assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
496 /* Parameter cases. */
497 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
498 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
500 /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
501 arg_info->storage = ArgValuetypeInReg;
502 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
503 /* No more registers, fallback passing parameter on stack as value. */
504 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
506 /* Passing value directly on stack, so use size of value. */
507 arg_info->storage = ArgOnStack;
508 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
509 arg_info->offset = *stack_size;
510 arg_info->arg_size = arg_size;
511 *stack_size += arg_size;
514 /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
515 arg_info->storage = ArgValuetypeAddrInIReg;
516 if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
517 /* No more registers, fallback passing address to parameter on stack. */
518 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
520 /* Passing an address to value on stack, so use size of register as argument size. */
521 arg_info->storage = ArgValuetypeAddrOnStack;
522 arg_size = sizeof (mgreg_t);
523 arg_info->offset = *stack_size;
524 arg_info->arg_size = arg_size;
525 *stack_size += arg_size;
529 /* Return value cases. */
530 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
531 assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
533 /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
534 arg_info->storage = ArgValuetypeInReg;
535 allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
537 /* Only RAX/XMM0 should be used to return valuetype. */
538 assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
540 /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
541 arg_info->storage = ArgValuetypeAddrInIReg;
542 allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
544 /* Only RAX should be used to return valuetype address. */
545 assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
547 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
548 arg_info->offset = *stack_size;
549 *stack_size += arg_size;
555 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
558 *arg_class = ARG_CLASS_NO_CLASS;
560 assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
563 /* Calculate argument class type and size of marshalled type. */
564 MonoMarshalType *info = mono_marshal_load_type_info (klass);
565 *arg_size = info->native_size;
567 /* Calculate argument class type and size of managed type. */
568 *arg_size = mono_class_value_size (klass, NULL);
571 /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
572 *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
574 if (*arg_class == ARG_CLASS_MEMORY) {
575 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
576 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
580 * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
581 * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
582 * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
583 * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
584 * it must be represented in call and cannot be dropped.
586 if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
587 arg_info->pass_empty_struct = TRUE;
588 *arg_size = SIZEOF_REGISTER;
589 *arg_class = ARG_CLASS_INTEGER;
592 assert (*arg_class != ARG_CLASS_NO_CLASS);
596 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
597 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
599 guint32 arg_size = SIZEOF_REGISTER;
600 MonoClass *klass = NULL;
601 ArgumentClass arg_class;
603 assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
605 klass = mono_class_from_mono_type (type);
606 get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
608 /* Only drop value type if its not an empty struct as input that must be represented in call */
609 if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
610 arg_info->storage = ArgValuetypeInReg;
611 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
613 /* Alocate storage for value type. */
614 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
618 #endif /* TARGET_WIN32 */
621 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
623 guint32 *gr, guint32 *fr, guint32 *stack_size)
626 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
628 guint32 size, quad, nquads, i, nfields;
629 /* Keep track of the size used in each quad so we can */
630 /* use the right size when copying args/return vars. */
631 guint32 quadsize [2] = {8, 8};
632 ArgumentClass args [2];
633 StructFieldInfo *fields = NULL;
634 GArray *fields_array;
636 gboolean pass_on_stack = FALSE;
639 klass = mono_class_from_mono_type (type);
640 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
642 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
643 /* We pass and return vtypes of size 8 in a register */
644 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
645 pass_on_stack = TRUE;
648 /* If this struct can't be split up naturally into 8-byte */
649 /* chunks (registers), pass it on the stack. */
651 MonoMarshalType *info = mono_marshal_load_type_info (klass);
653 struct_size = info->native_size;
655 struct_size = mono_class_value_size (klass, NULL);
658 * Collect field information recursively to be able to
659 * handle nested structures.
661 fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
662 collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
663 fields = (StructFieldInfo*)fields_array->data;
664 nfields = fields_array->len;
666 for (i = 0; i < nfields; ++i) {
667 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
668 pass_on_stack = TRUE;
674 ainfo->storage = ArgValuetypeInReg;
675 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
680 /* Allways pass in memory */
681 ainfo->offset = *stack_size;
682 *stack_size += ALIGN_TO (size, 8);
683 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
685 ainfo->arg_size = ALIGN_TO (size, 8);
687 g_array_free (fields_array, TRUE);
697 int n = mono_class_value_size (klass, NULL);
699 quadsize [0] = n >= 8 ? 8 : n;
700 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
702 /* Always pass in 1 or 2 integer registers */
703 args [0] = ARG_CLASS_INTEGER;
704 args [1] = ARG_CLASS_INTEGER;
705 /* Only the simplest cases are supported */
706 if (is_return && nquads != 1) {
707 args [0] = ARG_CLASS_MEMORY;
708 args [1] = ARG_CLASS_MEMORY;
712 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
713 * The X87 and SSEUP stuff is left out since there are no such types in
717 ainfo->storage = ArgValuetypeInReg;
718 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
722 if (struct_size > 16) {
723 ainfo->offset = *stack_size;
724 *stack_size += ALIGN_TO (struct_size, 8);
725 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
727 ainfo->arg_size = ALIGN_TO (struct_size, 8);
729 g_array_free (fields_array, TRUE);
733 args [0] = ARG_CLASS_NO_CLASS;
734 args [1] = ARG_CLASS_NO_CLASS;
735 for (quad = 0; quad < nquads; ++quad) {
736 ArgumentClass class1;
739 class1 = ARG_CLASS_MEMORY;
741 class1 = ARG_CLASS_NO_CLASS;
742 for (i = 0; i < nfields; ++i) {
743 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
744 /* Unaligned field */
748 /* Skip fields in other quad */
749 if ((quad == 0) && (fields [i].offset >= 8))
751 if ((quad == 1) && (fields [i].offset < 8))
754 /* How far into this quad this data extends.*/
755 /* (8 is size of quad) */
756 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
758 class1 = merge_argument_class_from_type (fields [i].type, class1);
760 /* Empty structs have a nonzero size, causing this assert to be hit */
762 g_assert (class1 != ARG_CLASS_NO_CLASS);
763 args [quad] = class1;
767 g_array_free (fields_array, TRUE);
769 /* Post merger cleanup */
770 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
771 args [0] = args [1] = ARG_CLASS_MEMORY;
773 /* Allocate registers */
778 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
780 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
783 ainfo->storage = ArgValuetypeInReg;
784 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
785 g_assert (quadsize [0] <= 8);
786 g_assert (quadsize [1] <= 8);
787 ainfo->pair_size [0] = quadsize [0];
788 ainfo->pair_size [1] = quadsize [1];
789 ainfo->nregs = nquads;
790 for (quad = 0; quad < nquads; ++quad) {
791 switch (args [quad]) {
792 case ARG_CLASS_INTEGER:
793 if (*gr >= PARAM_REGS)
794 args [quad] = ARG_CLASS_MEMORY;
796 ainfo->pair_storage [quad] = ArgInIReg;
798 ainfo->pair_regs [quad] = return_regs [*gr];
800 ainfo->pair_regs [quad] = param_regs [*gr];
805 if (*fr >= FLOAT_PARAM_REGS)
806 args [quad] = ARG_CLASS_MEMORY;
808 if (quadsize[quad] <= 4)
809 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
810 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
811 ainfo->pair_regs [quad] = *fr;
815 case ARG_CLASS_MEMORY:
817 case ARG_CLASS_NO_CLASS:
820 g_assert_not_reached ();
824 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
826 /* Revert possible register assignments */
830 ainfo->offset = *stack_size;
832 arg_size = ALIGN_TO (struct_size, 8);
834 arg_size = nquads * sizeof(mgreg_t);
835 *stack_size += arg_size;
836 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
838 ainfo->arg_size = arg_size;
841 #endif /* !TARGET_WIN32 */
847 * Obtain information about a call according to the calling convention.
848 * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
849 * Draft Version 0.23" document for more information.
850 * For AMD64 Windows, see "Overview of x64 Calling Conventions",
851 * https://msdn.microsoft.com/en-us/library/ms235286.aspx
854 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
856 guint32 i, gr, fr, pstart;
858 int n = sig->hasthis + sig->param_count;
859 guint32 stack_size = 0;
861 gboolean is_pinvoke = sig->pinvoke;
864 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
866 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
869 cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
875 /* Reserve space where the callee can save the argument registers */
876 stack_size = 4 * sizeof (mgreg_t);
880 ret_type = mini_get_underlying_type (sig->ret);
881 switch (ret_type->type) {
891 case MONO_TYPE_FNPTR:
892 case MONO_TYPE_CLASS:
893 case MONO_TYPE_OBJECT:
894 case MONO_TYPE_SZARRAY:
895 case MONO_TYPE_ARRAY:
896 case MONO_TYPE_STRING:
897 cinfo->ret.storage = ArgInIReg;
898 cinfo->ret.reg = AMD64_RAX;
902 cinfo->ret.storage = ArgInIReg;
903 cinfo->ret.reg = AMD64_RAX;
906 cinfo->ret.storage = ArgInFloatSSEReg;
907 cinfo->ret.reg = AMD64_XMM0;
910 cinfo->ret.storage = ArgInDoubleSSEReg;
911 cinfo->ret.reg = AMD64_XMM0;
913 case MONO_TYPE_GENERICINST:
914 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
915 cinfo->ret.storage = ArgInIReg;
916 cinfo->ret.reg = AMD64_RAX;
919 if (mini_is_gsharedvt_type (ret_type)) {
920 cinfo->ret.storage = ArgGsharedvtVariableInReg;
924 case MONO_TYPE_VALUETYPE:
925 case MONO_TYPE_TYPEDBYREF: {
926 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
928 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
929 g_assert (cinfo->ret.storage != ArgInIReg);
934 g_assert (mini_is_gsharedvt_type (ret_type));
935 cinfo->ret.storage = ArgGsharedvtVariableInReg;
940 g_error ("Can't handle as return value 0x%x", ret_type->type);
945 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
946 * the first argument, allowing 'this' to be always passed in the first arg reg.
947 * Also do this if the first argument is a reference type, since virtual calls
948 * are sometimes made using calli without sig->hasthis set, like in the delegate
951 ArgStorage ret_storage = cinfo->ret.storage;
952 if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
954 add_general (&gr, &stack_size, cinfo->args + 0);
956 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
959 add_general (&gr, &stack_size, &cinfo->ret);
960 cinfo->ret.storage = ret_storage;
961 cinfo->vret_arg_index = 1;
965 add_general (&gr, &stack_size, cinfo->args + 0);
967 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
968 add_general (&gr, &stack_size, &cinfo->ret);
969 cinfo->ret.storage = ret_storage;
973 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
975 fr = FLOAT_PARAM_REGS;
977 /* Emit the signature cookie just before the implicit arguments */
978 add_general (&gr, &stack_size, &cinfo->sig_cookie);
981 for (i = pstart; i < sig->param_count; ++i) {
982 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
986 /* The float param registers and other param registers must be the same index on Windows x64.*/
993 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
994 /* We allways pass the sig cookie on the stack for simplicity */
996 * Prevent implicit arguments + the sig cookie from being passed
1000 fr = FLOAT_PARAM_REGS;
1002 /* Emit the signature cookie just before the implicit arguments */
1003 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1006 ptype = mini_get_underlying_type (sig->params [i]);
1007 switch (ptype->type) {
1010 add_general (&gr, &stack_size, ainfo);
1014 add_general (&gr, &stack_size, ainfo);
1018 add_general (&gr, &stack_size, ainfo);
1023 case MONO_TYPE_FNPTR:
1024 case MONO_TYPE_CLASS:
1025 case MONO_TYPE_OBJECT:
1026 case MONO_TYPE_STRING:
1027 case MONO_TYPE_SZARRAY:
1028 case MONO_TYPE_ARRAY:
1029 add_general (&gr, &stack_size, ainfo);
1031 case MONO_TYPE_GENERICINST:
1032 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1033 add_general (&gr, &stack_size, ainfo);
1036 if (mini_is_gsharedvt_variable_type (ptype)) {
1037 /* gsharedvt arguments are passed by ref */
1038 add_general (&gr, &stack_size, ainfo);
1039 if (ainfo->storage == ArgInIReg)
1040 ainfo->storage = ArgGSharedVtInReg;
1042 ainfo->storage = ArgGSharedVtOnStack;
1046 case MONO_TYPE_VALUETYPE:
1047 case MONO_TYPE_TYPEDBYREF:
1048 add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1053 add_general (&gr, &stack_size, ainfo);
1056 add_float (&fr, &stack_size, ainfo, FALSE);
1059 add_float (&fr, &stack_size, ainfo, TRUE);
1062 case MONO_TYPE_MVAR:
1063 /* gsharedvt arguments are passed by ref */
1064 g_assert (mini_is_gsharedvt_type (ptype));
1065 add_general (&gr, &stack_size, ainfo);
1066 if (ainfo->storage == ArgInIReg)
1067 ainfo->storage = ArgGSharedVtInReg;
1069 ainfo->storage = ArgGSharedVtOnStack;
1072 g_assert_not_reached ();
1076 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1078 fr = FLOAT_PARAM_REGS;
1080 /* Emit the signature cookie just before the implicit arguments */
1081 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1084 cinfo->stack_usage = stack_size;
1085 cinfo->reg_usage = gr;
1086 cinfo->freg_usage = fr;
1091 * mono_arch_get_argument_info:
1092 * @csig: a method signature
1093 * @param_count: the number of parameters to consider
1094 * @arg_info: an array to store the result infos
1096 * Gathers information on parameters such as size, alignment and
1097 * padding. arg_info should be large enought to hold param_count + 1 entries.
1099 * Returns the size of the argument area on the stack.
1102 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1105 CallInfo *cinfo = get_call_info (NULL, csig);
1106 guint32 args_size = cinfo->stack_usage;
1108 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1109 if (csig->hasthis) {
1110 arg_info [0].offset = 0;
1113 for (k = 0; k < param_count; k++) {
1114 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1116 arg_info [k + 1].size = 0;
1125 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1129 MonoType *callee_ret;
1131 c1 = get_call_info (NULL, caller_sig);
1132 c2 = get_call_info (NULL, callee_sig);
1133 res = c1->stack_usage >= c2->stack_usage;
1134 callee_ret = mini_get_underlying_type (callee_sig->ret);
1135 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1136 /* An address on the callee's stack is passed as the first argument */
1146 * Initialize the cpu to execute managed code.
1149 mono_arch_cpu_init (void)
1154 /* spec compliance requires running with double precision */
1155 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1156 fpcw &= ~X86_FPCW_PRECC_MASK;
1157 fpcw |= X86_FPCW_PREC_DOUBLE;
1158 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1159 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1161 /* TODO: This is crashing on Win64 right now.
1162 * _control87 (_PC_53, MCW_PC);
1168 * Initialize architecture specific code.
1171 mono_arch_init (void)
1173 mono_os_mutex_init_recursive (&mini_arch_mutex);
1175 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1176 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1177 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1178 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1179 mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1181 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1182 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1186 bp_trampoline = mini_get_breakpoint_trampoline ();
1190 * Cleanup architecture specific code.
1193 mono_arch_cleanup (void)
1195 mono_os_mutex_destroy (&mini_arch_mutex);
1199 * This function returns the optimizations supported on this cpu.
1202 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1208 if (mono_hwcap_x86_has_cmov) {
1209 opts |= MONO_OPT_CMOV;
1211 if (mono_hwcap_x86_has_fcmov)
1212 opts |= MONO_OPT_FCMOV;
1214 *exclude_mask |= MONO_OPT_FCMOV;
1216 *exclude_mask |= MONO_OPT_CMOV;
1220 /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1221 /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1222 /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1223 /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1224 /* will now have a reference to an argument that won't be fully decomposed. */
1225 *exclude_mask |= MONO_OPT_SIMD;
1232 * This function test for all SSE functions supported.
1234 * Returns a bitmask corresponding to all supported versions.
1238 mono_arch_cpu_enumerate_simd_versions (void)
1240 guint32 sse_opts = 0;
1242 if (mono_hwcap_x86_has_sse1)
1243 sse_opts |= SIMD_VERSION_SSE1;
1245 if (mono_hwcap_x86_has_sse2)
1246 sse_opts |= SIMD_VERSION_SSE2;
1248 if (mono_hwcap_x86_has_sse3)
1249 sse_opts |= SIMD_VERSION_SSE3;
1251 if (mono_hwcap_x86_has_ssse3)
1252 sse_opts |= SIMD_VERSION_SSSE3;
1254 if (mono_hwcap_x86_has_sse41)
1255 sse_opts |= SIMD_VERSION_SSE41;
1257 if (mono_hwcap_x86_has_sse42)
1258 sse_opts |= SIMD_VERSION_SSE42;
1260 if (mono_hwcap_x86_has_sse4a)
1261 sse_opts |= SIMD_VERSION_SSE4a;
1269 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1274 for (i = 0; i < cfg->num_varinfo; i++) {
1275 MonoInst *ins = cfg->varinfo [i];
1276 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1279 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1282 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1283 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1286 if (mono_is_regsize_var (ins->inst_vtype)) {
1287 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1288 g_assert (i == vmv->idx);
1289 vars = g_list_prepend (vars, vmv);
1293 vars = mono_varlist_sort (cfg, vars, 0);
1299 * mono_arch_compute_omit_fp:
1301 * Determine whenever the frame pointer can be eliminated.
1304 mono_arch_compute_omit_fp (MonoCompile *cfg)
1306 MonoMethodSignature *sig;
1307 MonoMethodHeader *header;
1311 if (cfg->arch.omit_fp_computed)
1314 header = cfg->header;
1316 sig = mono_method_signature (cfg->method);
1318 if (!cfg->arch.cinfo)
1319 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1320 cinfo = (CallInfo *)cfg->arch.cinfo;
1323 * FIXME: Remove some of the restrictions.
1325 cfg->arch.omit_fp = TRUE;
1326 cfg->arch.omit_fp_computed = TRUE;
1328 if (cfg->disable_omit_fp)
1329 cfg->arch.omit_fp = FALSE;
1331 if (!debug_omit_fp ())
1332 cfg->arch.omit_fp = FALSE;
1334 if (cfg->method->save_lmf)
1335 cfg->arch.omit_fp = FALSE;
1337 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1338 cfg->arch.omit_fp = FALSE;
1339 if (header->num_clauses)
1340 cfg->arch.omit_fp = FALSE;
1341 if (cfg->param_area)
1342 cfg->arch.omit_fp = FALSE;
1343 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1344 cfg->arch.omit_fp = FALSE;
1345 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1346 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1347 cfg->arch.omit_fp = FALSE;
1348 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1349 ArgInfo *ainfo = &cinfo->args [i];
1351 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1353 * The stack offset can only be determined when the frame
1356 cfg->arch.omit_fp = FALSE;
1361 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1362 MonoInst *ins = cfg->varinfo [i];
1365 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1370 mono_arch_get_global_int_regs (MonoCompile *cfg)
1374 mono_arch_compute_omit_fp (cfg);
1376 if (cfg->arch.omit_fp)
1377 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1379 /* We use the callee saved registers for global allocation */
1380 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1381 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1382 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1383 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1384 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1386 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1387 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1394 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1399 /* All XMM registers */
1400 for (i = 0; i < 16; ++i)
1401 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1407 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1409 static GList *r = NULL;
1414 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1415 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1416 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1417 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1418 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1419 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1421 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1422 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1423 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1424 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1425 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1426 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1427 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1428 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1430 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1437 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1440 static GList *r = NULL;
1445 for (i = 0; i < AMD64_XMM_NREG; ++i)
1446 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1448 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1455 * mono_arch_regalloc_cost:
1457 * Return the cost, in number of memory references, of the action of
1458 * allocating the variable VMV into a register during global register
1462 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1464 MonoInst *ins = cfg->varinfo [vmv->idx];
1466 if (cfg->method->save_lmf)
1467 /* The register is already saved */
1468 /* substract 1 for the invisible store in the prolog */
1469 return (ins->opcode == OP_ARG) ? 0 : 1;
1472 return (ins->opcode == OP_ARG) ? 1 : 2;
1476 * mono_arch_fill_argument_info:
1478 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1482 mono_arch_fill_argument_info (MonoCompile *cfg)
1485 MonoMethodSignature *sig;
1490 sig = mono_method_signature (cfg->method);
1492 cinfo = (CallInfo *)cfg->arch.cinfo;
1493 sig_ret = mini_get_underlying_type (sig->ret);
1496 * Contrary to mono_arch_allocate_vars (), the information should describe
1497 * where the arguments are at the beginning of the method, not where they can be
1498 * accessed during the execution of the method. The later makes no sense for the
1499 * global register allocator, since a variable can be in more than one location.
1501 switch (cinfo->ret.storage) {
1503 case ArgInFloatSSEReg:
1504 case ArgInDoubleSSEReg:
1505 cfg->ret->opcode = OP_REGVAR;
1506 cfg->ret->inst_c0 = cinfo->ret.reg;
1508 case ArgValuetypeInReg:
1509 cfg->ret->opcode = OP_REGOFFSET;
1510 cfg->ret->inst_basereg = -1;
1511 cfg->ret->inst_offset = -1;
1516 g_assert_not_reached ();
1519 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1520 ArgInfo *ainfo = &cinfo->args [i];
1522 ins = cfg->args [i];
1524 switch (ainfo->storage) {
1526 case ArgInFloatSSEReg:
1527 case ArgInDoubleSSEReg:
1528 ins->opcode = OP_REGVAR;
1529 ins->inst_c0 = ainfo->reg;
1532 ins->opcode = OP_REGOFFSET;
1533 ins->inst_basereg = -1;
1534 ins->inst_offset = -1;
1536 case ArgValuetypeInReg:
1538 ins->opcode = OP_NOP;
1541 g_assert_not_reached ();
1547 mono_arch_allocate_vars (MonoCompile *cfg)
1550 MonoMethodSignature *sig;
1553 guint32 locals_stack_size, locals_stack_align;
1557 sig = mono_method_signature (cfg->method);
1559 cinfo = (CallInfo *)cfg->arch.cinfo;
1560 sig_ret = mini_get_underlying_type (sig->ret);
1562 mono_arch_compute_omit_fp (cfg);
1565 * We use the ABI calling conventions for managed code as well.
1566 * Exception: valuetypes are only sometimes passed or returned in registers.
1570 * The stack looks like this:
1571 * <incoming arguments passed on the stack>
1573 * <lmf/caller saved registers>
1576 * <localloc area> -> grows dynamically
1580 if (cfg->arch.omit_fp) {
1581 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1582 cfg->frame_reg = AMD64_RSP;
1585 /* Locals are allocated backwards from %fp */
1586 cfg->frame_reg = AMD64_RBP;
1590 cfg->arch.saved_iregs = cfg->used_int_regs;
1591 if (cfg->method->save_lmf) {
1592 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1593 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1594 cfg->arch.saved_iregs |= iregs_to_save;
1597 if (cfg->arch.omit_fp)
1598 cfg->arch.reg_save_area_offset = offset;
1599 /* Reserve space for callee saved registers */
1600 for (i = 0; i < AMD64_NREG; ++i)
1601 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1602 offset += sizeof(mgreg_t);
1604 if (!cfg->arch.omit_fp)
1605 cfg->arch.reg_save_area_offset = -offset;
1607 if (sig_ret->type != MONO_TYPE_VOID) {
1608 switch (cinfo->ret.storage) {
1610 case ArgInFloatSSEReg:
1611 case ArgInDoubleSSEReg:
1612 cfg->ret->opcode = OP_REGVAR;
1613 cfg->ret->inst_c0 = cinfo->ret.reg;
1614 cfg->ret->dreg = cinfo->ret.reg;
1616 case ArgValuetypeAddrInIReg:
1617 case ArgGsharedvtVariableInReg:
1618 /* The register is volatile */
1619 cfg->vret_addr->opcode = OP_REGOFFSET;
1620 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1621 if (cfg->arch.omit_fp) {
1622 cfg->vret_addr->inst_offset = offset;
1626 cfg->vret_addr->inst_offset = -offset;
1628 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1629 printf ("vret_addr =");
1630 mono_print_ins (cfg->vret_addr);
1633 case ArgValuetypeInReg:
1634 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1635 cfg->ret->opcode = OP_REGOFFSET;
1636 cfg->ret->inst_basereg = cfg->frame_reg;
1637 if (cfg->arch.omit_fp) {
1638 cfg->ret->inst_offset = offset;
1639 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1641 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1642 cfg->ret->inst_offset = - offset;
1646 g_assert_not_reached ();
1650 /* Allocate locals */
1651 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1652 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1653 char *mname = mono_method_full_name (cfg->method, TRUE);
1654 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1659 if (locals_stack_align) {
1660 offset += (locals_stack_align - 1);
1661 offset &= ~(locals_stack_align - 1);
1663 if (cfg->arch.omit_fp) {
1664 cfg->locals_min_stack_offset = offset;
1665 cfg->locals_max_stack_offset = offset + locals_stack_size;
1667 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1668 cfg->locals_max_stack_offset = - offset;
1671 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1672 if (offsets [i] != -1) {
1673 MonoInst *ins = cfg->varinfo [i];
1674 ins->opcode = OP_REGOFFSET;
1675 ins->inst_basereg = cfg->frame_reg;
1676 if (cfg->arch.omit_fp)
1677 ins->inst_offset = (offset + offsets [i]);
1679 ins->inst_offset = - (offset + offsets [i]);
1680 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1683 offset += locals_stack_size;
1685 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1686 g_assert (!cfg->arch.omit_fp);
1687 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1688 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1691 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1692 ins = cfg->args [i];
1693 if (ins->opcode != OP_REGVAR) {
1694 ArgInfo *ainfo = &cinfo->args [i];
1695 gboolean inreg = TRUE;
1697 /* FIXME: Allocate volatile arguments to registers */
1698 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1702 * Under AMD64, all registers used to pass arguments to functions
1703 * are volatile across calls.
1704 * FIXME: Optimize this.
1706 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1709 ins->opcode = OP_REGOFFSET;
1711 switch (ainfo->storage) {
1713 case ArgInFloatSSEReg:
1714 case ArgInDoubleSSEReg:
1715 case ArgGSharedVtInReg:
1717 ins->opcode = OP_REGVAR;
1718 ins->dreg = ainfo->reg;
1722 case ArgGSharedVtOnStack:
1723 g_assert (!cfg->arch.omit_fp);
1724 ins->opcode = OP_REGOFFSET;
1725 ins->inst_basereg = cfg->frame_reg;
1726 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1728 case ArgValuetypeInReg:
1730 case ArgValuetypeAddrInIReg:
1731 case ArgValuetypeAddrOnStack: {
1733 g_assert (!cfg->arch.omit_fp);
1734 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1735 MONO_INST_NEW (cfg, indir, 0);
1737 indir->opcode = OP_REGOFFSET;
1738 if (ainfo->pair_storage [0] == ArgInIReg) {
1739 indir->inst_basereg = cfg->frame_reg;
1740 offset = ALIGN_TO (offset, sizeof (gpointer));
1741 offset += (sizeof (gpointer));
1742 indir->inst_offset = - offset;
1745 indir->inst_basereg = cfg->frame_reg;
1746 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1749 ins->opcode = OP_VTARG_ADDR;
1750 ins->inst_left = indir;
1758 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1759 ins->opcode = OP_REGOFFSET;
1760 ins->inst_basereg = cfg->frame_reg;
1761 /* These arguments are saved to the stack in the prolog */
1762 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1763 if (cfg->arch.omit_fp) {
1764 ins->inst_offset = offset;
1765 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1766 // Arguments are yet supported by the stack map creation code
1767 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1769 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1770 ins->inst_offset = - offset;
1771 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1777 cfg->stack_offset = offset;
1781 mono_arch_create_vars (MonoCompile *cfg)
1783 MonoMethodSignature *sig;
1787 sig = mono_method_signature (cfg->method);
1789 if (!cfg->arch.cinfo)
1790 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1791 cinfo = (CallInfo *)cfg->arch.cinfo;
1793 if (cinfo->ret.storage == ArgValuetypeInReg)
1794 cfg->ret_var_is_local = TRUE;
1796 sig_ret = mini_get_underlying_type (sig->ret);
1797 if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1798 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1799 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1800 printf ("vret_addr = ");
1801 mono_print_ins (cfg->vret_addr);
1805 if (cfg->gen_sdb_seq_points) {
1808 if (cfg->compile_aot) {
1809 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1810 ins->flags |= MONO_INST_VOLATILE;
1811 cfg->arch.seq_point_info_var = ins;
1813 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1814 ins->flags |= MONO_INST_VOLATILE;
1815 cfg->arch.ss_tramp_var = ins;
1817 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1818 ins->flags |= MONO_INST_VOLATILE;
1819 cfg->arch.bp_tramp_var = ins;
1822 if (cfg->method->save_lmf)
1823 cfg->create_lmf_var = TRUE;
1825 if (cfg->method->save_lmf) {
1827 #if !defined(TARGET_WIN32)
1828 if (!optimize_for_xen)
1829 cfg->lmf_ir_mono_lmf = TRUE;
1835 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1841 MONO_INST_NEW (cfg, ins, OP_MOVE);
1842 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1843 ins->sreg1 = tree->dreg;
1844 MONO_ADD_INS (cfg->cbb, ins);
1845 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1847 case ArgInFloatSSEReg:
1848 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1849 ins->dreg = mono_alloc_freg (cfg);
1850 ins->sreg1 = tree->dreg;
1851 MONO_ADD_INS (cfg->cbb, ins);
1853 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1855 case ArgInDoubleSSEReg:
1856 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1857 ins->dreg = mono_alloc_freg (cfg);
1858 ins->sreg1 = tree->dreg;
1859 MONO_ADD_INS (cfg->cbb, ins);
1861 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1865 g_assert_not_reached ();
1870 arg_storage_to_load_membase (ArgStorage storage)
1874 #if defined(__mono_ilp32__)
1875 return OP_LOADI8_MEMBASE;
1877 return OP_LOAD_MEMBASE;
1879 case ArgInDoubleSSEReg:
1880 return OP_LOADR8_MEMBASE;
1881 case ArgInFloatSSEReg:
1882 return OP_LOADR4_MEMBASE;
1884 g_assert_not_reached ();
1891 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1893 MonoMethodSignature *tmp_sig;
1896 if (call->tail_call)
1899 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1902 * mono_ArgIterator_Setup assumes the signature cookie is
1903 * passed first and all the arguments which were before it are
1904 * passed on the stack after the signature. So compensate by
1905 * passing a different signature.
1907 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1908 tmp_sig->param_count -= call->signature->sentinelpos;
1909 tmp_sig->sentinelpos = 0;
1910 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1912 sig_reg = mono_alloc_ireg (cfg);
1913 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1915 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1919 static inline LLVMArgStorage
1920 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1924 return LLVMArgInIReg;
1927 case ArgGSharedVtInReg:
1928 case ArgGSharedVtOnStack:
1929 return LLVMArgGSharedVt;
1931 g_assert_not_reached ();
1937 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1943 LLVMCallInfo *linfo;
1944 MonoType *t, *sig_ret;
1946 n = sig->param_count + sig->hasthis;
1947 sig_ret = mini_get_underlying_type (sig->ret);
1949 cinfo = get_call_info (cfg->mempool, sig);
1951 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1954 * LLVM always uses the native ABI while we use our own ABI, the
1955 * only difference is the handling of vtypes:
1956 * - we only pass/receive them in registers in some cases, and only
1957 * in 1 or 2 integer registers.
1959 switch (cinfo->ret.storage) {
1961 linfo->ret.storage = LLVMArgNone;
1964 case ArgInFloatSSEReg:
1965 case ArgInDoubleSSEReg:
1966 linfo->ret.storage = LLVMArgNormal;
1968 case ArgValuetypeInReg: {
1969 ainfo = &cinfo->ret;
1972 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1973 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1974 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1975 cfg->disable_llvm = TRUE;
1979 linfo->ret.storage = LLVMArgVtypeInReg;
1980 for (j = 0; j < 2; ++j)
1981 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1984 case ArgValuetypeAddrInIReg:
1985 case ArgGsharedvtVariableInReg:
1986 /* Vtype returned using a hidden argument */
1987 linfo->ret.storage = LLVMArgVtypeRetAddr;
1988 linfo->vret_arg_index = cinfo->vret_arg_index;
1991 g_assert_not_reached ();
1995 for (i = 0; i < n; ++i) {
1996 ainfo = cinfo->args + i;
1998 if (i >= sig->hasthis)
1999 t = sig->params [i - sig->hasthis];
2001 t = &mono_defaults.int_class->byval_arg;
2002 t = mini_type_get_underlying_type (t);
2004 linfo->args [i].storage = LLVMArgNone;
2006 switch (ainfo->storage) {
2008 linfo->args [i].storage = LLVMArgNormal;
2010 case ArgInDoubleSSEReg:
2011 case ArgInFloatSSEReg:
2012 linfo->args [i].storage = LLVMArgNormal;
2015 if (MONO_TYPE_ISSTRUCT (t))
2016 linfo->args [i].storage = LLVMArgVtypeByVal;
2018 linfo->args [i].storage = LLVMArgNormal;
2020 case ArgValuetypeInReg:
2022 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2023 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2024 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2025 cfg->disable_llvm = TRUE;
2029 linfo->args [i].storage = LLVMArgVtypeInReg;
2030 for (j = 0; j < 2; ++j)
2031 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2033 case ArgGSharedVtInReg:
2034 case ArgGSharedVtOnStack:
2035 linfo->args [i].storage = LLVMArgGSharedVt;
2038 cfg->exception_message = g_strdup ("ainfo->storage");
2039 cfg->disable_llvm = TRUE;
2049 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2052 MonoMethodSignature *sig;
2058 sig = call->signature;
2059 n = sig->param_count + sig->hasthis;
2061 cinfo = get_call_info (cfg->mempool, sig);
2065 if (COMPILE_LLVM (cfg)) {
2066 /* We shouldn't be called in the llvm case */
2067 cfg->disable_llvm = TRUE;
2072 * Emit all arguments which are passed on the stack to prevent register
2073 * allocation problems.
2075 for (i = 0; i < n; ++i) {
2077 ainfo = cinfo->args + i;
2079 in = call->args [i];
2081 if (sig->hasthis && i == 0)
2082 t = &mono_defaults.object_class->byval_arg;
2084 t = sig->params [i - sig->hasthis];
2086 t = mini_get_underlying_type (t);
2087 //XXX what about ArgGSharedVtOnStack here?
2088 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2090 if (t->type == MONO_TYPE_R4)
2091 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2092 else if (t->type == MONO_TYPE_R8)
2093 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2095 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2097 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2099 if (cfg->compute_gc_maps) {
2102 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2108 * Emit all parameters passed in registers in non-reverse order for better readability
2109 * and to help the optimization in emit_prolog ().
2111 for (i = 0; i < n; ++i) {
2112 ainfo = cinfo->args + i;
2114 in = call->args [i];
2116 if (ainfo->storage == ArgInIReg)
2117 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2120 for (i = n - 1; i >= 0; --i) {
2123 ainfo = cinfo->args + i;
2125 in = call->args [i];
2127 if (sig->hasthis && i == 0)
2128 t = &mono_defaults.object_class->byval_arg;
2130 t = sig->params [i - sig->hasthis];
2131 t = mini_get_underlying_type (t);
2133 switch (ainfo->storage) {
2137 case ArgInFloatSSEReg:
2138 case ArgInDoubleSSEReg:
2139 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2142 case ArgValuetypeInReg:
2143 case ArgValuetypeAddrInIReg:
2144 case ArgValuetypeAddrOnStack:
2145 case ArgGSharedVtInReg:
2146 case ArgGSharedVtOnStack: {
2147 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2148 /* Already emitted above */
2150 //FIXME what about ArgGSharedVtOnStack ?
2151 if (ainfo->storage == ArgOnStack && call->tail_call) {
2152 MonoInst *call_inst = (MonoInst*)call;
2153 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2154 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2162 size = mono_type_native_stack_size (t, &align);
2165 * Other backends use mono_type_stack_size (), but that
2166 * aligns the size to 8, which is larger than the size of
2167 * the source, leading to reads of invalid memory if the
2168 * source is at the end of address space.
2170 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2173 if (size >= 10000) {
2174 /* Avoid asserts in emit_memcpy () */
2175 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2176 /* Continue normally */
2179 if (size > 0 || ainfo->pass_empty_struct) {
2180 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2181 arg->sreg1 = in->dreg;
2182 arg->klass = mono_class_from_mono_type (t);
2183 arg->backend.size = size;
2184 arg->inst_p0 = call;
2185 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2186 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2188 MONO_ADD_INS (cfg->cbb, arg);
2193 g_assert_not_reached ();
2196 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2197 /* Emit the signature cookie just before the implicit arguments */
2198 emit_sig_cookie (cfg, call, cinfo);
2201 /* Handle the case where there are no implicit arguments */
2202 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2203 emit_sig_cookie (cfg, call, cinfo);
2205 switch (cinfo->ret.storage) {
2206 case ArgValuetypeInReg:
2207 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2209 * Tell the JIT to use a more efficient calling convention: call using
2210 * OP_CALL, compute the result location after the call, and save the
2213 call->vret_in_reg = TRUE;
2215 * Nullify the instruction computing the vret addr to enable
2216 * future optimizations.
2219 NULLIFY_INS (call->vret_var);
2221 if (call->tail_call)
2224 * The valuetype is in RAX:RDX after the call, need to be copied to
2225 * the stack. Push the address here, so the call instruction can
2228 if (!cfg->arch.vret_addr_loc) {
2229 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2230 /* Prevent it from being register allocated or optimized away */
2231 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2234 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2237 case ArgValuetypeAddrInIReg:
2238 case ArgGsharedvtVariableInReg: {
2240 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2241 vtarg->sreg1 = call->vret_var->dreg;
2242 vtarg->dreg = mono_alloc_preg (cfg);
2243 MONO_ADD_INS (cfg->cbb, vtarg);
2245 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2252 if (cfg->method->save_lmf) {
2253 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2254 MONO_ADD_INS (cfg->cbb, arg);
2257 call->stack_usage = cinfo->stack_usage;
2261 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2264 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2265 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2266 int size = ins->backend.size;
2268 switch (ainfo->storage) {
2269 case ArgValuetypeInReg: {
2273 for (part = 0; part < 2; ++part) {
2274 if (ainfo->pair_storage [part] == ArgNone)
2277 if (ainfo->pass_empty_struct) {
2278 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2279 NEW_ICONST (cfg, load, 0);
2282 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2283 load->inst_basereg = src->dreg;
2284 load->inst_offset = part * sizeof(mgreg_t);
2286 switch (ainfo->pair_storage [part]) {
2288 load->dreg = mono_alloc_ireg (cfg);
2290 case ArgInDoubleSSEReg:
2291 case ArgInFloatSSEReg:
2292 load->dreg = mono_alloc_freg (cfg);
2295 g_assert_not_reached ();
2299 MONO_ADD_INS (cfg->cbb, load);
2301 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2305 case ArgValuetypeAddrInIReg:
2306 case ArgValuetypeAddrOnStack: {
2307 MonoInst *vtaddr, *load;
2309 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2311 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2313 MONO_INST_NEW (cfg, load, OP_LDADDR);
2314 cfg->has_indirection = TRUE;
2315 load->inst_p0 = vtaddr;
2316 vtaddr->flags |= MONO_INST_INDIRECT;
2317 load->type = STACK_MP;
2318 load->klass = vtaddr->klass;
2319 load->dreg = mono_alloc_ireg (cfg);
2320 MONO_ADD_INS (cfg->cbb, load);
2321 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2323 if (ainfo->pair_storage [0] == ArgInIReg) {
2324 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2325 arg->dreg = mono_alloc_ireg (cfg);
2326 arg->sreg1 = load->dreg;
2328 MONO_ADD_INS (cfg->cbb, arg);
2329 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2331 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2335 case ArgGSharedVtInReg:
2337 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2339 case ArgGSharedVtOnStack:
2340 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2344 int dreg = mono_alloc_ireg (cfg);
2346 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2347 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2348 } else if (size <= 40) {
2349 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2351 // FIXME: Code growth
2352 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2355 if (cfg->compute_gc_maps) {
2357 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2363 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2365 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2367 if (ret->type == MONO_TYPE_R4) {
2368 if (COMPILE_LLVM (cfg))
2369 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2371 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2373 } else if (ret->type == MONO_TYPE_R8) {
2374 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2378 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2381 #endif /* DISABLE_JIT */
2383 #define EMIT_COND_BRANCH(ins,cond,sign) \
2384 if (ins->inst_true_bb->native_offset) { \
2385 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2387 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2388 if ((cfg->opt & MONO_OPT_BRANCH) && \
2389 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2390 x86_branch8 (code, cond, 0, sign); \
2392 x86_branch32 (code, cond, 0, sign); \
2396 MonoMethodSignature *sig;
2401 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2405 switch (cinfo->ret.storage) {
2408 case ArgInFloatSSEReg:
2409 case ArgInDoubleSSEReg:
2410 case ArgValuetypeAddrInIReg:
2411 case ArgValuetypeInReg:
2417 for (i = 0; i < cinfo->nargs; ++i) {
2418 ArgInfo *ainfo = &cinfo->args [i];
2419 switch (ainfo->storage) {
2421 case ArgInFloatSSEReg:
2422 case ArgInDoubleSSEReg:
2423 case ArgValuetypeInReg:
2426 if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2438 * mono_arch_dyn_call_prepare:
2440 * Return a pointer to an arch-specific structure which contains information
2441 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2442 * supported for SIG.
2443 * This function is equivalent to ffi_prep_cif in libffi.
2446 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2448 ArchDynCallInfo *info;
2451 cinfo = get_call_info (NULL, sig);
2453 if (!dyn_call_supported (sig, cinfo)) {
2458 info = g_new0 (ArchDynCallInfo, 1);
2459 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2461 info->cinfo = cinfo;
2463 return (MonoDynCallInfo*)info;
2467 * mono_arch_dyn_call_free:
2469 * Free a MonoDynCallInfo structure.
2472 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2474 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2476 g_free (ainfo->cinfo);
2480 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2481 #define GREG_TO_PTR(greg) (gpointer)(greg)
2484 * mono_arch_get_start_dyn_call:
2486 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2487 * store the result into BUF.
2488 * ARGS should be an array of pointers pointing to the arguments.
2489 * RET should point to a memory buffer large enought to hold the result of the
2491 * This function should be as fast as possible, any work which does not depend
2492 * on the actual values of the arguments should be done in
2493 * mono_arch_dyn_call_prepare ().
2494 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2498 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2500 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2501 DynCallArgs *p = (DynCallArgs*)buf;
2502 int arg_index, greg, freg, i, pindex;
2503 MonoMethodSignature *sig = dinfo->sig;
2504 int buffer_offset = 0;
2505 static int param_reg_to_index [16];
2506 static gboolean param_reg_to_index_inited;
2508 if (!param_reg_to_index_inited) {
2509 for (i = 0; i < PARAM_REGS; ++i)
2510 param_reg_to_index [param_regs [i]] = i;
2511 mono_memory_barrier ();
2512 param_reg_to_index_inited = 1;
2515 g_assert (buf_len >= sizeof (DynCallArgs));
2525 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2526 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2531 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2532 p->regs [greg ++] = PTR_TO_GREG(ret);
2534 for (; pindex < sig->param_count; pindex++) {
2535 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2536 gpointer *arg = args [arg_index ++];
2537 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2540 if (ainfo->storage == ArgOnStack) {
2541 slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2543 slot = param_reg_to_index [ainfo->reg];
2547 p->regs [slot] = PTR_TO_GREG(*(arg));
2553 case MONO_TYPE_STRING:
2554 case MONO_TYPE_CLASS:
2555 case MONO_TYPE_ARRAY:
2556 case MONO_TYPE_SZARRAY:
2557 case MONO_TYPE_OBJECT:
2561 #if !defined(__mono_ilp32__)
2565 p->regs [slot] = PTR_TO_GREG(*(arg));
2567 #if defined(__mono_ilp32__)
2570 p->regs [slot] = *(guint64*)(arg);
2574 p->regs [slot] = *(guint8*)(arg);
2577 p->regs [slot] = *(gint8*)(arg);
2580 p->regs [slot] = *(gint16*)(arg);
2583 p->regs [slot] = *(guint16*)(arg);
2586 p->regs [slot] = *(gint32*)(arg);
2589 p->regs [slot] = *(guint32*)(arg);
2591 case MONO_TYPE_R4: {
2594 *(float*)&d = *(float*)(arg);
2596 p->fregs [freg ++] = d;
2601 p->fregs [freg ++] = *(double*)(arg);
2603 case MONO_TYPE_GENERICINST:
2604 if (MONO_TYPE_IS_REFERENCE (t)) {
2605 p->regs [slot] = PTR_TO_GREG(*(arg));
2607 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2608 MonoClass *klass = mono_class_from_mono_type (t);
2609 guint8 *nullable_buf;
2612 size = mono_class_value_size (klass, NULL);
2613 nullable_buf = p->buffer + buffer_offset;
2614 buffer_offset += size;
2615 g_assert (buffer_offset <= 256);
2617 /* The argument pointed to by arg is either a boxed vtype or null */
2618 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2620 arg = (gpointer*)nullable_buf;
2626 case MONO_TYPE_VALUETYPE: {
2627 switch (ainfo->storage) {
2628 case ArgValuetypeInReg:
2629 for (i = 0; i < 2; ++i) {
2630 switch (ainfo->pair_storage [i]) {
2634 slot = param_reg_to_index [ainfo->pair_regs [i]];
2635 p->regs [slot] = ((mgreg_t*)(arg))[i];
2637 case ArgInDoubleSSEReg:
2639 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2642 g_assert_not_reached ();
2648 for (i = 0; i < ainfo->arg_size / 8; ++i)
2649 p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2652 g_assert_not_reached ();
2658 g_assert_not_reached ();
2664 * mono_arch_finish_dyn_call:
2666 * Store the result of a dyn call into the return value buffer passed to
2667 * start_dyn_call ().
2668 * This function should be as fast as possible, any work which does not depend
2669 * on the actual values of the arguments should be done in
2670 * mono_arch_dyn_call_prepare ().
2673 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2675 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2676 MonoMethodSignature *sig = dinfo->sig;
2677 DynCallArgs *dargs = (DynCallArgs*)buf;
2678 guint8 *ret = dargs->ret;
2679 mgreg_t res = dargs->res;
2680 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2683 switch (sig_ret->type) {
2684 case MONO_TYPE_VOID:
2685 *(gpointer*)ret = NULL;
2687 case MONO_TYPE_STRING:
2688 case MONO_TYPE_CLASS:
2689 case MONO_TYPE_ARRAY:
2690 case MONO_TYPE_SZARRAY:
2691 case MONO_TYPE_OBJECT:
2695 *(gpointer*)ret = GREG_TO_PTR(res);
2701 *(guint8*)ret = res;
2704 *(gint16*)ret = res;
2707 *(guint16*)ret = res;
2710 *(gint32*)ret = res;
2713 *(guint32*)ret = res;
2716 *(gint64*)ret = res;
2719 *(guint64*)ret = res;
2722 *(float*)ret = *(float*)&(dargs->fregs [0]);
2725 *(double*)ret = dargs->fregs [0];
2727 case MONO_TYPE_GENERICINST:
2728 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2729 *(gpointer*)ret = GREG_TO_PTR(res);
2734 case MONO_TYPE_VALUETYPE:
2735 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2738 ArgInfo *ainfo = &dinfo->cinfo->ret;
2740 g_assert (ainfo->storage == ArgValuetypeInReg);
2742 for (i = 0; i < 2; ++i) {
2743 switch (ainfo->pair_storage [0]) {
2745 ((mgreg_t*)ret)[i] = res;
2747 case ArgInDoubleSSEReg:
2748 ((double*)ret)[i] = dargs->fregs [i];
2753 g_assert_not_reached ();
2760 g_assert_not_reached ();
2764 /* emit an exception if condition is fail */
2765 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2767 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2768 if (tins == NULL) { \
2769 mono_add_patch_info (cfg, code - cfg->native_code, \
2770 MONO_PATCH_INFO_EXC, exc_name); \
2771 x86_branch32 (code, cond, 0, signed); \
2773 EMIT_COND_BRANCH (tins, cond, signed); \
2777 #define EMIT_FPCOMPARE(code) do { \
2778 amd64_fcompp (code); \
2779 amd64_fnstsw (code); \
2782 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2783 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2784 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2785 amd64_ ##op (code); \
2786 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2787 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2791 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2793 gboolean no_patch = FALSE;
2796 * FIXME: Add support for thunks
2799 gboolean near_call = FALSE;
2802 * Indirect calls are expensive so try to make a near call if possible.
2803 * The caller memory is allocated by the code manager so it is
2804 * guaranteed to be at a 32 bit offset.
2807 if (patch_type != MONO_PATCH_INFO_ABS) {
2808 /* The target is in memory allocated using the code manager */
2811 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2812 if (((MonoMethod*)data)->klass->image->aot_module)
2813 /* The callee might be an AOT method */
2815 if (((MonoMethod*)data)->dynamic)
2816 /* The target is in malloc-ed memory */
2820 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2822 * The call might go directly to a native function without
2825 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2827 gconstpointer target = mono_icall_get_wrapper (mi);
2828 if ((((guint64)target) >> 32) != 0)
2834 MonoJumpInfo *jinfo = NULL;
2836 if (cfg->abs_patches)
2837 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2839 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2840 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2841 if (mi && (((guint64)mi->func) >> 32) == 0)
2846 * This is not really an optimization, but required because the
2847 * generic class init trampolines use R11 to pass the vtable.
2852 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2854 if (info->func == info->wrapper) {
2856 if ((((guint64)info->func) >> 32) == 0)
2860 /* See the comment in mono_codegen () */
2861 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2865 else if ((((guint64)data) >> 32) == 0) {
2872 if (cfg->method->dynamic)
2873 /* These methods are allocated using malloc */
2876 #ifdef MONO_ARCH_NOMAP32BIT
2879 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2880 if (optimize_for_xen)
2883 if (cfg->compile_aot) {
2890 * Align the call displacement to an address divisible by 4 so it does
2891 * not span cache lines. This is required for code patching to work on SMP
2894 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2895 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2896 amd64_padding (code, pad_size);
2898 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2899 amd64_call_code (code, 0);
2902 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2903 amd64_set_reg_template (code, GP_SCRATCH_REG);
2904 amd64_call_reg (code, GP_SCRATCH_REG);
2911 static inline guint8*
2912 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2915 if (win64_adjust_stack)
2916 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2918 code = emit_call_body (cfg, code, patch_type, data);
2920 if (win64_adjust_stack)
2921 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2928 store_membase_imm_to_store_membase_reg (int opcode)
2931 case OP_STORE_MEMBASE_IMM:
2932 return OP_STORE_MEMBASE_REG;
2933 case OP_STOREI4_MEMBASE_IMM:
2934 return OP_STOREI4_MEMBASE_REG;
2935 case OP_STOREI8_MEMBASE_IMM:
2936 return OP_STOREI8_MEMBASE_REG;
2944 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2947 * mono_arch_peephole_pass_1:
2949 * Perform peephole opts which should/can be performed before local regalloc
2952 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2956 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2957 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2959 switch (ins->opcode) {
2963 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2965 * X86_LEA is like ADD, but doesn't have the
2966 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2967 * its operand to 64 bit.
2969 ins->opcode = OP_X86_LEA_MEMBASE;
2970 ins->inst_basereg = ins->sreg1;
2975 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2979 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2980 * the latter has length 2-3 instead of 6 (reverse constant
2981 * propagation). These instruction sequences are very common
2982 * in the initlocals bblock.
2984 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2985 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2986 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2987 ins2->sreg1 = ins->dreg;
2988 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2990 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2993 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3001 case OP_COMPARE_IMM:
3002 case OP_LCOMPARE_IMM:
3003 /* OP_COMPARE_IMM (reg, 0)
3005 * OP_AMD64_TEST_NULL (reg)
3008 ins->opcode = OP_AMD64_TEST_NULL;
3010 case OP_ICOMPARE_IMM:
3012 ins->opcode = OP_X86_TEST_NULL;
3014 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3016 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3017 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3019 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3020 * OP_COMPARE_IMM reg, imm
3022 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3024 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3025 ins->inst_basereg == last_ins->inst_destbasereg &&
3026 ins->inst_offset == last_ins->inst_offset) {
3027 ins->opcode = OP_ICOMPARE_IMM;
3028 ins->sreg1 = last_ins->sreg1;
3030 /* check if we can remove cmp reg,0 with test null */
3032 ins->opcode = OP_X86_TEST_NULL;
3038 mono_peephole_ins (bb, ins);
3043 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3047 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3048 switch (ins->opcode) {
3051 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3052 /* reg = 0 -> XOR (reg, reg) */
3053 /* XOR sets cflags on x86, so we cant do it always */
3054 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3055 ins->opcode = OP_LXOR;
3056 ins->sreg1 = ins->dreg;
3057 ins->sreg2 = ins->dreg;
3065 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3066 * 0 result into 64 bits.
3068 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3069 ins->opcode = OP_IXOR;
3073 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3077 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3078 * the latter has length 2-3 instead of 6 (reverse constant
3079 * propagation). These instruction sequences are very common
3080 * in the initlocals bblock.
3082 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3083 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3084 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3085 ins2->sreg1 = ins->dreg;
3086 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3088 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3091 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3100 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3101 ins->opcode = OP_X86_INC_REG;
3104 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3105 ins->opcode = OP_X86_DEC_REG;
3109 mono_peephole_ins (bb, ins);
3113 #define NEW_INS(cfg,ins,dest,op) do { \
3114 MONO_INST_NEW ((cfg), (dest), (op)); \
3115 (dest)->cil_code = (ins)->cil_code; \
3116 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3120 * mono_arch_lowering_pass:
3122 * Converts complex opcodes into simpler ones so that each IR instruction
3123 * corresponds to one machine instruction.
3126 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3128 MonoInst *ins, *n, *temp;
3131 * FIXME: Need to add more instructions, but the current machine
3132 * description can't model some parts of the composite instructions like
3135 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3136 switch (ins->opcode) {
3140 case OP_IDIV_UN_IMM:
3141 case OP_IREM_UN_IMM:
3144 mono_decompose_op_imm (cfg, bb, ins);
3146 case OP_COMPARE_IMM:
3147 case OP_LCOMPARE_IMM:
3148 if (!amd64_use_imm32 (ins->inst_imm)) {
3149 NEW_INS (cfg, ins, temp, OP_I8CONST);
3150 temp->inst_c0 = ins->inst_imm;
3151 temp->dreg = mono_alloc_ireg (cfg);
3152 ins->opcode = OP_COMPARE;
3153 ins->sreg2 = temp->dreg;
3156 #ifndef __mono_ilp32__
3157 case OP_LOAD_MEMBASE:
3159 case OP_LOADI8_MEMBASE:
3160 /* Don't generate memindex opcodes (to simplify */
3161 /* read sandboxing) */
3162 if (!amd64_use_imm32 (ins->inst_offset)) {
3163 NEW_INS (cfg, ins, temp, OP_I8CONST);
3164 temp->inst_c0 = ins->inst_offset;
3165 temp->dreg = mono_alloc_ireg (cfg);
3166 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3167 ins->inst_indexreg = temp->dreg;
3170 #ifndef __mono_ilp32__
3171 case OP_STORE_MEMBASE_IMM:
3173 case OP_STOREI8_MEMBASE_IMM:
3174 if (!amd64_use_imm32 (ins->inst_imm)) {
3175 NEW_INS (cfg, ins, temp, OP_I8CONST);
3176 temp->inst_c0 = ins->inst_imm;
3177 temp->dreg = mono_alloc_ireg (cfg);
3178 ins->opcode = OP_STOREI8_MEMBASE_REG;
3179 ins->sreg1 = temp->dreg;
3182 #ifdef MONO_ARCH_SIMD_INTRINSICS
3183 case OP_EXPAND_I1: {
3184 int temp_reg1 = mono_alloc_ireg (cfg);
3185 int temp_reg2 = mono_alloc_ireg (cfg);
3186 int original_reg = ins->sreg1;
3188 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3189 temp->sreg1 = original_reg;
3190 temp->dreg = temp_reg1;
3192 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3193 temp->sreg1 = temp_reg1;
3194 temp->dreg = temp_reg2;
3197 NEW_INS (cfg, ins, temp, OP_LOR);
3198 temp->sreg1 = temp->dreg = temp_reg2;
3199 temp->sreg2 = temp_reg1;
3201 ins->opcode = OP_EXPAND_I2;
3202 ins->sreg1 = temp_reg2;
3211 bb->max_vreg = cfg->next_vreg;
3215 branch_cc_table [] = {
3216 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3217 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3218 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3221 /* Maps CMP_... constants to X86_CC_... constants */
3224 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3225 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3229 cc_signed_table [] = {
3230 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3231 FALSE, FALSE, FALSE, FALSE
3234 /*#include "cprop.c"*/
3236 static unsigned char*
3237 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3240 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3242 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3245 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3247 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3251 static unsigned char*
3252 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3254 int sreg = tree->sreg1;
3255 int need_touch = FALSE;
3257 #if defined(TARGET_WIN32)
3259 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3260 if (!tree->flags & MONO_INST_INIT)
3269 * If requested stack size is larger than one page,
3270 * perform stack-touch operation
3273 * Generate stack probe code.
3274 * Under Windows, it is necessary to allocate one page at a time,
3275 * "touching" stack after each successful sub-allocation. This is
3276 * because of the way stack growth is implemented - there is a
3277 * guard page before the lowest stack page that is currently commited.
3278 * Stack normally grows sequentially so OS traps access to the
3279 * guard page and commits more pages when needed.
3281 amd64_test_reg_imm (code, sreg, ~0xFFF);
3282 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3284 br[2] = code; /* loop */
3285 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3286 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3287 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3288 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3289 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3290 amd64_patch (br[3], br[2]);
3291 amd64_test_reg_reg (code, sreg, sreg);
3292 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3293 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3295 br[1] = code; x86_jump8 (code, 0);
3297 amd64_patch (br[0], code);
3298 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3299 amd64_patch (br[1], code);
3300 amd64_patch (br[4], code);
3303 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3305 if (tree->flags & MONO_INST_INIT) {
3307 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3308 amd64_push_reg (code, AMD64_RAX);
3311 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3312 amd64_push_reg (code, AMD64_RCX);
3315 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3316 amd64_push_reg (code, AMD64_RDI);
3320 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3321 if (sreg != AMD64_RCX)
3322 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3323 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3325 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3326 if (cfg->param_area)
3327 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3329 amd64_prefix (code, X86_REP_PREFIX);
3332 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3333 amd64_pop_reg (code, AMD64_RDI);
3334 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3335 amd64_pop_reg (code, AMD64_RCX);
3336 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3337 amd64_pop_reg (code, AMD64_RAX);
3343 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3348 /* Move return value to the target register */
3349 /* FIXME: do this in the local reg allocator */
3350 switch (ins->opcode) {
3353 case OP_CALL_MEMBASE:
3356 case OP_LCALL_MEMBASE:
3357 g_assert (ins->dreg == AMD64_RAX);
3361 case OP_FCALL_MEMBASE: {
3362 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3363 if (rtype->type == MONO_TYPE_R4) {
3364 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3367 if (ins->dreg != AMD64_XMM0)
3368 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3374 case OP_RCALL_MEMBASE:
3375 if (ins->dreg != AMD64_XMM0)
3376 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3380 case OP_VCALL_MEMBASE:
3383 case OP_VCALL2_MEMBASE:
3384 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3385 if (cinfo->ret.storage == ArgValuetypeInReg) {
3386 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3388 /* Load the destination address */
3389 g_assert (loc->opcode == OP_REGOFFSET);
3390 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3392 for (quad = 0; quad < 2; quad ++) {
3393 switch (cinfo->ret.pair_storage [quad]) {
3395 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3397 case ArgInFloatSSEReg:
3398 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3400 case ArgInDoubleSSEReg:
3401 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3416 #endif /* DISABLE_JIT */
3419 static int tls_gs_offset;
3423 mono_arch_have_fast_tls (void)
3426 static gboolean have_fast_tls = FALSE;
3427 static gboolean inited = FALSE;
3430 if (mini_get_debug_options ()->use_fallback_tls)
3434 return have_fast_tls;
3436 ins = (guint8*)pthread_getspecific;
3439 * We're looking for these two instructions:
3441 * mov %gs:[offset](,%rdi,8),%rax
3444 have_fast_tls = ins [0] == 0x65 &&
3454 tls_gs_offset = ins[5];
3457 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3458 * For that version we're looking for these instructions:
3462 * mov %gs:[offset](,%rdi,8),%rax
3466 if (!have_fast_tls) {
3467 have_fast_tls = ins [0] == 0x55 &&
3482 tls_gs_offset = ins[9];
3486 return have_fast_tls;
3487 #elif defined(TARGET_ANDROID)
3490 if (mini_get_debug_options ()->use_fallback_tls)
3497 mono_amd64_get_tls_gs_offset (void)
3500 return tls_gs_offset;
3502 g_assert_not_reached ();
3508 * mono_amd64_emit_tls_get:
3509 * @code: buffer to store code to
3510 * @dreg: hard register where to place the result
3511 * @tls_offset: offset info
3513 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3514 * the dreg register the item in the thread local storage identified
3517 * Returns: a pointer to the end of the stored code
3520 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3523 if (tls_offset < 64) {
3524 x86_prefix (code, X86_GS_PREFIX);
3525 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3529 g_assert (tls_offset < 0x440);
3530 /* Load TEB->TlsExpansionSlots */
3531 x86_prefix (code, X86_GS_PREFIX);
3532 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3533 amd64_test_reg_reg (code, dreg, dreg);
3535 amd64_branch (code, X86_CC_EQ, code, TRUE);
3536 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3537 amd64_patch (buf [0], code);
3539 #elif defined(TARGET_MACH)
3540 x86_prefix (code, X86_GS_PREFIX);
3541 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3543 if (optimize_for_xen) {
3544 x86_prefix (code, X86_FS_PREFIX);
3545 amd64_mov_reg_mem (code, dreg, 0, 8);
3546 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3548 x86_prefix (code, X86_FS_PREFIX);
3549 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3556 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3559 g_assert_not_reached ();
3560 #elif defined(TARGET_MACH)
3561 x86_prefix (code, X86_GS_PREFIX);
3562 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3564 g_assert (!optimize_for_xen);
3565 x86_prefix (code, X86_FS_PREFIX);
3566 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3574 * Emit code to initialize an LMF structure at LMF_OFFSET.
3577 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3580 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3583 * sp is saved right before calls but we need to save it here too so
3584 * async stack walks would work.
3586 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3588 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3589 if (cfg->arch.omit_fp && cfa_offset != -1)
3590 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3592 /* These can't contain refs */
3593 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3594 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3595 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3596 /* These are handled automatically by the stack marking code */
3597 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3604 #define TEB_LAST_ERROR_OFFSET 0x068
3607 emit_get_last_error (guint8* code, int dreg)
3609 /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3610 x86_prefix (code, X86_GS_PREFIX);
3611 amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3619 emit_get_last_error (guint8* code, int dreg)
3621 g_assert_not_reached ();
3626 /* benchmark and set based on cpu */
3627 #define LOOP_ALIGNMENT 8
3628 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3632 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3637 guint8 *code = cfg->native_code + cfg->code_len;
3640 /* Fix max_offset estimate for each successor bb */
3641 if (cfg->opt & MONO_OPT_BRANCH) {
3642 int current_offset = cfg->code_len;
3643 MonoBasicBlock *current_bb;
3644 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3645 current_bb->max_offset = current_offset;
3646 current_offset += current_bb->max_length;
3650 if (cfg->opt & MONO_OPT_LOOP) {
3651 int pad, align = LOOP_ALIGNMENT;
3652 /* set alignment depending on cpu */
3653 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3655 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3656 amd64_padding (code, pad);
3657 cfg->code_len += pad;
3658 bb->native_offset = cfg->code_len;
3662 if (cfg->verbose_level > 2)
3663 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3665 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3666 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3667 g_assert (!cfg->compile_aot);
3669 cov->data [bb->dfn].cil_code = bb->cil_code;
3670 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3671 /* this is not thread save, but good enough */
3672 amd64_inc_membase (code, AMD64_R11, 0);
3675 offset = code - cfg->native_code;
3677 mono_debug_open_block (cfg, bb, offset);
3679 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3680 x86_breakpoint (code);
3682 MONO_BB_FOR_EACH_INS (bb, ins) {
3683 offset = code - cfg->native_code;
3685 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3687 #define EXTRA_CODE_SPACE (16)
3689 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3690 cfg->code_size *= 2;
3691 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3692 code = cfg->native_code + offset;
3693 cfg->stat_code_reallocs++;
3696 if (cfg->debug_info)
3697 mono_debug_record_line_number (cfg, ins, offset);
3699 switch (ins->opcode) {
3701 amd64_mul_reg (code, ins->sreg2, TRUE);
3704 amd64_mul_reg (code, ins->sreg2, FALSE);
3706 case OP_X86_SETEQ_MEMBASE:
3707 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3709 case OP_STOREI1_MEMBASE_IMM:
3710 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3712 case OP_STOREI2_MEMBASE_IMM:
3713 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3715 case OP_STOREI4_MEMBASE_IMM:
3716 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3718 case OP_STOREI1_MEMBASE_REG:
3719 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3721 case OP_STOREI2_MEMBASE_REG:
3722 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3724 /* In AMD64 NaCl, pointers are 4 bytes, */
3725 /* so STORE_* != STOREI8_*. Likewise below. */
3726 case OP_STORE_MEMBASE_REG:
3727 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3729 case OP_STOREI8_MEMBASE_REG:
3730 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3732 case OP_STOREI4_MEMBASE_REG:
3733 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3735 case OP_STORE_MEMBASE_IMM:
3736 /* In NaCl, this could be a PCONST type, which could */
3737 /* mean a pointer type was copied directly into the */
3738 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3739 /* the value would be 0x00000000FFFFFFFF which is */
3740 /* not proper for an imm32 unless you cast it. */
3741 g_assert (amd64_is_imm32 (ins->inst_imm));
3742 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3744 case OP_STOREI8_MEMBASE_IMM:
3745 g_assert (amd64_is_imm32 (ins->inst_imm));
3746 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3749 #ifdef __mono_ilp32__
3750 /* In ILP32, pointers are 4 bytes, so separate these */
3751 /* cases, use literal 8 below where we really want 8 */
3752 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3753 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3757 // FIXME: Decompose this earlier
3758 if (amd64_use_imm32 (ins->inst_imm))
3759 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3761 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3762 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3766 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3767 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3770 // FIXME: Decompose this earlier
3771 if (amd64_use_imm32 (ins->inst_imm))
3772 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3774 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3775 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3779 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3780 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3783 /* For NaCl, pointers are 4 bytes, so separate these */
3784 /* cases, use literal 8 below where we really want 8 */
3785 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3786 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3788 case OP_LOAD_MEMBASE:
3789 g_assert (amd64_is_imm32 (ins->inst_offset));
3790 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3792 case OP_LOADI8_MEMBASE:
3793 /* Use literal 8 instead of sizeof pointer or */
3794 /* register, we really want 8 for this opcode */
3795 g_assert (amd64_is_imm32 (ins->inst_offset));
3796 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3798 case OP_LOADI4_MEMBASE:
3799 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3801 case OP_LOADU4_MEMBASE:
3802 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3804 case OP_LOADU1_MEMBASE:
3805 /* The cpu zero extends the result into 64 bits */
3806 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3808 case OP_LOADI1_MEMBASE:
3809 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3811 case OP_LOADU2_MEMBASE:
3812 /* The cpu zero extends the result into 64 bits */
3813 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3815 case OP_LOADI2_MEMBASE:
3816 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3818 case OP_AMD64_LOADI8_MEMINDEX:
3819 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3821 case OP_LCONV_TO_I1:
3822 case OP_ICONV_TO_I1:
3824 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3826 case OP_LCONV_TO_I2:
3827 case OP_ICONV_TO_I2:
3829 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3831 case OP_LCONV_TO_U1:
3832 case OP_ICONV_TO_U1:
3833 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3835 case OP_LCONV_TO_U2:
3836 case OP_ICONV_TO_U2:
3837 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3840 /* Clean out the upper word */
3841 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3844 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3848 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3850 case OP_COMPARE_IMM:
3851 #if defined(__mono_ilp32__)
3852 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3853 g_assert (amd64_is_imm32 (ins->inst_imm));
3854 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3857 case OP_LCOMPARE_IMM:
3858 g_assert (amd64_is_imm32 (ins->inst_imm));
3859 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3861 case OP_X86_COMPARE_REG_MEMBASE:
3862 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3864 case OP_X86_TEST_NULL:
3865 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3867 case OP_AMD64_TEST_NULL:
3868 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3871 case OP_X86_ADD_REG_MEMBASE:
3872 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3874 case OP_X86_SUB_REG_MEMBASE:
3875 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3877 case OP_X86_AND_REG_MEMBASE:
3878 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3880 case OP_X86_OR_REG_MEMBASE:
3881 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3883 case OP_X86_XOR_REG_MEMBASE:
3884 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3887 case OP_X86_ADD_MEMBASE_IMM:
3888 /* FIXME: Make a 64 version too */
3889 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3891 case OP_X86_SUB_MEMBASE_IMM:
3892 g_assert (amd64_is_imm32 (ins->inst_imm));
3893 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3895 case OP_X86_AND_MEMBASE_IMM:
3896 g_assert (amd64_is_imm32 (ins->inst_imm));
3897 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3899 case OP_X86_OR_MEMBASE_IMM:
3900 g_assert (amd64_is_imm32 (ins->inst_imm));
3901 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3903 case OP_X86_XOR_MEMBASE_IMM:
3904 g_assert (amd64_is_imm32 (ins->inst_imm));
3905 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3907 case OP_X86_ADD_MEMBASE_REG:
3908 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3910 case OP_X86_SUB_MEMBASE_REG:
3911 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3913 case OP_X86_AND_MEMBASE_REG:
3914 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3916 case OP_X86_OR_MEMBASE_REG:
3917 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3919 case OP_X86_XOR_MEMBASE_REG:
3920 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3922 case OP_X86_INC_MEMBASE:
3923 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3925 case OP_X86_INC_REG:
3926 amd64_inc_reg_size (code, ins->dreg, 4);
3928 case OP_X86_DEC_MEMBASE:
3929 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3931 case OP_X86_DEC_REG:
3932 amd64_dec_reg_size (code, ins->dreg, 4);
3934 case OP_X86_MUL_REG_MEMBASE:
3935 case OP_X86_MUL_MEMBASE_REG:
3936 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3938 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3939 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3941 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3942 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3944 case OP_AMD64_COMPARE_MEMBASE_REG:
3945 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3947 case OP_AMD64_COMPARE_MEMBASE_IMM:
3948 g_assert (amd64_is_imm32 (ins->inst_imm));
3949 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3951 case OP_X86_COMPARE_MEMBASE8_IMM:
3952 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3954 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3955 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3957 case OP_AMD64_COMPARE_REG_MEMBASE:
3958 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3961 case OP_AMD64_ADD_REG_MEMBASE:
3962 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3964 case OP_AMD64_SUB_REG_MEMBASE:
3965 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3967 case OP_AMD64_AND_REG_MEMBASE:
3968 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3970 case OP_AMD64_OR_REG_MEMBASE:
3971 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3973 case OP_AMD64_XOR_REG_MEMBASE:
3974 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3977 case OP_AMD64_ADD_MEMBASE_REG:
3978 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3980 case OP_AMD64_SUB_MEMBASE_REG:
3981 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3983 case OP_AMD64_AND_MEMBASE_REG:
3984 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3986 case OP_AMD64_OR_MEMBASE_REG:
3987 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3989 case OP_AMD64_XOR_MEMBASE_REG:
3990 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3993 case OP_AMD64_ADD_MEMBASE_IMM:
3994 g_assert (amd64_is_imm32 (ins->inst_imm));
3995 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3997 case OP_AMD64_SUB_MEMBASE_IMM:
3998 g_assert (amd64_is_imm32 (ins->inst_imm));
3999 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4001 case OP_AMD64_AND_MEMBASE_IMM:
4002 g_assert (amd64_is_imm32 (ins->inst_imm));
4003 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4005 case OP_AMD64_OR_MEMBASE_IMM:
4006 g_assert (amd64_is_imm32 (ins->inst_imm));
4007 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4009 case OP_AMD64_XOR_MEMBASE_IMM:
4010 g_assert (amd64_is_imm32 (ins->inst_imm));
4011 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4015 amd64_breakpoint (code);
4017 case OP_RELAXED_NOP:
4018 x86_prefix (code, X86_REP_PREFIX);
4026 case OP_DUMMY_STORE:
4027 case OP_DUMMY_ICONST:
4028 case OP_DUMMY_R8CONST:
4029 case OP_NOT_REACHED:
4032 case OP_IL_SEQ_POINT:
4033 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4035 case OP_SEQ_POINT: {
4036 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4037 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4040 /* Load ss_tramp_var */
4041 /* This is equal to &ss_trampoline */
4042 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4043 /* Load the trampoline address */
4044 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4045 /* Call it if it is non-null */
4046 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4048 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4049 amd64_call_reg (code, AMD64_R11);
4050 amd64_patch (label, code);
4054 * This is the address which is saved in seq points,
4056 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4058 if (cfg->compile_aot) {
4059 guint32 offset = code - cfg->native_code;
4061 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4065 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4066 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4067 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4068 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4069 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4071 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4072 /* Call the trampoline */
4073 amd64_call_reg (code, AMD64_R11);
4074 amd64_patch (label, code);
4076 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4080 * Emit a test+branch against a constant, the constant will be overwritten
4081 * by mono_arch_set_breakpoint () to cause the test to fail.
4083 amd64_mov_reg_imm (code, AMD64_R11, 0);
4084 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4086 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4089 g_assert (var->opcode == OP_REGOFFSET);
4090 /* Load bp_tramp_var */
4091 /* This is equal to &bp_trampoline */
4092 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4093 /* Call the trampoline */
4094 amd64_call_membase (code, AMD64_R11, 0);
4095 amd64_patch (label, code);
4098 * Add an additional nop so skipping the bp doesn't cause the ip to point
4099 * to another IL offset.
4107 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4110 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4114 g_assert (amd64_is_imm32 (ins->inst_imm));
4115 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4118 g_assert (amd64_is_imm32 (ins->inst_imm));
4119 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4124 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4127 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4131 g_assert (amd64_is_imm32 (ins->inst_imm));
4132 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4135 g_assert (amd64_is_imm32 (ins->inst_imm));
4136 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4139 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4143 g_assert (amd64_is_imm32 (ins->inst_imm));
4144 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4147 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4152 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4154 switch (ins->inst_imm) {
4158 if (ins->dreg != ins->sreg1)
4159 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4160 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4163 /* LEA r1, [r2 + r2*2] */
4164 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4167 /* LEA r1, [r2 + r2*4] */
4168 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4171 /* LEA r1, [r2 + r2*2] */
4173 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4174 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4177 /* LEA r1, [r2 + r2*8] */
4178 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4181 /* LEA r1, [r2 + r2*4] */
4183 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4184 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4187 /* LEA r1, [r2 + r2*2] */
4189 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4190 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4193 /* LEA r1, [r2 + r2*4] */
4194 /* LEA r1, [r1 + r1*4] */
4195 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4196 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4199 /* LEA r1, [r2 + r2*4] */
4201 /* LEA r1, [r1 + r1*4] */
4202 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4203 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4204 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4207 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4214 /* Regalloc magic makes the div/rem cases the same */
4215 if (ins->sreg2 == AMD64_RDX) {
4216 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4218 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4221 amd64_div_reg (code, ins->sreg2, TRUE);
4226 if (ins->sreg2 == AMD64_RDX) {
4227 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4228 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4229 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4231 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4232 amd64_div_reg (code, ins->sreg2, FALSE);
4237 if (ins->sreg2 == AMD64_RDX) {
4238 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4239 amd64_cdq_size (code, 4);
4240 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4242 amd64_cdq_size (code, 4);
4243 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4248 if (ins->sreg2 == AMD64_RDX) {
4249 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4250 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4251 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4253 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4254 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4258 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4259 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4262 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4266 g_assert (amd64_is_imm32 (ins->inst_imm));
4267 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4270 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4274 g_assert (amd64_is_imm32 (ins->inst_imm));
4275 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4278 g_assert (ins->sreg2 == AMD64_RCX);
4279 amd64_shift_reg (code, X86_SHL, ins->dreg);
4282 g_assert (ins->sreg2 == AMD64_RCX);
4283 amd64_shift_reg (code, X86_SAR, ins->dreg);
4287 g_assert (amd64_is_imm32 (ins->inst_imm));
4288 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4291 g_assert (amd64_is_imm32 (ins->inst_imm));
4292 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4294 case OP_LSHR_UN_IMM:
4295 g_assert (amd64_is_imm32 (ins->inst_imm));
4296 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4299 g_assert (ins->sreg2 == AMD64_RCX);
4300 amd64_shift_reg (code, X86_SHR, ins->dreg);
4304 g_assert (amd64_is_imm32 (ins->inst_imm));
4305 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4310 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4313 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4316 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4319 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4323 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4326 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4329 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4332 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4335 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4338 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4341 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4344 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4347 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4350 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4353 amd64_neg_reg_size (code, ins->sreg1, 4);
4356 amd64_not_reg_size (code, ins->sreg1, 4);
4359 g_assert (ins->sreg2 == AMD64_RCX);
4360 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4363 g_assert (ins->sreg2 == AMD64_RCX);
4364 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4367 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4369 case OP_ISHR_UN_IMM:
4370 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4373 g_assert (ins->sreg2 == AMD64_RCX);
4374 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4377 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4380 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4383 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4384 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4386 case OP_IMUL_OVF_UN:
4387 case OP_LMUL_OVF_UN: {
4388 /* the mul operation and the exception check should most likely be split */
4389 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4390 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4391 /*g_assert (ins->sreg2 == X86_EAX);
4392 g_assert (ins->dreg == X86_EAX);*/
4393 if (ins->sreg2 == X86_EAX) {
4394 non_eax_reg = ins->sreg1;
4395 } else if (ins->sreg1 == X86_EAX) {
4396 non_eax_reg = ins->sreg2;
4398 /* no need to save since we're going to store to it anyway */
4399 if (ins->dreg != X86_EAX) {
4401 amd64_push_reg (code, X86_EAX);
4403 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4404 non_eax_reg = ins->sreg2;
4406 if (ins->dreg == X86_EDX) {
4409 amd64_push_reg (code, X86_EAX);
4413 amd64_push_reg (code, X86_EDX);
4415 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4416 /* save before the check since pop and mov don't change the flags */
4417 if (ins->dreg != X86_EAX)
4418 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4420 amd64_pop_reg (code, X86_EDX);
4422 amd64_pop_reg (code, X86_EAX);
4423 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4427 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4429 case OP_ICOMPARE_IMM:
4430 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4452 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4460 case OP_CMOV_INE_UN:
4461 case OP_CMOV_IGE_UN:
4462 case OP_CMOV_IGT_UN:
4463 case OP_CMOV_ILE_UN:
4464 case OP_CMOV_ILT_UN:
4470 case OP_CMOV_LNE_UN:
4471 case OP_CMOV_LGE_UN:
4472 case OP_CMOV_LGT_UN:
4473 case OP_CMOV_LLE_UN:
4474 case OP_CMOV_LLT_UN:
4475 g_assert (ins->dreg == ins->sreg1);
4476 /* This needs to operate on 64 bit values */
4477 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4481 amd64_not_reg (code, ins->sreg1);
4484 amd64_neg_reg (code, ins->sreg1);
4489 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4490 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4492 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4495 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4496 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4499 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4500 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4503 if (ins->dreg != ins->sreg1)
4504 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4506 case OP_AMD64_SET_XMMREG_R4: {
4508 if (ins->dreg != ins->sreg1)
4509 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4511 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4515 case OP_AMD64_SET_XMMREG_R8: {
4516 if (ins->dreg != ins->sreg1)
4517 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4521 MonoCallInst *call = (MonoCallInst*)ins;
4522 int i, save_area_offset;
4524 g_assert (!cfg->method->save_lmf);
4526 /* Restore callee saved registers */
4527 save_area_offset = cfg->arch.reg_save_area_offset;
4528 for (i = 0; i < AMD64_NREG; ++i)
4529 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4530 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4531 save_area_offset += 8;
4534 if (cfg->arch.omit_fp) {
4535 if (cfg->arch.stack_alloc_size)
4536 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4538 if (call->stack_usage)
4541 /* Copy arguments on the stack to our argument area */
4542 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4543 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4544 amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4548 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4549 amd64_pop_reg (code, AMD64_RBP);
4550 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4556 offset = code - cfg->native_code;
4557 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4558 if (cfg->compile_aot)
4559 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4561 amd64_set_reg_template (code, AMD64_R11);
4562 amd64_jump_reg (code, AMD64_R11);
4563 ins->flags |= MONO_INST_GC_CALLSITE;
4564 ins->backend.pc_offset = code - cfg->native_code;
4568 /* ensure ins->sreg1 is not NULL */
4569 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4572 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4573 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4583 call = (MonoCallInst*)ins;
4585 * The AMD64 ABI forces callers to know about varargs.
4587 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4588 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4589 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4591 * Since the unmanaged calling convention doesn't contain a
4592 * 'vararg' entry, we have to treat every pinvoke call as a
4593 * potential vararg call.
4597 for (i = 0; i < AMD64_XMM_NREG; ++i)
4598 if (call->used_fregs & (1 << i))
4601 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4603 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4606 if (ins->flags & MONO_INST_HAS_METHOD)
4607 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4609 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4610 ins->flags |= MONO_INST_GC_CALLSITE;
4611 ins->backend.pc_offset = code - cfg->native_code;
4612 code = emit_move_return_value (cfg, ins, code);
4619 case OP_VOIDCALL_REG:
4621 call = (MonoCallInst*)ins;
4623 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4624 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4625 ins->sreg1 = AMD64_R11;
4629 * The AMD64 ABI forces callers to know about varargs.
4631 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4632 if (ins->sreg1 == AMD64_RAX) {
4633 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4634 ins->sreg1 = AMD64_R11;
4636 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4637 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4639 * Since the unmanaged calling convention doesn't contain a
4640 * 'vararg' entry, we have to treat every pinvoke call as a
4641 * potential vararg call.
4645 for (i = 0; i < AMD64_XMM_NREG; ++i)
4646 if (call->used_fregs & (1 << i))
4648 if (ins->sreg1 == AMD64_RAX) {
4649 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4650 ins->sreg1 = AMD64_R11;
4653 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4655 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4658 amd64_call_reg (code, ins->sreg1);
4659 ins->flags |= MONO_INST_GC_CALLSITE;
4660 ins->backend.pc_offset = code - cfg->native_code;
4661 code = emit_move_return_value (cfg, ins, code);
4663 case OP_FCALL_MEMBASE:
4664 case OP_RCALL_MEMBASE:
4665 case OP_LCALL_MEMBASE:
4666 case OP_VCALL_MEMBASE:
4667 case OP_VCALL2_MEMBASE:
4668 case OP_VOIDCALL_MEMBASE:
4669 case OP_CALL_MEMBASE:
4670 call = (MonoCallInst*)ins;
4672 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4673 ins->flags |= MONO_INST_GC_CALLSITE;
4674 ins->backend.pc_offset = code - cfg->native_code;
4675 code = emit_move_return_value (cfg, ins, code);
4679 MonoInst *var = cfg->dyn_call_var;
4682 g_assert (var->opcode == OP_REGOFFSET);
4684 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4685 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4687 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4689 /* Save args buffer */
4690 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4692 /* Set fp arg regs */
4693 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4694 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4696 amd64_branch8 (code, X86_CC_Z, -1, 1);
4697 for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4698 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4699 amd64_patch (label, code);
4701 /* Set stack args */
4702 for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4703 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4704 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4707 /* Set argument registers */
4708 for (i = 0; i < PARAM_REGS; ++i)
4709 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4712 amd64_call_reg (code, AMD64_R10);
4714 ins->flags |= MONO_INST_GC_CALLSITE;
4715 ins->backend.pc_offset = code - cfg->native_code;
4718 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4719 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4720 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4721 amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4724 case OP_AMD64_SAVE_SP_TO_LMF: {
4725 MonoInst *lmf_var = cfg->lmf_var;
4726 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4730 g_assert_not_reached ();
4731 amd64_push_reg (code, ins->sreg1);
4733 case OP_X86_PUSH_IMM:
4734 g_assert_not_reached ();
4735 g_assert (amd64_is_imm32 (ins->inst_imm));
4736 amd64_push_imm (code, ins->inst_imm);
4738 case OP_X86_PUSH_MEMBASE:
4739 g_assert_not_reached ();
4740 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4742 case OP_X86_PUSH_OBJ: {
4743 int size = ALIGN_TO (ins->inst_imm, 8);
4745 g_assert_not_reached ();
4747 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4748 amd64_push_reg (code, AMD64_RDI);
4749 amd64_push_reg (code, AMD64_RSI);
4750 amd64_push_reg (code, AMD64_RCX);
4751 if (ins->inst_offset)
4752 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4754 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4755 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4756 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4758 amd64_prefix (code, X86_REP_PREFIX);
4760 amd64_pop_reg (code, AMD64_RCX);
4761 amd64_pop_reg (code, AMD64_RSI);
4762 amd64_pop_reg (code, AMD64_RDI);
4765 case OP_GENERIC_CLASS_INIT: {
4768 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4770 amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4772 amd64_branch8 (code, X86_CC_NZ, -1, 1);
4774 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4775 ins->flags |= MONO_INST_GC_CALLSITE;
4776 ins->backend.pc_offset = code - cfg->native_code;
4778 x86_patch (jump, code);
4783 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4785 case OP_X86_LEA_MEMBASE:
4786 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4789 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4792 /* keep alignment */
4793 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4794 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4795 code = mono_emit_stack_alloc (cfg, code, ins);
4796 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4797 if (cfg->param_area)
4798 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4800 case OP_LOCALLOC_IMM: {
4801 guint32 size = ins->inst_imm;
4802 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4804 if (ins->flags & MONO_INST_INIT) {
4808 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4809 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4811 for (i = 0; i < size; i += 8)
4812 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4813 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4815 amd64_mov_reg_imm (code, ins->dreg, size);
4816 ins->sreg1 = ins->dreg;
4818 code = mono_emit_stack_alloc (cfg, code, ins);
4819 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4822 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4823 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4825 if (cfg->param_area)
4826 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4830 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4831 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4832 (gpointer)"mono_arch_throw_exception", FALSE);
4833 ins->flags |= MONO_INST_GC_CALLSITE;
4834 ins->backend.pc_offset = code - cfg->native_code;
4838 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4839 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4840 (gpointer)"mono_arch_rethrow_exception", FALSE);
4841 ins->flags |= MONO_INST_GC_CALLSITE;
4842 ins->backend.pc_offset = code - cfg->native_code;
4845 case OP_CALL_HANDLER:
4847 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4848 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4849 amd64_call_imm (code, 0);
4850 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4851 /* Restore stack alignment */
4852 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4854 case OP_START_HANDLER: {
4855 /* Even though we're saving RSP, use sizeof */
4856 /* gpointer because spvar is of type IntPtr */
4857 /* see: mono_create_spvar_for_region */
4858 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4859 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4861 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4862 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4864 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4868 case OP_ENDFINALLY: {
4869 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4870 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4874 case OP_ENDFILTER: {
4875 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4876 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4877 /* The local allocator will put the result into RAX */
4882 if (ins->dreg != AMD64_RAX)
4883 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4886 ins->inst_c0 = code - cfg->native_code;
4889 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4890 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4892 if (ins->inst_target_bb->native_offset) {
4893 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4895 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4896 if ((cfg->opt & MONO_OPT_BRANCH) &&
4897 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4898 x86_jump8 (code, 0);
4900 x86_jump32 (code, 0);
4904 amd64_jump_reg (code, ins->sreg1);
4927 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4928 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4930 case OP_COND_EXC_EQ:
4931 case OP_COND_EXC_NE_UN:
4932 case OP_COND_EXC_LT:
4933 case OP_COND_EXC_LT_UN:
4934 case OP_COND_EXC_GT:
4935 case OP_COND_EXC_GT_UN:
4936 case OP_COND_EXC_GE:
4937 case OP_COND_EXC_GE_UN:
4938 case OP_COND_EXC_LE:
4939 case OP_COND_EXC_LE_UN:
4940 case OP_COND_EXC_IEQ:
4941 case OP_COND_EXC_INE_UN:
4942 case OP_COND_EXC_ILT:
4943 case OP_COND_EXC_ILT_UN:
4944 case OP_COND_EXC_IGT:
4945 case OP_COND_EXC_IGT_UN:
4946 case OP_COND_EXC_IGE:
4947 case OP_COND_EXC_IGE_UN:
4948 case OP_COND_EXC_ILE:
4949 case OP_COND_EXC_ILE_UN:
4950 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4952 case OP_COND_EXC_OV:
4953 case OP_COND_EXC_NO:
4955 case OP_COND_EXC_NC:
4956 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4957 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4959 case OP_COND_EXC_IOV:
4960 case OP_COND_EXC_INO:
4961 case OP_COND_EXC_IC:
4962 case OP_COND_EXC_INC:
4963 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4964 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4967 /* floating point opcodes */
4969 double d = *(double *)ins->inst_p0;
4971 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4972 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4975 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4976 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4981 float f = *(float *)ins->inst_p0;
4983 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4985 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4987 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4990 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4991 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4993 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4997 case OP_STORER8_MEMBASE_REG:
4998 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5000 case OP_LOADR8_MEMBASE:
5001 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5003 case OP_STORER4_MEMBASE_REG:
5005 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5007 /* This requires a double->single conversion */
5008 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5009 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5012 case OP_LOADR4_MEMBASE:
5014 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5016 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5017 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5020 case OP_ICONV_TO_R4:
5022 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5024 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5025 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5028 case OP_ICONV_TO_R8:
5029 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5031 case OP_LCONV_TO_R4:
5033 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5035 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5036 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5039 case OP_LCONV_TO_R8:
5040 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5042 case OP_FCONV_TO_R4:
5044 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5046 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5047 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5050 case OP_FCONV_TO_I1:
5051 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5053 case OP_FCONV_TO_U1:
5054 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5056 case OP_FCONV_TO_I2:
5057 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5059 case OP_FCONV_TO_U2:
5060 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5062 case OP_FCONV_TO_U4:
5063 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5065 case OP_FCONV_TO_I4:
5067 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5069 case OP_FCONV_TO_I8:
5070 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5073 case OP_RCONV_TO_I1:
5074 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5075 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5077 case OP_RCONV_TO_U1:
5078 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5079 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5081 case OP_RCONV_TO_I2:
5082 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5083 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5085 case OP_RCONV_TO_U2:
5086 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5087 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5089 case OP_RCONV_TO_I4:
5090 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5092 case OP_RCONV_TO_U4:
5093 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5095 case OP_RCONV_TO_I8:
5096 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5098 case OP_RCONV_TO_R8:
5099 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5101 case OP_RCONV_TO_R4:
5102 if (ins->dreg != ins->sreg1)
5103 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5106 case OP_LCONV_TO_R_UN: {
5109 /* Based on gcc code */
5110 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5111 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5114 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5115 br [1] = code; x86_jump8 (code, 0);
5116 amd64_patch (br [0], code);
5119 /* Save to the red zone */
5120 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5121 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5122 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5123 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5124 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5125 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5126 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5127 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5128 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5130 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5131 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5132 amd64_patch (br [1], code);
5135 case OP_LCONV_TO_OVF_U4:
5136 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5137 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5138 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5140 case OP_LCONV_TO_OVF_I4_UN:
5141 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5142 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5143 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5146 if (ins->dreg != ins->sreg1)
5147 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5150 if (ins->dreg != ins->sreg1)
5151 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5153 case OP_MOVE_F_TO_I4:
5155 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5157 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5158 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5161 case OP_MOVE_I4_TO_F:
5162 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5164 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5166 case OP_MOVE_F_TO_I8:
5167 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5169 case OP_MOVE_I8_TO_F:
5170 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5173 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5176 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5179 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5182 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5185 static double r8_0 = -0.0;
5187 g_assert (ins->sreg1 == ins->dreg);
5189 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5190 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5194 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5197 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5200 static guint64 d = 0x7fffffffffffffffUL;
5202 g_assert (ins->sreg1 == ins->dreg);
5204 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5205 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5209 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5213 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5216 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5219 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5222 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5225 static float r4_0 = -0.0;
5227 g_assert (ins->sreg1 == ins->dreg);
5229 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5230 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5231 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5236 g_assert (cfg->opt & MONO_OPT_CMOV);
5237 g_assert (ins->dreg == ins->sreg1);
5238 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5239 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5242 g_assert (cfg->opt & MONO_OPT_CMOV);
5243 g_assert (ins->dreg == ins->sreg1);
5244 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5245 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5248 g_assert (cfg->opt & MONO_OPT_CMOV);
5249 g_assert (ins->dreg == ins->sreg1);
5250 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5251 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5254 g_assert (cfg->opt & MONO_OPT_CMOV);
5255 g_assert (ins->dreg == ins->sreg1);
5256 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5257 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5260 g_assert (cfg->opt & MONO_OPT_CMOV);
5261 g_assert (ins->dreg == ins->sreg1);
5262 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5263 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5266 g_assert (cfg->opt & MONO_OPT_CMOV);
5267 g_assert (ins->dreg == ins->sreg1);
5268 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5269 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5272 g_assert (cfg->opt & MONO_OPT_CMOV);
5273 g_assert (ins->dreg == ins->sreg1);
5274 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5275 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5278 g_assert (cfg->opt & MONO_OPT_CMOV);
5279 g_assert (ins->dreg == ins->sreg1);
5280 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5281 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5287 * The two arguments are swapped because the fbranch instructions
5288 * depend on this for the non-sse case to work.
5290 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5294 * FIXME: Get rid of this.
5295 * The two arguments are swapped because the fbranch instructions
5296 * depend on this for the non-sse case to work.
5298 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5302 /* zeroing the register at the start results in
5303 * shorter and faster code (we can also remove the widening op)
5305 guchar *unordered_check;
5307 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5308 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5309 unordered_check = code;
5310 x86_branch8 (code, X86_CC_P, 0, FALSE);
5312 if (ins->opcode == OP_FCEQ) {
5313 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5314 amd64_patch (unordered_check, code);
5316 guchar *jump_to_end;
5317 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5319 x86_jump8 (code, 0);
5320 amd64_patch (unordered_check, code);
5321 amd64_inc_reg (code, ins->dreg);
5322 amd64_patch (jump_to_end, code);
5328 /* zeroing the register at the start results in
5329 * shorter and faster code (we can also remove the widening op)
5331 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5332 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5333 if (ins->opcode == OP_FCLT_UN) {
5334 guchar *unordered_check = code;
5335 guchar *jump_to_end;
5336 x86_branch8 (code, X86_CC_P, 0, FALSE);
5337 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5339 x86_jump8 (code, 0);
5340 amd64_patch (unordered_check, code);
5341 amd64_inc_reg (code, ins->dreg);
5342 amd64_patch (jump_to_end, code);
5344 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5349 guchar *unordered_check;
5350 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5351 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5352 unordered_check = code;
5353 x86_branch8 (code, X86_CC_P, 0, FALSE);
5354 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5355 amd64_patch (unordered_check, code);
5360 /* zeroing the register at the start results in
5361 * shorter and faster code (we can also remove the widening op)
5363 guchar *unordered_check;
5365 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5366 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5367 if (ins->opcode == OP_FCGT) {
5368 unordered_check = code;
5369 x86_branch8 (code, X86_CC_P, 0, FALSE);
5370 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5371 amd64_patch (unordered_check, code);
5373 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5378 guchar *unordered_check;
5379 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5380 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5381 unordered_check = code;
5382 x86_branch8 (code, X86_CC_P, 0, FALSE);
5383 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5384 amd64_patch (unordered_check, code);
5394 gboolean unordered = FALSE;
5396 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5397 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5399 switch (ins->opcode) {
5401 x86_cond = X86_CC_EQ;
5404 x86_cond = X86_CC_LT;
5407 x86_cond = X86_CC_GT;
5410 x86_cond = X86_CC_GT;
5414 x86_cond = X86_CC_LT;
5418 g_assert_not_reached ();
5423 guchar *unordered_check;
5424 guchar *jump_to_end;
5426 unordered_check = code;
5427 x86_branch8 (code, X86_CC_P, 0, FALSE);
5428 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5430 x86_jump8 (code, 0);
5431 amd64_patch (unordered_check, code);
5432 amd64_inc_reg (code, ins->dreg);
5433 amd64_patch (jump_to_end, code);
5435 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5439 case OP_FCLT_MEMBASE:
5440 case OP_FCGT_MEMBASE:
5441 case OP_FCLT_UN_MEMBASE:
5442 case OP_FCGT_UN_MEMBASE:
5443 case OP_FCEQ_MEMBASE: {
5444 guchar *unordered_check, *jump_to_end;
5447 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5448 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5450 switch (ins->opcode) {
5451 case OP_FCEQ_MEMBASE:
5452 x86_cond = X86_CC_EQ;
5454 case OP_FCLT_MEMBASE:
5455 case OP_FCLT_UN_MEMBASE:
5456 x86_cond = X86_CC_LT;
5458 case OP_FCGT_MEMBASE:
5459 case OP_FCGT_UN_MEMBASE:
5460 x86_cond = X86_CC_GT;
5463 g_assert_not_reached ();
5466 unordered_check = code;
5467 x86_branch8 (code, X86_CC_P, 0, FALSE);
5468 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5470 switch (ins->opcode) {
5471 case OP_FCEQ_MEMBASE:
5472 case OP_FCLT_MEMBASE:
5473 case OP_FCGT_MEMBASE:
5474 amd64_patch (unordered_check, code);
5476 case OP_FCLT_UN_MEMBASE:
5477 case OP_FCGT_UN_MEMBASE:
5479 x86_jump8 (code, 0);
5480 amd64_patch (unordered_check, code);
5481 amd64_inc_reg (code, ins->dreg);
5482 amd64_patch (jump_to_end, code);
5490 guchar *jump = code;
5491 x86_branch8 (code, X86_CC_P, 0, TRUE);
5492 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5493 amd64_patch (jump, code);
5497 /* Branch if C013 != 100 */
5498 /* branch if !ZF or (PF|CF) */
5499 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5500 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5501 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5504 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5507 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5508 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5512 if (ins->opcode == OP_FBGT) {
5515 /* skip branch if C1=1 */
5517 x86_branch8 (code, X86_CC_P, 0, FALSE);
5518 /* branch if (C0 | C3) = 1 */
5519 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5520 amd64_patch (br1, code);
5523 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5527 /* Branch if C013 == 100 or 001 */
5530 /* skip branch if C1=1 */
5532 x86_branch8 (code, X86_CC_P, 0, FALSE);
5533 /* branch if (C0 | C3) = 1 */
5534 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5535 amd64_patch (br1, code);
5539 /* Branch if C013 == 000 */
5540 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5543 /* Branch if C013=000 or 100 */
5546 /* skip branch if C1=1 */
5548 x86_branch8 (code, X86_CC_P, 0, FALSE);
5549 /* branch if C0=0 */
5550 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5551 amd64_patch (br1, code);
5555 /* Branch if C013 != 001 */
5556 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5557 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5560 /* Transfer value to the fp stack */
5561 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5562 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5563 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5565 amd64_push_reg (code, AMD64_RAX);
5567 amd64_fnstsw (code);
5568 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5569 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5570 amd64_pop_reg (code, AMD64_RAX);
5571 amd64_fstp (code, 0);
5572 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5573 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5576 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5580 code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5583 case OP_MEMORY_BARRIER: {
5584 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5588 case OP_ATOMIC_ADD_I4:
5589 case OP_ATOMIC_ADD_I8: {
5590 int dreg = ins->dreg;
5591 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5593 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5596 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5597 amd64_prefix (code, X86_LOCK_PREFIX);
5598 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5599 /* dreg contains the old value, add with sreg2 value */
5600 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5602 if (ins->dreg != dreg)
5603 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5607 case OP_ATOMIC_EXCHANGE_I4:
5608 case OP_ATOMIC_EXCHANGE_I8: {
5609 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5611 /* LOCK prefix is implied. */
5612 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5613 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5614 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5617 case OP_ATOMIC_CAS_I4:
5618 case OP_ATOMIC_CAS_I8: {
5621 if (ins->opcode == OP_ATOMIC_CAS_I8)
5627 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5628 * an explanation of how this works.
5630 g_assert (ins->sreg3 == AMD64_RAX);
5631 g_assert (ins->sreg1 != AMD64_RAX);
5632 g_assert (ins->sreg1 != ins->sreg2);
5634 amd64_prefix (code, X86_LOCK_PREFIX);
5635 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5637 if (ins->dreg != AMD64_RAX)
5638 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5641 case OP_ATOMIC_LOAD_I1: {
5642 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5645 case OP_ATOMIC_LOAD_U1: {
5646 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5649 case OP_ATOMIC_LOAD_I2: {
5650 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5653 case OP_ATOMIC_LOAD_U2: {
5654 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5657 case OP_ATOMIC_LOAD_I4: {
5658 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5661 case OP_ATOMIC_LOAD_U4:
5662 case OP_ATOMIC_LOAD_I8:
5663 case OP_ATOMIC_LOAD_U8: {
5664 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5667 case OP_ATOMIC_LOAD_R4: {
5668 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5669 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5672 case OP_ATOMIC_LOAD_R8: {
5673 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5676 case OP_ATOMIC_STORE_I1:
5677 case OP_ATOMIC_STORE_U1:
5678 case OP_ATOMIC_STORE_I2:
5679 case OP_ATOMIC_STORE_U2:
5680 case OP_ATOMIC_STORE_I4:
5681 case OP_ATOMIC_STORE_U4:
5682 case OP_ATOMIC_STORE_I8:
5683 case OP_ATOMIC_STORE_U8: {
5686 switch (ins->opcode) {
5687 case OP_ATOMIC_STORE_I1:
5688 case OP_ATOMIC_STORE_U1:
5691 case OP_ATOMIC_STORE_I2:
5692 case OP_ATOMIC_STORE_U2:
5695 case OP_ATOMIC_STORE_I4:
5696 case OP_ATOMIC_STORE_U4:
5699 case OP_ATOMIC_STORE_I8:
5700 case OP_ATOMIC_STORE_U8:
5705 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5707 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5711 case OP_ATOMIC_STORE_R4: {
5712 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5713 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5715 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5719 case OP_ATOMIC_STORE_R8: {
5722 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5726 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5730 case OP_CARD_TABLE_WBARRIER: {
5731 int ptr = ins->sreg1;
5732 int value = ins->sreg2;
5734 int nursery_shift, card_table_shift;
5735 gpointer card_table_mask;
5736 size_t nursery_size;
5738 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5739 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5740 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5742 /*If either point to the stack we can simply avoid the WB. This happens due to
5743 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5745 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5749 * We need one register we can clobber, we choose EDX and make sreg1
5750 * fixed EAX to work around limitations in the local register allocator.
5751 * sreg2 might get allocated to EDX, but that is not a problem since
5752 * we use it before clobbering EDX.
5754 g_assert (ins->sreg1 == AMD64_RAX);
5757 * This is the code we produce:
5760 * edx >>= nursery_shift
5761 * cmp edx, (nursery_start >> nursery_shift)
5764 * edx >>= card_table_shift
5770 if (mono_gc_card_table_nursery_check ()) {
5771 if (value != AMD64_RDX)
5772 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5773 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5774 if (shifted_nursery_start >> 31) {
5776 * The value we need to compare against is 64 bits, so we need
5777 * another spare register. We use RBX, which we save and
5780 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5781 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5782 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5783 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5785 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5787 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5789 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5790 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5791 if (card_table_mask)
5792 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5794 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5795 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5797 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5799 if (mono_gc_card_table_nursery_check ())
5800 x86_patch (br, code);
5803 #ifdef MONO_ARCH_SIMD_INTRINSICS
5804 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5806 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5809 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5812 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5815 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5818 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5821 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5824 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5825 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5828 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5831 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5834 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5837 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5840 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5843 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5846 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5849 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5852 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5855 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5858 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5861 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5864 case OP_PSHUFLEW_HIGH:
5865 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5866 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5868 case OP_PSHUFLEW_LOW:
5869 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5870 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5873 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5874 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5877 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5878 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5881 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5882 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5886 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5889 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5892 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5895 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5898 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5901 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5904 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5905 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5908 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5911 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5914 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5917 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5920 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5923 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5926 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5929 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5932 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5935 case OP_EXTRACT_MASK:
5936 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5940 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5943 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5946 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5950 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5953 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5956 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5959 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5963 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5966 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5969 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5972 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5976 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5979 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5982 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5986 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5989 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5992 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5996 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5999 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6003 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6006 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6009 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6013 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6016 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6019 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6023 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6026 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6029 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6032 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6036 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6039 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6042 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6045 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6048 case OP_PSUM_ABS_DIFF:
6049 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6052 case OP_UNPACK_LOWB:
6053 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6055 case OP_UNPACK_LOWW:
6056 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6058 case OP_UNPACK_LOWD:
6059 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6061 case OP_UNPACK_LOWQ:
6062 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6064 case OP_UNPACK_LOWPS:
6065 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6067 case OP_UNPACK_LOWPD:
6068 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6071 case OP_UNPACK_HIGHB:
6072 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6074 case OP_UNPACK_HIGHW:
6075 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6077 case OP_UNPACK_HIGHD:
6078 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6080 case OP_UNPACK_HIGHQ:
6081 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6083 case OP_UNPACK_HIGHPS:
6084 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6086 case OP_UNPACK_HIGHPD:
6087 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6091 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6094 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6097 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6100 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6103 case OP_PADDB_SAT_UN:
6104 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6106 case OP_PSUBB_SAT_UN:
6107 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6109 case OP_PADDW_SAT_UN:
6110 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6112 case OP_PSUBW_SAT_UN:
6113 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6117 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6120 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6123 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6126 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6130 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6133 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6136 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6138 case OP_PMULW_HIGH_UN:
6139 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6142 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6146 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6149 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6153 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6156 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6160 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6163 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6167 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6170 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6174 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6177 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6181 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6184 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6188 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6191 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6194 /*TODO: This is appart of the sse spec but not added
6196 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6199 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6204 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6207 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6210 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6213 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6216 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6219 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6222 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6225 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6228 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6231 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6235 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6238 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6242 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6243 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6245 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6250 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6252 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6253 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6257 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6259 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6260 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6261 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6265 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6267 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6270 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6272 case OP_EXTRACTX_U2:
6273 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6275 case OP_INSERTX_U1_SLOW:
6276 /*sreg1 is the extracted ireg (scratch)
6277 /sreg2 is the to be inserted ireg (scratch)
6278 /dreg is the xreg to receive the value*/
6280 /*clear the bits from the extracted word*/
6281 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6282 /*shift the value to insert if needed*/
6283 if (ins->inst_c0 & 1)
6284 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6285 /*join them together*/
6286 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6287 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6289 case OP_INSERTX_I4_SLOW:
6290 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6291 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6292 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6294 case OP_INSERTX_I8_SLOW:
6295 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6297 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6299 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6302 case OP_INSERTX_R4_SLOW:
6303 switch (ins->inst_c0) {
6306 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6308 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6311 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6313 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6315 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6316 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6319 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6321 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6323 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6324 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6327 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6329 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6331 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6332 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6336 case OP_INSERTX_R8_SLOW:
6338 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6340 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6342 case OP_STOREX_MEMBASE_REG:
6343 case OP_STOREX_MEMBASE:
6344 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6346 case OP_LOADX_MEMBASE:
6347 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6349 case OP_LOADX_ALIGNED_MEMBASE:
6350 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6352 case OP_STOREX_ALIGNED_MEMBASE_REG:
6353 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6355 case OP_STOREX_NTA_MEMBASE_REG:
6356 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6358 case OP_PREFETCH_MEMBASE:
6359 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6363 /*FIXME the peephole pass should have killed this*/
6364 if (ins->dreg != ins->sreg1)
6365 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6368 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6371 amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6373 case OP_ICONV_TO_R4_RAW:
6374 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6376 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6379 case OP_FCONV_TO_R8_X:
6380 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6383 case OP_XCONV_R8_TO_I4:
6384 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6385 switch (ins->backend.source_opcode) {
6386 case OP_FCONV_TO_I1:
6387 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6389 case OP_FCONV_TO_U1:
6390 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6392 case OP_FCONV_TO_I2:
6393 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6395 case OP_FCONV_TO_U2:
6396 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6402 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6403 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6404 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6407 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6408 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6411 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6412 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6416 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6418 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6419 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6421 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6424 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6425 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6428 case OP_LIVERANGE_START: {
6429 if (cfg->verbose_level > 1)
6430 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6431 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6434 case OP_LIVERANGE_END: {
6435 if (cfg->verbose_level > 1)
6436 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6437 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6440 case OP_GC_SAFE_POINT: {
6443 g_assert (mono_threads_is_coop_enabled ());
6445 amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6446 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6447 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6448 amd64_patch (br[0], code);
6452 case OP_GC_LIVENESS_DEF:
6453 case OP_GC_LIVENESS_USE:
6454 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6455 ins->backend.pc_offset = code - cfg->native_code;
6457 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6458 ins->backend.pc_offset = code - cfg->native_code;
6459 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6461 case OP_GET_LAST_ERROR:
6462 emit_get_last_error(code, ins->dreg);
6465 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6466 g_assert_not_reached ();
6469 if ((code - cfg->native_code - offset) > max_len) {
6470 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6471 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6472 g_assert_not_reached ();
6476 cfg->code_len = code - cfg->native_code;
6479 #endif /* DISABLE_JIT */
6482 mono_arch_register_lowlevel_calls (void)
6484 /* The signature doesn't matter */
6485 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6487 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6489 extern void __chkstk (void);
6490 mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6492 extern void ___chkstk_ms (void);
6493 mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6499 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6501 unsigned char *ip = ji->ip.i + code;
6504 * Debug code to help track down problems where the target of a near call is
6507 if (amd64_is_near_call (ip)) {
6508 gint64 disp = (guint8*)target - (guint8*)ip;
6510 if (!amd64_is_imm32 (disp)) {
6511 printf ("TYPE: %d\n", ji->type);
6513 case MONO_PATCH_INFO_INTERNAL_METHOD:
6514 printf ("V: %s\n", ji->data.name);
6516 case MONO_PATCH_INFO_METHOD_JUMP:
6517 case MONO_PATCH_INFO_METHOD:
6518 printf ("V: %s\n", ji->data.method->name);
6526 amd64_patch (ip, (gpointer)target);
6532 get_max_epilog_size (MonoCompile *cfg)
6534 int max_epilog_size = 16;
6536 if (cfg->method->save_lmf)
6537 max_epilog_size += 256;
6539 if (mono_jit_trace_calls != NULL)
6540 max_epilog_size += 50;
6542 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6543 max_epilog_size += 50;
6545 max_epilog_size += (AMD64_NREG * 2);
6547 return max_epilog_size;
6551 * This macro is used for testing whenever the unwinder works correctly at every point
6552 * where an async exception can happen.
6554 /* This will generate a SIGSEGV at the given point in the code */
6555 #define async_exc_point(code) do { \
6556 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6557 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6558 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6559 cfg->arch.async_point_count ++; \
6565 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6567 int cfa_offset = *cfa_offset_input;
6569 /* Allocate windows stack frame using stack probing method */
6572 if (alloc_size >= 0x1000) {
6573 amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6574 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6577 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6578 if (cfg->arch.omit_fp) {
6579 cfa_offset += alloc_size;
6580 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6581 async_exc_point (code);
6584 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6585 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6586 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6587 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6588 // that will retrieve the expected results.
6589 if (cfg->arch.omit_fp)
6590 mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6593 *cfa_offset_input = cfa_offset;
6596 #endif /* TARGET_WIN32 */
6599 mono_arch_emit_prolog (MonoCompile *cfg)
6601 MonoMethod *method = cfg->method;
6603 MonoMethodSignature *sig;
6605 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6608 MonoInst *lmf_var = cfg->lmf_var;
6609 gboolean args_clobbered = FALSE;
6610 gboolean trace = FALSE;
6612 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6614 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6616 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6619 /* Amount of stack space allocated by register saving code */
6622 /* Offset between RSP and the CFA */
6626 * The prolog consists of the following parts:
6630 * - save callee saved regs using moves
6632 * - save rgctx if needed
6633 * - save lmf if needed
6636 * - save rgctx if needed
6637 * - save lmf if needed
6638 * - save callee saved regs using moves
6643 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6644 // IP saved at CFA - 8
6645 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6646 async_exc_point (code);
6647 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6649 if (!cfg->arch.omit_fp) {
6650 amd64_push_reg (code, AMD64_RBP);
6652 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6653 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6654 async_exc_point (code);
6655 /* These are handled automatically by the stack marking code */
6656 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6658 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6659 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6660 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6661 async_exc_point (code);
6664 /* The param area is always at offset 0 from sp */
6665 /* This needs to be allocated here, since it has to come after the spill area */
6666 if (cfg->param_area) {
6667 if (cfg->arch.omit_fp)
6669 g_assert_not_reached ();
6670 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6673 if (cfg->arch.omit_fp) {
6675 * On enter, the stack is misaligned by the pushing of the return
6676 * address. It is either made aligned by the pushing of %rbp, or by
6679 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6680 if ((alloc_size % 16) == 0) {
6682 /* Mark the padding slot as NOREF */
6683 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6686 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6687 if (cfg->stack_offset != alloc_size) {
6688 /* Mark the padding slot as NOREF */
6689 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6691 cfg->arch.sp_fp_offset = alloc_size;
6695 cfg->arch.stack_alloc_size = alloc_size;
6697 /* Allocate stack frame */
6699 code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6702 /* See mono_emit_stack_alloc */
6703 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6704 guint32 remaining_size = alloc_size;
6705 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6706 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6707 guint32 offset = code - cfg->native_code;
6708 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6709 while (required_code_size >= (cfg->code_size - offset))
6710 cfg->code_size *= 2;
6711 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6712 code = cfg->native_code + offset;
6713 cfg->stat_code_reallocs++;
6716 while (remaining_size >= 0x1000) {
6717 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6718 if (cfg->arch.omit_fp) {
6719 cfa_offset += 0x1000;
6720 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6722 async_exc_point (code);
6724 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6725 remaining_size -= 0x1000;
6727 if (remaining_size) {
6728 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6729 if (cfg->arch.omit_fp) {
6730 cfa_offset += remaining_size;
6731 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6732 async_exc_point (code);
6736 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6737 if (cfg->arch.omit_fp) {
6738 cfa_offset += alloc_size;
6739 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6740 async_exc_point (code);
6746 /* Stack alignment check */
6751 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6752 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6753 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6755 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6756 amd64_breakpoint (code);
6757 amd64_patch (buf, code);
6761 if (mini_get_debug_options ()->init_stacks) {
6762 /* Fill the stack frame with a dummy value to force deterministic behavior */
6764 /* Save registers to the red zone */
6765 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6766 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6768 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6769 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6770 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6773 amd64_prefix (code, X86_REP_PREFIX);
6776 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6777 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6781 if (method->save_lmf)
6782 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6784 /* Save callee saved registers */
6785 if (cfg->arch.omit_fp) {
6786 save_area_offset = cfg->arch.reg_save_area_offset;
6787 /* Save caller saved registers after sp is adjusted */
6788 /* The registers are saved at the bottom of the frame */
6789 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6791 /* The registers are saved just below the saved rbp */
6792 save_area_offset = cfg->arch.reg_save_area_offset;
6795 for (i = 0; i < AMD64_NREG; ++i) {
6796 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6797 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6799 if (cfg->arch.omit_fp) {
6800 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6801 /* These are handled automatically by the stack marking code */
6802 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6804 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6808 save_area_offset += 8;
6809 async_exc_point (code);
6813 /* store runtime generic context */
6814 if (cfg->rgctx_var) {
6815 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6816 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6818 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6820 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6821 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6824 /* compute max_length in order to use short forward jumps */
6825 max_epilog_size = get_max_epilog_size (cfg);
6826 if (cfg->opt & MONO_OPT_BRANCH) {
6827 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6831 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6833 /* max alignment for loops */
6834 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6835 max_length += LOOP_ALIGNMENT;
6837 MONO_BB_FOR_EACH_INS (bb, ins) {
6838 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6841 /* Take prolog and epilog instrumentation into account */
6842 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6843 max_length += max_epilog_size;
6845 bb->max_length = max_length;
6849 sig = mono_method_signature (method);
6852 cinfo = (CallInfo *)cfg->arch.cinfo;
6854 if (sig->ret->type != MONO_TYPE_VOID) {
6855 /* Save volatile arguments to the stack */
6856 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6857 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6860 /* Keep this in sync with emit_load_volatile_arguments */
6861 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6862 ArgInfo *ainfo = cinfo->args + i;
6864 ins = cfg->args [i];
6866 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6867 /* Unused arguments */
6870 /* Save volatile arguments to the stack */
6871 if (ins->opcode != OP_REGVAR) {
6872 switch (ainfo->storage) {
6878 if (stack_offset & 0x1)
6880 else if (stack_offset & 0x2)
6882 else if (stack_offset & 0x4)
6887 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6890 * Save the original location of 'this',
6891 * get_generic_info_from_stack_frame () needs this to properly look up
6892 * the argument value during the handling of async exceptions.
6894 if (ins == cfg->args [0]) {
6895 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6896 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6900 case ArgInFloatSSEReg:
6901 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6903 case ArgInDoubleSSEReg:
6904 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6906 case ArgValuetypeInReg:
6907 for (quad = 0; quad < 2; quad ++) {
6908 switch (ainfo->pair_storage [quad]) {
6910 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6912 case ArgInFloatSSEReg:
6913 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6915 case ArgInDoubleSSEReg:
6916 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6921 g_assert_not_reached ();
6925 case ArgValuetypeAddrInIReg:
6926 if (ainfo->pair_storage [0] == ArgInIReg)
6927 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6929 case ArgValuetypeAddrOnStack:
6931 case ArgGSharedVtInReg:
6932 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6938 /* Argument allocated to (non-volatile) register */
6939 switch (ainfo->storage) {
6941 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6944 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6947 g_assert_not_reached ();
6950 if (ins == cfg->args [0]) {
6951 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6952 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6957 if (cfg->method->save_lmf)
6958 args_clobbered = TRUE;
6961 args_clobbered = TRUE;
6962 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6965 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6966 args_clobbered = TRUE;
6969 * Optimize the common case of the first bblock making a call with the same
6970 * arguments as the method. This works because the arguments are still in their
6971 * original argument registers.
6972 * FIXME: Generalize this
6974 if (!args_clobbered) {
6975 MonoBasicBlock *first_bb = cfg->bb_entry;
6977 int filter = FILTER_IL_SEQ_POINT;
6979 next = mono_bb_first_inst (first_bb, filter);
6980 if (!next && first_bb->next_bb) {
6981 first_bb = first_bb->next_bb;
6982 next = mono_bb_first_inst (first_bb, filter);
6985 if (first_bb->in_count > 1)
6988 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6989 ArgInfo *ainfo = cinfo->args + i;
6990 gboolean match = FALSE;
6992 ins = cfg->args [i];
6993 if (ins->opcode != OP_REGVAR) {
6994 switch (ainfo->storage) {
6996 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6997 if (next->dreg == ainfo->reg) {
7001 next->opcode = OP_MOVE;
7002 next->sreg1 = ainfo->reg;
7003 /* Only continue if the instruction doesn't change argument regs */
7004 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7014 /* Argument allocated to (non-volatile) register */
7015 switch (ainfo->storage) {
7017 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7028 next = mono_inst_next (next, filter);
7029 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7036 if (cfg->gen_sdb_seq_points) {
7037 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7039 /* Initialize seq_point_info_var */
7040 if (cfg->compile_aot) {
7041 /* Initialize the variable from a GOT slot */
7042 /* Same as OP_AOTCONST */
7043 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7044 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7045 g_assert (info_var->opcode == OP_REGOFFSET);
7046 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7049 if (cfg->compile_aot) {
7050 /* Initialize ss_tramp_var */
7051 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7052 g_assert (ins->opcode == OP_REGOFFSET);
7054 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7055 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7056 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7058 /* Initialize ss_tramp_var */
7059 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7060 g_assert (ins->opcode == OP_REGOFFSET);
7062 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7063 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7065 /* Initialize bp_tramp_var */
7066 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7067 g_assert (ins->opcode == OP_REGOFFSET);
7069 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7070 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7074 cfg->code_len = code - cfg->native_code;
7076 g_assert (cfg->code_len < cfg->code_size);
7082 mono_arch_emit_epilog (MonoCompile *cfg)
7084 MonoMethod *method = cfg->method;
7087 int max_epilog_size;
7089 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7090 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7092 max_epilog_size = get_max_epilog_size (cfg);
7094 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7095 cfg->code_size *= 2;
7096 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7097 cfg->stat_code_reallocs++;
7099 code = cfg->native_code + cfg->code_len;
7101 cfg->has_unwind_info_for_epilog = TRUE;
7103 /* Mark the start of the epilog */
7104 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7106 /* Save the uwind state which is needed by the out-of-line code */
7107 mono_emit_unwind_op_remember_state (cfg, code);
7109 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7110 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7112 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7114 if (method->save_lmf) {
7115 /* check if we need to restore protection of the stack after a stack overflow */
7116 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7118 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7119 /* we load the value in a separate instruction: this mechanism may be
7120 * used later as a safer way to do thread interruption
7122 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7123 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7125 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7126 /* note that the call trampoline will preserve eax/edx */
7127 x86_call_reg (code, X86_ECX);
7128 x86_patch (patch, code);
7130 /* FIXME: maybe save the jit tls in the prolog */
7132 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7133 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7137 /* Restore callee saved regs */
7138 for (i = 0; i < AMD64_NREG; ++i) {
7139 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7140 /* Restore only used_int_regs, not arch.saved_iregs */
7141 #if defined(MONO_SUPPORT_TASKLETS)
7144 int restore_reg=(cfg->used_int_regs & (1 << i));
7147 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7148 mono_emit_unwind_op_same_value (cfg, code, i);
7149 async_exc_point (code);
7151 save_area_offset += 8;
7155 /* Load returned vtypes into registers if needed */
7156 cinfo = (CallInfo *)cfg->arch.cinfo;
7157 if (cinfo->ret.storage == ArgValuetypeInReg) {
7158 ArgInfo *ainfo = &cinfo->ret;
7159 MonoInst *inst = cfg->ret;
7161 for (quad = 0; quad < 2; quad ++) {
7162 switch (ainfo->pair_storage [quad]) {
7164 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7166 case ArgInFloatSSEReg:
7167 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7169 case ArgInDoubleSSEReg:
7170 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7175 g_assert_not_reached ();
7180 if (cfg->arch.omit_fp) {
7181 if (cfg->arch.stack_alloc_size) {
7182 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7186 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7187 amd64_pop_reg (code, AMD64_RBP);
7188 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7191 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7194 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7195 async_exc_point (code);
7198 /* Restore the unwind state to be the same as before the epilog */
7199 mono_emit_unwind_op_restore_state (cfg, code);
7201 cfg->code_len = code - cfg->native_code;
7203 g_assert (cfg->code_len < cfg->code_size);
7207 mono_arch_emit_exceptions (MonoCompile *cfg)
7209 MonoJumpInfo *patch_info;
7212 MonoClass *exc_classes [16];
7213 guint8 *exc_throw_start [16], *exc_throw_end [16];
7214 guint32 code_size = 0;
7216 /* Compute needed space */
7217 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7218 if (patch_info->type == MONO_PATCH_INFO_EXC)
7220 if (patch_info->type == MONO_PATCH_INFO_R8)
7221 code_size += 8 + 15; /* sizeof (double) + alignment */
7222 if (patch_info->type == MONO_PATCH_INFO_R4)
7223 code_size += 4 + 15; /* sizeof (float) + alignment */
7224 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7225 code_size += 8 + 7; /*sizeof (void*) + alignment */
7228 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7229 cfg->code_size *= 2;
7230 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7231 cfg->stat_code_reallocs++;
7234 code = cfg->native_code + cfg->code_len;
7236 /* add code to raise exceptions */
7238 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7239 switch (patch_info->type) {
7240 case MONO_PATCH_INFO_EXC: {
7241 MonoClass *exc_class;
7245 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7247 exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7248 throw_ip = patch_info->ip.i;
7250 //x86_breakpoint (code);
7251 /* Find a throw sequence for the same exception class */
7252 for (i = 0; i < nthrows; ++i)
7253 if (exc_classes [i] == exc_class)
7256 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7257 x86_jump_code (code, exc_throw_start [i]);
7258 patch_info->type = MONO_PATCH_INFO_NONE;
7262 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7266 exc_classes [nthrows] = exc_class;
7267 exc_throw_start [nthrows] = code;
7269 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7271 patch_info->type = MONO_PATCH_INFO_NONE;
7273 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7275 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7280 exc_throw_end [nthrows] = code;
7290 g_assert(code < cfg->native_code + cfg->code_size);
7293 /* Handle relocations with RIP relative addressing */
7294 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7295 gboolean remove = FALSE;
7296 guint8 *orig_code = code;
7298 switch (patch_info->type) {
7299 case MONO_PATCH_INFO_R8:
7300 case MONO_PATCH_INFO_R4: {
7301 guint8 *pos, *patch_pos;
7304 /* The SSE opcodes require a 16 byte alignment */
7305 code = (guint8*)ALIGN_TO (code, 16);
7307 pos = cfg->native_code + patch_info->ip.i;
7308 if (IS_REX (pos [1])) {
7309 patch_pos = pos + 5;
7310 target_pos = code - pos - 9;
7313 patch_pos = pos + 4;
7314 target_pos = code - pos - 8;
7317 if (patch_info->type == MONO_PATCH_INFO_R8) {
7318 *(double*)code = *(double*)patch_info->data.target;
7319 code += sizeof (double);
7321 *(float*)code = *(float*)patch_info->data.target;
7322 code += sizeof (float);
7325 *(guint32*)(patch_pos) = target_pos;
7330 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7333 if (cfg->compile_aot)
7336 /*loading is faster against aligned addresses.*/
7337 code = (guint8*)ALIGN_TO (code, 8);
7338 memset (orig_code, 0, code - orig_code);
7340 pos = cfg->native_code + patch_info->ip.i;
7342 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7343 if (IS_REX (pos [1]))
7344 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7346 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7348 *(gpointer*)code = (gpointer)patch_info->data.target;
7349 code += sizeof (gpointer);
7359 if (patch_info == cfg->patch_info)
7360 cfg->patch_info = patch_info->next;
7364 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7366 tmp->next = patch_info->next;
7369 g_assert (code < cfg->native_code + cfg->code_size);
7372 cfg->code_len = code - cfg->native_code;
7374 g_assert (cfg->code_len < cfg->code_size);
7378 #endif /* DISABLE_JIT */
7381 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7383 guchar *code = (guchar *)p;
7384 MonoMethodSignature *sig;
7386 int i, n, stack_area = 0;
7388 /* Keep this in sync with mono_arch_get_argument_info */
7390 if (enable_arguments) {
7391 /* Allocate a new area on the stack and save arguments there */
7392 sig = mono_method_signature (cfg->method);
7394 n = sig->param_count + sig->hasthis;
7396 stack_area = ALIGN_TO (n * 8, 16);
7398 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7400 for (i = 0; i < n; ++i) {
7401 inst = cfg->args [i];
7403 if (inst->opcode == OP_REGVAR)
7404 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7406 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7407 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7412 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7413 amd64_set_reg_template (code, AMD64_ARG_REG1);
7414 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7415 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7417 if (enable_arguments)
7418 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7432 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7434 guchar *code = (guchar *)p;
7435 int save_mode = SAVE_NONE;
7436 MonoMethod *method = cfg->method;
7437 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7440 switch (ret_type->type) {
7441 case MONO_TYPE_VOID:
7442 /* special case string .ctor icall */
7443 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7444 save_mode = SAVE_EAX;
7446 save_mode = SAVE_NONE;
7450 save_mode = SAVE_EAX;
7454 save_mode = SAVE_XMM;
7456 case MONO_TYPE_GENERICINST:
7457 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7458 save_mode = SAVE_EAX;
7462 case MONO_TYPE_VALUETYPE:
7463 save_mode = SAVE_STRUCT;
7466 save_mode = SAVE_EAX;
7470 /* Save the result and copy it into the proper argument register */
7471 switch (save_mode) {
7473 amd64_push_reg (code, AMD64_RAX);
7475 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7476 if (enable_arguments)
7477 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7481 if (enable_arguments)
7482 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7485 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7486 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7488 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7490 * The result is already in the proper argument register so no copying
7497 g_assert_not_reached ();
7500 /* Set %al since this is a varargs call */
7501 if (save_mode == SAVE_XMM)
7502 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7504 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7506 if (preserve_argument_registers) {
7507 for (i = 0; i < PARAM_REGS; ++i)
7508 amd64_push_reg (code, param_regs [i]);
7511 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7512 amd64_set_reg_template (code, AMD64_ARG_REG1);
7513 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7515 if (preserve_argument_registers) {
7516 for (i = PARAM_REGS - 1; i >= 0; --i)
7517 amd64_pop_reg (code, param_regs [i]);
7520 /* Restore result */
7521 switch (save_mode) {
7523 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7524 amd64_pop_reg (code, AMD64_RAX);
7530 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7531 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7532 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7537 g_assert_not_reached ();
7544 mono_arch_flush_icache (guint8 *code, gint size)
7550 mono_arch_flush_register_windows (void)
7555 mono_arch_is_inst_imm (gint64 imm)
7557 return amd64_use_imm32 (imm);
7561 * Determine whenever the trap whose info is in SIGINFO is caused by
7565 mono_arch_is_int_overflow (void *sigctx, void *info)
7572 mono_sigctx_to_monoctx (sigctx, &ctx);
7574 rip = (guint8*)ctx.gregs [AMD64_RIP];
7576 if (IS_REX (rip [0])) {
7577 reg = amd64_rex_b (rip [0]);
7583 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7585 reg += x86_modrm_rm (rip [1]);
7587 value = ctx.gregs [reg];
7597 mono_arch_get_patch_offset (guint8 *code)
7603 * mono_breakpoint_clean_code:
7605 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7606 * breakpoints in the original code, they are removed in the copy.
7608 * Returns TRUE if no sw breakpoint was present.
7611 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7614 * If method_start is non-NULL we need to perform bound checks, since we access memory
7615 * at code - offset we could go before the start of the method and end up in a different
7616 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7619 if (!method_start || code - offset >= method_start) {
7620 memcpy (buf, code - offset, size);
7622 int diff = code - method_start;
7623 memset (buf, 0, size);
7624 memcpy (buf + offset - diff, method_start, diff + size - offset);
7630 mono_arch_get_this_arg_reg (guint8 *code)
7632 return AMD64_ARG_REG1;
7636 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7638 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7641 #define MAX_ARCH_DELEGATE_PARAMS 10
7644 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7646 guint8 *code, *start;
7647 GSList *unwind_ops = NULL;
7650 unwind_ops = mono_arch_get_cie_program ();
7653 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7655 /* Replace the this argument with the target */
7656 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7657 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7658 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7660 g_assert ((code - start) < 64);
7661 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7663 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7665 if (param_count == 0) {
7666 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7668 /* We have to shift the arguments left */
7669 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7670 for (i = 0; i < param_count; ++i) {
7673 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7675 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7677 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7681 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7683 g_assert ((code - start) < 64);
7684 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7687 mono_arch_flush_icache (start, code - start);
7690 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7692 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7693 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7697 if (mono_jit_map_is_enabled ()) {
7700 buff = (char*)"delegate_invoke_has_target";
7702 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7703 mono_emit_jit_tramp (start, code - start, buff);
7707 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7712 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7715 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7717 guint8 *code, *start;
7722 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7725 start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7727 unwind_ops = mono_arch_get_cie_program ();
7729 /* Replace the this argument with the target */
7730 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7731 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7734 /* Load the IMT reg */
7735 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7738 /* Load the vtable */
7739 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7740 amd64_jump_membase (code, AMD64_RAX, offset);
7741 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7743 tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7744 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7745 g_free (tramp_name);
7751 * mono_arch_get_delegate_invoke_impls:
7753 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7757 mono_arch_get_delegate_invoke_impls (void)
7760 MonoTrampInfo *info;
7763 get_delegate_invoke_impl (&info, TRUE, 0);
7764 res = g_slist_prepend (res, info);
7766 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7767 get_delegate_invoke_impl (&info, FALSE, i);
7768 res = g_slist_prepend (res, info);
7771 for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7772 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7773 res = g_slist_prepend (res, info);
7776 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7777 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7778 res = g_slist_prepend (res, info);
7779 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7780 res = g_slist_prepend (res, info);
7787 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7789 guint8 *code, *start;
7792 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7795 /* FIXME: Support more cases */
7796 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7800 static guint8* cached = NULL;
7805 if (mono_aot_only) {
7806 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7808 MonoTrampInfo *info;
7809 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7810 mono_tramp_info_register (info, NULL);
7813 mono_memory_barrier ();
7817 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7818 for (i = 0; i < sig->param_count; ++i)
7819 if (!mono_is_regsize_var (sig->params [i]))
7821 if (sig->param_count > 4)
7824 code = cache [sig->param_count];
7828 if (mono_aot_only) {
7829 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7830 start = (guint8 *)mono_aot_get_trampoline (name);
7833 MonoTrampInfo *info;
7834 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7835 mono_tramp_info_register (info, NULL);
7838 mono_memory_barrier ();
7840 cache [sig->param_count] = start;
7847 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7849 MonoTrampInfo *info;
7852 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7854 mono_tramp_info_register (info, NULL);
7859 mono_arch_finish_init (void)
7861 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7862 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7867 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7871 #define CMP_SIZE (6 + 1)
7872 #define CMP_REG_REG_SIZE (4 + 1)
7873 #define BR_SMALL_SIZE 2
7874 #define BR_LARGE_SIZE 6
7875 #define MOV_REG_IMM_SIZE 10
7876 #define MOV_REG_IMM_32BIT_SIZE 6
7877 #define JUMP_REG_SIZE (2 + 1)
7880 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7882 int i, distance = 0;
7883 for (i = start; i < target; ++i)
7884 distance += imt_entries [i]->chunk_size;
7889 * LOCKING: called with the domain lock held
7892 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7893 gpointer fail_tramp)
7897 guint8 *code, *start;
7898 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7901 for (i = 0; i < count; ++i) {
7902 MonoIMTCheckItem *item = imt_entries [i];
7903 if (item->is_equals) {
7904 if (item->check_target_idx) {
7905 if (!item->compare_done) {
7906 if (amd64_use_imm32 ((gint64)item->key))
7907 item->chunk_size += CMP_SIZE;
7909 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7911 if (item->has_target_code) {
7912 item->chunk_size += MOV_REG_IMM_SIZE;
7914 if (vtable_is_32bit)
7915 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7917 item->chunk_size += MOV_REG_IMM_SIZE;
7919 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7922 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7923 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7925 if (vtable_is_32bit)
7926 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7928 item->chunk_size += MOV_REG_IMM_SIZE;
7929 item->chunk_size += JUMP_REG_SIZE;
7930 /* with assert below:
7931 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7936 if (amd64_use_imm32 ((gint64)item->key))
7937 item->chunk_size += CMP_SIZE;
7939 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7940 item->chunk_size += BR_LARGE_SIZE;
7941 imt_entries [item->check_target_idx]->compare_done = TRUE;
7943 size += item->chunk_size;
7946 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7948 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7951 unwind_ops = mono_arch_get_cie_program ();
7953 for (i = 0; i < count; ++i) {
7954 MonoIMTCheckItem *item = imt_entries [i];
7955 item->code_target = code;
7956 if (item->is_equals) {
7957 gboolean fail_case = !item->check_target_idx && fail_tramp;
7959 if (item->check_target_idx || fail_case) {
7960 if (!item->compare_done || fail_case) {
7961 if (amd64_use_imm32 ((gint64)item->key))
7962 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7964 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7965 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7968 item->jmp_code = code;
7969 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7970 if (item->has_target_code) {
7971 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7972 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7974 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7975 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7979 amd64_patch (item->jmp_code, code);
7980 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7981 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7982 item->jmp_code = NULL;
7985 /* enable the commented code to assert on wrong method */
7987 if (amd64_is_imm32 (item->key))
7988 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7990 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7991 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7993 item->jmp_code = code;
7994 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7995 /* See the comment below about R10 */
7996 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7997 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7998 amd64_patch (item->jmp_code, code);
7999 amd64_breakpoint (code);
8000 item->jmp_code = NULL;
8002 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8003 needs to be preserved. R10 needs
8004 to be preserved for calls which
8005 require a runtime generic context,
8006 but interface calls don't. */
8007 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8008 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8012 if (amd64_use_imm32 ((gint64)item->key))
8013 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8015 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8016 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8018 item->jmp_code = code;
8019 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8020 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8022 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8024 g_assert (code - item->code_target <= item->chunk_size);
8026 /* patch the branches to get to the target items */
8027 for (i = 0; i < count; ++i) {
8028 MonoIMTCheckItem *item = imt_entries [i];
8029 if (item->jmp_code) {
8030 if (item->check_target_idx) {
8031 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8037 mono_stats.imt_trampolines_size += code - start;
8038 g_assert (code - start <= size);
8039 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8041 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8043 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8049 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8051 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8055 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8057 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8061 mono_arch_get_cie_program (void)
8065 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8066 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8074 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8076 MonoInst *ins = NULL;
8079 if (cmethod->klass == mono_defaults.math_class) {
8080 if (strcmp (cmethod->name, "Sin") == 0) {
8082 } else if (strcmp (cmethod->name, "Cos") == 0) {
8084 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8086 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8090 if (opcode && fsig->param_count == 1) {
8091 MONO_INST_NEW (cfg, ins, opcode);
8092 ins->type = STACK_R8;
8093 ins->dreg = mono_alloc_freg (cfg);
8094 ins->sreg1 = args [0]->dreg;
8095 MONO_ADD_INS (cfg->cbb, ins);
8099 if (cfg->opt & MONO_OPT_CMOV) {
8100 if (strcmp (cmethod->name, "Min") == 0) {
8101 if (fsig->params [0]->type == MONO_TYPE_I4)
8103 if (fsig->params [0]->type == MONO_TYPE_U4)
8104 opcode = OP_IMIN_UN;
8105 else if (fsig->params [0]->type == MONO_TYPE_I8)
8107 else if (fsig->params [0]->type == MONO_TYPE_U8)
8108 opcode = OP_LMIN_UN;
8109 } else if (strcmp (cmethod->name, "Max") == 0) {
8110 if (fsig->params [0]->type == MONO_TYPE_I4)
8112 if (fsig->params [0]->type == MONO_TYPE_U4)
8113 opcode = OP_IMAX_UN;
8114 else if (fsig->params [0]->type == MONO_TYPE_I8)
8116 else if (fsig->params [0]->type == MONO_TYPE_U8)
8117 opcode = OP_LMAX_UN;
8121 if (opcode && fsig->param_count == 2) {
8122 MONO_INST_NEW (cfg, ins, opcode);
8123 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8124 ins->dreg = mono_alloc_ireg (cfg);
8125 ins->sreg1 = args [0]->dreg;
8126 ins->sreg2 = args [1]->dreg;
8127 MONO_ADD_INS (cfg->cbb, ins);
8131 /* OP_FREM is not IEEE compatible */
8132 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8133 MONO_INST_NEW (cfg, ins, OP_FREM);
8134 ins->inst_i0 = args [0];
8135 ins->inst_i1 = args [1];
8145 mono_arch_print_tree (MonoInst *tree, int arity)
8151 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8153 return ctx->gregs [reg];
8157 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8159 ctx->gregs [reg] = val;
8163 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8165 gpointer *sp, old_value;
8169 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8170 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8173 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8182 * mono_arch_emit_load_aotconst:
8184 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8185 * TARGET from the mscorlib GOT in full-aot code.
8186 * On AMD64, the result is placed into R11.
8189 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8191 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8192 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8198 * mono_arch_get_trampolines:
8200 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8204 mono_arch_get_trampolines (gboolean aot)
8206 return mono_amd64_get_exception_trampolines (aot);
8209 /* Soft Debug support */
8210 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8213 * mono_arch_set_breakpoint:
8215 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8216 * The location should contain code emitted by OP_SEQ_POINT.
8219 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8224 guint32 native_offset = ip - (guint8*)ji->code_start;
8225 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8227 g_assert (info->bp_addrs [native_offset] == 0);
8228 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8230 /* ip points to a mov r11, 0 */
8231 g_assert (code [0] == 0x41);
8232 g_assert (code [1] == 0xbb);
8233 amd64_mov_reg_imm (code, AMD64_R11, 1);
8238 * mono_arch_clear_breakpoint:
8240 * Clear the breakpoint at IP.
8243 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8248 guint32 native_offset = ip - (guint8*)ji->code_start;
8249 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8251 info->bp_addrs [native_offset] = NULL;
8253 amd64_mov_reg_imm (code, AMD64_R11, 0);
8258 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8260 /* We use soft breakpoints on amd64 */
8265 * mono_arch_skip_breakpoint:
8267 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8268 * we resume, the instruction is not executed again.
8271 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8273 g_assert_not_reached ();
8277 * mono_arch_start_single_stepping:
8279 * Start single stepping.
8282 mono_arch_start_single_stepping (void)
8284 ss_trampoline = mini_get_single_step_trampoline ();
8288 * mono_arch_stop_single_stepping:
8290 * Stop single stepping.
8293 mono_arch_stop_single_stepping (void)
8295 ss_trampoline = NULL;
8299 * mono_arch_is_single_step_event:
8301 * Return whenever the machine state in SIGCTX corresponds to a single
8305 mono_arch_is_single_step_event (void *info, void *sigctx)
8307 /* We use soft breakpoints on amd64 */
8312 * mono_arch_skip_single_step:
8314 * Modify CTX so the ip is placed after the single step trigger instruction,
8315 * we resume, the instruction is not executed again.
8318 mono_arch_skip_single_step (MonoContext *ctx)
8320 g_assert_not_reached ();
8324 * mono_arch_create_seq_point_info:
8326 * Return a pointer to a data structure which is used by the sequence
8327 * point implementation in AOTed code.
8330 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8335 // FIXME: Add a free function
8337 mono_domain_lock (domain);
8338 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8340 mono_domain_unlock (domain);
8343 ji = mono_jit_info_table_find (domain, (char*)code);
8346 // FIXME: Optimize the size
8347 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8349 info->ss_tramp_addr = &ss_trampoline;
8351 mono_domain_lock (domain);
8352 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8354 mono_domain_unlock (domain);
8361 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8363 ext->lmf.previous_lmf = prev_lmf;
8364 /* Mark that this is a MonoLMFExt */
8365 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8366 ext->lmf.rsp = (gssize)ext;
8372 mono_arch_opcode_supported (int opcode)
8375 case OP_ATOMIC_ADD_I4:
8376 case OP_ATOMIC_ADD_I8:
8377 case OP_ATOMIC_EXCHANGE_I4:
8378 case OP_ATOMIC_EXCHANGE_I8:
8379 case OP_ATOMIC_CAS_I4:
8380 case OP_ATOMIC_CAS_I8:
8381 case OP_ATOMIC_LOAD_I1:
8382 case OP_ATOMIC_LOAD_I2:
8383 case OP_ATOMIC_LOAD_I4:
8384 case OP_ATOMIC_LOAD_I8:
8385 case OP_ATOMIC_LOAD_U1:
8386 case OP_ATOMIC_LOAD_U2:
8387 case OP_ATOMIC_LOAD_U4:
8388 case OP_ATOMIC_LOAD_U8:
8389 case OP_ATOMIC_LOAD_R4:
8390 case OP_ATOMIC_LOAD_R8:
8391 case OP_ATOMIC_STORE_I1:
8392 case OP_ATOMIC_STORE_I2:
8393 case OP_ATOMIC_STORE_I4:
8394 case OP_ATOMIC_STORE_I8:
8395 case OP_ATOMIC_STORE_U1:
8396 case OP_ATOMIC_STORE_U2:
8397 case OP_ATOMIC_STORE_U4:
8398 case OP_ATOMIC_STORE_U8:
8399 case OP_ATOMIC_STORE_R4:
8400 case OP_ATOMIC_STORE_R8:
8408 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8410 return get_call_info (mp, sig);