mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internals.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /* The single step trampoline */
  69 static gpointer ss_trampoline;
  70
  71 /* The breakpoint trampoline */
  72 static gpointer bp_trampoline;
  73
  74 /* Offset between fp and the first argument in the callee */
  75 #define ARGS_OFFSET 16
  76 #define GP_SCRATCH_REG AMD64_R11
  77
  78 /*
  79  * AMD64 register usage:
  80  * - callee saved registers are used for global register allocation
  81  * - %r11 is used for materializing 64 bit constants in opcodes
  82  * - the rest is used for local allocation
  83  */
  84
  85 /*
  86  * Floating point comparison results:
  87  *                  ZF PF CF
  88  * A > B            0  0  0
  89  * A < B            0  0  1
  90  * A = B            1  0  0
  91  * A > B            0  0  0
  92  * UNORDERED        1  1  1
  93  */
  94
  95 const char*
  96 mono_arch_regname (int reg)
  97 {
  98         switch (reg) {
  99         case AMD64_RAX: return "%rax";
 100         case AMD64_RBX: return "%rbx";
 101         case AMD64_RCX: return "%rcx";
 102         case AMD64_RDX: return "%rdx";
 103         case AMD64_RSP: return "%rsp";
 104         case AMD64_RBP: return "%rbp";
 105         case AMD64_RDI: return "%rdi";
 106         case AMD64_RSI: return "%rsi";
 107         case AMD64_R8: return "%r8";
 108         case AMD64_R9: return "%r9";
 109         case AMD64_R10: return "%r10";
 110         case AMD64_R11: return "%r11";
 111         case AMD64_R12: return "%r12";
 112         case AMD64_R13: return "%r13";
 113         case AMD64_R14: return "%r14";
 114         case AMD64_R15: return "%r15";
 115         }
 116         return "unknown";
 117 }
 118
 119 static const char * packed_xmmregs [] = {
 120         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 121         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 122 };
 123
 124 static const char * single_xmmregs [] = {
 125         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 126         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 127 };
 128
 129 const char*
 130 mono_arch_fregname (int reg)
 131 {
 132         if (reg < AMD64_XMM_NREG)
 133                 return single_xmmregs [reg];
 134         else
 135                 return "unknown";
 136 }
 137
 138 const char *
 139 mono_arch_xregname (int reg)
 140 {
 141         if (reg < AMD64_XMM_NREG)
 142                 return packed_xmmregs [reg];
 143         else
 144                 return "unknown";
 145 }
 146
 147 static gboolean
 148 debug_omit_fp (void)
 149 {
 150 #if 0
 151         return mono_debug_count ();
 152 #else
 153         return TRUE;
 154 #endif
 155 }
 156
 157 static inline gboolean
 158 amd64_is_near_call (guint8 *code)
 159 {
 160         /* Skip REX */
 161         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 162                 code += 1;
 163
 164         return code [0] == 0xe8;
 165 }
 166
 167 static inline gboolean
 168 amd64_use_imm32 (gint64 val)
 169 {
 170         if (mini_get_debug_options()->single_imm_size)
 171                 return FALSE;
 172
 173         return amd64_is_imm32 (val);
 174 }
 175
 176 #ifdef __native_client_codegen__
 177
 178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 179 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 181 /* We only want to force bundle alignment for the top level instruction,    */
 182 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 183 static MonoNativeTlsKey nacl_instruction_depth;
 184
 185 static MonoNativeTlsKey nacl_rex_tag;
 186 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 187
 188 void
 189 amd64_nacl_clear_legacy_prefix_tag ()
 190 {
 191         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 192 }
 193
 194 void
 195 amd64_nacl_tag_legacy_prefix (guint8* code)
 196 {
 197         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 198                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 199 }
 200
 201 void
 202 amd64_nacl_tag_rex (guint8* code)
 203 {
 204         mono_native_tls_set_value (nacl_rex_tag, code);
 205 }
 206
 207 guint8*
 208 amd64_nacl_get_legacy_prefix_tag ()
 209 {
 210         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 211 }
 212
 213 guint8*
 214 amd64_nacl_get_rex_tag ()
 215 {
 216         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 217 }
 218
 219 /* Increment the instruction "depth" described above */
 220 void
 221 amd64_nacl_instruction_pre ()
 222 {
 223         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 224         depth++;
 225         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 226 }
 227
 228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 229 /* alignment if depth == 0 (top level instruction)                          */
 230 /* IN: start, end    pointers to instruction beginning and end              */
 231 /* OUT: start, end   pointers to beginning and end after possible alignment */
 232 /* GLOBALS: nacl_instruction_depth     defined above                        */
 233 void
 234 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 235 {
 236         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 237         depth--;
 238         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 239
 240         g_assert ( depth >= 0 );
 241         if (depth == 0) {
 242                 uintptr_t space_in_block;
 243                 uintptr_t instlen;
 244                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 245                 /* if legacy prefix is present, and if it was emitted before */
 246                 /* the start of the instruction sequence, adjust the start   */
 247                 if (prefix != NULL && prefix < *start) {
 248                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 249                         *start = prefix;
 250                 }
 251                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 252                 instlen = (uintptr_t)(*end - *start);
 253                 /* Only check for instructions which are less than        */
 254                 /* kNaClAlignment. The only instructions that should ever */
 255                 /* be that long are call sequences, which are already     */
 256                 /* padded out to align the return to the next bundle.     */
 257                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 258                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 259                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 260                         const size_t length = (size_t)((*end)-(*start));
 261                         g_assert (length < MAX_NACL_INST_LENGTH);
 262
 263                         memcpy (copy_of_instruction, *start, length);
 264                         *start = mono_arch_nacl_pad (*start, space_in_block);
 265                         memcpy (*start, copy_of_instruction, length);
 266                         *end = *start + length;
 267                 }
 268                 amd64_nacl_clear_legacy_prefix_tag ();
 269                 amd64_nacl_tag_rex (NULL);
 270         }
 271 }
 272
 273 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 274 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 275 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 276 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 277 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 278 /* IN:      code                                                            */
 279 /*             pointer to current instruction stream (in the                */
 280 /*             middle of an instruction, after opcode is emitted)           */
 281 /*          basereg/offset/dreg                                             */
 282 /*             operands of normal membase address                           */
 283 /* OUT:     code                                                            */
 284 /*             pointer to the end of the membase/memindex emit              */
 285 /* GLOBALS: nacl_rex_tag                                                    */
 286 /*             position in instruction stream that rex prefix was emitted   */
 287 /*          nacl_legacy_prefix_tag                                          */
 288 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 289 void
 290 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 291 {
 292         gint8 true_basereg = basereg;
 293
 294         /* Cache these values, they might change  */
 295         /* as new instructions are emitted below. */
 296         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 297         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 298
 299         /* 'basereg' is given masked to 0x7 at this point, so check */
 300         /* the rex prefix to see if this is an extended register.   */
 301         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 302                 true_basereg |= 0x8;
 303         }
 304
 305 #define X86_LEA_OPCODE (0x8D)
 306
 307         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 308                 guint8* old_instruction_start;
 309
 310                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 311                 /* 32-bits of the old base register (new index register)     */
 312                 guint8 buf[32];
 313                 guint8* buf_ptr = buf;
 314                 size_t insert_len;
 315
 316                 g_assert (rex_tag != NULL);
 317
 318                 if (IS_REX(*rex_tag)) {
 319                         /* The old rex.B should be the new rex.X */
 320                         if (*rex_tag & AMD64_REX_B) {
 321                                 *rex_tag |= AMD64_REX_X;
 322                         }
 323                         /* Since our new base is %r15 set rex.B */
 324                         *rex_tag |= AMD64_REX_B;
 325                 } else {
 326                         /* Shift the instruction by one byte  */
 327                         /* so we can insert a rex prefix      */
 328                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 329                         *code += 1;
 330                         /* New rex prefix only needs rex.B for %r15 base */
 331                         *rex_tag = AMD64_REX(AMD64_REX_B);
 332                 }
 333
 334                 if (legacy_prefix_tag) {
 335                         old_instruction_start = legacy_prefix_tag;
 336                 } else {
 337                         old_instruction_start = rex_tag;
 338                 }
 339
 340                 /* Clears the upper 32-bits of the previous base register */
 341                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 342                 insert_len = buf_ptr - buf;
 343
 344                 /* Move the old instruction forward to make */
 345                 /* room for 'mov' stored in 'buf_ptr'       */
 346                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 347                 *code += insert_len;
 348                 memcpy (old_instruction_start, buf, insert_len);
 349
 350                 /* Sandboxed replacement for the normal membase_emit */
 351                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 352
 353         } else {
 354                 /* Normal default behavior, emit membase memory location */
 355                 x86_membase_emit_body (*code, dreg, basereg, offset);
 356         }
 357 }
 358
 359
 360 static inline unsigned char*
 361 amd64_skip_nops (unsigned char* code)
 362 {
 363         guint8 in_nop;
 364         do {
 365                 in_nop = 0;
 366                 if (   code[0] == 0x90) {
 367                         in_nop = 1;
 368                         code += 1;
 369                 }
 370                 if (   code[0] == 0x66 && code[1] == 0x90) {
 371                         in_nop = 1;
 372                         code += 2;
 373                 }
 374                 if (code[0] == 0x0f && code[1] == 0x1f
 375                  && code[2] == 0x00) {
 376                         in_nop = 1;
 377                         code += 3;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x40 && code[3] == 0x00) {
 381                         in_nop = 1;
 382                         code += 4;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x44 && code[3] == 0x00
 386                  && code[4] == 0x00) {
 387                         in_nop = 1;
 388                         code += 5;
 389                 }
 390                 if (code[0] == 0x66 && code[1] == 0x0f
 391                  && code[2] == 0x1f && code[3] == 0x44
 392                  && code[4] == 0x00 && code[5] == 0x00) {
 393                         in_nop = 1;
 394                         code += 6;
 395                 }
 396                 if (code[0] == 0x0f && code[1] == 0x1f
 397                  && code[2] == 0x80 && code[3] == 0x00
 398                  && code[4] == 0x00 && code[5] == 0x00
 399                  && code[6] == 0x00) {
 400                         in_nop = 1;
 401                         code += 7;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x84 && code[3] == 0x00
 405                  && code[4] == 0x00 && code[5] == 0x00
 406                  && code[6] == 0x00 && code[7] == 0x00) {
 407                         in_nop = 1;
 408                         code += 8;
 409                 }
 410         } while ( in_nop );
 411         return code;
 412 }
 413
 414 guint8*
 415 mono_arch_nacl_skip_nops (guint8* code)
 416 {
 417   return amd64_skip_nops(code);
 418 }
 419
 420 #endif /*__native_client_codegen__*/
 421
 422 static void
 423 amd64_patch (unsigned char* code, gpointer target)
 424 {
 425         guint8 rex = 0;
 426
 427 #ifdef __native_client_codegen__
 428         code = amd64_skip_nops (code);
 429 #endif
 430 #if defined(__native_client_codegen__) && defined(__native_client__)
 431         if (nacl_is_code_address (code)) {
 432                 /* For tail calls, code is patched after being installed */
 433                 /* but not through the normal "patch callsite" method.   */
 434                 unsigned char buf[kNaClAlignment];
 435                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 436                 int ret;
 437                 memcpy (buf, aligned_code, kNaClAlignment);
 438                 /* Patch a temp buffer of bundle size, */
 439                 /* then install to actual location.    */
 440                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 441                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 442                 g_assert (ret == 0);
 443                 return;
 444         }
 445         target = nacl_modify_patch_target (target);
 446 #endif
 447
 448         /* Skip REX */
 449         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 450                 rex = code [0];
 451                 code += 1;
 452         }
 453
 454         if ((code [0] & 0xf8) == 0xb8) {
 455                 /* amd64_set_reg_template */
 456                 *(guint64*)(code + 1) = (guint64)target;
 457         }
 458         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 459                 /* mov 0(%rip), %dreg */
 460                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 461         }
 462         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 463                 /* call *<OFFSET>(%rip) */
 464                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 465         }
 466         else if (code [0] == 0xe8) {
 467                 /* call <DISP> */
 468                 gint64 disp = (guint8*)target - (guint8*)code;
 469                 g_assert (amd64_is_imm32 (disp));
 470                 x86_patch (code, (unsigned char*)target);
 471         }
 472         else
 473                 x86_patch (code, (unsigned char*)target);
 474 }
 475
 476 void
 477 mono_amd64_patch (unsigned char* code, gpointer target)
 478 {
 479         amd64_patch (code, target);
 480 }
 481
 482 typedef enum {
 483         ArgInIReg,
 484         ArgInFloatSSEReg,
 485         ArgInDoubleSSEReg,
 486         ArgOnStack,
 487         ArgValuetypeInReg,
 488         ArgValuetypeAddrInIReg,
 489         /* gsharedvt argument passed by addr */
 490         ArgGSharedVtInReg,
 491         ArgGSharedVtOnStack,
 492         ArgNone /* only in pair_storage */
 493 } ArgStorage;
 494
 495 typedef struct {
 496         gint16 offset;
 497         gint8  reg;
 498         ArgStorage storage;
 499
 500         /* Only if storage == ArgValuetypeInReg */
 501         ArgStorage pair_storage [2];
 502         gint8 pair_regs [2];
 503         /* The size of each pair */
 504         int pair_size [2];
 505         int nregs;
 506 } ArgInfo;
 507
 508 typedef struct {
 509         int nargs;
 510         guint32 stack_usage;
 511         guint32 reg_usage;
 512         guint32 freg_usage;
 513         gboolean need_stack_align;
 514         /* The index of the vret arg in the argument list */
 515         int vret_arg_index;
 516         ArgInfo ret;
 517         ArgInfo sig_cookie;
 518         ArgInfo args [1];
 519 } CallInfo;
 520
 521 #define DEBUG(a) if (cfg->verbose_level > 1) a
 522
 523 #ifdef TARGET_WIN32
 524 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 525
 526 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 527 #else
 528 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 529
 530  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 531 #endif
 532
 533 static void inline
 534 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 535 {
 536     ainfo->offset = *stack_size;
 537
 538     if (*gr >= PARAM_REGS) {
 539                 ainfo->storage = ArgOnStack;
 540                 /* Since the same stack slot size is used for all arg */
 541                 /*  types, it needs to be big enough to hold them all */
 542                 (*stack_size) += sizeof(mgreg_t);
 543     }
 544     else {
 545                 ainfo->storage = ArgInIReg;
 546                 ainfo->reg = param_regs [*gr];
 547                 (*gr) ++;
 548     }
 549 }
 550
 551 #ifdef TARGET_WIN32
 552 #define FLOAT_PARAM_REGS 4
 553 #else
 554 #define FLOAT_PARAM_REGS 8
 555 #endif
 556
 557 static void inline
 558 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 559 {
 560     ainfo->offset = *stack_size;
 561
 562     if (*gr >= FLOAT_PARAM_REGS) {
 563                 ainfo->storage = ArgOnStack;
 564                 /* Since the same stack slot size is used for both float */
 565                 /*  types, it needs to be big enough to hold them both */
 566                 (*stack_size) += sizeof(mgreg_t);
 567     }
 568     else {
 569                 /* A double register */
 570                 if (is_double)
 571                         ainfo->storage = ArgInDoubleSSEReg;
 572                 else
 573                         ainfo->storage = ArgInFloatSSEReg;
 574                 ainfo->reg = *gr;
 575                 (*gr) += 1;
 576     }
 577 }
 578
 579 typedef enum ArgumentClass {
 580         ARG_CLASS_NO_CLASS,
 581         ARG_CLASS_MEMORY,
 582         ARG_CLASS_INTEGER,
 583         ARG_CLASS_SSE
 584 } ArgumentClass;
 585
 586 static ArgumentClass
 587 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 588 {
 589         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 590         MonoType *ptype;
 591
 592         ptype = mini_get_underlying_type (type);
 593         switch (ptype->type) {
 594         case MONO_TYPE_I1:
 595         case MONO_TYPE_U1:
 596         case MONO_TYPE_I2:
 597         case MONO_TYPE_U2:
 598         case MONO_TYPE_I4:
 599         case MONO_TYPE_U4:
 600         case MONO_TYPE_I:
 601         case MONO_TYPE_U:
 602         case MONO_TYPE_STRING:
 603         case MONO_TYPE_OBJECT:
 604         case MONO_TYPE_CLASS:
 605         case MONO_TYPE_SZARRAY:
 606         case MONO_TYPE_PTR:
 607         case MONO_TYPE_FNPTR:
 608         case MONO_TYPE_ARRAY:
 609         case MONO_TYPE_I8:
 610         case MONO_TYPE_U8:
 611                 class2 = ARG_CLASS_INTEGER;
 612                 break;
 613         case MONO_TYPE_R4:
 614         case MONO_TYPE_R8:
 615 #ifdef TARGET_WIN32
 616                 class2 = ARG_CLASS_INTEGER;
 617 #else
 618                 class2 = ARG_CLASS_SSE;
 619 #endif
 620                 break;
 621
 622         case MONO_TYPE_TYPEDBYREF:
 623                 g_assert_not_reached ();
 624
 625         case MONO_TYPE_GENERICINST:
 626                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 627                         class2 = ARG_CLASS_INTEGER;
 628                         break;
 629                 }
 630                 /* fall through */
 631         case MONO_TYPE_VALUETYPE: {
 632                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 633                 int i;
 634
 635                 for (i = 0; i < info->num_fields; ++i) {
 636                         class2 = class1;
 637                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 638                 }
 639                 break;
 640         }
 641         default:
 642                 g_assert_not_reached ();
 643         }
 644
 645         /* Merge */
 646         if (class1 == class2)
 647                 ;
 648         else if (class1 == ARG_CLASS_NO_CLASS)
 649                 class1 = class2;
 650         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 651                 class1 = ARG_CLASS_MEMORY;
 652         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 653                 class1 = ARG_CLASS_INTEGER;
 654         else
 655                 class1 = ARG_CLASS_SSE;
 656
 657         return class1;
 658 }
 659 #ifdef __native_client_codegen__
 660
 661 /* Default alignment for Native Client is 32-byte. */
 662 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 663
 664 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 665 /* Check that alignment doesn't cross an alignment boundary.             */
 666 guint8*
 667 mono_arch_nacl_pad(guint8 *code, int pad)
 668 {
 669         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 670
 671         if (pad == 0) return code;
 672         /* assertion: alignment cannot cross a block boundary */
 673         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 674                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 675         while (pad >= kMaxPadding) {
 676                 amd64_padding (code, kMaxPadding);
 677                 pad -= kMaxPadding;
 678         }
 679         if (pad != 0) amd64_padding (code, pad);
 680         return code;
 681 }
 682 #endif
 683
 684 static int
 685 count_fields_nested (MonoClass *klass)
 686 {
 687         MonoMarshalType *info;
 688         int i, count;
 689
 690         info = mono_marshal_load_type_info (klass);
 691         g_assert(info);
 692         count = 0;
 693         for (i = 0; i < info->num_fields; ++i) {
 694                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 695                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 696                 else
 697                         count ++;
 698         }
 699         return count;
 700 }
 701
 702 static int
 703 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 704 {
 705         MonoMarshalType *info;
 706         int i;
 707
 708         info = mono_marshal_load_type_info (klass);
 709         g_assert(info);
 710         for (i = 0; i < info->num_fields; ++i) {
 711                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 712                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 713                 } else {
 714                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 715                         fields [index].offset += offset;
 716                         index ++;
 717                 }
 718         }
 719         return index;
 720 }
 721
 722 #ifdef TARGET_WIN32
 723 static void
 724 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 725                                          gboolean is_return,
 726                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 727 {
 728         guint32 size, i, nfields;
 729         guint32 argsize = 8;
 730         ArgumentClass arg_class;
 731         MonoMarshalType *info = NULL;
 732         MonoMarshalField *fields = NULL;
 733         MonoClass *klass;
 734         gboolean pass_on_stack = FALSE;
 735
 736         klass = mono_class_from_mono_type (type);
 737         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 738         if (!sig->pinvoke)
 739                 pass_on_stack = TRUE;
 740
 741         /* If this struct can't be split up naturally into 8-byte */
 742         /* chunks (registers), pass it on the stack.              */
 743         if (sig->pinvoke && !pass_on_stack) {
 744                 guint32 align;
 745                 guint32 field_size;
 746
 747                 info = mono_marshal_load_type_info (klass);
 748                 g_assert (info);
 749
 750                 /*
 751                  * Collect field information recursively to be able to
 752                  * handle nested structures.
 753                  */
 754                 nfields = count_fields_nested (klass);
 755                 fields = g_new0 (MonoMarshalField, nfields);
 756                 collect_field_info_nested (klass, fields, 0, 0);
 757
 758                 for (i = 0; i < nfields; ++i) {
 759                         field_size = mono_marshal_type_size (fields [i].field->type,
 760                                                            fields [i].mspec,
 761                                                            &align, TRUE, klass->unicode);
 762                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 763                                 pass_on_stack = TRUE;
 764                                 break;
 765                         }
 766                 }
 767         }
 768
 769         if (pass_on_stack) {
 770                 /* Allways pass in memory */
 771                 ainfo->offset = *stack_size;
 772                 *stack_size += ALIGN_TO (size, 8);
 773                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 774
 775                 g_free (fields);
 776                 return;
 777         }
 778
 779         if (!sig->pinvoke) {
 780                 int n = mono_class_value_size (klass, NULL);
 781
 782                 argsize = n;
 783
 784                 if (n > 8)
 785                         arg_class = ARG_CLASS_MEMORY;
 786                 else
 787                         /* Always pass in 1 integer register */
 788                         arg_class = ARG_CLASS_INTEGER;
 789         } else {
 790                 g_assert (info);
 791
 792                 if (!fields) {
 793                         ainfo->storage = ArgValuetypeInReg;
 794                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 795                         return;
 796                 }
 797
 798                 switch (info->native_size) {
 799                 case 1: case 2: case 4: case 8:
 800                         break;
 801                 default:
 802                         if (is_return) {
 803                                 ainfo->storage = ArgValuetypeAddrInIReg;
 804                                 ainfo->offset = *stack_size;
 805                                 *stack_size += ALIGN_TO (info->native_size, 8);
 806                         }
 807                         else {
 808                                 ainfo->storage = ArgValuetypeAddrInIReg;
 809
 810                                 if (*gr < PARAM_REGS) {
 811                                         ainfo->pair_storage [0] = ArgInIReg;
 812                                         ainfo->pair_regs [0] = param_regs [*gr];
 813                                         (*gr) ++;
 814                                 }
 815                                 else {
 816                                         ainfo->pair_storage [0] = ArgOnStack;
 817                                         ainfo->offset = *stack_size;
 818                                         *stack_size += 8;
 819                                 }
 820                         }
 821
 822                         g_free (fields);
 823                         return;
 824                 }
 825
 826                 int size;
 827                 guint32 align;
 828                 ArgumentClass class1;
 829
 830                 if (nfields == 0)
 831                         class1 = ARG_CLASS_MEMORY;
 832                 else
 833                         class1 = ARG_CLASS_NO_CLASS;
 834                 for (i = 0; i < nfields; ++i) {
 835                         size = mono_marshal_type_size (fields [i].field->type,
 836                                                                                    fields [i].mspec,
 837                                                                                    &align, TRUE, klass->unicode);
 838                         /* How far into this quad this data extends.*/
 839                         /* (8 is size of quad) */
 840                         argsize = fields [i].offset + size;
 841
 842                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 843                 }
 844                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 845                 arg_class = class1;
 846         }
 847
 848         g_free (fields);
 849
 850         /* Allocate registers */
 851         {
 852                 int orig_gr = *gr;
 853                 int orig_fr = *fr;
 854
 855                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 856                         argsize ++;
 857
 858                 ainfo->storage = ArgValuetypeInReg;
 859                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 860                 ainfo->pair_size [0] = argsize;
 861                 ainfo->pair_size [1] = 0;
 862                 ainfo->nregs = 1;
 863                 switch (arg_class) {
 864                 case ARG_CLASS_INTEGER:
 865                         if (*gr >= PARAM_REGS)
 866                                 arg_class = ARG_CLASS_MEMORY;
 867                         else {
 868                                 ainfo->pair_storage [0] = ArgInIReg;
 869                                 if (is_return)
 870                                         ainfo->pair_regs [0] = return_regs [*gr];
 871                                 else
 872                                         ainfo->pair_regs [0] = param_regs [*gr];
 873                                 (*gr) ++;
 874                         }
 875                         break;
 876                 case ARG_CLASS_SSE:
 877                         if (*fr >= FLOAT_PARAM_REGS)
 878                                 arg_class = ARG_CLASS_MEMORY;
 879                         else {
 880                                 if (argsize <= 4)
 881                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 882                                 else
 883                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 884                                 ainfo->pair_regs [0] = *fr;
 885                                 (*fr) ++;
 886                         }
 887                         break;
 888                 case ARG_CLASS_MEMORY:
 889                         break;
 890                 default:
 891                         g_assert_not_reached ();
 892                 }
 893
 894                 if (arg_class == ARG_CLASS_MEMORY) {
 895                         /* Revert possible register assignments */
 896                         *gr = orig_gr;
 897                         *fr = orig_fr;
 898
 899                         ainfo->offset = *stack_size;
 900                         *stack_size += sizeof (mgreg_t);
 901                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 902                 }
 903         }
 904 }
 905 #endif /* TARGET_WIN32 */
 906
 907 static void
 908 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 909                            gboolean is_return,
 910                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 911 {
 912 #ifdef TARGET_WIN32
 913         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 914 #else
 915         guint32 size, quad, nquads, i, nfields;
 916         /* Keep track of the size used in each quad so we can */
 917         /* use the right size when copying args/return vars.  */
 918         guint32 quadsize [2] = {8, 8};
 919         ArgumentClass args [2];
 920         MonoMarshalType *info = NULL;
 921         MonoMarshalField *fields = NULL;
 922         MonoClass *klass;
 923         gboolean pass_on_stack = FALSE;
 924
 925         klass = mono_class_from_mono_type (type);
 926         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 927         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 928                 /* We pass and return vtypes of size 8 in a register */
 929         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 930                 pass_on_stack = TRUE;
 931         }
 932
 933         /* If this struct can't be split up naturally into 8-byte */
 934         /* chunks (registers), pass it on the stack.              */
 935         if (sig->pinvoke && !pass_on_stack) {
 936                 guint32 align;
 937                 guint32 field_size;
 938
 939                 info = mono_marshal_load_type_info (klass);
 940                 g_assert (info);
 941
 942                 /*
 943                  * Collect field information recursively to be able to
 944                  * handle nested structures.
 945                  */
 946                 nfields = count_fields_nested (klass);
 947                 fields = g_new0 (MonoMarshalField, nfields);
 948                 collect_field_info_nested (klass, fields, 0, 0);
 949
 950                 for (i = 0; i < nfields; ++i) {
 951                         field_size = mono_marshal_type_size (fields [i].field->type,
 952                                                            fields [i].mspec,
 953                                                            &align, TRUE, klass->unicode);
 954                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 955                                 pass_on_stack = TRUE;
 956                                 break;
 957                         }
 958                 }
 959         }
 960
 961         if (size == 0) {
 962                 ainfo->storage = ArgValuetypeInReg;
 963                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 964                 return;
 965         }
 966
 967         if (pass_on_stack) {
 968                 /* Allways pass in memory */
 969                 ainfo->offset = *stack_size;
 970                 *stack_size += ALIGN_TO (size, 8);
 971                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 972
 973                 g_free (fields);
 974                 return;
 975         }
 976
 977         if (size > 8)
 978                 nquads = 2;
 979         else
 980                 nquads = 1;
 981
 982         if (!sig->pinvoke) {
 983                 int n = mono_class_value_size (klass, NULL);
 984
 985                 quadsize [0] = n >= 8 ? 8 : n;
 986                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 987
 988                 /* Always pass in 1 or 2 integer registers */
 989                 args [0] = ARG_CLASS_INTEGER;
 990                 args [1] = ARG_CLASS_INTEGER;
 991                 /* Only the simplest cases are supported */
 992                 if (is_return && nquads != 1) {
 993                         args [0] = ARG_CLASS_MEMORY;
 994                         args [1] = ARG_CLASS_MEMORY;
 995                 }
 996         } else {
 997                 /*
 998                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 999                  * The X87 and SSEUP stuff is left out since there are no such types in
1000                  * the CLR.
1001                  */
1002                 g_assert (info);
1003
1004                 if (!fields) {
1005                         ainfo->storage = ArgValuetypeInReg;
1006                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1007                         return;
1008                 }
1009
1010                 if (info->native_size > 16) {
1011                         ainfo->offset = *stack_size;
1012                         *stack_size += ALIGN_TO (info->native_size, 8);
1013                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1014
1015                         g_free (fields);
1016                         return;
1017                 }
1018
1019                 args [0] = ARG_CLASS_NO_CLASS;
1020                 args [1] = ARG_CLASS_NO_CLASS;
1021                 for (quad = 0; quad < nquads; ++quad) {
1022                         int size;
1023                         guint32 align;
1024                         ArgumentClass class1;
1025
1026                         if (nfields == 0)
1027                                 class1 = ARG_CLASS_MEMORY;
1028                         else
1029                                 class1 = ARG_CLASS_NO_CLASS;
1030                         for (i = 0; i < nfields; ++i) {
1031                                 size = mono_marshal_type_size (fields [i].field->type,
1032                                                                                            fields [i].mspec,
1033                                                                                            &align, TRUE, klass->unicode);
1034                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
1035                                         /* Unaligned field */
1036                                         NOT_IMPLEMENTED;
1037                                 }
1038
1039                                 /* Skip fields in other quad */
1040                                 if ((quad == 0) && (fields [i].offset >= 8))
1041                                         continue;
1042                                 if ((quad == 1) && (fields [i].offset < 8))
1043                                         continue;
1044
1045                                 /* How far into this quad this data extends.*/
1046                                 /* (8 is size of quad) */
1047                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
1048
1049                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1050                         }
1051                         g_assert (class1 != ARG_CLASS_NO_CLASS);
1052                         args [quad] = class1;
1053                 }
1054         }
1055
1056         g_free (fields);
1057
1058         /* Post merger cleanup */
1059         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1060                 args [0] = args [1] = ARG_CLASS_MEMORY;
1061
1062         /* Allocate registers */
1063         {
1064                 int orig_gr = *gr;
1065                 int orig_fr = *fr;
1066
1067                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1068                         quadsize [0] ++;
1069                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1070                         quadsize [1] ++;
1071
1072                 ainfo->storage = ArgValuetypeInReg;
1073                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1074                 g_assert (quadsize [0] <= 8);
1075                 g_assert (quadsize [1] <= 8);
1076                 ainfo->pair_size [0] = quadsize [0];
1077                 ainfo->pair_size [1] = quadsize [1];
1078                 ainfo->nregs = nquads;
1079                 for (quad = 0; quad < nquads; ++quad) {
1080                         switch (args [quad]) {
1081                         case ARG_CLASS_INTEGER:
1082                                 if (*gr >= PARAM_REGS)
1083                                         args [quad] = ARG_CLASS_MEMORY;
1084                                 else {
1085                                         ainfo->pair_storage [quad] = ArgInIReg;
1086                                         if (is_return)
1087                                                 ainfo->pair_regs [quad] = return_regs [*gr];
1088                                         else
1089                                                 ainfo->pair_regs [quad] = param_regs [*gr];
1090                                         (*gr) ++;
1091                                 }
1092                                 break;
1093                         case ARG_CLASS_SSE:
1094                                 if (*fr >= FLOAT_PARAM_REGS)
1095                                         args [quad] = ARG_CLASS_MEMORY;
1096                                 else {
1097                                         if (quadsize[quad] <= 4)
1098                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1099                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1100                                         ainfo->pair_regs [quad] = *fr;
1101                                         (*fr) ++;
1102                                 }
1103                                 break;
1104                         case ARG_CLASS_MEMORY:
1105                                 break;
1106                         default:
1107                                 g_assert_not_reached ();
1108                         }
1109                 }
1110
1111                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1112                         /* Revert possible register assignments */
1113                         *gr = orig_gr;
1114                         *fr = orig_fr;
1115
1116                         ainfo->offset = *stack_size;
1117                         if (sig->pinvoke)
1118                                 *stack_size += ALIGN_TO (info->native_size, 8);
1119                         else
1120                                 *stack_size += nquads * sizeof(mgreg_t);
1121                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1122                 }
1123         }
1124 #endif /* !TARGET_WIN32 */
1125 }
1126
1127 /*
1128  * get_call_info:
1129  *
1130  *  Obtain information about a call according to the calling convention.
1131  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1132  * Draft Version 0.23" document for more information.
1133  */
1134 static CallInfo*
1135 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1136 {
1137         guint32 i, gr, fr, pstart;
1138         MonoType *ret_type;
1139         int n = sig->hasthis + sig->param_count;
1140         guint32 stack_size = 0;
1141         CallInfo *cinfo;
1142         gboolean is_pinvoke = sig->pinvoke;
1143
1144         if (mp)
1145                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1146         else
1147                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1148
1149         cinfo->nargs = n;
1150
1151         gr = 0;
1152         fr = 0;
1153
1154 #ifdef TARGET_WIN32
1155         /* Reserve space where the callee can save the argument registers */
1156         stack_size = 4 * sizeof (mgreg_t);
1157 #endif
1158
1159         /* return value */
1160         ret_type = mini_get_underlying_type (sig->ret);
1161         switch (ret_type->type) {
1162         case MONO_TYPE_I1:
1163         case MONO_TYPE_U1:
1164         case MONO_TYPE_I2:
1165         case MONO_TYPE_U2:
1166         case MONO_TYPE_I4:
1167         case MONO_TYPE_U4:
1168         case MONO_TYPE_I:
1169         case MONO_TYPE_U:
1170         case MONO_TYPE_PTR:
1171         case MONO_TYPE_FNPTR:
1172         case MONO_TYPE_CLASS:
1173         case MONO_TYPE_OBJECT:
1174         case MONO_TYPE_SZARRAY:
1175         case MONO_TYPE_ARRAY:
1176         case MONO_TYPE_STRING:
1177                 cinfo->ret.storage = ArgInIReg;
1178                 cinfo->ret.reg = AMD64_RAX;
1179                 break;
1180         case MONO_TYPE_U8:
1181         case MONO_TYPE_I8:
1182                 cinfo->ret.storage = ArgInIReg;
1183                 cinfo->ret.reg = AMD64_RAX;
1184                 break;
1185         case MONO_TYPE_R4:
1186                 cinfo->ret.storage = ArgInFloatSSEReg;
1187                 cinfo->ret.reg = AMD64_XMM0;
1188                 break;
1189         case MONO_TYPE_R8:
1190                 cinfo->ret.storage = ArgInDoubleSSEReg;
1191                 cinfo->ret.reg = AMD64_XMM0;
1192                 break;
1193         case MONO_TYPE_GENERICINST:
1194                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1195                         cinfo->ret.storage = ArgInIReg;
1196                         cinfo->ret.reg = AMD64_RAX;
1197                         break;
1198                 }
1199                 if (mini_is_gsharedvt_type (ret_type)) {
1200                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1201                         break;
1202                 }
1203                 /* fall through */
1204         case MONO_TYPE_VALUETYPE:
1205         case MONO_TYPE_TYPEDBYREF: {
1206                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1207
1208                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1209                 g_assert (cinfo->ret.storage != ArgInIReg);
1210                 break;
1211         }
1212         case MONO_TYPE_VAR:
1213         case MONO_TYPE_MVAR:
1214                 g_assert (mini_is_gsharedvt_type (ret_type));
1215                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1216                 break;
1217         case MONO_TYPE_VOID:
1218                 break;
1219         default:
1220                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1221         }
1222
1223         pstart = 0;
1224         /*
1225          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1226          * the first argument, allowing 'this' to be always passed in the first arg reg.
1227          * Also do this if the first argument is a reference type, since virtual calls
1228          * are sometimes made using calli without sig->hasthis set, like in the delegate
1229          * invoke wrappers.
1230          */
1231         if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1232                 if (sig->hasthis) {
1233                         add_general (&gr, &stack_size, cinfo->args + 0);
1234                 } else {
1235                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1236                         pstart = 1;
1237                 }
1238                 add_general (&gr, &stack_size, &cinfo->ret);
1239                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1240                 cinfo->vret_arg_index = 1;
1241         } else {
1242                 /* this */
1243                 if (sig->hasthis)
1244                         add_general (&gr, &stack_size, cinfo->args + 0);
1245
1246                 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1247                         add_general (&gr, &stack_size, &cinfo->ret);
1248                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1249                 }
1250         }
1251
1252         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1253                 gr = PARAM_REGS;
1254                 fr = FLOAT_PARAM_REGS;
1255
1256                 /* Emit the signature cookie just before the implicit arguments */
1257                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1258         }
1259
1260         for (i = pstart; i < sig->param_count; ++i) {
1261                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1262                 MonoType *ptype;
1263
1264 #ifdef TARGET_WIN32
1265                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1266                 if (gr > fr)
1267                         fr = gr;
1268                 else if (fr > gr)
1269                         gr = fr;
1270 #endif
1271
1272                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1273                         /* We allways pass the sig cookie on the stack for simplicity */
1274                         /*
1275                          * Prevent implicit arguments + the sig cookie from being passed
1276                          * in registers.
1277                          */
1278                         gr = PARAM_REGS;
1279                         fr = FLOAT_PARAM_REGS;
1280
1281                         /* Emit the signature cookie just before the implicit arguments */
1282                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1283                 }
1284
1285                 ptype = mini_get_underlying_type (sig->params [i]);
1286                 switch (ptype->type) {
1287                 case MONO_TYPE_I1:
1288                 case MONO_TYPE_U1:
1289                         add_general (&gr, &stack_size, ainfo);
1290                         break;
1291                 case MONO_TYPE_I2:
1292                 case MONO_TYPE_U2:
1293                         add_general (&gr, &stack_size, ainfo);
1294                         break;
1295                 case MONO_TYPE_I4:
1296                 case MONO_TYPE_U4:
1297                         add_general (&gr, &stack_size, ainfo);
1298                         break;
1299                 case MONO_TYPE_I:
1300                 case MONO_TYPE_U:
1301                 case MONO_TYPE_PTR:
1302                 case MONO_TYPE_FNPTR:
1303                 case MONO_TYPE_CLASS:
1304                 case MONO_TYPE_OBJECT:
1305                 case MONO_TYPE_STRING:
1306                 case MONO_TYPE_SZARRAY:
1307                 case MONO_TYPE_ARRAY:
1308                         add_general (&gr, &stack_size, ainfo);
1309                         break;
1310                 case MONO_TYPE_GENERICINST:
1311                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1312                                 add_general (&gr, &stack_size, ainfo);
1313                                 break;
1314                         }
1315                         if (mini_is_gsharedvt_variable_type (ptype)) {
1316                                 /* gsharedvt arguments are passed by ref */
1317                                 add_general (&gr, &stack_size, ainfo);
1318                                 if (ainfo->storage == ArgInIReg)
1319                                         ainfo->storage = ArgGSharedVtInReg;
1320                                 else
1321                                         ainfo->storage = ArgGSharedVtOnStack;
1322                                 break;
1323                         }
1324                         /* fall through */
1325                 case MONO_TYPE_VALUETYPE:
1326                 case MONO_TYPE_TYPEDBYREF:
1327                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1328                         break;
1329                 case MONO_TYPE_U8:
1330
1331                 case MONO_TYPE_I8:
1332                         add_general (&gr, &stack_size, ainfo);
1333                         break;
1334                 case MONO_TYPE_R4:
1335                         add_float (&fr, &stack_size, ainfo, FALSE);
1336                         break;
1337                 case MONO_TYPE_R8:
1338                         add_float (&fr, &stack_size, ainfo, TRUE);
1339                         break;
1340                 case MONO_TYPE_VAR:
1341                 case MONO_TYPE_MVAR:
1342                         /* gsharedvt arguments are passed by ref */
1343                         g_assert (mini_is_gsharedvt_type (ptype));
1344                         add_general (&gr, &stack_size, ainfo);
1345                         if (ainfo->storage == ArgInIReg)
1346                                 ainfo->storage = ArgGSharedVtInReg;
1347                         else
1348                                 ainfo->storage = ArgGSharedVtOnStack;
1349                         break;
1350                 default:
1351                         g_assert_not_reached ();
1352                 }
1353         }
1354
1355         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1356                 gr = PARAM_REGS;
1357                 fr = FLOAT_PARAM_REGS;
1358
1359                 /* Emit the signature cookie just before the implicit arguments */
1360                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1361         }
1362
1363         cinfo->stack_usage = stack_size;
1364         cinfo->reg_usage = gr;
1365         cinfo->freg_usage = fr;
1366         return cinfo;
1367 }
1368
1369 /*
1370  * mono_arch_get_argument_info:
1371  * @csig:  a method signature
1372  * @param_count: the number of parameters to consider
1373  * @arg_info: an array to store the result infos
1374  *
1375  * Gathers information on parameters such as size, alignment and
1376  * padding. arg_info should be large enought to hold param_count + 1 entries.
1377  *
1378  * Returns the size of the argument area on the stack.
1379  */
1380 int
1381 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1382 {
1383         int k;
1384         CallInfo *cinfo = get_call_info (NULL, csig);
1385         guint32 args_size = cinfo->stack_usage;
1386
1387         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1388         if (csig->hasthis) {
1389                 arg_info [0].offset = 0;
1390         }
1391
1392         for (k = 0; k < param_count; k++) {
1393                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1394                 /* FIXME: */
1395                 arg_info [k + 1].size = 0;
1396         }
1397
1398         g_free (cinfo);
1399
1400         return args_size;
1401 }
1402
1403 gboolean
1404 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1405 {
1406         CallInfo *c1, *c2;
1407         gboolean res;
1408         MonoType *callee_ret;
1409
1410         c1 = get_call_info (NULL, caller_sig);
1411         c2 = get_call_info (NULL, callee_sig);
1412         res = c1->stack_usage >= c2->stack_usage;
1413         callee_ret = mini_get_underlying_type (callee_sig->ret);
1414         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1415                 /* An address on the callee's stack is passed as the first argument */
1416                 res = FALSE;
1417
1418         g_free (c1);
1419         g_free (c2);
1420
1421         return res;
1422 }
1423
1424 /*
1425  * Initialize the cpu to execute managed code.
1426  */
1427 void
1428 mono_arch_cpu_init (void)
1429 {
1430 #ifndef _MSC_VER
1431         guint16 fpcw;
1432
1433         /* spec compliance requires running with double precision */
1434         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1435         fpcw &= ~X86_FPCW_PRECC_MASK;
1436         fpcw |= X86_FPCW_PREC_DOUBLE;
1437         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1438         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1439 #else
1440         /* TODO: This is crashing on Win64 right now.
1441         * _control87 (_PC_53, MCW_PC);
1442         */
1443 #endif
1444 }
1445
1446 /*
1447  * Initialize architecture specific code.
1448  */
1449 void
1450 mono_arch_init (void)
1451 {
1452         mono_os_mutex_init_recursive (&mini_arch_mutex);
1453 #if defined(__native_client_codegen__)
1454         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1455         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1456         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1457         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1458 #endif
1459
1460         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1461         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1462         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1463         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1464
1465         if (!mono_aot_only)
1466                 bp_trampoline = mini_get_breakpoint_trampoline ();
1467 }
1468
1469 /*
1470  * Cleanup architecture specific code.
1471  */
1472 void
1473 mono_arch_cleanup (void)
1474 {
1475         mono_os_mutex_destroy (&mini_arch_mutex);
1476 #if defined(__native_client_codegen__)
1477         mono_native_tls_free (nacl_instruction_depth);
1478         mono_native_tls_free (nacl_rex_tag);
1479         mono_native_tls_free (nacl_legacy_prefix_tag);
1480 #endif
1481 }
1482
1483 /*
1484  * This function returns the optimizations supported on this cpu.
1485  */
1486 guint32
1487 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1488 {
1489         guint32 opts = 0;
1490
1491         *exclude_mask = 0;
1492
1493         if (mono_hwcap_x86_has_cmov) {
1494                 opts |= MONO_OPT_CMOV;
1495
1496                 if (mono_hwcap_x86_has_fcmov)
1497                         opts |= MONO_OPT_FCMOV;
1498                 else
1499                         *exclude_mask |= MONO_OPT_FCMOV;
1500         } else {
1501                 *exclude_mask |= MONO_OPT_CMOV;
1502         }
1503
1504         return opts;
1505 }
1506
1507 /*
1508  * This function test for all SSE functions supported.
1509  *
1510  * Returns a bitmask corresponding to all supported versions.
1511  *
1512  */
1513 guint32
1514 mono_arch_cpu_enumerate_simd_versions (void)
1515 {
1516         guint32 sse_opts = 0;
1517
1518         if (mono_hwcap_x86_has_sse1)
1519                 sse_opts |= SIMD_VERSION_SSE1;
1520
1521         if (mono_hwcap_x86_has_sse2)
1522                 sse_opts |= SIMD_VERSION_SSE2;
1523
1524         if (mono_hwcap_x86_has_sse3)
1525                 sse_opts |= SIMD_VERSION_SSE3;
1526
1527         if (mono_hwcap_x86_has_ssse3)
1528                 sse_opts |= SIMD_VERSION_SSSE3;
1529
1530         if (mono_hwcap_x86_has_sse41)
1531                 sse_opts |= SIMD_VERSION_SSE41;
1532
1533         if (mono_hwcap_x86_has_sse42)
1534                 sse_opts |= SIMD_VERSION_SSE42;
1535
1536         if (mono_hwcap_x86_has_sse4a)
1537                 sse_opts |= SIMD_VERSION_SSE4a;
1538
1539         return sse_opts;
1540 }
1541
1542 #ifndef DISABLE_JIT
1543
1544 GList *
1545 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1546 {
1547         GList *vars = NULL;
1548         int i;
1549
1550         for (i = 0; i < cfg->num_varinfo; i++) {
1551                 MonoInst *ins = cfg->varinfo [i];
1552                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1553
1554                 /* unused vars */
1555                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1556                         continue;
1557
1558                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1559                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1560                         continue;
1561
1562                 if (mono_is_regsize_var (ins->inst_vtype)) {
1563                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1564                         g_assert (i == vmv->idx);
1565                         vars = g_list_prepend (vars, vmv);
1566                 }
1567         }
1568
1569         vars = mono_varlist_sort (cfg, vars, 0);
1570
1571         return vars;
1572 }
1573
1574 /**
1575  * mono_arch_compute_omit_fp:
1576  *
1577  *   Determine whenever the frame pointer can be eliminated.
1578  */
1579 static void
1580 mono_arch_compute_omit_fp (MonoCompile *cfg)
1581 {
1582         MonoMethodSignature *sig;
1583         MonoMethodHeader *header;
1584         int i, locals_size;
1585         CallInfo *cinfo;
1586
1587         if (cfg->arch.omit_fp_computed)
1588                 return;
1589
1590         header = cfg->header;
1591
1592         sig = mono_method_signature (cfg->method);
1593
1594         if (!cfg->arch.cinfo)
1595                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1596         cinfo = (CallInfo *)cfg->arch.cinfo;
1597
1598         /*
1599          * FIXME: Remove some of the restrictions.
1600          */
1601         cfg->arch.omit_fp = TRUE;
1602         cfg->arch.omit_fp_computed = TRUE;
1603
1604 #ifdef __native_client_codegen__
1605         /* NaCl modules may not change the value of RBP, so it cannot be */
1606         /* used as a normal register, but it can be used as a frame pointer*/
1607         cfg->disable_omit_fp = TRUE;
1608         cfg->arch.omit_fp = FALSE;
1609 #endif
1610
1611         if (cfg->disable_omit_fp)
1612                 cfg->arch.omit_fp = FALSE;
1613
1614         if (!debug_omit_fp ())
1615                 cfg->arch.omit_fp = FALSE;
1616         /*
1617         if (cfg->method->save_lmf)
1618                 cfg->arch.omit_fp = FALSE;
1619         */
1620         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1621                 cfg->arch.omit_fp = FALSE;
1622         if (header->num_clauses)
1623                 cfg->arch.omit_fp = FALSE;
1624         if (cfg->param_area)
1625                 cfg->arch.omit_fp = FALSE;
1626         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1627                 cfg->arch.omit_fp = FALSE;
1628         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1629                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1630                 cfg->arch.omit_fp = FALSE;
1631         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1632                 ArgInfo *ainfo = &cinfo->args [i];
1633
1634                 if (ainfo->storage == ArgOnStack) {
1635                         /*
1636                          * The stack offset can only be determined when the frame
1637                          * size is known.
1638                          */
1639                         cfg->arch.omit_fp = FALSE;
1640                 }
1641         }
1642
1643         locals_size = 0;
1644         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1645                 MonoInst *ins = cfg->varinfo [i];
1646                 int ialign;
1647
1648                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1649         }
1650 }
1651
1652 GList *
1653 mono_arch_get_global_int_regs (MonoCompile *cfg)
1654 {
1655         GList *regs = NULL;
1656
1657         mono_arch_compute_omit_fp (cfg);
1658
1659         if (cfg->arch.omit_fp)
1660                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1661
1662         /* We use the callee saved registers for global allocation */
1663         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1664         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1665         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1666         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1667 #ifndef __native_client_codegen__
1668         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1669 #endif
1670 #ifdef TARGET_WIN32
1671         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1672         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1673 #endif
1674
1675         return regs;
1676 }
1677
1678 GList*
1679 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1680 {
1681         GList *regs = NULL;
1682         int i;
1683
1684         /* All XMM registers */
1685         for (i = 0; i < 16; ++i)
1686                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1687
1688         return regs;
1689 }
1690
1691 GList*
1692 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1693 {
1694         static GList *r = NULL;
1695
1696         if (r == NULL) {
1697                 GList *regs = NULL;
1698
1699                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1700                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1701                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1702                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1703                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1704 #ifndef __native_client_codegen__
1705                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1706 #endif
1707
1708                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1709                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1710                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1711                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1712                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1713                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1714                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1715                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1716
1717                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1718         }
1719
1720         return r;
1721 }
1722
1723 GList*
1724 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1725 {
1726         int i;
1727         static GList *r = NULL;
1728
1729         if (r == NULL) {
1730                 GList *regs = NULL;
1731
1732                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1733                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1734
1735                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1736         }
1737
1738         return r;
1739 }
1740
1741 /*
1742  * mono_arch_regalloc_cost:
1743  *
1744  *  Return the cost, in number of memory references, of the action of
1745  * allocating the variable VMV into a register during global register
1746  * allocation.
1747  */
1748 guint32
1749 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1750 {
1751         MonoInst *ins = cfg->varinfo [vmv->idx];
1752
1753         if (cfg->method->save_lmf)
1754                 /* The register is already saved */
1755                 /* substract 1 for the invisible store in the prolog */
1756                 return (ins->opcode == OP_ARG) ? 0 : 1;
1757         else
1758                 /* push+pop */
1759                 return (ins->opcode == OP_ARG) ? 1 : 2;
1760 }
1761
1762 /*
1763  * mono_arch_fill_argument_info:
1764  *
1765  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1766  * of the method.
1767  */
1768 void
1769 mono_arch_fill_argument_info (MonoCompile *cfg)
1770 {
1771         MonoType *sig_ret;
1772         MonoMethodSignature *sig;
1773         MonoInst *ins;
1774         int i;
1775         CallInfo *cinfo;
1776
1777         sig = mono_method_signature (cfg->method);
1778
1779         cinfo = (CallInfo *)cfg->arch.cinfo;
1780         sig_ret = mini_get_underlying_type (sig->ret);
1781
1782         /*
1783          * Contrary to mono_arch_allocate_vars (), the information should describe
1784          * where the arguments are at the beginning of the method, not where they can be
1785          * accessed during the execution of the method. The later makes no sense for the
1786          * global register allocator, since a variable can be in more than one location.
1787          */
1788         switch (cinfo->ret.storage) {
1789         case ArgInIReg:
1790         case ArgInFloatSSEReg:
1791         case ArgInDoubleSSEReg:
1792                 cfg->ret->opcode = OP_REGVAR;
1793                 cfg->ret->inst_c0 = cinfo->ret.reg;
1794                 break;
1795         case ArgValuetypeInReg:
1796                 cfg->ret->opcode = OP_REGOFFSET;
1797                 cfg->ret->inst_basereg = -1;
1798                 cfg->ret->inst_offset = -1;
1799                 break;
1800         case ArgNone:
1801                 break;
1802         default:
1803                 g_assert_not_reached ();
1804         }
1805
1806         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1807                 ArgInfo *ainfo = &cinfo->args [i];
1808
1809                 ins = cfg->args [i];
1810
1811                 switch (ainfo->storage) {
1812                 case ArgInIReg:
1813                 case ArgInFloatSSEReg:
1814                 case ArgInDoubleSSEReg:
1815                         ins->opcode = OP_REGVAR;
1816                         ins->inst_c0 = ainfo->reg;
1817                         break;
1818                 case ArgOnStack:
1819                         ins->opcode = OP_REGOFFSET;
1820                         ins->inst_basereg = -1;
1821                         ins->inst_offset = -1;
1822                         break;
1823                 case ArgValuetypeInReg:
1824                         /* Dummy */
1825                         ins->opcode = OP_NOP;
1826                         break;
1827                 default:
1828                         g_assert_not_reached ();
1829                 }
1830         }
1831 }
1832
1833 void
1834 mono_arch_allocate_vars (MonoCompile *cfg)
1835 {
1836         MonoType *sig_ret;
1837         MonoMethodSignature *sig;
1838         MonoInst *ins;
1839         int i, offset;
1840         guint32 locals_stack_size, locals_stack_align;
1841         gint32 *offsets;
1842         CallInfo *cinfo;
1843
1844         sig = mono_method_signature (cfg->method);
1845
1846         cinfo = (CallInfo *)cfg->arch.cinfo;
1847         sig_ret = mini_get_underlying_type (sig->ret);
1848
1849         mono_arch_compute_omit_fp (cfg);
1850
1851         /*
1852          * We use the ABI calling conventions for managed code as well.
1853          * Exception: valuetypes are only sometimes passed or returned in registers.
1854          */
1855
1856         /*
1857          * The stack looks like this:
1858          * <incoming arguments passed on the stack>
1859          * <return value>
1860          * <lmf/caller saved registers>
1861          * <locals>
1862          * <spill area>
1863          * <localloc area>  -> grows dynamically
1864          * <params area>
1865          */
1866
1867         if (cfg->arch.omit_fp) {
1868                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1869                 cfg->frame_reg = AMD64_RSP;
1870                 offset = 0;
1871         } else {
1872                 /* Locals are allocated backwards from %fp */
1873                 cfg->frame_reg = AMD64_RBP;
1874                 offset = 0;
1875         }
1876
1877         cfg->arch.saved_iregs = cfg->used_int_regs;
1878         if (cfg->method->save_lmf)
1879                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1880                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1881
1882         if (cfg->arch.omit_fp)
1883                 cfg->arch.reg_save_area_offset = offset;
1884         /* Reserve space for callee saved registers */
1885         for (i = 0; i < AMD64_NREG; ++i)
1886                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1887                         offset += sizeof(mgreg_t);
1888                 }
1889         if (!cfg->arch.omit_fp)
1890                 cfg->arch.reg_save_area_offset = -offset;
1891
1892         if (sig_ret->type != MONO_TYPE_VOID) {
1893                 switch (cinfo->ret.storage) {
1894                 case ArgInIReg:
1895                 case ArgInFloatSSEReg:
1896                 case ArgInDoubleSSEReg:
1897                         cfg->ret->opcode = OP_REGVAR;
1898                         cfg->ret->inst_c0 = cinfo->ret.reg;
1899                         break;
1900                 case ArgValuetypeAddrInIReg:
1901                         /* The register is volatile */
1902                         cfg->vret_addr->opcode = OP_REGOFFSET;
1903                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1904                         if (cfg->arch.omit_fp) {
1905                                 cfg->vret_addr->inst_offset = offset;
1906                                 offset += 8;
1907                         } else {
1908                                 offset += 8;
1909                                 cfg->vret_addr->inst_offset = -offset;
1910                         }
1911                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1912                                 printf ("vret_addr =");
1913                                 mono_print_ins (cfg->vret_addr);
1914                         }
1915                         break;
1916                 case ArgValuetypeInReg:
1917                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1918                         cfg->ret->opcode = OP_REGOFFSET;
1919                         cfg->ret->inst_basereg = cfg->frame_reg;
1920                         if (cfg->arch.omit_fp) {
1921                                 cfg->ret->inst_offset = offset;
1922                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1923                         } else {
1924                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1925                                 cfg->ret->inst_offset = - offset;
1926                         }
1927                         break;
1928                 default:
1929                         g_assert_not_reached ();
1930                 }
1931                 cfg->ret->dreg = cfg->ret->inst_c0;
1932         }
1933
1934         /* Allocate locals */
1935         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1936         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1937                 char *mname = mono_method_full_name (cfg->method, TRUE);
1938                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1939                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1940                 g_free (mname);
1941                 return;
1942         }
1943
1944         if (locals_stack_align) {
1945                 offset += (locals_stack_align - 1);
1946                 offset &= ~(locals_stack_align - 1);
1947         }
1948         if (cfg->arch.omit_fp) {
1949                 cfg->locals_min_stack_offset = offset;
1950                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1951         } else {
1952                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1953                 cfg->locals_max_stack_offset = - offset;
1954         }
1955
1956         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1957                 if (offsets [i] != -1) {
1958                         MonoInst *ins = cfg->varinfo [i];
1959                         ins->opcode = OP_REGOFFSET;
1960                         ins->inst_basereg = cfg->frame_reg;
1961                         if (cfg->arch.omit_fp)
1962                                 ins->inst_offset = (offset + offsets [i]);
1963                         else
1964                                 ins->inst_offset = - (offset + offsets [i]);
1965                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1966                 }
1967         }
1968         offset += locals_stack_size;
1969
1970         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1971                 g_assert (!cfg->arch.omit_fp);
1972                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1973                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1974         }
1975
1976         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1977                 ins = cfg->args [i];
1978                 if (ins->opcode != OP_REGVAR) {
1979                         ArgInfo *ainfo = &cinfo->args [i];
1980                         gboolean inreg = TRUE;
1981
1982                         /* FIXME: Allocate volatile arguments to registers */
1983                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1984                                 inreg = FALSE;
1985
1986                         /*
1987                          * Under AMD64, all registers used to pass arguments to functions
1988                          * are volatile across calls.
1989                          * FIXME: Optimize this.
1990                          */
1991                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1992                                 inreg = FALSE;
1993
1994                         ins->opcode = OP_REGOFFSET;
1995
1996                         switch (ainfo->storage) {
1997                         case ArgInIReg:
1998                         case ArgInFloatSSEReg:
1999                         case ArgInDoubleSSEReg:
2000                         case ArgGSharedVtInReg:
2001                                 if (inreg) {
2002                                         ins->opcode = OP_REGVAR;
2003                                         ins->dreg = ainfo->reg;
2004                                 }
2005                                 break;
2006                         case ArgOnStack:
2007                         case ArgGSharedVtOnStack:
2008                                 g_assert (!cfg->arch.omit_fp);
2009                                 ins->opcode = OP_REGOFFSET;
2010                                 ins->inst_basereg = cfg->frame_reg;
2011                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
2012                                 break;
2013                         case ArgValuetypeInReg:
2014                                 break;
2015                         case ArgValuetypeAddrInIReg: {
2016                                 MonoInst *indir;
2017                                 g_assert (!cfg->arch.omit_fp);
2018
2019                                 MONO_INST_NEW (cfg, indir, 0);
2020                                 indir->opcode = OP_REGOFFSET;
2021                                 if (ainfo->pair_storage [0] == ArgInIReg) {
2022                                         indir->inst_basereg = cfg->frame_reg;
2023                                         offset = ALIGN_TO (offset, sizeof (gpointer));
2024                                         offset += (sizeof (gpointer));
2025                                         indir->inst_offset = - offset;
2026                                 }
2027                                 else {
2028                                         indir->inst_basereg = cfg->frame_reg;
2029                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
2030                                 }
2031
2032                                 ins->opcode = OP_VTARG_ADDR;
2033                                 ins->inst_left = indir;
2034
2035                                 break;
2036                         }
2037                         default:
2038                                 NOT_IMPLEMENTED;
2039                         }
2040
2041                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
2042                                 ins->opcode = OP_REGOFFSET;
2043                                 ins->inst_basereg = cfg->frame_reg;
2044                                 /* These arguments are saved to the stack in the prolog */
2045                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2046                                 if (cfg->arch.omit_fp) {
2047                                         ins->inst_offset = offset;
2048                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2049                                         // Arguments are yet supported by the stack map creation code
2050                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2051                                 } else {
2052                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2053                                         ins->inst_offset = - offset;
2054                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2055                                 }
2056                         }
2057                 }
2058         }
2059
2060         cfg->stack_offset = offset;
2061 }
2062
2063 void
2064 mono_arch_create_vars (MonoCompile *cfg)
2065 {
2066         MonoMethodSignature *sig;
2067         CallInfo *cinfo;
2068         MonoType *sig_ret;
2069
2070         sig = mono_method_signature (cfg->method);
2071
2072         if (!cfg->arch.cinfo)
2073                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2074         cinfo = (CallInfo *)cfg->arch.cinfo;
2075
2076         if (cinfo->ret.storage == ArgValuetypeInReg)
2077                 cfg->ret_var_is_local = TRUE;
2078
2079         sig_ret = mini_get_underlying_type (sig->ret);
2080         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2081                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2082                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2083                         printf ("vret_addr = ");
2084                         mono_print_ins (cfg->vret_addr);
2085                 }
2086         }
2087
2088         if (cfg->gen_sdb_seq_points) {
2089                 MonoInst *ins;
2090
2091                 if (cfg->compile_aot) {
2092                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2093                         ins->flags |= MONO_INST_VOLATILE;
2094                         cfg->arch.seq_point_info_var = ins;
2095                 }
2096                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2097                 ins->flags |= MONO_INST_VOLATILE;
2098                 cfg->arch.ss_tramp_var = ins;
2099
2100                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2101                 ins->flags |= MONO_INST_VOLATILE;
2102                 cfg->arch.bp_tramp_var = ins;
2103         }
2104
2105         if (cfg->method->save_lmf)
2106                 cfg->create_lmf_var = TRUE;
2107
2108         if (cfg->method->save_lmf) {
2109                 cfg->lmf_ir = TRUE;
2110 #if !defined(TARGET_WIN32)
2111                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2112                         cfg->lmf_ir_mono_lmf = TRUE;
2113 #endif
2114         }
2115 }
2116
2117 static void
2118 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2119 {
2120         MonoInst *ins;
2121
2122         switch (storage) {
2123         case ArgInIReg:
2124                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2125                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2126                 ins->sreg1 = tree->dreg;
2127                 MONO_ADD_INS (cfg->cbb, ins);
2128                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2129                 break;
2130         case ArgInFloatSSEReg:
2131                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2132                 ins->dreg = mono_alloc_freg (cfg);
2133                 ins->sreg1 = tree->dreg;
2134                 MONO_ADD_INS (cfg->cbb, ins);
2135
2136                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2137                 break;
2138         case ArgInDoubleSSEReg:
2139                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2140                 ins->dreg = mono_alloc_freg (cfg);
2141                 ins->sreg1 = tree->dreg;
2142                 MONO_ADD_INS (cfg->cbb, ins);
2143
2144                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2145
2146                 break;
2147         default:
2148                 g_assert_not_reached ();
2149         }
2150 }
2151
2152 static int
2153 arg_storage_to_load_membase (ArgStorage storage)
2154 {
2155         switch (storage) {
2156         case ArgInIReg:
2157 #if defined(__mono_ilp32__)
2158                 return OP_LOADI8_MEMBASE;
2159 #else
2160                 return OP_LOAD_MEMBASE;
2161 #endif
2162         case ArgInDoubleSSEReg:
2163                 return OP_LOADR8_MEMBASE;
2164         case ArgInFloatSSEReg:
2165                 return OP_LOADR4_MEMBASE;
2166         default:
2167                 g_assert_not_reached ();
2168         }
2169
2170         return -1;
2171 }
2172
2173 static void
2174 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2175 {
2176         MonoMethodSignature *tmp_sig;
2177         int sig_reg;
2178
2179         if (call->tail_call)
2180                 NOT_IMPLEMENTED;
2181
2182         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2183
2184         /*
2185          * mono_ArgIterator_Setup assumes the signature cookie is
2186          * passed first and all the arguments which were before it are
2187          * passed on the stack after the signature. So compensate by
2188          * passing a different signature.
2189          */
2190         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2191         tmp_sig->param_count -= call->signature->sentinelpos;
2192         tmp_sig->sentinelpos = 0;
2193         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2194
2195         sig_reg = mono_alloc_ireg (cfg);
2196         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2197
2198         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2199 }
2200
2201 #ifdef ENABLE_LLVM
2202 static inline LLVMArgStorage
2203 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2204 {
2205         switch (storage) {
2206         case ArgInIReg:
2207                 return LLVMArgInIReg;
2208         case ArgNone:
2209                 return LLVMArgNone;
2210         case ArgGSharedVtInReg:
2211         case ArgGSharedVtOnStack:
2212                 return LLVMArgGSharedVt;
2213         default:
2214                 g_assert_not_reached ();
2215                 return LLVMArgNone;
2216         }
2217 }
2218
2219 LLVMCallInfo*
2220 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2221 {
2222         int i, n;
2223         CallInfo *cinfo;
2224         ArgInfo *ainfo;
2225         int j;
2226         LLVMCallInfo *linfo;
2227         MonoType *t, *sig_ret;
2228
2229         n = sig->param_count + sig->hasthis;
2230         sig_ret = mini_get_underlying_type (sig->ret);
2231
2232         cinfo = get_call_info (cfg->mempool, sig);
2233
2234         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2235
2236         /*
2237          * LLVM always uses the native ABI while we use our own ABI, the
2238          * only difference is the handling of vtypes:
2239          * - we only pass/receive them in registers in some cases, and only
2240          *   in 1 or 2 integer registers.
2241          */
2242         switch (cinfo->ret.storage) {
2243         case ArgNone:
2244                 linfo->ret.storage = LLVMArgNone;
2245                 break;
2246         case ArgInIReg:
2247         case ArgInFloatSSEReg:
2248         case ArgInDoubleSSEReg:
2249                 linfo->ret.storage = LLVMArgNormal;
2250                 break;
2251         case ArgValuetypeInReg: {
2252                 ainfo = &cinfo->ret;
2253
2254                 if (sig->pinvoke &&
2255                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2256                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2257                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
2258                         cfg->disable_llvm = TRUE;
2259                         return linfo;
2260                 }
2261
2262                 linfo->ret.storage = LLVMArgVtypeInReg;
2263                 for (j = 0; j < 2; ++j)
2264                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2265                 break;
2266         }
2267         case ArgValuetypeAddrInIReg:
2268                 /* Vtype returned using a hidden argument */
2269                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2270                 linfo->vret_arg_index = cinfo->vret_arg_index;
2271                 break;
2272         default:
2273                 g_assert_not_reached ();
2274                 break;
2275         }
2276
2277         for (i = 0; i < n; ++i) {
2278                 ainfo = cinfo->args + i;
2279
2280                 if (i >= sig->hasthis)
2281                         t = sig->params [i - sig->hasthis];
2282                 else
2283                         t = &mono_defaults.int_class->byval_arg;
2284
2285                 linfo->args [i].storage = LLVMArgNone;
2286
2287                 switch (ainfo->storage) {
2288                 case ArgInIReg:
2289                         linfo->args [i].storage = LLVMArgNormal;
2290                         break;
2291                 case ArgInDoubleSSEReg:
2292                 case ArgInFloatSSEReg:
2293                         linfo->args [i].storage = LLVMArgNormal;
2294                         break;
2295                 case ArgOnStack:
2296                         if (MONO_TYPE_ISSTRUCT (t))
2297                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2298                         else
2299                                 linfo->args [i].storage = LLVMArgNormal;
2300                         break;
2301                 case ArgValuetypeInReg:
2302                         if (sig->pinvoke &&
2303                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2304                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2305                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2306                                 cfg->disable_llvm = TRUE;
2307                                 return linfo;
2308                         }
2309
2310                         linfo->args [i].storage = LLVMArgVtypeInReg;
2311                         for (j = 0; j < 2; ++j)
2312                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2313                         break;
2314                 case ArgGSharedVtInReg:
2315                 case ArgGSharedVtOnStack:
2316                         linfo->args [i].storage = LLVMArgGSharedVt;
2317                         break;
2318                 default:
2319                         cfg->exception_message = g_strdup ("ainfo->storage");
2320                         cfg->disable_llvm = TRUE;
2321                         break;
2322                 }
2323         }
2324
2325         return linfo;
2326 }
2327 #endif
2328
2329 void
2330 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2331 {
2332         MonoInst *arg, *in;
2333         MonoMethodSignature *sig;
2334         MonoType *sig_ret;
2335         int i, n;
2336         CallInfo *cinfo;
2337         ArgInfo *ainfo;
2338
2339         sig = call->signature;
2340         n = sig->param_count + sig->hasthis;
2341
2342         cinfo = get_call_info (cfg->mempool, sig);
2343
2344         sig_ret = sig->ret;
2345
2346         if (COMPILE_LLVM (cfg)) {
2347                 /* We shouldn't be called in the llvm case */
2348                 cfg->disable_llvm = TRUE;
2349                 return;
2350         }
2351
2352         /*
2353          * Emit all arguments which are passed on the stack to prevent register
2354          * allocation problems.
2355          */
2356         for (i = 0; i < n; ++i) {
2357                 MonoType *t;
2358                 ainfo = cinfo->args + i;
2359
2360                 in = call->args [i];
2361
2362                 if (sig->hasthis && i == 0)
2363                         t = &mono_defaults.object_class->byval_arg;
2364                 else
2365                         t = sig->params [i - sig->hasthis];
2366
2367                 t = mini_get_underlying_type (t);
2368                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2369                         if (!t->byref) {
2370                                 if (t->type == MONO_TYPE_R4)
2371                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2372                                 else if (t->type == MONO_TYPE_R8)
2373                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2374                                 else
2375                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2376                         } else {
2377                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2378                         }
2379                         if (cfg->compute_gc_maps) {
2380                                 MonoInst *def;
2381
2382                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2383                         }
2384                 }
2385         }
2386
2387         /*
2388          * Emit all parameters passed in registers in non-reverse order for better readability
2389          * and to help the optimization in emit_prolog ().
2390          */
2391         for (i = 0; i < n; ++i) {
2392                 ainfo = cinfo->args + i;
2393
2394                 in = call->args [i];
2395
2396                 if (ainfo->storage == ArgInIReg)
2397                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2398         }
2399
2400         for (i = n - 1; i >= 0; --i) {
2401                 MonoType *t;
2402
2403                 ainfo = cinfo->args + i;
2404
2405                 in = call->args [i];
2406
2407                 if (sig->hasthis && i == 0)
2408                         t = &mono_defaults.object_class->byval_arg;
2409                 else
2410                         t = sig->params [i - sig->hasthis];
2411                 t = mini_get_underlying_type (t);
2412
2413                 switch (ainfo->storage) {
2414                 case ArgInIReg:
2415                         /* Already done */
2416                         break;
2417                 case ArgInFloatSSEReg:
2418                 case ArgInDoubleSSEReg:
2419                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2420                         break;
2421                 case ArgOnStack:
2422                 case ArgValuetypeInReg:
2423                 case ArgValuetypeAddrInIReg:
2424                 case ArgGSharedVtInReg:
2425                 case ArgGSharedVtOnStack: {
2426                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2427                                 /* Already emitted above */
2428                                 break;
2429                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2430                                 MonoInst *call_inst = (MonoInst*)call;
2431                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2432                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2433                                 break;
2434                         }
2435
2436                         guint32 align;
2437                         guint32 size;
2438
2439                         if (sig->pinvoke)
2440                                 size = mono_type_native_stack_size (t, &align);
2441                         else {
2442                                 /*
2443                                  * Other backends use mono_type_stack_size (), but that
2444                                  * aligns the size to 8, which is larger than the size of
2445                                  * the source, leading to reads of invalid memory if the
2446                                  * source is at the end of address space.
2447                                  */
2448                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2449                         }
2450
2451                         if (size >= 10000) {
2452                                 /* Avoid asserts in emit_memcpy () */
2453                                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2454                                 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2455                                 /* Continue normally */
2456                         }
2457
2458                         if (size > 0) {
2459                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2460                                 arg->sreg1 = in->dreg;
2461                                 arg->klass = mono_class_from_mono_type (t);
2462                                 arg->backend.size = size;
2463                                 arg->inst_p0 = call;
2464                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2465                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2466
2467                                 MONO_ADD_INS (cfg->cbb, arg);
2468                         }
2469                         break;
2470                 }
2471                 default:
2472                         g_assert_not_reached ();
2473                 }
2474
2475                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2476                         /* Emit the signature cookie just before the implicit arguments */
2477                         emit_sig_cookie (cfg, call, cinfo);
2478         }
2479
2480         /* Handle the case where there are no implicit arguments */
2481         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2482                 emit_sig_cookie (cfg, call, cinfo);
2483
2484         switch (cinfo->ret.storage) {
2485         case ArgValuetypeInReg:
2486                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2487                         /*
2488                          * Tell the JIT to use a more efficient calling convention: call using
2489                          * OP_CALL, compute the result location after the call, and save the
2490                          * result there.
2491                          */
2492                         call->vret_in_reg = TRUE;
2493                         /*
2494                          * Nullify the instruction computing the vret addr to enable
2495                          * future optimizations.
2496                          */
2497                         if (call->vret_var)
2498                                 NULLIFY_INS (call->vret_var);
2499                 } else {
2500                         if (call->tail_call)
2501                                 NOT_IMPLEMENTED;
2502                         /*
2503                          * The valuetype is in RAX:RDX after the call, need to be copied to
2504                          * the stack. Push the address here, so the call instruction can
2505                          * access it.
2506                          */
2507                         if (!cfg->arch.vret_addr_loc) {
2508                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2509                                 /* Prevent it from being register allocated or optimized away */
2510                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2511                         }
2512
2513                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2514                 }
2515                 break;
2516         case ArgValuetypeAddrInIReg: {
2517                 MonoInst *vtarg;
2518                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2519                 vtarg->sreg1 = call->vret_var->dreg;
2520                 vtarg->dreg = mono_alloc_preg (cfg);
2521                 MONO_ADD_INS (cfg->cbb, vtarg);
2522
2523                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2524                 break;
2525         }
2526         default:
2527                 break;
2528         }
2529
2530         if (cfg->method->save_lmf) {
2531                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2532                 MONO_ADD_INS (cfg->cbb, arg);
2533         }
2534
2535         call->stack_usage = cinfo->stack_usage;
2536 }
2537
2538 void
2539 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2540 {
2541         MonoInst *arg;
2542         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2543         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2544         int size = ins->backend.size;
2545
2546         switch (ainfo->storage) {
2547         case ArgValuetypeInReg: {
2548                 MonoInst *load;
2549                 int part;
2550
2551                 for (part = 0; part < 2; ++part) {
2552                         if (ainfo->pair_storage [part] == ArgNone)
2553                                 continue;
2554
2555                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2556                         load->inst_basereg = src->dreg;
2557                         load->inst_offset = part * sizeof(mgreg_t);
2558
2559                         switch (ainfo->pair_storage [part]) {
2560                         case ArgInIReg:
2561                                 load->dreg = mono_alloc_ireg (cfg);
2562                                 break;
2563                         case ArgInDoubleSSEReg:
2564                         case ArgInFloatSSEReg:
2565                                 load->dreg = mono_alloc_freg (cfg);
2566                                 break;
2567                         default:
2568                                 g_assert_not_reached ();
2569                         }
2570                         MONO_ADD_INS (cfg->cbb, load);
2571
2572                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2573                 }
2574                 break;
2575         }
2576         case ArgValuetypeAddrInIReg: {
2577                 MonoInst *vtaddr, *load;
2578                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2579
2580                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2581                 cfg->has_indirection = TRUE;
2582                 load->inst_p0 = vtaddr;
2583                 vtaddr->flags |= MONO_INST_INDIRECT;
2584                 load->type = STACK_MP;
2585                 load->klass = vtaddr->klass;
2586                 load->dreg = mono_alloc_ireg (cfg);
2587                 MONO_ADD_INS (cfg->cbb, load);
2588                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2589
2590                 if (ainfo->pair_storage [0] == ArgInIReg) {
2591                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2592                         arg->dreg = mono_alloc_ireg (cfg);
2593                         arg->sreg1 = load->dreg;
2594                         arg->inst_imm = 0;
2595                         MONO_ADD_INS (cfg->cbb, arg);
2596                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2597                 } else {
2598                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2599                 }
2600                 break;
2601         }
2602         case ArgGSharedVtInReg:
2603                 /* Pass by addr */
2604                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2605                 break;
2606         case ArgGSharedVtOnStack:
2607                 g_assert_not_reached ();
2608                 break;
2609         default:
2610                 if (size == 8) {
2611                         int dreg = mono_alloc_ireg (cfg);
2612
2613                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2614                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2615                 } else if (size <= 40) {
2616                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2617                 } else {
2618                         // FIXME: Code growth
2619                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2620                 }
2621
2622                 if (cfg->compute_gc_maps) {
2623                         MonoInst *def;
2624                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2625                 }
2626         }
2627 }
2628
2629 void
2630 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2631 {
2632         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2633
2634         if (ret->type == MONO_TYPE_R4) {
2635                 if (COMPILE_LLVM (cfg))
2636                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2637                 else
2638                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2639                 return;
2640         } else if (ret->type == MONO_TYPE_R8) {
2641                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2642                 return;
2643         }
2644
2645         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2646 }
2647
2648 #endif /* DISABLE_JIT */
2649
2650 #define EMIT_COND_BRANCH(ins,cond,sign) \
2651         if (ins->inst_true_bb->native_offset) { \
2652                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2653         } else { \
2654                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2655                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2656             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2657                         x86_branch8 (code, cond, 0, sign); \
2658                 else \
2659                         x86_branch32 (code, cond, 0, sign); \
2660 }
2661
2662 typedef struct {
2663         MonoMethodSignature *sig;
2664         CallInfo *cinfo;
2665 } ArchDynCallInfo;
2666
2667 static gboolean
2668 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2669 {
2670         int i;
2671
2672 #ifdef HOST_WIN32
2673         return FALSE;
2674 #endif
2675
2676         switch (cinfo->ret.storage) {
2677         case ArgNone:
2678         case ArgInIReg:
2679                 break;
2680         case ArgValuetypeInReg: {
2681                 ArgInfo *ainfo = &cinfo->ret;
2682
2683                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2684                         return FALSE;
2685                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2686                         return FALSE;
2687                 break;
2688         }
2689         default:
2690                 return FALSE;
2691         }
2692
2693         for (i = 0; i < cinfo->nargs; ++i) {
2694                 ArgInfo *ainfo = &cinfo->args [i];
2695                 switch (ainfo->storage) {
2696                 case ArgInIReg:
2697                         break;
2698                 case ArgValuetypeInReg:
2699                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2700                                 return FALSE;
2701                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2702                                 return FALSE;
2703                         break;
2704                 default:
2705                         return FALSE;
2706                 }
2707         }
2708
2709         return TRUE;
2710 }
2711
2712 /*
2713  * mono_arch_dyn_call_prepare:
2714  *
2715  *   Return a pointer to an arch-specific structure which contains information
2716  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2717  * supported for SIG.
2718  * This function is equivalent to ffi_prep_cif in libffi.
2719  */
2720 MonoDynCallInfo*
2721 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2722 {
2723         ArchDynCallInfo *info;
2724         CallInfo *cinfo;
2725
2726         cinfo = get_call_info (NULL, sig);
2727
2728         if (!dyn_call_supported (sig, cinfo)) {
2729                 g_free (cinfo);
2730                 return NULL;
2731         }
2732
2733         info = g_new0 (ArchDynCallInfo, 1);
2734         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2735         info->sig = sig;
2736         info->cinfo = cinfo;
2737
2738         return (MonoDynCallInfo*)info;
2739 }
2740
2741 /*
2742  * mono_arch_dyn_call_free:
2743  *
2744  *   Free a MonoDynCallInfo structure.
2745  */
2746 void
2747 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2748 {
2749         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2750
2751         g_free (ainfo->cinfo);
2752         g_free (ainfo);
2753 }
2754
2755 #if !defined(__native_client__)
2756 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2757 #define GREG_TO_PTR(greg) (gpointer)(greg)
2758 #else
2759 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2760 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2761 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2762 #endif
2763
2764 /*
2765  * mono_arch_get_start_dyn_call:
2766  *
2767  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2768  * store the result into BUF.
2769  * ARGS should be an array of pointers pointing to the arguments.
2770  * RET should point to a memory buffer large enought to hold the result of the
2771  * call.
2772  * This function should be as fast as possible, any work which does not depend
2773  * on the actual values of the arguments should be done in
2774  * mono_arch_dyn_call_prepare ().
2775  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2776  * libffi.
2777  */
2778 void
2779 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2780 {
2781         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2782         DynCallArgs *p = (DynCallArgs*)buf;
2783         int arg_index, greg, i, pindex;
2784         MonoMethodSignature *sig = dinfo->sig;
2785         int buffer_offset = 0;
2786
2787         g_assert (buf_len >= sizeof (DynCallArgs));
2788
2789         p->res = 0;
2790         p->ret = ret;
2791
2792         arg_index = 0;
2793         greg = 0;
2794         pindex = 0;
2795
2796         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2797                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2798                 if (!sig->hasthis)
2799                         pindex = 1;
2800         }
2801
2802         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2803                 p->regs [greg ++] = PTR_TO_GREG(ret);
2804
2805         for (i = pindex; i < sig->param_count; i++) {
2806                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2807                 gpointer *arg = args [arg_index ++];
2808
2809                 if (t->byref) {
2810                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2811                         continue;
2812                 }
2813
2814                 switch (t->type) {
2815                 case MONO_TYPE_STRING:
2816                 case MONO_TYPE_CLASS:
2817                 case MONO_TYPE_ARRAY:
2818                 case MONO_TYPE_SZARRAY:
2819                 case MONO_TYPE_OBJECT:
2820                 case MONO_TYPE_PTR:
2821                 case MONO_TYPE_I:
2822                 case MONO_TYPE_U:
2823 #if !defined(__mono_ilp32__)
2824                 case MONO_TYPE_I8:
2825                 case MONO_TYPE_U8:
2826 #endif
2827                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2828                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2829                         break;
2830 #if defined(__mono_ilp32__)
2831                 case MONO_TYPE_I8:
2832                 case MONO_TYPE_U8:
2833                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2834                         p->regs [greg ++] = *(guint64*)(arg);
2835                         break;
2836 #endif
2837                 case MONO_TYPE_U1:
2838                         p->regs [greg ++] = *(guint8*)(arg);
2839                         break;
2840                 case MONO_TYPE_I1:
2841                         p->regs [greg ++] = *(gint8*)(arg);
2842                         break;
2843                 case MONO_TYPE_I2:
2844                         p->regs [greg ++] = *(gint16*)(arg);
2845                         break;
2846                 case MONO_TYPE_U2:
2847                         p->regs [greg ++] = *(guint16*)(arg);
2848                         break;
2849                 case MONO_TYPE_I4:
2850                         p->regs [greg ++] = *(gint32*)(arg);
2851                         break;
2852                 case MONO_TYPE_U4:
2853                         p->regs [greg ++] = *(guint32*)(arg);
2854                         break;
2855                 case MONO_TYPE_GENERICINST:
2856                     if (MONO_TYPE_IS_REFERENCE (t)) {
2857                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2858                                 break;
2859                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2860                                         MonoClass *klass = mono_class_from_mono_type (t);
2861                                         guint8 *nullable_buf;
2862                                         int size;
2863
2864                                         size = mono_class_value_size (klass, NULL);
2865                                         nullable_buf = p->buffer + buffer_offset;
2866                                         buffer_offset += size;
2867                                         g_assert (buffer_offset <= 256);
2868
2869                                         /* The argument pointed to by arg is either a boxed vtype or null */
2870                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2871
2872                                         arg = (gpointer*)nullable_buf;
2873                                         /* Fall though */
2874
2875                         } else {
2876                                 /* Fall through */
2877                         }
2878                 case MONO_TYPE_VALUETYPE: {
2879                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2880
2881                         g_assert (ainfo->storage == ArgValuetypeInReg);
2882                         if (ainfo->pair_storage [0] != ArgNone) {
2883                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2884                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2885                         }
2886                         if (ainfo->pair_storage [1] != ArgNone) {
2887                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2888                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2889                         }
2890                         break;
2891                 }
2892                 default:
2893                         g_assert_not_reached ();
2894                 }
2895         }
2896
2897         g_assert (greg <= PARAM_REGS);
2898 }
2899
2900 /*
2901  * mono_arch_finish_dyn_call:
2902  *
2903  *   Store the result of a dyn call into the return value buffer passed to
2904  * start_dyn_call ().
2905  * This function should be as fast as possible, any work which does not depend
2906  * on the actual values of the arguments should be done in
2907  * mono_arch_dyn_call_prepare ().
2908  */
2909 void
2910 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2911 {
2912         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2913         MonoMethodSignature *sig = dinfo->sig;
2914         guint8 *ret = ((DynCallArgs*)buf)->ret;
2915         mgreg_t res = ((DynCallArgs*)buf)->res;
2916         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2917
2918         switch (sig_ret->type) {
2919         case MONO_TYPE_VOID:
2920                 *(gpointer*)ret = NULL;
2921                 break;
2922         case MONO_TYPE_STRING:
2923         case MONO_TYPE_CLASS:
2924         case MONO_TYPE_ARRAY:
2925         case MONO_TYPE_SZARRAY:
2926         case MONO_TYPE_OBJECT:
2927         case MONO_TYPE_I:
2928         case MONO_TYPE_U:
2929         case MONO_TYPE_PTR:
2930                 *(gpointer*)ret = GREG_TO_PTR(res);
2931                 break;
2932         case MONO_TYPE_I1:
2933                 *(gint8*)ret = res;
2934                 break;
2935         case MONO_TYPE_U1:
2936                 *(guint8*)ret = res;
2937                 break;
2938         case MONO_TYPE_I2:
2939                 *(gint16*)ret = res;
2940                 break;
2941         case MONO_TYPE_U2:
2942                 *(guint16*)ret = res;
2943                 break;
2944         case MONO_TYPE_I4:
2945                 *(gint32*)ret = res;
2946                 break;
2947         case MONO_TYPE_U4:
2948                 *(guint32*)ret = res;
2949                 break;
2950         case MONO_TYPE_I8:
2951                 *(gint64*)ret = res;
2952                 break;
2953         case MONO_TYPE_U8:
2954                 *(guint64*)ret = res;
2955                 break;
2956         case MONO_TYPE_GENERICINST:
2957                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2958                         *(gpointer*)ret = GREG_TO_PTR(res);
2959                         break;
2960                 } else {
2961                         /* Fall through */
2962                 }
2963         case MONO_TYPE_VALUETYPE:
2964                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2965                         /* Nothing to do */
2966                 } else {
2967                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2968
2969                         g_assert (ainfo->storage == ArgValuetypeInReg);
2970
2971                         if (ainfo->pair_storage [0] != ArgNone) {
2972                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2973                                 ((mgreg_t*)ret)[0] = res;
2974                         }
2975
2976                         g_assert (ainfo->pair_storage [1] == ArgNone);
2977                 }
2978                 break;
2979         default:
2980                 g_assert_not_reached ();
2981         }
2982 }
2983
2984 /* emit an exception if condition is fail */
2985 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2986         do {                                                        \
2987                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2988                 if (tins == NULL) {                                                                             \
2989                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2990                                         MONO_PATCH_INFO_EXC, exc_name);  \
2991                         x86_branch32 (code, cond, 0, signed);               \
2992                 } else {        \
2993                         EMIT_COND_BRANCH (tins, cond, signed);  \
2994                 }                       \
2995         } while (0);
2996
2997 #define EMIT_FPCOMPARE(code) do { \
2998         amd64_fcompp (code); \
2999         amd64_fnstsw (code); \
3000 } while (0);
3001
3002 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
3003     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
3004         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
3005         amd64_ ##op (code); \
3006         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3007         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3008 } while (0);
3009
3010 static guint8*
3011 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3012 {
3013         gboolean no_patch = FALSE;
3014
3015         /*
3016          * FIXME: Add support for thunks
3017          */
3018         {
3019                 gboolean near_call = FALSE;
3020
3021                 /*
3022                  * Indirect calls are expensive so try to make a near call if possible.
3023                  * The caller memory is allocated by the code manager so it is
3024                  * guaranteed to be at a 32 bit offset.
3025                  */
3026
3027                 if (patch_type != MONO_PATCH_INFO_ABS) {
3028                         /* The target is in memory allocated using the code manager */
3029                         near_call = TRUE;
3030
3031                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3032                                 if (((MonoMethod*)data)->klass->image->aot_module)
3033                                         /* The callee might be an AOT method */
3034                                         near_call = FALSE;
3035                                 if (((MonoMethod*)data)->dynamic)
3036                                         /* The target is in malloc-ed memory */
3037                                         near_call = FALSE;
3038                         }
3039
3040                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3041                                 /*
3042                                  * The call might go directly to a native function without
3043                                  * the wrapper.
3044                                  */
3045                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
3046                                 if (mi) {
3047                                         gconstpointer target = mono_icall_get_wrapper (mi);
3048                                         if ((((guint64)target) >> 32) != 0)
3049                                                 near_call = FALSE;
3050                                 }
3051                         }
3052                 }
3053                 else {
3054                         MonoJumpInfo *jinfo = NULL;
3055
3056                         if (cfg->abs_patches)
3057                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
3058                         if (jinfo) {
3059                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3060                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3061                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3062                                                 near_call = TRUE;
3063                                         no_patch = TRUE;
3064                                 } else {
3065                                         /*
3066                                          * This is not really an optimization, but required because the
3067                                          * generic class init trampolines use R11 to pass the vtable.
3068                                          */
3069                                         near_call = TRUE;
3070                                 }
3071                         } else {
3072                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3073                                 if (info) {
3074                                         if (info->func == info->wrapper) {
3075                                                 /* No wrapper */
3076                                                 if ((((guint64)info->func) >> 32) == 0)
3077                                                         near_call = TRUE;
3078                                         }
3079                                         else {
3080                                                 /* See the comment in mono_codegen () */
3081                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3082                                                         near_call = TRUE;
3083                                         }
3084                                 }
3085                                 else if ((((guint64)data) >> 32) == 0) {
3086                                         near_call = TRUE;
3087                                         no_patch = TRUE;
3088                                 }
3089                         }
3090                 }
3091
3092                 if (cfg->method->dynamic)
3093                         /* These methods are allocated using malloc */
3094                         near_call = FALSE;
3095
3096 #ifdef MONO_ARCH_NOMAP32BIT
3097                 near_call = FALSE;
3098 #endif
3099 #if defined(__native_client__)
3100                 /* Always use near_call == TRUE for Native Client */
3101                 near_call = TRUE;
3102 #endif
3103                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3104                 if (optimize_for_xen)
3105                         near_call = FALSE;
3106
3107                 if (cfg->compile_aot) {
3108                         near_call = TRUE;
3109                         no_patch = TRUE;
3110                 }
3111
3112                 if (near_call) {
3113                         /*
3114                          * Align the call displacement to an address divisible by 4 so it does
3115                          * not span cache lines. This is required for code patching to work on SMP
3116                          * systems.
3117                          */
3118                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3119                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3120                                 amd64_padding (code, pad_size);
3121                         }
3122                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3123                         amd64_call_code (code, 0);
3124                 }
3125                 else {
3126                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3127                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3128                         amd64_call_reg (code, GP_SCRATCH_REG);
3129                 }
3130         }
3131
3132         return code;
3133 }
3134
3135 static inline guint8*
3136 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3137 {
3138 #ifdef TARGET_WIN32
3139         if (win64_adjust_stack)
3140                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3141 #endif
3142         code = emit_call_body (cfg, code, patch_type, data);
3143 #ifdef TARGET_WIN32
3144         if (win64_adjust_stack)
3145                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3146 #endif
3147
3148         return code;
3149 }
3150
3151 static inline int
3152 store_membase_imm_to_store_membase_reg (int opcode)
3153 {
3154         switch (opcode) {
3155         case OP_STORE_MEMBASE_IMM:
3156                 return OP_STORE_MEMBASE_REG;
3157         case OP_STOREI4_MEMBASE_IMM:
3158                 return OP_STOREI4_MEMBASE_REG;
3159         case OP_STOREI8_MEMBASE_IMM:
3160                 return OP_STOREI8_MEMBASE_REG;
3161         }
3162
3163         return -1;
3164 }
3165
3166 #ifndef DISABLE_JIT
3167
3168 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3169
3170 /*
3171  * mono_arch_peephole_pass_1:
3172  *
3173  *   Perform peephole opts which should/can be performed before local regalloc
3174  */
3175 void
3176 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3177 {
3178         MonoInst *ins, *n;
3179
3180         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3181                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3182
3183                 switch (ins->opcode) {
3184                 case OP_ADD_IMM:
3185                 case OP_IADD_IMM:
3186                 case OP_LADD_IMM:
3187                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3188                                 /*
3189                                  * X86_LEA is like ADD, but doesn't have the
3190                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3191                                  * its operand to 64 bit.
3192                                  */
3193                                 ins->opcode = OP_X86_LEA_MEMBASE;
3194                                 ins->inst_basereg = ins->sreg1;
3195                         }
3196                         break;
3197                 case OP_LXOR:
3198                 case OP_IXOR:
3199                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3200                                 MonoInst *ins2;
3201
3202                                 /*
3203                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3204                                  * the latter has length 2-3 instead of 6 (reverse constant
3205                                  * propagation). These instruction sequences are very common
3206                                  * in the initlocals bblock.
3207                                  */
3208                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3209                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3210                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3211                                                 ins2->sreg1 = ins->dreg;
3212                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3213                                                 /* Continue */
3214                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3215                                                 NULLIFY_INS (ins2);
3216                                                 /* Continue */
3217                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3218                                                 /* Continue */
3219                                         } else {
3220                                                 break;
3221                                         }
3222                                 }
3223                         }
3224                         break;
3225                 case OP_COMPARE_IMM:
3226                 case OP_LCOMPARE_IMM:
3227                         /* OP_COMPARE_IMM (reg, 0)
3228                          * -->
3229                          * OP_AMD64_TEST_NULL (reg)
3230                          */
3231                         if (!ins->inst_imm)
3232                                 ins->opcode = OP_AMD64_TEST_NULL;
3233                         break;
3234                 case OP_ICOMPARE_IMM:
3235                         if (!ins->inst_imm)
3236                                 ins->opcode = OP_X86_TEST_NULL;
3237                         break;
3238                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3239                         /*
3240                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3241                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3242                          * -->
3243                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3244                          * OP_COMPARE_IMM reg, imm
3245                          *
3246                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3247                          */
3248                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3249                             ins->inst_basereg == last_ins->inst_destbasereg &&
3250                             ins->inst_offset == last_ins->inst_offset) {
3251                                         ins->opcode = OP_ICOMPARE_IMM;
3252                                         ins->sreg1 = last_ins->sreg1;
3253
3254                                         /* check if we can remove cmp reg,0 with test null */
3255                                         if (!ins->inst_imm)
3256                                                 ins->opcode = OP_X86_TEST_NULL;
3257                                 }
3258
3259                         break;
3260                 }
3261
3262                 mono_peephole_ins (bb, ins);
3263         }
3264 }
3265
3266 void
3267 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3268 {
3269         MonoInst *ins, *n;
3270
3271         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3272                 switch (ins->opcode) {
3273                 case OP_ICONST:
3274                 case OP_I8CONST: {
3275                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3276                         /* reg = 0 -> XOR (reg, reg) */
3277                         /* XOR sets cflags on x86, so we cant do it always */
3278                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3279                                 ins->opcode = OP_LXOR;
3280                                 ins->sreg1 = ins->dreg;
3281                                 ins->sreg2 = ins->dreg;
3282                                 /* Fall through */
3283                         } else {
3284                                 break;
3285                         }
3286                 }
3287                 case OP_LXOR:
3288                         /*
3289                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3290                          * 0 result into 64 bits.
3291                          */
3292                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3293                                 ins->opcode = OP_IXOR;
3294                         }
3295                         /* Fall through */
3296                 case OP_IXOR:
3297                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3298                                 MonoInst *ins2;
3299
3300                                 /*
3301                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3302                                  * the latter has length 2-3 instead of 6 (reverse constant
3303                                  * propagation). These instruction sequences are very common
3304                                  * in the initlocals bblock.
3305                                  */
3306                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3307                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3308                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3309                                                 ins2->sreg1 = ins->dreg;
3310                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3311                                                 /* Continue */
3312                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3313                                                 NULLIFY_INS (ins2);
3314                                                 /* Continue */
3315                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3316                                                 /* Continue */
3317                                         } else {
3318                                                 break;
3319                                         }
3320                                 }
3321                         }
3322                         break;
3323                 case OP_IADD_IMM:
3324                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3325                                 ins->opcode = OP_X86_INC_REG;
3326                         break;
3327                 case OP_ISUB_IMM:
3328                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3329                                 ins->opcode = OP_X86_DEC_REG;
3330                         break;
3331                 }
3332
3333                 mono_peephole_ins (bb, ins);
3334         }
3335 }
3336
3337 #define NEW_INS(cfg,ins,dest,op) do {   \
3338                 MONO_INST_NEW ((cfg), (dest), (op)); \
3339         (dest)->cil_code = (ins)->cil_code; \
3340         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3341         } while (0)
3342
3343 /*
3344  * mono_arch_lowering_pass:
3345  *
3346  *  Converts complex opcodes into simpler ones so that each IR instruction
3347  * corresponds to one machine instruction.
3348  */
3349 void
3350 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3351 {
3352         MonoInst *ins, *n, *temp;
3353
3354         /*
3355          * FIXME: Need to add more instructions, but the current machine
3356          * description can't model some parts of the composite instructions like
3357          * cdq.
3358          */
3359         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3360                 switch (ins->opcode) {
3361                 case OP_DIV_IMM:
3362                 case OP_REM_IMM:
3363                 case OP_IDIV_IMM:
3364                 case OP_IDIV_UN_IMM:
3365                 case OP_IREM_UN_IMM:
3366                 case OP_LREM_IMM:
3367                 case OP_IREM_IMM:
3368                         mono_decompose_op_imm (cfg, bb, ins);
3369                         break;
3370                 case OP_COMPARE_IMM:
3371                 case OP_LCOMPARE_IMM:
3372                         if (!amd64_use_imm32 (ins->inst_imm)) {
3373                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3374                                 temp->inst_c0 = ins->inst_imm;
3375                                 temp->dreg = mono_alloc_ireg (cfg);
3376                                 ins->opcode = OP_COMPARE;
3377                                 ins->sreg2 = temp->dreg;
3378                         }
3379                         break;
3380 #ifndef __mono_ilp32__
3381                 case OP_LOAD_MEMBASE:
3382 #endif
3383                 case OP_LOADI8_MEMBASE:
3384 #ifndef __native_client_codegen__
3385                 /*  Don't generate memindex opcodes (to simplify */
3386                 /*  read sandboxing) */
3387                         if (!amd64_use_imm32 (ins->inst_offset)) {
3388                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3389                                 temp->inst_c0 = ins->inst_offset;
3390                                 temp->dreg = mono_alloc_ireg (cfg);
3391                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3392                                 ins->inst_indexreg = temp->dreg;
3393                         }
3394 #endif
3395                         break;
3396 #ifndef __mono_ilp32__
3397                 case OP_STORE_MEMBASE_IMM:
3398 #endif
3399                 case OP_STOREI8_MEMBASE_IMM:
3400                         if (!amd64_use_imm32 (ins->inst_imm)) {
3401                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3402                                 temp->inst_c0 = ins->inst_imm;
3403                                 temp->dreg = mono_alloc_ireg (cfg);
3404                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3405                                 ins->sreg1 = temp->dreg;
3406                         }
3407                         break;
3408 #ifdef MONO_ARCH_SIMD_INTRINSICS
3409                 case OP_EXPAND_I1: {
3410                                 int temp_reg1 = mono_alloc_ireg (cfg);
3411                                 int temp_reg2 = mono_alloc_ireg (cfg);
3412                                 int original_reg = ins->sreg1;
3413
3414                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3415                                 temp->sreg1 = original_reg;
3416                                 temp->dreg = temp_reg1;
3417
3418                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3419                                 temp->sreg1 = temp_reg1;
3420                                 temp->dreg = temp_reg2;
3421                                 temp->inst_imm = 8;
3422
3423                                 NEW_INS (cfg, ins, temp, OP_LOR);
3424                                 temp->sreg1 = temp->dreg = temp_reg2;
3425                                 temp->sreg2 = temp_reg1;
3426
3427                                 ins->opcode = OP_EXPAND_I2;
3428                                 ins->sreg1 = temp_reg2;
3429                         }
3430                         break;
3431 #endif
3432                 default:
3433                         break;
3434                 }
3435         }
3436
3437         bb->max_vreg = cfg->next_vreg;
3438 }
3439
3440 static const int
3441 branch_cc_table [] = {
3442         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3443         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3444         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3445 };
3446
3447 /* Maps CMP_... constants to X86_CC_... constants */
3448 static const int
3449 cc_table [] = {
3450         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3451         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3452 };
3453
3454 static const int
3455 cc_signed_table [] = {
3456         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3457         FALSE, FALSE, FALSE, FALSE
3458 };
3459
3460 /*#include "cprop.c"*/
3461
3462 static unsigned char*
3463 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3464 {
3465         if (size == 8)
3466                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3467         else
3468                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3469
3470         if (size == 1)
3471                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3472         else if (size == 2)
3473                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3474         return code;
3475 }
3476
3477 static unsigned char*
3478 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3479 {
3480         int sreg = tree->sreg1;
3481         int need_touch = FALSE;
3482
3483 #if defined(TARGET_WIN32)
3484         need_touch = TRUE;
3485 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3486         if (!tree->flags & MONO_INST_INIT)
3487                 need_touch = TRUE;
3488 #endif
3489
3490         if (need_touch) {
3491                 guint8* br[5];
3492
3493                 /*
3494                  * Under Windows:
3495                  * If requested stack size is larger than one page,
3496                  * perform stack-touch operation
3497                  */
3498                 /*
3499                  * Generate stack probe code.
3500                  * Under Windows, it is necessary to allocate one page at a time,
3501                  * "touching" stack after each successful sub-allocation. This is
3502                  * because of the way stack growth is implemented - there is a
3503                  * guard page before the lowest stack page that is currently commited.
3504                  * Stack normally grows sequentially so OS traps access to the
3505                  * guard page and commits more pages when needed.
3506                  */
3507                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3508                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3509
3510                 br[2] = code; /* loop */
3511                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3512                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3513                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3514                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3515                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3516                 amd64_patch (br[3], br[2]);
3517                 amd64_test_reg_reg (code, sreg, sreg);
3518                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3519                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3520
3521                 br[1] = code; x86_jump8 (code, 0);
3522
3523                 amd64_patch (br[0], code);
3524                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3525                 amd64_patch (br[1], code);
3526                 amd64_patch (br[4], code);
3527         }
3528         else
3529                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3530
3531         if (tree->flags & MONO_INST_INIT) {
3532                 int offset = 0;
3533                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3534                         amd64_push_reg (code, AMD64_RAX);
3535                         offset += 8;
3536                 }
3537                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3538                         amd64_push_reg (code, AMD64_RCX);
3539                         offset += 8;
3540                 }
3541                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3542                         amd64_push_reg (code, AMD64_RDI);
3543                         offset += 8;
3544                 }
3545
3546                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3547                 if (sreg != AMD64_RCX)
3548                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3549                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3550
3551                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3552                 if (cfg->param_area)
3553                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3554                 amd64_cld (code);
3555 #if defined(__default_codegen__)
3556                 amd64_prefix (code, X86_REP_PREFIX);
3557                 amd64_stosl (code);
3558 #elif defined(__native_client_codegen__)
3559                 /* NaCl stos pseudo-instruction */
3560                 amd64_codegen_pre(code);
3561                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3562                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3563                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3564                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3565                 amd64_prefix (code, X86_REP_PREFIX);
3566                 amd64_stosl (code);
3567                 amd64_codegen_post(code);
3568 #endif /* __native_client_codegen__ */
3569
3570                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3571                         amd64_pop_reg (code, AMD64_RDI);
3572                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3573                         amd64_pop_reg (code, AMD64_RCX);
3574                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3575                         amd64_pop_reg (code, AMD64_RAX);
3576         }
3577         return code;
3578 }
3579
3580 static guint8*
3581 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3582 {
3583         CallInfo *cinfo;
3584         guint32 quad;
3585
3586         /* Move return value to the target register */
3587         /* FIXME: do this in the local reg allocator */
3588         switch (ins->opcode) {
3589         case OP_CALL:
3590         case OP_CALL_REG:
3591         case OP_CALL_MEMBASE:
3592         case OP_LCALL:
3593         case OP_LCALL_REG:
3594         case OP_LCALL_MEMBASE:
3595                 g_assert (ins->dreg == AMD64_RAX);
3596                 break;
3597         case OP_FCALL:
3598         case OP_FCALL_REG:
3599         case OP_FCALL_MEMBASE: {
3600                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3601                 if (rtype->type == MONO_TYPE_R4) {
3602                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3603                 }
3604                 else {
3605                         if (ins->dreg != AMD64_XMM0)
3606                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3607                 }
3608                 break;
3609         }
3610         case OP_RCALL:
3611         case OP_RCALL_REG:
3612         case OP_RCALL_MEMBASE:
3613                 if (ins->dreg != AMD64_XMM0)
3614                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3615                 break;
3616         case OP_VCALL:
3617         case OP_VCALL_REG:
3618         case OP_VCALL_MEMBASE:
3619         case OP_VCALL2:
3620         case OP_VCALL2_REG:
3621         case OP_VCALL2_MEMBASE:
3622                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3623                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3624                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3625
3626                         /* Load the destination address */
3627                         g_assert (loc->opcode == OP_REGOFFSET);
3628                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3629
3630                         for (quad = 0; quad < 2; quad ++) {
3631                                 switch (cinfo->ret.pair_storage [quad]) {
3632                                 case ArgInIReg:
3633                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3634                                         break;
3635                                 case ArgInFloatSSEReg:
3636                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3637                                         break;
3638                                 case ArgInDoubleSSEReg:
3639                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3640                                         break;
3641                                 case ArgNone:
3642                                         break;
3643                                 default:
3644                                         NOT_IMPLEMENTED;
3645                                 }
3646                         }
3647                 }
3648                 break;
3649         }
3650
3651         return code;
3652 }
3653
3654 #endif /* DISABLE_JIT */
3655
3656 #ifdef __APPLE__
3657 static int tls_gs_offset;
3658 #endif
3659
3660 gboolean
3661 mono_amd64_have_tls_get (void)
3662 {
3663 #ifdef TARGET_MACH
3664         static gboolean have_tls_get = FALSE;
3665         static gboolean inited = FALSE;
3666
3667         if (inited)
3668                 return have_tls_get;
3669
3670 #if MONO_HAVE_FAST_TLS
3671         guint8 *ins = (guint8*)pthread_getspecific;
3672
3673         /*
3674          * We're looking for these two instructions:
3675          *
3676          * mov    %gs:[offset](,%rdi,8),%rax
3677          * retq
3678          */
3679         have_tls_get = ins [0] == 0x65 &&
3680                        ins [1] == 0x48 &&
3681                        ins [2] == 0x8b &&
3682                        ins [3] == 0x04 &&
3683                        ins [4] == 0xfd &&
3684                        ins [6] == 0x00 &&
3685                        ins [7] == 0x00 &&
3686                        ins [8] == 0x00 &&
3687                        ins [9] == 0xc3;
3688
3689         tls_gs_offset = ins[5];
3690
3691         /*
3692          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3693          * For that version we're looking for these instructions:
3694          *
3695          * pushq  %rbp
3696          * movq   %rsp, %rbp
3697          * mov    %gs:[offset](,%rdi,8),%rax
3698          * popq   %rbp
3699          * retq
3700          */
3701         if (!have_tls_get) {
3702                 have_tls_get = ins [0] == 0x55 &&
3703                                ins [1] == 0x48 &&
3704                                ins [2] == 0x89 &&
3705                                ins [3] == 0xe5 &&
3706                                ins [4] == 0x65 &&
3707                                ins [5] == 0x48 &&
3708                                ins [6] == 0x8b &&
3709                                ins [7] == 0x04 &&
3710                                ins [8] == 0xfd &&
3711                                ins [10] == 0x00 &&
3712                                ins [11] == 0x00 &&
3713                                ins [12] == 0x00 &&
3714                                ins [13] == 0x5d &&
3715                                ins [14] == 0xc3;
3716
3717                 tls_gs_offset = ins[9];
3718         }
3719 #endif
3720
3721         inited = TRUE;
3722
3723         return have_tls_get;
3724 #elif defined(TARGET_ANDROID)
3725         return FALSE;
3726 #else
3727         return TRUE;
3728 #endif
3729 }
3730
3731 int
3732 mono_amd64_get_tls_gs_offset (void)
3733 {
3734 #ifdef TARGET_OSX
3735         return tls_gs_offset;
3736 #else
3737         g_assert_not_reached ();
3738         return -1;
3739 #endif
3740 }
3741
3742 /*
3743  * mono_amd64_emit_tls_get:
3744  * @code: buffer to store code to
3745  * @dreg: hard register where to place the result
3746  * @tls_offset: offset info
3747  *
3748  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3749  * the dreg register the item in the thread local storage identified
3750  * by tls_offset.
3751  *
3752  * Returns: a pointer to the end of the stored code
3753  */
3754 guint8*
3755 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3756 {
3757 #ifdef TARGET_WIN32
3758         if (tls_offset < 64) {
3759                 x86_prefix (code, X86_GS_PREFIX);
3760                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3761         } else {
3762                 guint8 *buf [16];
3763
3764                 g_assert (tls_offset < 0x440);
3765                 /* Load TEB->TlsExpansionSlots */
3766                 x86_prefix (code, X86_GS_PREFIX);
3767                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3768                 amd64_test_reg_reg (code, dreg, dreg);
3769                 buf [0] = code;
3770                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3771                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3772                 amd64_patch (buf [0], code);
3773         }
3774 #elif defined(__APPLE__)
3775         x86_prefix (code, X86_GS_PREFIX);
3776         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3777 #else
3778         if (optimize_for_xen) {
3779                 x86_prefix (code, X86_FS_PREFIX);
3780                 amd64_mov_reg_mem (code, dreg, 0, 8);
3781                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3782         } else {
3783                 x86_prefix (code, X86_FS_PREFIX);
3784                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3785         }
3786 #endif
3787         return code;
3788 }
3789
3790 static guint8*
3791 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3792 {
3793         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3794 #ifdef TARGET_OSX
3795         if (dreg != offset_reg)
3796                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3797         amd64_prefix (code, X86_GS_PREFIX);
3798         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3799 #elif defined(__linux__)
3800         int tmpreg = -1;
3801
3802         if (dreg == offset_reg) {
3803                 /* Use a temporary reg by saving it to the redzone */
3804                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3805                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3806                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3807                 offset_reg = tmpreg;
3808         }
3809         x86_prefix (code, X86_FS_PREFIX);
3810         amd64_mov_reg_mem (code, dreg, 0, 8);
3811         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3812         if (tmpreg != -1)
3813                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3814 #else
3815         g_assert_not_reached ();
3816 #endif
3817         return code;
3818 }
3819
3820 static guint8*
3821 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3822 {
3823 #ifdef TARGET_WIN32
3824         g_assert_not_reached ();
3825 #elif defined(__APPLE__)
3826         x86_prefix (code, X86_GS_PREFIX);
3827         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3828 #else
3829         g_assert (!optimize_for_xen);
3830         x86_prefix (code, X86_FS_PREFIX);
3831         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3832 #endif
3833         return code;
3834 }
3835
3836 static guint8*
3837 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3838 {
3839         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3840 #ifdef TARGET_WIN32
3841         g_assert_not_reached ();
3842 #elif defined(__APPLE__)
3843         x86_prefix (code, X86_GS_PREFIX);
3844         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3845 #else
3846         x86_prefix (code, X86_FS_PREFIX);
3847         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3848 #endif
3849         return code;
3850 }
3851
3852  /*
3853  * mono_arch_translate_tls_offset:
3854  *
3855  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3856  */
3857 int
3858 mono_arch_translate_tls_offset (int offset)
3859 {
3860 #ifdef __APPLE__
3861         return tls_gs_offset + (offset * 8);
3862 #else
3863         return offset;
3864 #endif
3865 }
3866
3867 /*
3868  * emit_setup_lmf:
3869  *
3870  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3871  */
3872 static guint8*
3873 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3874 {
3875         /*
3876          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3877          */
3878         /*
3879          * sp is saved right before calls but we need to save it here too so
3880          * async stack walks would work.
3881          */
3882         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3883         /* Save rbp */
3884         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3885         if (cfg->arch.omit_fp && cfa_offset != -1)
3886                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3887
3888         /* These can't contain refs */
3889         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3890         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3891         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3892         /* These are handled automatically by the stack marking code */
3893         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3894
3895         return code;
3896 }
3897
3898 #define REAL_PRINT_REG(text,reg) \
3899 mono_assert (reg >= 0); \
3900 amd64_push_reg (code, AMD64_RAX); \
3901 amd64_push_reg (code, AMD64_RDX); \
3902 amd64_push_reg (code, AMD64_RCX); \
3903 amd64_push_reg (code, reg); \
3904 amd64_push_imm (code, reg); \
3905 amd64_push_imm (code, text " %d %p\n"); \
3906 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3907 amd64_call_reg (code, AMD64_RAX); \
3908 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3909 amd64_pop_reg (code, AMD64_RCX); \
3910 amd64_pop_reg (code, AMD64_RDX); \
3911 amd64_pop_reg (code, AMD64_RAX);
3912
3913 /* benchmark and set based on cpu */
3914 #define LOOP_ALIGNMENT 8
3915 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3916
3917 #ifndef DISABLE_JIT
3918 void
3919 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3920 {
3921         MonoInst *ins;
3922         MonoCallInst *call;
3923         guint offset;
3924         guint8 *code = cfg->native_code + cfg->code_len;
3925         int max_len;
3926
3927         /* Fix max_offset estimate for each successor bb */
3928         if (cfg->opt & MONO_OPT_BRANCH) {
3929                 int current_offset = cfg->code_len;
3930                 MonoBasicBlock *current_bb;
3931                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3932                         current_bb->max_offset = current_offset;
3933                         current_offset += current_bb->max_length;
3934                 }
3935         }
3936
3937         if (cfg->opt & MONO_OPT_LOOP) {
3938                 int pad, align = LOOP_ALIGNMENT;
3939                 /* set alignment depending on cpu */
3940                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3941                         pad = align - pad;
3942                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3943                         amd64_padding (code, pad);
3944                         cfg->code_len += pad;
3945                         bb->native_offset = cfg->code_len;
3946                 }
3947         }
3948
3949 #if defined(__native_client_codegen__)
3950         /* For Native Client, all indirect call/jump targets must be */
3951         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3952         /* indirectly as well.                                       */
3953         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3954                                       (bb->flags & BB_EXCEPTION_HANDLER);
3955
3956         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3957                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3958                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3959                 cfg->code_len += pad;
3960                 bb->native_offset = cfg->code_len;
3961         }
3962 #endif  /*__native_client_codegen__*/
3963
3964         if (cfg->verbose_level > 2)
3965                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3966
3967         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3968                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3969                 g_assert (!cfg->compile_aot);
3970
3971                 cov->data [bb->dfn].cil_code = bb->cil_code;
3972                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3973                 /* this is not thread save, but good enough */
3974                 amd64_inc_membase (code, AMD64_R11, 0);
3975         }
3976
3977         offset = code - cfg->native_code;
3978
3979         mono_debug_open_block (cfg, bb, offset);
3980
3981     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3982                 x86_breakpoint (code);
3983
3984         MONO_BB_FOR_EACH_INS (bb, ins) {
3985                 offset = code - cfg->native_code;
3986
3987                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3988
3989 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3990
3991                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3992                         cfg->code_size *= 2;
3993                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3994                         code = cfg->native_code + offset;
3995                         cfg->stat_code_reallocs++;
3996                 }
3997
3998                 if (cfg->debug_info)
3999                         mono_debug_record_line_number (cfg, ins, offset);
4000
4001                 switch (ins->opcode) {
4002                 case OP_BIGMUL:
4003                         amd64_mul_reg (code, ins->sreg2, TRUE);
4004                         break;
4005                 case OP_BIGMUL_UN:
4006                         amd64_mul_reg (code, ins->sreg2, FALSE);
4007                         break;
4008                 case OP_X86_SETEQ_MEMBASE:
4009                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
4010                         break;
4011                 case OP_STOREI1_MEMBASE_IMM:
4012                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
4013                         break;
4014                 case OP_STOREI2_MEMBASE_IMM:
4015                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
4016                         break;
4017                 case OP_STOREI4_MEMBASE_IMM:
4018                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
4019                         break;
4020                 case OP_STOREI1_MEMBASE_REG:
4021                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4022                         break;
4023                 case OP_STOREI2_MEMBASE_REG:
4024                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4025                         break;
4026                 /* In AMD64 NaCl, pointers are 4 bytes, */
4027                 /*  so STORE_* != STOREI8_*. Likewise below. */
4028                 case OP_STORE_MEMBASE_REG:
4029                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4030                         break;
4031                 case OP_STOREI8_MEMBASE_REG:
4032                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4033                         break;
4034                 case OP_STOREI4_MEMBASE_REG:
4035                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4036                         break;
4037                 case OP_STORE_MEMBASE_IMM:
4038 #ifndef __native_client_codegen__
4039                         /* In NaCl, this could be a PCONST type, which could */
4040                         /* mean a pointer type was copied directly into the  */
4041                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4042                         /* the value would be 0x00000000FFFFFFFF which is    */
4043                         /* not proper for an imm32 unless you cast it.       */
4044                         g_assert (amd64_is_imm32 (ins->inst_imm));
4045 #endif
4046                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4047                         break;
4048                 case OP_STOREI8_MEMBASE_IMM:
4049                         g_assert (amd64_is_imm32 (ins->inst_imm));
4050                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4051                         break;
4052                 case OP_LOAD_MEM:
4053 #ifdef __mono_ilp32__
4054                         /* In ILP32, pointers are 4 bytes, so separate these */
4055                         /* cases, use literal 8 below where we really want 8 */
4056                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4057                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4058                         break;
4059 #endif
4060                 case OP_LOADI8_MEM:
4061                         // FIXME: Decompose this earlier
4062                         if (amd64_use_imm32 (ins->inst_imm))
4063                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4064                         else {
4065                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4066                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4067                         }
4068                         break;
4069                 case OP_LOADI4_MEM:
4070                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4071                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4072                         break;
4073                 case OP_LOADU4_MEM:
4074                         // FIXME: Decompose this earlier
4075                         if (amd64_use_imm32 (ins->inst_imm))
4076                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4077                         else {
4078                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4079                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4080                         }
4081                         break;
4082                 case OP_LOADU1_MEM:
4083                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4084                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4085                         break;
4086                 case OP_LOADU2_MEM:
4087                         /* For NaCl, pointers are 4 bytes, so separate these */
4088                         /* cases, use literal 8 below where we really want 8 */
4089                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4090                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4091                         break;
4092                 case OP_LOAD_MEMBASE:
4093                         g_assert (amd64_is_imm32 (ins->inst_offset));
4094                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4095                         break;
4096                 case OP_LOADI8_MEMBASE:
4097                         /* Use literal 8 instead of sizeof pointer or */
4098                         /* register, we really want 8 for this opcode */
4099                         g_assert (amd64_is_imm32 (ins->inst_offset));
4100                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4101                         break;
4102                 case OP_LOADI4_MEMBASE:
4103                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4104                         break;
4105                 case OP_LOADU4_MEMBASE:
4106                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4107                         break;
4108                 case OP_LOADU1_MEMBASE:
4109                         /* The cpu zero extends the result into 64 bits */
4110                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4111                         break;
4112                 case OP_LOADI1_MEMBASE:
4113                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4114                         break;
4115                 case OP_LOADU2_MEMBASE:
4116                         /* The cpu zero extends the result into 64 bits */
4117                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4118                         break;
4119                 case OP_LOADI2_MEMBASE:
4120                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4121                         break;
4122                 case OP_AMD64_LOADI8_MEMINDEX:
4123                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4124                         break;
4125                 case OP_LCONV_TO_I1:
4126                 case OP_ICONV_TO_I1:
4127                 case OP_SEXT_I1:
4128                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4129                         break;
4130                 case OP_LCONV_TO_I2:
4131                 case OP_ICONV_TO_I2:
4132                 case OP_SEXT_I2:
4133                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4134                         break;
4135                 case OP_LCONV_TO_U1:
4136                 case OP_ICONV_TO_U1:
4137                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4138                         break;
4139                 case OP_LCONV_TO_U2:
4140                 case OP_ICONV_TO_U2:
4141                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4142                         break;
4143                 case OP_ZEXT_I4:
4144                         /* Clean out the upper word */
4145                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4146                         break;
4147                 case OP_SEXT_I4:
4148                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4149                         break;
4150                 case OP_COMPARE:
4151                 case OP_LCOMPARE:
4152                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4153                         break;
4154                 case OP_COMPARE_IMM:
4155 #if defined(__mono_ilp32__)
4156                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4157                         g_assert (amd64_is_imm32 (ins->inst_imm));
4158                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4159                         break;
4160 #endif
4161                 case OP_LCOMPARE_IMM:
4162                         g_assert (amd64_is_imm32 (ins->inst_imm));
4163                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4164                         break;
4165                 case OP_X86_COMPARE_REG_MEMBASE:
4166                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4167                         break;
4168                 case OP_X86_TEST_NULL:
4169                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4170                         break;
4171                 case OP_AMD64_TEST_NULL:
4172                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4173                         break;
4174
4175                 case OP_X86_ADD_REG_MEMBASE:
4176                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4177                         break;
4178                 case OP_X86_SUB_REG_MEMBASE:
4179                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4180                         break;
4181                 case OP_X86_AND_REG_MEMBASE:
4182                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4183                         break;
4184                 case OP_X86_OR_REG_MEMBASE:
4185                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4186                         break;
4187                 case OP_X86_XOR_REG_MEMBASE:
4188                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4189                         break;
4190
4191                 case OP_X86_ADD_MEMBASE_IMM:
4192                         /* FIXME: Make a 64 version too */
4193                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4194                         break;
4195                 case OP_X86_SUB_MEMBASE_IMM:
4196                         g_assert (amd64_is_imm32 (ins->inst_imm));
4197                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4198                         break;
4199                 case OP_X86_AND_MEMBASE_IMM:
4200                         g_assert (amd64_is_imm32 (ins->inst_imm));
4201                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4202                         break;
4203                 case OP_X86_OR_MEMBASE_IMM:
4204                         g_assert (amd64_is_imm32 (ins->inst_imm));
4205                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4206                         break;
4207                 case OP_X86_XOR_MEMBASE_IMM:
4208                         g_assert (amd64_is_imm32 (ins->inst_imm));
4209                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4210                         break;
4211                 case OP_X86_ADD_MEMBASE_REG:
4212                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4213                         break;
4214                 case OP_X86_SUB_MEMBASE_REG:
4215                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4216                         break;
4217                 case OP_X86_AND_MEMBASE_REG:
4218                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4219                         break;
4220                 case OP_X86_OR_MEMBASE_REG:
4221                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4222                         break;
4223                 case OP_X86_XOR_MEMBASE_REG:
4224                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4225                         break;
4226                 case OP_X86_INC_MEMBASE:
4227                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4228                         break;
4229                 case OP_X86_INC_REG:
4230                         amd64_inc_reg_size (code, ins->dreg, 4);
4231                         break;
4232                 case OP_X86_DEC_MEMBASE:
4233                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4234                         break;
4235                 case OP_X86_DEC_REG:
4236                         amd64_dec_reg_size (code, ins->dreg, 4);
4237                         break;
4238                 case OP_X86_MUL_REG_MEMBASE:
4239                 case OP_X86_MUL_MEMBASE_REG:
4240                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4241                         break;
4242                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4243                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4244                         break;
4245                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4246                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4247                         break;
4248                 case OP_AMD64_COMPARE_MEMBASE_REG:
4249                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4250                         break;
4251                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4252                         g_assert (amd64_is_imm32 (ins->inst_imm));
4253                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4254                         break;
4255                 case OP_X86_COMPARE_MEMBASE8_IMM:
4256                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4257                         break;
4258                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4259                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4260                         break;
4261                 case OP_AMD64_COMPARE_REG_MEMBASE:
4262                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4263                         break;
4264
4265                 case OP_AMD64_ADD_REG_MEMBASE:
4266                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4267                         break;
4268                 case OP_AMD64_SUB_REG_MEMBASE:
4269                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4270                         break;
4271                 case OP_AMD64_AND_REG_MEMBASE:
4272                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4273                         break;
4274                 case OP_AMD64_OR_REG_MEMBASE:
4275                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4276                         break;
4277                 case OP_AMD64_XOR_REG_MEMBASE:
4278                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4279                         break;
4280
4281                 case OP_AMD64_ADD_MEMBASE_REG:
4282                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4283                         break;
4284                 case OP_AMD64_SUB_MEMBASE_REG:
4285                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4286                         break;
4287                 case OP_AMD64_AND_MEMBASE_REG:
4288                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4289                         break;
4290                 case OP_AMD64_OR_MEMBASE_REG:
4291                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4292                         break;
4293                 case OP_AMD64_XOR_MEMBASE_REG:
4294                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4295                         break;
4296
4297                 case OP_AMD64_ADD_MEMBASE_IMM:
4298                         g_assert (amd64_is_imm32 (ins->inst_imm));
4299                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4300                         break;
4301                 case OP_AMD64_SUB_MEMBASE_IMM:
4302                         g_assert (amd64_is_imm32 (ins->inst_imm));
4303                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4304                         break;
4305                 case OP_AMD64_AND_MEMBASE_IMM:
4306                         g_assert (amd64_is_imm32 (ins->inst_imm));
4307                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4308                         break;
4309                 case OP_AMD64_OR_MEMBASE_IMM:
4310                         g_assert (amd64_is_imm32 (ins->inst_imm));
4311                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4312                         break;
4313                 case OP_AMD64_XOR_MEMBASE_IMM:
4314                         g_assert (amd64_is_imm32 (ins->inst_imm));
4315                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4316                         break;
4317
4318                 case OP_BREAK:
4319                         amd64_breakpoint (code);
4320                         break;
4321                 case OP_RELAXED_NOP:
4322                         x86_prefix (code, X86_REP_PREFIX);
4323                         x86_nop (code);
4324                         break;
4325                 case OP_HARD_NOP:
4326                         x86_nop (code);
4327                         break;
4328                 case OP_NOP:
4329                 case OP_DUMMY_USE:
4330                 case OP_DUMMY_STORE:
4331                 case OP_DUMMY_ICONST:
4332                 case OP_DUMMY_R8CONST:
4333                 case OP_NOT_REACHED:
4334                 case OP_NOT_NULL:
4335                         break;
4336                 case OP_IL_SEQ_POINT:
4337                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4338                         break;
4339                 case OP_SEQ_POINT: {
4340                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4341                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4342                                 guint8 *label;
4343
4344                                 /* Load ss_tramp_var */
4345                                 /* This is equal to &ss_trampoline */
4346                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4347                                 /* Load the trampoline address */
4348                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4349                                 /* Call it if it is non-null */
4350                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4351                                 label = code;
4352                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4353                                 amd64_call_reg (code, AMD64_R11);
4354                                 amd64_patch (label, code);
4355                         }
4356
4357                         /*
4358                          * This is the address which is saved in seq points,
4359                          */
4360                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4361
4362                         if (cfg->compile_aot) {
4363                                 guint32 offset = code - cfg->native_code;
4364                                 guint32 val;
4365                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4366                                 guint8 *label;
4367
4368                                 /* Load info var */
4369                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4370                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4371                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4372                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4373                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4374                                 label = code;
4375                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4376                                 /* Call the trampoline */
4377                                 amd64_call_reg (code, AMD64_R11);
4378                                 amd64_patch (label, code);
4379                         } else {
4380                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4381                                 guint8 *label;
4382
4383                                 /*
4384                                  * Emit a test+branch against a constant, the constant will be overwritten
4385                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4386                                  */
4387                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4388                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4389                                 label = code;
4390                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4391
4392                                 g_assert (var);
4393                                 g_assert (var->opcode == OP_REGOFFSET);
4394                                 /* Load bp_tramp_var */
4395                                 /* This is equal to &bp_trampoline */
4396                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4397                                 /* Call the trampoline */
4398                                 amd64_call_membase (code, AMD64_R11, 0);
4399                                 amd64_patch (label, code);
4400                         }
4401                         /*
4402                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4403                          * to another IL offset.
4404                          */
4405                         x86_nop (code);
4406                         break;
4407                 }
4408                 case OP_ADDCC:
4409                 case OP_LADDCC:
4410                 case OP_LADD:
4411                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4412                         break;
4413                 case OP_ADC:
4414                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4415                         break;
4416                 case OP_ADD_IMM:
4417                 case OP_LADD_IMM:
4418                         g_assert (amd64_is_imm32 (ins->inst_imm));
4419                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4420                         break;
4421                 case OP_ADC_IMM:
4422                         g_assert (amd64_is_imm32 (ins->inst_imm));
4423                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4424                         break;
4425                 case OP_SUBCC:
4426                 case OP_LSUBCC:
4427                 case OP_LSUB:
4428                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4429                         break;
4430                 case OP_SBB:
4431                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4432                         break;
4433                 case OP_SUB_IMM:
4434                 case OP_LSUB_IMM:
4435                         g_assert (amd64_is_imm32 (ins->inst_imm));
4436                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4437                         break;
4438                 case OP_SBB_IMM:
4439                         g_assert (amd64_is_imm32 (ins->inst_imm));
4440                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4441                         break;
4442                 case OP_LAND:
4443                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4444                         break;
4445                 case OP_AND_IMM:
4446                 case OP_LAND_IMM:
4447                         g_assert (amd64_is_imm32 (ins->inst_imm));
4448                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4449                         break;
4450                 case OP_LMUL:
4451                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4452                         break;
4453                 case OP_MUL_IMM:
4454                 case OP_LMUL_IMM:
4455                 case OP_IMUL_IMM: {
4456                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4457
4458                         switch (ins->inst_imm) {
4459                         case 2:
4460                                 /* MOV r1, r2 */
4461                                 /* ADD r1, r1 */
4462                                 if (ins->dreg != ins->sreg1)
4463                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4464                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4465                                 break;
4466                         case 3:
4467                                 /* LEA r1, [r2 + r2*2] */
4468                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4469                                 break;
4470                         case 5:
4471                                 /* LEA r1, [r2 + r2*4] */
4472                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4473                                 break;
4474                         case 6:
4475                                 /* LEA r1, [r2 + r2*2] */
4476                                 /* ADD r1, r1          */
4477                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4478                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4479                                 break;
4480                         case 9:
4481                                 /* LEA r1, [r2 + r2*8] */
4482                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4483                                 break;
4484                         case 10:
4485                                 /* LEA r1, [r2 + r2*4] */
4486                                 /* ADD r1, r1          */
4487                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4488                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4489                                 break;
4490                         case 12:
4491                                 /* LEA r1, [r2 + r2*2] */
4492                                 /* SHL r1, 2           */
4493                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4494                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4495                                 break;
4496                         case 25:
4497                                 /* LEA r1, [r2 + r2*4] */
4498                                 /* LEA r1, [r1 + r1*4] */
4499                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4500                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4501                                 break;
4502                         case 100:
4503                                 /* LEA r1, [r2 + r2*4] */
4504                                 /* SHL r1, 2           */
4505                                 /* LEA r1, [r1 + r1*4] */
4506                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4507                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4508                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4509                                 break;
4510                         default:
4511                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4512                                 break;
4513                         }
4514                         break;
4515                 }
4516                 case OP_LDIV:
4517                 case OP_LREM:
4518 #if defined( __native_client_codegen__ )
4519                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4520                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4521 #endif
4522                         /* Regalloc magic makes the div/rem cases the same */
4523                         if (ins->sreg2 == AMD64_RDX) {
4524                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4525                                 amd64_cdq (code);
4526                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4527                         } else {
4528                                 amd64_cdq (code);
4529                                 amd64_div_reg (code, ins->sreg2, TRUE);
4530                         }
4531                         break;
4532                 case OP_LDIV_UN:
4533                 case OP_LREM_UN:
4534 #if defined( __native_client_codegen__ )
4535                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4536                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4537 #endif
4538                         if (ins->sreg2 == AMD64_RDX) {
4539                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4540                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4541                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4542                         } else {
4543                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4544                                 amd64_div_reg (code, ins->sreg2, FALSE);
4545                         }
4546                         break;
4547                 case OP_IDIV:
4548                 case OP_IREM:
4549 #if defined( __native_client_codegen__ )
4550                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4551                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4552 #endif
4553                         if (ins->sreg2 == AMD64_RDX) {
4554                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4555                                 amd64_cdq_size (code, 4);
4556                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4557                         } else {
4558                                 amd64_cdq_size (code, 4);
4559                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4560                         }
4561                         break;
4562                 case OP_IDIV_UN:
4563                 case OP_IREM_UN:
4564 #if defined( __native_client_codegen__ )
4565                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4566                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4567 #endif
4568                         if (ins->sreg2 == AMD64_RDX) {
4569                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4570                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4571                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4572                         } else {
4573                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4574                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4575                         }
4576                         break;
4577                 case OP_LMUL_OVF:
4578                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4579                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4580                         break;
4581                 case OP_LOR:
4582                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4583                         break;
4584                 case OP_OR_IMM:
4585                 case OP_LOR_IMM:
4586                         g_assert (amd64_is_imm32 (ins->inst_imm));
4587                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4588                         break;
4589                 case OP_LXOR:
4590                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4591                         break;
4592                 case OP_XOR_IMM:
4593                 case OP_LXOR_IMM:
4594                         g_assert (amd64_is_imm32 (ins->inst_imm));
4595                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4596                         break;
4597                 case OP_LSHL:
4598                         g_assert (ins->sreg2 == AMD64_RCX);
4599                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4600                         break;
4601                 case OP_LSHR:
4602                         g_assert (ins->sreg2 == AMD64_RCX);
4603                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4604                         break;
4605                 case OP_SHR_IMM:
4606                 case OP_LSHR_IMM:
4607                         g_assert (amd64_is_imm32 (ins->inst_imm));
4608                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4609                         break;
4610                 case OP_SHR_UN_IMM:
4611                         g_assert (amd64_is_imm32 (ins->inst_imm));
4612                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4613                         break;
4614                 case OP_LSHR_UN_IMM:
4615                         g_assert (amd64_is_imm32 (ins->inst_imm));
4616                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4617                         break;
4618                 case OP_LSHR_UN:
4619                         g_assert (ins->sreg2 == AMD64_RCX);
4620                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4621                         break;
4622                 case OP_SHL_IMM:
4623                 case OP_LSHL_IMM:
4624                         g_assert (amd64_is_imm32 (ins->inst_imm));
4625                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4626                         break;
4627
4628                 case OP_IADDCC:
4629                 case OP_IADD:
4630                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4631                         break;
4632                 case OP_IADC:
4633                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4634                         break;
4635                 case OP_IADD_IMM:
4636                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4637                         break;
4638                 case OP_IADC_IMM:
4639                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4640                         break;
4641                 case OP_ISUBCC:
4642                 case OP_ISUB:
4643                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4644                         break;
4645                 case OP_ISBB:
4646                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4647                         break;
4648                 case OP_ISUB_IMM:
4649                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4650                         break;
4651                 case OP_ISBB_IMM:
4652                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4653                         break;
4654                 case OP_IAND:
4655                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4656                         break;
4657                 case OP_IAND_IMM:
4658                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4659                         break;
4660                 case OP_IOR:
4661                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4662                         break;
4663                 case OP_IOR_IMM:
4664                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4665                         break;
4666                 case OP_IXOR:
4667                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4668                         break;
4669                 case OP_IXOR_IMM:
4670                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4671                         break;
4672                 case OP_INEG:
4673                         amd64_neg_reg_size (code, ins->sreg1, 4);
4674                         break;
4675                 case OP_INOT:
4676                         amd64_not_reg_size (code, ins->sreg1, 4);
4677                         break;
4678                 case OP_ISHL:
4679                         g_assert (ins->sreg2 == AMD64_RCX);
4680                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4681                         break;
4682                 case OP_ISHR:
4683                         g_assert (ins->sreg2 == AMD64_RCX);
4684                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4685                         break;
4686                 case OP_ISHR_IMM:
4687                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4688                         break;
4689                 case OP_ISHR_UN_IMM:
4690                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4691                         break;
4692                 case OP_ISHR_UN:
4693                         g_assert (ins->sreg2 == AMD64_RCX);
4694                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4695                         break;
4696                 case OP_ISHL_IMM:
4697                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4698                         break;
4699                 case OP_IMUL:
4700                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4701                         break;
4702                 case OP_IMUL_OVF:
4703                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4704                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4705                         break;
4706                 case OP_IMUL_OVF_UN:
4707                 case OP_LMUL_OVF_UN: {
4708                         /* the mul operation and the exception check should most likely be split */
4709                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4710                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4711                         /*g_assert (ins->sreg2 == X86_EAX);
4712                         g_assert (ins->dreg == X86_EAX);*/
4713                         if (ins->sreg2 == X86_EAX) {
4714                                 non_eax_reg = ins->sreg1;
4715                         } else if (ins->sreg1 == X86_EAX) {
4716                                 non_eax_reg = ins->sreg2;
4717                         } else {
4718                                 /* no need to save since we're going to store to it anyway */
4719                                 if (ins->dreg != X86_EAX) {
4720                                         saved_eax = TRUE;
4721                                         amd64_push_reg (code, X86_EAX);
4722                                 }
4723                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4724                                 non_eax_reg = ins->sreg2;
4725                         }
4726                         if (ins->dreg == X86_EDX) {
4727                                 if (!saved_eax) {
4728                                         saved_eax = TRUE;
4729                                         amd64_push_reg (code, X86_EAX);
4730                                 }
4731                         } else {
4732                                 saved_edx = TRUE;
4733                                 amd64_push_reg (code, X86_EDX);
4734                         }
4735                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4736                         /* save before the check since pop and mov don't change the flags */
4737                         if (ins->dreg != X86_EAX)
4738                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4739                         if (saved_edx)
4740                                 amd64_pop_reg (code, X86_EDX);
4741                         if (saved_eax)
4742                                 amd64_pop_reg (code, X86_EAX);
4743                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4744                         break;
4745                 }
4746                 case OP_ICOMPARE:
4747                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4748                         break;
4749                 case OP_ICOMPARE_IMM:
4750                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4751                         break;
4752                 case OP_IBEQ:
4753                 case OP_IBLT:
4754                 case OP_IBGT:
4755                 case OP_IBGE:
4756                 case OP_IBLE:
4757                 case OP_LBEQ:
4758                 case OP_LBLT:
4759                 case OP_LBGT:
4760                 case OP_LBGE:
4761                 case OP_LBLE:
4762                 case OP_IBNE_UN:
4763                 case OP_IBLT_UN:
4764                 case OP_IBGT_UN:
4765                 case OP_IBGE_UN:
4766                 case OP_IBLE_UN:
4767                 case OP_LBNE_UN:
4768                 case OP_LBLT_UN:
4769                 case OP_LBGT_UN:
4770                 case OP_LBGE_UN:
4771                 case OP_LBLE_UN:
4772                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4773                         break;
4774
4775                 case OP_CMOV_IEQ:
4776                 case OP_CMOV_IGE:
4777                 case OP_CMOV_IGT:
4778                 case OP_CMOV_ILE:
4779                 case OP_CMOV_ILT:
4780                 case OP_CMOV_INE_UN:
4781                 case OP_CMOV_IGE_UN:
4782                 case OP_CMOV_IGT_UN:
4783                 case OP_CMOV_ILE_UN:
4784                 case OP_CMOV_ILT_UN:
4785                 case OP_CMOV_LEQ:
4786                 case OP_CMOV_LGE:
4787                 case OP_CMOV_LGT:
4788                 case OP_CMOV_LLE:
4789                 case OP_CMOV_LLT:
4790                 case OP_CMOV_LNE_UN:
4791                 case OP_CMOV_LGE_UN:
4792                 case OP_CMOV_LGT_UN:
4793                 case OP_CMOV_LLE_UN:
4794                 case OP_CMOV_LLT_UN:
4795                         g_assert (ins->dreg == ins->sreg1);
4796                         /* This needs to operate on 64 bit values */
4797                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4798                         break;
4799
4800                 case OP_LNOT:
4801                         amd64_not_reg (code, ins->sreg1);
4802                         break;
4803                 case OP_LNEG:
4804                         amd64_neg_reg (code, ins->sreg1);
4805                         break;
4806
4807                 case OP_ICONST:
4808                 case OP_I8CONST:
4809                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4810                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4811                         else
4812                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4813                         break;
4814                 case OP_AOTCONST:
4815                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4816                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4817                         break;
4818                 case OP_JUMP_TABLE:
4819                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4820                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4821                         break;
4822                 case OP_MOVE:
4823                         if (ins->dreg != ins->sreg1)
4824                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4825                         break;
4826                 case OP_AMD64_SET_XMMREG_R4: {
4827                         if (cfg->r4fp) {
4828                                 if (ins->dreg != ins->sreg1)
4829                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4830                         } else {
4831                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4832                         }
4833                         break;
4834                 }
4835                 case OP_AMD64_SET_XMMREG_R8: {
4836                         if (ins->dreg != ins->sreg1)
4837                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4838                         break;
4839                 }
4840                 case OP_TAILCALL: {
4841                         MonoCallInst *call = (MonoCallInst*)ins;
4842                         int i, save_area_offset;
4843
4844                         g_assert (!cfg->method->save_lmf);
4845
4846                         /* Restore callee saved registers */
4847                         save_area_offset = cfg->arch.reg_save_area_offset;
4848                         for (i = 0; i < AMD64_NREG; ++i)
4849                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4850                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4851                                         save_area_offset += 8;
4852                                 }
4853
4854                         if (cfg->arch.omit_fp) {
4855                                 if (cfg->arch.stack_alloc_size)
4856                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4857                                 // FIXME:
4858                                 if (call->stack_usage)
4859                                         NOT_IMPLEMENTED;
4860                         } else {
4861                                 /* Copy arguments on the stack to our argument area */
4862                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4863                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4864                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4865                                 }
4866
4867                                 amd64_leave (code);
4868                         }
4869
4870                         offset = code - cfg->native_code;
4871                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4872                         if (cfg->compile_aot)
4873                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4874                         else
4875                                 amd64_set_reg_template (code, AMD64_R11);
4876                         amd64_jump_reg (code, AMD64_R11);
4877                         ins->flags |= MONO_INST_GC_CALLSITE;
4878                         ins->backend.pc_offset = code - cfg->native_code;
4879                         break;
4880                 }
4881                 case OP_CHECK_THIS:
4882                         /* ensure ins->sreg1 is not NULL */
4883                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4884                         break;
4885                 case OP_ARGLIST: {
4886                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4887                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4888                         break;
4889                 }
4890                 case OP_CALL:
4891                 case OP_FCALL:
4892                 case OP_RCALL:
4893                 case OP_LCALL:
4894                 case OP_VCALL:
4895                 case OP_VCALL2:
4896                 case OP_VOIDCALL:
4897                         call = (MonoCallInst*)ins;
4898                         /*
4899                          * The AMD64 ABI forces callers to know about varargs.
4900                          */
4901                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4902                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4903                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4904                                 /*
4905                                  * Since the unmanaged calling convention doesn't contain a
4906                                  * 'vararg' entry, we have to treat every pinvoke call as a
4907                                  * potential vararg call.
4908                                  */
4909                                 guint32 nregs, i;
4910                                 nregs = 0;
4911                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4912                                         if (call->used_fregs & (1 << i))
4913                                                 nregs ++;
4914                                 if (!nregs)
4915                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4916                                 else
4917                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4918                         }
4919
4920                         if (ins->flags & MONO_INST_HAS_METHOD)
4921                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4922                         else
4923                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4924                         ins->flags |= MONO_INST_GC_CALLSITE;
4925                         ins->backend.pc_offset = code - cfg->native_code;
4926                         code = emit_move_return_value (cfg, ins, code);
4927                         break;
4928                 case OP_FCALL_REG:
4929                 case OP_RCALL_REG:
4930                 case OP_LCALL_REG:
4931                 case OP_VCALL_REG:
4932                 case OP_VCALL2_REG:
4933                 case OP_VOIDCALL_REG:
4934                 case OP_CALL_REG:
4935                         call = (MonoCallInst*)ins;
4936
4937                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4938                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4939                                 ins->sreg1 = AMD64_R11;
4940                         }
4941
4942                         /*
4943                          * The AMD64 ABI forces callers to know about varargs.
4944                          */
4945                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4946                                 if (ins->sreg1 == AMD64_RAX) {
4947                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4948                                         ins->sreg1 = AMD64_R11;
4949                                 }
4950                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4951                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4952                                 /*
4953                                  * Since the unmanaged calling convention doesn't contain a
4954                                  * 'vararg' entry, we have to treat every pinvoke call as a
4955                                  * potential vararg call.
4956                                  */
4957                                 guint32 nregs, i;
4958                                 nregs = 0;
4959                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4960                                         if (call->used_fregs & (1 << i))
4961                                                 nregs ++;
4962                                 if (ins->sreg1 == AMD64_RAX) {
4963                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4964                                         ins->sreg1 = AMD64_R11;
4965                                 }
4966                                 if (!nregs)
4967                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4968                                 else
4969                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4970                         }
4971
4972                         amd64_call_reg (code, ins->sreg1);
4973                         ins->flags |= MONO_INST_GC_CALLSITE;
4974                         ins->backend.pc_offset = code - cfg->native_code;
4975                         code = emit_move_return_value (cfg, ins, code);
4976                         break;
4977                 case OP_FCALL_MEMBASE:
4978                 case OP_RCALL_MEMBASE:
4979                 case OP_LCALL_MEMBASE:
4980                 case OP_VCALL_MEMBASE:
4981                 case OP_VCALL2_MEMBASE:
4982                 case OP_VOIDCALL_MEMBASE:
4983                 case OP_CALL_MEMBASE:
4984                         call = (MonoCallInst*)ins;
4985
4986                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4987                         ins->flags |= MONO_INST_GC_CALLSITE;
4988                         ins->backend.pc_offset = code - cfg->native_code;
4989                         code = emit_move_return_value (cfg, ins, code);
4990                         break;
4991                 case OP_DYN_CALL: {
4992                         int i;
4993                         MonoInst *var = cfg->dyn_call_var;
4994
4995                         g_assert (var->opcode == OP_REGOFFSET);
4996
4997                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4998                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4999                         /* r10 = ftn */
5000                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
5001
5002                         /* Save args buffer */
5003                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
5004
5005                         /* Set argument registers */
5006                         for (i = 0; i < PARAM_REGS; ++i)
5007                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
5008
5009                         /* Make the call */
5010                         amd64_call_reg (code, AMD64_R10);
5011
5012                         ins->flags |= MONO_INST_GC_CALLSITE;
5013                         ins->backend.pc_offset = code - cfg->native_code;
5014
5015                         /* Save result */
5016                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5017                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5018                         break;
5019                 }
5020                 case OP_AMD64_SAVE_SP_TO_LMF: {
5021                         MonoInst *lmf_var = cfg->lmf_var;
5022                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5023                         break;
5024                 }
5025                 case OP_X86_PUSH:
5026                         g_assert_not_reached ();
5027                         amd64_push_reg (code, ins->sreg1);
5028                         break;
5029                 case OP_X86_PUSH_IMM:
5030                         g_assert_not_reached ();
5031                         g_assert (amd64_is_imm32 (ins->inst_imm));
5032                         amd64_push_imm (code, ins->inst_imm);
5033                         break;
5034                 case OP_X86_PUSH_MEMBASE:
5035                         g_assert_not_reached ();
5036                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5037                         break;
5038                 case OP_X86_PUSH_OBJ: {
5039                         int size = ALIGN_TO (ins->inst_imm, 8);
5040
5041                         g_assert_not_reached ();
5042
5043                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5044                         amd64_push_reg (code, AMD64_RDI);
5045                         amd64_push_reg (code, AMD64_RSI);
5046                         amd64_push_reg (code, AMD64_RCX);
5047                         if (ins->inst_offset)
5048                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5049                         else
5050                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5051                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5052                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5053                         amd64_cld (code);
5054                         amd64_prefix (code, X86_REP_PREFIX);
5055                         amd64_movsd (code);
5056                         amd64_pop_reg (code, AMD64_RCX);
5057                         amd64_pop_reg (code, AMD64_RSI);
5058                         amd64_pop_reg (code, AMD64_RDI);
5059                         break;
5060                 }
5061                 case OP_GENERIC_CLASS_INIT: {
5062                         static int byte_offset = -1;
5063                         static guint8 bitmask;
5064                         guint8 *jump;
5065
5066                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5067
5068                         if (byte_offset < 0)
5069                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5070
5071                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5072                         jump = code;
5073                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
5074
5075                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5076                         ins->flags |= MONO_INST_GC_CALLSITE;
5077                         ins->backend.pc_offset = code - cfg->native_code;
5078
5079                         x86_patch (jump, code);
5080                         break;
5081                 }
5082
5083                 case OP_X86_LEA:
5084                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5085                         break;
5086                 case OP_X86_LEA_MEMBASE:
5087                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5088                         break;
5089                 case OP_X86_XCHG:
5090                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5091                         break;
5092                 case OP_LOCALLOC:
5093                         /* keep alignment */
5094                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5095                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5096                         code = mono_emit_stack_alloc (cfg, code, ins);
5097                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5098                         if (cfg->param_area)
5099                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5100                         break;
5101                 case OP_LOCALLOC_IMM: {
5102                         guint32 size = ins->inst_imm;
5103                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5104
5105                         if (ins->flags & MONO_INST_INIT) {
5106                                 if (size < 64) {
5107                                         int i;
5108
5109                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5110                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5111
5112                                         for (i = 0; i < size; i += 8)
5113                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5114                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5115                                 } else {
5116                                         amd64_mov_reg_imm (code, ins->dreg, size);
5117                                         ins->sreg1 = ins->dreg;
5118
5119                                         code = mono_emit_stack_alloc (cfg, code, ins);
5120                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5121                                 }
5122                         } else {
5123                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5124                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5125                         }
5126                         if (cfg->param_area)
5127                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5128                         break;
5129                 }
5130                 case OP_THROW: {
5131                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5132                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5133                                              (gpointer)"mono_arch_throw_exception", FALSE);
5134                         ins->flags |= MONO_INST_GC_CALLSITE;
5135                         ins->backend.pc_offset = code - cfg->native_code;
5136                         break;
5137                 }
5138                 case OP_RETHROW: {
5139                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5140                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5141                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5142                         ins->flags |= MONO_INST_GC_CALLSITE;
5143                         ins->backend.pc_offset = code - cfg->native_code;
5144                         break;
5145                 }
5146                 case OP_CALL_HANDLER:
5147                         /* Align stack */
5148                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5149                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5150                         amd64_call_imm (code, 0);
5151                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5152                         /* Restore stack alignment */
5153                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5154                         break;
5155                 case OP_START_HANDLER: {
5156                         /* Even though we're saving RSP, use sizeof */
5157                         /* gpointer because spvar is of type IntPtr */
5158                         /* see: mono_create_spvar_for_region */
5159                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5160                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5161
5162                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5163                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5164                                 cfg->param_area) {
5165                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5166                         }
5167                         break;
5168                 }
5169                 case OP_ENDFINALLY: {
5170                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5171                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5172                         amd64_ret (code);
5173                         break;
5174                 }
5175                 case OP_ENDFILTER: {
5176                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5177                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5178                         /* The local allocator will put the result into RAX */
5179                         amd64_ret (code);
5180                         break;
5181                 }
5182                 case OP_GET_EX_OBJ:
5183                         if (ins->dreg != AMD64_RAX)
5184                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5185                         break;
5186                 case OP_LABEL:
5187                         ins->inst_c0 = code - cfg->native_code;
5188                         break;
5189                 case OP_BR:
5190                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5191                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5192                         //break;
5193                                 if (ins->inst_target_bb->native_offset) {
5194                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5195                                 } else {
5196                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5197                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5198                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5199                                                 x86_jump8 (code, 0);
5200                                         else
5201                                                 x86_jump32 (code, 0);
5202                         }
5203                         break;
5204                 case OP_BR_REG:
5205                         amd64_jump_reg (code, ins->sreg1);
5206                         break;
5207                 case OP_ICNEQ:
5208                 case OP_ICGE:
5209                 case OP_ICLE:
5210                 case OP_ICGE_UN:
5211                 case OP_ICLE_UN:
5212
5213                 case OP_CEQ:
5214                 case OP_LCEQ:
5215                 case OP_ICEQ:
5216                 case OP_CLT:
5217                 case OP_LCLT:
5218                 case OP_ICLT:
5219                 case OP_CGT:
5220                 case OP_ICGT:
5221                 case OP_LCGT:
5222                 case OP_CLT_UN:
5223                 case OP_LCLT_UN:
5224                 case OP_ICLT_UN:
5225                 case OP_CGT_UN:
5226                 case OP_LCGT_UN:
5227                 case OP_ICGT_UN:
5228                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5229                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5230                         break;
5231                 case OP_COND_EXC_EQ:
5232                 case OP_COND_EXC_NE_UN:
5233                 case OP_COND_EXC_LT:
5234                 case OP_COND_EXC_LT_UN:
5235                 case OP_COND_EXC_GT:
5236                 case OP_COND_EXC_GT_UN:
5237                 case OP_COND_EXC_GE:
5238                 case OP_COND_EXC_GE_UN:
5239                 case OP_COND_EXC_LE:
5240                 case OP_COND_EXC_LE_UN:
5241                 case OP_COND_EXC_IEQ:
5242                 case OP_COND_EXC_INE_UN:
5243                 case OP_COND_EXC_ILT:
5244                 case OP_COND_EXC_ILT_UN:
5245                 case OP_COND_EXC_IGT:
5246                 case OP_COND_EXC_IGT_UN:
5247                 case OP_COND_EXC_IGE:
5248                 case OP_COND_EXC_IGE_UN:
5249                 case OP_COND_EXC_ILE:
5250                 case OP_COND_EXC_ILE_UN:
5251                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5252                         break;
5253                 case OP_COND_EXC_OV:
5254                 case OP_COND_EXC_NO:
5255                 case OP_COND_EXC_C:
5256                 case OP_COND_EXC_NC:
5257                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5258                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5259                         break;
5260                 case OP_COND_EXC_IOV:
5261                 case OP_COND_EXC_INO:
5262                 case OP_COND_EXC_IC:
5263                 case OP_COND_EXC_INC:
5264                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5265                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5266                         break;
5267
5268                 /* floating point opcodes */
5269                 case OP_R8CONST: {
5270                         double d = *(double *)ins->inst_p0;
5271
5272                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5273                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5274                         }
5275                         else {
5276                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5277                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5278                         }
5279                         break;
5280                 }
5281                 case OP_R4CONST: {
5282                         float f = *(float *)ins->inst_p0;
5283
5284                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5285                                 if (cfg->r4fp)
5286                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5287                                 else
5288                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5289                         }
5290                         else {
5291                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5292                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5293                                 if (!cfg->r4fp)
5294                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5295                         }
5296                         break;
5297                 }
5298                 case OP_STORER8_MEMBASE_REG:
5299                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5300                         break;
5301                 case OP_LOADR8_MEMBASE:
5302                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5303                         break;
5304                 case OP_STORER4_MEMBASE_REG:
5305                         if (cfg->r4fp) {
5306                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5307                         } else {
5308                                 /* This requires a double->single conversion */
5309                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5310                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5311                         }
5312                         break;
5313                 case OP_LOADR4_MEMBASE:
5314                         if (cfg->r4fp) {
5315                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5316                         } else {
5317                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5318                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5319                         }
5320                         break;
5321                 case OP_ICONV_TO_R4:
5322                         if (cfg->r4fp) {
5323                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5324                         } else {
5325                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5326                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5327                         }
5328                         break;
5329                 case OP_ICONV_TO_R8:
5330                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5331                         break;
5332                 case OP_LCONV_TO_R4:
5333                         if (cfg->r4fp) {
5334                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5335                         } else {
5336                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5337                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5338                         }
5339                         break;
5340                 case OP_LCONV_TO_R8:
5341                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5342                         break;
5343                 case OP_FCONV_TO_R4:
5344                         if (cfg->r4fp) {
5345                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5346                         } else {
5347                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5348                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5349                         }
5350                         break;
5351                 case OP_FCONV_TO_I1:
5352                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5353                         break;
5354                 case OP_FCONV_TO_U1:
5355                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5356                         break;
5357                 case OP_FCONV_TO_I2:
5358                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5359                         break;
5360                 case OP_FCONV_TO_U2:
5361                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5362                         break;
5363                 case OP_FCONV_TO_U4:
5364                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5365                         break;
5366                 case OP_FCONV_TO_I4:
5367                 case OP_FCONV_TO_I:
5368                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5369                         break;
5370                 case OP_FCONV_TO_I8:
5371                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5372                         break;
5373
5374                 case OP_RCONV_TO_I1:
5375                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5376                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5377                         break;
5378                 case OP_RCONV_TO_U1:
5379                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5380                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5381                         break;
5382                 case OP_RCONV_TO_I2:
5383                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5384                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5385                         break;
5386                 case OP_RCONV_TO_U2:
5387                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5388                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5389                         break;
5390                 case OP_RCONV_TO_I4:
5391                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5392                         break;
5393                 case OP_RCONV_TO_U4:
5394                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5395                         break;
5396                 case OP_RCONV_TO_I8:
5397                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5398                         break;
5399                 case OP_RCONV_TO_R8:
5400                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5401                         break;
5402                 case OP_RCONV_TO_R4:
5403                         if (ins->dreg != ins->sreg1)
5404                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5405                         break;
5406
5407                 case OP_LCONV_TO_R_UN: {
5408                         guint8 *br [2];
5409
5410                         /* Based on gcc code */
5411                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5412                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5413
5414                         /* Positive case */
5415                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5416                         br [1] = code; x86_jump8 (code, 0);
5417                         amd64_patch (br [0], code);
5418
5419                         /* Negative case */
5420                         /* Save to the red zone */
5421                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5422                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5423                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5424                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5425                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5426                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5427                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5428                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5429                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5430                         /* Restore */
5431                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5432                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5433                         amd64_patch (br [1], code);
5434                         break;
5435                 }
5436                 case OP_LCONV_TO_OVF_U4:
5437                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5438                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5439                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5440                         break;
5441                 case OP_LCONV_TO_OVF_I4_UN:
5442                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5443                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5444                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5445                         break;
5446                 case OP_FMOVE:
5447                         if (ins->dreg != ins->sreg1)
5448                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5449                         break;
5450                 case OP_RMOVE:
5451                         if (ins->dreg != ins->sreg1)
5452                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5453                         break;
5454                 case OP_MOVE_F_TO_I4:
5455                         if (cfg->r4fp) {
5456                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5457                         } else {
5458                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5459                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5460                         }
5461                         break;
5462                 case OP_MOVE_I4_TO_F:
5463                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5464                         if (!cfg->r4fp)
5465                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5466                         break;
5467                 case OP_MOVE_F_TO_I8:
5468                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5469                         break;
5470                 case OP_MOVE_I8_TO_F:
5471                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5472                         break;
5473                 case OP_FADD:
5474                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5475                         break;
5476                 case OP_FSUB:
5477                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5478                         break;
5479                 case OP_FMUL:
5480                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5481                         break;
5482                 case OP_FDIV:
5483                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5484                         break;
5485                 case OP_FNEG: {
5486                         static double r8_0 = -0.0;
5487
5488                         g_assert (ins->sreg1 == ins->dreg);
5489
5490                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5491                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5492                         break;
5493                 }
5494                 case OP_SIN:
5495                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5496                         break;
5497                 case OP_COS:
5498                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5499                         break;
5500                 case OP_ABS: {
5501                         static guint64 d = 0x7fffffffffffffffUL;
5502
5503                         g_assert (ins->sreg1 == ins->dreg);
5504
5505                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5506                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5507                         break;
5508                 }
5509                 case OP_SQRT:
5510                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5511                         break;
5512
5513                 case OP_RADD:
5514                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5515                         break;
5516                 case OP_RSUB:
5517                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5518                         break;
5519                 case OP_RMUL:
5520                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5521                         break;
5522                 case OP_RDIV:
5523                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5524                         break;
5525                 case OP_RNEG: {
5526                         static float r4_0 = -0.0;
5527
5528                         g_assert (ins->sreg1 == ins->dreg);
5529
5530                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5531                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5532                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5533                         break;
5534                 }
5535
5536                 case OP_IMIN:
5537                         g_assert (cfg->opt & MONO_OPT_CMOV);
5538                         g_assert (ins->dreg == ins->sreg1);
5539                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5540                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5541                         break;
5542                 case OP_IMIN_UN:
5543                         g_assert (cfg->opt & MONO_OPT_CMOV);
5544                         g_assert (ins->dreg == ins->sreg1);
5545                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5546                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5547                         break;
5548                 case OP_IMAX:
5549                         g_assert (cfg->opt & MONO_OPT_CMOV);
5550                         g_assert (ins->dreg == ins->sreg1);
5551                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5552                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5553                         break;
5554                 case OP_IMAX_UN:
5555                         g_assert (cfg->opt & MONO_OPT_CMOV);
5556                         g_assert (ins->dreg == ins->sreg1);
5557                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5558                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5559                         break;
5560                 case OP_LMIN:
5561                         g_assert (cfg->opt & MONO_OPT_CMOV);
5562                         g_assert (ins->dreg == ins->sreg1);
5563                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5564                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5565                         break;
5566                 case OP_LMIN_UN:
5567                         g_assert (cfg->opt & MONO_OPT_CMOV);
5568                         g_assert (ins->dreg == ins->sreg1);
5569                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5570                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5571                         break;
5572                 case OP_LMAX:
5573                         g_assert (cfg->opt & MONO_OPT_CMOV);
5574                         g_assert (ins->dreg == ins->sreg1);
5575                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5576                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5577                         break;
5578                 case OP_LMAX_UN:
5579                         g_assert (cfg->opt & MONO_OPT_CMOV);
5580                         g_assert (ins->dreg == ins->sreg1);
5581                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5582                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5583                         break;
5584                 case OP_X86_FPOP:
5585                         break;
5586                 case OP_FCOMPARE:
5587                         /*
5588                          * The two arguments are swapped because the fbranch instructions
5589                          * depend on this for the non-sse case to work.
5590                          */
5591                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5592                         break;
5593                 case OP_RCOMPARE:
5594                         /*
5595                          * FIXME: Get rid of this.
5596                          * The two arguments are swapped because the fbranch instructions
5597                          * depend on this for the non-sse case to work.
5598                          */
5599                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5600                         break;
5601                 case OP_FCNEQ:
5602                 case OP_FCEQ: {
5603                         /* zeroing the register at the start results in
5604                          * shorter and faster code (we can also remove the widening op)
5605                          */
5606                         guchar *unordered_check;
5607
5608                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5609                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5610                         unordered_check = code;
5611                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5612
5613                         if (ins->opcode == OP_FCEQ) {
5614                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5615                                 amd64_patch (unordered_check, code);
5616                         } else {
5617                                 guchar *jump_to_end;
5618                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5619                                 jump_to_end = code;
5620                                 x86_jump8 (code, 0);
5621                                 amd64_patch (unordered_check, code);
5622                                 amd64_inc_reg (code, ins->dreg);
5623                                 amd64_patch (jump_to_end, code);
5624                         }
5625                         break;
5626                 }
5627                 case OP_FCLT:
5628                 case OP_FCLT_UN: {
5629                         /* zeroing the register at the start results in
5630                          * shorter and faster code (we can also remove the widening op)
5631                          */
5632                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5633                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5634                         if (ins->opcode == OP_FCLT_UN) {
5635                                 guchar *unordered_check = code;
5636                                 guchar *jump_to_end;
5637                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5638                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5639                                 jump_to_end = code;
5640                                 x86_jump8 (code, 0);
5641                                 amd64_patch (unordered_check, code);
5642                                 amd64_inc_reg (code, ins->dreg);
5643                                 amd64_patch (jump_to_end, code);
5644                         } else {
5645                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5646                         }
5647                         break;
5648                 }
5649                 case OP_FCLE: {
5650                         guchar *unordered_check;
5651                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5652                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5653                         unordered_check = code;
5654                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5655                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5656                         amd64_patch (unordered_check, code);
5657                         break;
5658                 }
5659                 case OP_FCGT:
5660                 case OP_FCGT_UN: {
5661                         /* zeroing the register at the start results in
5662                          * shorter and faster code (we can also remove the widening op)
5663                          */
5664                         guchar *unordered_check;
5665
5666                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5667                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5668                         if (ins->opcode == OP_FCGT) {
5669                                 unordered_check = code;
5670                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5671                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5672                                 amd64_patch (unordered_check, code);
5673                         } else {
5674                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5675                         }
5676                         break;
5677                 }
5678                 case OP_FCGE: {
5679                         guchar *unordered_check;
5680                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5681                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5682                         unordered_check = code;
5683                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5684                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5685                         amd64_patch (unordered_check, code);
5686                         break;
5687                 }
5688
5689                 case OP_RCEQ:
5690                 case OP_RCGT:
5691                 case OP_RCLT:
5692                 case OP_RCLT_UN:
5693                 case OP_RCGT_UN: {
5694                         int x86_cond;
5695                         gboolean unordered = FALSE;
5696
5697                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5698                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5699
5700                         switch (ins->opcode) {
5701                         case OP_RCEQ:
5702                                 x86_cond = X86_CC_EQ;
5703                                 break;
5704                         case OP_RCGT:
5705                                 x86_cond = X86_CC_LT;
5706                                 break;
5707                         case OP_RCLT:
5708                                 x86_cond = X86_CC_GT;
5709                                 break;
5710                         case OP_RCLT_UN:
5711                                 x86_cond = X86_CC_GT;
5712                                 unordered = TRUE;
5713                                 break;
5714                         case OP_RCGT_UN:
5715                                 x86_cond = X86_CC_LT;
5716                                 unordered = TRUE;
5717                                 break;
5718                         default:
5719                                 g_assert_not_reached ();
5720                                 break;
5721                         }
5722
5723                         if (unordered) {
5724                                 guchar *unordered_check;
5725                                 guchar *jump_to_end;
5726
5727                                 unordered_check = code;
5728                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5729                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5730                                 jump_to_end = code;
5731                                 x86_jump8 (code, 0);
5732                                 amd64_patch (unordered_check, code);
5733                                 amd64_inc_reg (code, ins->dreg);
5734                                 amd64_patch (jump_to_end, code);
5735                         } else {
5736                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5737                         }
5738                         break;
5739                 }
5740                 case OP_FCLT_MEMBASE:
5741                 case OP_FCGT_MEMBASE:
5742                 case OP_FCLT_UN_MEMBASE:
5743                 case OP_FCGT_UN_MEMBASE:
5744                 case OP_FCEQ_MEMBASE: {
5745                         guchar *unordered_check, *jump_to_end;
5746                         int x86_cond;
5747
5748                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5749                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5750
5751                         switch (ins->opcode) {
5752                         case OP_FCEQ_MEMBASE:
5753                                 x86_cond = X86_CC_EQ;
5754                                 break;
5755                         case OP_FCLT_MEMBASE:
5756                         case OP_FCLT_UN_MEMBASE:
5757                                 x86_cond = X86_CC_LT;
5758                                 break;
5759                         case OP_FCGT_MEMBASE:
5760                         case OP_FCGT_UN_MEMBASE:
5761                                 x86_cond = X86_CC_GT;
5762                                 break;
5763                         default:
5764                                 g_assert_not_reached ();
5765                         }
5766
5767                         unordered_check = code;
5768                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5769                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5770
5771                         switch (ins->opcode) {
5772                         case OP_FCEQ_MEMBASE:
5773                         case OP_FCLT_MEMBASE:
5774                         case OP_FCGT_MEMBASE:
5775                                 amd64_patch (unordered_check, code);
5776                                 break;
5777                         case OP_FCLT_UN_MEMBASE:
5778                         case OP_FCGT_UN_MEMBASE:
5779                                 jump_to_end = code;
5780                                 x86_jump8 (code, 0);
5781                                 amd64_patch (unordered_check, code);
5782                                 amd64_inc_reg (code, ins->dreg);
5783                                 amd64_patch (jump_to_end, code);
5784                                 break;
5785                         default:
5786                                 break;
5787                         }
5788                         break;
5789                 }
5790                 case OP_FBEQ: {
5791                         guchar *jump = code;
5792                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5793                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5794                         amd64_patch (jump, code);
5795                         break;
5796                 }
5797                 case OP_FBNE_UN:
5798                         /* Branch if C013 != 100 */
5799                         /* branch if !ZF or (PF|CF) */
5800                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5801                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5802                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5803                         break;
5804                 case OP_FBLT:
5805                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5806                         break;
5807                 case OP_FBLT_UN:
5808                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5809                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5810                         break;
5811                 case OP_FBGT:
5812                 case OP_FBGT_UN:
5813                         if (ins->opcode == OP_FBGT) {
5814                                 guchar *br1;
5815
5816                                 /* skip branch if C1=1 */
5817                                 br1 = code;
5818                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5819                                 /* branch if (C0 | C3) = 1 */
5820                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5821                                 amd64_patch (br1, code);
5822                                 break;
5823                         } else {
5824                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5825                         }
5826                         break;
5827                 case OP_FBGE: {
5828                         /* Branch if C013 == 100 or 001 */
5829                         guchar *br1;
5830
5831                         /* skip branch if C1=1 */
5832                         br1 = code;
5833                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5834                         /* branch if (C0 | C3) = 1 */
5835                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5836                         amd64_patch (br1, code);
5837                         break;
5838                 }
5839                 case OP_FBGE_UN:
5840                         /* Branch if C013 == 000 */
5841                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5842                         break;
5843                 case OP_FBLE: {
5844                         /* Branch if C013=000 or 100 */
5845                         guchar *br1;
5846
5847                         /* skip branch if C1=1 */
5848                         br1 = code;
5849                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5850                         /* branch if C0=0 */
5851                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5852                         amd64_patch (br1, code);
5853                         break;
5854                 }
5855                 case OP_FBLE_UN:
5856                         /* Branch if C013 != 001 */
5857                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5858                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5859                         break;
5860                 case OP_CKFINITE:
5861                         /* Transfer value to the fp stack */
5862                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5863                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5864                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5865
5866                         amd64_push_reg (code, AMD64_RAX);
5867                         amd64_fxam (code);
5868                         amd64_fnstsw (code);
5869                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5870                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5871                         amd64_pop_reg (code, AMD64_RAX);
5872                         amd64_fstp (code, 0);
5873                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5874                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5875                         break;
5876                 case OP_TLS_GET: {
5877                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5878                         break;
5879                 }
5880                 case OP_TLS_GET_REG:
5881                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5882                         break;
5883                 case OP_TLS_SET: {
5884                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5885                         break;
5886                 }
5887                 case OP_TLS_SET_REG: {
5888                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 }
5891                 case OP_MEMORY_BARRIER: {
5892                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5893                                 x86_mfence (code);
5894                         break;
5895                 }
5896                 case OP_ATOMIC_ADD_I4:
5897                 case OP_ATOMIC_ADD_I8: {
5898                         int dreg = ins->dreg;
5899                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5900
5901                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5902                                 dreg = AMD64_R11;
5903
5904                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5905                         amd64_prefix (code, X86_LOCK_PREFIX);
5906                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5907                         /* dreg contains the old value, add with sreg2 value */
5908                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5909
5910                         if (ins->dreg != dreg)
5911                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5912
5913                         break;
5914                 }
5915                 case OP_ATOMIC_EXCHANGE_I4:
5916                 case OP_ATOMIC_EXCHANGE_I8: {
5917                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5918
5919                         /* LOCK prefix is implied. */
5920                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5921                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5922                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5923                         break;
5924                 }
5925                 case OP_ATOMIC_CAS_I4:
5926                 case OP_ATOMIC_CAS_I8: {
5927                         guint32 size;
5928
5929                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5930                                 size = 8;
5931                         else
5932                                 size = 4;
5933
5934                         /*
5935                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5936                          * an explanation of how this works.
5937                          */
5938                         g_assert (ins->sreg3 == AMD64_RAX);
5939                         g_assert (ins->sreg1 != AMD64_RAX);
5940                         g_assert (ins->sreg1 != ins->sreg2);
5941
5942                         amd64_prefix (code, X86_LOCK_PREFIX);
5943                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5944
5945                         if (ins->dreg != AMD64_RAX)
5946                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5947                         break;
5948                 }
5949                 case OP_ATOMIC_LOAD_I1: {
5950                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5951                         break;
5952                 }
5953                 case OP_ATOMIC_LOAD_U1: {
5954                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5955                         break;
5956                 }
5957                 case OP_ATOMIC_LOAD_I2: {
5958                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5959                         break;
5960                 }
5961                 case OP_ATOMIC_LOAD_U2: {
5962                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5963                         break;
5964                 }
5965                 case OP_ATOMIC_LOAD_I4: {
5966                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5967                         break;
5968                 }
5969                 case OP_ATOMIC_LOAD_U4:
5970                 case OP_ATOMIC_LOAD_I8:
5971                 case OP_ATOMIC_LOAD_U8: {
5972                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5973                         break;
5974                 }
5975                 case OP_ATOMIC_LOAD_R4: {
5976                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5977                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5978                         break;
5979                 }
5980                 case OP_ATOMIC_LOAD_R8: {
5981                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5982                         break;
5983                 }
5984                 case OP_ATOMIC_STORE_I1:
5985                 case OP_ATOMIC_STORE_U1:
5986                 case OP_ATOMIC_STORE_I2:
5987                 case OP_ATOMIC_STORE_U2:
5988                 case OP_ATOMIC_STORE_I4:
5989                 case OP_ATOMIC_STORE_U4:
5990                 case OP_ATOMIC_STORE_I8:
5991                 case OP_ATOMIC_STORE_U8: {
5992                         int size;
5993
5994                         switch (ins->opcode) {
5995                         case OP_ATOMIC_STORE_I1:
5996                         case OP_ATOMIC_STORE_U1:
5997                                 size = 1;
5998                                 break;
5999                         case OP_ATOMIC_STORE_I2:
6000                         case OP_ATOMIC_STORE_U2:
6001                                 size = 2;
6002                                 break;
6003                         case OP_ATOMIC_STORE_I4:
6004                         case OP_ATOMIC_STORE_U4:
6005                                 size = 4;
6006                                 break;
6007                         case OP_ATOMIC_STORE_I8:
6008                         case OP_ATOMIC_STORE_U8:
6009                                 size = 8;
6010                                 break;
6011                         }
6012
6013                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
6014
6015                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6016                                 x86_mfence (code);
6017                         break;
6018                 }
6019                 case OP_ATOMIC_STORE_R4: {
6020                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6021                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6022
6023                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6024                                 x86_mfence (code);
6025                         break;
6026                 }
6027                 case OP_ATOMIC_STORE_R8: {
6028                         x86_nop (code);
6029                         x86_nop (code);
6030                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6031                         x86_nop (code);
6032                         x86_nop (code);
6033
6034                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6035                                 x86_mfence (code);
6036                         break;
6037                 }
6038                 case OP_CARD_TABLE_WBARRIER: {
6039                         int ptr = ins->sreg1;
6040                         int value = ins->sreg2;
6041                         guchar *br = 0;
6042                         int nursery_shift, card_table_shift;
6043                         gpointer card_table_mask;
6044                         size_t nursery_size;
6045
6046                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6047                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6048                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6049
6050                         /*If either point to the stack we can simply avoid the WB. This happens due to
6051                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6052                          */
6053                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6054                                 continue;
6055
6056                         /*
6057                          * We need one register we can clobber, we choose EDX and make sreg1
6058                          * fixed EAX to work around limitations in the local register allocator.
6059                          * sreg2 might get allocated to EDX, but that is not a problem since
6060                          * we use it before clobbering EDX.
6061                          */
6062                         g_assert (ins->sreg1 == AMD64_RAX);
6063
6064                         /*
6065                          * This is the code we produce:
6066                          *
6067                          *   edx = value
6068                          *   edx >>= nursery_shift
6069                          *   cmp edx, (nursery_start >> nursery_shift)
6070                          *   jne done
6071                          *   edx = ptr
6072                          *   edx >>= card_table_shift
6073                          *   edx += cardtable
6074                          *   [edx] = 1
6075                          * done:
6076                          */
6077
6078                         if (mono_gc_card_table_nursery_check ()) {
6079                                 if (value != AMD64_RDX)
6080                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6081                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6082                                 if (shifted_nursery_start >> 31) {
6083                                         /*
6084                                          * The value we need to compare against is 64 bits, so we need
6085                                          * another spare register.  We use RBX, which we save and
6086                                          * restore.
6087                                          */
6088                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6089                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6090                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6091                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6092                                 } else {
6093                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6094                                 }
6095                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6096                         }
6097                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6098                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6099                         if (card_table_mask)
6100                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6101
6102                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6103                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6104
6105                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6106
6107                         if (mono_gc_card_table_nursery_check ())
6108                                 x86_patch (br, code);
6109                         break;
6110                 }
6111 #ifdef MONO_ARCH_SIMD_INTRINSICS
6112                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6113                 case OP_ADDPS:
6114                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6115                         break;
6116                 case OP_DIVPS:
6117                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6118                         break;
6119                 case OP_MULPS:
6120                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122                 case OP_SUBPS:
6123                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125                 case OP_MAXPS:
6126                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6127                         break;
6128                 case OP_MINPS:
6129                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_COMPPS:
6132                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6133                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6134                         break;
6135                 case OP_ANDPS:
6136                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138                 case OP_ANDNPS:
6139                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6140                         break;
6141                 case OP_ORPS:
6142                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6143                         break;
6144                 case OP_XORPS:
6145                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6146                         break;
6147                 case OP_SQRTPS:
6148                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6149                         break;
6150                 case OP_RSQRTPS:
6151                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6152                         break;
6153                 case OP_RCPPS:
6154                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6155                         break;
6156                 case OP_ADDSUBPS:
6157                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6158                         break;
6159                 case OP_HADDPS:
6160                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6161                         break;
6162                 case OP_HSUBPS:
6163                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6164                         break;
6165                 case OP_DUPPS_HIGH:
6166                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6167                         break;
6168                 case OP_DUPPS_LOW:
6169                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6170                         break;
6171
6172                 case OP_PSHUFLEW_HIGH:
6173                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6174                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6175                         break;
6176                 case OP_PSHUFLEW_LOW:
6177                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6178                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6179                         break;
6180                 case OP_PSHUFLED:
6181                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6182                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6183                         break;
6184                 case OP_SHUFPS:
6185                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6186                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6187                         break;
6188                 case OP_SHUFPD:
6189                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6190                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6191                         break;
6192
6193                 case OP_ADDPD:
6194                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6195                         break;
6196                 case OP_DIVPD:
6197                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6198                         break;
6199                 case OP_MULPD:
6200                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6201                         break;
6202                 case OP_SUBPD:
6203                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6204                         break;
6205                 case OP_MAXPD:
6206                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6207                         break;
6208                 case OP_MINPD:
6209                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6210                         break;
6211                 case OP_COMPPD:
6212                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6213                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6214                         break;
6215                 case OP_ANDPD:
6216                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6217                         break;
6218                 case OP_ANDNPD:
6219                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6220                         break;
6221                 case OP_ORPD:
6222                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6223                         break;
6224                 case OP_XORPD:
6225                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6226                         break;
6227                 case OP_SQRTPD:
6228                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6229                         break;
6230                 case OP_ADDSUBPD:
6231                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6232                         break;
6233                 case OP_HADDPD:
6234                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236                 case OP_HSUBPD:
6237                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239                 case OP_DUPPD:
6240                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6241                         break;
6242
6243                 case OP_EXTRACT_MASK:
6244                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6245                         break;
6246
6247                 case OP_PAND:
6248                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6249                         break;
6250                 case OP_POR:
6251                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6252                         break;
6253                 case OP_PXOR:
6254                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6255                         break;
6256
6257                 case OP_PADDB:
6258                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6259                         break;
6260                 case OP_PADDW:
6261                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6262                         break;
6263                 case OP_PADDD:
6264                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6265                         break;
6266                 case OP_PADDQ:
6267                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6268                         break;
6269
6270                 case OP_PSUBB:
6271                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6272                         break;
6273                 case OP_PSUBW:
6274                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6275                         break;
6276                 case OP_PSUBD:
6277                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6278                         break;
6279                 case OP_PSUBQ:
6280                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6281                         break;
6282
6283                 case OP_PMAXB_UN:
6284                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6285                         break;
6286                 case OP_PMAXW_UN:
6287                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6288                         break;
6289                 case OP_PMAXD_UN:
6290                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6291                         break;
6292
6293                 case OP_PMAXB:
6294                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6295                         break;
6296                 case OP_PMAXW:
6297                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6298                         break;
6299                 case OP_PMAXD:
6300                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6301                         break;
6302
6303                 case OP_PAVGB_UN:
6304                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6305                         break;
6306                 case OP_PAVGW_UN:
6307                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6308                         break;
6309
6310                 case OP_PMINB_UN:
6311                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6312                         break;
6313                 case OP_PMINW_UN:
6314                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6315                         break;
6316                 case OP_PMIND_UN:
6317                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6318                         break;
6319
6320                 case OP_PMINB:
6321                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6322                         break;
6323                 case OP_PMINW:
6324                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6325                         break;
6326                 case OP_PMIND:
6327                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6328                         break;
6329
6330                 case OP_PCMPEQB:
6331                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6332                         break;
6333                 case OP_PCMPEQW:
6334                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6335                         break;
6336                 case OP_PCMPEQD:
6337                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6338                         break;
6339                 case OP_PCMPEQQ:
6340                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6341                         break;
6342
6343                 case OP_PCMPGTB:
6344                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6345                         break;
6346                 case OP_PCMPGTW:
6347                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6348                         break;
6349                 case OP_PCMPGTD:
6350                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6351                         break;
6352                 case OP_PCMPGTQ:
6353                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6354                         break;
6355
6356                 case OP_PSUM_ABS_DIFF:
6357                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6358                         break;
6359
6360                 case OP_UNPACK_LOWB:
6361                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6362                         break;
6363                 case OP_UNPACK_LOWW:
6364                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6365                         break;
6366                 case OP_UNPACK_LOWD:
6367                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6368                         break;
6369                 case OP_UNPACK_LOWQ:
6370                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6371                         break;
6372                 case OP_UNPACK_LOWPS:
6373                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6374                         break;
6375                 case OP_UNPACK_LOWPD:
6376                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6377                         break;
6378
6379                 case OP_UNPACK_HIGHB:
6380                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6381                         break;
6382                 case OP_UNPACK_HIGHW:
6383                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6384                         break;
6385                 case OP_UNPACK_HIGHD:
6386                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6387                         break;
6388                 case OP_UNPACK_HIGHQ:
6389                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6390                         break;
6391                 case OP_UNPACK_HIGHPS:
6392                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6393                         break;
6394                 case OP_UNPACK_HIGHPD:
6395                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6396                         break;
6397
6398                 case OP_PACKW:
6399                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6400                         break;
6401                 case OP_PACKD:
6402                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6403                         break;
6404                 case OP_PACKW_UN:
6405                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6406                         break;
6407                 case OP_PACKD_UN:
6408                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6409                         break;
6410
6411                 case OP_PADDB_SAT_UN:
6412                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6413                         break;
6414                 case OP_PSUBB_SAT_UN:
6415                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6416                         break;
6417                 case OP_PADDW_SAT_UN:
6418                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6419                         break;
6420                 case OP_PSUBW_SAT_UN:
6421                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6422                         break;
6423
6424                 case OP_PADDB_SAT:
6425                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6426                         break;
6427                 case OP_PSUBB_SAT:
6428                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6429                         break;
6430                 case OP_PADDW_SAT:
6431                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6432                         break;
6433                 case OP_PSUBW_SAT:
6434                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6435                         break;
6436
6437                 case OP_PMULW:
6438                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6439                         break;
6440                 case OP_PMULD:
6441                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6442                         break;
6443                 case OP_PMULQ:
6444                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6445                         break;
6446                 case OP_PMULW_HIGH_UN:
6447                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6448                         break;
6449                 case OP_PMULW_HIGH:
6450                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6451                         break;
6452
6453                 case OP_PSHRW:
6454                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6455                         break;
6456                 case OP_PSHRW_REG:
6457                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6458                         break;
6459
6460                 case OP_PSARW:
6461                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6462                         break;
6463                 case OP_PSARW_REG:
6464                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6465                         break;
6466
6467                 case OP_PSHLW:
6468                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6469                         break;
6470                 case OP_PSHLW_REG:
6471                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6472                         break;
6473
6474                 case OP_PSHRD:
6475                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6476                         break;
6477                 case OP_PSHRD_REG:
6478                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6479                         break;
6480
6481                 case OP_PSARD:
6482                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6483                         break;
6484                 case OP_PSARD_REG:
6485                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6486                         break;
6487
6488                 case OP_PSHLD:
6489                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6490                         break;
6491                 case OP_PSHLD_REG:
6492                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6493                         break;
6494
6495                 case OP_PSHRQ:
6496                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6497                         break;
6498                 case OP_PSHRQ_REG:
6499                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6500                         break;
6501
6502                 /*TODO: This is appart of the sse spec but not added
6503                 case OP_PSARQ:
6504                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6505                         break;
6506                 case OP_PSARQ_REG:
6507                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6508                         break;
6509                 */
6510
6511                 case OP_PSHLQ:
6512                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6513                         break;
6514                 case OP_PSHLQ_REG:
6515                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6516                         break;
6517                 case OP_CVTDQ2PD:
6518                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6519                         break;
6520                 case OP_CVTDQ2PS:
6521                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6522                         break;
6523                 case OP_CVTPD2DQ:
6524                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6525                         break;
6526                 case OP_CVTPD2PS:
6527                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6528                         break;
6529                 case OP_CVTPS2DQ:
6530                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6531                         break;
6532                 case OP_CVTPS2PD:
6533                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6534                         break;
6535                 case OP_CVTTPD2DQ:
6536                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6537                         break;
6538                 case OP_CVTTPS2DQ:
6539                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6540                         break;
6541
6542                 case OP_ICONV_TO_X:
6543                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6544                         break;
6545                 case OP_EXTRACT_I4:
6546                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6547                         break;
6548                 case OP_EXTRACT_I8:
6549                         if (ins->inst_c0) {
6550                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6551                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6552                         } else {
6553                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6554                         }
6555                         break;
6556                 case OP_EXTRACT_I1:
6557                 case OP_EXTRACT_U1:
6558                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6559                         if (ins->inst_c0)
6560                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6561                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6562                         break;
6563                 case OP_EXTRACT_I2:
6564                 case OP_EXTRACT_U2:
6565                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6566                         if (ins->inst_c0)
6567                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6568                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6569                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6570                         break;
6571                 case OP_EXTRACT_R8:
6572                         if (ins->inst_c0)
6573                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6574                         else
6575                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6576                         break;
6577                 case OP_INSERT_I2:
6578                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6579                         break;
6580                 case OP_EXTRACTX_U2:
6581                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6582                         break;
6583                 case OP_INSERTX_U1_SLOW:
6584                         /*sreg1 is the extracted ireg (scratch)
6585                         /sreg2 is the to be inserted ireg (scratch)
6586                         /dreg is the xreg to receive the value*/
6587
6588                         /*clear the bits from the extracted word*/
6589                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6590                         /*shift the value to insert if needed*/
6591                         if (ins->inst_c0 & 1)
6592                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6593                         /*join them together*/
6594                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6595                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6596                         break;
6597                 case OP_INSERTX_I4_SLOW:
6598                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6599                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6600                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6601                         break;
6602                 case OP_INSERTX_I8_SLOW:
6603                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6604                         if (ins->inst_c0)
6605                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6606                         else
6607                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6608                         break;
6609
6610                 case OP_INSERTX_R4_SLOW:
6611                         switch (ins->inst_c0) {
6612                         case 0:
6613                                 if (cfg->r4fp)
6614                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6615                                 else
6616                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6617                                 break;
6618                         case 1:
6619                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6620                                 if (cfg->r4fp)
6621                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6622                                 else
6623                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6624                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6625                                 break;
6626                         case 2:
6627                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6628                                 if (cfg->r4fp)
6629                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6630                                 else
6631                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6632                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6633                                 break;
6634                         case 3:
6635                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6636                                 if (cfg->r4fp)
6637                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6638                                 else
6639                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6640                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6641                                 break;
6642                         }
6643                         break;
6644                 case OP_INSERTX_R8_SLOW:
6645                         if (ins->inst_c0)
6646                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6647                         else
6648                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6649                         break;
6650                 case OP_STOREX_MEMBASE_REG:
6651                 case OP_STOREX_MEMBASE:
6652                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6653                         break;
6654                 case OP_LOADX_MEMBASE:
6655                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6656                         break;
6657                 case OP_LOADX_ALIGNED_MEMBASE:
6658                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6659                         break;
6660                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6661                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6662                         break;
6663                 case OP_STOREX_NTA_MEMBASE_REG:
6664                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6665                         break;
6666                 case OP_PREFETCH_MEMBASE:
6667                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6668                         break;
6669
6670                 case OP_XMOVE:
6671                         /*FIXME the peephole pass should have killed this*/
6672                         if (ins->dreg != ins->sreg1)
6673                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6674                         break;
6675                 case OP_XZERO:
6676                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6677                         break;
6678                 case OP_ICONV_TO_R4_RAW:
6679                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6680                         break;
6681
6682                 case OP_FCONV_TO_R8_X:
6683                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6684                         break;
6685
6686                 case OP_XCONV_R8_TO_I4:
6687                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6688                         switch (ins->backend.source_opcode) {
6689                         case OP_FCONV_TO_I1:
6690                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6691                                 break;
6692                         case OP_FCONV_TO_U1:
6693                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6694                                 break;
6695                         case OP_FCONV_TO_I2:
6696                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6697                                 break;
6698                         case OP_FCONV_TO_U2:
6699                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6700                                 break;
6701                         }
6702                         break;
6703
6704                 case OP_EXPAND_I2:
6705                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6706                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6707                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6708                         break;
6709                 case OP_EXPAND_I4:
6710                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6711                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6712                         break;
6713                 case OP_EXPAND_I8:
6714                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6715                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6716                         break;
6717                 case OP_EXPAND_R4:
6718                         if (cfg->r4fp) {
6719                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6720                         } else {
6721                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6722                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6723                         }
6724                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6725                         break;
6726                 case OP_EXPAND_R8:
6727                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6728                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6729                         break;
6730 #endif
6731                 case OP_LIVERANGE_START: {
6732                         if (cfg->verbose_level > 1)
6733                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6734                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6735                         break;
6736                 }
6737                 case OP_LIVERANGE_END: {
6738                         if (cfg->verbose_level > 1)
6739                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6740                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6741                         break;
6742                 }
6743                 case OP_GC_SAFE_POINT: {
6744                         const char *polling_func = NULL;
6745                         int compare_val = 0;
6746                         guint8 *br [1];
6747
6748 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6749                         polling_func = "mono_nacl_gc";
6750                         compare_val = 0xFFFFFFFF;
6751 #else
6752                         g_assert (mono_threads_is_coop_enabled ());
6753                         polling_func = "mono_threads_state_poll";
6754                         compare_val = 1;
6755 #endif
6756
6757                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6758                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6759                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6760                         amd64_patch (br[0], code);
6761                         break;
6762                 }
6763
6764                 case OP_GC_LIVENESS_DEF:
6765                 case OP_GC_LIVENESS_USE:
6766                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6767                         ins->backend.pc_offset = code - cfg->native_code;
6768                         break;
6769                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6770                         ins->backend.pc_offset = code - cfg->native_code;
6771                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6772                         break;
6773                 default:
6774                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6775                         g_assert_not_reached ();
6776                 }
6777
6778                 if ((code - cfg->native_code - offset) > max_len) {
6779 #if !defined(__native_client_codegen__)
6780                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6781                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6782                         g_assert_not_reached ();
6783 #endif
6784                 }
6785         }
6786
6787         cfg->code_len = code - cfg->native_code;
6788 }
6789
6790 #endif /* DISABLE_JIT */
6791
6792 void
6793 mono_arch_register_lowlevel_calls (void)
6794 {
6795         /* The signature doesn't matter */
6796         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6797 }
6798
6799 void
6800 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6801 {
6802         unsigned char *ip = ji->ip.i + code;
6803
6804         /*
6805          * Debug code to help track down problems where the target of a near call is
6806          * is not valid.
6807          */
6808         if (amd64_is_near_call (ip)) {
6809                 gint64 disp = (guint8*)target - (guint8*)ip;
6810
6811                 if (!amd64_is_imm32 (disp)) {
6812                         printf ("TYPE: %d\n", ji->type);
6813                         switch (ji->type) {
6814                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6815                                 printf ("V: %s\n", ji->data.name);
6816                                 break;
6817                         case MONO_PATCH_INFO_METHOD_JUMP:
6818                         case MONO_PATCH_INFO_METHOD:
6819                                 printf ("V: %s\n", ji->data.method->name);
6820                                 break;
6821                         default:
6822                                 break;
6823                         }
6824                 }
6825         }
6826
6827         amd64_patch (ip, (gpointer)target);
6828 }
6829
6830 #ifndef DISABLE_JIT
6831
6832 static int
6833 get_max_epilog_size (MonoCompile *cfg)
6834 {
6835         int max_epilog_size = 16;
6836
6837         if (cfg->method->save_lmf)
6838                 max_epilog_size += 256;
6839
6840         if (mono_jit_trace_calls != NULL)
6841                 max_epilog_size += 50;
6842
6843         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6844                 max_epilog_size += 50;
6845
6846         max_epilog_size += (AMD64_NREG * 2);
6847
6848         return max_epilog_size;
6849 }
6850
6851 /*
6852  * This macro is used for testing whenever the unwinder works correctly at every point
6853  * where an async exception can happen.
6854  */
6855 /* This will generate a SIGSEGV at the given point in the code */
6856 #define async_exc_point(code) do { \
6857     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6858          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6859              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6860          cfg->arch.async_point_count ++; \
6861     } \
6862 } while (0)
6863
6864 guint8 *
6865 mono_arch_emit_prolog (MonoCompile *cfg)
6866 {
6867         MonoMethod *method = cfg->method;
6868         MonoBasicBlock *bb;
6869         MonoMethodSignature *sig;
6870         MonoInst *ins;
6871         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6872         guint8 *code;
6873         CallInfo *cinfo;
6874         MonoInst *lmf_var = cfg->lmf_var;
6875         gboolean args_clobbered = FALSE;
6876         gboolean trace = FALSE;
6877 #ifdef __native_client_codegen__
6878         guint alignment_check;
6879 #endif
6880
6881         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6882
6883 #if defined(__default_codegen__)
6884         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6885 #elif defined(__native_client_codegen__)
6886         /* native_code_alloc is not 32-byte aligned, native_code is. */
6887         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6888
6889         /* Align native_code to next nearest kNaclAlignment byte. */
6890         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6891         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6892
6893         code = cfg->native_code;
6894
6895         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6896         g_assert (alignment_check == 0);
6897 #endif
6898
6899         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6900                 trace = TRUE;
6901
6902         /* Amount of stack space allocated by register saving code */
6903         pos = 0;
6904
6905         /* Offset between RSP and the CFA */
6906         cfa_offset = 0;
6907
6908         /*
6909          * The prolog consists of the following parts:
6910          * FP present:
6911          * - push rbp, mov rbp, rsp
6912          * - save callee saved regs using pushes
6913          * - allocate frame
6914          * - save rgctx if needed
6915          * - save lmf if needed
6916          * FP not present:
6917          * - allocate frame
6918          * - save rgctx if needed
6919          * - save lmf if needed
6920          * - save callee saved regs using moves
6921          */
6922
6923         // CFA = sp + 8
6924         cfa_offset = 8;
6925         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6926         // IP saved at CFA - 8
6927         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6928         async_exc_point (code);
6929         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6930
6931         if (!cfg->arch.omit_fp) {
6932                 amd64_push_reg (code, AMD64_RBP);
6933                 cfa_offset += 8;
6934                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6935                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6936                 async_exc_point (code);
6937 #ifdef TARGET_WIN32
6938                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6939 #endif
6940                 /* These are handled automatically by the stack marking code */
6941                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6942
6943                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6944                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6945                 async_exc_point (code);
6946 #ifdef TARGET_WIN32
6947                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6948 #endif
6949         }
6950
6951         /* The param area is always at offset 0 from sp */
6952         /* This needs to be allocated here, since it has to come after the spill area */
6953         if (cfg->param_area) {
6954                 if (cfg->arch.omit_fp)
6955                         // FIXME:
6956                         g_assert_not_reached ();
6957                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6958         }
6959
6960         if (cfg->arch.omit_fp) {
6961                 /*
6962                  * On enter, the stack is misaligned by the pushing of the return
6963                  * address. It is either made aligned by the pushing of %rbp, or by
6964                  * this.
6965                  */
6966                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6967                 if ((alloc_size % 16) == 0) {
6968                         alloc_size += 8;
6969                         /* Mark the padding slot as NOREF */
6970                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6971                 }
6972         } else {
6973                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6974                 if (cfg->stack_offset != alloc_size) {
6975                         /* Mark the padding slot as NOREF */
6976                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6977                 }
6978                 cfg->arch.sp_fp_offset = alloc_size;
6979                 alloc_size -= pos;
6980         }
6981
6982         cfg->arch.stack_alloc_size = alloc_size;
6983
6984         /* Allocate stack frame */
6985         if (alloc_size) {
6986                 /* See mono_emit_stack_alloc */
6987 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6988                 guint32 remaining_size = alloc_size;
6989                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6990                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6991                 guint32 offset = code - cfg->native_code;
6992                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6993                         while (required_code_size >= (cfg->code_size - offset))
6994                                 cfg->code_size *= 2;
6995                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6996                         code = cfg->native_code + offset;
6997                         cfg->stat_code_reallocs++;
6998                 }
6999
7000                 while (remaining_size >= 0x1000) {
7001                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
7002                         if (cfg->arch.omit_fp) {
7003                                 cfa_offset += 0x1000;
7004                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7005                         }
7006                         async_exc_point (code);
7007 #ifdef TARGET_WIN32
7008                         if (cfg->arch.omit_fp)
7009                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
7010 #endif
7011
7012                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
7013                         remaining_size -= 0x1000;
7014                 }
7015                 if (remaining_size) {
7016                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7017                         if (cfg->arch.omit_fp) {
7018                                 cfa_offset += remaining_size;
7019                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7020                                 async_exc_point (code);
7021                         }
7022 #ifdef TARGET_WIN32
7023                         if (cfg->arch.omit_fp)
7024                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7025 #endif
7026                 }
7027 #else
7028                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7029                 if (cfg->arch.omit_fp) {
7030                         cfa_offset += alloc_size;
7031                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7032                         async_exc_point (code);
7033                 }
7034 #endif
7035         }
7036
7037         /* Stack alignment check */
7038 #if 0
7039         {
7040                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7041                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7042                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7043                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
7044                 amd64_breakpoint (code);
7045         }
7046 #endif
7047
7048         if (mini_get_debug_options ()->init_stacks) {
7049                 /* Fill the stack frame with a dummy value to force deterministic behavior */
7050
7051                 /* Save registers to the red zone */
7052                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7053                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7054
7055                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7056                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7057                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7058
7059                 amd64_cld (code);
7060 #if defined(__default_codegen__)
7061                 amd64_prefix (code, X86_REP_PREFIX);
7062                 amd64_stosl (code);
7063 #elif defined(__native_client_codegen__)
7064                 /* NaCl stos pseudo-instruction */
7065                 amd64_codegen_pre (code);
7066                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
7067                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7068                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7069                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7070                 amd64_prefix (code, X86_REP_PREFIX);
7071                 amd64_stosl (code);
7072                 amd64_codegen_post (code);
7073 #endif /* __native_client_codegen__ */
7074
7075                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7076                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7077         }
7078
7079         /* Save LMF */
7080         if (method->save_lmf)
7081                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7082
7083         /* Save callee saved registers */
7084         if (cfg->arch.omit_fp) {
7085                 save_area_offset = cfg->arch.reg_save_area_offset;
7086                 /* Save caller saved registers after sp is adjusted */
7087                 /* The registers are saved at the bottom of the frame */
7088                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7089         } else {
7090                 /* The registers are saved just below the saved rbp */
7091                 save_area_offset = cfg->arch.reg_save_area_offset;
7092         }
7093
7094         for (i = 0; i < AMD64_NREG; ++i) {
7095                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7096                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7097
7098                         if (cfg->arch.omit_fp) {
7099                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7100                                 /* These are handled automatically by the stack marking code */
7101                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7102                         } else {
7103                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7104                                 // FIXME: GC
7105                         }
7106
7107                         save_area_offset += 8;
7108                         async_exc_point (code);
7109                 }
7110         }
7111
7112         /* store runtime generic context */
7113         if (cfg->rgctx_var) {
7114                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7115                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7116
7117                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7118
7119                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7120                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7121         }
7122
7123         /* compute max_length in order to use short forward jumps */
7124         max_epilog_size = get_max_epilog_size (cfg);
7125         if (cfg->opt & MONO_OPT_BRANCH) {
7126                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7127                         MonoInst *ins;
7128                         int max_length = 0;
7129
7130                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7131                                 max_length += 6;
7132                         /* max alignment for loops */
7133                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7134                                 max_length += LOOP_ALIGNMENT;
7135 #ifdef __native_client_codegen__
7136                         /* max alignment for native client */
7137                         max_length += kNaClAlignment;
7138 #endif
7139
7140                         MONO_BB_FOR_EACH_INS (bb, ins) {
7141 #ifdef __native_client_codegen__
7142                                 {
7143                                         int space_in_block = kNaClAlignment -
7144                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7145                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7146                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7147                                                 max_length += space_in_block;
7148                                         }
7149                                 }
7150 #endif  /*__native_client_codegen__*/
7151                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7152                         }
7153
7154                         /* Take prolog and epilog instrumentation into account */
7155                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7156                                 max_length += max_epilog_size;
7157
7158                         bb->max_length = max_length;
7159                 }
7160         }
7161
7162         sig = mono_method_signature (method);
7163         pos = 0;
7164
7165         cinfo = (CallInfo *)cfg->arch.cinfo;
7166
7167         if (sig->ret->type != MONO_TYPE_VOID) {
7168                 /* Save volatile arguments to the stack */
7169                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7170                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7171         }
7172
7173         /* Keep this in sync with emit_load_volatile_arguments */
7174         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7175                 ArgInfo *ainfo = cinfo->args + i;
7176
7177                 ins = cfg->args [i];
7178
7179                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7180                         /* Unused arguments */
7181                         continue;
7182
7183                 /* Save volatile arguments to the stack */
7184                 if (ins->opcode != OP_REGVAR) {
7185                         switch (ainfo->storage) {
7186                         case ArgInIReg: {
7187                                 guint32 size = 8;
7188
7189                                 /* FIXME: I1 etc */
7190                                 /*
7191                                 if (stack_offset & 0x1)
7192                                         size = 1;
7193                                 else if (stack_offset & 0x2)
7194                                         size = 2;
7195                                 else if (stack_offset & 0x4)
7196                                         size = 4;
7197                                 else
7198                                         size = 8;
7199                                 */
7200                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7201
7202                                 /*
7203                                  * Save the original location of 'this',
7204                                  * get_generic_info_from_stack_frame () needs this to properly look up
7205                                  * the argument value during the handling of async exceptions.
7206                                  */
7207                                 if (ins == cfg->args [0]) {
7208                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7209                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7210                                 }
7211                                 break;
7212                         }
7213                         case ArgInFloatSSEReg:
7214                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7215                                 break;
7216                         case ArgInDoubleSSEReg:
7217                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7218                                 break;
7219                         case ArgValuetypeInReg:
7220                                 for (quad = 0; quad < 2; quad ++) {
7221                                         switch (ainfo->pair_storage [quad]) {
7222                                         case ArgInIReg:
7223                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7224                                                 break;
7225                                         case ArgInFloatSSEReg:
7226                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7227                                                 break;
7228                                         case ArgInDoubleSSEReg:
7229                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7230                                                 break;
7231                                         case ArgNone:
7232                                                 break;
7233                                         default:
7234                                                 g_assert_not_reached ();
7235                                         }
7236                                 }
7237                                 break;
7238                         case ArgValuetypeAddrInIReg:
7239                                 if (ainfo->pair_storage [0] == ArgInIReg)
7240                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7241                                 break;
7242                         default:
7243                                 break;
7244                         }
7245                 } else {
7246                         /* Argument allocated to (non-volatile) register */
7247                         switch (ainfo->storage) {
7248                         case ArgInIReg:
7249                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7250                                 break;
7251                         case ArgOnStack:
7252                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7253                                 break;
7254                         default:
7255                                 g_assert_not_reached ();
7256                         }
7257
7258                         if (ins == cfg->args [0]) {
7259                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7260                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7261                         }
7262                 }
7263         }
7264
7265         if (cfg->method->save_lmf)
7266                 args_clobbered = TRUE;
7267
7268         if (trace) {
7269                 args_clobbered = TRUE;
7270                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7271         }
7272
7273         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7274                 args_clobbered = TRUE;
7275
7276         /*
7277          * Optimize the common case of the first bblock making a call with the same
7278          * arguments as the method. This works because the arguments are still in their
7279          * original argument registers.
7280          * FIXME: Generalize this
7281          */
7282         if (!args_clobbered) {
7283                 MonoBasicBlock *first_bb = cfg->bb_entry;
7284                 MonoInst *next;
7285                 int filter = FILTER_IL_SEQ_POINT;
7286
7287                 next = mono_bb_first_inst (first_bb, filter);
7288                 if (!next && first_bb->next_bb) {
7289                         first_bb = first_bb->next_bb;
7290                         next = mono_bb_first_inst (first_bb, filter);
7291                 }
7292
7293                 if (first_bb->in_count > 1)
7294                         next = NULL;
7295
7296                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7297                         ArgInfo *ainfo = cinfo->args + i;
7298                         gboolean match = FALSE;
7299
7300                         ins = cfg->args [i];
7301                         if (ins->opcode != OP_REGVAR) {
7302                                 switch (ainfo->storage) {
7303                                 case ArgInIReg: {
7304                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7305                                                 if (next->dreg == ainfo->reg) {
7306                                                         NULLIFY_INS (next);
7307                                                         match = TRUE;
7308                                                 } else {
7309                                                         next->opcode = OP_MOVE;
7310                                                         next->sreg1 = ainfo->reg;
7311                                                         /* Only continue if the instruction doesn't change argument regs */
7312                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7313                                                                 match = TRUE;
7314                                                 }
7315                                         }
7316                                         break;
7317                                 }
7318                                 default:
7319                                         break;
7320                                 }
7321                         } else {
7322                                 /* Argument allocated to (non-volatile) register */
7323                                 switch (ainfo->storage) {
7324                                 case ArgInIReg:
7325                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7326                                                 NULLIFY_INS (next);
7327                                                 match = TRUE;
7328                                         }
7329                                         break;
7330                                 default:
7331                                         break;
7332                                 }
7333                         }
7334
7335                         if (match) {
7336                                 next = mono_inst_next (next, filter);
7337                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7338                                 if (!next)
7339                                         break;
7340                         }
7341                 }
7342         }
7343
7344         if (cfg->gen_sdb_seq_points) {
7345                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7346
7347                 /* Initialize seq_point_info_var */
7348                 if (cfg->compile_aot) {
7349                         /* Initialize the variable from a GOT slot */
7350                         /* Same as OP_AOTCONST */
7351                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7352                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7353                         g_assert (info_var->opcode == OP_REGOFFSET);
7354                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7355                 }
7356
7357                 if (cfg->compile_aot) {
7358                         /* Initialize ss_tramp_var */
7359                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7360                         g_assert (ins->opcode == OP_REGOFFSET);
7361
7362                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7363                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7364                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7365                 } else {
7366                         /* Initialize ss_tramp_var */
7367                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7368                         g_assert (ins->opcode == OP_REGOFFSET);
7369
7370                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7371                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7372
7373                         /* Initialize bp_tramp_var */
7374                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7375                         g_assert (ins->opcode == OP_REGOFFSET);
7376
7377                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7378                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7379                 }
7380         }
7381
7382         cfg->code_len = code - cfg->native_code;
7383
7384         g_assert (cfg->code_len < cfg->code_size);
7385
7386         return code;
7387 }
7388
7389 void
7390 mono_arch_emit_epilog (MonoCompile *cfg)
7391 {
7392         MonoMethod *method = cfg->method;
7393         int quad, i;
7394         guint8 *code;
7395         int max_epilog_size;
7396         CallInfo *cinfo;
7397         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7398         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7399
7400         max_epilog_size = get_max_epilog_size (cfg);
7401
7402         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7403                 cfg->code_size *= 2;
7404                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7405                 cfg->stat_code_reallocs++;
7406         }
7407         code = cfg->native_code + cfg->code_len;
7408
7409         cfg->has_unwind_info_for_epilog = TRUE;
7410
7411         /* Mark the start of the epilog */
7412         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7413
7414         /* Save the uwind state which is needed by the out-of-line code */
7415         mono_emit_unwind_op_remember_state (cfg, code);
7416
7417         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7418                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7419
7420         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7421
7422         if (method->save_lmf) {
7423                 /* check if we need to restore protection of the stack after a stack overflow */
7424                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7425                         guint8 *patch;
7426                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7427                         /* we load the value in a separate instruction: this mechanism may be
7428                          * used later as a safer way to do thread interruption
7429                          */
7430                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7431                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7432                         patch = code;
7433                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7434                         /* note that the call trampoline will preserve eax/edx */
7435                         x86_call_reg (code, X86_ECX);
7436                         x86_patch (patch, code);
7437                 } else {
7438                         /* FIXME: maybe save the jit tls in the prolog */
7439                 }
7440                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7441                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7442                 }
7443         }
7444
7445         /* Restore callee saved regs */
7446         for (i = 0; i < AMD64_NREG; ++i) {
7447                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7448                         /* Restore only used_int_regs, not arch.saved_iregs */
7449                         if (cfg->used_int_regs & (1 << i)) {
7450                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7451                                 mono_emit_unwind_op_same_value (cfg, code, i);
7452                                 async_exc_point (code);
7453                         }
7454                         save_area_offset += 8;
7455                 }
7456         }
7457
7458         /* Load returned vtypes into registers if needed */
7459         cinfo = (CallInfo *)cfg->arch.cinfo;
7460         if (cinfo->ret.storage == ArgValuetypeInReg) {
7461                 ArgInfo *ainfo = &cinfo->ret;
7462                 MonoInst *inst = cfg->ret;
7463
7464                 for (quad = 0; quad < 2; quad ++) {
7465                         switch (ainfo->pair_storage [quad]) {
7466                         case ArgInIReg:
7467                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7468                                 break;
7469                         case ArgInFloatSSEReg:
7470                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7471                                 break;
7472                         case ArgInDoubleSSEReg:
7473                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7474                                 break;
7475                         case ArgNone:
7476                                 break;
7477                         default:
7478                                 g_assert_not_reached ();
7479                         }
7480                 }
7481         }
7482
7483         if (cfg->arch.omit_fp) {
7484                 if (cfg->arch.stack_alloc_size) {
7485                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7486                 }
7487         } else {
7488                 amd64_leave (code);
7489                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7490         }
7491         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7492         async_exc_point (code);
7493         amd64_ret (code);
7494
7495         /* Restore the unwind state to be the same as before the epilog */
7496         mono_emit_unwind_op_restore_state (cfg, code);
7497
7498         cfg->code_len = code - cfg->native_code;
7499
7500         g_assert (cfg->code_len < cfg->code_size);
7501 }
7502
7503 void
7504 mono_arch_emit_exceptions (MonoCompile *cfg)
7505 {
7506         MonoJumpInfo *patch_info;
7507         int nthrows, i;
7508         guint8 *code;
7509         MonoClass *exc_classes [16];
7510         guint8 *exc_throw_start [16], *exc_throw_end [16];
7511         guint32 code_size = 0;
7512
7513         /* Compute needed space */
7514         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7515                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7516                         code_size += 40;
7517                 if (patch_info->type == MONO_PATCH_INFO_R8)
7518                         code_size += 8 + 15; /* sizeof (double) + alignment */
7519                 if (patch_info->type == MONO_PATCH_INFO_R4)
7520                         code_size += 4 + 15; /* sizeof (float) + alignment */
7521                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7522                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7523         }
7524
7525 #ifdef __native_client_codegen__
7526         /* Give us extra room on Native Client.  This could be   */
7527         /* more carefully calculated, but bundle alignment makes */
7528         /* it much trickier, so *2 like other places is good.    */
7529         code_size *= 2;
7530 #endif
7531
7532         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7533                 cfg->code_size *= 2;
7534                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7535                 cfg->stat_code_reallocs++;
7536         }
7537
7538         code = cfg->native_code + cfg->code_len;
7539
7540         /* add code to raise exceptions */
7541         nthrows = 0;
7542         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7543                 switch (patch_info->type) {
7544                 case MONO_PATCH_INFO_EXC: {
7545                         MonoClass *exc_class;
7546                         guint8 *buf, *buf2;
7547                         guint32 throw_ip;
7548
7549                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7550
7551                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7552                         g_assert (exc_class);
7553                         throw_ip = patch_info->ip.i;
7554
7555                         //x86_breakpoint (code);
7556                         /* Find a throw sequence for the same exception class */
7557                         for (i = 0; i < nthrows; ++i)
7558                                 if (exc_classes [i] == exc_class)
7559                                         break;
7560                         if (i < nthrows) {
7561                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7562                                 x86_jump_code (code, exc_throw_start [i]);
7563                                 patch_info->type = MONO_PATCH_INFO_NONE;
7564                         }
7565                         else {
7566                                 buf = code;
7567                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7568                                 buf2 = code;
7569
7570                                 if (nthrows < 16) {
7571                                         exc_classes [nthrows] = exc_class;
7572                                         exc_throw_start [nthrows] = code;
7573                                 }
7574                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7575
7576                                 patch_info->type = MONO_PATCH_INFO_NONE;
7577
7578                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7579
7580                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7581                                 while (buf < buf2)
7582                                         x86_nop (buf);
7583
7584                                 if (nthrows < 16) {
7585                                         exc_throw_end [nthrows] = code;
7586                                         nthrows ++;
7587                                 }
7588                         }
7589                         break;
7590                 }
7591                 default:
7592                         /* do nothing */
7593                         break;
7594                 }
7595                 g_assert(code < cfg->native_code + cfg->code_size);
7596         }
7597
7598         /* Handle relocations with RIP relative addressing */
7599         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7600                 gboolean remove = FALSE;
7601                 guint8 *orig_code = code;
7602
7603                 switch (patch_info->type) {
7604                 case MONO_PATCH_INFO_R8:
7605                 case MONO_PATCH_INFO_R4: {
7606                         guint8 *pos, *patch_pos;
7607                         guint32 target_pos;
7608
7609                         /* The SSE opcodes require a 16 byte alignment */
7610 #if defined(__default_codegen__)
7611                         code = (guint8*)ALIGN_TO (code, 16);
7612 #elif defined(__native_client_codegen__)
7613                         {
7614                                 /* Pad this out with HLT instructions  */
7615                                 /* or we can get garbage bytes emitted */
7616                                 /* which will fail validation          */
7617                                 guint8 *aligned_code;
7618                                 /* extra align to make room for  */
7619                                 /* mov/push below                      */
7620                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7621                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7622                                 /* The technique of hiding data in an  */
7623                                 /* instruction has a problem here: we  */
7624                                 /* need the data aligned to a 16-byte  */
7625                                 /* boundary but the instruction cannot */
7626                                 /* cross the bundle boundary. so only  */
7627                                 /* odd multiples of 16 can be used     */
7628                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7629                                         aligned_code += 16;
7630                                 }
7631                                 while (code < aligned_code) {
7632                                         *(code++) = 0xf4; /* hlt */
7633                                 }
7634                         }
7635 #endif
7636
7637                         pos = cfg->native_code + patch_info->ip.i;
7638                         if (IS_REX (pos [1])) {
7639                                 patch_pos = pos + 5;
7640                                 target_pos = code - pos - 9;
7641                         }
7642                         else {
7643                                 patch_pos = pos + 4;
7644                                 target_pos = code - pos - 8;
7645                         }
7646
7647                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7648 #ifdef __native_client_codegen__
7649                                 /* Hide 64-bit data in a         */
7650                                 /* "mov imm64, r11" instruction. */
7651                                 /* write it before the start of  */
7652                                 /* the data*/
7653                                 *(code-2) = 0x49; /* prefix      */
7654                                 *(code-1) = 0xbb; /* mov X, %r11 */
7655 #endif
7656                                 *(double*)code = *(double*)patch_info->data.target;
7657                                 code += sizeof (double);
7658                         } else {
7659 #ifdef __native_client_codegen__
7660                                 /* Hide 32-bit data in a        */
7661                                 /* "push imm32" instruction.    */
7662                                 *(code-1) = 0x68; /* push */
7663 #endif
7664                                 *(float*)code = *(float*)patch_info->data.target;
7665                                 code += sizeof (float);
7666                         }
7667
7668                         *(guint32*)(patch_pos) = target_pos;
7669
7670                         remove = TRUE;
7671                         break;
7672                 }
7673                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7674                         guint8 *pos;
7675
7676                         if (cfg->compile_aot)
7677                                 continue;
7678
7679                         /*loading is faster against aligned addresses.*/
7680                         code = (guint8*)ALIGN_TO (code, 8);
7681                         memset (orig_code, 0, code - orig_code);
7682
7683                         pos = cfg->native_code + patch_info->ip.i;
7684
7685                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7686                         if (IS_REX (pos [1]))
7687                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7688                         else
7689                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7690
7691                         *(gpointer*)code = (gpointer)patch_info->data.target;
7692                         code += sizeof (gpointer);
7693
7694                         remove = TRUE;
7695                         break;
7696                 }
7697                 default:
7698                         break;
7699                 }
7700
7701                 if (remove) {
7702                         if (patch_info == cfg->patch_info)
7703                                 cfg->patch_info = patch_info->next;
7704                         else {
7705                                 MonoJumpInfo *tmp;
7706
7707                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7708                                         ;
7709                                 tmp->next = patch_info->next;
7710                         }
7711                 }
7712                 g_assert (code < cfg->native_code + cfg->code_size);
7713         }
7714
7715         cfg->code_len = code - cfg->native_code;
7716
7717         g_assert (cfg->code_len < cfg->code_size);
7718
7719 }
7720
7721 #endif /* DISABLE_JIT */
7722
7723 void*
7724 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7725 {
7726         guchar *code = (guchar *)p;
7727         MonoMethodSignature *sig;
7728         MonoInst *inst;
7729         int i, n, stack_area = 0;
7730
7731         /* Keep this in sync with mono_arch_get_argument_info */
7732
7733         if (enable_arguments) {
7734                 /* Allocate a new area on the stack and save arguments there */
7735                 sig = mono_method_signature (cfg->method);
7736
7737                 n = sig->param_count + sig->hasthis;
7738
7739                 stack_area = ALIGN_TO (n * 8, 16);
7740
7741                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7742
7743                 for (i = 0; i < n; ++i) {
7744                         inst = cfg->args [i];
7745
7746                         if (inst->opcode == OP_REGVAR)
7747                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7748                         else {
7749                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7750                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7751                         }
7752                 }
7753         }
7754
7755         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7756         amd64_set_reg_template (code, AMD64_ARG_REG1);
7757         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7758         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7759
7760         if (enable_arguments)
7761                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7762
7763         return code;
7764 }
7765
7766 enum {
7767         SAVE_NONE,
7768         SAVE_STRUCT,
7769         SAVE_EAX,
7770         SAVE_EAX_EDX,
7771         SAVE_XMM
7772 };
7773
7774 void*
7775 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7776 {
7777         guchar *code = (guchar *)p;
7778         int save_mode = SAVE_NONE;
7779         MonoMethod *method = cfg->method;
7780         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7781         int i;
7782
7783         switch (ret_type->type) {
7784         case MONO_TYPE_VOID:
7785                 /* special case string .ctor icall */
7786                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7787                         save_mode = SAVE_EAX;
7788                 else
7789                         save_mode = SAVE_NONE;
7790                 break;
7791         case MONO_TYPE_I8:
7792         case MONO_TYPE_U8:
7793                 save_mode = SAVE_EAX;
7794                 break;
7795         case MONO_TYPE_R4:
7796         case MONO_TYPE_R8:
7797                 save_mode = SAVE_XMM;
7798                 break;
7799         case MONO_TYPE_GENERICINST:
7800                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7801                         save_mode = SAVE_EAX;
7802                         break;
7803                 }
7804                 /* Fall through */
7805         case MONO_TYPE_VALUETYPE:
7806                 save_mode = SAVE_STRUCT;
7807                 break;
7808         default:
7809                 save_mode = SAVE_EAX;
7810                 break;
7811         }
7812
7813         /* Save the result and copy it into the proper argument register */
7814         switch (save_mode) {
7815         case SAVE_EAX:
7816                 amd64_push_reg (code, AMD64_RAX);
7817                 /* Align stack */
7818                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7819                 if (enable_arguments)
7820                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7821                 break;
7822         case SAVE_STRUCT:
7823                 /* FIXME: */
7824                 if (enable_arguments)
7825                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7826                 break;
7827         case SAVE_XMM:
7828                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7829                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7830                 /* Align stack */
7831                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7832                 /*
7833                  * The result is already in the proper argument register so no copying
7834                  * needed.
7835                  */
7836                 break;
7837         case SAVE_NONE:
7838                 break;
7839         default:
7840                 g_assert_not_reached ();
7841         }
7842
7843         /* Set %al since this is a varargs call */
7844         if (save_mode == SAVE_XMM)
7845                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7846         else
7847                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7848
7849         if (preserve_argument_registers) {
7850                 for (i = 0; i < PARAM_REGS; ++i)
7851                         amd64_push_reg (code, param_regs [i]);
7852         }
7853
7854         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7855         amd64_set_reg_template (code, AMD64_ARG_REG1);
7856         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7857
7858         if (preserve_argument_registers) {
7859                 for (i = PARAM_REGS - 1; i >= 0; --i)
7860                         amd64_pop_reg (code, param_regs [i]);
7861         }
7862
7863         /* Restore result */
7864         switch (save_mode) {
7865         case SAVE_EAX:
7866                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7867                 amd64_pop_reg (code, AMD64_RAX);
7868                 break;
7869         case SAVE_STRUCT:
7870                 /* FIXME: */
7871                 break;
7872         case SAVE_XMM:
7873                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7874                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7875                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7876                 break;
7877         case SAVE_NONE:
7878                 break;
7879         default:
7880                 g_assert_not_reached ();
7881         }
7882
7883         return code;
7884 }
7885
7886 void
7887 mono_arch_flush_icache (guint8 *code, gint size)
7888 {
7889         /* Not needed */
7890 }
7891
7892 void
7893 mono_arch_flush_register_windows (void)
7894 {
7895 }
7896
7897 gboolean
7898 mono_arch_is_inst_imm (gint64 imm)
7899 {
7900         return amd64_use_imm32 (imm);
7901 }
7902
7903 /*
7904  * Determine whenever the trap whose info is in SIGINFO is caused by
7905  * integer overflow.
7906  */
7907 gboolean
7908 mono_arch_is_int_overflow (void *sigctx, void *info)
7909 {
7910         MonoContext ctx;
7911         guint8* rip;
7912         int reg;
7913         gint64 value;
7914
7915         mono_sigctx_to_monoctx (sigctx, &ctx);
7916
7917         rip = (guint8*)ctx.gregs [AMD64_RIP];
7918
7919         if (IS_REX (rip [0])) {
7920                 reg = amd64_rex_b (rip [0]);
7921                 rip ++;
7922         }
7923         else
7924                 reg = 0;
7925
7926         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7927                 /* idiv REG */
7928                 reg += x86_modrm_rm (rip [1]);
7929
7930                 value = ctx.gregs [reg];
7931
7932                 if (value == -1)
7933                         return TRUE;
7934         }
7935
7936         return FALSE;
7937 }
7938
7939 guint32
7940 mono_arch_get_patch_offset (guint8 *code)
7941 {
7942         return 3;
7943 }
7944
7945 /**
7946  * mono_breakpoint_clean_code:
7947  *
7948  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7949  * breakpoints in the original code, they are removed in the copy.
7950  *
7951  * Returns TRUE if no sw breakpoint was present.
7952  */
7953 gboolean
7954 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7955 {
7956         /*
7957          * If method_start is non-NULL we need to perform bound checks, since we access memory
7958          * at code - offset we could go before the start of the method and end up in a different
7959          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7960          * instead.
7961          */
7962         if (!method_start || code - offset >= method_start) {
7963                 memcpy (buf, code - offset, size);
7964         } else {
7965                 int diff = code - method_start;
7966                 memset (buf, 0, size);
7967                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7968         }
7969         return TRUE;
7970 }
7971
7972 #if defined(__native_client_codegen__)
7973 /* For membase calls, we want the base register. for Native Client,  */
7974 /* all indirect calls have the following sequence with the given sizes: */
7975 /* mov %eXX,%eXX                                [2-3]   */
7976 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7977 /* and $0xffffffffffffffe0,%r11d                [4]     */
7978 /* add %r15,%r11                                [3]     */
7979 /* callq *%r11                                  [3]     */
7980
7981
7982 /* Determine if code points to a NaCl call-through-register sequence, */
7983 /* (i.e., the last 3 instructions listed above) */
7984 int
7985 is_nacl_call_reg_sequence(guint8* code)
7986 {
7987         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7988                                "\x4d\x03\xdf"     /* add */
7989                                "\x41\xff\xd3";   /* call */
7990         return memcmp(code, sequence, 10) == 0;
7991 }
7992
7993 /* Determine if code points to the first opcode of the mov membase component */
7994 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7995 /* (there could be a REX prefix before the opcode but it is ignored) */
7996 static int
7997 is_nacl_indirect_call_membase_sequence(guint8* code)
7998 {
7999                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
8000         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
8001                /* and that src reg = dest reg */
8002                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
8003                /* Check that next inst is mov, uses SIB byte (rm = 4), */
8004                IS_REX(code[2]) &&
8005                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
8006                /* and has dst of r11 and base of r15 */
8007                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
8008                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
8009 }
8010 #endif /* __native_client_codegen__ */
8011
8012 int
8013 mono_arch_get_this_arg_reg (guint8 *code)
8014 {
8015         return AMD64_ARG_REG1;
8016 }
8017
8018 gpointer
8019 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8020 {
8021         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8022 }
8023
8024 #define MAX_ARCH_DELEGATE_PARAMS 10
8025
8026 static gpointer
8027 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8028 {
8029         guint8 *code, *start;
8030         GSList *unwind_ops = NULL;
8031         int i;
8032
8033         unwind_ops = mono_arch_get_cie_program ();
8034
8035         if (has_target) {
8036                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8037
8038                 /* Replace the this argument with the target */
8039                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8040                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8041                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8042
8043                 g_assert ((code - start) < 64);
8044         } else {
8045                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8046
8047                 if (param_count == 0) {
8048                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8049                 } else {
8050                         /* We have to shift the arguments left */
8051                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8052                         for (i = 0; i < param_count; ++i) {
8053 #ifdef TARGET_WIN32
8054                                 if (i < 3)
8055                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8056                                 else
8057                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8058 #else
8059                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8060 #endif
8061                         }
8062
8063                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8064                 }
8065                 g_assert ((code - start) < 64);
8066         }
8067
8068         nacl_global_codeman_validate (&start, 64, &code);
8069         mono_arch_flush_icache (start, code - start);
8070
8071         if (has_target) {
8072                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8073         } else {
8074                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8075                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8076                 g_free (name);
8077         }
8078
8079         if (mono_jit_map_is_enabled ()) {
8080                 char *buff;
8081                 if (has_target)
8082                         buff = (char*)"delegate_invoke_has_target";
8083                 else
8084                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8085                 mono_emit_jit_tramp (start, code - start, buff);
8086                 if (!has_target)
8087                         g_free (buff);
8088         }
8089         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8090
8091         return start;
8092 }
8093
8094 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8095
8096 static gpointer
8097 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8098 {
8099         guint8 *code, *start;
8100         int size = 20;
8101         char *tramp_name;
8102         GSList *unwind_ops;
8103
8104         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8105                 return NULL;
8106
8107         start = code = (guint8 *)mono_global_codeman_reserve (size);
8108
8109         unwind_ops = mono_arch_get_cie_program ();
8110
8111         /* Replace the this argument with the target */
8112         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8113         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8114
8115         if (load_imt_reg) {
8116                 /* Load the IMT reg */
8117                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8118         }
8119
8120         /* Load the vtable */
8121         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8122         amd64_jump_membase (code, AMD64_RAX, offset);
8123         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8124
8125         if (load_imt_reg)
8126                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8127         else
8128                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8129         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8130         g_free (tramp_name);
8131
8132         return start;
8133 }
8134
8135 /*
8136  * mono_arch_get_delegate_invoke_impls:
8137  *
8138  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8139  * trampolines.
8140  */
8141 GSList*
8142 mono_arch_get_delegate_invoke_impls (void)
8143 {
8144         GSList *res = NULL;
8145         MonoTrampInfo *info;
8146         int i;
8147
8148         get_delegate_invoke_impl (&info, TRUE, 0);
8149         res = g_slist_prepend (res, info);
8150
8151         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8152                 get_delegate_invoke_impl (&info, FALSE, i);
8153                 res = g_slist_prepend (res, info);
8154         }
8155
8156         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8157                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8158                 res = g_slist_prepend (res, info);
8159
8160                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8161                 res = g_slist_prepend (res, info);
8162         }
8163
8164         return res;
8165 }
8166
8167 gpointer
8168 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8169 {
8170         guint8 *code, *start;
8171         int i;
8172
8173         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8174                 return NULL;
8175
8176         /* FIXME: Support more cases */
8177         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8178                 return NULL;
8179
8180         if (has_target) {
8181                 static guint8* cached = NULL;
8182
8183                 if (cached)
8184                         return cached;
8185
8186                 if (mono_aot_only) {
8187                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8188                 } else {
8189                         MonoTrampInfo *info;
8190                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
8191                         mono_tramp_info_register (info, NULL);
8192                 }
8193
8194                 mono_memory_barrier ();
8195
8196                 cached = start;
8197         } else {
8198                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8199                 for (i = 0; i < sig->param_count; ++i)
8200                         if (!mono_is_regsize_var (sig->params [i]))
8201                                 return NULL;
8202                 if (sig->param_count > 4)
8203                         return NULL;
8204
8205                 code = cache [sig->param_count];
8206                 if (code)
8207                         return code;
8208
8209                 if (mono_aot_only) {
8210                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8211                         start = (guint8 *)mono_aot_get_trampoline (name);
8212                         g_free (name);
8213                 } else {
8214                         MonoTrampInfo *info;
8215                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8216                         mono_tramp_info_register (info, NULL);
8217                 }
8218
8219                 mono_memory_barrier ();
8220
8221                 cache [sig->param_count] = start;
8222         }
8223
8224         return start;
8225 }
8226
8227 gpointer
8228 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8229 {
8230         MonoTrampInfo *info;
8231         gpointer code;
8232
8233         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8234         if (code)
8235                 mono_tramp_info_register (info, NULL);
8236         return code;
8237 }
8238
8239 void
8240 mono_arch_finish_init (void)
8241 {
8242 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8243         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8244 #endif
8245 }
8246
8247 void
8248 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8249 {
8250 }
8251
8252 #if defined(__default_codegen__)
8253 #define CMP_SIZE (6 + 1)
8254 #define CMP_REG_REG_SIZE (4 + 1)
8255 #define BR_SMALL_SIZE 2
8256 #define BR_LARGE_SIZE 6
8257 #define MOV_REG_IMM_SIZE 10
8258 #define MOV_REG_IMM_32BIT_SIZE 6
8259 #define JUMP_REG_SIZE (2 + 1)
8260 #elif defined(__native_client_codegen__)
8261 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8262 #define CMP_SIZE ((6 + 1) * 2 - 1)
8263 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8264 #define BR_SMALL_SIZE (2 * 2 - 1)
8265 #define BR_LARGE_SIZE (6 * 2 - 1)
8266 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8267 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8268 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8269 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8270 /* Jump membase's size is large and unpredictable    */
8271 /* in native client, just pad it out a whole bundle. */
8272 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8273 #endif
8274
8275 static int
8276 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8277 {
8278         int i, distance = 0;
8279         for (i = start; i < target; ++i)
8280                 distance += imt_entries [i]->chunk_size;
8281         return distance;
8282 }
8283
8284 /*
8285  * LOCKING: called with the domain lock held
8286  */
8287 gpointer
8288 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8289         gpointer fail_tramp)
8290 {
8291         int i;
8292         int size = 0;
8293         guint8 *code, *start;
8294         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8295         GSList *unwind_ops;
8296
8297         for (i = 0; i < count; ++i) {
8298                 MonoIMTCheckItem *item = imt_entries [i];
8299                 if (item->is_equals) {
8300                         if (item->check_target_idx) {
8301                                 if (!item->compare_done) {
8302                                         if (amd64_use_imm32 ((gint64)item->key))
8303                                                 item->chunk_size += CMP_SIZE;
8304                                         else
8305                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8306                                 }
8307                                 if (item->has_target_code) {
8308                                         item->chunk_size += MOV_REG_IMM_SIZE;
8309                                 } else {
8310                                         if (vtable_is_32bit)
8311                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8312                                         else
8313                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8314 #ifdef __native_client_codegen__
8315                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8316 #endif
8317                                 }
8318                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8319                         } else {
8320                                 if (fail_tramp) {
8321                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8322                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8323                                 } else {
8324                                         if (vtable_is_32bit)
8325                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8326                                         else
8327                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8328                                         item->chunk_size += JUMP_REG_SIZE;
8329                                         /* with assert below:
8330                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8331                                          */
8332 #ifdef __native_client_codegen__
8333                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8334 #endif
8335                                 }
8336                         }
8337                 } else {
8338                         if (amd64_use_imm32 ((gint64)item->key))
8339                                 item->chunk_size += CMP_SIZE;
8340                         else
8341                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8342                         item->chunk_size += BR_LARGE_SIZE;
8343                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8344                 }
8345                 size += item->chunk_size;
8346         }
8347 #if defined(__native_client__) && defined(__native_client_codegen__)
8348         /* In Native Client, we don't re-use thunks, allocate from the */
8349         /* normal code manager paths. */
8350         code = mono_domain_code_reserve (domain, size);
8351 #else
8352         if (fail_tramp)
8353                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8354         else
8355                 code = (guint8 *)mono_domain_code_reserve (domain, size);
8356 #endif
8357         start = code;
8358
8359         unwind_ops = mono_arch_get_cie_program ();
8360
8361         for (i = 0; i < count; ++i) {
8362                 MonoIMTCheckItem *item = imt_entries [i];
8363                 item->code_target = code;
8364                 if (item->is_equals) {
8365                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8366
8367                         if (item->check_target_idx || fail_case) {
8368                                 if (!item->compare_done || fail_case) {
8369                                         if (amd64_use_imm32 ((gint64)item->key))
8370                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8371                                         else {
8372                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8373                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8374                                         }
8375                                 }
8376                                 item->jmp_code = code;
8377                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8378                                 if (item->has_target_code) {
8379                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8380                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8381                                 } else {
8382                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8383                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8384                                 }
8385
8386                                 if (fail_case) {
8387                                         amd64_patch (item->jmp_code, code);
8388                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8389                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8390                                         item->jmp_code = NULL;
8391                                 }
8392                         } else {
8393                                 /* enable the commented code to assert on wrong method */
8394 #if 0
8395                                 if (amd64_is_imm32 (item->key))
8396                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8397                                 else {
8398                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8399                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8400                                 }
8401                                 item->jmp_code = code;
8402                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8403                                 /* See the comment below about R10 */
8404                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8405                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8406                                 amd64_patch (item->jmp_code, code);
8407                                 amd64_breakpoint (code);
8408                                 item->jmp_code = NULL;
8409 #else
8410                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8411                                    needs to be preserved.  R10 needs
8412                                    to be preserved for calls which
8413                                    require a runtime generic context,
8414                                    but interface calls don't. */
8415                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8416                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8417 #endif
8418                         }
8419                 } else {
8420                         if (amd64_use_imm32 ((gint64)item->key))
8421                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8422                         else {
8423                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8424                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8425                         }
8426                         item->jmp_code = code;
8427                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8428                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8429                         else
8430                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8431                 }
8432                 g_assert (code - item->code_target <= item->chunk_size);
8433         }
8434         /* patch the branches to get to the target items */
8435         for (i = 0; i < count; ++i) {
8436                 MonoIMTCheckItem *item = imt_entries [i];
8437                 if (item->jmp_code) {
8438                         if (item->check_target_idx) {
8439                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8440                         }
8441                 }
8442         }
8443
8444         if (!fail_tramp)
8445                 mono_stats.imt_thunks_size += code - start;
8446         g_assert (code - start <= size);
8447
8448         nacl_domain_code_validate(domain, &start, size, &code);
8449         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8450
8451         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8452
8453         return start;
8454 }
8455
8456 MonoMethod*
8457 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8458 {
8459         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8460 }
8461
8462 MonoVTable*
8463 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8464 {
8465         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8466 }
8467
8468 GSList*
8469 mono_arch_get_cie_program (void)
8470 {
8471         GSList *l = NULL;
8472
8473         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8474         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8475
8476         return l;
8477 }
8478
8479 #ifndef DISABLE_JIT
8480
8481 MonoInst*
8482 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8483 {
8484         MonoInst *ins = NULL;
8485         int opcode = 0;
8486
8487         if (cmethod->klass == mono_defaults.math_class) {
8488                 if (strcmp (cmethod->name, "Sin") == 0) {
8489                         opcode = OP_SIN;
8490                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8491                         opcode = OP_COS;
8492                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8493                         opcode = OP_SQRT;
8494                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8495                         opcode = OP_ABS;
8496                 }
8497
8498                 if (opcode && fsig->param_count == 1) {
8499                         MONO_INST_NEW (cfg, ins, opcode);
8500                         ins->type = STACK_R8;
8501                         ins->dreg = mono_alloc_freg (cfg);
8502                         ins->sreg1 = args [0]->dreg;
8503                         MONO_ADD_INS (cfg->cbb, ins);
8504                 }
8505
8506                 opcode = 0;
8507                 if (cfg->opt & MONO_OPT_CMOV) {
8508                         if (strcmp (cmethod->name, "Min") == 0) {
8509                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8510                                         opcode = OP_IMIN;
8511                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8512                                         opcode = OP_IMIN_UN;
8513                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8514                                         opcode = OP_LMIN;
8515                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8516                                         opcode = OP_LMIN_UN;
8517                         } else if (strcmp (cmethod->name, "Max") == 0) {
8518                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8519                                         opcode = OP_IMAX;
8520                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8521                                         opcode = OP_IMAX_UN;
8522                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8523                                         opcode = OP_LMAX;
8524                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8525                                         opcode = OP_LMAX_UN;
8526                         }
8527                 }
8528
8529                 if (opcode && fsig->param_count == 2) {
8530                         MONO_INST_NEW (cfg, ins, opcode);
8531                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8532                         ins->dreg = mono_alloc_ireg (cfg);
8533                         ins->sreg1 = args [0]->dreg;
8534                         ins->sreg2 = args [1]->dreg;
8535                         MONO_ADD_INS (cfg->cbb, ins);
8536                 }
8537
8538 #if 0
8539                 /* OP_FREM is not IEEE compatible */
8540                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8541                         MONO_INST_NEW (cfg, ins, OP_FREM);
8542                         ins->inst_i0 = args [0];
8543                         ins->inst_i1 = args [1];
8544                 }
8545 #endif
8546         }
8547
8548         return ins;
8549 }
8550 #endif
8551
8552 gboolean
8553 mono_arch_print_tree (MonoInst *tree, int arity)
8554 {
8555         return 0;
8556 }
8557
8558 mgreg_t
8559 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8560 {
8561         return ctx->gregs [reg];
8562 }
8563
8564 void
8565 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8566 {
8567         ctx->gregs [reg] = val;
8568 }
8569
8570 gpointer
8571 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8572 {
8573         gpointer *sp, old_value;
8574         char *bp;
8575
8576         /*Load the spvar*/
8577         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8578         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8579
8580         old_value = *sp;
8581         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8582                 return old_value;
8583
8584         *sp = new_value;
8585
8586         return old_value;
8587 }
8588
8589 /*
8590  * mono_arch_emit_load_aotconst:
8591  *
8592  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8593  * TARGET from the mscorlib GOT in full-aot code.
8594  * On AMD64, the result is placed into R11.
8595  */
8596 guint8*
8597 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8598 {
8599         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8600         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8601
8602         return code;
8603 }
8604
8605 /*
8606  * mono_arch_get_trampolines:
8607  *
8608  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8609  * for AOT.
8610  */
8611 GSList *
8612 mono_arch_get_trampolines (gboolean aot)
8613 {
8614         return mono_amd64_get_exception_trampolines (aot);
8615 }
8616
8617 /* Soft Debug support */
8618 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8619
8620 /*
8621  * mono_arch_set_breakpoint:
8622  *
8623  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8624  * The location should contain code emitted by OP_SEQ_POINT.
8625  */
8626 void
8627 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8628 {
8629         guint8 *code = ip;
8630
8631         if (ji->from_aot) {
8632                 guint32 native_offset = ip - (guint8*)ji->code_start;
8633                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8634
8635                 g_assert (info->bp_addrs [native_offset] == 0);
8636                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8637         } else {
8638                 /* ip points to a mov r11, 0 */
8639                 g_assert (code [0] == 0x41);
8640                 g_assert (code [1] == 0xbb);
8641                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8642         }
8643 }
8644
8645 /*
8646  * mono_arch_clear_breakpoint:
8647  *
8648  *   Clear the breakpoint at IP.
8649  */
8650 void
8651 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8652 {
8653         guint8 *code = ip;
8654
8655         if (ji->from_aot) {
8656                 guint32 native_offset = ip - (guint8*)ji->code_start;
8657                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8658
8659                 info->bp_addrs [native_offset] = NULL;
8660         } else {
8661                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8662         }
8663 }
8664
8665 gboolean
8666 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8667 {
8668         /* We use soft breakpoints on amd64 */
8669         return FALSE;
8670 }
8671
8672 /*
8673  * mono_arch_skip_breakpoint:
8674  *
8675  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8676  * we resume, the instruction is not executed again.
8677  */
8678 void
8679 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8680 {
8681         g_assert_not_reached ();
8682 }
8683
8684 /*
8685  * mono_arch_start_single_stepping:
8686  *
8687  *   Start single stepping.
8688  */
8689 void
8690 mono_arch_start_single_stepping (void)
8691 {
8692         ss_trampoline = mini_get_single_step_trampoline ();
8693 }
8694
8695 /*
8696  * mono_arch_stop_single_stepping:
8697  *
8698  *   Stop single stepping.
8699  */
8700 void
8701 mono_arch_stop_single_stepping (void)
8702 {
8703         ss_trampoline = NULL;
8704 }
8705
8706 /*
8707  * mono_arch_is_single_step_event:
8708  *
8709  *   Return whenever the machine state in SIGCTX corresponds to a single
8710  * step event.
8711  */
8712 gboolean
8713 mono_arch_is_single_step_event (void *info, void *sigctx)
8714 {
8715         /* We use soft breakpoints on amd64 */
8716         return FALSE;
8717 }
8718
8719 /*
8720  * mono_arch_skip_single_step:
8721  *
8722  *   Modify CTX so the ip is placed after the single step trigger instruction,
8723  * we resume, the instruction is not executed again.
8724  */
8725 void
8726 mono_arch_skip_single_step (MonoContext *ctx)
8727 {
8728         g_assert_not_reached ();
8729 }
8730
8731 /*
8732  * mono_arch_create_seq_point_info:
8733  *
8734  *   Return a pointer to a data structure which is used by the sequence
8735  * point implementation in AOTed code.
8736  */
8737 gpointer
8738 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8739 {
8740         SeqPointInfo *info;
8741         MonoJitInfo *ji;
8742
8743         // FIXME: Add a free function
8744
8745         mono_domain_lock (domain);
8746         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8747                                                                 code);
8748         mono_domain_unlock (domain);
8749
8750         if (!info) {
8751                 ji = mono_jit_info_table_find (domain, (char*)code);
8752                 g_assert (ji);
8753
8754                 // FIXME: Optimize the size
8755                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8756
8757                 info->ss_tramp_addr = &ss_trampoline;
8758
8759                 mono_domain_lock (domain);
8760                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8761                                                          code, info);
8762                 mono_domain_unlock (domain);
8763         }
8764
8765         return info;
8766 }
8767
8768 void
8769 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8770 {
8771         ext->lmf.previous_lmf = prev_lmf;
8772         /* Mark that this is a MonoLMFExt */
8773         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8774         ext->lmf.rsp = (gssize)ext;
8775 }
8776
8777 #endif
8778
8779 gboolean
8780 mono_arch_opcode_supported (int opcode)
8781 {
8782         switch (opcode) {
8783         case OP_ATOMIC_ADD_I4:
8784         case OP_ATOMIC_ADD_I8:
8785         case OP_ATOMIC_EXCHANGE_I4:
8786         case OP_ATOMIC_EXCHANGE_I8:
8787         case OP_ATOMIC_CAS_I4:
8788         case OP_ATOMIC_CAS_I8:
8789         case OP_ATOMIC_LOAD_I1:
8790         case OP_ATOMIC_LOAD_I2:
8791         case OP_ATOMIC_LOAD_I4:
8792         case OP_ATOMIC_LOAD_I8:
8793         case OP_ATOMIC_LOAD_U1:
8794         case OP_ATOMIC_LOAD_U2:
8795         case OP_ATOMIC_LOAD_U4:
8796         case OP_ATOMIC_LOAD_U8:
8797         case OP_ATOMIC_LOAD_R4:
8798         case OP_ATOMIC_LOAD_R8:
8799         case OP_ATOMIC_STORE_I1:
8800         case OP_ATOMIC_STORE_I2:
8801         case OP_ATOMIC_STORE_I4:
8802         case OP_ATOMIC_STORE_I8:
8803         case OP_ATOMIC_STORE_U1:
8804         case OP_ATOMIC_STORE_U2:
8805         case OP_ATOMIC_STORE_U4:
8806         case OP_ATOMIC_STORE_U8:
8807         case OP_ATOMIC_STORE_R4:
8808         case OP_ATOMIC_STORE_R8:
8809                 return TRUE;
8810         default:
8811                 return FALSE;
8812         }
8813 }
8814
8815 #if defined(ENABLE_GSHAREDVT) && defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
8816
8817 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8818
8819 #endif /* !MONOTOUCH */