mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 const char*
  97 mono_arch_regname (int reg)
  98 {
  99         switch (reg) {
 100         case AMD64_RAX: return "%rax";
 101         case AMD64_RBX: return "%rbx";
 102         case AMD64_RCX: return "%rcx";
 103         case AMD64_RDX: return "%rdx";
 104         case AMD64_RSP: return "%rsp";
 105         case AMD64_RBP: return "%rbp";
 106         case AMD64_RDI: return "%rdi";
 107         case AMD64_RSI: return "%rsi";
 108         case AMD64_R8: return "%r8";
 109         case AMD64_R9: return "%r9";
 110         case AMD64_R10: return "%r10";
 111         case AMD64_R11: return "%r11";
 112         case AMD64_R12: return "%r12";
 113         case AMD64_R13: return "%r13";
 114         case AMD64_R14: return "%r14";
 115         case AMD64_R15: return "%r15";
 116         }
 117         return "unknown";
 118 }
 119
 120 static const char * packed_xmmregs [] = {
 121         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 122         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 123 };
 124
 125 static const char * single_xmmregs [] = {
 126         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 127         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 128 };
 129
 130 const char*
 131 mono_arch_fregname (int reg)
 132 {
 133         if (reg < AMD64_XMM_NREG)
 134                 return single_xmmregs [reg];
 135         else
 136                 return "unknown";
 137 }
 138
 139 const char *
 140 mono_arch_xregname (int reg)
 141 {
 142         if (reg < AMD64_XMM_NREG)
 143                 return packed_xmmregs [reg];
 144         else
 145                 return "unknown";
 146 }
 147
 148 G_GNUC_UNUSED static void
 149 break_count (void)
 150 {
 151 }
 152
 153 G_GNUC_UNUSED static gboolean
 154 debug_count (void)
 155 {
 156         static int count = 0;
 157         count ++;
 158
 159         if (!getenv ("COUNT"))
 160                 return TRUE;
 161
 162         if (count == atoi (getenv ("COUNT"))) {
 163                 break_count ();
 164         }
 165
 166         if (count > atoi (getenv ("COUNT"))) {
 167                 return FALSE;
 168         }
 169
 170         return TRUE;
 171 }
 172
 173 static gboolean
 174 debug_omit_fp (void)
 175 {
 176 #if 0
 177         return debug_count ();
 178 #else
 179         return TRUE;
 180 #endif
 181 }
 182
 183 static inline gboolean
 184 amd64_is_near_call (guint8 *code)
 185 {
 186         /* Skip REX */
 187         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 188                 code += 1;
 189
 190         return code [0] == 0xe8;
 191 }
 192
 193 static inline void
 194 amd64_patch (unsigned char* code, gpointer target)
 195 {
 196         guint8 rex = 0;
 197
 198         /* Skip REX */
 199         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 200                 rex = code [0];
 201                 code += 1;
 202         }
 203
 204         if ((code [0] & 0xf8) == 0xb8) {
 205                 /* amd64_set_reg_template */
 206                 *(guint64*)(code + 1) = (guint64)target;
 207         }
 208         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 209                 /* mov 0(%rip), %dreg */
 210                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 211         }
 212         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 213                 /* call *<OFFSET>(%rip) */
 214                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 215         }
 216         else if ((code [0] == 0xe8)) {
 217                 /* call <DISP> */
 218                 gint64 disp = (guint8*)target - (guint8*)code;
 219                 g_assert (amd64_is_imm32 (disp));
 220                 x86_patch (code, (unsigned char*)target);
 221         }
 222         else
 223                 x86_patch (code, (unsigned char*)target);
 224 }
 225
 226 void
 227 mono_amd64_patch (unsigned char* code, gpointer target)
 228 {
 229         amd64_patch (code, target);
 230 }
 231
 232 typedef enum {
 233         ArgInIReg,
 234         ArgInFloatSSEReg,
 235         ArgInDoubleSSEReg,
 236         ArgOnStack,
 237         ArgValuetypeInReg,
 238         ArgValuetypeAddrInIReg,
 239         ArgNone /* only in pair_storage */
 240 } ArgStorage;
 241
 242 typedef struct {
 243         gint16 offset;
 244         gint8  reg;
 245         ArgStorage storage;
 246
 247         /* Only if storage == ArgValuetypeInReg */
 248         ArgStorage pair_storage [2];
 249         gint8 pair_regs [2];
 250 } ArgInfo;
 251
 252 typedef struct {
 253         int nargs;
 254         guint32 stack_usage;
 255         guint32 reg_usage;
 256         guint32 freg_usage;
 257         gboolean need_stack_align;
 258         ArgInfo ret;
 259         ArgInfo sig_cookie;
 260         ArgInfo args [1];
 261 } CallInfo;
 262
 263 #define DEBUG(a) if (cfg->verbose_level > 1) a
 264
 265 #ifdef PLATFORM_WIN32
 266 #define PARAM_REGS 4
 267
 268 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 269
 270 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 271 #else
 272 #define PARAM_REGS 6
 273
 274 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 275
 276  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 277 #endif
 278
 279 static void inline
 280 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 281 {
 282     ainfo->offset = *stack_size;
 283
 284     if (*gr >= PARAM_REGS) {
 285                 ainfo->storage = ArgOnStack;
 286                 (*stack_size) += sizeof (gpointer);
 287     }
 288     else {
 289                 ainfo->storage = ArgInIReg;
 290                 ainfo->reg = param_regs [*gr];
 291                 (*gr) ++;
 292     }
 293 }
 294
 295 #ifdef PLATFORM_WIN32
 296 #define FLOAT_PARAM_REGS 4
 297 #else
 298 #define FLOAT_PARAM_REGS 8
 299 #endif
 300
 301 static void inline
 302 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 303 {
 304     ainfo->offset = *stack_size;
 305
 306     if (*gr >= FLOAT_PARAM_REGS) {
 307                 ainfo->storage = ArgOnStack;
 308                 (*stack_size) += sizeof (gpointer);
 309     }
 310     else {
 311                 /* A double register */
 312                 if (is_double)
 313                         ainfo->storage = ArgInDoubleSSEReg;
 314                 else
 315                         ainfo->storage = ArgInFloatSSEReg;
 316                 ainfo->reg = *gr;
 317                 (*gr) += 1;
 318     }
 319 }
 320
 321 typedef enum ArgumentClass {
 322         ARG_CLASS_NO_CLASS,
 323         ARG_CLASS_MEMORY,
 324         ARG_CLASS_INTEGER,
 325         ARG_CLASS_SSE
 326 } ArgumentClass;
 327
 328 static ArgumentClass
 329 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 330 {
 331         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 332         MonoType *ptype;
 333
 334         ptype = mini_type_get_underlying_type (NULL, type);
 335         switch (ptype->type) {
 336         case MONO_TYPE_BOOLEAN:
 337         case MONO_TYPE_CHAR:
 338         case MONO_TYPE_I1:
 339         case MONO_TYPE_U1:
 340         case MONO_TYPE_I2:
 341         case MONO_TYPE_U2:
 342         case MONO_TYPE_I4:
 343         case MONO_TYPE_U4:
 344         case MONO_TYPE_I:
 345         case MONO_TYPE_U:
 346         case MONO_TYPE_STRING:
 347         case MONO_TYPE_OBJECT:
 348         case MONO_TYPE_CLASS:
 349         case MONO_TYPE_SZARRAY:
 350         case MONO_TYPE_PTR:
 351         case MONO_TYPE_FNPTR:
 352         case MONO_TYPE_ARRAY:
 353         case MONO_TYPE_I8:
 354         case MONO_TYPE_U8:
 355                 class2 = ARG_CLASS_INTEGER;
 356                 break;
 357         case MONO_TYPE_R4:
 358         case MONO_TYPE_R8:
 359 #ifdef PLATFORM_WIN32
 360                 class2 = ARG_CLASS_INTEGER;
 361 #else
 362                 class2 = ARG_CLASS_SSE;
 363 #endif
 364                 break;
 365
 366         case MONO_TYPE_TYPEDBYREF:
 367                 g_assert_not_reached ();
 368
 369         case MONO_TYPE_GENERICINST:
 370                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 371                         class2 = ARG_CLASS_INTEGER;
 372                         break;
 373                 }
 374                 /* fall through */
 375         case MONO_TYPE_VALUETYPE: {
 376                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 377                 int i;
 378
 379                 for (i = 0; i < info->num_fields; ++i) {
 380                         class2 = class1;
 381                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 382                 }
 383                 break;
 384         }
 385         default:
 386                 g_assert_not_reached ();
 387         }
 388
 389         /* Merge */
 390         if (class1 == class2)
 391                 ;
 392         else if (class1 == ARG_CLASS_NO_CLASS)
 393                 class1 = class2;
 394         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 395                 class1 = ARG_CLASS_MEMORY;
 396         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 397                 class1 = ARG_CLASS_INTEGER;
 398         else
 399                 class1 = ARG_CLASS_SSE;
 400
 401         return class1;
 402 }
 403
 404 static void
 405 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 406                            gboolean is_return,
 407                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 408 {
 409         guint32 size, quad, nquads, i;
 410         ArgumentClass args [2];
 411         MonoMarshalType *info = NULL;
 412         MonoClass *klass;
 413         MonoGenericSharingContext tmp_gsctx;
 414         gboolean pass_on_stack = FALSE;
 415
 416         /*
 417          * The gsctx currently contains no data, it is only used for checking whenever
 418          * open types are allowed, some callers like mono_arch_get_argument_info ()
 419          * don't pass it to us, so work around that.
 420          */
 421         if (!gsctx)
 422                 gsctx = &tmp_gsctx;
 423
 424         klass = mono_class_from_mono_type (type);
 425         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 426 #ifndef PLATFORM_WIN32
 427         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 428                 /* We pass and return vtypes of size 8 in a register */
 429         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 430                 pass_on_stack = TRUE;
 431         }
 432 #else
 433         if (!sig->pinvoke) {
 434                 pass_on_stack = TRUE;
 435         }
 436 #endif
 437
 438         if (pass_on_stack) {
 439                 /* Allways pass in memory */
 440                 ainfo->offset = *stack_size;
 441                 *stack_size += ALIGN_TO (size, 8);
 442                 ainfo->storage = ArgOnStack;
 443
 444                 return;
 445         }
 446
 447         /* FIXME: Handle structs smaller than 8 bytes */
 448         //if ((size % 8) != 0)
 449         //      NOT_IMPLEMENTED;
 450
 451         if (size > 8)
 452                 nquads = 2;
 453         else
 454                 nquads = 1;
 455
 456         if (!sig->pinvoke) {
 457                 /* Always pass in 1 or 2 integer registers */
 458                 args [0] = ARG_CLASS_INTEGER;
 459                 args [1] = ARG_CLASS_INTEGER;
 460                 /* Only the simplest cases are supported */
 461                 if (is_return && nquads != 1) {
 462                         args [0] = ARG_CLASS_MEMORY;
 463                         args [1] = ARG_CLASS_MEMORY;
 464                 }
 465         } else {
 466                 /*
 467                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 468                  * The X87 and SSEUP stuff is left out since there are no such types in
 469                  * the CLR.
 470                  */
 471                 info = mono_marshal_load_type_info (klass);
 472                 g_assert (info);
 473
 474 #ifndef PLATFORM_WIN32
 475                 if (info->native_size > 16) {
 476                         ainfo->offset = *stack_size;
 477                         *stack_size += ALIGN_TO (info->native_size, 8);
 478                         ainfo->storage = ArgOnStack;
 479
 480                         return;
 481                 }
 482 #else
 483                 switch (info->native_size) {
 484                 case 1: case 2: case 4: case 8:
 485                         break;
 486                 default:
 487                         if (is_return) {
 488                                 ainfo->storage = ArgOnStack;
 489                                 ainfo->offset = *stack_size;
 490                                 *stack_size += ALIGN_TO (info->native_size, 8);
 491                         }
 492                         else {
 493                                 ainfo->storage = ArgValuetypeAddrInIReg;
 494
 495                                 if (*gr < PARAM_REGS) {
 496                                         ainfo->pair_storage [0] = ArgInIReg;
 497                                         ainfo->pair_regs [0] = param_regs [*gr];
 498                                         (*gr) ++;
 499                                 }
 500                                 else {
 501                                         ainfo->pair_storage [0] = ArgOnStack;
 502                                         ainfo->offset = *stack_size;
 503                                         *stack_size += 8;
 504                                 }
 505                         }
 506
 507                         return;
 508                 }
 509 #endif
 510
 511                 args [0] = ARG_CLASS_NO_CLASS;
 512                 args [1] = ARG_CLASS_NO_CLASS;
 513                 for (quad = 0; quad < nquads; ++quad) {
 514                         int size;
 515                         guint32 align;
 516                         ArgumentClass class1;
 517
 518                         if (info->num_fields == 0)
 519                                 class1 = ARG_CLASS_MEMORY;
 520                         else
 521                                 class1 = ARG_CLASS_NO_CLASS;
 522                         for (i = 0; i < info->num_fields; ++i) {
 523                                 size = mono_marshal_type_size (info->fields [i].field->type,
 524                                                                                            info->fields [i].mspec,
 525                                                                                            &align, TRUE, klass->unicode);
 526                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 527                                         /* Unaligned field */
 528                                         NOT_IMPLEMENTED;
 529                                 }
 530
 531                                 /* Skip fields in other quad */
 532                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 533                                         continue;
 534                                 if ((quad == 1) && (info->fields [i].offset < 8))
 535                                         continue;
 536
 537                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 538                         }
 539                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 540                         args [quad] = class1;
 541                 }
 542         }
 543
 544         /* Post merger cleanup */
 545         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 546                 args [0] = args [1] = ARG_CLASS_MEMORY;
 547
 548         /* Allocate registers */
 549         {
 550                 int orig_gr = *gr;
 551                 int orig_fr = *fr;
 552
 553                 ainfo->storage = ArgValuetypeInReg;
 554                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 555                 for (quad = 0; quad < nquads; ++quad) {
 556                         switch (args [quad]) {
 557                         case ARG_CLASS_INTEGER:
 558                                 if (*gr >= PARAM_REGS)
 559                                         args [quad] = ARG_CLASS_MEMORY;
 560                                 else {
 561                                         ainfo->pair_storage [quad] = ArgInIReg;
 562                                         if (is_return)
 563                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 564                                         else
 565                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 566                                         (*gr) ++;
 567                                 }
 568                                 break;
 569                         case ARG_CLASS_SSE:
 570                                 if (*fr >= FLOAT_PARAM_REGS)
 571                                         args [quad] = ARG_CLASS_MEMORY;
 572                                 else {
 573                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 574                                         ainfo->pair_regs [quad] = *fr;
 575                                         (*fr) ++;
 576                                 }
 577                                 break;
 578                         case ARG_CLASS_MEMORY:
 579                                 break;
 580                         default:
 581                                 g_assert_not_reached ();
 582                         }
 583                 }
 584
 585                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 586                         /* Revert possible register assignments */
 587                         *gr = orig_gr;
 588                         *fr = orig_fr;
 589
 590                         ainfo->offset = *stack_size;
 591                         if (sig->pinvoke)
 592                                 *stack_size += ALIGN_TO (info->native_size, 8);
 593                         else
 594                                 *stack_size += nquads * sizeof (gpointer);
 595                         ainfo->storage = ArgOnStack;
 596                 }
 597         }
 598 }
 599
 600 /*
 601  * get_call_info:
 602  *
 603  *  Obtain information about a call according to the calling convention.
 604  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 605  * Draft Version 0.23" document for more information.
 606  */
 607 static CallInfo*
 608 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 609 {
 610         guint32 i, gr, fr;
 611         MonoType *ret_type;
 612         int n = sig->hasthis + sig->param_count;
 613         guint32 stack_size = 0;
 614         CallInfo *cinfo;
 615
 616         if (mp)
 617                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 618         else
 619                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 620
 621         gr = 0;
 622         fr = 0;
 623
 624         /* return value */
 625         {
 626                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 627                 switch (ret_type->type) {
 628                 case MONO_TYPE_BOOLEAN:
 629                 case MONO_TYPE_I1:
 630                 case MONO_TYPE_U1:
 631                 case MONO_TYPE_I2:
 632                 case MONO_TYPE_U2:
 633                 case MONO_TYPE_CHAR:
 634                 case MONO_TYPE_I4:
 635                 case MONO_TYPE_U4:
 636                 case MONO_TYPE_I:
 637                 case MONO_TYPE_U:
 638                 case MONO_TYPE_PTR:
 639                 case MONO_TYPE_FNPTR:
 640                 case MONO_TYPE_CLASS:
 641                 case MONO_TYPE_OBJECT:
 642                 case MONO_TYPE_SZARRAY:
 643                 case MONO_TYPE_ARRAY:
 644                 case MONO_TYPE_STRING:
 645                         cinfo->ret.storage = ArgInIReg;
 646                         cinfo->ret.reg = AMD64_RAX;
 647                         break;
 648                 case MONO_TYPE_U8:
 649                 case MONO_TYPE_I8:
 650                         cinfo->ret.storage = ArgInIReg;
 651                         cinfo->ret.reg = AMD64_RAX;
 652                         break;
 653                 case MONO_TYPE_R4:
 654                         cinfo->ret.storage = ArgInFloatSSEReg;
 655                         cinfo->ret.reg = AMD64_XMM0;
 656                         break;
 657                 case MONO_TYPE_R8:
 658                         cinfo->ret.storage = ArgInDoubleSSEReg;
 659                         cinfo->ret.reg = AMD64_XMM0;
 660                         break;
 661                 case MONO_TYPE_GENERICINST:
 662                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 663                                 cinfo->ret.storage = ArgInIReg;
 664                                 cinfo->ret.reg = AMD64_RAX;
 665                                 break;
 666                         }
 667                         /* fall through */
 668                 case MONO_TYPE_VALUETYPE: {
 669                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 670
 671                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 672                         if (cinfo->ret.storage == ArgOnStack)
 673                                 /* The caller passes the address where the value is stored */
 674                                 add_general (&gr, &stack_size, &cinfo->ret);
 675                         break;
 676                 }
 677                 case MONO_TYPE_TYPEDBYREF:
 678                         /* Same as a valuetype with size 24 */
 679                         add_general (&gr, &stack_size, &cinfo->ret);
 680                         ;
 681                         break;
 682                 case MONO_TYPE_VOID:
 683                         break;
 684                 default:
 685                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 686                 }
 687         }
 688
 689         /* this */
 690         if (sig->hasthis)
 691                 add_general (&gr, &stack_size, cinfo->args + 0);
 692
 693         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 694                 gr = PARAM_REGS;
 695                 fr = FLOAT_PARAM_REGS;
 696
 697                 /* Emit the signature cookie just before the implicit arguments */
 698                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 699         }
 700
 701         for (i = 0; i < sig->param_count; ++i) {
 702                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 703                 MonoType *ptype;
 704
 705 #ifdef PLATFORM_WIN32
 706                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 707                 if (gr > fr)
 708                         fr = gr;
 709                 else if (fr > gr)
 710                         gr = fr;
 711 #endif
 712
 713                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 714                         /* We allways pass the sig cookie on the stack for simplicity */
 715                         /*
 716                          * Prevent implicit arguments + the sig cookie from being passed
 717                          * in registers.
 718                          */
 719                         gr = PARAM_REGS;
 720                         fr = FLOAT_PARAM_REGS;
 721
 722                         /* Emit the signature cookie just before the implicit arguments */
 723                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 724                 }
 725
 726                 if (sig->params [i]->byref) {
 727                         add_general (&gr, &stack_size, ainfo);
 728                         continue;
 729                 }
 730                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 731                 switch (ptype->type) {
 732                 case MONO_TYPE_BOOLEAN:
 733                 case MONO_TYPE_I1:
 734                 case MONO_TYPE_U1:
 735                         add_general (&gr, &stack_size, ainfo);
 736                         break;
 737                 case MONO_TYPE_I2:
 738                 case MONO_TYPE_U2:
 739                 case MONO_TYPE_CHAR:
 740                         add_general (&gr, &stack_size, ainfo);
 741                         break;
 742                 case MONO_TYPE_I4:
 743                 case MONO_TYPE_U4:
 744                         add_general (&gr, &stack_size, ainfo);
 745                         break;
 746                 case MONO_TYPE_I:
 747                 case MONO_TYPE_U:
 748                 case MONO_TYPE_PTR:
 749                 case MONO_TYPE_FNPTR:
 750                 case MONO_TYPE_CLASS:
 751                 case MONO_TYPE_OBJECT:
 752                 case MONO_TYPE_STRING:
 753                 case MONO_TYPE_SZARRAY:
 754                 case MONO_TYPE_ARRAY:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_GENERICINST:
 758                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 759                                 add_general (&gr, &stack_size, ainfo);
 760                                 break;
 761                         }
 762                         /* fall through */
 763                 case MONO_TYPE_VALUETYPE:
 764                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 765                         break;
 766                 case MONO_TYPE_TYPEDBYREF:
 767 #ifdef PLATFORM_WIN32
 768                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 769 #else
 770                         stack_size += sizeof (MonoTypedRef);
 771                         ainfo->storage = ArgOnStack;
 772 #endif
 773                         break;
 774                 case MONO_TYPE_U8:
 775                 case MONO_TYPE_I8:
 776                         add_general (&gr, &stack_size, ainfo);
 777                         break;
 778                 case MONO_TYPE_R4:
 779                         add_float (&fr, &stack_size, ainfo, FALSE);
 780                         break;
 781                 case MONO_TYPE_R8:
 782                         add_float (&fr, &stack_size, ainfo, TRUE);
 783                         break;
 784                 default:
 785                         g_assert_not_reached ();
 786                 }
 787         }
 788
 789         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 790                 gr = PARAM_REGS;
 791                 fr = FLOAT_PARAM_REGS;
 792
 793                 /* Emit the signature cookie just before the implicit arguments */
 794                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 795         }
 796
 797 #ifdef PLATFORM_WIN32
 798         // There always is 32 bytes reserved on the stack when calling on Winx64
 799         stack_size += 0x20;
 800 #endif
 801
 802         if (stack_size & 0x8) {
 803                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 804                 cinfo->need_stack_align = TRUE;
 805                 stack_size += 8;
 806         }
 807
 808         cinfo->stack_usage = stack_size;
 809         cinfo->reg_usage = gr;
 810         cinfo->freg_usage = fr;
 811         return cinfo;
 812 }
 813
 814 /*
 815  * mono_arch_get_argument_info:
 816  * @csig:  a method signature
 817  * @param_count: the number of parameters to consider
 818  * @arg_info: an array to store the result infos
 819  *
 820  * Gathers information on parameters such as size, alignment and
 821  * padding. arg_info should be large enought to hold param_count + 1 entries.
 822  *
 823  * Returns the size of the argument area on the stack.
 824  */
 825 int
 826 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 827 {
 828         int k;
 829         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 830         guint32 args_size = cinfo->stack_usage;
 831
 832         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 833         if (csig->hasthis) {
 834                 arg_info [0].offset = 0;
 835         }
 836
 837         for (k = 0; k < param_count; k++) {
 838                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 839                 /* FIXME: */
 840                 arg_info [k + 1].size = 0;
 841         }
 842
 843         g_free (cinfo);
 844
 845         return args_size;
 846 }
 847
 848 static int
 849 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 850 {
 851 #ifndef _MSC_VER
 852         __asm__ __volatile__ ("cpuid"
 853                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 854                 : "a" (id));
 855 #else
 856         int info[4];
 857         __cpuid(info, id);
 858         *p_eax = info[0];
 859         *p_ebx = info[1];
 860         *p_ecx = info[2];
 861         *p_edx = info[3];
 862 #endif
 863         return 1;
 864 }
 865
 866 /*
 867  * Initialize the cpu to execute managed code.
 868  */
 869 void
 870 mono_arch_cpu_init (void)
 871 {
 872 #ifndef _MSC_VER
 873         guint16 fpcw;
 874
 875         /* spec compliance requires running with double precision */
 876         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 877         fpcw &= ~X86_FPCW_PRECC_MASK;
 878         fpcw |= X86_FPCW_PREC_DOUBLE;
 879         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 880         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 881 #else
 882         /* TODO: This is crashing on Win64 right now.
 883         * _control87 (_PC_53, MCW_PC);
 884         */
 885 #endif
 886 }
 887
 888 /*
 889  * Initialize architecture specific code.
 890  */
 891 void
 892 mono_arch_init (void)
 893 {
 894         InitializeCriticalSection (&mini_arch_mutex);
 895 }
 896
 897 /*
 898  * Cleanup architecture specific code.
 899  */
 900 void
 901 mono_arch_cleanup (void)
 902 {
 903         DeleteCriticalSection (&mini_arch_mutex);
 904 }
 905
 906 /*
 907  * This function returns the optimizations supported on this cpu.
 908  */
 909 guint32
 910 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 911 {
 912         int eax, ebx, ecx, edx;
 913         guint32 opts = 0;
 914
 915         /* FIXME: AMD64 */
 916
 917         *exclude_mask = 0;
 918         /* Feature Flags function, flags returned in EDX. */
 919         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 920                 if (edx & (1 << 15)) {
 921                         opts |= MONO_OPT_CMOV;
 922                         if (edx & 1)
 923                                 opts |= MONO_OPT_FCMOV;
 924                         else
 925                                 *exclude_mask |= MONO_OPT_FCMOV;
 926                 } else
 927                         *exclude_mask |= MONO_OPT_CMOV;
 928         }
 929
 930         return opts;
 931 }
 932
 933 /*
 934  * This function test for all SSE functions supported.
 935  *
 936  * Returns a bitmask corresponding to all supported versions.
 937  *
 938  * TODO detect other versions like SSE4a.
 939  */
 940 guint32
 941 mono_arch_cpu_enumerate_simd_versions (void)
 942 {
 943         int eax, ebx, ecx, edx;
 944         guint32 sse_opts = 0;
 945
 946         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 947                 if (edx & (1 << 25))
 948                         sse_opts |= 1 << SIMD_VERSION_SSE1;
 949                 if (edx & (1 << 26))
 950                         sse_opts |= 1 << SIMD_VERSION_SSE2;
 951                 if (ecx & (1 << 0))
 952                         sse_opts |= 1 << SIMD_VERSION_SSE3;
 953                 if (ecx & (1 << 9))
 954                         sse_opts |= 1 << SIMD_VERSION_SSSE3;
 955                 if (ecx & (1 << 19))
 956                         sse_opts |= 1 << SIMD_VERSION_SSE41;
 957                 if (ecx & (1 << 20))
 958                         sse_opts |= 1 << SIMD_VERSION_SSE42;
 959         }
 960         return sse_opts;
 961 }
 962
 963 GList *
 964 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 965 {
 966         GList *vars = NULL;
 967         int i;
 968
 969         for (i = 0; i < cfg->num_varinfo; i++) {
 970                 MonoInst *ins = cfg->varinfo [i];
 971                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 972
 973                 /* unused vars */
 974                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 975                         continue;
 976
 977                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 978                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 979                         continue;
 980
 981                 if (mono_is_regsize_var (ins->inst_vtype)) {
 982                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 983                         g_assert (i == vmv->idx);
 984                         vars = g_list_prepend (vars, vmv);
 985                 }
 986         }
 987
 988         vars = mono_varlist_sort (cfg, vars, 0);
 989
 990         return vars;
 991 }
 992
 993 /**
 994  * mono_arch_compute_omit_fp:
 995  *
 996  *   Determine whenever the frame pointer can be eliminated.
 997  */
 998 static void
 999 mono_arch_compute_omit_fp (MonoCompile *cfg)
1000 {
1001         MonoMethodSignature *sig;
1002         MonoMethodHeader *header;
1003         int i, locals_size;
1004         CallInfo *cinfo;
1005
1006         if (cfg->arch.omit_fp_computed)
1007                 return;
1008
1009         header = mono_method_get_header (cfg->method);
1010
1011         sig = mono_method_signature (cfg->method);
1012
1013         if (!cfg->arch.cinfo)
1014                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1015         cinfo = cfg->arch.cinfo;
1016
1017         /*
1018          * FIXME: Remove some of the restrictions.
1019          */
1020         cfg->arch.omit_fp = TRUE;
1021         cfg->arch.omit_fp_computed = TRUE;
1022
1023         if (cfg->disable_omit_fp)
1024                 cfg->arch.omit_fp = FALSE;
1025
1026         if (!debug_omit_fp ())
1027                 cfg->arch.omit_fp = FALSE;
1028         /*
1029         if (cfg->method->save_lmf)
1030                 cfg->arch.omit_fp = FALSE;
1031         */
1032         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1033                 cfg->arch.omit_fp = FALSE;
1034         if (header->num_clauses)
1035                 cfg->arch.omit_fp = FALSE;
1036         if (cfg->param_area)
1037                 cfg->arch.omit_fp = FALSE;
1038         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1039                 cfg->arch.omit_fp = FALSE;
1040         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1041                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1042                 cfg->arch.omit_fp = FALSE;
1043         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1044                 ArgInfo *ainfo = &cinfo->args [i];
1045
1046                 if (ainfo->storage == ArgOnStack) {
1047                         /*
1048                          * The stack offset can only be determined when the frame
1049                          * size is known.
1050                          */
1051                         cfg->arch.omit_fp = FALSE;
1052                 }
1053         }
1054
1055         locals_size = 0;
1056         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1057                 MonoInst *ins = cfg->varinfo [i];
1058                 int ialign;
1059
1060                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1061         }
1062 }
1063
1064 GList *
1065 mono_arch_get_global_int_regs (MonoCompile *cfg)
1066 {
1067         GList *regs = NULL;
1068
1069         mono_arch_compute_omit_fp (cfg);
1070
1071         if (cfg->globalra) {
1072                 if (cfg->arch.omit_fp)
1073                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1074
1075                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1076                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1077                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1078                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1079                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1080
1081                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1082                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1084                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1085                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1089         } else {
1090                 if (cfg->arch.omit_fp)
1091                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1092
1093                 /* We use the callee saved registers for global allocation */
1094                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1099 #ifdef PLATFORM_WIN32
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1101                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1102 #endif
1103         }
1104
1105         return regs;
1106 }
1107
1108 GList*
1109 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1110 {
1111         GList *regs = NULL;
1112         int i;
1113
1114         /* All XMM registers */
1115         for (i = 0; i < 16; ++i)
1116                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1117
1118         return regs;
1119 }
1120
1121 GList*
1122 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1123 {
1124         static GList *r = NULL;
1125
1126         if (r == NULL) {
1127                 GList *regs = NULL;
1128
1129                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1130                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1131                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1132                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1133                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1134                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1135
1136                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1137                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1138                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1139                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1140                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1141                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1142                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1143                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1144
1145                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1146         }
1147
1148         return r;
1149 }
1150
1151 GList*
1152 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1153 {
1154         int i;
1155         static GList *r = NULL;
1156
1157         if (r == NULL) {
1158                 GList *regs = NULL;
1159
1160                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1161                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1162
1163                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1164         }
1165
1166         return r;
1167 }
1168
1169 /*
1170  * mono_arch_regalloc_cost:
1171  *
1172  *  Return the cost, in number of memory references, of the action of
1173  * allocating the variable VMV into a register during global register
1174  * allocation.
1175  */
1176 guint32
1177 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1178 {
1179         MonoInst *ins = cfg->varinfo [vmv->idx];
1180
1181         if (cfg->method->save_lmf)
1182                 /* The register is already saved */
1183                 /* substract 1 for the invisible store in the prolog */
1184                 return (ins->opcode == OP_ARG) ? 0 : 1;
1185         else
1186                 /* push+pop */
1187                 return (ins->opcode == OP_ARG) ? 1 : 2;
1188 }
1189
1190 /*
1191  * mono_arch_fill_argument_info:
1192  *
1193  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1194  * of the method.
1195  */
1196 void
1197 mono_arch_fill_argument_info (MonoCompile *cfg)
1198 {
1199         MonoMethodSignature *sig;
1200         MonoMethodHeader *header;
1201         MonoInst *ins;
1202         int i;
1203         CallInfo *cinfo;
1204
1205         header = mono_method_get_header (cfg->method);
1206
1207         sig = mono_method_signature (cfg->method);
1208
1209         cinfo = cfg->arch.cinfo;
1210
1211         /*
1212          * Contrary to mono_arch_allocate_vars (), the information should describe
1213          * where the arguments are at the beginning of the method, not where they can be
1214          * accessed during the execution of the method. The later makes no sense for the
1215          * global register allocator, since a variable can be in more than one location.
1216          */
1217         if (sig->ret->type != MONO_TYPE_VOID) {
1218                 switch (cinfo->ret.storage) {
1219                 case ArgInIReg:
1220                 case ArgInFloatSSEReg:
1221                 case ArgInDoubleSSEReg:
1222                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1223                                 cfg->vret_addr->opcode = OP_REGVAR;
1224                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1225                         }
1226                         else {
1227                                 cfg->ret->opcode = OP_REGVAR;
1228                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1229                         }
1230                         break;
1231                 case ArgValuetypeInReg:
1232                         cfg->ret->opcode = OP_REGOFFSET;
1233                         cfg->ret->inst_basereg = -1;
1234                         cfg->ret->inst_offset = -1;
1235                         break;
1236                 default:
1237                         g_assert_not_reached ();
1238                 }
1239         }
1240
1241         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1242                 ArgInfo *ainfo = &cinfo->args [i];
1243                 MonoType *arg_type;
1244
1245                 ins = cfg->args [i];
1246
1247                 if (sig->hasthis && (i == 0))
1248                         arg_type = &mono_defaults.object_class->byval_arg;
1249                 else
1250                         arg_type = sig->params [i - sig->hasthis];
1251
1252                 switch (ainfo->storage) {
1253                 case ArgInIReg:
1254                 case ArgInFloatSSEReg:
1255                 case ArgInDoubleSSEReg:
1256                         ins->opcode = OP_REGVAR;
1257                         ins->inst_c0 = ainfo->reg;
1258                         break;
1259                 case ArgOnStack:
1260                         ins->opcode = OP_REGOFFSET;
1261                         ins->inst_basereg = -1;
1262                         ins->inst_offset = -1;
1263                         break;
1264                 case ArgValuetypeInReg:
1265                         /* Dummy */
1266                         ins->opcode = OP_NOP;
1267                         break;
1268                 default:
1269                         g_assert_not_reached ();
1270                 }
1271         }
1272 }
1273
1274 void
1275 mono_arch_allocate_vars (MonoCompile *cfg)
1276 {
1277         MonoMethodSignature *sig;
1278         MonoMethodHeader *header;
1279         MonoInst *ins;
1280         int i, offset;
1281         guint32 locals_stack_size, locals_stack_align;
1282         gint32 *offsets;
1283         CallInfo *cinfo;
1284
1285         header = mono_method_get_header (cfg->method);
1286
1287         sig = mono_method_signature (cfg->method);
1288
1289         cinfo = cfg->arch.cinfo;
1290
1291         mono_arch_compute_omit_fp (cfg);
1292
1293         /*
1294          * We use the ABI calling conventions for managed code as well.
1295          * Exception: valuetypes are only sometimes passed or returned in registers.
1296          */
1297
1298         /*
1299          * The stack looks like this:
1300          * <incoming arguments passed on the stack>
1301          * <return value>
1302          * <lmf/caller saved registers>
1303          * <locals>
1304          * <spill area>
1305          * <localloc area>  -> grows dynamically
1306          * <params area>
1307          */
1308
1309         if (cfg->arch.omit_fp) {
1310                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1311                 cfg->frame_reg = AMD64_RSP;
1312                 offset = 0;
1313         } else {
1314                 /* Locals are allocated backwards from %fp */
1315                 cfg->frame_reg = AMD64_RBP;
1316                 offset = 0;
1317         }
1318
1319         if (cfg->method->save_lmf) {
1320                 /* Reserve stack space for saving LMF */
1321                 if (cfg->arch.omit_fp) {
1322                         cfg->arch.lmf_offset = offset;
1323                         offset += sizeof (MonoLMF);
1324                 }
1325                 else {
1326                         offset += sizeof (MonoLMF);
1327                         cfg->arch.lmf_offset = -offset;
1328                 }
1329         } else {
1330                 if (cfg->arch.omit_fp)
1331                         cfg->arch.reg_save_area_offset = offset;
1332                 /* Reserve space for caller saved registers */
1333                 for (i = 0; i < AMD64_NREG; ++i)
1334                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1335                                 offset += sizeof (gpointer);
1336                         }
1337         }
1338
1339         if (sig->ret->type != MONO_TYPE_VOID) {
1340                 switch (cinfo->ret.storage) {
1341                 case ArgInIReg:
1342                 case ArgInFloatSSEReg:
1343                 case ArgInDoubleSSEReg:
1344                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1345                                 if (cfg->globalra) {
1346                                         cfg->vret_addr->opcode = OP_REGVAR;
1347                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1348                                 } else {
1349                                         /* The register is volatile */
1350                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1351                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1352                                         if (cfg->arch.omit_fp) {
1353                                                 cfg->vret_addr->inst_offset = offset;
1354                                                 offset += 8;
1355                                         } else {
1356                                                 offset += 8;
1357                                                 cfg->vret_addr->inst_offset = -offset;
1358                                         }
1359                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1360                                                 printf ("vret_addr =");
1361                                                 mono_print_ins (cfg->vret_addr);
1362                                         }
1363                                 }
1364                         }
1365                         else {
1366                                 cfg->ret->opcode = OP_REGVAR;
1367                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1368                         }
1369                         break;
1370                 case ArgValuetypeInReg:
1371                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1372                         cfg->ret->opcode = OP_REGOFFSET;
1373                         cfg->ret->inst_basereg = cfg->frame_reg;
1374                         if (cfg->arch.omit_fp) {
1375                                 cfg->ret->inst_offset = offset;
1376                                 offset += 16;
1377                         } else {
1378                                 offset += 16;
1379                                 cfg->ret->inst_offset = - offset;
1380                         }
1381                         break;
1382                 default:
1383                         g_assert_not_reached ();
1384                 }
1385                 if (!cfg->globalra)
1386                         cfg->ret->dreg = cfg->ret->inst_c0;
1387         }
1388
1389         /* Allocate locals */
1390         if (!cfg->globalra) {
1391                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1392                 if (locals_stack_align) {
1393                         offset += (locals_stack_align - 1);
1394                         offset &= ~(locals_stack_align - 1);
1395                 }
1396                 if (cfg->arch.omit_fp) {
1397                         cfg->locals_min_stack_offset = offset;
1398                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1399                 } else {
1400                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1401                         cfg->locals_max_stack_offset = - offset;
1402                 }
1403
1404                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1405                         if (offsets [i] != -1) {
1406                                 MonoInst *ins = cfg->varinfo [i];
1407                                 ins->opcode = OP_REGOFFSET;
1408                                 ins->inst_basereg = cfg->frame_reg;
1409                                 if (cfg->arch.omit_fp)
1410                                         ins->inst_offset = (offset + offsets [i]);
1411                                 else
1412                                         ins->inst_offset = - (offset + offsets [i]);
1413                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1414                         }
1415                 }
1416                 offset += locals_stack_size;
1417         }
1418
1419         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1420                 g_assert (!cfg->arch.omit_fp);
1421                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1422                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1423         }
1424
1425         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1426                 ins = cfg->args [i];
1427                 if (ins->opcode != OP_REGVAR) {
1428                         ArgInfo *ainfo = &cinfo->args [i];
1429                         gboolean inreg = TRUE;
1430                         MonoType *arg_type;
1431
1432                         if (sig->hasthis && (i == 0))
1433                                 arg_type = &mono_defaults.object_class->byval_arg;
1434                         else
1435                                 arg_type = sig->params [i - sig->hasthis];
1436
1437                         if (cfg->globalra) {
1438                                 /* The new allocator needs info about the original locations of the arguments */
1439                                 switch (ainfo->storage) {
1440                                 case ArgInIReg:
1441                                 case ArgInFloatSSEReg:
1442                                 case ArgInDoubleSSEReg:
1443                                         ins->opcode = OP_REGVAR;
1444                                         ins->inst_c0 = ainfo->reg;
1445                                         break;
1446                                 case ArgOnStack:
1447                                         g_assert (!cfg->arch.omit_fp);
1448                                         ins->opcode = OP_REGOFFSET;
1449                                         ins->inst_basereg = cfg->frame_reg;
1450                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1451                                         break;
1452                                 case ArgValuetypeInReg:
1453                                         ins->opcode = OP_REGOFFSET;
1454                                         ins->inst_basereg = cfg->frame_reg;
1455                                         /* These arguments are saved to the stack in the prolog */
1456                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1457                                         if (cfg->arch.omit_fp) {
1458                                                 ins->inst_offset = offset;
1459                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1460                                         } else {
1461                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1462                                                 ins->inst_offset = - offset;
1463                                         }
1464                                         break;
1465                                 default:
1466                                         g_assert_not_reached ();
1467                                 }
1468
1469                                 continue;
1470                         }
1471
1472                         /* FIXME: Allocate volatile arguments to registers */
1473                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1474                                 inreg = FALSE;
1475
1476                         /*
1477                          * Under AMD64, all registers used to pass arguments to functions
1478                          * are volatile across calls.
1479                          * FIXME: Optimize this.
1480                          */
1481                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1482                                 inreg = FALSE;
1483
1484                         ins->opcode = OP_REGOFFSET;
1485
1486                         switch (ainfo->storage) {
1487                         case ArgInIReg:
1488                         case ArgInFloatSSEReg:
1489                         case ArgInDoubleSSEReg:
1490                                 if (inreg) {
1491                                         ins->opcode = OP_REGVAR;
1492                                         ins->dreg = ainfo->reg;
1493                                 }
1494                                 break;
1495                         case ArgOnStack:
1496                                 g_assert (!cfg->arch.omit_fp);
1497                                 ins->opcode = OP_REGOFFSET;
1498                                 ins->inst_basereg = cfg->frame_reg;
1499                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1500                                 break;
1501                         case ArgValuetypeInReg:
1502                                 break;
1503                         case ArgValuetypeAddrInIReg: {
1504                                 MonoInst *indir;
1505                                 g_assert (!cfg->arch.omit_fp);
1506
1507                                 MONO_INST_NEW (cfg, indir, 0);
1508                                 indir->opcode = OP_REGOFFSET;
1509                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1510                                         indir->inst_basereg = cfg->frame_reg;
1511                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1512                                         offset += (sizeof (gpointer));
1513                                         indir->inst_offset = - offset;
1514                                 }
1515                                 else {
1516                                         indir->inst_basereg = cfg->frame_reg;
1517                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1518                                 }
1519
1520                                 ins->opcode = OP_VTARG_ADDR;
1521                                 ins->inst_left = indir;
1522
1523                                 break;
1524                         }
1525                         default:
1526                                 NOT_IMPLEMENTED;
1527                         }
1528
1529                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1530                                 ins->opcode = OP_REGOFFSET;
1531                                 ins->inst_basereg = cfg->frame_reg;
1532                                 /* These arguments are saved to the stack in the prolog */
1533                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1534                                 if (cfg->arch.omit_fp) {
1535                                         ins->inst_offset = offset;
1536                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1537                                 } else {
1538                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1539                                         ins->inst_offset = - offset;
1540                                 }
1541                         }
1542                 }
1543         }
1544
1545         cfg->stack_offset = offset;
1546 }
1547
1548 void
1549 mono_arch_create_vars (MonoCompile *cfg)
1550 {
1551         MonoMethodSignature *sig;
1552         CallInfo *cinfo;
1553
1554         sig = mono_method_signature (cfg->method);
1555
1556         if (!cfg->arch.cinfo)
1557                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1558         cinfo = cfg->arch.cinfo;
1559
1560         if (cinfo->ret.storage == ArgValuetypeInReg)
1561                 cfg->ret_var_is_local = TRUE;
1562
1563         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1564                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1565                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1566                         printf ("vret_addr = ");
1567                         mono_print_ins (cfg->vret_addr);
1568                 }
1569         }
1570
1571 #ifdef MONO_AMD64_NO_PUSHES
1572         /*
1573          * When this is set, we pass arguments on the stack by moves, and by allocating
1574          * a bigger stack frame, instead of pushes.
1575          * Pushes complicate exception handling because the arguments on the stack have
1576          * to be popped each time a frame is unwound. They also make fp elimination
1577          * impossible.
1578          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1579          * on a new frame which doesn't include a param area.
1580          */
1581         cfg->arch.no_pushes = TRUE;
1582 #endif
1583 }
1584
1585 static void
1586 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1587 {
1588         MonoInst *ins;
1589
1590         switch (storage) {
1591         case ArgInIReg:
1592                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1593                 ins->dreg = mono_alloc_ireg (cfg);
1594                 ins->sreg1 = tree->dreg;
1595                 MONO_ADD_INS (cfg->cbb, ins);
1596                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1597                 break;
1598         case ArgInFloatSSEReg:
1599                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1600                 ins->dreg = mono_alloc_freg (cfg);
1601                 ins->sreg1 = tree->dreg;
1602                 MONO_ADD_INS (cfg->cbb, ins);
1603
1604                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1605                 break;
1606         case ArgInDoubleSSEReg:
1607                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1608                 ins->dreg = mono_alloc_freg (cfg);
1609                 ins->sreg1 = tree->dreg;
1610                 MONO_ADD_INS (cfg->cbb, ins);
1611
1612                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1613
1614                 break;
1615         default:
1616                 g_assert_not_reached ();
1617         }
1618 }
1619
1620 static int
1621 arg_storage_to_load_membase (ArgStorage storage)
1622 {
1623         switch (storage) {
1624         case ArgInIReg:
1625                 return OP_LOAD_MEMBASE;
1626         case ArgInDoubleSSEReg:
1627                 return OP_LOADR8_MEMBASE;
1628         case ArgInFloatSSEReg:
1629                 return OP_LOADR4_MEMBASE;
1630         default:
1631                 g_assert_not_reached ();
1632         }
1633
1634         return -1;
1635 }
1636
1637 static void
1638 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1639 {
1640         MonoInst *arg;
1641         MonoMethodSignature *tmp_sig;
1642         MonoInst *sig_arg;
1643
1644         if (call->tail_call)
1645                 NOT_IMPLEMENTED;
1646
1647         /* FIXME: Add support for signature tokens to AOT */
1648         cfg->disable_aot = TRUE;
1649
1650         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1651
1652         /*
1653          * mono_ArgIterator_Setup assumes the signature cookie is
1654          * passed first and all the arguments which were before it are
1655          * passed on the stack after the signature. So compensate by
1656          * passing a different signature.
1657          */
1658         tmp_sig = mono_metadata_signature_dup (call->signature);
1659         tmp_sig->param_count -= call->signature->sentinelpos;
1660         tmp_sig->sentinelpos = 0;
1661         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1662
1663         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1664         sig_arg->dreg = mono_alloc_ireg (cfg);
1665         sig_arg->inst_p0 = tmp_sig;
1666         MONO_ADD_INS (cfg->cbb, sig_arg);
1667
1668         if (cfg->arch.no_pushes) {
1669                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1670         } else {
1671                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1672                 arg->sreg1 = sig_arg->dreg;
1673                 MONO_ADD_INS (cfg->cbb, arg);
1674         }
1675 }
1676
1677 static inline LLVMArgStorage
1678 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1679 {
1680         switch (storage) {
1681         case ArgInIReg:
1682                 return LLVMArgInIReg;
1683         case ArgNone:
1684                 return LLVMArgNone;
1685         default:
1686                 g_assert_not_reached ();
1687                 return LLVMArgNone;
1688         }
1689 }
1690
1691 #ifdef ENABLE_LLVM
1692 LLVMCallInfo*
1693 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1694 {
1695         int i, n;
1696         CallInfo *cinfo;
1697         ArgInfo *ainfo;
1698         int j;
1699         LLVMCallInfo *linfo;
1700
1701         n = sig->param_count + sig->hasthis;
1702
1703         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1704
1705         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1706
1707         /*
1708          * LLVM always uses the native ABI while we use our own ABI, the
1709          * only difference is the handling of vtypes:
1710          * - we only pass/receive them in registers in some cases, and only
1711          *   in 1 or 2 integer registers.
1712          */
1713         if (cinfo->ret.storage == ArgValuetypeInReg) {
1714                 if (sig->pinvoke) {
1715                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1716                         cfg->disable_llvm = TRUE;
1717                         return linfo;
1718                 }
1719
1720                 linfo->ret.storage = LLVMArgVtypeInReg;
1721                 for (j = 0; j < 2; ++j)
1722                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1723         }
1724
1725         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1726                 /* Vtype returned using a hidden argument */
1727                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1728         }
1729
1730         for (i = 0; i < n; ++i) {
1731                 ainfo = cinfo->args + i;
1732
1733                 linfo->args [i].storage = LLVMArgNone;
1734
1735                 switch (ainfo->storage) {
1736                 case ArgInIReg:
1737                         linfo->args [i].storage = LLVMArgInIReg;
1738                         break;
1739                 case ArgInDoubleSSEReg:
1740                 case ArgInFloatSSEReg:
1741                         linfo->args [i].storage = LLVMArgInFPReg;
1742                         break;
1743                 case ArgOnStack:
1744                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1745                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1746                         } else {
1747                                 linfo->args [i].storage = LLVMArgInIReg;
1748                                 if (!sig->params [i - sig->hasthis]->byref) {
1749                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1750                                                 linfo->args [i].storage = LLVMArgInFPReg;
1751                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1752                                                 linfo->args [i].storage = LLVMArgInFPReg;
1753                                         }
1754                                 }
1755                         }
1756                         break;
1757                 case ArgValuetypeInReg:
1758                         if (sig->pinvoke) {
1759                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1760                                 cfg->disable_llvm = TRUE;
1761                                 return linfo;
1762                         }
1763
1764                         linfo->args [i].storage = LLVMArgVtypeInReg;
1765                         for (j = 0; j < 2; ++j)
1766                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1767                         break;
1768                 default:
1769                         cfg->exception_message = g_strdup ("ainfo->storage");
1770                         cfg->disable_llvm = TRUE;
1771                         break;
1772                 }
1773         }
1774
1775         return linfo;
1776 }
1777 #endif
1778
1779 void
1780 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1781 {
1782         MonoInst *arg, *in;
1783         MonoMethodSignature *sig;
1784         int i, n, stack_size;
1785         CallInfo *cinfo;
1786         ArgInfo *ainfo;
1787
1788         stack_size = 0;
1789
1790         sig = call->signature;
1791         n = sig->param_count + sig->hasthis;
1792
1793         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1794
1795         if (COMPILE_LLVM (cfg)) {
1796                 /* We shouldn't be called in the llvm case */
1797                 cfg->disable_llvm = TRUE;
1798                 return;
1799         }
1800
1801         if (cinfo->need_stack_align) {
1802                 if (!cfg->arch.no_pushes)
1803                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1804         }
1805
1806         /*
1807          * Emit all arguments which are passed on the stack to prevent register
1808          * allocation problems.
1809          */
1810         if (cfg->arch.no_pushes) {
1811                 for (i = 0; i < n; ++i) {
1812                         MonoType *t;
1813                         ainfo = cinfo->args + i;
1814
1815                         in = call->args [i];
1816
1817                         if (sig->hasthis && i == 0)
1818                                 t = &mono_defaults.object_class->byval_arg;
1819                         else
1820                                 t = sig->params [i - sig->hasthis];
1821
1822                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1823                                 if (!t->byref) {
1824                                         if (t->type == MONO_TYPE_R4)
1825                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1826                                         else if (t->type == MONO_TYPE_R8)
1827                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1828                                         else
1829                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1830                                 } else {
1831                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1832                                 }
1833                         }
1834                 }
1835         }
1836
1837         /*
1838          * Emit all parameters passed in registers in non-reverse order for better readability
1839          * and to help the optimization in emit_prolog ().
1840          */
1841         for (i = 0; i < n; ++i) {
1842                 ainfo = cinfo->args + i;
1843
1844                 in = call->args [i];
1845
1846                 if (ainfo->storage == ArgInIReg)
1847                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1848         }
1849
1850         for (i = n - 1; i >= 0; --i) {
1851                 ainfo = cinfo->args + i;
1852
1853                 in = call->args [i];
1854
1855                 switch (ainfo->storage) {
1856                 case ArgInIReg:
1857                         /* Already done */
1858                         break;
1859                 case ArgInFloatSSEReg:
1860                 case ArgInDoubleSSEReg:
1861                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1862                         break;
1863                 case ArgOnStack:
1864                 case ArgValuetypeInReg:
1865                 case ArgValuetypeAddrInIReg:
1866                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1867                                 MonoInst *call_inst = (MonoInst*)call;
1868                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1869                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1870                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1871                                 guint32 align;
1872                                 guint32 size;
1873
1874                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1875                                         size = sizeof (MonoTypedRef);
1876                                         align = sizeof (gpointer);
1877                                 }
1878                                 else {
1879                                         if (sig->pinvoke)
1880                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1881                                         else {
1882                                                 /*
1883                                                  * Other backends use mono_type_stack_size (), but that
1884                                                  * aligns the size to 8, which is larger than the size of
1885                                                  * the source, leading to reads of invalid memory if the
1886                                                  * source is at the end of address space.
1887                                                  */
1888                                                 size = mono_class_value_size (in->klass, &align);
1889                                         }
1890                                 }
1891                                 g_assert (in->klass);
1892
1893                                 if (size > 0) {
1894                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1895                                         arg->sreg1 = in->dreg;
1896                                         arg->klass = in->klass;
1897                                         arg->backend.size = size;
1898                                         arg->inst_p0 = call;
1899                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1900                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1901
1902                                         MONO_ADD_INS (cfg->cbb, arg);
1903                                 }
1904                         } else {
1905                                 if (cfg->arch.no_pushes) {
1906                                         /* Already done */
1907                                 } else {
1908                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1909                                         arg->sreg1 = in->dreg;
1910                                         if (!sig->params [i - sig->hasthis]->byref) {
1911                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1912                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1913                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
1914                                                         arg->inst_destbasereg = X86_ESP;
1915                                                         arg->inst_offset = 0;
1916                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1917                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1918                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
1919                                                         arg->inst_destbasereg = X86_ESP;
1920                                                         arg->inst_offset = 0;
1921                                                 }
1922                                         }
1923                                         MONO_ADD_INS (cfg->cbb, arg);
1924                                 }
1925                         }
1926                         break;
1927                 default:
1928                         g_assert_not_reached ();
1929                 }
1930
1931                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1932                         /* Emit the signature cookie just before the implicit arguments */
1933                         emit_sig_cookie (cfg, call, cinfo);
1934         }
1935
1936         /* Handle the case where there are no implicit arguments */
1937         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1938                 emit_sig_cookie (cfg, call, cinfo);
1939
1940         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1941                 MonoInst *vtarg;
1942
1943                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1944                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1945                                 /*
1946                                  * Tell the JIT to use a more efficient calling convention: call using
1947                                  * OP_CALL, compute the result location after the call, and save the
1948                                  * result there.
1949                                  */
1950                                 call->vret_in_reg = TRUE;
1951                                 /*
1952                                  * Nullify the instruction computing the vret addr to enable
1953                                  * future optimizations.
1954                                  */
1955                                 if (call->vret_var)
1956                                         NULLIFY_INS (call->vret_var);
1957                         } else {
1958                                 if (call->tail_call)
1959                                         NOT_IMPLEMENTED;
1960                                 /*
1961                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1962                                  * the stack. Push the address here, so the call instruction can
1963                                  * access it.
1964                                  */
1965                                 if (!cfg->arch.vret_addr_loc) {
1966                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1967                                         /* Prevent it from being register allocated or optimized away */
1968                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1969                                 }
1970
1971                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1972                         }
1973                 }
1974                 else {
1975                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1976                         vtarg->sreg1 = call->vret_var->dreg;
1977                         vtarg->dreg = mono_alloc_preg (cfg);
1978                         MONO_ADD_INS (cfg->cbb, vtarg);
1979
1980                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1981                 }
1982         }
1983
1984 #ifdef PLATFORM_WIN32
1985         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1986                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1987         }
1988 #endif
1989
1990         if (cfg->method->save_lmf) {
1991                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1992                 MONO_ADD_INS (cfg->cbb, arg);
1993         }
1994
1995         call->stack_usage = cinfo->stack_usage;
1996 }
1997
1998 void
1999 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2000 {
2001         MonoInst *arg;
2002         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2003         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2004         int size = ins->backend.size;
2005
2006         if (ainfo->storage == ArgValuetypeInReg) {
2007                 MonoInst *load;
2008                 int part;
2009
2010                 for (part = 0; part < 2; ++part) {
2011                         if (ainfo->pair_storage [part] == ArgNone)
2012                                 continue;
2013
2014                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2015                         load->inst_basereg = src->dreg;
2016                         load->inst_offset = part * sizeof (gpointer);
2017
2018                         switch (ainfo->pair_storage [part]) {
2019                         case ArgInIReg:
2020                                 load->dreg = mono_alloc_ireg (cfg);
2021                                 break;
2022                         case ArgInDoubleSSEReg:
2023                         case ArgInFloatSSEReg:
2024                                 load->dreg = mono_alloc_freg (cfg);
2025                                 break;
2026                         default:
2027                                 g_assert_not_reached ();
2028                         }
2029                         MONO_ADD_INS (cfg->cbb, load);
2030
2031                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2032                 }
2033         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2034                 MonoInst *vtaddr, *load;
2035                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2036
2037                 g_assert (!cfg->arch.no_pushes);
2038
2039                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2040                 load->inst_p0 = vtaddr;
2041                 vtaddr->flags |= MONO_INST_INDIRECT;
2042                 load->type = STACK_MP;
2043                 load->klass = vtaddr->klass;
2044                 load->dreg = mono_alloc_ireg (cfg);
2045                 MONO_ADD_INS (cfg->cbb, load);
2046                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2047
2048                 if (ainfo->pair_storage [0] == ArgInIReg) {
2049                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2050                         arg->dreg = mono_alloc_ireg (cfg);
2051                         arg->sreg1 = load->dreg;
2052                         arg->inst_imm = 0;
2053                         MONO_ADD_INS (cfg->cbb, arg);
2054                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2055                 } else {
2056                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2057                         arg->sreg1 = load->dreg;
2058                         MONO_ADD_INS (cfg->cbb, arg);
2059                 }
2060         } else {
2061                 if (size == 8) {
2062                         if (cfg->arch.no_pushes) {
2063                                 int dreg = mono_alloc_ireg (cfg);
2064
2065                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2066                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2067                         } else {
2068                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2069                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2070                                 arg->inst_basereg = src->dreg;
2071                                 arg->inst_offset = 0;
2072                                 MONO_ADD_INS (cfg->cbb, arg);
2073                         }
2074                 } else if (size <= 40) {
2075                         if (cfg->arch.no_pushes) {
2076                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2077                         } else {
2078                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2079                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2080                         }
2081                 } else {
2082                         if (cfg->arch.no_pushes) {
2083                                 // FIXME: Code growth
2084                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2085                         } else {
2086                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2087                                 arg->inst_basereg = src->dreg;
2088                                 arg->inst_offset = 0;
2089                                 arg->inst_imm = size;
2090                                 MONO_ADD_INS (cfg->cbb, arg);
2091                         }
2092                 }
2093         }
2094 }
2095
2096 void
2097 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2098 {
2099         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2100
2101         if (!ret->byref) {
2102                 if (ret->type == MONO_TYPE_R4) {
2103                         if (COMPILE_LLVM (cfg))
2104                                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2105                         else
2106                                 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2107                         return;
2108                 } else if (ret->type == MONO_TYPE_R8) {
2109                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2110                         return;
2111                 }
2112         }
2113
2114         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2115 }
2116
2117 #define EMIT_COND_BRANCH(ins,cond,sign) \
2118         if (ins->inst_true_bb->native_offset) { \
2119                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2120         } else { \
2121                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2122                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2123             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2124                         x86_branch8 (code, cond, 0, sign); \
2125                 else \
2126                         x86_branch32 (code, cond, 0, sign); \
2127 }
2128
2129 /* emit an exception if condition is fail */
2130 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2131         do {                                                        \
2132                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2133                 if (tins == NULL) {                                                                             \
2134                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2135                                         MONO_PATCH_INFO_EXC, exc_name);  \
2136                         x86_branch32 (code, cond, 0, signed);               \
2137                 } else {        \
2138                         EMIT_COND_BRANCH (tins, cond, signed);  \
2139                 }                       \
2140         } while (0);
2141
2142 #define EMIT_FPCOMPARE(code) do { \
2143         amd64_fcompp (code); \
2144         amd64_fnstsw (code); \
2145 } while (0);
2146
2147 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2148     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2149         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2150         amd64_ ##op (code); \
2151         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2152         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2153 } while (0);
2154
2155 static guint8*
2156 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2157 {
2158         gboolean no_patch = FALSE;
2159
2160         /*
2161          * FIXME: Add support for thunks
2162          */
2163         {
2164                 gboolean near_call = FALSE;
2165
2166                 /*
2167                  * Indirect calls are expensive so try to make a near call if possible.
2168                  * The caller memory is allocated by the code manager so it is
2169                  * guaranteed to be at a 32 bit offset.
2170                  */
2171
2172                 if (patch_type != MONO_PATCH_INFO_ABS) {
2173                         /* The target is in memory allocated using the code manager */
2174                         near_call = TRUE;
2175
2176                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2177                                 if (((MonoMethod*)data)->klass->image->aot_module)
2178                                         /* The callee might be an AOT method */
2179                                         near_call = FALSE;
2180                                 if (((MonoMethod*)data)->dynamic)
2181                                         /* The target is in malloc-ed memory */
2182                                         near_call = FALSE;
2183                         }
2184
2185                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2186                                 /*
2187                                  * The call might go directly to a native function without
2188                                  * the wrapper.
2189                                  */
2190                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2191                                 if (mi) {
2192                                         gconstpointer target = mono_icall_get_wrapper (mi);
2193                                         if ((((guint64)target) >> 32) != 0)
2194                                                 near_call = FALSE;
2195                                 }
2196                         }
2197                 }
2198                 else {
2199                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2200                                 /*
2201                                  * This is not really an optimization, but required because the
2202                                  * generic class init trampolines use R11 to pass the vtable.
2203                                  */
2204                                 near_call = TRUE;
2205                         } else {
2206                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2207                                 if (info) {
2208                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2209                                                 strstr (cfg->method->name, info->name)) {
2210                                                 /* A call to the wrapped function */
2211                                                 if ((((guint64)data) >> 32) == 0)
2212                                                         near_call = TRUE;
2213                                                 no_patch = TRUE;
2214                                         }
2215                                         else if (info->func == info->wrapper) {
2216                                                 /* No wrapper */
2217                                                 if ((((guint64)info->func) >> 32) == 0)
2218                                                         near_call = TRUE;
2219                                         }
2220                                         else {
2221                                                 /* See the comment in mono_codegen () */
2222                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2223                                                         near_call = TRUE;
2224                                         }
2225                                 }
2226                                 else if ((((guint64)data) >> 32) == 0) {
2227                                         near_call = TRUE;
2228                                         no_patch = TRUE;
2229                                 }
2230                         }
2231                 }
2232
2233                 if (cfg->method->dynamic)
2234                         /* These methods are allocated using malloc */
2235                         near_call = FALSE;
2236
2237                 if (cfg->compile_aot) {
2238                         near_call = TRUE;
2239                         no_patch = TRUE;
2240                 }
2241
2242 #ifdef MONO_ARCH_NOMAP32BIT
2243                 near_call = FALSE;
2244 #endif
2245
2246                 if (near_call) {
2247                         /*
2248                          * Align the call displacement to an address divisible by 4 so it does
2249                          * not span cache lines. This is required for code patching to work on SMP
2250                          * systems.
2251                          */
2252                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2253                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2254                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2255                         amd64_call_code (code, 0);
2256                 }
2257                 else {
2258                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2259                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2260                         amd64_call_reg (code, GP_SCRATCH_REG);
2261                 }
2262         }
2263
2264         return code;
2265 }
2266
2267 static inline guint8*
2268 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2269 {
2270 #ifdef PLATFORM_WIN32
2271         if (win64_adjust_stack)
2272                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2273 #endif
2274         code = emit_call_body (cfg, code, patch_type, data);
2275 #ifdef PLATFORM_WIN32
2276         if (win64_adjust_stack)
2277                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2278 #endif
2279
2280         return code;
2281 }
2282
2283 static inline int
2284 store_membase_imm_to_store_membase_reg (int opcode)
2285 {
2286         switch (opcode) {
2287         case OP_STORE_MEMBASE_IMM:
2288                 return OP_STORE_MEMBASE_REG;
2289         case OP_STOREI4_MEMBASE_IMM:
2290                 return OP_STOREI4_MEMBASE_REG;
2291         case OP_STOREI8_MEMBASE_IMM:
2292                 return OP_STOREI8_MEMBASE_REG;
2293         }
2294
2295         return -1;
2296 }
2297
2298 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2299
2300 /*
2301  * mono_arch_peephole_pass_1:
2302  *
2303  *   Perform peephole opts which should/can be performed before local regalloc
2304  */
2305 void
2306 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2307 {
2308         MonoInst *ins, *n;
2309
2310         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2311                 MonoInst *last_ins = ins->prev;
2312
2313                 switch (ins->opcode) {
2314                 case OP_ADD_IMM:
2315                 case OP_IADD_IMM:
2316                 case OP_LADD_IMM:
2317                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2318                                 /*
2319                                  * X86_LEA is like ADD, but doesn't have the
2320                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2321                                  * its operand to 64 bit.
2322                                  */
2323                                 ins->opcode = OP_X86_LEA_MEMBASE;
2324                                 ins->inst_basereg = ins->sreg1;
2325                         }
2326                         break;
2327                 case OP_LXOR:
2328                 case OP_IXOR:
2329                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2330                                 MonoInst *ins2;
2331
2332                                 /*
2333                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2334                                  * the latter has length 2-3 instead of 6 (reverse constant
2335                                  * propagation). These instruction sequences are very common
2336                                  * in the initlocals bblock.
2337                                  */
2338                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2339                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2340                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2341                                                 ins2->sreg1 = ins->dreg;
2342                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2343                                                 /* Continue */
2344                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2345                                                 NULLIFY_INS (ins2);
2346                                                 /* Continue */
2347                                         } else {
2348                                                 break;
2349                                         }
2350                                 }
2351                         }
2352                         break;
2353                 case OP_COMPARE_IMM:
2354                 case OP_LCOMPARE_IMM:
2355                         /* OP_COMPARE_IMM (reg, 0)
2356                          * -->
2357                          * OP_AMD64_TEST_NULL (reg)
2358                          */
2359                         if (!ins->inst_imm)
2360                                 ins->opcode = OP_AMD64_TEST_NULL;
2361                         break;
2362                 case OP_ICOMPARE_IMM:
2363                         if (!ins->inst_imm)
2364                                 ins->opcode = OP_X86_TEST_NULL;
2365                         break;
2366                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2367                         /*
2368                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2369                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2370                          * -->
2371                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2372                          * OP_COMPARE_IMM reg, imm
2373                          *
2374                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2375                          */
2376                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2377                             ins->inst_basereg == last_ins->inst_destbasereg &&
2378                             ins->inst_offset == last_ins->inst_offset) {
2379                                         ins->opcode = OP_ICOMPARE_IMM;
2380                                         ins->sreg1 = last_ins->sreg1;
2381
2382                                         /* check if we can remove cmp reg,0 with test null */
2383                                         if (!ins->inst_imm)
2384                                                 ins->opcode = OP_X86_TEST_NULL;
2385                                 }
2386
2387                         break;
2388                 }
2389
2390                 mono_peephole_ins (bb, ins);
2391         }
2392 }
2393
2394 void
2395 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2396 {
2397         MonoInst *ins, *n;
2398
2399         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2400                 switch (ins->opcode) {
2401                 case OP_ICONST:
2402                 case OP_I8CONST: {
2403                         /* reg = 0 -> XOR (reg, reg) */
2404                         /* XOR sets cflags on x86, so we cant do it always */
2405                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2406                                 ins->opcode = OP_LXOR;
2407                                 ins->sreg1 = ins->dreg;
2408                                 ins->sreg2 = ins->dreg;
2409                                 /* Fall through */
2410                         } else {
2411                                 break;
2412                         }
2413                 }
2414                 case OP_LXOR:
2415                         /*
2416                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2417                          * 0 result into 64 bits.
2418                          */
2419                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2420                                 ins->opcode = OP_IXOR;
2421                         }
2422                         /* Fall through */
2423                 case OP_IXOR:
2424                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2425                                 MonoInst *ins2;
2426
2427                                 /*
2428                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2429                                  * the latter has length 2-3 instead of 6 (reverse constant
2430                                  * propagation). These instruction sequences are very common
2431                                  * in the initlocals bblock.
2432                                  */
2433                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2434                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2435                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2436                                                 ins2->sreg1 = ins->dreg;
2437                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2438                                                 /* Continue */
2439                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2440                                                 NULLIFY_INS (ins2);
2441                                                 /* Continue */
2442                                         } else {
2443                                                 break;
2444                                         }
2445                                 }
2446                         }
2447                         break;
2448                 case OP_IADD_IMM:
2449                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2450                                 ins->opcode = OP_X86_INC_REG;
2451                         break;
2452                 case OP_ISUB_IMM:
2453                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2454                                 ins->opcode = OP_X86_DEC_REG;
2455                         break;
2456                 }
2457
2458                 mono_peephole_ins (bb, ins);
2459         }
2460 }
2461
2462 #define NEW_INS(cfg,ins,dest,op) do {   \
2463                 MONO_INST_NEW ((cfg), (dest), (op)); \
2464         (dest)->cil_code = (ins)->cil_code; \
2465         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2466         } while (0)
2467
2468 /*
2469  * mono_arch_lowering_pass:
2470  *
2471  *  Converts complex opcodes into simpler ones so that each IR instruction
2472  * corresponds to one machine instruction.
2473  */
2474 void
2475 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2476 {
2477         MonoInst *ins, *n, *temp;
2478
2479         /*
2480          * FIXME: Need to add more instructions, but the current machine
2481          * description can't model some parts of the composite instructions like
2482          * cdq.
2483          */
2484         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2485                 switch (ins->opcode) {
2486                 case OP_DIV_IMM:
2487                 case OP_REM_IMM:
2488                 case OP_IDIV_IMM:
2489                 case OP_IDIV_UN_IMM:
2490                 case OP_IREM_UN_IMM:
2491                         mono_decompose_op_imm (cfg, bb, ins);
2492                         break;
2493                 case OP_IREM_IMM:
2494                         /* Keep the opcode if we can implement it efficiently */
2495                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2496                                 mono_decompose_op_imm (cfg, bb, ins);
2497                         break;
2498                 case OP_COMPARE_IMM:
2499                 case OP_LCOMPARE_IMM:
2500                         if (!amd64_is_imm32 (ins->inst_imm)) {
2501                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2502                                 temp->inst_c0 = ins->inst_imm;
2503                                 temp->dreg = mono_alloc_ireg (cfg);
2504                                 ins->opcode = OP_COMPARE;
2505                                 ins->sreg2 = temp->dreg;
2506                         }
2507                         break;
2508                 case OP_LOAD_MEMBASE:
2509                 case OP_LOADI8_MEMBASE:
2510                         if (!amd64_is_imm32 (ins->inst_offset)) {
2511                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2512                                 temp->inst_c0 = ins->inst_offset;
2513                                 temp->dreg = mono_alloc_ireg (cfg);
2514                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2515                                 ins->inst_indexreg = temp->dreg;
2516                         }
2517                         break;
2518                 case OP_STORE_MEMBASE_IMM:
2519                 case OP_STOREI8_MEMBASE_IMM:
2520                         if (!amd64_is_imm32 (ins->inst_imm)) {
2521                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2522                                 temp->inst_c0 = ins->inst_imm;
2523                                 temp->dreg = mono_alloc_ireg (cfg);
2524                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2525                                 ins->sreg1 = temp->dreg;
2526                         }
2527                         break;
2528 #ifdef MONO_ARCH_SIMD_INTRINSICS
2529                 case OP_EXPAND_I1: {
2530                                 int temp_reg1 = mono_alloc_ireg (cfg);
2531                                 int temp_reg2 = mono_alloc_ireg (cfg);
2532                                 int original_reg = ins->sreg1;
2533
2534                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2535                                 temp->sreg1 = original_reg;
2536                                 temp->dreg = temp_reg1;
2537
2538                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2539                                 temp->sreg1 = temp_reg1;
2540                                 temp->dreg = temp_reg2;
2541                                 temp->inst_imm = 8;
2542
2543                                 NEW_INS (cfg, ins, temp, OP_LOR);
2544                                 temp->sreg1 = temp->dreg = temp_reg2;
2545                                 temp->sreg2 = temp_reg1;
2546
2547                                 ins->opcode = OP_EXPAND_I2;
2548                                 ins->sreg1 = temp_reg2;
2549                         }
2550                         break;
2551 #endif
2552                 default:
2553                         break;
2554                 }
2555         }
2556
2557         bb->max_vreg = cfg->next_vreg;
2558 }
2559
2560 static const int
2561 branch_cc_table [] = {
2562         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2563         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2564         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2565 };
2566
2567 /* Maps CMP_... constants to X86_CC_... constants */
2568 static const int
2569 cc_table [] = {
2570         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2571         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2572 };
2573
2574 static const int
2575 cc_signed_table [] = {
2576         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2577         FALSE, FALSE, FALSE, FALSE
2578 };
2579
2580 /*#include "cprop.c"*/
2581
2582 static unsigned char*
2583 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2584 {
2585         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2586
2587         if (size == 1)
2588                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2589         else if (size == 2)
2590                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2591         return code;
2592 }
2593
2594 static unsigned char*
2595 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2596 {
2597         int sreg = tree->sreg1;
2598         int need_touch = FALSE;
2599
2600 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2601         if (!tree->flags & MONO_INST_INIT)
2602                 need_touch = TRUE;
2603 #endif
2604
2605         if (need_touch) {
2606                 guint8* br[5];
2607
2608                 /*
2609                  * Under Windows:
2610                  * If requested stack size is larger than one page,
2611                  * perform stack-touch operation
2612                  */
2613                 /*
2614                  * Generate stack probe code.
2615                  * Under Windows, it is necessary to allocate one page at a time,
2616                  * "touching" stack after each successful sub-allocation. This is
2617                  * because of the way stack growth is implemented - there is a
2618                  * guard page before the lowest stack page that is currently commited.
2619                  * Stack normally grows sequentially so OS traps access to the
2620                  * guard page and commits more pages when needed.
2621                  */
2622                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2623                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2624
2625                 br[2] = code; /* loop */
2626                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2627                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2628                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2629                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2630                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2631                 amd64_patch (br[3], br[2]);
2632                 amd64_test_reg_reg (code, sreg, sreg);
2633                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2634                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2635
2636                 br[1] = code; x86_jump8 (code, 0);
2637
2638                 amd64_patch (br[0], code);
2639                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2640                 amd64_patch (br[1], code);
2641                 amd64_patch (br[4], code);
2642         }
2643         else
2644                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2645
2646         if (tree->flags & MONO_INST_INIT) {
2647                 int offset = 0;
2648                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2649                         amd64_push_reg (code, AMD64_RAX);
2650                         offset += 8;
2651                 }
2652                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2653                         amd64_push_reg (code, AMD64_RCX);
2654                         offset += 8;
2655                 }
2656                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2657                         amd64_push_reg (code, AMD64_RDI);
2658                         offset += 8;
2659                 }
2660
2661                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2662                 if (sreg != AMD64_RCX)
2663                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2664                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2665
2666                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2667                 if (cfg->param_area && cfg->arch.no_pushes)
2668                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
2669                 amd64_cld (code);
2670                 amd64_prefix (code, X86_REP_PREFIX);
2671                 amd64_stosl (code);
2672
2673                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2674                         amd64_pop_reg (code, AMD64_RDI);
2675                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2676                         amd64_pop_reg (code, AMD64_RCX);
2677                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2678                         amd64_pop_reg (code, AMD64_RAX);
2679         }
2680         return code;
2681 }
2682
2683 static guint8*
2684 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2685 {
2686         CallInfo *cinfo;
2687         guint32 quad;
2688
2689         /* Move return value to the target register */
2690         /* FIXME: do this in the local reg allocator */
2691         switch (ins->opcode) {
2692         case OP_CALL:
2693         case OP_CALL_REG:
2694         case OP_CALL_MEMBASE:
2695         case OP_LCALL:
2696         case OP_LCALL_REG:
2697         case OP_LCALL_MEMBASE:
2698                 g_assert (ins->dreg == AMD64_RAX);
2699                 break;
2700         case OP_FCALL:
2701         case OP_FCALL_REG:
2702         case OP_FCALL_MEMBASE:
2703                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2704                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2705                 }
2706                 else {
2707                         if (ins->dreg != AMD64_XMM0)
2708                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2709                 }
2710                 break;
2711         case OP_VCALL:
2712         case OP_VCALL_REG:
2713         case OP_VCALL_MEMBASE:
2714         case OP_VCALL2:
2715         case OP_VCALL2_REG:
2716         case OP_VCALL2_MEMBASE:
2717                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2718                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2719                         MonoInst *loc = cfg->arch.vret_addr_loc;
2720
2721                         /* Load the destination address */
2722                         g_assert (loc->opcode == OP_REGOFFSET);
2723                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2724
2725                         for (quad = 0; quad < 2; quad ++) {
2726                                 switch (cinfo->ret.pair_storage [quad]) {
2727                                 case ArgInIReg:
2728                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2729                                         break;
2730                                 case ArgInFloatSSEReg:
2731                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2732                                         break;
2733                                 case ArgInDoubleSSEReg:
2734                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2735                                         break;
2736                                 case ArgNone:
2737                                         break;
2738                                 default:
2739                                         NOT_IMPLEMENTED;
2740                                 }
2741                         }
2742                 }
2743                 break;
2744         }
2745
2746         return code;
2747 }
2748
2749 /*
2750  * mono_amd64_emit_tls_get:
2751  * @code: buffer to store code to
2752  * @dreg: hard register where to place the result
2753  * @tls_offset: offset info
2754  *
2755  * mono_amd64_emit_tls_get emits in @code the native code that puts in
2756  * the dreg register the item in the thread local storage identified
2757  * by tls_offset.
2758  *
2759  * Returns: a pointer to the end of the stored code
2760  */
2761 guint8*
2762 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
2763 {
2764 #ifdef PLATFORM_WIN32
2765         g_assert (tls_offset < 64);
2766         x86_prefix (code, X86_GS_PREFIX);
2767         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2768 #else
2769         if (optimize_for_xen) {
2770                 x86_prefix (code, X86_FS_PREFIX);
2771                 amd64_mov_reg_mem (code, dreg, 0, 8);
2772                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2773         } else {
2774                 x86_prefix (code, X86_FS_PREFIX);
2775                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2776         }
2777 #endif
2778         return code;
2779 }
2780
2781 #define REAL_PRINT_REG(text,reg) \
2782 mono_assert (reg >= 0); \
2783 amd64_push_reg (code, AMD64_RAX); \
2784 amd64_push_reg (code, AMD64_RDX); \
2785 amd64_push_reg (code, AMD64_RCX); \
2786 amd64_push_reg (code, reg); \
2787 amd64_push_imm (code, reg); \
2788 amd64_push_imm (code, text " %d %p\n"); \
2789 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2790 amd64_call_reg (code, AMD64_RAX); \
2791 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2792 amd64_pop_reg (code, AMD64_RCX); \
2793 amd64_pop_reg (code, AMD64_RDX); \
2794 amd64_pop_reg (code, AMD64_RAX);
2795
2796 /* benchmark and set based on cpu */
2797 #define LOOP_ALIGNMENT 8
2798 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2799
2800 #ifndef DISABLE_JIT
2801
2802 void
2803 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2804 {
2805         MonoInst *ins;
2806         MonoCallInst *call;
2807         guint offset;
2808         guint8 *code = cfg->native_code + cfg->code_len;
2809         MonoInst *last_ins = NULL;
2810         guint last_offset = 0;
2811         int max_len;
2812
2813         /* Fix max_offset estimate for each successor bb */
2814         if (cfg->opt & MONO_OPT_BRANCH) {
2815                 int current_offset = cfg->code_len;
2816                 MonoBasicBlock *current_bb;
2817                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
2818                         current_bb->max_offset = current_offset;
2819                         current_offset += current_bb->max_length;
2820                 }
2821         }
2822
2823         if (cfg->opt & MONO_OPT_LOOP) {
2824                 int pad, align = LOOP_ALIGNMENT;
2825                 /* set alignment depending on cpu */
2826                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2827                         pad = align - pad;
2828                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2829                         amd64_padding (code, pad);
2830                         cfg->code_len += pad;
2831                         bb->native_offset = cfg->code_len;
2832                 }
2833         }
2834
2835         if (cfg->verbose_level > 2)
2836                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2837
2838         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2839                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2840                 g_assert (!cfg->compile_aot);
2841
2842                 cov->data [bb->dfn].cil_code = bb->cil_code;
2843                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2844                 /* this is not thread save, but good enough */
2845                 amd64_inc_membase (code, AMD64_R11, 0);
2846         }
2847
2848         offset = code - cfg->native_code;
2849
2850         mono_debug_open_block (cfg, bb, offset);
2851
2852     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
2853                 x86_breakpoint (code);
2854
2855         MONO_BB_FOR_EACH_INS (bb, ins) {
2856                 offset = code - cfg->native_code;
2857
2858                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2859
2860                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2861                         cfg->code_size *= 2;
2862                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2863                         code = cfg->native_code + offset;
2864                         mono_jit_stats.code_reallocs++;
2865                 }
2866
2867                 if (cfg->debug_info)
2868                         mono_debug_record_line_number (cfg, ins, offset);
2869
2870                 switch (ins->opcode) {
2871                 case OP_BIGMUL:
2872                         amd64_mul_reg (code, ins->sreg2, TRUE);
2873                         break;
2874                 case OP_BIGMUL_UN:
2875                         amd64_mul_reg (code, ins->sreg2, FALSE);
2876                         break;
2877                 case OP_X86_SETEQ_MEMBASE:
2878                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2879                         break;
2880                 case OP_STOREI1_MEMBASE_IMM:
2881                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2882                         break;
2883                 case OP_STOREI2_MEMBASE_IMM:
2884                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2885                         break;
2886                 case OP_STOREI4_MEMBASE_IMM:
2887                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2888                         break;
2889                 case OP_STOREI1_MEMBASE_REG:
2890                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2891                         break;
2892                 case OP_STOREI2_MEMBASE_REG:
2893                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2894                         break;
2895                 case OP_STORE_MEMBASE_REG:
2896                 case OP_STOREI8_MEMBASE_REG:
2897                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2898                         break;
2899                 case OP_STOREI4_MEMBASE_REG:
2900                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2901                         break;
2902                 case OP_STORE_MEMBASE_IMM:
2903                 case OP_STOREI8_MEMBASE_IMM:
2904                         g_assert (amd64_is_imm32 (ins->inst_imm));
2905                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2906                         break;
2907                 case OP_LOAD_MEM:
2908                 case OP_LOADI8_MEM:
2909                         // FIXME: Decompose this earlier
2910                         if (amd64_is_imm32 (ins->inst_imm))
2911                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2912                         else {
2913                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2914                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2915                         }
2916                         break;
2917                 case OP_LOADI4_MEM:
2918                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2919                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2920                         break;
2921                 case OP_LOADU4_MEM:
2922                         // FIXME: Decompose this earlier
2923                         if (amd64_is_imm32 (ins->inst_imm))
2924                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
2925                         else {
2926                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2927                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2928                         }
2929                         break;
2930                 case OP_LOADU1_MEM:
2931                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2932                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2933                         break;
2934                 case OP_LOADU2_MEM:
2935                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2936                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2937                         break;
2938                 case OP_LOAD_MEMBASE:
2939                 case OP_LOADI8_MEMBASE:
2940                         g_assert (amd64_is_imm32 (ins->inst_offset));
2941                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2942                         break;
2943                 case OP_LOADI4_MEMBASE:
2944                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2945                         break;
2946                 case OP_LOADU4_MEMBASE:
2947                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2948                         break;
2949                 case OP_LOADU1_MEMBASE:
2950                         /* The cpu zero extends the result into 64 bits */
2951                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
2952                         break;
2953                 case OP_LOADI1_MEMBASE:
2954                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2955                         break;
2956                 case OP_LOADU2_MEMBASE:
2957                         /* The cpu zero extends the result into 64 bits */
2958                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
2959                         break;
2960                 case OP_LOADI2_MEMBASE:
2961                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2962                         break;
2963                 case OP_AMD64_LOADI8_MEMINDEX:
2964                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2965                         break;
2966                 case OP_LCONV_TO_I1:
2967                 case OP_ICONV_TO_I1:
2968                 case OP_SEXT_I1:
2969                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2970                         break;
2971                 case OP_LCONV_TO_I2:
2972                 case OP_ICONV_TO_I2:
2973                 case OP_SEXT_I2:
2974                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2975                         break;
2976                 case OP_LCONV_TO_U1:
2977                 case OP_ICONV_TO_U1:
2978                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2979                         break;
2980                 case OP_LCONV_TO_U2:
2981                 case OP_ICONV_TO_U2:
2982                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2983                         break;
2984                 case OP_ZEXT_I4:
2985                         /* Clean out the upper word */
2986                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2987                         break;
2988                 case OP_SEXT_I4:
2989                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2990                         break;
2991                 case OP_COMPARE:
2992                 case OP_LCOMPARE:
2993                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2994                         break;
2995                 case OP_COMPARE_IMM:
2996                 case OP_LCOMPARE_IMM:
2997                         g_assert (amd64_is_imm32 (ins->inst_imm));
2998                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2999                         break;
3000                 case OP_X86_COMPARE_REG_MEMBASE:
3001                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3002                         break;
3003                 case OP_X86_TEST_NULL:
3004                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3005                         break;
3006                 case OP_AMD64_TEST_NULL:
3007                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3008                         break;
3009
3010                 case OP_X86_ADD_REG_MEMBASE:
3011                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3012                         break;
3013                 case OP_X86_SUB_REG_MEMBASE:
3014                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3015                         break;
3016                 case OP_X86_AND_REG_MEMBASE:
3017                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3018                         break;
3019                 case OP_X86_OR_REG_MEMBASE:
3020                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3021                         break;
3022                 case OP_X86_XOR_REG_MEMBASE:
3023                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3024                         break;
3025
3026                 case OP_X86_ADD_MEMBASE_IMM:
3027                         /* FIXME: Make a 64 version too */
3028                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3029                         break;
3030                 case OP_X86_SUB_MEMBASE_IMM:
3031                         g_assert (amd64_is_imm32 (ins->inst_imm));
3032                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3033                         break;
3034                 case OP_X86_AND_MEMBASE_IMM:
3035                         g_assert (amd64_is_imm32 (ins->inst_imm));
3036                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3037                         break;
3038                 case OP_X86_OR_MEMBASE_IMM:
3039                         g_assert (amd64_is_imm32 (ins->inst_imm));
3040                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3041                         break;
3042                 case OP_X86_XOR_MEMBASE_IMM:
3043                         g_assert (amd64_is_imm32 (ins->inst_imm));
3044                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3045                         break;
3046                 case OP_X86_ADD_MEMBASE_REG:
3047                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3048                         break;
3049                 case OP_X86_SUB_MEMBASE_REG:
3050                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3051                         break;
3052                 case OP_X86_AND_MEMBASE_REG:
3053                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3054                         break;
3055                 case OP_X86_OR_MEMBASE_REG:
3056                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3057                         break;
3058                 case OP_X86_XOR_MEMBASE_REG:
3059                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3060                         break;
3061                 case OP_X86_INC_MEMBASE:
3062                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3063                         break;
3064                 case OP_X86_INC_REG:
3065                         amd64_inc_reg_size (code, ins->dreg, 4);
3066                         break;
3067                 case OP_X86_DEC_MEMBASE:
3068                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3069                         break;
3070                 case OP_X86_DEC_REG:
3071                         amd64_dec_reg_size (code, ins->dreg, 4);
3072                         break;
3073                 case OP_X86_MUL_REG_MEMBASE:
3074                 case OP_X86_MUL_MEMBASE_REG:
3075                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3076                         break;
3077                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3078                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3079                         break;
3080                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3081                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3082                         break;
3083                 case OP_AMD64_COMPARE_MEMBASE_REG:
3084                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3085                         break;
3086                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3087                         g_assert (amd64_is_imm32 (ins->inst_imm));
3088                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3089                         break;
3090                 case OP_X86_COMPARE_MEMBASE8_IMM:
3091                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3092                         break;
3093                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3094                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3095                         break;
3096                 case OP_AMD64_COMPARE_REG_MEMBASE:
3097                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3098                         break;
3099
3100                 case OP_AMD64_ADD_REG_MEMBASE:
3101                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3102                         break;
3103                 case OP_AMD64_SUB_REG_MEMBASE:
3104                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3105                         break;
3106                 case OP_AMD64_AND_REG_MEMBASE:
3107                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3108                         break;
3109                 case OP_AMD64_OR_REG_MEMBASE:
3110                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3111                         break;
3112                 case OP_AMD64_XOR_REG_MEMBASE:
3113                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3114                         break;
3115
3116                 case OP_AMD64_ADD_MEMBASE_REG:
3117                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3118                         break;
3119                 case OP_AMD64_SUB_MEMBASE_REG:
3120                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3121                         break;
3122                 case OP_AMD64_AND_MEMBASE_REG:
3123                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3124                         break;
3125                 case OP_AMD64_OR_MEMBASE_REG:
3126                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3127                         break;
3128                 case OP_AMD64_XOR_MEMBASE_REG:
3129                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3130                         break;
3131
3132                 case OP_AMD64_ADD_MEMBASE_IMM:
3133                         g_assert (amd64_is_imm32 (ins->inst_imm));
3134                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3135                         break;
3136                 case OP_AMD64_SUB_MEMBASE_IMM:
3137                         g_assert (amd64_is_imm32 (ins->inst_imm));
3138                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3139                         break;
3140                 case OP_AMD64_AND_MEMBASE_IMM:
3141                         g_assert (amd64_is_imm32 (ins->inst_imm));
3142                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3143                         break;
3144                 case OP_AMD64_OR_MEMBASE_IMM:
3145                         g_assert (amd64_is_imm32 (ins->inst_imm));
3146                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3147                         break;
3148                 case OP_AMD64_XOR_MEMBASE_IMM:
3149                         g_assert (amd64_is_imm32 (ins->inst_imm));
3150                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3151                         break;
3152
3153                 case OP_BREAK:
3154                         amd64_breakpoint (code);
3155                         break;
3156                 case OP_RELAXED_NOP:
3157                         x86_prefix (code, X86_REP_PREFIX);
3158                         x86_nop (code);
3159                         break;
3160                 case OP_HARD_NOP:
3161                         x86_nop (code);
3162                         break;
3163                 case OP_NOP:
3164                 case OP_DUMMY_USE:
3165                 case OP_DUMMY_STORE:
3166                 case OP_NOT_REACHED:
3167                 case OP_NOT_NULL:
3168                         break;
3169                 case OP_ADDCC:
3170                 case OP_LADD:
3171                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3172                         break;
3173                 case OP_ADC:
3174                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3175                         break;
3176                 case OP_ADD_IMM:
3177                 case OP_LADD_IMM:
3178                         g_assert (amd64_is_imm32 (ins->inst_imm));
3179                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3180                         break;
3181                 case OP_ADC_IMM:
3182                         g_assert (amd64_is_imm32 (ins->inst_imm));
3183                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3184                         break;
3185                 case OP_SUBCC:
3186                 case OP_LSUB:
3187                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3188                         break;
3189                 case OP_SBB:
3190                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3191                         break;
3192                 case OP_SUB_IMM:
3193                 case OP_LSUB_IMM:
3194                         g_assert (amd64_is_imm32 (ins->inst_imm));
3195                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3196                         break;
3197                 case OP_SBB_IMM:
3198                         g_assert (amd64_is_imm32 (ins->inst_imm));
3199                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3200                         break;
3201                 case OP_LAND:
3202                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3203                         break;
3204                 case OP_AND_IMM:
3205                 case OP_LAND_IMM:
3206                         g_assert (amd64_is_imm32 (ins->inst_imm));
3207                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3208                         break;
3209                 case OP_LMUL:
3210                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3211                         break;
3212                 case OP_MUL_IMM:
3213                 case OP_LMUL_IMM:
3214                 case OP_IMUL_IMM: {
3215                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3216
3217                         switch (ins->inst_imm) {
3218                         case 2:
3219                                 /* MOV r1, r2 */
3220                                 /* ADD r1, r1 */
3221                                 if (ins->dreg != ins->sreg1)
3222                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3223                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3224                                 break;
3225                         case 3:
3226                                 /* LEA r1, [r2 + r2*2] */
3227                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3228                                 break;
3229                         case 5:
3230                                 /* LEA r1, [r2 + r2*4] */
3231                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3232                                 break;
3233                         case 6:
3234                                 /* LEA r1, [r2 + r2*2] */
3235                                 /* ADD r1, r1          */
3236                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3237                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3238                                 break;
3239                         case 9:
3240                                 /* LEA r1, [r2 + r2*8] */
3241                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3242                                 break;
3243                         case 10:
3244                                 /* LEA r1, [r2 + r2*4] */
3245                                 /* ADD r1, r1          */
3246                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3247                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3248                                 break;
3249                         case 12:
3250                                 /* LEA r1, [r2 + r2*2] */
3251                                 /* SHL r1, 2           */
3252                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3253                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3254                                 break;
3255                         case 25:
3256                                 /* LEA r1, [r2 + r2*4] */
3257                                 /* LEA r1, [r1 + r1*4] */
3258                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3259                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3260                                 break;
3261                         case 100:
3262                                 /* LEA r1, [r2 + r2*4] */
3263                                 /* SHL r1, 2           */
3264                                 /* LEA r1, [r1 + r1*4] */
3265                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3266                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3267                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3268                                 break;
3269                         default:
3270                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3271                                 break;
3272                         }
3273                         break;
3274                 }
3275                 case OP_LDIV:
3276                 case OP_LREM:
3277                         /* Regalloc magic makes the div/rem cases the same */
3278                         if (ins->sreg2 == AMD64_RDX) {
3279                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3280                                 amd64_cdq (code);
3281                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3282                         } else {
3283                                 amd64_cdq (code);
3284                                 amd64_div_reg (code, ins->sreg2, TRUE);
3285                         }
3286                         break;
3287                 case OP_LDIV_UN:
3288                 case OP_LREM_UN:
3289                         if (ins->sreg2 == AMD64_RDX) {
3290                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3291                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3292                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3293                         } else {
3294                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3295                                 amd64_div_reg (code, ins->sreg2, FALSE);
3296                         }
3297                         break;
3298                 case OP_IDIV:
3299                 case OP_IREM:
3300                         if (ins->sreg2 == AMD64_RDX) {
3301                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3302                                 amd64_cdq_size (code, 4);
3303                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3304                         } else {
3305                                 amd64_cdq_size (code, 4);
3306                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3307                         }
3308                         break;
3309                 case OP_IDIV_UN:
3310                 case OP_IREM_UN:
3311                         if (ins->sreg2 == AMD64_RDX) {
3312                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3313                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3314                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3315                         } else {
3316                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3317                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3318                         }
3319                         break;
3320                 case OP_IREM_IMM: {
3321                         int power = mono_is_power_of_two (ins->inst_imm);
3322
3323                         g_assert (ins->sreg1 == X86_EAX);
3324                         g_assert (ins->dreg == X86_EAX);
3325                         g_assert (power >= 0);
3326
3327                         if (power == 0) {
3328                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3329                                 break;
3330                         }
3331
3332                         /* Based on gcc code */
3333
3334                         /* Add compensation for negative dividents */
3335                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3336                         if (power > 1)
3337                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3338                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3339                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3340                         /* Compute remainder */
3341                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3342                         /* Remove compensation */
3343                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3344                         break;
3345                 }
3346                 case OP_LMUL_OVF:
3347                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3348                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3349                         break;
3350                 case OP_LOR:
3351                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3352                         break;
3353                 case OP_OR_IMM:
3354                 case OP_LOR_IMM:
3355                         g_assert (amd64_is_imm32 (ins->inst_imm));
3356                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3357                         break;
3358                 case OP_LXOR:
3359                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3360                         break;
3361                 case OP_XOR_IMM:
3362                 case OP_LXOR_IMM:
3363                         g_assert (amd64_is_imm32 (ins->inst_imm));
3364                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3365                         break;
3366                 case OP_LSHL:
3367                         g_assert (ins->sreg2 == AMD64_RCX);
3368                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3369                         break;
3370                 case OP_LSHR:
3371                         g_assert (ins->sreg2 == AMD64_RCX);
3372                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3373                         break;
3374                 case OP_SHR_IMM:
3375                         g_assert (amd64_is_imm32 (ins->inst_imm));
3376                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3377                         break;
3378                 case OP_LSHR_IMM:
3379                         g_assert (amd64_is_imm32 (ins->inst_imm));
3380                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3381                         break;
3382                 case OP_SHR_UN_IMM:
3383                         g_assert (amd64_is_imm32 (ins->inst_imm));
3384                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3385                         break;
3386                 case OP_LSHR_UN_IMM:
3387                         g_assert (amd64_is_imm32 (ins->inst_imm));
3388                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3389                         break;
3390                 case OP_LSHR_UN:
3391                         g_assert (ins->sreg2 == AMD64_RCX);
3392                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3393                         break;
3394                 case OP_SHL_IMM:
3395                         g_assert (amd64_is_imm32 (ins->inst_imm));
3396                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3397                         break;
3398                 case OP_LSHL_IMM:
3399                         g_assert (amd64_is_imm32 (ins->inst_imm));
3400                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3401                         break;
3402
3403                 case OP_IADDCC:
3404                 case OP_IADD:
3405                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3406                         break;
3407                 case OP_IADC:
3408                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3409                         break;
3410                 case OP_IADD_IMM:
3411                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3412                         break;
3413                 case OP_IADC_IMM:
3414                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3415                         break;
3416                 case OP_ISUBCC:
3417                 case OP_ISUB:
3418                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3419                         break;
3420                 case OP_ISBB:
3421                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3422                         break;
3423                 case OP_ISUB_IMM:
3424                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3425                         break;
3426                 case OP_ISBB_IMM:
3427                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3428                         break;
3429                 case OP_IAND:
3430                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3431                         break;
3432                 case OP_IAND_IMM:
3433                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3434                         break;
3435                 case OP_IOR:
3436                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3437                         break;
3438                 case OP_IOR_IMM:
3439                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3440                         break;
3441                 case OP_IXOR:
3442                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3443                         break;
3444                 case OP_IXOR_IMM:
3445                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3446                         break;
3447                 case OP_INEG:
3448                         amd64_neg_reg_size (code, ins->sreg1, 4);
3449                         break;
3450                 case OP_INOT:
3451                         amd64_not_reg_size (code, ins->sreg1, 4);
3452                         break;
3453                 case OP_ISHL:
3454                         g_assert (ins->sreg2 == AMD64_RCX);
3455                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3456                         break;
3457                 case OP_ISHR:
3458                         g_assert (ins->sreg2 == AMD64_RCX);
3459                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3460                         break;
3461                 case OP_ISHR_IMM:
3462                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3463                         break;
3464                 case OP_ISHR_UN_IMM:
3465                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3466                         break;
3467                 case OP_ISHR_UN:
3468                         g_assert (ins->sreg2 == AMD64_RCX);
3469                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3470                         break;
3471                 case OP_ISHL_IMM:
3472                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3473                         break;
3474                 case OP_IMUL:
3475                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3476                         break;
3477                 case OP_IMUL_OVF:
3478                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3479                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3480                         break;
3481                 case OP_IMUL_OVF_UN:
3482                 case OP_LMUL_OVF_UN: {
3483                         /* the mul operation and the exception check should most likely be split */
3484                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3485                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3486                         /*g_assert (ins->sreg2 == X86_EAX);
3487                         g_assert (ins->dreg == X86_EAX);*/
3488                         if (ins->sreg2 == X86_EAX) {
3489                                 non_eax_reg = ins->sreg1;
3490                         } else if (ins->sreg1 == X86_EAX) {
3491                                 non_eax_reg = ins->sreg2;
3492                         } else {
3493                                 /* no need to save since we're going to store to it anyway */
3494                                 if (ins->dreg != X86_EAX) {
3495                                         saved_eax = TRUE;
3496                                         amd64_push_reg (code, X86_EAX);
3497                                 }
3498                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3499                                 non_eax_reg = ins->sreg2;
3500                         }
3501                         if (ins->dreg == X86_EDX) {
3502                                 if (!saved_eax) {
3503                                         saved_eax = TRUE;
3504                                         amd64_push_reg (code, X86_EAX);
3505                                 }
3506                         } else {
3507                                 saved_edx = TRUE;
3508                                 amd64_push_reg (code, X86_EDX);
3509                         }
3510                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3511                         /* save before the check since pop and mov don't change the flags */
3512                         if (ins->dreg != X86_EAX)
3513                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3514                         if (saved_edx)
3515                                 amd64_pop_reg (code, X86_EDX);
3516                         if (saved_eax)
3517                                 amd64_pop_reg (code, X86_EAX);
3518                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3519                         break;
3520                 }
3521                 case OP_ICOMPARE:
3522                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3523                         break;
3524                 case OP_ICOMPARE_IMM:
3525                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3526                         break;
3527                 case OP_IBEQ:
3528                 case OP_IBLT:
3529                 case OP_IBGT:
3530                 case OP_IBGE:
3531                 case OP_IBLE:
3532                 case OP_LBEQ:
3533                 case OP_LBLT:
3534                 case OP_LBGT:
3535                 case OP_LBGE:
3536                 case OP_LBLE:
3537                 case OP_IBNE_UN:
3538                 case OP_IBLT_UN:
3539                 case OP_IBGT_UN:
3540                 case OP_IBGE_UN:
3541                 case OP_IBLE_UN:
3542                 case OP_LBNE_UN:
3543                 case OP_LBLT_UN:
3544                 case OP_LBGT_UN:
3545                 case OP_LBGE_UN:
3546                 case OP_LBLE_UN:
3547                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3548                         break;
3549
3550                 case OP_CMOV_IEQ:
3551                 case OP_CMOV_IGE:
3552                 case OP_CMOV_IGT:
3553                 case OP_CMOV_ILE:
3554                 case OP_CMOV_ILT:
3555                 case OP_CMOV_INE_UN:
3556                 case OP_CMOV_IGE_UN:
3557                 case OP_CMOV_IGT_UN:
3558                 case OP_CMOV_ILE_UN:
3559                 case OP_CMOV_ILT_UN:
3560                 case OP_CMOV_LEQ:
3561                 case OP_CMOV_LGE:
3562                 case OP_CMOV_LGT:
3563                 case OP_CMOV_LLE:
3564                 case OP_CMOV_LLT:
3565                 case OP_CMOV_LNE_UN:
3566                 case OP_CMOV_LGE_UN:
3567                 case OP_CMOV_LGT_UN:
3568                 case OP_CMOV_LLE_UN:
3569                 case OP_CMOV_LLT_UN:
3570                         g_assert (ins->dreg == ins->sreg1);
3571                         /* This needs to operate on 64 bit values */
3572                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3573                         break;
3574
3575                 case OP_LNOT:
3576                         amd64_not_reg (code, ins->sreg1);
3577                         break;
3578                 case OP_LNEG:
3579                         amd64_neg_reg (code, ins->sreg1);
3580                         break;
3581
3582                 case OP_ICONST:
3583                 case OP_I8CONST:
3584                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3585                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3586                         else
3587                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3588                         break;
3589                 case OP_AOTCONST:
3590                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3591                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3592                         break;
3593                 case OP_JUMP_TABLE:
3594                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3595                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3596                         break;
3597                 case OP_MOVE:
3598                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3599                         break;
3600                 case OP_AMD64_SET_XMMREG_R4: {
3601                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3602                         break;
3603                 }
3604                 case OP_AMD64_SET_XMMREG_R8: {
3605                         if (ins->dreg != ins->sreg1)
3606                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3607                         break;
3608                 }
3609                 case OP_TAILCALL: {
3610                         /*
3611                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3612                          * Keep in sync with the code in emit_epilog.
3613                          */
3614                         int pos = 0, i;
3615
3616                         /* FIXME: no tracing support... */
3617                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3618                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
3619
3620                         g_assert (!cfg->method->save_lmf);
3621
3622                         if (cfg->arch.omit_fp) {
3623                                 guint32 save_offset = 0;
3624                                 /* Pop callee-saved registers */
3625                                 for (i = 0; i < AMD64_NREG; ++i)
3626                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3627                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3628                                                 save_offset += 8;
3629                                         }
3630                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3631                         }
3632                         else {
3633                                 for (i = 0; i < AMD64_NREG; ++i)
3634                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3635                                                 pos -= sizeof (gpointer);
3636
3637                                 if (pos)
3638                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3639
3640                                 /* Pop registers in reverse order */
3641                                 for (i = AMD64_NREG - 1; i > 0; --i)
3642                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3643                                                 amd64_pop_reg (code, i);
3644                                         }
3645
3646                                 amd64_leave (code);
3647                         }
3648
3649                         offset = code - cfg->native_code;
3650                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3651                         if (cfg->compile_aot)
3652                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3653                         else
3654                                 amd64_set_reg_template (code, AMD64_R11);
3655                         amd64_jump_reg (code, AMD64_R11);
3656                         break;
3657                 }
3658                 case OP_CHECK_THIS:
3659                         /* ensure ins->sreg1 is not NULL */
3660                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3661                         break;
3662                 case OP_ARGLIST: {
3663                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3664                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3665                         break;
3666                 }
3667                 case OP_CALL:
3668                 case OP_FCALL:
3669                 case OP_LCALL:
3670                 case OP_VCALL:
3671                 case OP_VCALL2:
3672                 case OP_VOIDCALL:
3673                         call = (MonoCallInst*)ins;
3674                         /*
3675                          * The AMD64 ABI forces callers to know about varargs.
3676                          */
3677                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3678                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3679                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3680                                 /*
3681                                  * Since the unmanaged calling convention doesn't contain a
3682                                  * 'vararg' entry, we have to treat every pinvoke call as a
3683                                  * potential vararg call.
3684                                  */
3685                                 guint32 nregs, i;
3686                                 nregs = 0;
3687                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3688                                         if (call->used_fregs & (1 << i))
3689                                                 nregs ++;
3690                                 if (!nregs)
3691                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3692                                 else
3693                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3694                         }
3695
3696                         if (ins->flags & MONO_INST_HAS_METHOD)
3697                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3698                         else
3699                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3700                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
3701                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3702                         code = emit_move_return_value (cfg, ins, code);
3703                         break;
3704                 case OP_FCALL_REG:
3705                 case OP_LCALL_REG:
3706                 case OP_VCALL_REG:
3707                 case OP_VCALL2_REG:
3708                 case OP_VOIDCALL_REG:
3709                 case OP_CALL_REG:
3710                         call = (MonoCallInst*)ins;
3711
3712                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3713                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3714                                 ins->sreg1 = AMD64_R11;
3715                         }
3716
3717                         /*
3718                          * The AMD64 ABI forces callers to know about varargs.
3719                          */
3720                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3721                                 if (ins->sreg1 == AMD64_RAX) {
3722                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3723                                         ins->sreg1 = AMD64_R11;
3724                                 }
3725                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3726                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3727                                 /*
3728                                  * Since the unmanaged calling convention doesn't contain a
3729                                  * 'vararg' entry, we have to treat every pinvoke call as a
3730                                  * potential vararg call.
3731                                  */
3732                                 guint32 nregs, i;
3733                                 nregs = 0;
3734                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3735                                         if (call->used_fregs & (1 << i))
3736                                                 nregs ++;
3737                                 if (ins->sreg1 == AMD64_RAX) {
3738                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3739                                         ins->sreg1 = AMD64_R11;
3740                                 }
3741                                 if (!nregs)
3742                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3743                                 else
3744                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3745                         }
3746
3747                         amd64_call_reg (code, ins->sreg1);
3748                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
3749                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3750                         code = emit_move_return_value (cfg, ins, code);
3751                         break;
3752                 case OP_FCALL_MEMBASE:
3753                 case OP_LCALL_MEMBASE:
3754                 case OP_VCALL_MEMBASE:
3755                 case OP_VCALL2_MEMBASE:
3756                 case OP_VOIDCALL_MEMBASE:
3757                 case OP_CALL_MEMBASE:
3758                         call = (MonoCallInst*)ins;
3759
3760                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3761                                 /*
3762                                  * Can't use R11 because it is clobbered by the trampoline
3763                                  * code, and the reg value is needed by get_vcall_slot_addr.
3764                                  */
3765                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3766                                 ins->sreg1 = AMD64_RAX;
3767                         }
3768
3769                         /*
3770                          * Emit a few nops to simplify get_vcall_slot ().
3771                          */
3772                         amd64_nop (code);
3773                         amd64_nop (code);
3774                         amd64_nop (code);
3775
3776                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3777                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
3778                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3779                         code = emit_move_return_value (cfg, ins, code);
3780                         break;
3781                 case OP_AMD64_SAVE_SP_TO_LMF:
3782                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3783                         break;
3784                 case OP_X86_PUSH:
3785                         g_assert (!cfg->arch.no_pushes);
3786                         amd64_push_reg (code, ins->sreg1);
3787                         break;
3788                 case OP_X86_PUSH_IMM:
3789                         g_assert (!cfg->arch.no_pushes);
3790                         g_assert (amd64_is_imm32 (ins->inst_imm));
3791                         amd64_push_imm (code, ins->inst_imm);
3792                         break;
3793                 case OP_X86_PUSH_MEMBASE:
3794                         g_assert (!cfg->arch.no_pushes);
3795                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3796                         break;
3797                 case OP_X86_PUSH_OBJ: {
3798                         int size = ALIGN_TO (ins->inst_imm, 8);
3799
3800                         g_assert (!cfg->arch.no_pushes);
3801
3802                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3803                         amd64_push_reg (code, AMD64_RDI);
3804                         amd64_push_reg (code, AMD64_RSI);
3805                         amd64_push_reg (code, AMD64_RCX);
3806                         if (ins->inst_offset)
3807                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3808                         else
3809                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3810                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
3811                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
3812                         amd64_cld (code);
3813                         amd64_prefix (code, X86_REP_PREFIX);
3814                         amd64_movsd (code);
3815                         amd64_pop_reg (code, AMD64_RCX);
3816                         amd64_pop_reg (code, AMD64_RSI);
3817                         amd64_pop_reg (code, AMD64_RDI);
3818                         break;
3819                 }
3820                 case OP_X86_LEA:
3821                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3822                         break;
3823                 case OP_X86_LEA_MEMBASE:
3824                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3825                         break;
3826                 case OP_X86_XCHG:
3827                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3828                         break;
3829                 case OP_LOCALLOC:
3830                         /* keep alignment */
3831                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3832                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3833                         code = mono_emit_stack_alloc (cfg, code, ins);
3834                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3835                         if (cfg->param_area && cfg->arch.no_pushes)
3836                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
3837                         break;
3838                 case OP_LOCALLOC_IMM: {
3839                         guint32 size = ins->inst_imm;
3840                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3841
3842                         if (ins->flags & MONO_INST_INIT) {
3843                                 if (size < 64) {
3844                                         int i;
3845
3846                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3847                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3848
3849                                         for (i = 0; i < size; i += 8)
3850                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3851                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3852                                 } else {
3853                                         amd64_mov_reg_imm (code, ins->dreg, size);
3854                                         ins->sreg1 = ins->dreg;
3855
3856                                         code = mono_emit_stack_alloc (cfg, code, ins);
3857                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3858                                 }
3859                         } else {
3860                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3861                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3862                         }
3863                         if (cfg->param_area && cfg->arch.no_pushes)
3864                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
3865                         break;
3866                 }
3867                 case OP_THROW: {
3868                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3869                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3870                                              (gpointer)"mono_arch_throw_exception", FALSE);
3871                         break;
3872                 }
3873                 case OP_RETHROW: {
3874                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3875                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3876                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
3877                         break;
3878                 }
3879                 case OP_CALL_HANDLER:
3880                         /* Align stack */
3881                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3882                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3883                         amd64_call_imm (code, 0);
3884                         /* Restore stack alignment */
3885                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3886                         break;
3887                 case OP_START_HANDLER: {
3888                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3889                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3890
3891                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
3892                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
3893                                 cfg->param_area && cfg->arch.no_pushes) {
3894                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
3895                         }
3896                         break;
3897                 }
3898                 case OP_ENDFINALLY: {
3899                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3900                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3901                         amd64_ret (code);
3902                         break;
3903                 }
3904                 case OP_ENDFILTER: {
3905                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3906                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3907                         /* The local allocator will put the result into RAX */
3908                         amd64_ret (code);
3909                         break;
3910                 }
3911
3912                 case OP_LABEL:
3913                         ins->inst_c0 = code - cfg->native_code;
3914                         break;
3915                 case OP_BR:
3916                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3917                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3918                         //break;
3919                                 if (ins->inst_target_bb->native_offset) {
3920                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3921                                 } else {
3922                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3923                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3924                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
3925                                                 x86_jump8 (code, 0);
3926                                         else
3927                                                 x86_jump32 (code, 0);
3928                         }
3929                         break;
3930                 case OP_BR_REG:
3931                         amd64_jump_reg (code, ins->sreg1);
3932                         break;
3933                 case OP_CEQ:
3934                 case OP_LCEQ:
3935                 case OP_ICEQ:
3936                 case OP_CLT:
3937                 case OP_LCLT:
3938                 case OP_ICLT:
3939                 case OP_CGT:
3940                 case OP_ICGT:
3941                 case OP_LCGT:
3942                 case OP_CLT_UN:
3943                 case OP_LCLT_UN:
3944                 case OP_ICLT_UN:
3945                 case OP_CGT_UN:
3946                 case OP_LCGT_UN:
3947                 case OP_ICGT_UN:
3948                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3949                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3950                         break;
3951                 case OP_COND_EXC_EQ:
3952                 case OP_COND_EXC_NE_UN:
3953                 case OP_COND_EXC_LT:
3954                 case OP_COND_EXC_LT_UN:
3955                 case OP_COND_EXC_GT:
3956                 case OP_COND_EXC_GT_UN:
3957                 case OP_COND_EXC_GE:
3958                 case OP_COND_EXC_GE_UN:
3959                 case OP_COND_EXC_LE:
3960                 case OP_COND_EXC_LE_UN:
3961                 case OP_COND_EXC_IEQ:
3962                 case OP_COND_EXC_INE_UN:
3963                 case OP_COND_EXC_ILT:
3964                 case OP_COND_EXC_ILT_UN:
3965                 case OP_COND_EXC_IGT:
3966                 case OP_COND_EXC_IGT_UN:
3967                 case OP_COND_EXC_IGE:
3968                 case OP_COND_EXC_IGE_UN:
3969                 case OP_COND_EXC_ILE:
3970                 case OP_COND_EXC_ILE_UN:
3971                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3972                         break;
3973                 case OP_COND_EXC_OV:
3974                 case OP_COND_EXC_NO:
3975                 case OP_COND_EXC_C:
3976                 case OP_COND_EXC_NC:
3977                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3978                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3979                         break;
3980                 case OP_COND_EXC_IOV:
3981                 case OP_COND_EXC_INO:
3982                 case OP_COND_EXC_IC:
3983                 case OP_COND_EXC_INC:
3984                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3985                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3986                         break;
3987
3988                 /* floating point opcodes */
3989                 case OP_R8CONST: {
3990                         double d = *(double *)ins->inst_p0;
3991
3992                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3993                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3994                         }
3995                         else {
3996                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3997                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3998                         }
3999                         break;
4000                 }
4001                 case OP_R4CONST: {
4002                         float f = *(float *)ins->inst_p0;
4003
4004                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4005                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4006                         }
4007                         else {
4008                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4009                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4010                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4011                         }
4012                         break;
4013                 }
4014                 case OP_STORER8_MEMBASE_REG:
4015                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4016                         break;
4017                 case OP_LOADR8_SPILL_MEMBASE:
4018                         g_assert_not_reached ();
4019                         break;
4020                 case OP_LOADR8_MEMBASE:
4021                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4022                         break;
4023                 case OP_STORER4_MEMBASE_REG:
4024                         /* This requires a double->single conversion */
4025                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4026                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4027                         break;
4028                 case OP_LOADR4_MEMBASE:
4029                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4030                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4031                         break;
4032                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4033                 case OP_ICONV_TO_R8:
4034                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4035                         break;
4036                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4037                 case OP_LCONV_TO_R8:
4038                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4039                         break;
4040                 case OP_FCONV_TO_R4:
4041                         /* FIXME: nothing to do ?? */
4042                         break;
4043                 case OP_FCONV_TO_I1:
4044                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4045                         break;
4046                 case OP_FCONV_TO_U1:
4047                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4048                         break;
4049                 case OP_FCONV_TO_I2:
4050                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4051                         break;
4052                 case OP_FCONV_TO_U2:
4053                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4054                         break;
4055                 case OP_FCONV_TO_U4:
4056                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4057                         break;
4058                 case OP_FCONV_TO_I4:
4059                 case OP_FCONV_TO_I:
4060                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4061                         break;
4062                 case OP_FCONV_TO_I8:
4063                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4064                         break;
4065                 case OP_LCONV_TO_R_UN: {
4066                         guint8 *br [2];
4067
4068                         /* Based on gcc code */
4069                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4070                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4071
4072                         /* Positive case */
4073                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4074                         br [1] = code; x86_jump8 (code, 0);
4075                         amd64_patch (br [0], code);
4076
4077                         /* Negative case */
4078                         /* Save to the red zone */
4079                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4080                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4081                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4082                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4083                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4084                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4085                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4086                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4087                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4088                         /* Restore */
4089                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4090                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4091                         amd64_patch (br [1], code);
4092                         break;
4093                 }
4094                 case OP_LCONV_TO_OVF_U4:
4095                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4096                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4097                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4098                         break;
4099                 case OP_LCONV_TO_OVF_I4_UN:
4100                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4101                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4102                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4103                         break;
4104                 case OP_FMOVE:
4105                         if (ins->dreg != ins->sreg1)
4106                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4107                         break;
4108                 case OP_FADD:
4109                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4110                         break;
4111                 case OP_FSUB:
4112                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4113                         break;
4114                 case OP_FMUL:
4115                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4116                         break;
4117                 case OP_FDIV:
4118                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4119                         break;
4120                 case OP_FNEG: {
4121                         static double r8_0 = -0.0;
4122
4123                         g_assert (ins->sreg1 == ins->dreg);
4124
4125                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4126                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4127                         break;
4128                 }
4129                 case OP_SIN:
4130                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4131                         break;
4132                 case OP_COS:
4133                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4134                         break;
4135                 case OP_ABS: {
4136                         static guint64 d = 0x7fffffffffffffffUL;
4137
4138                         g_assert (ins->sreg1 == ins->dreg);
4139
4140                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4141                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4142                         break;
4143                 }
4144                 case OP_SQRT:
4145                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4146                         break;
4147                 case OP_IMIN:
4148                         g_assert (cfg->opt & MONO_OPT_CMOV);
4149                         g_assert (ins->dreg == ins->sreg1);
4150                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4151                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4152                         break;
4153                 case OP_IMIN_UN:
4154                         g_assert (cfg->opt & MONO_OPT_CMOV);
4155                         g_assert (ins->dreg == ins->sreg1);
4156                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4157                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4158                         break;
4159                 case OP_IMAX:
4160                         g_assert (cfg->opt & MONO_OPT_CMOV);
4161                         g_assert (ins->dreg == ins->sreg1);
4162                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4163                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4164                         break;
4165                 case OP_IMAX_UN:
4166                         g_assert (cfg->opt & MONO_OPT_CMOV);
4167                         g_assert (ins->dreg == ins->sreg1);
4168                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4169                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4170                         break;
4171                 case OP_LMIN:
4172                         g_assert (cfg->opt & MONO_OPT_CMOV);
4173                         g_assert (ins->dreg == ins->sreg1);
4174                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4175                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4176                         break;
4177                 case OP_LMIN_UN:
4178                         g_assert (cfg->opt & MONO_OPT_CMOV);
4179                         g_assert (ins->dreg == ins->sreg1);
4180                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4181                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4182                         break;
4183                 case OP_LMAX:
4184                         g_assert (cfg->opt & MONO_OPT_CMOV);
4185                         g_assert (ins->dreg == ins->sreg1);
4186                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4187                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4188                         break;
4189                 case OP_LMAX_UN:
4190                         g_assert (cfg->opt & MONO_OPT_CMOV);
4191                         g_assert (ins->dreg == ins->sreg1);
4192                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4193                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4194                         break;
4195                 case OP_X86_FPOP:
4196                         break;
4197                 case OP_FCOMPARE:
4198                         /*
4199                          * The two arguments are swapped because the fbranch instructions
4200                          * depend on this for the non-sse case to work.
4201                          */
4202                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4203                         break;
4204                 case OP_FCEQ: {
4205                         /* zeroing the register at the start results in
4206                          * shorter and faster code (we can also remove the widening op)
4207                          */
4208                         guchar *unordered_check;
4209                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4210                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4211                         unordered_check = code;
4212                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4213                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4214                         amd64_patch (unordered_check, code);
4215                         break;
4216                 }
4217                 case OP_FCLT:
4218                 case OP_FCLT_UN:
4219                         /* zeroing the register at the start results in
4220                          * shorter and faster code (we can also remove the widening op)
4221                          */
4222                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4223                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4224                         if (ins->opcode == OP_FCLT_UN) {
4225                                 guchar *unordered_check = code;
4226                                 guchar *jump_to_end;
4227                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4228                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4229                                 jump_to_end = code;
4230                                 x86_jump8 (code, 0);
4231                                 amd64_patch (unordered_check, code);
4232                                 amd64_inc_reg (code, ins->dreg);
4233                                 amd64_patch (jump_to_end, code);
4234                         } else {
4235                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4236                         }
4237                         break;
4238                 case OP_FCGT:
4239                 case OP_FCGT_UN: {
4240                         /* zeroing the register at the start results in
4241                          * shorter and faster code (we can also remove the widening op)
4242                          */
4243                         guchar *unordered_check;
4244                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4245                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4246                         if (ins->opcode == OP_FCGT) {
4247                                 unordered_check = code;
4248                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4249                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4250                                 amd64_patch (unordered_check, code);
4251                         } else {
4252                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4253                         }
4254                         break;
4255                 }
4256                 case OP_FCLT_MEMBASE:
4257                 case OP_FCGT_MEMBASE:
4258                 case OP_FCLT_UN_MEMBASE:
4259                 case OP_FCGT_UN_MEMBASE:
4260                 case OP_FCEQ_MEMBASE: {
4261                         guchar *unordered_check, *jump_to_end;
4262                         int x86_cond;
4263
4264                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4265                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4266
4267                         switch (ins->opcode) {
4268                         case OP_FCEQ_MEMBASE:
4269                                 x86_cond = X86_CC_EQ;
4270                                 break;
4271                         case OP_FCLT_MEMBASE:
4272                         case OP_FCLT_UN_MEMBASE:
4273                                 x86_cond = X86_CC_LT;
4274                                 break;
4275                         case OP_FCGT_MEMBASE:
4276                         case OP_FCGT_UN_MEMBASE:
4277                                 x86_cond = X86_CC_GT;
4278                                 break;
4279                         default:
4280                                 g_assert_not_reached ();
4281                         }
4282
4283                         unordered_check = code;
4284                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4285                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4286
4287                         switch (ins->opcode) {
4288                         case OP_FCEQ_MEMBASE:
4289                         case OP_FCLT_MEMBASE:
4290                         case OP_FCGT_MEMBASE:
4291                                 amd64_patch (unordered_check, code);
4292                                 break;
4293                         case OP_FCLT_UN_MEMBASE:
4294                         case OP_FCGT_UN_MEMBASE:
4295                                 jump_to_end = code;
4296                                 x86_jump8 (code, 0);
4297                                 amd64_patch (unordered_check, code);
4298                                 amd64_inc_reg (code, ins->dreg);
4299                                 amd64_patch (jump_to_end, code);
4300                                 break;
4301                         default:
4302                                 break;
4303                         }
4304                         break;
4305                 }
4306                 case OP_FBEQ: {
4307                         guchar *jump = code;
4308                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4309                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4310                         amd64_patch (jump, code);
4311                         break;
4312                 }
4313                 case OP_FBNE_UN:
4314                         /* Branch if C013 != 100 */
4315                         /* branch if !ZF or (PF|CF) */
4316                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4317                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4318                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4319                         break;
4320                 case OP_FBLT:
4321                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4322                         break;
4323                 case OP_FBLT_UN:
4324                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4325                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4326                         break;
4327                 case OP_FBGT:
4328                 case OP_FBGT_UN:
4329                         if (ins->opcode == OP_FBGT) {
4330                                 guchar *br1;
4331
4332                                 /* skip branch if C1=1 */
4333                                 br1 = code;
4334                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4335                                 /* branch if (C0 | C3) = 1 */
4336                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4337                                 amd64_patch (br1, code);
4338                                 break;
4339                         } else {
4340                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4341                         }
4342                         break;
4343                 case OP_FBGE: {
4344                         /* Branch if C013 == 100 or 001 */
4345                         guchar *br1;
4346
4347                         /* skip branch if C1=1 */
4348                         br1 = code;
4349                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4350                         /* branch if (C0 | C3) = 1 */
4351                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4352                         amd64_patch (br1, code);
4353                         break;
4354                 }
4355                 case OP_FBGE_UN:
4356                         /* Branch if C013 == 000 */
4357                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4358                         break;
4359                 case OP_FBLE: {
4360                         /* Branch if C013=000 or 100 */
4361                         guchar *br1;
4362
4363                         /* skip branch if C1=1 */
4364                         br1 = code;
4365                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4366                         /* branch if C0=0 */
4367                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4368                         amd64_patch (br1, code);
4369                         break;
4370                 }
4371                 case OP_FBLE_UN:
4372                         /* Branch if C013 != 001 */
4373                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4374                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4375                         break;
4376                 case OP_CKFINITE:
4377                         /* Transfer value to the fp stack */
4378                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4379                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4380                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4381
4382                         amd64_push_reg (code, AMD64_RAX);
4383                         amd64_fxam (code);
4384                         amd64_fnstsw (code);
4385                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4386                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4387                         amd64_pop_reg (code, AMD64_RAX);
4388                         amd64_fstp (code, 0);
4389                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4390                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4391                         break;
4392                 case OP_TLS_GET: {
4393                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4394                         break;
4395                 }
4396                 case OP_MEMORY_BARRIER: {
4397                         /* Not needed on amd64 */
4398                         break;
4399                 }
4400                 case OP_ATOMIC_ADD_I4:
4401                 case OP_ATOMIC_ADD_I8: {
4402                         int dreg = ins->dreg;
4403                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4404
4405                         if (dreg == ins->inst_basereg)
4406                                 dreg = AMD64_R11;
4407
4408                         if (dreg != ins->sreg2)
4409                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4410
4411                         x86_prefix (code, X86_LOCK_PREFIX);
4412                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4413
4414                         if (dreg != ins->dreg)
4415                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4416
4417                         break;
4418                 }
4419                 case OP_ATOMIC_ADD_NEW_I4:
4420                 case OP_ATOMIC_ADD_NEW_I8: {
4421                         int dreg = ins->dreg;
4422                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4423
4424                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4425                                 dreg = AMD64_R11;
4426
4427                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4428                         amd64_prefix (code, X86_LOCK_PREFIX);
4429                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4430                         /* dreg contains the old value, add with sreg2 value */
4431                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4432
4433                         if (ins->dreg != dreg)
4434                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4435
4436                         break;
4437                 }
4438                 case OP_ATOMIC_EXCHANGE_I4:
4439                 case OP_ATOMIC_EXCHANGE_I8: {
4440                         guchar *br[2];
4441                         int sreg2 = ins->sreg2;
4442                         int breg = ins->inst_basereg;
4443                         guint32 size;
4444                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4445
4446                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4447                                 size = 8;
4448                         else
4449                                 size = 4;
4450
4451                         /*
4452                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4453                          * an explanation of how this works.
4454                          */
4455
4456                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4457                          * hack to overcome limits in x86 reg allocator
4458                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4459                          */
4460                         g_assert (ins->dreg == AMD64_RAX);
4461
4462                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4463                                 /* Highly unlikely, but possible */
4464                                 need_push = TRUE;
4465
4466                         /* The pushes invalidate rsp */
4467                         if ((breg == AMD64_RAX) || need_push) {
4468                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4469                                 breg = AMD64_R11;
4470                         }
4471
4472                         /* We need the EAX reg for the comparand */
4473                         if (ins->sreg2 == AMD64_RAX) {
4474                                 if (breg != AMD64_R11) {
4475                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4476                                         sreg2 = AMD64_R11;
4477                                 } else {
4478                                         g_assert (need_push);
4479                                         amd64_push_reg (code, AMD64_RDX);
4480                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4481                                         sreg2 = AMD64_RDX;
4482                                         rdx_pushed = TRUE;
4483                                 }
4484                         }
4485
4486                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4487
4488                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4489                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4490                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4491                         amd64_patch (br [1], br [0]);
4492
4493                         if (rdx_pushed)
4494                                 amd64_pop_reg (code, AMD64_RDX);
4495
4496                         break;
4497                 }
4498                 case OP_ATOMIC_CAS_I4:
4499                 case OP_ATOMIC_CAS_I8: {
4500                         guint32 size;
4501
4502                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4503                                 size = 8;
4504                         else
4505                                 size = 4;
4506
4507                         /*
4508                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4509                          * an explanation of how this works.
4510                          */
4511                         g_assert (ins->sreg3 == AMD64_RAX);
4512                         g_assert (ins->sreg1 != AMD64_RAX);
4513                         g_assert (ins->sreg1 != ins->sreg2);
4514
4515                         amd64_prefix (code, X86_LOCK_PREFIX);
4516                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4517
4518                         if (ins->dreg != AMD64_RAX)
4519                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4520                         break;
4521                 }
4522 #ifdef MONO_ARCH_SIMD_INTRINSICS
4523                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4524                 case OP_ADDPS:
4525                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4526                         break;
4527                 case OP_DIVPS:
4528                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4529                         break;
4530                 case OP_MULPS:
4531                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4532                         break;
4533                 case OP_SUBPS:
4534                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4535                         break;
4536                 case OP_MAXPS:
4537                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4538                         break;
4539                 case OP_MINPS:
4540                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4541                         break;
4542                 case OP_COMPPS:
4543                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4544                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4545                         break;
4546                 case OP_ANDPS:
4547                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4548                         break;
4549                 case OP_ANDNPS:
4550                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4551                         break;
4552                 case OP_ORPS:
4553                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4554                         break;
4555                 case OP_XORPS:
4556                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
4557                         break;
4558                 case OP_SQRTPS:
4559                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4560                         break;
4561                 case OP_RSQRTPS:
4562                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4563                         break;
4564                 case OP_RCPPS:
4565                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
4566                         break;
4567                 case OP_ADDSUBPS:
4568                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4569                         break;
4570                 case OP_HADDPS:
4571                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
4572                         break;
4573                 case OP_HSUBPS:
4574                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4575                         break;
4576                 case OP_DUPPS_HIGH:
4577                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
4578                         break;
4579                 case OP_DUPPS_LOW:
4580                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
4581                         break;
4582
4583                 case OP_PSHUFLEW_HIGH:
4584                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4585                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4586                         break;
4587                 case OP_PSHUFLEW_LOW:
4588                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4589                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4590                         break;
4591                 case OP_PSHUFLED:
4592                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4593                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4594                         break;
4595
4596                 case OP_ADDPD:
4597                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
4598                         break;
4599                 case OP_DIVPD:
4600                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
4601                         break;
4602                 case OP_MULPD:
4603                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
4604                         break;
4605                 case OP_SUBPD:
4606                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
4607                         break;
4608                 case OP_MAXPD:
4609                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
4610                         break;
4611                 case OP_MINPD:
4612                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
4613                         break;
4614                 case OP_COMPPD:
4615                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4616                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4617                         break;
4618                 case OP_ANDPD:
4619                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
4620                         break;
4621                 case OP_ANDNPD:
4622                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
4623                         break;
4624                 case OP_ORPD:
4625                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
4626                         break;
4627                 case OP_XORPD:
4628                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
4629                         break;
4630                 /* TODO: This op is in the AMD64 manual but has not been implemented.
4631                 case OP_SQRTPD:
4632                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
4633                         break;
4634                 */
4635                 case OP_ADDSUBPD:
4636                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
4637                         break;
4638                 case OP_HADDPD:
4639                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
4640                         break;
4641                 case OP_HSUBPD:
4642                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
4643                         break;
4644                 case OP_DUPPD:
4645                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
4646                         break;
4647
4648                 case OP_EXTRACT_MASK:
4649                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
4650                         break;
4651
4652                 case OP_PAND:
4653                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
4654                         break;
4655                 case OP_POR:
4656                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
4657                         break;
4658                 case OP_PXOR:
4659                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
4660                         break;
4661
4662                 case OP_PADDB:
4663                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
4664                         break;
4665                 case OP_PADDW:
4666                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
4667                         break;
4668                 case OP_PADDD:
4669                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
4670                         break;
4671                 case OP_PADDQ:
4672                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
4673                         break;
4674
4675                 case OP_PSUBB:
4676                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
4677                         break;
4678                 case OP_PSUBW:
4679                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
4680                         break;
4681                 case OP_PSUBD:
4682                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
4683                         break;
4684                 case OP_PSUBQ:
4685                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
4686                         break;
4687
4688                 case OP_PMAXB_UN:
4689                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
4690                         break;
4691                 case OP_PMAXW_UN:
4692                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
4693                         break;
4694                 case OP_PMAXD_UN:
4695                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
4696                         break;
4697
4698                 case OP_PMAXB:
4699                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
4700                         break;
4701                 case OP_PMAXW:
4702                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
4703                         break;
4704                 case OP_PMAXD:
4705                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
4706                         break;
4707
4708                 case OP_PAVGB_UN:
4709                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
4710                         break;
4711                 case OP_PAVGW_UN:
4712                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
4713                         break;
4714
4715                 case OP_PMINB_UN:
4716                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
4717                         break;
4718                 case OP_PMINW_UN:
4719                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
4720                         break;
4721                 case OP_PMIND_UN:
4722                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
4723                         break;
4724
4725                 case OP_PMINB:
4726                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
4727                         break;
4728                 case OP_PMINW:
4729                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
4730                         break;
4731                 case OP_PMIND:
4732                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
4733                         break;
4734
4735                 case OP_PCMPEQB:
4736                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
4737                         break;
4738                 case OP_PCMPEQW:
4739                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
4740                         break;
4741                 case OP_PCMPEQD:
4742                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
4743                         break;
4744                 case OP_PCMPEQQ:
4745                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
4746                         break;
4747
4748                 case OP_PCMPGTB:
4749                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
4750                         break;
4751                 case OP_PCMPGTW:
4752                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
4753                         break;
4754                 case OP_PCMPGTD:
4755                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
4756                         break;
4757                 case OP_PCMPGTQ:
4758                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
4759                         break;
4760
4761                 case OP_PSUM_ABS_DIFF:
4762                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
4763                         break;
4764
4765                 case OP_UNPACK_LOWB:
4766                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
4767                         break;
4768                 case OP_UNPACK_LOWW:
4769                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
4770                         break;
4771                 case OP_UNPACK_LOWD:
4772                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
4773                         break;
4774                 case OP_UNPACK_LOWQ:
4775                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
4776                         break;
4777                 case OP_UNPACK_LOWPS:
4778                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
4779                         break;
4780                 case OP_UNPACK_LOWPD:
4781                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
4782                         break;
4783
4784                 case OP_UNPACK_HIGHB:
4785                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
4786                         break;
4787                 case OP_UNPACK_HIGHW:
4788                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
4789                         break;
4790                 case OP_UNPACK_HIGHD:
4791                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
4792                         break;
4793                 case OP_UNPACK_HIGHQ:
4794                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
4795                         break;
4796                 case OP_UNPACK_HIGHPS:
4797                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
4798                         break;
4799                 case OP_UNPACK_HIGHPD:
4800                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
4801                         break;
4802
4803                 case OP_PACKW:
4804                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
4805                         break;
4806                 case OP_PACKD:
4807                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
4808                         break;
4809                 case OP_PACKW_UN:
4810                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
4811                         break;
4812                 case OP_PACKD_UN:
4813                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
4814                         break;
4815
4816                 case OP_PADDB_SAT_UN:
4817                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
4818                         break;
4819                 case OP_PSUBB_SAT_UN:
4820                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
4821                         break;
4822                 case OP_PADDW_SAT_UN:
4823                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
4824                         break;
4825                 case OP_PSUBW_SAT_UN:
4826                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
4827                         break;
4828
4829                 case OP_PADDB_SAT:
4830                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
4831                         break;
4832                 case OP_PSUBB_SAT:
4833                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
4834                         break;
4835                 case OP_PADDW_SAT:
4836                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
4837                         break;
4838                 case OP_PSUBW_SAT:
4839                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
4840                         break;
4841
4842                 case OP_PMULW:
4843                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
4844                         break;
4845                 case OP_PMULD:
4846                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
4847                         break;
4848                 case OP_PMULQ:
4849                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
4850                         break;
4851                 case OP_PMULW_HIGH_UN:
4852                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
4853                         break;
4854                 case OP_PMULW_HIGH:
4855                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
4856                         break;
4857
4858                 case OP_PSHRW:
4859                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
4860                         break;
4861                 case OP_PSHRW_REG:
4862                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
4863                         break;
4864
4865                 case OP_PSARW:
4866                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
4867                         break;
4868                 case OP_PSARW_REG:
4869                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
4870                         break;
4871
4872                 case OP_PSHLW:
4873                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
4874                         break;
4875                 case OP_PSHLW_REG:
4876                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
4877                         break;
4878
4879                 case OP_PSHRD:
4880                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
4881                         break;
4882                 case OP_PSHRD_REG:
4883                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
4884                         break;
4885
4886                 case OP_PSARD:
4887                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
4888                         break;
4889                 case OP_PSARD_REG:
4890                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
4891                         break;
4892
4893                 case OP_PSHLD:
4894                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
4895                         break;
4896                 case OP_PSHLD_REG:
4897                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
4898                         break;
4899
4900                 case OP_PSHRQ:
4901                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
4902                         break;
4903                 case OP_PSHRQ_REG:
4904                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
4905                         break;
4906
4907                 /*TODO: This is appart of the sse spec but not added
4908                 case OP_PSARQ:
4909                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
4910                         break;
4911                 case OP_PSARQ_REG:
4912                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
4913                         break;
4914                 */
4915
4916                 case OP_PSHLQ:
4917                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
4918                         break;
4919                 case OP_PSHLQ_REG:
4920                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
4921                         break;
4922
4923                 case OP_ICONV_TO_X:
4924                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
4925                         break;
4926                 case OP_EXTRACT_I4:
4927                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
4928                         break;
4929                 case OP_EXTRACT_I8:
4930                         if (ins->inst_c0) {
4931                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
4932                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
4933                         } else {
4934                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
4935                         }
4936                         break;
4937                 case OP_EXTRACT_I1:
4938                 case OP_EXTRACT_U1:
4939                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
4940                         if (ins->inst_c0)
4941                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
4942                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
4943                         break;
4944                 case OP_EXTRACT_I2:
4945                 case OP_EXTRACT_U2:
4946                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
4947                         if (ins->inst_c0)
4948                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
4949                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4950                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
4951                         break;
4952                 case OP_EXTRACT_R8:
4953                         if (ins->inst_c0)
4954                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
4955                         else
4956                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4957                         break;
4958                 case OP_INSERT_I2:
4959                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4960                         break;
4961                 case OP_EXTRACTX_U2:
4962                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4963                         break;
4964                 case OP_INSERTX_U1_SLOW:
4965                         /*sreg1 is the extracted ireg (scratch)
4966                         /sreg2 is the to be inserted ireg (scratch)
4967                         /dreg is the xreg to receive the value*/
4968
4969                         /*clear the bits from the extracted word*/
4970                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
4971                         /*shift the value to insert if needed*/
4972                         if (ins->inst_c0 & 1)
4973                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
4974                         /*join them together*/
4975                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4976                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
4977                         break;
4978                 case OP_INSERTX_I4_SLOW:
4979                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
4980                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
4981                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
4982                         break;
4983                 case OP_INSERTX_I8_SLOW:
4984                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
4985                         if (ins->inst_c0)
4986                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
4987                         else
4988                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
4989                         break;
4990
4991                 case OP_INSERTX_R4_SLOW:
4992                         switch (ins->inst_c0) {
4993                         case 0:
4994                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
4995                                 break;
4996                         case 1:
4997                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
4998                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
4999                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5000                                 break;
5001                         case 2:
5002                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5003                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5004                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5005                                 break;
5006                         case 3:
5007                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5008                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5009                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5010                                 break;
5011                         }
5012                         break;
5013                 case OP_INSERTX_R8_SLOW:
5014                         if (ins->inst_c0)
5015                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5016                         else
5017                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5018                         break;
5019                 case OP_STOREX_MEMBASE_REG:
5020                 case OP_STOREX_MEMBASE:
5021                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5022                         break;
5023                 case OP_LOADX_MEMBASE:
5024                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5025                         break;
5026                 case OP_LOADX_ALIGNED_MEMBASE:
5027                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5028                         break;
5029                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5030                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5031                         break;
5032                 case OP_STOREX_NTA_MEMBASE_REG:
5033                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5034                         break;
5035                 case OP_PREFETCH_MEMBASE:
5036                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5037                         break;
5038
5039                 case OP_XMOVE:
5040                         /*FIXME the peephole pass should have killed this*/
5041                         if (ins->dreg != ins->sreg1)
5042                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5043                         break;
5044                 case OP_XZERO:
5045                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5046                         break;
5047                 case OP_ICONV_TO_R8_RAW:
5048                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5049                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5050                         break;
5051
5052                 case OP_FCONV_TO_R8_X:
5053                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5054                         break;
5055
5056                 case OP_XCONV_R8_TO_I4:
5057                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5058                         switch (ins->backend.source_opcode) {
5059                         case OP_FCONV_TO_I1:
5060                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5061                                 break;
5062                         case OP_FCONV_TO_U1:
5063                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5064                                 break;
5065                         case OP_FCONV_TO_I2:
5066                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5067                                 break;
5068                         case OP_FCONV_TO_U2:
5069                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5070                                 break;
5071                         }
5072                         break;
5073
5074                 case OP_EXPAND_I2:
5075                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5076                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5077                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5078                         break;
5079                 case OP_EXPAND_I4:
5080                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5081                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5082                         break;
5083                 case OP_EXPAND_I8:
5084                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5085                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5086                         break;
5087                 case OP_EXPAND_R4:
5088                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5089                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5090                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5091                         break;
5092                 case OP_EXPAND_R8:
5093                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5094                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5095                         break;
5096 #endif
5097                 case OP_LIVERANGE_START: {
5098                         if (cfg->verbose_level > 1)
5099                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5100                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5101                         break;
5102                 }
5103                 case OP_LIVERANGE_END: {
5104                         if (cfg->verbose_level > 1)
5105                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5106                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5107                         break;
5108                 }
5109                 default:
5110                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5111                         g_assert_not_reached ();
5112                 }
5113
5114                 if ((code - cfg->native_code - offset) > max_len) {
5115                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5116                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5117                         g_assert_not_reached ();
5118                 }
5119
5120                 last_ins = ins;
5121                 last_offset = offset;
5122         }
5123
5124         cfg->code_len = code - cfg->native_code;
5125 }
5126
5127 #endif /* DISABLE_JIT */
5128
5129 void
5130 mono_arch_register_lowlevel_calls (void)
5131 {
5132         /* The signature doesn't matter */
5133         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5134 }
5135
5136 void
5137 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5138 {
5139         MonoJumpInfo *patch_info;
5140         gboolean compile_aot = !run_cctors;
5141
5142         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5143                 unsigned char *ip = patch_info->ip.i + code;
5144                 unsigned char *target;
5145
5146                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5147
5148                 if (compile_aot) {
5149                         switch (patch_info->type) {
5150                         case MONO_PATCH_INFO_BB:
5151                         case MONO_PATCH_INFO_LABEL:
5152                                 break;
5153                         default:
5154                                 /* No need to patch these */
5155                                 continue;
5156                         }
5157                 }
5158
5159                 switch (patch_info->type) {
5160                 case MONO_PATCH_INFO_NONE:
5161                         continue;
5162                 case MONO_PATCH_INFO_METHOD_REL:
5163                 case MONO_PATCH_INFO_R8:
5164                 case MONO_PATCH_INFO_R4:
5165                         g_assert_not_reached ();
5166                         continue;
5167                 case MONO_PATCH_INFO_BB:
5168                         break;
5169                 default:
5170                         break;
5171                 }
5172
5173                 /*
5174                  * Debug code to help track down problems where the target of a near call is
5175                  * is not valid.
5176                  */
5177                 if (amd64_is_near_call (ip)) {
5178                         gint64 disp = (guint8*)target - (guint8*)ip;
5179
5180                         if (!amd64_is_imm32 (disp)) {
5181                                 printf ("TYPE: %d\n", patch_info->type);
5182                                 switch (patch_info->type) {
5183                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5184                                         printf ("V: %s\n", patch_info->data.name);
5185                                         break;
5186                                 case MONO_PATCH_INFO_METHOD_JUMP:
5187                                 case MONO_PATCH_INFO_METHOD:
5188                                         printf ("V: %s\n", patch_info->data.method->name);
5189                                         break;
5190                                 default:
5191                                         break;
5192                                 }
5193                         }
5194                 }
5195
5196                 amd64_patch (ip, (gpointer)target);
5197         }
5198 }
5199
5200 static int
5201 get_max_epilog_size (MonoCompile *cfg)
5202 {
5203         int max_epilog_size = 16;
5204
5205         if (cfg->method->save_lmf)
5206                 max_epilog_size += 256;
5207
5208         if (mono_jit_trace_calls != NULL)
5209                 max_epilog_size += 50;
5210
5211         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5212                 max_epilog_size += 50;
5213
5214         max_epilog_size += (AMD64_NREG * 2);
5215
5216         return max_epilog_size;
5217 }
5218
5219 /*
5220  * This macro is used for testing whenever the unwinder works correctly at every point
5221  * where an async exception can happen.
5222  */
5223 /* This will generate a SIGSEGV at the given point in the code */
5224 #define async_exc_point(code) do { \
5225     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5226          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5227              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5228          cfg->arch.async_point_count ++; \
5229     } \
5230 } while (0)
5231
5232 guint8 *
5233 mono_arch_emit_prolog (MonoCompile *cfg)
5234 {
5235         MonoMethod *method = cfg->method;
5236         MonoBasicBlock *bb;
5237         MonoMethodSignature *sig;
5238         MonoInst *ins;
5239         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5240         guint8 *code;
5241         CallInfo *cinfo;
5242         gint32 lmf_offset = cfg->arch.lmf_offset;
5243         gboolean args_clobbered = FALSE;
5244         gboolean trace = FALSE;
5245
5246         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
5247
5248         code = cfg->native_code = g_malloc (cfg->code_size);
5249
5250         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5251                 trace = TRUE;
5252
5253         /* Amount of stack space allocated by register saving code */
5254         pos = 0;
5255
5256         /* Offset between RSP and the CFA */
5257         cfa_offset = 0;
5258
5259         /*
5260          * The prolog consists of the following parts:
5261          * FP present:
5262          * - push rbp, mov rbp, rsp
5263          * - save callee saved regs using pushes
5264          * - allocate frame
5265          * - save rgctx if needed
5266          * - save lmf if needed
5267          * FP not present:
5268          * - allocate frame
5269          * - save rgctx if needed
5270          * - save lmf if needed
5271          * - save callee saved regs using moves
5272          */
5273
5274         // CFA = sp + 8
5275         cfa_offset = 8;
5276         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5277         // IP saved at CFA - 8
5278         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5279         async_exc_point (code);
5280
5281         if (!cfg->arch.omit_fp) {
5282                 amd64_push_reg (code, AMD64_RBP);
5283                 cfa_offset += 8;
5284                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5285                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5286                 async_exc_point (code);
5287 #ifdef PLATFORM_WIN32
5288                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5289 #endif
5290
5291                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5292                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5293                 async_exc_point (code);
5294 #ifdef PLATFORM_WIN32
5295                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5296 #endif
5297         }
5298
5299         /* Save callee saved registers */
5300         if (!cfg->arch.omit_fp && !method->save_lmf) {
5301                 int offset = cfa_offset;
5302
5303                 for (i = 0; i < AMD64_NREG; ++i)
5304                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5305                                 amd64_push_reg (code, i);
5306                                 pos += sizeof (gpointer);
5307                                 offset += 8;
5308                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5309                                 async_exc_point (code);
5310                         }
5311         }
5312
5313         /* The param area is always at offset 0 from sp */
5314         /* This needs to be allocated here, since it has to come after the spill area */
5315         if (cfg->arch.no_pushes && cfg->param_area) {
5316                 if (cfg->arch.omit_fp)
5317                         // FIXME:
5318                         g_assert_not_reached ();
5319                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5320         }
5321
5322         if (cfg->arch.omit_fp) {
5323                 /*
5324                  * On enter, the stack is misaligned by the the pushing of the return
5325                  * address. It is either made aligned by the pushing of %rbp, or by
5326                  * this.
5327                  */
5328                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5329                 if ((alloc_size % 16) == 0)
5330                         alloc_size += 8;
5331         } else {
5332                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5333
5334                 alloc_size -= pos;
5335         }
5336
5337         cfg->arch.stack_alloc_size = alloc_size;
5338
5339         /* Allocate stack frame */
5340         if (alloc_size) {
5341                 /* See mono_emit_stack_alloc */
5342 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5343                 guint32 remaining_size = alloc_size;
5344                 while (remaining_size >= 0x1000) {
5345                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5346                         if (cfg->arch.omit_fp) {
5347                                 cfa_offset += 0x1000;
5348                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5349                         }
5350                         async_exc_point (code);
5351 #ifdef PLATFORM_WIN32
5352                         if (cfg->arch.omit_fp)
5353                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5354 #endif
5355
5356                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5357                         remaining_size -= 0x1000;
5358                 }
5359                 if (remaining_size) {
5360                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5361                         if (cfg->arch.omit_fp) {
5362                                 cfa_offset += remaining_size;
5363                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5364                                 async_exc_point (code);
5365                         }
5366 #ifdef PLATFORM_WIN32
5367                         if (cfg->arch.omit_fp)
5368                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5369 #endif
5370                 }
5371 #else
5372                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5373                 if (cfg->arch.omit_fp) {
5374                         cfa_offset += alloc_size;
5375                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5376                         async_exc_point (code);
5377                 }
5378 #endif
5379         }
5380
5381         /* Stack alignment check */
5382 #if 0
5383         {
5384                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5385                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5386                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5387                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5388                 amd64_breakpoint (code);
5389         }
5390 #endif
5391
5392         /* Save LMF */
5393         if (method->save_lmf) {
5394                 /*
5395                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5396                  */
5397                 /* sp is saved right before calls */
5398                 /* Skip method (only needed for trampoline LMF frames) */
5399                 /* Save callee saved regs */
5400                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5401                         int offset;
5402
5403                         switch (i) {
5404                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5405                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5406                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5407                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5408                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5409                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5410 #ifdef PLATFORM_WIN32
5411                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5412                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5413 #endif
5414                         default:
5415                                 offset = -1;
5416                                 break;
5417                         }
5418
5419                         if (offset != -1) {
5420                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5421                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5422                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5423                         }
5424                 }
5425         }
5426
5427         /* Save callee saved registers */
5428         if (cfg->arch.omit_fp && !method->save_lmf) {
5429                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5430
5431                 /* Save caller saved registers after sp is adjusted */
5432                 /* The registers are saved at the bottom of the frame */
5433                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5434                 for (i = 0; i < AMD64_NREG; ++i)
5435                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5436                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5437                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5438                                 save_area_offset += 8;
5439                                 async_exc_point (code);
5440                         }
5441         }
5442
5443         /* store runtime generic context */
5444         if (cfg->rgctx_var) {
5445                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5446                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5447
5448                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5449         }
5450
5451         /* compute max_length in order to use short forward jumps */
5452         max_epilog_size = get_max_epilog_size (cfg);
5453         if (cfg->opt & MONO_OPT_BRANCH) {
5454                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5455                         MonoInst *ins;
5456                         int max_length = 0;
5457
5458                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5459                                 max_length += 6;
5460                         /* max alignment for loops */
5461                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5462                                 max_length += LOOP_ALIGNMENT;
5463
5464                         MONO_BB_FOR_EACH_INS (bb, ins) {
5465                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5466                         }
5467
5468                         /* Take prolog and epilog instrumentation into account */
5469                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5470                                 max_length += max_epilog_size;
5471
5472                         bb->max_length = max_length;
5473                 }
5474         }
5475
5476         sig = mono_method_signature (method);
5477         pos = 0;
5478
5479         cinfo = cfg->arch.cinfo;
5480
5481         if (sig->ret->type != MONO_TYPE_VOID) {
5482                 /* Save volatile arguments to the stack */
5483                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5484                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5485         }
5486
5487         /* Keep this in sync with emit_load_volatile_arguments */
5488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5489                 ArgInfo *ainfo = cinfo->args + i;
5490                 gint32 stack_offset;
5491                 MonoType *arg_type;
5492
5493                 ins = cfg->args [i];
5494
5495                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5496                         /* Unused arguments */
5497                         continue;
5498
5499                 if (sig->hasthis && (i == 0))
5500                         arg_type = &mono_defaults.object_class->byval_arg;
5501                 else
5502                         arg_type = sig->params [i - sig->hasthis];
5503
5504                 stack_offset = ainfo->offset + ARGS_OFFSET;
5505
5506                 if (cfg->globalra) {
5507                         /* All the other moves are done by the register allocator */
5508                         switch (ainfo->storage) {
5509                         case ArgInFloatSSEReg:
5510                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5511                                 break;
5512                         case ArgValuetypeInReg:
5513                                 for (quad = 0; quad < 2; quad ++) {
5514                                         switch (ainfo->pair_storage [quad]) {
5515                                         case ArgInIReg:
5516                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5517                                                 break;
5518                                         case ArgInFloatSSEReg:
5519                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5520                                                 break;
5521                                         case ArgInDoubleSSEReg:
5522                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5523                                                 break;
5524                                         case ArgNone:
5525                                                 break;
5526                                         default:
5527                                                 g_assert_not_reached ();
5528                                         }
5529                                 }
5530                                 break;
5531                         default:
5532                                 break;
5533                         }
5534
5535                         continue;
5536                 }
5537
5538                 /* Save volatile arguments to the stack */
5539                 if (ins->opcode != OP_REGVAR) {
5540                         switch (ainfo->storage) {
5541                         case ArgInIReg: {
5542                                 guint32 size = 8;
5543
5544                                 /* FIXME: I1 etc */
5545                                 /*
5546                                 if (stack_offset & 0x1)
5547                                         size = 1;
5548                                 else if (stack_offset & 0x2)
5549                                         size = 2;
5550                                 else if (stack_offset & 0x4)
5551                                         size = 4;
5552                                 else
5553                                         size = 8;
5554                                 */
5555                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5556                                 break;
5557                         }
5558                         case ArgInFloatSSEReg:
5559                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5560                                 break;
5561                         case ArgInDoubleSSEReg:
5562                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5563                                 break;
5564                         case ArgValuetypeInReg:
5565                                 for (quad = 0; quad < 2; quad ++) {
5566                                         switch (ainfo->pair_storage [quad]) {
5567                                         case ArgInIReg:
5568                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5569                                                 break;
5570                                         case ArgInFloatSSEReg:
5571                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5572                                                 break;
5573                                         case ArgInDoubleSSEReg:
5574                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5575                                                 break;
5576                                         case ArgNone:
5577                                                 break;
5578                                         default:
5579                                                 g_assert_not_reached ();
5580                                         }
5581                                 }
5582                                 break;
5583                         case ArgValuetypeAddrInIReg:
5584                                 if (ainfo->pair_storage [0] == ArgInIReg)
5585                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5586                                 break;
5587                         default:
5588                                 break;
5589                         }
5590                 } else {
5591                         /* Argument allocated to (non-volatile) register */
5592                         switch (ainfo->storage) {
5593                         case ArgInIReg:
5594                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5595                                 break;
5596                         case ArgOnStack:
5597                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5598                                 break;
5599                         default:
5600                                 g_assert_not_reached ();
5601                         }
5602                 }
5603         }
5604
5605         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5606         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5607                 guint64 domain = (guint64)cfg->domain;
5608
5609                 args_clobbered = TRUE;
5610
5611                 /*
5612                  * The call might clobber argument registers, but they are already
5613                  * saved to the stack/global regs.
5614                  */
5615                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5616                         guint8 *buf, *no_domain_branch;
5617
5618                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5619                         if (cfg->compile_aot) {
5620                                 /* AOT code is only used in the root domain */
5621                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
5622                         } else {
5623                                 if ((domain >> 32) == 0)
5624                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5625                                 else
5626                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5627                         }
5628                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5629                         no_domain_branch = code;
5630                         x86_branch8 (code, X86_CC_NE, 0, 0);
5631                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5632                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5633                         buf = code;
5634                         x86_branch8 (code, X86_CC_NE, 0, 0);
5635                         amd64_patch (no_domain_branch, code);
5636                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5637                                           (gpointer)"mono_jit_thread_attach", TRUE);
5638                         amd64_patch (buf, code);
5639 #ifdef PLATFORM_WIN32
5640                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5641                         /* FIXME: Add a separate key for LMF to avoid this */
5642                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5643 #endif
5644                 } else {
5645                         g_assert (!cfg->compile_aot);
5646                         if (cfg->compile_aot) {
5647                                 /* AOT code is only used in the root domain */
5648                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
5649                         } else {
5650                                 if ((domain >> 32) == 0)
5651                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5652                                 else
5653                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5654                         }
5655                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5656                                           (gpointer)"mono_jit_thread_attach", TRUE);
5657                 }
5658         }
5659
5660         if (method->save_lmf) {
5661                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5662                         /*
5663                          * Optimized version which uses the mono_lmf TLS variable instead of
5664                          * indirection through the mono_lmf_addr TLS variable.
5665                          */
5666                         /* %rax = previous_lmf */
5667                         x86_prefix (code, X86_FS_PREFIX);
5668                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5669
5670                         /* Save previous_lmf */
5671                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5672                         /* Set new lmf */
5673                         if (lmf_offset == 0) {
5674                                 x86_prefix (code, X86_FS_PREFIX);
5675                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5676                         } else {
5677                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5678                                 x86_prefix (code, X86_FS_PREFIX);
5679                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5680                         }
5681                 } else {
5682                         if (lmf_addr_tls_offset != -1) {
5683                                 /* Load lmf quicky using the FS register */
5684                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5685 #ifdef PLATFORM_WIN32
5686                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5687                                 /* FIXME: Add a separate key for LMF to avoid this */
5688                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5689 #endif
5690                         }
5691                         else {
5692                                 /*
5693                                  * The call might clobber argument registers, but they are already
5694                                  * saved to the stack/global regs.
5695                                  */
5696                                 args_clobbered = TRUE;
5697                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5698                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
5699                         }
5700
5701                         /* Save lmf_addr */
5702                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5703                         /* Save previous_lmf */
5704                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5705                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5706                         /* Set new lmf */
5707                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5708                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5709                 }
5710         }
5711
5712         if (trace) {
5713                 args_clobbered = TRUE;
5714                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5715         }
5716
5717         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5718                 args_clobbered = TRUE;
5719
5720         /*
5721          * Optimize the common case of the first bblock making a call with the same
5722          * arguments as the method. This works because the arguments are still in their
5723          * original argument registers.
5724          * FIXME: Generalize this
5725          */
5726         if (!args_clobbered) {
5727                 MonoBasicBlock *first_bb = cfg->bb_entry;
5728                 MonoInst *next;
5729
5730                 next = mono_bb_first_ins (first_bb);
5731                 if (!next && first_bb->next_bb) {
5732                         first_bb = first_bb->next_bb;
5733                         next = mono_bb_first_ins (first_bb);
5734                 }
5735
5736                 if (first_bb->in_count > 1)
5737                         next = NULL;
5738
5739                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5740                         ArgInfo *ainfo = cinfo->args + i;
5741                         gboolean match = FALSE;
5742
5743                         ins = cfg->args [i];
5744                         if (ins->opcode != OP_REGVAR) {
5745                                 switch (ainfo->storage) {
5746                                 case ArgInIReg: {
5747                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5748                                                 if (next->dreg == ainfo->reg) {
5749                                                         NULLIFY_INS (next);
5750                                                         match = TRUE;
5751                                                 } else {
5752                                                         next->opcode = OP_MOVE;
5753                                                         next->sreg1 = ainfo->reg;
5754                                                         /* Only continue if the instruction doesn't change argument regs */
5755                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5756                                                                 match = TRUE;
5757                                                 }
5758                                         }
5759                                         break;
5760                                 }
5761                                 default:
5762                                         break;
5763                                 }
5764                         } else {
5765                                 /* Argument allocated to (non-volatile) register */
5766                                 switch (ainfo->storage) {
5767                                 case ArgInIReg:
5768                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5769                                                 NULLIFY_INS (next);
5770                                                 match = TRUE;
5771                                         }
5772                                         break;
5773                                 default:
5774                                         break;
5775                                 }
5776                         }
5777
5778                         if (match) {
5779                                 next = next->next;
5780                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5781                                 if (!next)
5782                                         break;
5783                         }
5784                 }
5785         }
5786
5787         cfg->code_len = code - cfg->native_code;
5788
5789         g_assert (cfg->code_len < cfg->code_size);
5790
5791         return code;
5792 }
5793
5794 void
5795 mono_arch_emit_epilog (MonoCompile *cfg)
5796 {
5797         MonoMethod *method = cfg->method;
5798         int quad, pos, i;
5799         guint8 *code;
5800         int max_epilog_size;
5801         CallInfo *cinfo;
5802         gint32 lmf_offset = cfg->arch.lmf_offset;
5803
5804         max_epilog_size = get_max_epilog_size (cfg);
5805
5806         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5807                 cfg->code_size *= 2;
5808                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5809                 mono_jit_stats.code_reallocs++;
5810         }
5811
5812         code = cfg->native_code + cfg->code_len;
5813
5814         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5815                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5816
5817         /* the code restoring the registers must be kept in sync with OP_JMP */
5818         pos = 0;
5819
5820         if (method->save_lmf) {
5821                 /* check if we need to restore protection of the stack after a stack overflow */
5822                 if (mono_get_jit_tls_offset () != -1) {
5823                         guint8 *patch;
5824                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
5825                         /* we load the value in a separate instruction: this mechanism may be
5826                          * used later as a safer way to do thread interruption
5827                          */
5828                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
5829                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
5830                         patch = code;
5831                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
5832                         /* note that the call trampoline will preserve eax/edx */
5833                         x86_call_reg (code, X86_ECX);
5834                         x86_patch (patch, code);
5835                 } else {
5836                         /* FIXME: maybe save the jit tls in the prolog */
5837                 }
5838                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5839                         /*
5840                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5841                          * through the mono_lmf_addr TLS variable.
5842                          */
5843                         /* reg = previous_lmf */
5844                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5845                         x86_prefix (code, X86_FS_PREFIX);
5846                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5847                 } else {
5848                         /* Restore previous lmf */
5849                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5850                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5851                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5852                 }
5853
5854                 /* Restore caller saved regs */
5855                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5856                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5857                 }
5858                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5859                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5860                 }
5861                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5862                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5863                 }
5864                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5865                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5866                 }
5867                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5868                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5869                 }
5870                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5871                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5872                 }
5873 #ifdef PLATFORM_WIN32
5874                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
5875                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
5876                 }
5877                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
5878                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
5879                 }
5880 #endif
5881         } else {
5882
5883                 if (cfg->arch.omit_fp) {
5884                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5885
5886                         for (i = 0; i < AMD64_NREG; ++i)
5887                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5888                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5889                                         save_area_offset += 8;
5890                                 }
5891                 }
5892                 else {
5893                         for (i = 0; i < AMD64_NREG; ++i)
5894                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5895                                         pos -= sizeof (gpointer);
5896
5897                         if (pos) {
5898                                 if (pos == - sizeof (gpointer)) {
5899                                         /* Only one register, so avoid lea */
5900                                         for (i = AMD64_NREG - 1; i > 0; --i)
5901                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5902                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5903                                                 }
5904                                 }
5905                                 else {
5906                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5907
5908                                         /* Pop registers in reverse order */
5909                                         for (i = AMD64_NREG - 1; i > 0; --i)
5910                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5911                                                         amd64_pop_reg (code, i);
5912                                                 }
5913                                 }
5914                         }
5915                 }
5916         }
5917
5918         /* Load returned vtypes into registers if needed */
5919         cinfo = cfg->arch.cinfo;
5920         if (cinfo->ret.storage == ArgValuetypeInReg) {
5921                 ArgInfo *ainfo = &cinfo->ret;
5922                 MonoInst *inst = cfg->ret;
5923
5924                 for (quad = 0; quad < 2; quad ++) {
5925                         switch (ainfo->pair_storage [quad]) {
5926                         case ArgInIReg:
5927                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5928                                 break;
5929                         case ArgInFloatSSEReg:
5930                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5931                                 break;
5932                         case ArgInDoubleSSEReg:
5933                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5934                                 break;
5935                         case ArgNone:
5936                                 break;
5937                         default:
5938                                 g_assert_not_reached ();
5939                         }
5940                 }
5941         }
5942
5943         if (cfg->arch.omit_fp) {
5944                 if (cfg->arch.stack_alloc_size)
5945                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5946         } else {
5947                 amd64_leave (code);
5948         }
5949         async_exc_point (code);
5950         amd64_ret (code);
5951
5952         cfg->code_len = code - cfg->native_code;
5953
5954         g_assert (cfg->code_len < cfg->code_size);
5955 }
5956
5957 void
5958 mono_arch_emit_exceptions (MonoCompile *cfg)
5959 {
5960         MonoJumpInfo *patch_info;
5961         int nthrows, i;
5962         guint8 *code;
5963         MonoClass *exc_classes [16];
5964         guint8 *exc_throw_start [16], *exc_throw_end [16];
5965         guint32 code_size = 0;
5966
5967         /* Compute needed space */
5968         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5969                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5970                         code_size += 40;
5971                 if (patch_info->type == MONO_PATCH_INFO_R8)
5972                         code_size += 8 + 15; /* sizeof (double) + alignment */
5973                 if (patch_info->type == MONO_PATCH_INFO_R4)
5974                         code_size += 4 + 15; /* sizeof (float) + alignment */
5975         }
5976
5977         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5978                 cfg->code_size *= 2;
5979                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5980                 mono_jit_stats.code_reallocs++;
5981         }
5982
5983         code = cfg->native_code + cfg->code_len;
5984
5985         /* add code to raise exceptions */
5986         nthrows = 0;
5987         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5988                 switch (patch_info->type) {
5989                 case MONO_PATCH_INFO_EXC: {
5990                         MonoClass *exc_class;
5991                         guint8 *buf, *buf2;
5992                         guint32 throw_ip;
5993
5994                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5995
5996                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5997                         g_assert (exc_class);
5998                         throw_ip = patch_info->ip.i;
5999
6000                         //x86_breakpoint (code);
6001                         /* Find a throw sequence for the same exception class */
6002                         for (i = 0; i < nthrows; ++i)
6003                                 if (exc_classes [i] == exc_class)
6004                                         break;
6005                         if (i < nthrows) {
6006                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6007                                 x86_jump_code (code, exc_throw_start [i]);
6008                                 patch_info->type = MONO_PATCH_INFO_NONE;
6009                         }
6010                         else {
6011                                 buf = code;
6012                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6013                                 buf2 = code;
6014
6015                                 if (nthrows < 16) {
6016                                         exc_classes [nthrows] = exc_class;
6017                                         exc_throw_start [nthrows] = code;
6018                                 }
6019                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6020
6021                                 patch_info->type = MONO_PATCH_INFO_NONE;
6022
6023                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6024
6025                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6026                                 while (buf < buf2)
6027                                         x86_nop (buf);
6028
6029                                 if (nthrows < 16) {
6030                                         exc_throw_end [nthrows] = code;
6031                                         nthrows ++;
6032                                 }
6033                         }
6034                         break;
6035                 }
6036                 default:
6037                         /* do nothing */
6038                         break;
6039                 }
6040         }
6041
6042         /* Handle relocations with RIP relative addressing */
6043         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6044                 gboolean remove = FALSE;
6045
6046                 switch (patch_info->type) {
6047                 case MONO_PATCH_INFO_R8:
6048                 case MONO_PATCH_INFO_R4: {
6049                         guint8 *pos;
6050
6051                         /* The SSE opcodes require a 16 byte alignment */
6052                         code = (guint8*)ALIGN_TO (code, 16);
6053
6054                         pos = cfg->native_code + patch_info->ip.i;
6055
6056                         if (IS_REX (pos [1]))
6057                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6058                         else
6059                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6060
6061                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6062                                 *(double*)code = *(double*)patch_info->data.target;
6063                                 code += sizeof (double);
6064                         } else {
6065                                 *(float*)code = *(float*)patch_info->data.target;
6066                                 code += sizeof (float);
6067                         }
6068
6069                         remove = TRUE;
6070                         break;
6071                 }
6072                 default:
6073                         break;
6074                 }
6075
6076                 if (remove) {
6077                         if (patch_info == cfg->patch_info)
6078                                 cfg->patch_info = patch_info->next;
6079                         else {
6080                                 MonoJumpInfo *tmp;
6081
6082                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6083                                         ;
6084                                 tmp->next = patch_info->next;
6085                         }
6086                 }
6087         }
6088
6089         cfg->code_len = code - cfg->native_code;
6090
6091         g_assert (cfg->code_len < cfg->code_size);
6092
6093 }
6094
6095 void*
6096 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6097 {
6098         guchar *code = p;
6099         CallInfo *cinfo = NULL;
6100         MonoMethodSignature *sig;
6101         MonoInst *inst;
6102         int i, n, stack_area = 0;
6103
6104         /* Keep this in sync with mono_arch_get_argument_info */
6105
6106         if (enable_arguments) {
6107                 /* Allocate a new area on the stack and save arguments there */
6108                 sig = mono_method_signature (cfg->method);
6109
6110                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6111
6112                 n = sig->param_count + sig->hasthis;
6113
6114                 stack_area = ALIGN_TO (n * 8, 16);
6115
6116                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6117
6118                 for (i = 0; i < n; ++i) {
6119                         inst = cfg->args [i];
6120
6121                         if (inst->opcode == OP_REGVAR)
6122                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6123                         else {
6124                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6125                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6126                         }
6127                 }
6128         }
6129
6130         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6131         amd64_set_reg_template (code, AMD64_ARG_REG1);
6132         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6133         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6134
6135         if (enable_arguments)
6136                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6137
6138         return code;
6139 }
6140
6141 enum {
6142         SAVE_NONE,
6143         SAVE_STRUCT,
6144         SAVE_EAX,
6145         SAVE_EAX_EDX,
6146         SAVE_XMM
6147 };
6148
6149 void*
6150 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6151 {
6152         guchar *code = p;
6153         int save_mode = SAVE_NONE;
6154         MonoMethod *method = cfg->method;
6155         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
6156
6157         switch (rtype) {
6158         case MONO_TYPE_VOID:
6159                 /* special case string .ctor icall */
6160                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6161                         save_mode = SAVE_EAX;
6162                 else
6163                         save_mode = SAVE_NONE;
6164                 break;
6165         case MONO_TYPE_I8:
6166         case MONO_TYPE_U8:
6167                 save_mode = SAVE_EAX;
6168                 break;
6169         case MONO_TYPE_R4:
6170         case MONO_TYPE_R8:
6171                 save_mode = SAVE_XMM;
6172                 break;
6173         case MONO_TYPE_GENERICINST:
6174                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
6175                         save_mode = SAVE_EAX;
6176                         break;
6177                 }
6178                 /* Fall through */
6179         case MONO_TYPE_VALUETYPE:
6180                 save_mode = SAVE_STRUCT;
6181                 break;
6182         default:
6183                 save_mode = SAVE_EAX;
6184                 break;
6185         }
6186
6187         /* Save the result and copy it into the proper argument register */
6188         switch (save_mode) {
6189         case SAVE_EAX:
6190                 amd64_push_reg (code, AMD64_RAX);
6191                 /* Align stack */
6192                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6193                 if (enable_arguments)
6194                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6195                 break;
6196         case SAVE_STRUCT:
6197                 /* FIXME: */
6198                 if (enable_arguments)
6199                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6200                 break;
6201         case SAVE_XMM:
6202                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6203                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6204                 /* Align stack */
6205                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6206                 /*
6207                  * The result is already in the proper argument register so no copying
6208                  * needed.
6209                  */
6210                 break;
6211         case SAVE_NONE:
6212                 break;
6213         default:
6214                 g_assert_not_reached ();
6215         }
6216
6217         /* Set %al since this is a varargs call */
6218         if (save_mode == SAVE_XMM)
6219                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6220         else
6221                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6222
6223         if (preserve_argument_registers) {
6224                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6225                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6226         }
6227
6228         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6229         amd64_set_reg_template (code, AMD64_ARG_REG1);
6230         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6231
6232         if (preserve_argument_registers) {
6233                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6234                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6235         }
6236
6237         /* Restore result */
6238         switch (save_mode) {
6239         case SAVE_EAX:
6240                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6241                 amd64_pop_reg (code, AMD64_RAX);
6242                 break;
6243         case SAVE_STRUCT:
6244                 /* FIXME: */
6245                 break;
6246         case SAVE_XMM:
6247                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6248                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6249                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6250                 break;
6251         case SAVE_NONE:
6252                 break;
6253         default:
6254                 g_assert_not_reached ();
6255         }
6256
6257         return code;
6258 }
6259
6260 void
6261 mono_arch_flush_icache (guint8 *code, gint size)
6262 {
6263         /* Not needed */
6264 }
6265
6266 void
6267 mono_arch_flush_register_windows (void)
6268 {
6269 }
6270
6271 gboolean
6272 mono_arch_is_inst_imm (gint64 imm)
6273 {
6274         return amd64_is_imm32 (imm);
6275 }
6276
6277 /*
6278  * Determine whenever the trap whose info is in SIGINFO is caused by
6279  * integer overflow.
6280  */
6281 gboolean
6282 mono_arch_is_int_overflow (void *sigctx, void *info)
6283 {
6284         MonoContext ctx;
6285         guint8* rip;
6286         int reg;
6287         gint64 value;
6288
6289         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6290
6291         rip = (guint8*)ctx.rip;
6292
6293         if (IS_REX (rip [0])) {
6294                 reg = amd64_rex_b (rip [0]);
6295                 rip ++;
6296         }
6297         else
6298                 reg = 0;
6299
6300         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6301                 /* idiv REG */
6302                 reg += x86_modrm_rm (rip [1]);
6303
6304                 switch (reg) {
6305                 case AMD64_RAX:
6306                         value = ctx.rax;
6307                         break;
6308                 case AMD64_RBX:
6309                         value = ctx.rbx;
6310                         break;
6311                 case AMD64_RCX:
6312                         value = ctx.rcx;
6313                         break;
6314                 case AMD64_RDX:
6315                         value = ctx.rdx;
6316                         break;
6317                 case AMD64_RBP:
6318                         value = ctx.rbp;
6319                         break;
6320                 case AMD64_RSP:
6321                         value = ctx.rsp;
6322                         break;
6323                 case AMD64_RSI:
6324                         value = ctx.rsi;
6325                         break;
6326                 case AMD64_RDI:
6327                         value = ctx.rdi;
6328                         break;
6329                 case AMD64_R12:
6330                         value = ctx.r12;
6331                         break;
6332                 case AMD64_R13:
6333                         value = ctx.r13;
6334                         break;
6335                 case AMD64_R14:
6336                         value = ctx.r14;
6337                         break;
6338                 case AMD64_R15:
6339                         value = ctx.r15;
6340                         break;
6341                 default:
6342                         g_assert_not_reached ();
6343                         reg = -1;
6344                 }
6345
6346                 if (value == -1)
6347                         return TRUE;
6348         }
6349
6350         return FALSE;
6351 }
6352
6353 guint32
6354 mono_arch_get_patch_offset (guint8 *code)
6355 {
6356         return 3;
6357 }
6358
6359 /**
6360  * mono_breakpoint_clean_code:
6361  *
6362  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6363  * breakpoints in the original code, they are removed in the copy.
6364  *
6365  * Returns TRUE if no sw breakpoint was present.
6366  */
6367 gboolean
6368 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6369 {
6370         int i;
6371         gboolean can_write = TRUE;
6372         /*
6373          * If method_start is non-NULL we need to perform bound checks, since we access memory
6374          * at code - offset we could go before the start of the method and end up in a different
6375          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6376          * instead.
6377          */
6378         if (!method_start || code - offset >= method_start) {
6379                 memcpy (buf, code - offset, size);
6380         } else {
6381                 int diff = code - method_start;
6382                 memset (buf, 0, size);
6383                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6384         }
6385         code -= offset;
6386         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6387                 int idx = mono_breakpoint_info_index [i];
6388                 guint8 *ptr;
6389                 if (idx < 1)
6390                         continue;
6391                 ptr = mono_breakpoint_info [idx].address;
6392                 if (ptr >= code && ptr < code + size) {
6393                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6394                         can_write = FALSE;
6395                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6396                         buf [ptr - code] = saved_byte;
6397                 }
6398         }
6399         return can_write;
6400 }
6401
6402 gpointer
6403 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6404 {
6405         guint8 buf [10];
6406         guint32 reg;
6407         gint32 disp;
6408         guint8 rex = 0;
6409
6410         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
6411         code = buf + 9;
6412
6413         *displacement = 0;
6414
6415         code -= 7;
6416
6417         /*
6418          * A given byte sequence can match more than case here, so we have to be
6419          * really careful about the ordering of the cases. Longer sequences
6420          * come first.
6421          * There are two types of calls:
6422          * - direct calls: 0xff address_byte 8/32 bits displacement
6423          * - indirect calls: nop nop nop <call>
6424          * The nops make sure we don't confuse the instruction preceeding an indirect
6425          * call with a direct call.
6426          */
6427         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6428                 /* call OFFSET(%rip) */
6429                 disp = *(guint32*)(code + 3);
6430                 return (gpointer*)(code + disp + 7);
6431         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6432                 /* call *[reg+disp32] using indexed addressing */
6433                 /* The LLVM JIT emits this, and we emit it too for %r12 */
6434                 if (IS_REX (code [-1])) {
6435                         rex = code [-1];
6436                         g_assert (amd64_rex_x (rex) == 0);
6437                 }
6438                 reg = amd64_sib_base (code [2]);
6439                 disp = *(gint32*)(code + 3);
6440         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6441                 /* call *[reg+disp32] */
6442                 if (IS_REX (code [0]))
6443                         rex = code [0];
6444                 reg = amd64_modrm_rm (code [2]);
6445                 disp = *(gint32*)(code + 3);
6446                 /* R10 is clobbered by the IMT thunk code */
6447                 g_assert (reg != AMD64_R10);
6448         } else if (code [2] == 0xe8) {
6449                 /* call <ADDR> */
6450                 return NULL;
6451         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6452                 /* call *[r12+disp8] using indexed addressing */
6453                 if (IS_REX (code [2]))
6454                         rex = code [2];
6455                 reg = amd64_sib_base (code [5]);
6456                 disp = *(gint8*)(code + 6);
6457         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6458                 /* call *%reg */
6459                 return NULL;
6460         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6461                 /* call *[reg+disp8] */
6462                 if (IS_REX (code [3]))
6463                         rex = code [3];
6464                 reg = amd64_modrm_rm (code [5]);
6465                 disp = *(gint8*)(code + 6);
6466                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6467         }
6468         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6469                 /* call *%reg */
6470                 if (IS_REX (code [4]))
6471                         rex = code [4];
6472                 reg = amd64_modrm_rm (code [6]);
6473                 disp = 0;
6474         }
6475         else
6476                 g_assert_not_reached ();
6477
6478         reg += amd64_rex_b (rex);
6479
6480         /* R11 is clobbered by the trampoline code */
6481         g_assert (reg != AMD64_R11);
6482
6483         *displacement = disp;
6484         return (gpointer)regs [reg];
6485 }
6486
6487 int
6488 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6489 {
6490         int this_reg = AMD64_ARG_REG1;
6491
6492         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6493                 CallInfo *cinfo;
6494
6495                 if (!gsctx && code)
6496                         gsctx = mono_get_generic_context_from_code (code);
6497
6498                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6499
6500                 if (cinfo->ret.storage != ArgValuetypeInReg)
6501                         this_reg = AMD64_ARG_REG2;
6502                 g_free (cinfo);
6503         }
6504
6505         return this_reg;
6506 }
6507
6508 gpointer
6509 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
6510 {
6511         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6512 }
6513
6514 #define MAX_ARCH_DELEGATE_PARAMS 10
6515
6516 static gpointer
6517 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6518 {
6519         guint8 *code, *start;
6520         int i;
6521
6522         if (has_target) {
6523                 start = code = mono_global_codeman_reserve (64);
6524
6525                 /* Replace the this argument with the target */
6526                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6527                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6528                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6529
6530                 g_assert ((code - start) < 64);
6531         } else {
6532                 start = code = mono_global_codeman_reserve (64);
6533
6534                 if (param_count == 0) {
6535                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6536                 } else {
6537                         /* We have to shift the arguments left */
6538                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6539                         for (i = 0; i < param_count; ++i) {
6540 #ifdef PLATFORM_WIN32
6541                                 if (i < 3)
6542                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6543                                 else
6544                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6545 #else
6546                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6547 #endif
6548                         }
6549
6550                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6551                 }
6552                 g_assert ((code - start) < 64);
6553         }
6554
6555         mono_debug_add_delegate_trampoline (start, code - start);
6556
6557         if (code_len)
6558                 *code_len = code - start;
6559
6560         return start;
6561 }
6562
6563 /*
6564  * mono_arch_get_delegate_invoke_impls:
6565  *
6566  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
6567  * trampolines.
6568  */
6569 GSList*
6570 mono_arch_get_delegate_invoke_impls (void)
6571 {
6572         GSList *res = NULL;
6573         guint8 *code;
6574         guint32 code_len;
6575         int i;
6576
6577         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6578         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
6579
6580         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6581                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6582                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
6583         }
6584
6585         return res;
6586 }
6587
6588 gpointer
6589 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6590 {
6591         guint8 *code, *start;
6592         int i;
6593
6594         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6595                 return NULL;
6596
6597         /* FIXME: Support more cases */
6598         if (MONO_TYPE_ISSTRUCT (sig->ret))
6599                 return NULL;
6600
6601         if (has_target) {
6602                 static guint8* cached = NULL;
6603
6604                 if (cached)
6605                         return cached;
6606
6607                 if (mono_aot_only)
6608                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
6609                 else
6610                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
6611
6612                 mono_memory_barrier ();
6613
6614                 cached = start;
6615         } else {
6616                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6617                 for (i = 0; i < sig->param_count; ++i)
6618                         if (!mono_is_regsize_var (sig->params [i]))
6619                                 return NULL;
6620                 if (sig->param_count > 4)
6621                         return NULL;
6622
6623                 code = cache [sig->param_count];
6624                 if (code)
6625                         return code;
6626
6627                 if (mono_aot_only) {
6628                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6629                         start = mono_aot_get_named_code (name);
6630                         g_free (name);
6631                 } else {
6632                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6633                 }
6634
6635                 mono_memory_barrier ();
6636
6637                 cache [sig->param_count] = start;
6638         }
6639
6640         return start;
6641 }
6642
6643 /*
6644  * Support for fast access to the thread-local lmf structure using the GS
6645  * segment register on NPTL + kernel 2.6.x.
6646  */
6647
6648 static gboolean tls_offset_inited = FALSE;
6649
6650 void
6651 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6652 {
6653         if (!tls_offset_inited) {
6654 #ifdef PLATFORM_WIN32
6655                 /*
6656                  * We need to init this multiple times, since when we are first called, the key might not
6657                  * be initialized yet.
6658                  */
6659                 appdomain_tls_offset = mono_domain_get_tls_key ();
6660                 lmf_tls_offset = mono_get_jit_tls_key ();
6661                 thread_tls_offset = mono_thread_get_tls_key ();
6662                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6663
6664                 /* Only 64 tls entries can be accessed using inline code */
6665                 if (appdomain_tls_offset >= 64)
6666                         appdomain_tls_offset = -1;
6667                 if (lmf_tls_offset >= 64)
6668                         lmf_tls_offset = -1;
6669                 if (thread_tls_offset >= 64)
6670                         thread_tls_offset = -1;
6671 #else
6672                 tls_offset_inited = TRUE;
6673 #ifdef MONO_XEN_OPT
6674                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6675 #endif
6676                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6677                 lmf_tls_offset = mono_get_lmf_tls_offset ();
6678                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6679                 thread_tls_offset = mono_thread_get_tls_offset ();
6680 #endif
6681         }
6682 }
6683
6684 void
6685 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6686 {
6687 }
6688
6689 #ifdef MONO_ARCH_HAVE_IMT
6690
6691 #define CMP_SIZE (6 + 1)
6692 #define CMP_REG_REG_SIZE (4 + 1)
6693 #define BR_SMALL_SIZE 2
6694 #define BR_LARGE_SIZE 6
6695 #define MOV_REG_IMM_SIZE 10
6696 #define MOV_REG_IMM_32BIT_SIZE 6
6697 #define JUMP_REG_SIZE (2 + 1)
6698
6699 static int
6700 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6701 {
6702         int i, distance = 0;
6703         for (i = start; i < target; ++i)
6704                 distance += imt_entries [i]->chunk_size;
6705         return distance;
6706 }
6707
6708 /*
6709  * LOCKING: called with the domain lock held
6710  */
6711 gpointer
6712 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
6713         gpointer fail_tramp)
6714 {
6715         int i;
6716         int size = 0;
6717         guint8 *code, *start;
6718         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6719
6720         for (i = 0; i < count; ++i) {
6721                 MonoIMTCheckItem *item = imt_entries [i];
6722                 if (item->is_equals) {
6723                         if (item->check_target_idx) {
6724                                 if (!item->compare_done) {
6725                                         if (amd64_is_imm32 (item->key))
6726                                                 item->chunk_size += CMP_SIZE;
6727                                         else
6728                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6729                                 }
6730                                 if (item->has_target_code) {
6731                                         item->chunk_size += MOV_REG_IMM_SIZE;
6732                                 } else {
6733                                         if (vtable_is_32bit)
6734                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6735                                         else
6736                                                 item->chunk_size += MOV_REG_IMM_SIZE;
6737                                 }
6738                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6739                         } else {
6740                                 if (fail_tramp) {
6741                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
6742                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
6743                                 } else {
6744                                         if (vtable_is_32bit)
6745                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6746                                         else
6747                                                 item->chunk_size += MOV_REG_IMM_SIZE;
6748                                         item->chunk_size += JUMP_REG_SIZE;
6749                                         /* with assert below:
6750                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6751                                          */
6752                                 }
6753                         }
6754                 } else {
6755                         if (amd64_is_imm32 (item->key))
6756                                 item->chunk_size += CMP_SIZE;
6757                         else
6758                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6759                         item->chunk_size += BR_LARGE_SIZE;
6760                         imt_entries [item->check_target_idx]->compare_done = TRUE;
6761                 }
6762                 size += item->chunk_size;
6763         }
6764         if (fail_tramp)
6765                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
6766         else
6767                 code = mono_domain_code_reserve (domain, size);
6768         start = code;
6769         for (i = 0; i < count; ++i) {
6770                 MonoIMTCheckItem *item = imt_entries [i];
6771                 item->code_target = code;
6772                 if (item->is_equals) {
6773                         gboolean fail_case = !item->check_target_idx && fail_tramp;
6774
6775                         if (item->check_target_idx || fail_case) {
6776                                 if (!item->compare_done || fail_case) {
6777                                         if (amd64_is_imm32 (item->key))
6778                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6779                                         else {
6780                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6781                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6782                                         }
6783                                 }
6784                                 item->jmp_code = code;
6785                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6786                                 /* See the comment below about R10 */
6787                                 if (item->has_target_code) {
6788                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
6789                                         amd64_jump_reg (code, AMD64_R10);
6790                                 } else {
6791                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6792                                         amd64_jump_membase (code, AMD64_R10, 0);
6793                                 }
6794
6795                                 if (fail_case) {
6796                                         amd64_patch (item->jmp_code, code);
6797                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
6798                                         amd64_jump_reg (code, AMD64_R10);
6799                                         item->jmp_code = NULL;
6800                                 }
6801                         } else {
6802                                 /* enable the commented code to assert on wrong method */
6803 #if 0
6804                                 if (amd64_is_imm32 (item->key))
6805                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6806                                 else {
6807                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
6808                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6809                                 }
6810                                 item->jmp_code = code;
6811                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6812                                 /* See the comment below about R10 */
6813                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6814                                 amd64_jump_membase (code, AMD64_R10, 0);
6815                                 amd64_patch (item->jmp_code, code);
6816                                 amd64_breakpoint (code);
6817                                 item->jmp_code = NULL;
6818 #else
6819                                 /* We're using R10 here because R11
6820                                    needs to be preserved.  R10 needs
6821                                    to be preserved for calls which
6822                                    require a runtime generic context,
6823                                    but interface calls don't. */
6824                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
6825                                 amd64_jump_membase (code, AMD64_R10, 0);
6826 #endif
6827                         }
6828                 } else {
6829                         if (amd64_is_imm32 (item->key))
6830                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
6831                         else {
6832                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
6833                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6834                         }
6835                         item->jmp_code = code;
6836                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6837                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6838                         else
6839                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6840                 }
6841                 g_assert (code - item->code_target <= item->chunk_size);
6842         }
6843         /* patch the branches to get to the target items */
6844         for (i = 0; i < count; ++i) {
6845                 MonoIMTCheckItem *item = imt_entries [i];
6846                 if (item->jmp_code) {
6847                         if (item->check_target_idx) {
6848                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6849                         }
6850                 }
6851         }
6852
6853         if (!fail_tramp)
6854                 mono_stats.imt_thunks_size += code - start;
6855         g_assert (code - start <= size);
6856
6857         return start;
6858 }
6859
6860 MonoMethod*
6861 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
6862 {
6863         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
6864 }
6865
6866 MonoObject*
6867 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6868 {
6869         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), regs, NULL);
6870 }
6871 #endif
6872
6873 MonoVTable*
6874 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
6875 {
6876         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6877 }
6878
6879 MonoInst*
6880 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6881 {
6882         MonoInst *ins = NULL;
6883         int opcode = 0;
6884
6885         if (cmethod->klass == mono_defaults.math_class) {
6886                 if (strcmp (cmethod->name, "Sin") == 0) {
6887                         opcode = OP_SIN;
6888                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6889                         opcode = OP_COS;
6890                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6891                         opcode = OP_SQRT;
6892                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6893                         opcode = OP_ABS;
6894                 }
6895
6896                 if (opcode) {
6897                         MONO_INST_NEW (cfg, ins, opcode);
6898                         ins->type = STACK_R8;
6899                         ins->dreg = mono_alloc_freg (cfg);
6900                         ins->sreg1 = args [0]->dreg;
6901                         MONO_ADD_INS (cfg->cbb, ins);
6902                 }
6903
6904                 opcode = 0;
6905                 if (cfg->opt & MONO_OPT_CMOV) {
6906                         if (strcmp (cmethod->name, "Min") == 0) {
6907                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6908                                         opcode = OP_IMIN;
6909                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6910                                         opcode = OP_IMIN_UN;
6911                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6912                                         opcode = OP_LMIN;
6913                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6914                                         opcode = OP_LMIN_UN;
6915                         } else if (strcmp (cmethod->name, "Max") == 0) {
6916                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6917                                         opcode = OP_IMAX;
6918                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6919                                         opcode = OP_IMAX_UN;
6920                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6921                                         opcode = OP_LMAX;
6922                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6923                                         opcode = OP_LMAX_UN;
6924                         }
6925                 }
6926
6927                 if (opcode) {
6928                         MONO_INST_NEW (cfg, ins, opcode);
6929                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6930                         ins->dreg = mono_alloc_ireg (cfg);
6931                         ins->sreg1 = args [0]->dreg;
6932                         ins->sreg2 = args [1]->dreg;
6933                         MONO_ADD_INS (cfg->cbb, ins);
6934                 }
6935
6936 #if 0
6937                 /* OP_FREM is not IEEE compatible */
6938                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6939                         MONO_INST_NEW (cfg, ins, OP_FREM);
6940                         ins->inst_i0 = args [0];
6941                         ins->inst_i1 = args [1];
6942                 }
6943 #endif
6944         }
6945
6946         /*
6947          * Can't implement CompareExchange methods this way since they have
6948          * three arguments.
6949          */
6950
6951         return ins;
6952 }
6953
6954 gboolean
6955 mono_arch_print_tree (MonoInst *tree, int arity)
6956 {
6957         return 0;
6958 }
6959
6960 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6961 {
6962         MonoInst* ins;
6963
6964         if (appdomain_tls_offset == -1)
6965                 return NULL;
6966
6967         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6968         ins->inst_offset = appdomain_tls_offset;
6969         return ins;
6970 }
6971
6972 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6973 {
6974         MonoInst* ins;
6975
6976         if (thread_tls_offset == -1)
6977                 return NULL;
6978
6979         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6980         ins->inst_offset = thread_tls_offset;
6981         return ins;
6982 }
6983
6984 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6985
6986 gpointer
6987 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6988 {
6989         switch (reg) {
6990         case AMD64_RCX: return (gpointer)ctx->rcx;
6991         case AMD64_RDX: return (gpointer)ctx->rdx;
6992         case AMD64_RBX: return (gpointer)ctx->rbx;
6993         case AMD64_RBP: return (gpointer)ctx->rbp;
6994         case AMD64_RSP: return (gpointer)ctx->rsp;
6995         default:
6996                 if (reg < 8)
6997                         return _CTX_REG (ctx, rax, reg);
6998                 else if (reg >= 12)
6999                         return _CTX_REG (ctx, r12, reg - 12);
7000                 else
7001                         g_assert_not_reached ();
7002         }
7003 }