mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 void mini_emit_memcpy2 (MonoCompile *cfg, int destreg, int doffset, int srcreg, int soffset, int size, int align);
  97
  98 const char*
  99 mono_arch_regname (int reg)
 100 {
 101         switch (reg) {
 102         case AMD64_RAX: return "%rax";
 103         case AMD64_RBX: return "%rbx";
 104         case AMD64_RCX: return "%rcx";
 105         case AMD64_RDX: return "%rdx";
 106         case AMD64_RSP: return "%rsp";
 107         case AMD64_RBP: return "%rbp";
 108         case AMD64_RDI: return "%rdi";
 109         case AMD64_RSI: return "%rsi";
 110         case AMD64_R8: return "%r8";
 111         case AMD64_R9: return "%r9";
 112         case AMD64_R10: return "%r10";
 113         case AMD64_R11: return "%r11";
 114         case AMD64_R12: return "%r12";
 115         case AMD64_R13: return "%r13";
 116         case AMD64_R14: return "%r14";
 117         case AMD64_R15: return "%r15";
 118         }
 119         return "unknown";
 120 }
 121
 122 static const char * xmmregs [] = {
 123         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 124         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 125 };
 126
 127 const char*
 128 mono_arch_fregname (int reg)
 129 {
 130         if (reg < AMD64_XMM_NREG)
 131                 return xmmregs [reg];
 132         else
 133                 return "unknown";
 134 }
 135
 136 G_GNUC_UNUSED static void
 137 break_count (void)
 138 {
 139 }
 140
 141 G_GNUC_UNUSED static gboolean
 142 debug_count (void)
 143 {
 144         static int count = 0;
 145         count ++;
 146
 147         if (!getenv ("COUNT"))
 148                 return TRUE;
 149
 150         if (count == atoi (getenv ("COUNT"))) {
 151                 break_count ();
 152         }
 153
 154         if (count > atoi (getenv ("COUNT"))) {
 155                 return FALSE;
 156         }
 157
 158         return TRUE;
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 static inline void
 182 amd64_patch (unsigned char* code, gpointer target)
 183 {
 184         guint8 rex = 0;
 185
 186         /* Skip REX */
 187         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 188                 rex = code [0];
 189                 code += 1;
 190         }
 191
 192         if ((code [0] & 0xf8) == 0xb8) {
 193                 /* amd64_set_reg_template */
 194                 *(guint64*)(code + 1) = (guint64)target;
 195         }
 196         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 197                 /* mov 0(%rip), %dreg */
 198                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 199         }
 200         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 201                 /* call *<OFFSET>(%rip) */
 202                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 203         }
 204         else if ((code [0] == 0xe8)) {
 205                 /* call <DISP> */
 206                 gint64 disp = (guint8*)target - (guint8*)code;
 207                 g_assert (amd64_is_imm32 (disp));
 208                 x86_patch (code, (unsigned char*)target);
 209         }
 210         else
 211                 x86_patch (code, (unsigned char*)target);
 212 }
 213
 214 void
 215 mono_amd64_patch (unsigned char* code, gpointer target)
 216 {
 217         amd64_patch (code, target);
 218 }
 219
 220 typedef enum {
 221         ArgInIReg,
 222         ArgInFloatSSEReg,
 223         ArgInDoubleSSEReg,
 224         ArgOnStack,
 225         ArgValuetypeInReg,
 226         ArgValuetypeAddrInIReg,
 227         ArgNone /* only in pair_storage */
 228 } ArgStorage;
 229
 230 typedef struct {
 231         gint16 offset;
 232         gint8  reg;
 233         ArgStorage storage;
 234
 235         /* Only if storage == ArgValuetypeInReg */
 236         ArgStorage pair_storage [2];
 237         gint8 pair_regs [2];
 238 } ArgInfo;
 239
 240 typedef struct {
 241         int nargs;
 242         guint32 stack_usage;
 243         guint32 reg_usage;
 244         guint32 freg_usage;
 245         gboolean need_stack_align;
 246         ArgInfo ret;
 247         ArgInfo sig_cookie;
 248         ArgInfo args [1];
 249 } CallInfo;
 250
 251 #define DEBUG(a) if (cfg->verbose_level > 1) a
 252
 253 #define NEW_ICONST(cfg,dest,val) do {   \
 254                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 255                 (dest)->opcode = OP_ICONST;     \
 256                 (dest)->inst_c0 = (val);        \
 257                 (dest)->type = STACK_I4;        \
 258         } while (0)
 259
 260 #ifdef PLATFORM_WIN32
 261 #define PARAM_REGS 4
 262
 263 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 264
 265 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 266 #else
 267 #define PARAM_REGS 6
 268
 269 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 270
 271  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 272 #endif
 273
 274 static void inline
 275 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 276 {
 277     ainfo->offset = *stack_size;
 278
 279     if (*gr >= PARAM_REGS) {
 280                 ainfo->storage = ArgOnStack;
 281                 (*stack_size) += sizeof (gpointer);
 282     }
 283     else {
 284                 ainfo->storage = ArgInIReg;
 285                 ainfo->reg = param_regs [*gr];
 286                 (*gr) ++;
 287     }
 288 }
 289
 290 #ifdef PLATFORM_WIN32
 291 #define FLOAT_PARAM_REGS 4
 292 #else
 293 #define FLOAT_PARAM_REGS 8
 294 #endif
 295
 296 static void inline
 297 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= FLOAT_PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 /* A double register */
 307                 if (is_double)
 308                         ainfo->storage = ArgInDoubleSSEReg;
 309                 else
 310                         ainfo->storage = ArgInFloatSSEReg;
 311                 ainfo->reg = *gr;
 312                 (*gr) += 1;
 313     }
 314 }
 315
 316 typedef enum ArgumentClass {
 317         ARG_CLASS_NO_CLASS,
 318         ARG_CLASS_MEMORY,
 319         ARG_CLASS_INTEGER,
 320         ARG_CLASS_SSE
 321 } ArgumentClass;
 322
 323 static ArgumentClass
 324 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 325 {
 326         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 327         MonoType *ptype;
 328
 329         ptype = mono_type_get_underlying_type (type);
 330         switch (ptype->type) {
 331         case MONO_TYPE_BOOLEAN:
 332         case MONO_TYPE_CHAR:
 333         case MONO_TYPE_I1:
 334         case MONO_TYPE_U1:
 335         case MONO_TYPE_I2:
 336         case MONO_TYPE_U2:
 337         case MONO_TYPE_I4:
 338         case MONO_TYPE_U4:
 339         case MONO_TYPE_I:
 340         case MONO_TYPE_U:
 341         case MONO_TYPE_STRING:
 342         case MONO_TYPE_OBJECT:
 343         case MONO_TYPE_CLASS:
 344         case MONO_TYPE_SZARRAY:
 345         case MONO_TYPE_PTR:
 346         case MONO_TYPE_FNPTR:
 347         case MONO_TYPE_ARRAY:
 348         case MONO_TYPE_I8:
 349         case MONO_TYPE_U8:
 350                 class2 = ARG_CLASS_INTEGER;
 351                 break;
 352         case MONO_TYPE_R4:
 353         case MONO_TYPE_R8:
 354 #ifdef PLATFORM_WIN32
 355                 class2 = ARG_CLASS_INTEGER;
 356 #else
 357                 class2 = ARG_CLASS_SSE;
 358 #endif
 359                 break;
 360
 361         case MONO_TYPE_TYPEDBYREF:
 362                 g_assert_not_reached ();
 363
 364         case MONO_TYPE_GENERICINST:
 365                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 366                         class2 = ARG_CLASS_INTEGER;
 367                         break;
 368                 }
 369                 /* fall through */
 370         case MONO_TYPE_VALUETYPE: {
 371                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 372                 int i;
 373
 374                 for (i = 0; i < info->num_fields; ++i) {
 375                         class2 = class1;
 376                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 377                 }
 378                 break;
 379         }
 380         default:
 381                 g_assert_not_reached ();
 382         }
 383
 384         /* Merge */
 385         if (class1 == class2)
 386                 ;
 387         else if (class1 == ARG_CLASS_NO_CLASS)
 388                 class1 = class2;
 389         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 390                 class1 = ARG_CLASS_MEMORY;
 391         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 392                 class1 = ARG_CLASS_INTEGER;
 393         else
 394                 class1 = ARG_CLASS_SSE;
 395
 396         return class1;
 397 }
 398
 399 static void
 400 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 401                gboolean is_return,
 402                guint32 *gr, guint32 *fr, guint32 *stack_size)
 403 {
 404         guint32 size, quad, nquads, i;
 405         ArgumentClass args [2];
 406         MonoMarshalType *info;
 407         MonoClass *klass;
 408
 409         klass = mono_class_from_mono_type (type);
 410         if (sig->pinvoke)
 411                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 412         else
 413                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 414 #ifndef PLATFORM_WIN32
 415         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 416                 /* We pass and return vtypes of size 8 in a register */
 417         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 418 #else
 419         if (!sig->pinvoke) {
 420 #endif
 421                 /* Allways pass in memory */
 422                 ainfo->offset = *stack_size;
 423                 *stack_size += ALIGN_TO (size, 8);
 424                 ainfo->storage = ArgOnStack;
 425
 426                 return;
 427         }
 428
 429         /* FIXME: Handle structs smaller than 8 bytes */
 430         //if ((size % 8) != 0)
 431         //      NOT_IMPLEMENTED;
 432
 433         if (size > 8)
 434                 nquads = 2;
 435         else
 436                 nquads = 1;
 437
 438         if (!sig->pinvoke) {
 439                 /* Always pass in 1 or 2 integer registers */
 440                 args [0] = ARG_CLASS_INTEGER;
 441                 args [1] = ARG_CLASS_INTEGER;
 442                 /* Only the simplest cases are supported */
 443                 if (is_return && nquads != 1) {
 444                         args [0] = ARG_CLASS_MEMORY;
 445                         args [1] = ARG_CLASS_MEMORY;
 446                 }
 447         } else {
 448                 /*
 449                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 450                  * The X87 and SSEUP stuff is left out since there are no such types in
 451                  * the CLR.
 452                  */
 453                 info = mono_marshal_load_type_info (klass);
 454                 g_assert (info);
 455
 456 #ifndef PLATFORM_WIN32
 457                 if (info->native_size > 16) {
 458                         ainfo->offset = *stack_size;
 459                         *stack_size += ALIGN_TO (info->native_size, 8);
 460                         ainfo->storage = ArgOnStack;
 461
 462                         return;
 463                 }
 464 #else
 465                 switch (info->native_size) {
 466                 case 1: case 2: case 4: case 8:
 467                         break;
 468                 default:
 469                         if (is_return) {
 470                                 ainfo->storage = ArgOnStack;
 471                                 ainfo->offset = *stack_size;
 472                                 *stack_size += ALIGN_TO (info->native_size, 8);
 473                         }
 474                         else {
 475                                 ainfo->storage = ArgValuetypeAddrInIReg;
 476
 477                                 if (*gr < PARAM_REGS) {
 478                                         ainfo->pair_storage [0] = ArgInIReg;
 479                                         ainfo->pair_regs [0] = param_regs [*gr];
 480                                         (*gr) ++;
 481                                 }
 482                                 else {
 483                                         ainfo->pair_storage [0] = ArgOnStack;
 484                                         ainfo->offset = *stack_size;
 485                                         *stack_size += 8;
 486                                 }
 487                         }
 488
 489                         return;
 490                 }
 491 #endif
 492
 493                 args [0] = ARG_CLASS_NO_CLASS;
 494                 args [1] = ARG_CLASS_NO_CLASS;
 495                 for (quad = 0; quad < nquads; ++quad) {
 496                         int size;
 497                         guint32 align;
 498                         ArgumentClass class1;
 499
 500                         if (info->num_fields == 0)
 501                                 class1 = ARG_CLASS_MEMORY;
 502                         else
 503                                 class1 = ARG_CLASS_NO_CLASS;
 504                         for (i = 0; i < info->num_fields; ++i) {
 505                                 size = mono_marshal_type_size (info->fields [i].field->type,
 506                                                                                            info->fields [i].mspec,
 507                                                                                            &align, TRUE, klass->unicode);
 508                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 509                                         /* Unaligned field */
 510                                         NOT_IMPLEMENTED;
 511                                 }
 512
 513                                 /* Skip fields in other quad */
 514                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 515                                         continue;
 516                                 if ((quad == 1) && (info->fields [i].offset < 8))
 517                                         continue;
 518
 519                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 520                         }
 521                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 522                         args [quad] = class1;
 523                 }
 524         }
 525
 526         /* Post merger cleanup */
 527         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 528                 args [0] = args [1] = ARG_CLASS_MEMORY;
 529
 530         /* Allocate registers */
 531         {
 532                 int orig_gr = *gr;
 533                 int orig_fr = *fr;
 534
 535                 ainfo->storage = ArgValuetypeInReg;
 536                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 537                 for (quad = 0; quad < nquads; ++quad) {
 538                         switch (args [quad]) {
 539                         case ARG_CLASS_INTEGER:
 540                                 if (*gr >= PARAM_REGS)
 541                                         args [quad] = ARG_CLASS_MEMORY;
 542                                 else {
 543                                         ainfo->pair_storage [quad] = ArgInIReg;
 544                                         if (is_return)
 545                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 546                                         else
 547                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 548                                         (*gr) ++;
 549                                 }
 550                                 break;
 551                         case ARG_CLASS_SSE:
 552                                 if (*fr >= FLOAT_PARAM_REGS)
 553                                         args [quad] = ARG_CLASS_MEMORY;
 554                                 else {
 555                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 556                                         ainfo->pair_regs [quad] = *fr;
 557                                         (*fr) ++;
 558                                 }
 559                                 break;
 560                         case ARG_CLASS_MEMORY:
 561                                 break;
 562                         default:
 563                                 g_assert_not_reached ();
 564                         }
 565                 }
 566
 567                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 568                         /* Revert possible register assignments */
 569                         *gr = orig_gr;
 570                         *fr = orig_fr;
 571
 572                         ainfo->offset = *stack_size;
 573                         if (sig->pinvoke)
 574                                 *stack_size += ALIGN_TO (info->native_size, 8);
 575                         else
 576                                 *stack_size += nquads * sizeof (gpointer);
 577                         ainfo->storage = ArgOnStack;
 578                 }
 579         }
 580 }
 581
 582 /*
 583  * get_call_info:
 584  *
 585  *  Obtain information about a call according to the calling convention.
 586  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 587  * Draft Version 0.23" document for more information.
 588  */
 589 static CallInfo*
 590 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 591 {
 592         guint32 i, gr, fr;
 593         MonoType *ret_type;
 594         int n = sig->hasthis + sig->param_count;
 595         guint32 stack_size = 0;
 596         CallInfo *cinfo;
 597
 598         if (mp)
 599                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 600         else
 601                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 602
 603         gr = 0;
 604         fr = 0;
 605
 606         /* return value */
 607         {
 608                 ret_type = mono_type_get_underlying_type (sig->ret);
 609                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 610                 switch (ret_type->type) {
 611                 case MONO_TYPE_BOOLEAN:
 612                 case MONO_TYPE_I1:
 613                 case MONO_TYPE_U1:
 614                 case MONO_TYPE_I2:
 615                 case MONO_TYPE_U2:
 616                 case MONO_TYPE_CHAR:
 617                 case MONO_TYPE_I4:
 618                 case MONO_TYPE_U4:
 619                 case MONO_TYPE_I:
 620                 case MONO_TYPE_U:
 621                 case MONO_TYPE_PTR:
 622                 case MONO_TYPE_FNPTR:
 623                 case MONO_TYPE_CLASS:
 624                 case MONO_TYPE_OBJECT:
 625                 case MONO_TYPE_SZARRAY:
 626                 case MONO_TYPE_ARRAY:
 627                 case MONO_TYPE_STRING:
 628                         cinfo->ret.storage = ArgInIReg;
 629                         cinfo->ret.reg = AMD64_RAX;
 630                         break;
 631                 case MONO_TYPE_U8:
 632                 case MONO_TYPE_I8:
 633                         cinfo->ret.storage = ArgInIReg;
 634                         cinfo->ret.reg = AMD64_RAX;
 635                         break;
 636                 case MONO_TYPE_R4:
 637                         cinfo->ret.storage = ArgInFloatSSEReg;
 638                         cinfo->ret.reg = AMD64_XMM0;
 639                         break;
 640                 case MONO_TYPE_R8:
 641                         cinfo->ret.storage = ArgInDoubleSSEReg;
 642                         cinfo->ret.reg = AMD64_XMM0;
 643                         break;
 644                 case MONO_TYPE_GENERICINST:
 645                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 646                                 cinfo->ret.storage = ArgInIReg;
 647                                 cinfo->ret.reg = AMD64_RAX;
 648                                 break;
 649                         }
 650                         /* fall through */
 651                 case MONO_TYPE_VALUETYPE: {
 652                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 653
 654                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 655                         if (cinfo->ret.storage == ArgOnStack)
 656                                 /* The caller passes the address where the value is stored */
 657                                 add_general (&gr, &stack_size, &cinfo->ret);
 658                         break;
 659                 }
 660                 case MONO_TYPE_TYPEDBYREF:
 661                         /* Same as a valuetype with size 24 */
 662                         add_general (&gr, &stack_size, &cinfo->ret);
 663                         ;
 664                         break;
 665                 case MONO_TYPE_VOID:
 666                         break;
 667                 default:
 668                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 669                 }
 670         }
 671
 672         /* this */
 673         if (sig->hasthis)
 674                 add_general (&gr, &stack_size, cinfo->args + 0);
 675
 676         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 677                 gr = PARAM_REGS;
 678                 fr = FLOAT_PARAM_REGS;
 679
 680                 /* Emit the signature cookie just before the implicit arguments */
 681                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 682         }
 683
 684         for (i = 0; i < sig->param_count; ++i) {
 685                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 686                 MonoType *ptype;
 687
 688 #ifdef PLATFORM_WIN32
 689                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 690                 if (gr > fr)
 691                         fr = gr;
 692                 else if (fr > gr)
 693                         gr = fr;
 694 #endif
 695
 696                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 697                         /* We allways pass the sig cookie on the stack for simplicity */
 698                         /*
 699                          * Prevent implicit arguments + the sig cookie from being passed
 700                          * in registers.
 701                          */
 702                         gr = PARAM_REGS;
 703                         fr = FLOAT_PARAM_REGS;
 704
 705                         /* Emit the signature cookie just before the implicit arguments */
 706                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 707                 }
 708
 709                 if (sig->params [i]->byref) {
 710                         add_general (&gr, &stack_size, ainfo);
 711                         continue;
 712                 }
 713                 ptype = mono_type_get_underlying_type (sig->params [i]);
 714                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 715                 switch (ptype->type) {
 716                 case MONO_TYPE_BOOLEAN:
 717                 case MONO_TYPE_I1:
 718                 case MONO_TYPE_U1:
 719                         add_general (&gr, &stack_size, ainfo);
 720                         break;
 721                 case MONO_TYPE_I2:
 722                 case MONO_TYPE_U2:
 723                 case MONO_TYPE_CHAR:
 724                         add_general (&gr, &stack_size, ainfo);
 725                         break;
 726                 case MONO_TYPE_I4:
 727                 case MONO_TYPE_U4:
 728                         add_general (&gr, &stack_size, ainfo);
 729                         break;
 730                 case MONO_TYPE_I:
 731                 case MONO_TYPE_U:
 732                 case MONO_TYPE_PTR:
 733                 case MONO_TYPE_FNPTR:
 734                 case MONO_TYPE_CLASS:
 735                 case MONO_TYPE_OBJECT:
 736                 case MONO_TYPE_STRING:
 737                 case MONO_TYPE_SZARRAY:
 738                 case MONO_TYPE_ARRAY:
 739                         add_general (&gr, &stack_size, ainfo);
 740                         break;
 741                 case MONO_TYPE_GENERICINST:
 742                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 743                                 add_general (&gr, &stack_size, ainfo);
 744                                 break;
 745                         }
 746                         /* fall through */
 747                 case MONO_TYPE_VALUETYPE:
 748                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 749                         break;
 750                 case MONO_TYPE_TYPEDBYREF:
 751 #ifdef PLATFORM_WIN32
 752                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 753 #else
 754                         stack_size += sizeof (MonoTypedRef);
 755                         ainfo->storage = ArgOnStack;
 756 #endif
 757                         break;
 758                 case MONO_TYPE_U8:
 759                 case MONO_TYPE_I8:
 760                         add_general (&gr, &stack_size, ainfo);
 761                         break;
 762                 case MONO_TYPE_R4:
 763                         add_float (&fr, &stack_size, ainfo, FALSE);
 764                         break;
 765                 case MONO_TYPE_R8:
 766                         add_float (&fr, &stack_size, ainfo, TRUE);
 767                         break;
 768                 default:
 769                         g_assert_not_reached ();
 770                 }
 771         }
 772
 773         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 774                 gr = PARAM_REGS;
 775                 fr = FLOAT_PARAM_REGS;
 776
 777                 /* Emit the signature cookie just before the implicit arguments */
 778                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 779         }
 780
 781 #ifdef PLATFORM_WIN32
 782         // There always is 32 bytes reserved on the stack when calling on Winx64
 783         stack_size += 0x20;
 784 #endif
 785
 786         if (stack_size & 0x8) {
 787                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 788                 cinfo->need_stack_align = TRUE;
 789                 stack_size += 8;
 790         }
 791
 792         cinfo->stack_usage = stack_size;
 793         cinfo->reg_usage = gr;
 794         cinfo->freg_usage = fr;
 795         return cinfo;
 796 }
 797
 798 /*
 799  * mono_arch_get_argument_info:
 800  * @csig:  a method signature
 801  * @param_count: the number of parameters to consider
 802  * @arg_info: an array to store the result infos
 803  *
 804  * Gathers information on parameters such as size, alignment and
 805  * padding. arg_info should be large enought to hold param_count + 1 entries.
 806  *
 807  * Returns the size of the argument area on the stack.
 808  */
 809 int
 810 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 811 {
 812         int k;
 813         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 814         guint32 args_size = cinfo->stack_usage;
 815
 816         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 817         if (csig->hasthis) {
 818                 arg_info [0].offset = 0;
 819         }
 820
 821         for (k = 0; k < param_count; k++) {
 822                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 823                 /* FIXME: */
 824                 arg_info [k + 1].size = 0;
 825         }
 826
 827         g_free (cinfo);
 828
 829         return args_size;
 830 }
 831
 832 static int
 833 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 834 {
 835 #ifndef _MSC_VER
 836         __asm__ __volatile__ ("cpuid"
 837                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 838                 : "a" (id));
 839 #else
 840         int info[4];
 841         __cpuid(info, id);
 842         *p_eax = info[0];
 843         *p_ebx = info[1];
 844         *p_ecx = info[2];
 845         *p_edx = info[3];
 846 #endif
 847         return 1;
 848 }
 849
 850 /*
 851  * Initialize the cpu to execute managed code.
 852  */
 853 void
 854 mono_arch_cpu_init (void)
 855 {
 856 #ifndef _MSC_VER
 857         guint16 fpcw;
 858
 859         /* spec compliance requires running with double precision */
 860         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 861         fpcw &= ~X86_FPCW_PRECC_MASK;
 862         fpcw |= X86_FPCW_PREC_DOUBLE;
 863         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 864         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 865 #else
 866         /* TODO: This is crashing on Win64 right now.
 867         * _control87 (_PC_53, MCW_PC);
 868         */
 869 #endif
 870 }
 871
 872 /*
 873  * Initialize architecture specific code.
 874  */
 875 void
 876 mono_arch_init (void)
 877 {
 878         InitializeCriticalSection (&mini_arch_mutex);
 879 }
 880
 881 /*
 882  * Cleanup architecture specific code.
 883  */
 884 void
 885 mono_arch_cleanup (void)
 886 {
 887         DeleteCriticalSection (&mini_arch_mutex);
 888 }
 889
 890 /*
 891  * This function returns the optimizations supported on this cpu.
 892  */
 893 guint32
 894 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 895 {
 896         int eax, ebx, ecx, edx;
 897         guint32 opts = 0;
 898
 899         /* FIXME: AMD64 */
 900
 901         *exclude_mask = 0;
 902         /* Feature Flags function, flags returned in EDX. */
 903         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 904                 if (edx & (1 << 15)) {
 905                         opts |= MONO_OPT_CMOV;
 906                         if (edx & 1)
 907                                 opts |= MONO_OPT_FCMOV;
 908                         else
 909                                 *exclude_mask |= MONO_OPT_FCMOV;
 910                 } else
 911                         *exclude_mask |= MONO_OPT_CMOV;
 912         }
 913 #ifdef PLATFORM_WIN32
 914         /* FIXME */
 915         *exclude_mask |= (MONO_OPT_PEEPHOLE | MONO_OPT_BRANCH);
 916 #endif
 917         return opts;
 918 }
 919
 920 GList *
 921 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 922 {
 923         GList *vars = NULL;
 924         int i;
 925
 926         for (i = 0; i < cfg->num_varinfo; i++) {
 927                 MonoInst *ins = cfg->varinfo [i];
 928                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 929
 930                 /* unused vars */
 931                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 932                         continue;
 933
 934                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 935                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 936                         continue;
 937
 938                 if (mono_is_regsize_var (ins->inst_vtype)) {
 939                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 940                         g_assert (i == vmv->idx);
 941                         vars = g_list_prepend (vars, vmv);
 942                 }
 943         }
 944
 945         vars = mono_varlist_sort (cfg, vars, 0);
 946
 947         return vars;
 948 }
 949
 950 /**
 951  * mono_arch_compute_omit_fp:
 952  *
 953  *   Determine whenever the frame pointer can be eliminated.
 954  */
 955 static void
 956 mono_arch_compute_omit_fp (MonoCompile *cfg)
 957 {
 958         MonoMethodSignature *sig;
 959         MonoMethodHeader *header;
 960         int i, locals_size;
 961         CallInfo *cinfo;
 962
 963         if (cfg->arch.omit_fp_computed)
 964                 return;
 965
 966         header = mono_method_get_header (cfg->method);
 967
 968         sig = mono_method_signature (cfg->method);
 969
 970         if (!cfg->arch.cinfo)
 971                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 972         cinfo = cfg->arch.cinfo;
 973
 974         /*
 975          * FIXME: Remove some of the restrictions.
 976          */
 977         cfg->arch.omit_fp = TRUE;
 978         cfg->arch.omit_fp_computed = TRUE;
 979
 980         if (cfg->disable_omit_fp)
 981                 cfg->arch.omit_fp = FALSE;
 982
 983         if (!debug_omit_fp ())
 984                 cfg->arch.omit_fp = FALSE;
 985         /*
 986         if (cfg->method->save_lmf)
 987                 cfg->arch.omit_fp = FALSE;
 988         */
 989         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 990                 cfg->arch.omit_fp = FALSE;
 991         if (header->num_clauses)
 992                 cfg->arch.omit_fp = FALSE;
 993         if (cfg->param_area)
 994                 cfg->arch.omit_fp = FALSE;
 995         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 996                 cfg->arch.omit_fp = FALSE;
 997         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 998                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 999                 cfg->arch.omit_fp = FALSE;
1000         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1001                 ArgInfo *ainfo = &cinfo->args [i];
1002
1003                 if (ainfo->storage == ArgOnStack) {
1004                         /*
1005                          * The stack offset can only be determined when the frame
1006                          * size is known.
1007                          */
1008                         cfg->arch.omit_fp = FALSE;
1009                 }
1010         }
1011
1012         locals_size = 0;
1013         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1014                 MonoInst *ins = cfg->varinfo [i];
1015                 int ialign;
1016
1017                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1018         }
1019
1020         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1021                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1022                 cfg->arch.omit_fp = FALSE;
1023         }
1024 }
1025
1026 GList *
1027 mono_arch_get_global_int_regs (MonoCompile *cfg)
1028 {
1029         GList *regs = NULL;
1030
1031         mono_arch_compute_omit_fp (cfg);
1032
1033         if (cfg->globalra) {
1034                 if (cfg->arch.omit_fp)
1035                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1036
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1042
1043                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1051         } else {
1052                 if (cfg->arch.omit_fp)
1053                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1054
1055                 /* We use the callee saved registers for global allocation */
1056                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1057                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1058                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1059                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1060                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1061         }
1062
1063         return regs;
1064 }
1065
1066 GList*
1067 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1068 {
1069         GList *regs = NULL;
1070         int i;
1071
1072         /* All XMM registers */
1073         for (i = 0; i < 16; ++i)
1074                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1075
1076         return regs;
1077 }
1078
1079 GList*
1080 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1081 {
1082         static GList *r = NULL;
1083
1084         if (r == NULL) {
1085                 GList *regs = NULL;
1086
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1093
1094                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1099                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1101                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1102
1103                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1104         }
1105
1106         return r;
1107 }
1108
1109 GList*
1110 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1111 {
1112         int i;
1113         static GList *r = NULL;
1114
1115         if (r == NULL) {
1116                 GList *regs = NULL;
1117
1118                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1119                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1120
1121                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1122         }
1123
1124         return r;
1125 }
1126
1127 /*
1128  * mono_arch_regalloc_cost:
1129  *
1130  *  Return the cost, in number of memory references, of the action of
1131  * allocating the variable VMV into a register during global register
1132  * allocation.
1133  */
1134 guint32
1135 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1136 {
1137         MonoInst *ins = cfg->varinfo [vmv->idx];
1138
1139         if (cfg->method->save_lmf)
1140                 /* The register is already saved */
1141                 /* substract 1 for the invisible store in the prolog */
1142                 return (ins->opcode == OP_ARG) ? 0 : 1;
1143         else
1144                 /* push+pop */
1145                 return (ins->opcode == OP_ARG) ? 1 : 2;
1146 }
1147
1148 /*
1149  * mono_arch_fill_argument_info:
1150  *
1151  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1152  * of the method.
1153  */
1154 void
1155 mono_arch_fill_argument_info (MonoCompile *cfg)
1156 {
1157         MonoMethodSignature *sig;
1158         MonoMethodHeader *header;
1159         MonoInst *ins;
1160         int i;
1161         CallInfo *cinfo;
1162
1163         header = mono_method_get_header (cfg->method);
1164
1165         sig = mono_method_signature (cfg->method);
1166
1167         cinfo = cfg->arch.cinfo;
1168
1169         /*
1170          * Contrary to mono_arch_allocate_vars (), the information should describe
1171          * where the arguments are at the beginning of the method, not where they can be
1172          * accessed during the execution of the method. The later makes no sense for the
1173          * global register allocator, since a variable can be in more than one location.
1174          */
1175         if (sig->ret->type != MONO_TYPE_VOID) {
1176                 switch (cinfo->ret.storage) {
1177                 case ArgInIReg:
1178                 case ArgInFloatSSEReg:
1179                 case ArgInDoubleSSEReg:
1180                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1181                                 cfg->vret_addr->opcode = OP_REGVAR;
1182                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1183                         }
1184                         else {
1185                                 cfg->ret->opcode = OP_REGVAR;
1186                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1187                         }
1188                         break;
1189                 case ArgValuetypeInReg:
1190                         cfg->ret->opcode = OP_REGOFFSET;
1191                         cfg->ret->inst_basereg = -1;
1192                         cfg->ret->inst_offset = -1;
1193                         break;
1194                 default:
1195                         g_assert_not_reached ();
1196                 }
1197         }
1198
1199         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1200                 ArgInfo *ainfo = &cinfo->args [i];
1201                 MonoType *arg_type;
1202
1203                 ins = cfg->args [i];
1204
1205                 if (sig->hasthis && (i == 0))
1206                         arg_type = &mono_defaults.object_class->byval_arg;
1207                 else
1208                         arg_type = sig->params [i - sig->hasthis];
1209
1210                 switch (ainfo->storage) {
1211                 case ArgInIReg:
1212                 case ArgInFloatSSEReg:
1213                 case ArgInDoubleSSEReg:
1214                         ins->opcode = OP_REGVAR;
1215                         ins->inst_c0 = ainfo->reg;
1216                         break;
1217                 case ArgOnStack:
1218                         ins->opcode = OP_REGOFFSET;
1219                         ins->inst_basereg = -1;
1220                         ins->inst_offset = -1;
1221                         break;
1222                 case ArgValuetypeInReg:
1223                         /* Dummy */
1224                         ins->opcode = OP_NOP;
1225                         break;
1226                 default:
1227                         g_assert_not_reached ();
1228                 }
1229         }
1230 }
1231
1232 void
1233 mono_arch_allocate_vars (MonoCompile *cfg)
1234 {
1235         MonoMethodSignature *sig;
1236         MonoMethodHeader *header;
1237         MonoInst *ins;
1238         int i, offset;
1239         guint32 locals_stack_size, locals_stack_align;
1240         gint32 *offsets;
1241         CallInfo *cinfo;
1242
1243         header = mono_method_get_header (cfg->method);
1244
1245         sig = mono_method_signature (cfg->method);
1246
1247         cinfo = cfg->arch.cinfo;
1248
1249         mono_arch_compute_omit_fp (cfg);
1250
1251         /*
1252          * We use the ABI calling conventions for managed code as well.
1253          * Exception: valuetypes are never passed or returned in registers.
1254          */
1255
1256         if (cfg->arch.omit_fp) {
1257                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1258                 cfg->frame_reg = AMD64_RSP;
1259                 offset = 0;
1260         } else {
1261                 /* Locals are allocated backwards from %fp */
1262                 cfg->frame_reg = AMD64_RBP;
1263                 offset = 0;
1264         }
1265
1266         if (cfg->method->save_lmf) {
1267                 /* Reserve stack space for saving LMF */
1268                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1269                 g_assert (offset == 0);
1270                 if (cfg->arch.omit_fp) {
1271                         cfg->arch.lmf_offset = offset;
1272                         offset += sizeof (MonoLMF);
1273                 }
1274                 else {
1275                         offset += sizeof (MonoLMF);
1276                         cfg->arch.lmf_offset = -offset;
1277                 }
1278         } else {
1279                 if (cfg->arch.omit_fp)
1280                         cfg->arch.reg_save_area_offset = offset;
1281                 /* Reserve space for caller saved registers */
1282                 for (i = 0; i < AMD64_NREG; ++i)
1283                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1284                                 offset += sizeof (gpointer);
1285                         }
1286         }
1287
1288         if (sig->ret->type != MONO_TYPE_VOID) {
1289                 switch (cinfo->ret.storage) {
1290                 case ArgInIReg:
1291                 case ArgInFloatSSEReg:
1292                 case ArgInDoubleSSEReg:
1293                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1294                                 if (cfg->globalra) {
1295                                         cfg->vret_addr->opcode = OP_REGVAR;
1296                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1297                                 } else {
1298                                         /* The register is volatile */
1299                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1300                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1301                                         if (cfg->arch.omit_fp) {
1302                                                 cfg->vret_addr->inst_offset = offset;
1303                                                 offset += 8;
1304                                         } else {
1305                                                 offset += 8;
1306                                                 cfg->vret_addr->inst_offset = -offset;
1307                                         }
1308                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1309                                                 printf ("vret_addr =");
1310                                                 mono_print_ins (cfg->vret_addr);
1311                                         }
1312                                 }
1313                         }
1314                         else {
1315                                 cfg->ret->opcode = OP_REGVAR;
1316                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1317                         }
1318                         break;
1319                 case ArgValuetypeInReg:
1320                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1321                         cfg->ret->opcode = OP_REGOFFSET;
1322                         cfg->ret->inst_basereg = cfg->frame_reg;
1323                         if (cfg->arch.omit_fp) {
1324                                 cfg->ret->inst_offset = offset;
1325                                 offset += 16;
1326                         } else {
1327                                 offset += 16;
1328                                 cfg->ret->inst_offset = - offset;
1329                         }
1330                         break;
1331                 default:
1332                         g_assert_not_reached ();
1333                 }
1334                 if (!cfg->globalra)
1335                         cfg->ret->dreg = cfg->ret->inst_c0;
1336         }
1337
1338         /* Allocate locals */
1339         if (!cfg->globalra) {
1340                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1341                 if (locals_stack_align) {
1342                         offset += (locals_stack_align - 1);
1343                         offset &= ~(locals_stack_align - 1);
1344                 }
1345                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1346                         if (offsets [i] != -1) {
1347                                 MonoInst *ins = cfg->varinfo [i];
1348                                 ins->opcode = OP_REGOFFSET;
1349                                 ins->inst_basereg = cfg->frame_reg;
1350                                 if (cfg->arch.omit_fp)
1351                                         ins->inst_offset = (offset + offsets [i]);
1352                                 else
1353                                         ins->inst_offset = - (offset + offsets [i]);
1354                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1355                         }
1356                 }
1357                 offset += locals_stack_size;
1358         }
1359
1360         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1361                 g_assert (!cfg->arch.omit_fp);
1362                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1363                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1364         }
1365
1366         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1367                 ins = cfg->args [i];
1368                 if (ins->opcode != OP_REGVAR) {
1369                         ArgInfo *ainfo = &cinfo->args [i];
1370                         gboolean inreg = TRUE;
1371                         MonoType *arg_type;
1372
1373                         if (sig->hasthis && (i == 0))
1374                                 arg_type = &mono_defaults.object_class->byval_arg;
1375                         else
1376                                 arg_type = sig->params [i - sig->hasthis];
1377
1378                         if (cfg->globalra) {
1379                                 /* The new allocator needs info about the original locations of the arguments */
1380                                 switch (ainfo->storage) {
1381                                 case ArgInIReg:
1382                                 case ArgInFloatSSEReg:
1383                                 case ArgInDoubleSSEReg:
1384                                         ins->opcode = OP_REGVAR;
1385                                         ins->inst_c0 = ainfo->reg;
1386                                         break;
1387                                 case ArgOnStack:
1388                                         g_assert (!cfg->arch.omit_fp);
1389                                         ins->opcode = OP_REGOFFSET;
1390                                         ins->inst_basereg = cfg->frame_reg;
1391                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1392                                         break;
1393                                 case ArgValuetypeInReg:
1394                                         ins->opcode = OP_REGOFFSET;
1395                                         ins->inst_basereg = cfg->frame_reg;
1396                                         /* These arguments are saved to the stack in the prolog */
1397                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1398                                         if (cfg->arch.omit_fp) {
1399                                                 ins->inst_offset = offset;
1400                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1401                                         } else {
1402                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1403                                                 ins->inst_offset = - offset;
1404                                         }
1405                                         break;
1406                                 default:
1407                                         g_assert_not_reached ();
1408                                 }
1409
1410                                 continue;
1411                         }
1412
1413                         /* FIXME: Allocate volatile arguments to registers */
1414                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1415                                 inreg = FALSE;
1416
1417                         /*
1418                          * Under AMD64, all registers used to pass arguments to functions
1419                          * are volatile across calls.
1420                          * FIXME: Optimize this.
1421                          */
1422                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1423                                 inreg = FALSE;
1424
1425                         ins->opcode = OP_REGOFFSET;
1426
1427                         switch (ainfo->storage) {
1428                         case ArgInIReg:
1429                         case ArgInFloatSSEReg:
1430                         case ArgInDoubleSSEReg:
1431                                 if (inreg) {
1432                                         ins->opcode = OP_REGVAR;
1433                                         ins->dreg = ainfo->reg;
1434                                 }
1435                                 break;
1436                         case ArgOnStack:
1437                                 g_assert (!cfg->arch.omit_fp);
1438                                 ins->opcode = OP_REGOFFSET;
1439                                 ins->inst_basereg = cfg->frame_reg;
1440                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1441                                 break;
1442                         case ArgValuetypeInReg:
1443                                 break;
1444                         case ArgValuetypeAddrInIReg: {
1445                                 MonoInst *indir;
1446                                 g_assert (!cfg->arch.omit_fp);
1447
1448                                 MONO_INST_NEW (cfg, indir, 0);
1449                                 indir->opcode = OP_REGOFFSET;
1450                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1451                                         indir->inst_basereg = cfg->frame_reg;
1452                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1453                                         offset += (sizeof (gpointer));
1454                                         indir->inst_offset = - offset;
1455                                 }
1456                                 else {
1457                                         indir->inst_basereg = cfg->frame_reg;
1458                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1459                                 }
1460
1461                                 ins->opcode = OP_VTARG_ADDR;
1462                                 ins->inst_left = indir;
1463
1464                                 break;
1465                         }
1466                         default:
1467                                 NOT_IMPLEMENTED;
1468                         }
1469
1470                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1471                                 ins->opcode = OP_REGOFFSET;
1472                                 ins->inst_basereg = cfg->frame_reg;
1473                                 /* These arguments are saved to the stack in the prolog */
1474                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1475                                 if (cfg->arch.omit_fp) {
1476                                         ins->inst_offset = offset;
1477                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1478                                 } else {
1479                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1480                                         ins->inst_offset = - offset;
1481                                 }
1482                         }
1483                 }
1484         }
1485
1486         cfg->stack_offset = offset;
1487 }
1488
1489 void
1490 mono_arch_create_vars (MonoCompile *cfg)
1491 {
1492         MonoMethodSignature *sig;
1493         CallInfo *cinfo;
1494
1495         sig = mono_method_signature (cfg->method);
1496
1497         if (!cfg->arch.cinfo)
1498                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1499         cinfo = cfg->arch.cinfo;
1500
1501         if (cinfo->ret.storage == ArgValuetypeInReg)
1502                 cfg->ret_var_is_local = TRUE;
1503
1504         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1505                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1506                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1507                         printf ("vret_addr = ");
1508                         mono_print_ins (cfg->vret_addr);
1509                 }
1510         }
1511 }
1512
1513 static void
1514 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1515 {
1516         switch (storage) {
1517         case ArgInIReg:
1518                 arg->opcode = OP_OUTARG_REG;
1519                 arg->inst_left = tree;
1520                 arg->inst_call = call;
1521                 arg->backend.reg3 = reg;
1522                 break;
1523         case ArgInFloatSSEReg:
1524                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1525                 arg->inst_left = tree;
1526                 arg->inst_call = call;
1527                 arg->backend.reg3 = reg;
1528                 break;
1529         case ArgInDoubleSSEReg:
1530                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1531                 arg->inst_left = tree;
1532                 arg->inst_call = call;
1533                 arg->backend.reg3 = reg;
1534                 break;
1535         default:
1536                 g_assert_not_reached ();
1537         }
1538 }
1539
1540 static void
1541 add_outarg_reg2 (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1542 {
1543         MonoInst *ins;
1544
1545         switch (storage) {
1546         case ArgInIReg:
1547                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1548                 ins->dreg = mono_alloc_ireg (cfg);
1549                 ins->sreg1 = tree->dreg;
1550                 MONO_ADD_INS (cfg->cbb, ins);
1551                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1552                 break;
1553         case ArgInFloatSSEReg:
1554                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1555                 ins->dreg = mono_alloc_freg (cfg);
1556                 ins->sreg1 = tree->dreg;
1557                 MONO_ADD_INS (cfg->cbb, ins);
1558
1559                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1560                 break;
1561         case ArgInDoubleSSEReg:
1562                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1563                 ins->dreg = mono_alloc_freg (cfg);
1564                 ins->sreg1 = tree->dreg;
1565                 MONO_ADD_INS (cfg->cbb, ins);
1566
1567                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1568
1569                 break;
1570         default:
1571                 g_assert_not_reached ();
1572         }
1573 }
1574
1575 static int
1576 arg_storage_to_ldind (ArgStorage storage)
1577 {
1578         switch (storage) {
1579         case ArgInIReg:
1580                 return CEE_LDIND_I;
1581         case ArgInDoubleSSEReg:
1582                 return CEE_LDIND_R8;
1583         case ArgInFloatSSEReg:
1584                 return CEE_LDIND_R4;
1585         default:
1586                 g_assert_not_reached ();
1587         }
1588
1589         return -1;
1590 }
1591
1592 static int
1593 arg_storage_to_load_membase (ArgStorage storage)
1594 {
1595         switch (storage) {
1596         case ArgInIReg:
1597                 return OP_LOAD_MEMBASE;
1598         case ArgInDoubleSSEReg:
1599                 return OP_LOADR8_MEMBASE;
1600         case ArgInFloatSSEReg:
1601                 return OP_LOADR4_MEMBASE;
1602         default:
1603                 g_assert_not_reached ();
1604         }
1605
1606         return -1;
1607 }
1608
1609 static void
1610 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1611 {
1612         MonoInst *arg;
1613         MonoMethodSignature *tmp_sig;
1614         MonoInst *sig_arg;
1615
1616         /* FIXME: Add support for signature tokens to AOT */
1617         cfg->disable_aot = TRUE;
1618
1619         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1620
1621         /*
1622          * mono_ArgIterator_Setup assumes the signature cookie is
1623          * passed first and all the arguments which were before it are
1624          * passed on the stack after the signature. So compensate by
1625          * passing a different signature.
1626          */
1627         tmp_sig = mono_metadata_signature_dup (call->signature);
1628         tmp_sig->param_count -= call->signature->sentinelpos;
1629         tmp_sig->sentinelpos = 0;
1630         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1631
1632         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1633         sig_arg->inst_p0 = tmp_sig;
1634
1635         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1636         arg->inst_left = sig_arg;
1637         arg->type = STACK_PTR;
1638
1639         /* prepend, so they get reversed */
1640         arg->next = call->out_args;
1641         call->out_args = arg;
1642 }
1643
1644 /*
1645  * take the arguments and generate the arch-specific
1646  * instructions to properly call the function in call.
1647  * This includes pushing, moving arguments to the right register
1648  * etc.
1649  */
1650 MonoCallInst*
1651 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1652         MonoInst *arg, *in;
1653         MonoMethodSignature *sig;
1654         int i, n, stack_size;
1655         CallInfo *cinfo;
1656         ArgInfo *ainfo;
1657
1658         stack_size = 0;
1659
1660         sig = call->signature;
1661         n = sig->param_count + sig->hasthis;
1662
1663         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1664
1665         if (cfg->method->save_lmf) {
1666                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1667                 arg->next = call->out_args;
1668                 call->out_args = arg;
1669         }
1670
1671         for (i = 0; i < n; ++i) {
1672                 ainfo = cinfo->args + i;
1673
1674                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1675                         /* Emit the signature cookie just before the implicit arguments */
1676                         emit_sig_cookie (cfg, call, cinfo);
1677                 }
1678
1679                 if (is_virtual && i == 0) {
1680                         /* the argument will be attached to the call instruction */
1681                         in = call->args [i];
1682                 } else {
1683                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1684                         in = call->args [i];
1685                         arg->cil_code = in->cil_code;
1686                         arg->inst_left = in;
1687                         arg->type = in->type;
1688                         /* prepend, so they get reversed */
1689                         arg->next = call->out_args;
1690                         call->out_args = arg;
1691 #if 0
1692                         if (!cinfo->stack_usage)
1693                                 /* Keep the assignments to the arg registers in order if possible */
1694                                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1695                         else
1696                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1697 #endif
1698
1699                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1700                                 guint32 align;
1701                                 guint32 size;
1702
1703                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1704                                         size = sizeof (MonoTypedRef);
1705                                         align = sizeof (gpointer);
1706                                 }
1707                                 else
1708                                 if (sig->pinvoke)
1709                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1710                                 else {
1711                                         /*
1712                                          * Other backends use mini_type_stack_size (), but that
1713                                          * aligns the size to 8, which is larger than the size of
1714                                          * the source, leading to reads of invalid memory if the
1715                                          * source is at the end of address space.
1716                                          */
1717                                         size = mono_class_value_size (in->klass, &align);
1718                                 }
1719                                 if (ainfo->storage == ArgValuetypeInReg) {
1720                                         if (ainfo->pair_storage [1] == ArgNone) {
1721                                                 MonoInst *load;
1722
1723                                                 /* Simpler case */
1724
1725                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1726                                                 load->inst_left = in;
1727
1728                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1729                                         }
1730                                         else {
1731                                                 /* Trees can't be shared so make a copy */
1732                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1733                                                 MonoInst *load, *load2, *offset_ins;
1734
1735                                                 /* Reg1 */
1736                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1737                                                 load->ssa_op = MONO_SSA_LOAD;
1738                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1739
1740                                                 NEW_ICONST (cfg, offset_ins, 0);
1741                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1742                                                 load2->inst_left = load;
1743                                                 load2->inst_right = offset_ins;
1744
1745                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1746                                                 load->inst_left = load2;
1747
1748                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1749
1750                                                 /* Reg2 */
1751                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1752                                                 load->ssa_op = MONO_SSA_LOAD;
1753                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1754
1755                                                 NEW_ICONST (cfg, offset_ins, 8);
1756                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1757                                                 load2->inst_left = load;
1758                                                 load2->inst_right = offset_ins;
1759
1760                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1761                                                 load->inst_left = load2;
1762
1763                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1764                                                 arg->cil_code = in->cil_code;
1765                                                 arg->type = in->type;
1766                                                 /* prepend, so they get reversed */
1767                                                 arg->next = call->out_args;
1768                                                 call->out_args = arg;
1769
1770                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1771
1772                                                 /* Prepend a copy inst */
1773                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1774                                                 arg->cil_code = in->cil_code;
1775                                                 arg->ssa_op = MONO_SSA_STORE;
1776                                                 arg->inst_left = vtaddr;
1777                                                 arg->inst_right = in;
1778                                                 arg->type = in->type;
1779
1780                                                 /* prepend, so they get reversed */
1781                                                 arg->next = call->out_args;
1782                                                 call->out_args = arg;
1783                                         }
1784                                 }
1785                                 else if (ainfo->storage == ArgValuetypeAddrInIReg){
1786
1787                                         /* Add a temp variable to the method*/
1788                                         MonoInst *load;
1789                                         MonoInst *vtaddr = mono_compile_create_var (cfg, &in->klass->byval_arg, OP_LOCAL);
1790
1791                                         MONO_INST_NEW (cfg, load, OP_LDADDR);
1792                                         load->ssa_op = MONO_SSA_LOAD;
1793                                         load->inst_left = vtaddr;
1794
1795                                         if (ainfo->pair_storage [0] == ArgInIReg) {
1796                                                 /* Inserted after the copy.  Load the address of the temp to the argument regster.*/
1797                                                 arg->opcode = OP_OUTARG_REG;
1798                                                 arg->inst_left = load;
1799                                                 arg->inst_call = call;
1800                                                 arg->backend.reg3 =  ainfo->pair_regs [0];
1801                                         }
1802                                         else {
1803                                                 /* Inserted after the copy.  Load the address of the temp on the stack.*/
1804                                                 arg->opcode = OP_OUTARG_VT;
1805                                                 arg->inst_left = load;
1806                                                 arg->type = STACK_PTR;
1807                                                 arg->klass = mono_defaults.int_class;
1808                                                 arg->backend.is_pinvoke = sig->pinvoke;
1809                                                 arg->inst_imm = size;
1810                                         }
1811
1812                                         /*Copy the argument to the temp variable.*/
1813                                         MONO_INST_NEW (cfg, load, OP_MEMCPY);
1814                                         load->backend.memcpy_args = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoMemcpyArgs));
1815                                         load->backend.memcpy_args->size = size;
1816                                         load->backend.memcpy_args->align = align;
1817                                         load->inst_left = (cfg)->varinfo [vtaddr->inst_c0];
1818                                         load->inst_right = in->inst_i0;
1819
1820                                         // FIXME:
1821                                         g_assert_not_reached ();
1822                                         //MONO_INST_LIST_ADD (&load->node, &call->out_args);
1823                                 }
1824                                 else {
1825                                         arg->opcode = OP_OUTARG_VT;
1826                                         arg->klass = in->klass;
1827                                         arg->backend.is_pinvoke = sig->pinvoke;
1828                                         arg->inst_imm = size;
1829                                 }
1830                         }
1831                         else {
1832                                 switch (ainfo->storage) {
1833                                 case ArgInIReg:
1834                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1835                                         break;
1836                                 case ArgInFloatSSEReg:
1837                                 case ArgInDoubleSSEReg:
1838                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1839                                         break;
1840                                 case ArgOnStack:
1841                                         arg->opcode = OP_OUTARG;
1842                                         if (!sig->params [i - sig->hasthis]->byref) {
1843                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1844                                                         arg->opcode = OP_OUTARG_R4;
1845                                                 else
1846                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1847                                                                 arg->opcode = OP_OUTARG_R8;
1848                                         }
1849                                         break;
1850                                 default:
1851                                         g_assert_not_reached ();
1852                                 }
1853                         }
1854                 }
1855         }
1856
1857         /* Handle the case where there are no implicit arguments */
1858         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1859                 emit_sig_cookie (cfg, call, cinfo);
1860         }
1861
1862         if (cinfo->ret.storage == ArgValuetypeInReg) {
1863                 /* This is needed by mono_arch_emit_this_vret_args () */
1864                 if (!cfg->arch.vret_addr_loc) {
1865                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1866                         /* Prevent it from being register allocated or optimized away */
1867                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1868                 }
1869         }
1870
1871         if (cinfo->need_stack_align) {
1872                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1873                 arg->inst_c0 = 8;
1874                 /* prepend, so they get reversed */
1875                 arg->next = call->out_args;
1876                 call->out_args = arg;
1877         }
1878
1879 #ifdef PLATFORM_WIN32
1880         /* Always reserve 32 bytes of stack space on Win64 */
1881         /*MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1882         arg->inst_c0 = 32;
1883         MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);*/
1884         NOT_IMPLEMENTED;
1885 #endif
1886
1887 #if 0
1888         if (cfg->method->save_lmf) {
1889                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1890                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1891         }
1892 #endif
1893
1894         call->stack_usage = cinfo->stack_usage;
1895         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1896         cfg->flags |= MONO_CFG_HAS_CALLS;
1897
1898         return call;
1899 }
1900
1901 static void
1902 emit_sig_cookie2 (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1903 {
1904         MonoInst *arg;
1905         MonoMethodSignature *tmp_sig;
1906         MonoInst *sig_arg;
1907
1908         if (call->tail_call)
1909                 NOT_IMPLEMENTED;
1910
1911         /* FIXME: Add support for signature tokens to AOT */
1912         cfg->disable_aot = TRUE;
1913
1914         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1915
1916         /*
1917          * mono_ArgIterator_Setup assumes the signature cookie is
1918          * passed first and all the arguments which were before it are
1919          * passed on the stack after the signature. So compensate by
1920          * passing a different signature.
1921          */
1922         tmp_sig = mono_metadata_signature_dup (call->signature);
1923         tmp_sig->param_count -= call->signature->sentinelpos;
1924         tmp_sig->sentinelpos = 0;
1925         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1926
1927         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1928         sig_arg->dreg = mono_alloc_ireg (cfg);
1929         sig_arg->inst_p0 = tmp_sig;
1930         MONO_ADD_INS (cfg->cbb, sig_arg);
1931
1932         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1933         arg->sreg1 = sig_arg->dreg;
1934         MONO_ADD_INS (cfg->cbb, arg);
1935 }
1936
1937 void
1938 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1939 {
1940         MonoInst *arg, *in;
1941         MonoMethodSignature *sig;
1942         int i, n, stack_size;
1943         CallInfo *cinfo;
1944         ArgInfo *ainfo;
1945
1946         stack_size = 0;
1947
1948         sig = call->signature;
1949         n = sig->param_count + sig->hasthis;
1950
1951         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1952
1953         if (cinfo->need_stack_align) {
1954                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1955         }
1956
1957         /*
1958          * Emit all parameters passed in registers in non-reverse order for better readability
1959          * and to help the optimization in emit_prolog ().
1960          */
1961         for (i = 0; i < n; ++i) {
1962                 ainfo = cinfo->args + i;
1963
1964                 in = call->args [i];
1965
1966                 if (ainfo->storage == ArgInIReg)
1967                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1968         }
1969
1970         for (i = n - 1; i >= 0; --i) {
1971                 ainfo = cinfo->args + i;
1972
1973                 in = call->args [i];
1974
1975                 switch (ainfo->storage) {
1976                 case ArgInIReg:
1977                         /* Already done */
1978                         break;
1979                 case ArgInFloatSSEReg:
1980                 case ArgInDoubleSSEReg:
1981                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1982                         break;
1983                 case ArgOnStack:
1984                 case ArgValuetypeInReg:
1985                 case ArgValuetypeAddrInIReg:
1986                         if (ainfo->storage == ArgOnStack && call->tail_call)
1987                                 NOT_IMPLEMENTED;
1988                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1989                                 guint32 align;
1990                                 guint32 size;
1991
1992                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1993                                         size = sizeof (MonoTypedRef);
1994                                         align = sizeof (gpointer);
1995                                 }
1996                                 else {
1997                                         if (sig->pinvoke)
1998                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1999                                         else {
2000                                                 /*
2001                                                  * Other backends use mono_type_stack_size (), but that
2002                                                  * aligns the size to 8, which is larger than the size of
2003                                                  * the source, leading to reads of invalid memory if the
2004                                                  * source is at the end of address space.
2005                                                  */
2006                                                 size = mono_class_value_size (in->klass, &align);
2007                                         }
2008                                 }
2009                                 g_assert (in->klass);
2010
2011                                 if (size > 0) {
2012                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2013                                         arg->sreg1 = in->dreg;
2014                                         arg->klass = in->klass;
2015                                         arg->backend.size = size;
2016                                         arg->inst_p0 = call;
2017                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2018                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2019
2020                                         MONO_ADD_INS (cfg->cbb, arg);
2021                                 }
2022                         } else {
2023                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2024                                 arg->sreg1 = in->dreg;
2025                                 if (!sig->params [i - sig->hasthis]->byref) {
2026                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2027                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2028                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
2029                                                 arg->inst_destbasereg = X86_ESP;
2030                                                 arg->inst_offset = 0;
2031                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2032                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2033                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
2034                                                 arg->inst_destbasereg = X86_ESP;
2035                                                 arg->inst_offset = 0;
2036                                         }
2037                                 }
2038                                 MONO_ADD_INS (cfg->cbb, arg);
2039                         }
2040                         break;
2041                 default:
2042                         g_assert_not_reached ();
2043                 }
2044
2045                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2046                         /* Emit the signature cookie just before the implicit arguments */
2047                         emit_sig_cookie2 (cfg, call, cinfo);
2048                 }
2049         }
2050
2051         /* Handle the case where there are no implicit arguments */
2052         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
2053                 emit_sig_cookie2 (cfg, call, cinfo);
2054         }
2055
2056         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2057                 MonoInst *vtarg;
2058
2059                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2060                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2061                                 /*
2062                                  * Tell the JIT to use a more efficient calling convention: call using
2063                                  * OP_CALL, compute the result location after the call, and save the
2064                                  * result there.
2065                                  */
2066                                 call->vret_in_reg = TRUE;
2067                         } else {
2068                                 if (call->tail_call)
2069                                         NOT_IMPLEMENTED;
2070                                 /*
2071                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2072                                  * the stack. Push the address here, so the call instruction can
2073                                  * access it.
2074                                  */
2075                                 if (!cfg->arch.vret_addr_loc) {
2076                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2077                                         /* Prevent it from being register allocated or optimized away */
2078                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2079                                 }
2080
2081                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2082                         }
2083                 }
2084                 else {
2085                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2086                         vtarg->sreg1 = call->vret_var->dreg;
2087                         vtarg->dreg = mono_alloc_preg (cfg);
2088                         MONO_ADD_INS (cfg->cbb, vtarg);
2089
2090                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2091                 }
2092         }
2093
2094 #ifdef PLATFORM_WIN32
2095         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2096                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2097         }
2098 #endif
2099
2100         if (cfg->method->save_lmf) {
2101                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2102                 MONO_ADD_INS (cfg->cbb, arg);
2103         }
2104
2105         call->stack_usage = cinfo->stack_usage;
2106 }
2107
2108 void
2109 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2110 {
2111         MonoInst *arg;
2112         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2113         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2114         int size = ins->backend.size;
2115
2116         if (ainfo->storage == ArgValuetypeInReg) {
2117                 MonoInst *load;
2118                 int part;
2119
2120                 for (part = 0; part < 2; ++part) {
2121                         if (ainfo->pair_storage [part] == ArgNone)
2122                                 continue;
2123
2124                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2125                         load->inst_basereg = src->dreg;
2126                         load->inst_offset = part * sizeof (gpointer);
2127
2128                         switch (ainfo->pair_storage [part]) {
2129                         case ArgInIReg:
2130                                 load->dreg = mono_alloc_ireg (cfg);
2131                                 break;
2132                         case ArgInDoubleSSEReg:
2133                         case ArgInFloatSSEReg:
2134                                 load->dreg = mono_alloc_freg (cfg);
2135                                 break;
2136                         default:
2137                                 g_assert_not_reached ();
2138                         }
2139                         MONO_ADD_INS (cfg->cbb, load);
2140
2141                         add_outarg_reg2 (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2142                 }
2143         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2144                 MonoInst *vtaddr, *load;
2145                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2146
2147                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2148                 load->inst_p0 = vtaddr;
2149                 vtaddr->flags |= MONO_INST_INDIRECT;
2150                 load->type = STACK_MP;
2151                 load->klass = vtaddr->klass;
2152                 load->dreg = mono_alloc_ireg (cfg);
2153                 MONO_ADD_INS (cfg->cbb, load);
2154                 mini_emit_memcpy2 (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2155
2156                 if (ainfo->pair_storage [0] == ArgInIReg) {
2157                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2158                         arg->dreg = ainfo->pair_regs [0];
2159                         arg->sreg1 = load->dreg;
2160                         arg->inst_imm = 0;
2161                         MONO_ADD_INS (cfg->cbb, arg);
2162                 } else {
2163                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2164                         arg->sreg1 = load->dreg;
2165                         MONO_ADD_INS (cfg->cbb, arg);
2166                 }
2167         } else {
2168                 if (size == 8) {
2169                         /* Can't use this for < 8 since it does an 8 byte memory load */
2170                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2171                         arg->inst_basereg = src->dreg;
2172                         arg->inst_offset = 0;
2173                         MONO_ADD_INS (cfg->cbb, arg);
2174                 } else if (size <= 40) {
2175                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2176                         mini_emit_memcpy2 (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2177                 } else {
2178                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2179                         arg->inst_basereg = src->dreg;
2180                         arg->inst_offset = 0;
2181                         arg->inst_imm = size;
2182                         MONO_ADD_INS (cfg->cbb, arg);
2183                 }
2184         }
2185 }
2186
2187 void
2188 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2189 {
2190         MonoType *ret = mono_type_get_underlying_type (mono_method_signature (method)->ret);
2191
2192         if (!ret->byref) {
2193                 if (ret->type == MONO_TYPE_R4) {
2194                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2195                         return;
2196                 } else if (ret->type == MONO_TYPE_R8) {
2197                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2198                         return;
2199                 }
2200         }
2201
2202         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2203 }
2204
2205 #define EMIT_COND_BRANCH(ins,cond,sign) \
2206 if (ins->flags & MONO_INST_BRLABEL) { \
2207         if (ins->inst_i0->inst_c0) { \
2208                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
2209         } else { \
2210                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
2211                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2212                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
2213                         x86_branch8 (code, cond, 0, sign); \
2214                 else \
2215                         x86_branch32 (code, cond, 0, sign); \
2216         } \
2217 } else { \
2218         if (ins->inst_true_bb->native_offset) { \
2219                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2220         } else { \
2221                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2222                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2223                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
2224                         x86_branch8 (code, cond, 0, sign); \
2225                 else \
2226                         x86_branch32 (code, cond, 0, sign); \
2227         } \
2228 }
2229
2230 /* emit an exception if condition is fail */
2231 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2232         do {                                                        \
2233                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2234                 if (tins == NULL) {                                                                             \
2235                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2236                                         MONO_PATCH_INFO_EXC, exc_name);  \
2237                         x86_branch32 (code, cond, 0, signed);               \
2238                 } else {        \
2239                         EMIT_COND_BRANCH (tins, cond, signed);  \
2240                 }                       \
2241         } while (0);
2242
2243 #define EMIT_FPCOMPARE(code) do { \
2244         amd64_fcompp (code); \
2245         amd64_fnstsw (code); \
2246 } while (0);
2247
2248 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2249     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2250         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2251         amd64_ ##op (code); \
2252         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2253         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2254 } while (0);
2255
2256 static guint8*
2257 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2258 {
2259         gboolean no_patch = FALSE;
2260
2261         /*
2262          * FIXME: Add support for thunks
2263          */
2264         {
2265                 gboolean near_call = FALSE;
2266
2267                 /*
2268                  * Indirect calls are expensive so try to make a near call if possible.
2269                  * The caller memory is allocated by the code manager so it is
2270                  * guaranteed to be at a 32 bit offset.
2271                  */
2272
2273                 if (patch_type != MONO_PATCH_INFO_ABS) {
2274                         /* The target is in memory allocated using the code manager */
2275                         near_call = TRUE;
2276
2277                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2278                                 if (((MonoMethod*)data)->klass->image->aot_module)
2279                                         /* The callee might be an AOT method */
2280                                         near_call = FALSE;
2281                                 if (((MonoMethod*)data)->dynamic)
2282                                         /* The target is in malloc-ed memory */
2283                                         near_call = FALSE;
2284                         }
2285
2286                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2287                                 /*
2288                                  * The call might go directly to a native function without
2289                                  * the wrapper.
2290                                  */
2291                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2292                                 if (mi) {
2293                                         gconstpointer target = mono_icall_get_wrapper (mi);
2294                                         if ((((guint64)target) >> 32) != 0)
2295                                                 near_call = FALSE;
2296                                 }
2297                         }
2298                 }
2299                 else {
2300                         if (mono_find_class_init_trampoline_by_addr (data))
2301                                 near_call = TRUE;
2302                         else {
2303                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2304                                 if (info) {
2305                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2306                                                 strstr (cfg->method->name, info->name)) {
2307                                                 /* A call to the wrapped function */
2308                                                 if ((((guint64)data) >> 32) == 0)
2309                                                         near_call = TRUE;
2310                                                 no_patch = TRUE;
2311                                         }
2312                                         else if (info->func == info->wrapper) {
2313                                                 /* No wrapper */
2314                                                 if ((((guint64)info->func) >> 32) == 0)
2315                                                         near_call = TRUE;
2316                                         }
2317                                         else {
2318                                                 /* See the comment in mono_codegen () */
2319                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2320                                                         near_call = TRUE;
2321                                         }
2322                                 }
2323                                 else if ((((guint64)data) >> 32) == 0) {
2324                                         near_call = TRUE;
2325                                         no_patch = TRUE;
2326                                 }
2327                         }
2328                 }
2329
2330                 if (cfg->method->dynamic)
2331                         /* These methods are allocated using malloc */
2332                         near_call = FALSE;
2333
2334                 if (cfg->compile_aot)
2335                         near_call = TRUE;
2336
2337 #ifdef MONO_ARCH_NOMAP32BIT
2338                 near_call = FALSE;
2339 #endif
2340
2341                 if (near_call) {
2342                         /*
2343                          * Align the call displacement to an address divisible by 4 so it does
2344                          * not span cache lines. This is required for code patching to work on SMP
2345                          * systems.
2346                          */
2347                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2348                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2349                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2350                         amd64_call_code (code, 0);
2351                 }
2352                 else {
2353                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2354                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2355                         amd64_call_reg (code, GP_SCRATCH_REG);
2356                 }
2357         }
2358
2359         return code;
2360 }
2361
2362 static inline guint8*
2363 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2364 {
2365 #ifdef PLATFORM_WIN32
2366         if (win64_adjust_stack)
2367                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2368 #endif
2369         code = emit_call_body (cfg, code, patch_type, data);
2370 #ifdef PLATFORM_WIN32
2371         if (win64_adjust_stack)
2372                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2373 #endif
2374
2375         return code;
2376 }
2377
2378 static inline int
2379 store_membase_imm_to_store_membase_reg (int opcode)
2380 {
2381         switch (opcode) {
2382         case OP_STORE_MEMBASE_IMM:
2383                 return OP_STORE_MEMBASE_REG;
2384         case OP_STOREI4_MEMBASE_IMM:
2385                 return OP_STOREI4_MEMBASE_REG;
2386         case OP_STOREI8_MEMBASE_IMM:
2387                 return OP_STOREI8_MEMBASE_REG;
2388         }
2389
2390         return -1;
2391 }
2392
2393 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2394
2395 /*
2396  * mono_arch_peephole_pass_1:
2397  *
2398  *   Perform peephole opts which should/can be performed before local regalloc
2399  */
2400 void
2401 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2402 {
2403         MonoInst *ins, *n;
2404
2405         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2406                 MonoInst *last_ins = ins->prev;
2407
2408                 switch (ins->opcode) {
2409                 case OP_ADD_IMM:
2410                 case OP_IADD_IMM:
2411                 case OP_LADD_IMM:
2412                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2413                                 /*
2414                                  * X86_LEA is like ADD, but doesn't have the
2415                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2416                                  * its operand to 64 bit.
2417                                  */
2418                                 ins->opcode = OP_X86_LEA_MEMBASE;
2419                                 ins->inst_basereg = ins->sreg1;
2420                         }
2421                         break;
2422                 case OP_LXOR:
2423                 case OP_IXOR:
2424                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2425                                 MonoInst *ins2;
2426
2427                                 /*
2428                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2429                                  * the latter has length 2-3 instead of 6 (reverse constant
2430                                  * propagation). These instruction sequences are very common
2431                                  * in the initlocals bblock.
2432                                  */
2433                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2434                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2435                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2436                                                 ins2->sreg1 = ins->dreg;
2437                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2438                                                 /* Continue */
2439                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2440                                                 NULLIFY_INS (ins2);
2441                                                 /* Continue */
2442                                         } else {
2443                                                 break;
2444                                         }
2445                                 }
2446                         }
2447                         break;
2448                 case OP_COMPARE_IMM:
2449                 case OP_LCOMPARE_IMM:
2450                         /* OP_COMPARE_IMM (reg, 0)
2451                          * -->
2452                          * OP_AMD64_TEST_NULL (reg)
2453                          */
2454                         if (!ins->inst_imm)
2455                                 ins->opcode = OP_AMD64_TEST_NULL;
2456                         break;
2457                 case OP_ICOMPARE_IMM:
2458                         if (!ins->inst_imm)
2459                                 ins->opcode = OP_X86_TEST_NULL;
2460                         break;
2461                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2462                         /*
2463                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2464                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2465                          * -->
2466                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2467                          * OP_COMPARE_IMM reg, imm
2468                          *
2469                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2470                          */
2471                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2472                             ins->inst_basereg == last_ins->inst_destbasereg &&
2473                             ins->inst_offset == last_ins->inst_offset) {
2474                                         ins->opcode = OP_ICOMPARE_IMM;
2475                                         ins->sreg1 = last_ins->sreg1;
2476
2477                                         /* check if we can remove cmp reg,0 with test null */
2478                                         if (!ins->inst_imm)
2479                                                 ins->opcode = OP_X86_TEST_NULL;
2480                                 }
2481
2482                         break;
2483                 }
2484
2485                 mono_peephole_ins (bb, ins);
2486         }
2487 }
2488
2489 void
2490 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2491 {
2492         MonoInst *ins, *n;
2493
2494         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2495                 switch (ins->opcode) {
2496                 case OP_ICONST:
2497                 case OP_I8CONST: {
2498                         /* reg = 0 -> XOR (reg, reg) */
2499                         /* XOR sets cflags on x86, so we cant do it always */
2500                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2501                                 ins->opcode = OP_LXOR;
2502                                 ins->sreg1 = ins->dreg;
2503                                 ins->sreg2 = ins->dreg;
2504                                 /* Fall through */
2505                         } else {
2506                                 break;
2507                         }
2508                 }
2509                 case OP_LXOR:
2510                         /*
2511                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2512                          * 0 result into 64 bits.
2513                          */
2514                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2515                                 ins->opcode = OP_IXOR;
2516                         }
2517                         /* Fall through */
2518                 case OP_IXOR:
2519                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2520                                 MonoInst *ins2;
2521
2522                                 /*
2523                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2524                                  * the latter has length 2-3 instead of 6 (reverse constant
2525                                  * propagation). These instruction sequences are very common
2526                                  * in the initlocals bblock.
2527                                  */
2528                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2529                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2530                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2531                                                 ins2->sreg1 = ins->dreg;
2532                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2533                                                 /* Continue */
2534                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2535                                                 NULLIFY_INS (ins2);
2536                                                 /* Continue */
2537                                         } else {
2538                                                 break;
2539                                         }
2540                                 }
2541                         }
2542                         break;
2543                 case OP_IADD_IMM:
2544                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2545                                 ins->opcode = OP_X86_INC_REG;
2546                         break;
2547                 case OP_ISUB_IMM:
2548                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2549                                 ins->opcode = OP_X86_DEC_REG;
2550                         break;
2551                 }
2552
2553                 mono_peephole_ins (bb, ins);
2554         }
2555 }
2556
2557 #define NEW_INS(cfg,ins,dest,op) do {   \
2558                 MONO_INST_NEW ((cfg), (dest), (op)); \
2559         (dest)->cil_code = (ins)->cil_code; \
2560         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2561         } while (0)
2562
2563 /*
2564  * mono_arch_lowering_pass:
2565  *
2566  *  Converts complex opcodes into simpler ones so that each IR instruction
2567  * corresponds to one machine instruction.
2568  */
2569 void
2570 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2571 {
2572         MonoInst *ins, *n, *temp;
2573
2574         if (bb->max_vreg > cfg->rs->next_vreg)
2575                 cfg->rs->next_vreg = bb->max_vreg;
2576
2577         /*
2578          * FIXME: Need to add more instructions, but the current machine
2579          * description can't model some parts of the composite instructions like
2580          * cdq.
2581          */
2582         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2583                 switch (ins->opcode) {
2584                 case OP_DIV_IMM:
2585                 case OP_REM_IMM:
2586                 case OP_IDIV_IMM:
2587                 case OP_IREM_IMM:
2588                 case OP_IDIV_UN_IMM:
2589                 case OP_IREM_UN_IMM:
2590                         mono_decompose_op_imm (cfg, bb, ins);
2591                         break;
2592                 case OP_COMPARE_IMM:
2593                 case OP_LCOMPARE_IMM:
2594                         if (!amd64_is_imm32 (ins->inst_imm)) {
2595                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2596                                 temp->inst_c0 = ins->inst_imm;
2597                                 if (cfg->globalra)
2598                                         temp->dreg = mono_alloc_ireg (cfg);
2599                                 else
2600                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2601                                 ins->opcode = OP_COMPARE;
2602                                 ins->sreg2 = temp->dreg;
2603                         }
2604                         break;
2605                 case OP_LOAD_MEMBASE:
2606                 case OP_LOADI8_MEMBASE:
2607                         if (!amd64_is_imm32 (ins->inst_offset)) {
2608                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2609                                 temp->inst_c0 = ins->inst_offset;
2610                                 if (cfg->globalra)
2611                                         temp->dreg = mono_alloc_ireg (cfg);
2612                                 else
2613                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2614                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2615                                 ins->inst_indexreg = temp->dreg;
2616                         }
2617                         break;
2618                 case OP_STORE_MEMBASE_IMM:
2619                 case OP_STOREI8_MEMBASE_IMM:
2620                         if (!amd64_is_imm32 (ins->inst_imm)) {
2621                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2622                                 temp->inst_c0 = ins->inst_imm;
2623                                 if (cfg->globalra)
2624                                         temp->dreg = mono_alloc_ireg (cfg);
2625                                 else
2626                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2627                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2628                                 ins->sreg1 = temp->dreg;
2629                         }
2630                         break;
2631                 default:
2632                         break;
2633                 }
2634         }
2635
2636         bb->max_vreg = cfg->rs->next_vreg;
2637 }
2638
2639 static const int
2640 branch_cc_table [] = {
2641         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2642         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2643         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2644 };
2645
2646 /* Maps CMP_... constants to X86_CC_... constants */
2647 static const int
2648 cc_table [] = {
2649         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2650         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2651 };
2652
2653 static const int
2654 cc_signed_table [] = {
2655         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2656         FALSE, FALSE, FALSE, FALSE
2657 };
2658
2659 /*#include "cprop.c"*/
2660
2661 static unsigned char*
2662 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2663 {
2664         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2665
2666         if (size == 1)
2667                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2668         else if (size == 2)
2669                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2670         return code;
2671 }
2672
2673 static unsigned char*
2674 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2675 {
2676         int sreg = tree->sreg1;
2677         int need_touch = FALSE;
2678
2679 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2680         if (!tree->flags & MONO_INST_INIT)
2681                 need_touch = TRUE;
2682 #endif
2683
2684         if (need_touch) {
2685                 guint8* br[5];
2686
2687                 /*
2688                  * Under Windows:
2689                  * If requested stack size is larger than one page,
2690                  * perform stack-touch operation
2691                  */
2692                 /*
2693                  * Generate stack probe code.
2694                  * Under Windows, it is necessary to allocate one page at a time,
2695                  * "touching" stack after each successful sub-allocation. This is
2696                  * because of the way stack growth is implemented - there is a
2697                  * guard page before the lowest stack page that is currently commited.
2698                  * Stack normally grows sequentially so OS traps access to the
2699                  * guard page and commits more pages when needed.
2700                  */
2701                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2702                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2703
2704                 br[2] = code; /* loop */
2705                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2706                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2707                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2708                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2709                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2710                 amd64_patch (br[3], br[2]);
2711                 amd64_test_reg_reg (code, sreg, sreg);
2712                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2713                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2714
2715                 br[1] = code; x86_jump8 (code, 0);
2716
2717                 amd64_patch (br[0], code);
2718                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2719                 amd64_patch (br[1], code);
2720                 amd64_patch (br[4], code);
2721         }
2722         else
2723                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2724
2725         if (tree->flags & MONO_INST_INIT) {
2726                 int offset = 0;
2727                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2728                         amd64_push_reg (code, AMD64_RAX);
2729                         offset += 8;
2730                 }
2731                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2732                         amd64_push_reg (code, AMD64_RCX);
2733                         offset += 8;
2734                 }
2735                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2736                         amd64_push_reg (code, AMD64_RDI);
2737                         offset += 8;
2738                 }
2739
2740                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2741                 if (sreg != AMD64_RCX)
2742                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2743                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2744
2745                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2746                 amd64_cld (code);
2747                 amd64_prefix (code, X86_REP_PREFIX);
2748                 amd64_stosl (code);
2749
2750                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2751                         amd64_pop_reg (code, AMD64_RDI);
2752                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2753                         amd64_pop_reg (code, AMD64_RCX);
2754                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2755                         amd64_pop_reg (code, AMD64_RAX);
2756         }
2757         return code;
2758 }
2759
2760 static guint8*
2761 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2762 {
2763         CallInfo *cinfo;
2764         guint32 quad;
2765
2766         /* Move return value to the target register */
2767         /* FIXME: do this in the local reg allocator */
2768         switch (ins->opcode) {
2769         case OP_CALL:
2770         case OP_CALL_REG:
2771         case OP_CALL_MEMBASE:
2772         case OP_LCALL:
2773         case OP_LCALL_REG:
2774         case OP_LCALL_MEMBASE:
2775                 g_assert (ins->dreg == AMD64_RAX);
2776                 break;
2777         case OP_FCALL:
2778         case OP_FCALL_REG:
2779         case OP_FCALL_MEMBASE:
2780                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2781                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2782                 }
2783                 else {
2784                         if (ins->dreg != AMD64_XMM0)
2785                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2786                 }
2787                 break;
2788         case OP_VCALL:
2789         case OP_VCALL_REG:
2790         case OP_VCALL_MEMBASE:
2791         case OP_VCALL2:
2792         case OP_VCALL2_REG:
2793         case OP_VCALL2_MEMBASE:
2794                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2795                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2796                         MonoInst *loc = cfg->arch.vret_addr_loc;
2797
2798                         /* Load the destination address */
2799                         g_assert (loc->opcode == OP_REGOFFSET);
2800                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2801
2802                         for (quad = 0; quad < 2; quad ++) {
2803                                 switch (cinfo->ret.pair_storage [quad]) {
2804                                 case ArgInIReg:
2805                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2806                                         break;
2807                                 case ArgInFloatSSEReg:
2808                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2809                                         break;
2810                                 case ArgInDoubleSSEReg:
2811                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2812                                         break;
2813                                 case ArgNone:
2814                                         break;
2815                                 default:
2816                                         NOT_IMPLEMENTED;
2817                                 }
2818                         }
2819                 }
2820                 break;
2821         }
2822
2823         return code;
2824 }
2825
2826 /*
2827  * emit_tls_get:
2828  * @code: buffer to store code to
2829  * @dreg: hard register where to place the result
2830  * @tls_offset: offset info
2831  *
2832  * emit_tls_get emits in @code the native code that puts in the dreg register
2833  * the item in the thread local storage identified by tls_offset.
2834  *
2835  * Returns: a pointer to the end of the stored code
2836  */
2837 static guint8*
2838 emit_tls_get (guint8* code, int dreg, int tls_offset)
2839 {
2840 #ifdef PLATFORM_WIN32
2841         g_assert (tls_offset < 64);
2842         x86_prefix (code, X86_GS_PREFIX);
2843         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2844 #else
2845         if (optimize_for_xen) {
2846                 x86_prefix (code, X86_FS_PREFIX);
2847                 amd64_mov_reg_mem (code, dreg, 0, 8);
2848                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2849         } else {
2850                 x86_prefix (code, X86_FS_PREFIX);
2851                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2852         }
2853 #endif
2854         return code;
2855 }
2856
2857 /*
2858  * emit_load_volatile_arguments:
2859  *
2860  *  Load volatile arguments from the stack to the original input registers.
2861  * Required before a tail call.
2862  */
2863 static guint8*
2864 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2865 {
2866         MonoMethod *method = cfg->method;
2867         MonoMethodSignature *sig;
2868         MonoInst *ins;
2869         CallInfo *cinfo;
2870         guint32 i, quad;
2871
2872         /* FIXME: Generate intermediate code instead */
2873
2874         sig = mono_method_signature (method);
2875
2876         cinfo = cfg->arch.cinfo;
2877
2878         /* This is the opposite of the code in emit_prolog */
2879         if (sig->ret->type != MONO_TYPE_VOID) {
2880                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2881                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2882         }
2883
2884         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2885                 ArgInfo *ainfo = cinfo->args + i;
2886                 MonoType *arg_type;
2887                 ins = cfg->args [i];
2888
2889                 if (sig->hasthis && (i == 0))
2890                         arg_type = &mono_defaults.object_class->byval_arg;
2891                 else
2892                         arg_type = sig->params [i - sig->hasthis];
2893
2894                 if (ins->opcode != OP_REGVAR) {
2895                         switch (ainfo->storage) {
2896                         case ArgInIReg: {
2897                                 guint32 size = 8;
2898
2899                                 /* FIXME: I1 etc */
2900                                 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2901                                 break;
2902                         }
2903                         case ArgInFloatSSEReg:
2904                                 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2905                                 break;
2906                         case ArgInDoubleSSEReg:
2907                                 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2908                                 break;
2909                         case ArgValuetypeInReg:
2910                                 for (quad = 0; quad < 2; quad ++) {
2911                                         switch (ainfo->pair_storage [quad]) {
2912                                         case ArgInIReg:
2913                                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2914                                                 break;
2915                                         case ArgInFloatSSEReg:
2916                                         case ArgInDoubleSSEReg:
2917                                                 g_assert_not_reached ();
2918                                                 break;
2919                                         case ArgNone:
2920                                                 break;
2921                                         default:
2922                                                 g_assert_not_reached ();
2923                                         }
2924                                 }
2925                                 break;
2926                         case ArgValuetypeAddrInIReg:
2927                                 if (ainfo->pair_storage [0] == ArgInIReg)
2928                                         amd64_mov_reg_membase (code, ainfo->pair_regs [0], ins->inst_left->inst_basereg, ins->inst_left->inst_offset,  sizeof (gpointer));
2929                                 break;
2930                         default:
2931                                 break;
2932                         }
2933                 }
2934                 else {
2935                         g_assert (ainfo->storage == ArgInIReg);
2936
2937                         amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2938                 }
2939         }
2940
2941         return code;
2942 }
2943
2944 #define REAL_PRINT_REG(text,reg) \
2945 mono_assert (reg >= 0); \
2946 amd64_push_reg (code, AMD64_RAX); \
2947 amd64_push_reg (code, AMD64_RDX); \
2948 amd64_push_reg (code, AMD64_RCX); \
2949 amd64_push_reg (code, reg); \
2950 amd64_push_imm (code, reg); \
2951 amd64_push_imm (code, text " %d %p\n"); \
2952 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2953 amd64_call_reg (code, AMD64_RAX); \
2954 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2955 amd64_pop_reg (code, AMD64_RCX); \
2956 amd64_pop_reg (code, AMD64_RDX); \
2957 amd64_pop_reg (code, AMD64_RAX);
2958
2959 /* benchmark and set based on cpu */
2960 #define LOOP_ALIGNMENT 8
2961 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2962
2963 void
2964 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2965 {
2966         MonoInst *ins;
2967         MonoCallInst *call;
2968         guint offset;
2969         guint8 *code = cfg->native_code + cfg->code_len;
2970         MonoInst *last_ins = NULL;
2971         guint last_offset = 0;
2972         int max_len, cpos;
2973
2974         if (cfg->opt & MONO_OPT_LOOP) {
2975                 int pad, align = LOOP_ALIGNMENT;
2976                 /* set alignment depending on cpu */
2977                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2978                         pad = align - pad;
2979                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2980                         amd64_padding (code, pad);
2981                         cfg->code_len += pad;
2982                         bb->native_offset = cfg->code_len;
2983                 }
2984         }
2985
2986         if (cfg->verbose_level > 2)
2987                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2988
2989         cpos = bb->max_offset;
2990
2991         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2992                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2993                 g_assert (!cfg->compile_aot);
2994                 cpos += 6;
2995
2996                 cov->data [bb->dfn].cil_code = bb->cil_code;
2997                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2998                 /* this is not thread save, but good enough */
2999                 amd64_inc_membase (code, AMD64_R11, 0);
3000         }
3001
3002         offset = code - cfg->native_code;
3003
3004         mono_debug_open_block (cfg, bb, offset);
3005
3006         MONO_BB_FOR_EACH_INS (bb, ins) {
3007                 offset = code - cfg->native_code;
3008
3009                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3010
3011                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3012                         cfg->code_size *= 2;
3013                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3014                         code = cfg->native_code + offset;
3015                         mono_jit_stats.code_reallocs++;
3016                 }
3017
3018                 if (cfg->debug_info)
3019                         mono_debug_record_line_number (cfg, ins, offset);
3020
3021                 switch (ins->opcode) {
3022                 case OP_BIGMUL:
3023                         amd64_mul_reg (code, ins->sreg2, TRUE);
3024                         break;
3025                 case OP_BIGMUL_UN:
3026                         amd64_mul_reg (code, ins->sreg2, FALSE);
3027                         break;
3028                 case OP_X86_SETEQ_MEMBASE:
3029                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3030                         break;
3031                 case OP_STOREI1_MEMBASE_IMM:
3032                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3033                         break;
3034                 case OP_STOREI2_MEMBASE_IMM:
3035                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3036                         break;
3037                 case OP_STOREI4_MEMBASE_IMM:
3038                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3039                         break;
3040                 case OP_STOREI1_MEMBASE_REG:
3041                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3042                         break;
3043                 case OP_STOREI2_MEMBASE_REG:
3044                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3045                         break;
3046                 case OP_STORE_MEMBASE_REG:
3047                 case OP_STOREI8_MEMBASE_REG:
3048                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3049                         break;
3050                 case OP_STOREI4_MEMBASE_REG:
3051                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3052                         break;
3053                 case OP_STORE_MEMBASE_IMM:
3054                 case OP_STOREI8_MEMBASE_IMM:
3055                         g_assert (amd64_is_imm32 (ins->inst_imm));
3056                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3057                         break;
3058                 case OP_LOAD_MEM:
3059                 case OP_LOADI8_MEM:
3060                         // FIXME: Decompose this earlier
3061                         if (amd64_is_imm32 (ins->inst_imm))
3062                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3063                         else {
3064                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3065                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3066                         }
3067                         break;
3068                 case OP_LOADI4_MEM:
3069                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3070                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3071                         break;
3072                 case OP_LOADU4_MEM:
3073                         // FIXME: Decompose this earlier
3074                         if (cfg->new_ir) {
3075                                 if (amd64_is_imm32 (ins->inst_imm))
3076                                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3077                                 else {
3078                                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3079                                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3080                                 }
3081                         } else {
3082                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
3083                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3084                         }
3085                         break;
3086                 case OP_LOADU1_MEM:
3087                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3088                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3089                         break;
3090                 case OP_LOADU2_MEM:
3091                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3092                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3093                         break;
3094                 case OP_LOAD_MEMBASE:
3095                 case OP_LOADI8_MEMBASE:
3096                         g_assert (amd64_is_imm32 (ins->inst_offset));
3097                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3098                         break;
3099                 case OP_LOADI4_MEMBASE:
3100                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3101                         break;
3102                 case OP_LOADU4_MEMBASE:
3103                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3104                         break;
3105                 case OP_LOADU1_MEMBASE:
3106                         /* The cpu zero extends the result into 64 bits */
3107                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3108                         break;
3109                 case OP_LOADI1_MEMBASE:
3110                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3111                         break;
3112                 case OP_LOADU2_MEMBASE:
3113                         /* The cpu zero extends the result into 64 bits */
3114                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3115                         break;
3116                 case OP_LOADI2_MEMBASE:
3117                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3118                         break;
3119                 case OP_AMD64_LOADI8_MEMINDEX:
3120                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3121                         break;
3122                 case OP_LCONV_TO_I1:
3123                 case OP_ICONV_TO_I1:
3124                 case OP_SEXT_I1:
3125                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3126                         break;
3127                 case OP_LCONV_TO_I2:
3128                 case OP_ICONV_TO_I2:
3129                 case OP_SEXT_I2:
3130                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3131                         break;
3132                 case OP_LCONV_TO_U1:
3133                 case OP_ICONV_TO_U1:
3134                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3135                         break;
3136                 case OP_LCONV_TO_U2:
3137                 case OP_ICONV_TO_U2:
3138                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3139                         break;
3140                 case OP_ZEXT_I4:
3141                         /* Clean out the upper word */
3142                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3143                         break;
3144                 case OP_SEXT_I4:
3145                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3146                         break;
3147                 case OP_COMPARE:
3148                 case OP_LCOMPARE:
3149                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3150                         break;
3151                 case OP_COMPARE_IMM:
3152                 case OP_LCOMPARE_IMM:
3153                         g_assert (amd64_is_imm32 (ins->inst_imm));
3154                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3155                         break;
3156                 case OP_X86_COMPARE_REG_MEMBASE:
3157                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3158                         break;
3159                 case OP_X86_TEST_NULL:
3160                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3161                         break;
3162                 case OP_AMD64_TEST_NULL:
3163                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3164                         break;
3165
3166                 case OP_X86_ADD_REG_MEMBASE:
3167                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3168                         break;
3169                 case OP_X86_SUB_REG_MEMBASE:
3170                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3171                         break;
3172                 case OP_X86_AND_REG_MEMBASE:
3173                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3174                         break;
3175                 case OP_X86_OR_REG_MEMBASE:
3176                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3177                         break;
3178                 case OP_X86_XOR_REG_MEMBASE:
3179                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3180                         break;
3181
3182                 case OP_X86_ADD_MEMBASE_IMM:
3183                         /* FIXME: Make a 64 version too */
3184                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3185                         break;
3186                 case OP_X86_SUB_MEMBASE_IMM:
3187                         g_assert (amd64_is_imm32 (ins->inst_imm));
3188                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3189                         break;
3190                 case OP_X86_AND_MEMBASE_IMM:
3191                         g_assert (amd64_is_imm32 (ins->inst_imm));
3192                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3193                         break;
3194                 case OP_X86_OR_MEMBASE_IMM:
3195                         g_assert (amd64_is_imm32 (ins->inst_imm));
3196                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3197                         break;
3198                 case OP_X86_XOR_MEMBASE_IMM:
3199                         g_assert (amd64_is_imm32 (ins->inst_imm));
3200                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3201                         break;
3202                 case OP_X86_ADD_MEMBASE_REG:
3203                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3204                         break;
3205                 case OP_X86_SUB_MEMBASE_REG:
3206                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3207                         break;
3208                 case OP_X86_AND_MEMBASE_REG:
3209                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3210                         break;
3211                 case OP_X86_OR_MEMBASE_REG:
3212                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3213                         break;
3214                 case OP_X86_XOR_MEMBASE_REG:
3215                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3216                         break;
3217                 case OP_X86_INC_MEMBASE:
3218                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3219                         break;
3220                 case OP_X86_INC_REG:
3221                         amd64_inc_reg_size (code, ins->dreg, 4);
3222                         break;
3223                 case OP_X86_DEC_MEMBASE:
3224                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3225                         break;
3226                 case OP_X86_DEC_REG:
3227                         amd64_dec_reg_size (code, ins->dreg, 4);
3228                         break;
3229                 case OP_X86_MUL_REG_MEMBASE:
3230                 case OP_X86_MUL_MEMBASE_REG:
3231                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3232                         break;
3233                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3234                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3235                         break;
3236                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3237                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3238                         break;
3239                 case OP_AMD64_COMPARE_MEMBASE_REG:
3240                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3241                         break;
3242                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3243                         g_assert (amd64_is_imm32 (ins->inst_imm));
3244                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3245                         break;
3246                 case OP_X86_COMPARE_MEMBASE8_IMM:
3247                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3248                         break;
3249                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3250                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3251                         break;
3252                 case OP_AMD64_COMPARE_REG_MEMBASE:
3253                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3254                         break;
3255
3256                 case OP_AMD64_ADD_REG_MEMBASE:
3257                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3258                         break;
3259                 case OP_AMD64_SUB_REG_MEMBASE:
3260                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3261                         break;
3262                 case OP_AMD64_AND_REG_MEMBASE:
3263                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3264                         break;
3265                 case OP_AMD64_OR_REG_MEMBASE:
3266                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3267                         break;
3268                 case OP_AMD64_XOR_REG_MEMBASE:
3269                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3270                         break;
3271
3272                 case OP_AMD64_ADD_MEMBASE_REG:
3273                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3274                         break;
3275                 case OP_AMD64_SUB_MEMBASE_REG:
3276                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3277                         break;
3278                 case OP_AMD64_AND_MEMBASE_REG:
3279                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3280                         break;
3281                 case OP_AMD64_OR_MEMBASE_REG:
3282                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3283                         break;
3284                 case OP_AMD64_XOR_MEMBASE_REG:
3285                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3286                         break;
3287
3288                 case OP_AMD64_ADD_MEMBASE_IMM:
3289                         g_assert (amd64_is_imm32 (ins->inst_imm));
3290                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3291                         break;
3292                 case OP_AMD64_SUB_MEMBASE_IMM:
3293                         g_assert (amd64_is_imm32 (ins->inst_imm));
3294                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3295                         break;
3296                 case OP_AMD64_AND_MEMBASE_IMM:
3297                         g_assert (amd64_is_imm32 (ins->inst_imm));
3298                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3299                         break;
3300                 case OP_AMD64_OR_MEMBASE_IMM:
3301                         g_assert (amd64_is_imm32 (ins->inst_imm));
3302                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3303                         break;
3304                 case OP_AMD64_XOR_MEMBASE_IMM:
3305                         g_assert (amd64_is_imm32 (ins->inst_imm));
3306                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3307                         break;
3308
3309                 case OP_BREAK:
3310                         amd64_breakpoint (code);
3311                         break;
3312                 case OP_NOP:
3313                 case OP_DUMMY_USE:
3314                 case OP_DUMMY_STORE:
3315                 case OP_NOT_REACHED:
3316                 case OP_NOT_NULL:
3317                         break;
3318                 case OP_ADDCC:
3319                 case OP_LADD:
3320                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3321                         break;
3322                 case OP_ADC:
3323                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3324                         break;
3325                 case OP_ADD_IMM:
3326                 case OP_LADD_IMM:
3327                         g_assert (amd64_is_imm32 (ins->inst_imm));
3328                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3329                         break;
3330                 case OP_ADC_IMM:
3331                         g_assert (amd64_is_imm32 (ins->inst_imm));
3332                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3333                         break;
3334                 case OP_SUBCC:
3335                 case OP_LSUB:
3336                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3337                         break;
3338                 case OP_SBB:
3339                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3340                         break;
3341                 case OP_SUB_IMM:
3342                 case OP_LSUB_IMM:
3343                         g_assert (amd64_is_imm32 (ins->inst_imm));
3344                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3345                         break;
3346                 case OP_SBB_IMM:
3347                         g_assert (amd64_is_imm32 (ins->inst_imm));
3348                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3349                         break;
3350                 case OP_LAND:
3351                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3352                         break;
3353                 case OP_AND_IMM:
3354                 case OP_LAND_IMM:
3355                         g_assert (amd64_is_imm32 (ins->inst_imm));
3356                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3357                         break;
3358                 case OP_LMUL:
3359                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3360                         break;
3361                 case OP_MUL_IMM:
3362                 case OP_LMUL_IMM:
3363                 case OP_IMUL_IMM: {
3364                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3365
3366                         switch (ins->inst_imm) {
3367                         case 2:
3368                                 /* MOV r1, r2 */
3369                                 /* ADD r1, r1 */
3370                                 if (ins->dreg != ins->sreg1)
3371                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3372                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3373                                 break;
3374                         case 3:
3375                                 /* LEA r1, [r2 + r2*2] */
3376                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3377                                 break;
3378                         case 5:
3379                                 /* LEA r1, [r2 + r2*4] */
3380                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3381                                 break;
3382                         case 6:
3383                                 /* LEA r1, [r2 + r2*2] */
3384                                 /* ADD r1, r1          */
3385                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3386                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3387                                 break;
3388                         case 9:
3389                                 /* LEA r1, [r2 + r2*8] */
3390                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3391                                 break;
3392                         case 10:
3393                                 /* LEA r1, [r2 + r2*4] */
3394                                 /* ADD r1, r1          */
3395                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3396                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3397                                 break;
3398                         case 12:
3399                                 /* LEA r1, [r2 + r2*2] */
3400                                 /* SHL r1, 2           */
3401                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3402                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3403                                 break;
3404                         case 25:
3405                                 /* LEA r1, [r2 + r2*4] */
3406                                 /* LEA r1, [r1 + r1*4] */
3407                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3408                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3409                                 break;
3410                         case 100:
3411                                 /* LEA r1, [r2 + r2*4] */
3412                                 /* SHL r1, 2           */
3413                                 /* LEA r1, [r1 + r1*4] */
3414                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3415                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3416                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3417                                 break;
3418                         default:
3419                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3420                                 break;
3421                         }
3422                         break;
3423                 }
3424                 case OP_LDIV:
3425                 case OP_LREM:
3426                         /* Regalloc magic makes the div/rem cases the same */
3427                         if (ins->sreg2 == AMD64_RDX) {
3428                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3429                                 amd64_cdq (code);
3430                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3431                         } else {
3432                                 amd64_cdq (code);
3433                                 amd64_div_reg (code, ins->sreg2, TRUE);
3434                         }
3435                         break;
3436                 case OP_LDIV_UN:
3437                 case OP_LREM_UN:
3438                         if (ins->sreg2 == AMD64_RDX) {
3439                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3440                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3441                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3442                         } else {
3443                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3444                                 amd64_div_reg (code, ins->sreg2, FALSE);
3445                         }
3446                         break;
3447                 case OP_IDIV:
3448                 case OP_IREM:
3449                         if (ins->sreg2 == AMD64_RDX) {
3450                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3451                                 amd64_cdq_size (code, 4);
3452                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3453                         } else {
3454                                 amd64_cdq_size (code, 4);
3455                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3456                         }
3457                         break;
3458                 case OP_IDIV_UN:
3459                 case OP_IREM_UN:
3460                         if (ins->sreg2 == AMD64_RDX) {
3461                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3462                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3463                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3464                         } else {
3465                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3466                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3467                         }
3468                         break;
3469                 case OP_LMUL_OVF:
3470                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3471                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3472                         break;
3473                 case OP_LOR:
3474                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3475                         break;
3476                 case OP_OR_IMM:
3477                 case OP_LOR_IMM:
3478                         g_assert (amd64_is_imm32 (ins->inst_imm));
3479                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3480                         break;
3481                 case OP_LXOR:
3482                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3483                         break;
3484                 case OP_XOR_IMM:
3485                 case OP_LXOR_IMM:
3486                         g_assert (amd64_is_imm32 (ins->inst_imm));
3487                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3488                         break;
3489                 case OP_LSHL:
3490                         g_assert (ins->sreg2 == AMD64_RCX);
3491                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3492                         break;
3493                 case OP_LSHR:
3494                         g_assert (ins->sreg2 == AMD64_RCX);
3495                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3496                         break;
3497                 case OP_SHR_IMM:
3498                         g_assert (amd64_is_imm32 (ins->inst_imm));
3499                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3500                         break;
3501                 case OP_LSHR_IMM:
3502                         g_assert (amd64_is_imm32 (ins->inst_imm));
3503                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3504                         break;
3505                 case OP_SHR_UN_IMM:
3506                         g_assert (amd64_is_imm32 (ins->inst_imm));
3507                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3508                         break;
3509                 case OP_LSHR_UN_IMM:
3510                         g_assert (amd64_is_imm32 (ins->inst_imm));
3511                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3512                         break;
3513                 case OP_LSHR_UN:
3514                         g_assert (ins->sreg2 == AMD64_RCX);
3515                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3516                         break;
3517                 case OP_SHL_IMM:
3518                         g_assert (amd64_is_imm32 (ins->inst_imm));
3519                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3520                         break;
3521                 case OP_LSHL_IMM:
3522                         g_assert (amd64_is_imm32 (ins->inst_imm));
3523                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3524                         break;
3525
3526                 case OP_IADDCC:
3527                 case OP_IADD:
3528                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3529                         break;
3530                 case OP_IADC:
3531                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3532                         break;
3533                 case OP_IADD_IMM:
3534                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3535                         break;
3536                 case OP_IADC_IMM:
3537                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3538                         break;
3539                 case OP_ISUBCC:
3540                 case OP_ISUB:
3541                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3542                         break;
3543                 case OP_ISBB:
3544                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3545                         break;
3546                 case OP_ISUB_IMM:
3547                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3548                         break;
3549                 case OP_ISBB_IMM:
3550                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3551                         break;
3552                 case OP_IAND:
3553                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3554                         break;
3555                 case OP_IAND_IMM:
3556                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3557                         break;
3558                 case OP_IOR:
3559                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3560                         break;
3561                 case OP_IOR_IMM:
3562                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3563                         break;
3564                 case OP_IXOR:
3565                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3566                         break;
3567                 case OP_IXOR_IMM:
3568                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3569                         break;
3570                 case OP_INEG:
3571                         amd64_neg_reg_size (code, ins->sreg1, 4);
3572                         break;
3573                 case OP_INOT:
3574                         amd64_not_reg_size (code, ins->sreg1, 4);
3575                         break;
3576                 case OP_ISHL:
3577                         g_assert (ins->sreg2 == AMD64_RCX);
3578                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3579                         break;
3580                 case OP_ISHR:
3581                         g_assert (ins->sreg2 == AMD64_RCX);
3582                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3583                         break;
3584                 case OP_ISHR_IMM:
3585                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3586                         break;
3587                 case OP_ISHR_UN_IMM:
3588                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3589                         break;
3590                 case OP_ISHR_UN:
3591                         g_assert (ins->sreg2 == AMD64_RCX);
3592                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3593                         break;
3594                 case OP_ISHL_IMM:
3595                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3596                         break;
3597                 case OP_IMUL:
3598                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3599                         break;
3600                 case OP_IMUL_OVF:
3601                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3602                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3603                         break;
3604                 case OP_IMUL_OVF_UN:
3605                 case OP_LMUL_OVF_UN: {
3606                         /* the mul operation and the exception check should most likely be split */
3607                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3608                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3609                         /*g_assert (ins->sreg2 == X86_EAX);
3610                         g_assert (ins->dreg == X86_EAX);*/
3611                         if (ins->sreg2 == X86_EAX) {
3612                                 non_eax_reg = ins->sreg1;
3613                         } else if (ins->sreg1 == X86_EAX) {
3614                                 non_eax_reg = ins->sreg2;
3615                         } else {
3616                                 /* no need to save since we're going to store to it anyway */
3617                                 if (ins->dreg != X86_EAX) {
3618                                         saved_eax = TRUE;
3619                                         amd64_push_reg (code, X86_EAX);
3620                                 }
3621                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3622                                 non_eax_reg = ins->sreg2;
3623                         }
3624                         if (ins->dreg == X86_EDX) {
3625                                 if (!saved_eax) {
3626                                         saved_eax = TRUE;
3627                                         amd64_push_reg (code, X86_EAX);
3628                                 }
3629                         } else {
3630                                 saved_edx = TRUE;
3631                                 amd64_push_reg (code, X86_EDX);
3632                         }
3633                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3634                         /* save before the check since pop and mov don't change the flags */
3635                         if (ins->dreg != X86_EAX)
3636                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3637                         if (saved_edx)
3638                                 amd64_pop_reg (code, X86_EDX);
3639                         if (saved_eax)
3640                                 amd64_pop_reg (code, X86_EAX);
3641                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3642                         break;
3643                 }
3644                 case OP_ICOMPARE:
3645                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3646                         break;
3647                 case OP_ICOMPARE_IMM:
3648                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3649                         break;
3650                 case OP_IBEQ:
3651                 case OP_IBLT:
3652                 case OP_IBGT:
3653                 case OP_IBGE:
3654                 case OP_IBLE:
3655                 case OP_LBEQ:
3656                 case OP_LBLT:
3657                 case OP_LBGT:
3658                 case OP_LBGE:
3659                 case OP_LBLE:
3660                 case OP_IBNE_UN:
3661                 case OP_IBLT_UN:
3662                 case OP_IBGT_UN:
3663                 case OP_IBGE_UN:
3664                 case OP_IBLE_UN:
3665                 case OP_LBNE_UN:
3666                 case OP_LBLT_UN:
3667                 case OP_LBGT_UN:
3668                 case OP_LBGE_UN:
3669                 case OP_LBLE_UN:
3670                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3671                         break;
3672
3673                 case OP_CMOV_IEQ:
3674                 case OP_CMOV_IGE:
3675                 case OP_CMOV_IGT:
3676                 case OP_CMOV_ILE:
3677                 case OP_CMOV_ILT:
3678                 case OP_CMOV_INE_UN:
3679                 case OP_CMOV_IGE_UN:
3680                 case OP_CMOV_IGT_UN:
3681                 case OP_CMOV_ILE_UN:
3682                 case OP_CMOV_ILT_UN:
3683                 case OP_CMOV_LEQ:
3684                 case OP_CMOV_LGE:
3685                 case OP_CMOV_LGT:
3686                 case OP_CMOV_LLE:
3687                 case OP_CMOV_LLT:
3688                 case OP_CMOV_LNE_UN:
3689                 case OP_CMOV_LGE_UN:
3690                 case OP_CMOV_LGT_UN:
3691                 case OP_CMOV_LLE_UN:
3692                 case OP_CMOV_LLT_UN:
3693                         g_assert (ins->dreg == ins->sreg1);
3694                         /* This needs to operate on 64 bit values */
3695                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3696                         break;
3697
3698                 case OP_LNOT:
3699                         amd64_not_reg (code, ins->sreg1);
3700                         break;
3701                 case OP_LNEG:
3702                         amd64_neg_reg (code, ins->sreg1);
3703                         break;
3704
3705                 case OP_ICONST:
3706                 case OP_I8CONST:
3707                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3708                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3709                         else
3710                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3711                         break;
3712                 case OP_AOTCONST:
3713                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3714                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3715                         break;
3716                 case OP_JUMP_TABLE:
3717                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3718                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3719                         break;
3720                 case OP_MOVE:
3721                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3722                         break;
3723                 case OP_AMD64_SET_XMMREG_R4: {
3724                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3725                         break;
3726                 }
3727                 case OP_AMD64_SET_XMMREG_R8: {
3728                         if (ins->dreg != ins->sreg1)
3729                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3730                         break;
3731                 }
3732                 case OP_JMP:
3733                 case OP_TAILCALL: {
3734                         /*
3735                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3736                          * Keep in sync with the code in emit_epilog.
3737                          */
3738                         int pos = 0, i;
3739
3740                         /* FIXME: no tracing support... */
3741                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3742                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3743
3744                         g_assert (!cfg->method->save_lmf);
3745
3746                         if (ins->opcode == OP_JMP)
3747                                 code = emit_load_volatile_arguments (cfg, code);
3748
3749                         if (cfg->arch.omit_fp) {
3750                                 guint32 save_offset = 0;
3751                                 /* Pop callee-saved registers */
3752                                 for (i = 0; i < AMD64_NREG; ++i)
3753                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3754                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3755                                                 save_offset += 8;
3756                                         }
3757                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3758                         }
3759                         else {
3760                                 for (i = 0; i < AMD64_NREG; ++i)
3761                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3762                                                 pos -= sizeof (gpointer);
3763
3764                                 if (pos)
3765                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3766
3767                                 /* Pop registers in reverse order */
3768                                 for (i = AMD64_NREG - 1; i > 0; --i)
3769                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3770                                                 amd64_pop_reg (code, i);
3771                                         }
3772
3773                                 amd64_leave (code);
3774                         }
3775
3776                         offset = code - cfg->native_code;
3777                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3778                         if (cfg->compile_aot)
3779                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3780                         else
3781                                 amd64_set_reg_template (code, AMD64_R11);
3782                         amd64_jump_reg (code, AMD64_R11);
3783                         break;
3784                 }
3785                 case OP_CHECK_THIS:
3786                         /* ensure ins->sreg1 is not NULL */
3787                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3788                         break;
3789                 case OP_ARGLIST: {
3790                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3791                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3792                         break;
3793                 }
3794                 case OP_CALL:
3795                 case OP_FCALL:
3796                 case OP_LCALL:
3797                 case OP_VCALL:
3798                 case OP_VCALL2:
3799                 case OP_VOIDCALL:
3800                         call = (MonoCallInst*)ins;
3801                         /*
3802                          * The AMD64 ABI forces callers to know about varargs.
3803                          */
3804                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3805                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3806                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3807                                 /*
3808                                  * Since the unmanaged calling convention doesn't contain a
3809                                  * 'vararg' entry, we have to treat every pinvoke call as a
3810                                  * potential vararg call.
3811                                  */
3812                                 guint32 nregs, i;
3813                                 nregs = 0;
3814                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3815                                         if (call->used_fregs & (1 << i))
3816                                                 nregs ++;
3817                                 if (!nregs)
3818                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3819                                 else
3820                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3821                         }
3822
3823                         if (ins->flags & MONO_INST_HAS_METHOD)
3824                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3825                         else
3826                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3827                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3828                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3829                         code = emit_move_return_value (cfg, ins, code);
3830                         break;
3831                 case OP_FCALL_REG:
3832                 case OP_LCALL_REG:
3833                 case OP_VCALL_REG:
3834                 case OP_VCALL2_REG:
3835                 case OP_VOIDCALL_REG:
3836                 case OP_CALL_REG:
3837                         call = (MonoCallInst*)ins;
3838
3839                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3840                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3841                                 ins->sreg1 = AMD64_R11;
3842                         }
3843
3844                         /*
3845                          * The AMD64 ABI forces callers to know about varargs.
3846                          */
3847                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3848                                 if (ins->sreg1 == AMD64_RAX) {
3849                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3850                                         ins->sreg1 = AMD64_R11;
3851                                 }
3852                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3853                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3854                                 /*
3855                                  * Since the unmanaged calling convention doesn't contain a
3856                                  * 'vararg' entry, we have to treat every pinvoke call as a
3857                                  * potential vararg call.
3858                                  */
3859                                 guint32 nregs, i;
3860                                 nregs = 0;
3861                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3862                                         if (call->used_fregs & (1 << i))
3863                                                 nregs ++;
3864                                 if (ins->sreg1 == AMD64_RAX) {
3865                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3866                                         ins->sreg1 = AMD64_R11;
3867                                 }
3868                                 if (!nregs)
3869                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3870                                 else
3871                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3872                         }
3873
3874                         amd64_call_reg (code, ins->sreg1);
3875                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3876                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3877                         code = emit_move_return_value (cfg, ins, code);
3878                         break;
3879                 case OP_FCALL_MEMBASE:
3880                 case OP_LCALL_MEMBASE:
3881                 case OP_VCALL_MEMBASE:
3882                 case OP_VCALL2_MEMBASE:
3883                 case OP_VOIDCALL_MEMBASE:
3884                 case OP_CALL_MEMBASE:
3885                         call = (MonoCallInst*)ins;
3886
3887                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3888                                 /*
3889                                  * Can't use R11 because it is clobbered by the trampoline
3890                                  * code, and the reg value is needed by get_vcall_slot_addr.
3891                                  */
3892                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3893                                 ins->sreg1 = AMD64_RAX;
3894                         }
3895
3896                         if (call->method && ins->inst_offset < 0) {
3897                                 gssize val;
3898
3899                                 /*
3900                                  * This is a possible IMT call so save the IMT method in the proper
3901                                  * register. We don't use the generic code in method-to-ir.c, because
3902                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3903                                  * maintain control over the layout of the code.
3904                                  * Also put the base reg in %rax to simplify find_imt_method ().
3905                                  */
3906                                 if (ins->sreg1 != AMD64_RAX) {
3907                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3908                                         ins->sreg1 = AMD64_RAX;
3909                                 }
3910                                 val = (gssize)(gpointer)call->method;
3911
3912                                 // FIXME: Generics sharing
3913 #if 0
3914                                 if ((((guint64)val) >> 32) == 0)
3915                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3916                                 else
3917                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3918 #endif
3919                         }
3920
3921                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3922                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3923                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3924                         code = emit_move_return_value (cfg, ins, code);
3925                         break;
3926                 case OP_AMD64_SAVE_SP_TO_LMF:
3927                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3928                         break;
3929                 case OP_OUTARG:
3930                 case OP_X86_PUSH:
3931                         amd64_push_reg (code, ins->sreg1);
3932                         break;
3933                 case OP_X86_PUSH_IMM:
3934                         g_assert (amd64_is_imm32 (ins->inst_imm));
3935                         amd64_push_imm (code, ins->inst_imm);
3936                         break;
3937                 case OP_X86_PUSH_MEMBASE:
3938                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3939                         break;
3940                 case OP_X86_PUSH_OBJ:
3941                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3942                         amd64_push_reg (code, AMD64_RDI);
3943                         amd64_push_reg (code, AMD64_RSI);
3944                         amd64_push_reg (code, AMD64_RCX);
3945                         if (ins->inst_offset)
3946                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3947                         else
3948                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3949                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3950                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3951                         amd64_cld (code);
3952                         amd64_prefix (code, X86_REP_PREFIX);
3953                         amd64_movsd (code);
3954                         amd64_pop_reg (code, AMD64_RCX);
3955                         amd64_pop_reg (code, AMD64_RSI);
3956                         amd64_pop_reg (code, AMD64_RDI);
3957                         break;
3958                 case OP_X86_LEA:
3959                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3960                         break;
3961                 case OP_X86_LEA_MEMBASE:
3962                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3963                         break;
3964                 case OP_X86_XCHG:
3965                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3966                         break;
3967                 case OP_LOCALLOC:
3968                         /* keep alignment */
3969                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3970                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3971                         code = mono_emit_stack_alloc (code, ins);
3972                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3973                         break;
3974                 case OP_LOCALLOC_IMM: {
3975                         guint32 size = ins->inst_imm;
3976                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3977
3978                         if (ins->flags & MONO_INST_INIT) {
3979                                 /* FIXME: Optimize this */
3980                                 amd64_mov_reg_imm (code, ins->dreg, size);
3981                                 ins->sreg1 = ins->dreg;
3982
3983                                 code = mono_emit_stack_alloc (code, ins);
3984                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3985                         } else {
3986                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3987                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3988                         }
3989                         break;
3990                 }
3991                 case OP_THROW: {
3992                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3993                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3994                                              (gpointer)"mono_arch_throw_exception", FALSE);
3995                         break;
3996                 }
3997                 case OP_RETHROW: {
3998                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3999                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4000                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4001                         break;
4002                 }
4003                 case OP_CALL_HANDLER:
4004                         /* Align stack */
4005                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4006                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4007                         amd64_call_imm (code, 0);
4008                         /* Restore stack alignment */
4009                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4010                         break;
4011                 case OP_START_HANDLER: {
4012                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4013                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4014                         break;
4015                 }
4016                 case OP_ENDFINALLY: {
4017                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4018                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4019                         amd64_ret (code);
4020                         break;
4021                 }
4022                 case OP_ENDFILTER: {
4023                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4024                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4025                         /* The local allocator will put the result into RAX */
4026                         amd64_ret (code);
4027                         break;
4028                 }
4029
4030                 case OP_LABEL:
4031                         ins->inst_c0 = code - cfg->native_code;
4032                         break;
4033                 case OP_BR:
4034                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4035                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4036                         //break;
4037                         if (ins->flags & MONO_INST_BRLABEL) {
4038                                 if (ins->inst_i0->inst_c0) {
4039                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
4040                                 } else {
4041                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
4042                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4043                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
4044                                                 x86_jump8 (code, 0);
4045                                         else
4046                                                 x86_jump32 (code, 0);
4047                                 }
4048                         } else {
4049                                 if (ins->inst_target_bb->native_offset) {
4050                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4051                                 } else {
4052                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4053                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4054                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
4055                                                 x86_jump8 (code, 0);
4056                                         else
4057                                                 x86_jump32 (code, 0);
4058                                 }
4059                         }
4060                         break;
4061                 case OP_BR_REG:
4062                         amd64_jump_reg (code, ins->sreg1);
4063                         break;
4064                 case OP_CEQ:
4065                 case OP_LCEQ:
4066                 case OP_ICEQ:
4067                 case OP_CLT:
4068                 case OP_LCLT:
4069                 case OP_ICLT:
4070                 case OP_CGT:
4071                 case OP_ICGT:
4072                 case OP_LCGT:
4073                 case OP_CLT_UN:
4074                 case OP_LCLT_UN:
4075                 case OP_ICLT_UN:
4076                 case OP_CGT_UN:
4077                 case OP_LCGT_UN:
4078                 case OP_ICGT_UN:
4079                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4080                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4081                         break;
4082                 case OP_COND_EXC_EQ:
4083                 case OP_COND_EXC_NE_UN:
4084                 case OP_COND_EXC_LT:
4085                 case OP_COND_EXC_LT_UN:
4086                 case OP_COND_EXC_GT:
4087                 case OP_COND_EXC_GT_UN:
4088                 case OP_COND_EXC_GE:
4089                 case OP_COND_EXC_GE_UN:
4090                 case OP_COND_EXC_LE:
4091                 case OP_COND_EXC_LE_UN:
4092                 case OP_COND_EXC_IEQ:
4093                 case OP_COND_EXC_INE_UN:
4094                 case OP_COND_EXC_ILT:
4095                 case OP_COND_EXC_ILT_UN:
4096                 case OP_COND_EXC_IGT:
4097                 case OP_COND_EXC_IGT_UN:
4098                 case OP_COND_EXC_IGE:
4099                 case OP_COND_EXC_IGE_UN:
4100                 case OP_COND_EXC_ILE:
4101                 case OP_COND_EXC_ILE_UN:
4102                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4103                         break;
4104                 case OP_COND_EXC_OV:
4105                 case OP_COND_EXC_NO:
4106                 case OP_COND_EXC_C:
4107                 case OP_COND_EXC_NC:
4108                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4109                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4110                         break;
4111                 case OP_COND_EXC_IOV:
4112                 case OP_COND_EXC_INO:
4113                 case OP_COND_EXC_IC:
4114                 case OP_COND_EXC_INC:
4115                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4116                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4117                         break;
4118
4119                 /* floating point opcodes */
4120                 case OP_R8CONST: {
4121                         double d = *(double *)ins->inst_p0;
4122
4123                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4124                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4125                         }
4126                         else {
4127                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4128                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4129                         }
4130                         break;
4131                 }
4132                 case OP_R4CONST: {
4133                         float f = *(float *)ins->inst_p0;
4134
4135                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4136                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4137                         }
4138                         else {
4139                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4140                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4141                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4142                         }
4143                         break;
4144                 }
4145                 case OP_STORER8_MEMBASE_REG:
4146                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4147                         break;
4148                 case OP_LOADR8_SPILL_MEMBASE:
4149                         g_assert_not_reached ();
4150                         break;
4151                 case OP_LOADR8_MEMBASE:
4152                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4153                         break;
4154                 case OP_STORER4_MEMBASE_REG:
4155                         /* This requires a double->single conversion */
4156                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4157                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4158                         break;
4159                 case OP_LOADR4_MEMBASE:
4160                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4161                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4162                         break;
4163                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4164                 case OP_ICONV_TO_R8:
4165                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4166                         break;
4167                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4168                 case OP_LCONV_TO_R8:
4169                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4170                         break;
4171                 case OP_FCONV_TO_R4:
4172                         /* FIXME: nothing to do ?? */
4173                         break;
4174                 case OP_FCONV_TO_I1:
4175                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4176                         break;
4177                 case OP_FCONV_TO_U1:
4178                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4179                         break;
4180                 case OP_FCONV_TO_I2:
4181                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4182                         break;
4183                 case OP_FCONV_TO_U2:
4184                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4185                         break;
4186                 case OP_FCONV_TO_U4:
4187                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4188                         break;
4189                 case OP_FCONV_TO_I4:
4190                 case OP_FCONV_TO_I:
4191                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4192                         break;
4193                 case OP_FCONV_TO_I8:
4194                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4195                         break;
4196                 case OP_LCONV_TO_R_UN: {
4197                         guint8 *br [2];
4198
4199                         /* Based on gcc code */
4200                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4201                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4202
4203                         /* Positive case */
4204                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4205                         br [1] = code; x86_jump8 (code, 0);
4206                         amd64_patch (br [0], code);
4207
4208                         /* Negative case */
4209                         /* Save to the red zone */
4210                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4211                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4212                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4213                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4214                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4215                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4216                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4217                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4218                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4219                         /* Restore */
4220                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4221                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4222                         amd64_patch (br [1], code);
4223                         break;
4224                 }
4225                 case OP_LCONV_TO_OVF_U4:
4226                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4227                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4228                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4229                         break;
4230                 case OP_LCONV_TO_OVF_I4_UN:
4231                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4232                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4233                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4234                         break;
4235                 case OP_FMOVE:
4236                         if (ins->dreg != ins->sreg1)
4237                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4238                         break;
4239                 case OP_FADD:
4240                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4241                         break;
4242                 case OP_FSUB:
4243                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4244                         break;
4245                 case OP_FMUL:
4246                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4247                         break;
4248                 case OP_FDIV:
4249                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4250                         break;
4251                 case OP_FNEG: {
4252                         static double r8_0 = -0.0;
4253
4254                         g_assert (ins->sreg1 == ins->dreg);
4255
4256                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4257                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4258                         break;
4259                 }
4260                 case OP_SIN:
4261                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4262                         break;
4263                 case OP_COS:
4264                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4265                         break;
4266                 case OP_ABS: {
4267                         static guint64 d = 0x7fffffffffffffffUL;
4268
4269                         g_assert (ins->sreg1 == ins->dreg);
4270
4271                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4272                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4273                         break;
4274                 }
4275                 case OP_SQRT:
4276                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4277                         break;
4278                 case OP_IMIN:
4279                         g_assert (cfg->opt & MONO_OPT_CMOV);
4280                         g_assert (ins->dreg == ins->sreg1);
4281                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4282                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4283                         break;
4284                 case OP_IMIN_UN:
4285                         g_assert (cfg->opt & MONO_OPT_CMOV);
4286                         g_assert (ins->dreg == ins->sreg1);
4287                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4288                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4289                         break;
4290                 case OP_IMAX:
4291                         g_assert (cfg->opt & MONO_OPT_CMOV);
4292                         g_assert (ins->dreg == ins->sreg1);
4293                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4294                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4295                         break;
4296                 case OP_IMAX_UN:
4297                         g_assert (cfg->opt & MONO_OPT_CMOV);
4298                         g_assert (ins->dreg == ins->sreg1);
4299                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4300                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4301                         break;
4302                 case OP_LMIN:
4303                         g_assert (cfg->opt & MONO_OPT_CMOV);
4304                         g_assert (ins->dreg == ins->sreg1);
4305                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4306                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4307                         break;
4308                 case OP_LMIN_UN:
4309                         g_assert (cfg->opt & MONO_OPT_CMOV);
4310                         g_assert (ins->dreg == ins->sreg1);
4311                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4312                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4313                         break;
4314                 case OP_LMAX:
4315                         g_assert (cfg->opt & MONO_OPT_CMOV);
4316                         g_assert (ins->dreg == ins->sreg1);
4317                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4318                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4319                         break;
4320                 case OP_LMAX_UN:
4321                         g_assert (cfg->opt & MONO_OPT_CMOV);
4322                         g_assert (ins->dreg == ins->sreg1);
4323                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4324                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4325                         break;
4326                 case OP_X86_FPOP:
4327                         break;
4328                 case OP_FCOMPARE:
4329                         /*
4330                          * The two arguments are swapped because the fbranch instructions
4331                          * depend on this for the non-sse case to work.
4332                          */
4333                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4334                         break;
4335                 case OP_FCEQ: {
4336                         /* zeroing the register at the start results in
4337                          * shorter and faster code (we can also remove the widening op)
4338                          */
4339                         guchar *unordered_check;
4340                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4341                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4342                         unordered_check = code;
4343                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4344                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4345                         amd64_patch (unordered_check, code);
4346                         break;
4347                 }
4348                 case OP_FCLT:
4349                 case OP_FCLT_UN:
4350                         /* zeroing the register at the start results in
4351                          * shorter and faster code (we can also remove the widening op)
4352                          */
4353                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4354                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4355                         if (ins->opcode == OP_FCLT_UN) {
4356                                 guchar *unordered_check = code;
4357                                 guchar *jump_to_end;
4358                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4359                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4360                                 jump_to_end = code;
4361                                 x86_jump8 (code, 0);
4362                                 amd64_patch (unordered_check, code);
4363                                 amd64_inc_reg (code, ins->dreg);
4364                                 amd64_patch (jump_to_end, code);
4365                         } else {
4366                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4367                         }
4368                         break;
4369                 case OP_FCGT:
4370                 case OP_FCGT_UN: {
4371                         /* zeroing the register at the start results in
4372                          * shorter and faster code (we can also remove the widening op)
4373                          */
4374                         guchar *unordered_check;
4375                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4376                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4377                         if (ins->opcode == OP_FCGT) {
4378                                 unordered_check = code;
4379                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4380                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4381                                 amd64_patch (unordered_check, code);
4382                         } else {
4383                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4384                         }
4385                         break;
4386                 }
4387                 case OP_FCLT_MEMBASE:
4388                 case OP_FCGT_MEMBASE:
4389                 case OP_FCLT_UN_MEMBASE:
4390                 case OP_FCGT_UN_MEMBASE:
4391                 case OP_FCEQ_MEMBASE: {
4392                         guchar *unordered_check, *jump_to_end;
4393                         int x86_cond;
4394
4395                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4396                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4397
4398                         switch (ins->opcode) {
4399                         case OP_FCEQ_MEMBASE:
4400                                 x86_cond = X86_CC_EQ;
4401                                 break;
4402                         case OP_FCLT_MEMBASE:
4403                         case OP_FCLT_UN_MEMBASE:
4404                                 x86_cond = X86_CC_LT;
4405                                 break;
4406                         case OP_FCGT_MEMBASE:
4407                         case OP_FCGT_UN_MEMBASE:
4408                                 x86_cond = X86_CC_GT;
4409                                 break;
4410                         default:
4411                                 g_assert_not_reached ();
4412                         }
4413
4414                         unordered_check = code;
4415                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4416                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4417
4418                         switch (ins->opcode) {
4419                         case OP_FCEQ_MEMBASE:
4420                         case OP_FCLT_MEMBASE:
4421                         case OP_FCGT_MEMBASE:
4422                                 amd64_patch (unordered_check, code);
4423                                 break;
4424                         case OP_FCLT_UN_MEMBASE:
4425                         case OP_FCGT_UN_MEMBASE:
4426                                 jump_to_end = code;
4427                                 x86_jump8 (code, 0);
4428                                 amd64_patch (unordered_check, code);
4429                                 amd64_inc_reg (code, ins->dreg);
4430                                 amd64_patch (jump_to_end, code);
4431                                 break;
4432                         default:
4433                                 break;
4434                         }
4435                         break;
4436                 }
4437                 case OP_FBEQ: {
4438                         guchar *jump = code;
4439                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4440                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4441                         amd64_patch (jump, code);
4442                         break;
4443                 }
4444                 case OP_FBNE_UN:
4445                         /* Branch if C013 != 100 */
4446                         /* branch if !ZF or (PF|CF) */
4447                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4448                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4449                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4450                         break;
4451                 case OP_FBLT:
4452                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4453                         break;
4454                 case OP_FBLT_UN:
4455                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4456                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4457                         break;
4458                 case OP_FBGT:
4459                 case OP_FBGT_UN:
4460                         if (ins->opcode == OP_FBGT) {
4461                                 guchar *br1;
4462
4463                                 /* skip branch if C1=1 */
4464                                 br1 = code;
4465                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4466                                 /* branch if (C0 | C3) = 1 */
4467                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4468                                 amd64_patch (br1, code);
4469                                 break;
4470                         } else {
4471                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4472                         }
4473                         break;
4474                 case OP_FBGE: {
4475                         /* Branch if C013 == 100 or 001 */
4476                         guchar *br1;
4477
4478                         /* skip branch if C1=1 */
4479                         br1 = code;
4480                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4481                         /* branch if (C0 | C3) = 1 */
4482                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4483                         amd64_patch (br1, code);
4484                         break;
4485                 }
4486                 case OP_FBGE_UN:
4487                         /* Branch if C013 == 000 */
4488                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4489                         break;
4490                 case OP_FBLE: {
4491                         /* Branch if C013=000 or 100 */
4492                         guchar *br1;
4493
4494                         /* skip branch if C1=1 */
4495                         br1 = code;
4496                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4497                         /* branch if C0=0 */
4498                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4499                         amd64_patch (br1, code);
4500                         break;
4501                 }
4502                 case OP_FBLE_UN:
4503                         /* Branch if C013 != 001 */
4504                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4505                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4506                         break;
4507                 case OP_CKFINITE:
4508                         /* Transfer value to the fp stack */
4509                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4510                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4511                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4512
4513                         amd64_push_reg (code, AMD64_RAX);
4514                         amd64_fxam (code);
4515                         amd64_fnstsw (code);
4516                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4517                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4518                         amd64_pop_reg (code, AMD64_RAX);
4519                         amd64_fstp (code, 0);
4520                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4521                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4522                         break;
4523                 case OP_TLS_GET: {
4524                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4525                         break;
4526                 }
4527                 case OP_MEMORY_BARRIER: {
4528                         /* Not needed on amd64 */
4529                         break;
4530                 }
4531                 case OP_ATOMIC_ADD_I4:
4532                 case OP_ATOMIC_ADD_I8: {
4533                         int dreg = ins->dreg;
4534                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4535
4536                         if (dreg == ins->inst_basereg)
4537                                 dreg = AMD64_R11;
4538
4539                         if (dreg != ins->sreg2)
4540                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4541
4542                         x86_prefix (code, X86_LOCK_PREFIX);
4543                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4544
4545                         if (dreg != ins->dreg)
4546                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4547
4548                         break;
4549                 }
4550                 case OP_ATOMIC_ADD_NEW_I4:
4551                 case OP_ATOMIC_ADD_NEW_I8: {
4552                         int dreg = ins->dreg;
4553                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4554
4555                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4556                                 dreg = AMD64_R11;
4557
4558                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4559                         amd64_prefix (code, X86_LOCK_PREFIX);
4560                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4561                         /* dreg contains the old value, add with sreg2 value */
4562                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4563
4564                         if (ins->dreg != dreg)
4565                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4566
4567                         break;
4568                 }
4569                 case OP_ATOMIC_EXCHANGE_I4:
4570                 case OP_ATOMIC_EXCHANGE_I8:
4571                 case OP_ATOMIC_CAS_IMM_I4: {
4572                         guchar *br[2];
4573                         int sreg2 = ins->sreg2;
4574                         int breg = ins->inst_basereg;
4575                         guint32 size;
4576                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4577
4578                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4579                                 size = 8;
4580                         else
4581                                 size = 4;
4582
4583                         /*
4584                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4585                          * an explanation of how this works.
4586                          */
4587
4588                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4589                          * hack to overcome limits in x86 reg allocator
4590                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4591                          */
4592                         g_assert (ins->dreg == AMD64_RAX);
4593
4594                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4595                                 /* Highly unlikely, but possible */
4596                                 need_push = TRUE;
4597
4598                         /* The pushes invalidate rsp */
4599                         if ((breg == AMD64_RAX) || need_push) {
4600                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4601                                 breg = AMD64_R11;
4602                         }
4603
4604                         /* We need the EAX reg for the comparand */
4605                         if (ins->sreg2 == AMD64_RAX) {
4606                                 if (breg != AMD64_R11) {
4607                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4608                                         sreg2 = AMD64_R11;
4609                                 } else {
4610                                         g_assert (need_push);
4611                                         amd64_push_reg (code, AMD64_RDX);
4612                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4613                                         sreg2 = AMD64_RDX;
4614                                         rdx_pushed = TRUE;
4615                                 }
4616                         }
4617
4618                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4619                                 if (ins->backend.data == NULL)
4620                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4621                                 else
4622                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4623
4624                                 amd64_prefix (code, X86_LOCK_PREFIX);
4625                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4626                         } else {
4627                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4628
4629                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4630                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4631                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4632                                 amd64_patch (br [1], br [0]);
4633                         }
4634
4635                         if (rdx_pushed)
4636                                 amd64_pop_reg (code, AMD64_RDX);
4637
4638                         break;
4639                 }
4640                 default:
4641                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4642                         g_assert_not_reached ();
4643                 }
4644
4645                 if ((code - cfg->native_code - offset) > max_len) {
4646                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4647                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4648                         g_assert_not_reached ();
4649                 }
4650
4651                 cpos += max_len;
4652
4653                 last_ins = ins;
4654                 last_offset = offset;
4655         }
4656
4657         cfg->code_len = code - cfg->native_code;
4658 }
4659
4660 void
4661 mono_arch_register_lowlevel_calls (void)
4662 {
4663         /* The signature doesn't matter */
4664         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4665 }
4666
4667 void
4668 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4669 {
4670         MonoJumpInfo *patch_info;
4671         gboolean compile_aot = !run_cctors;
4672
4673         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4674                 unsigned char *ip = patch_info->ip.i + code;
4675                 unsigned char *target;
4676
4677                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4678
4679                 if (compile_aot) {
4680                         switch (patch_info->type) {
4681                         case MONO_PATCH_INFO_BB:
4682                         case MONO_PATCH_INFO_LABEL:
4683                                 break;
4684                         default:
4685                                 /* No need to patch these */
4686                                 continue;
4687                         }
4688                 }
4689
4690                 switch (patch_info->type) {
4691                 case MONO_PATCH_INFO_NONE:
4692                         continue;
4693                 case MONO_PATCH_INFO_METHOD_REL:
4694                 case MONO_PATCH_INFO_R8:
4695                 case MONO_PATCH_INFO_R4:
4696                         g_assert_not_reached ();
4697                         continue;
4698                 case MONO_PATCH_INFO_BB:
4699                         break;
4700                 default:
4701                         break;
4702                 }
4703
4704                 /*
4705                  * Debug code to help track down problems where the target of a near call is
4706                  * is not valid.
4707                  */
4708                 if (amd64_is_near_call (ip)) {
4709                         gint64 disp = (guint8*)target - (guint8*)ip;
4710
4711                         if (!amd64_is_imm32 (disp)) {
4712                                 printf ("TYPE: %d\n", patch_info->type);
4713                                 switch (patch_info->type) {
4714                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4715                                         printf ("V: %s\n", patch_info->data.name);
4716                                         break;
4717                                 case MONO_PATCH_INFO_METHOD_JUMP:
4718                                 case MONO_PATCH_INFO_METHOD:
4719                                         printf ("V: %s\n", patch_info->data.method->name);
4720                                         break;
4721                                 default:
4722                                         break;
4723                                 }
4724                         }
4725                 }
4726
4727                 amd64_patch (ip, (gpointer)target);
4728         }
4729 }
4730
4731 static int
4732 get_max_epilog_size (MonoCompile *cfg)
4733 {
4734         int max_epilog_size = 16;
4735
4736         if (cfg->method->save_lmf)
4737                 max_epilog_size += 256;
4738
4739         if (mono_jit_trace_calls != NULL)
4740                 max_epilog_size += 50;
4741
4742         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4743                 max_epilog_size += 50;
4744
4745         max_epilog_size += (AMD64_NREG * 2);
4746
4747         return max_epilog_size;
4748 }
4749
4750 /*
4751  * This macro is used for testing whenever the unwinder works correctly at every point
4752  * where an async exception can happen.
4753  */
4754 /* This will generate a SIGSEGV at the given point in the code */
4755 #define async_exc_point(code) do { \
4756     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4757          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4758              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4759          cfg->arch.async_point_count ++; \
4760     } \
4761 } while (0)
4762
4763 guint8 *
4764 mono_arch_emit_prolog (MonoCompile *cfg)
4765 {
4766         MonoMethod *method = cfg->method;
4767         MonoBasicBlock *bb;
4768         MonoMethodSignature *sig;
4769         MonoInst *ins;
4770         int alloc_size, pos, max_offset, i, quad, max_epilog_size;
4771         guint8 *code;
4772         CallInfo *cinfo;
4773         gint32 lmf_offset = cfg->arch.lmf_offset;
4774         gboolean args_clobbered = FALSE;
4775         gboolean trace = FALSE;
4776
4777         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4778
4779         code = cfg->native_code = g_malloc (cfg->code_size);
4780
4781         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4782                 trace = TRUE;
4783
4784         /* Amount of stack space allocated by register saving code */
4785         pos = 0;
4786
4787         /*
4788          * The prolog consists of the following parts:
4789          * FP present:
4790          * - push rbp, mov rbp, rsp
4791          * - save callee saved regs using pushes
4792          * - allocate frame
4793          * - save rgctx if needed
4794          * - save lmf if needed
4795          * FP not present:
4796          * - allocate frame
4797          * - save rgctx if needed
4798          * - save lmf if needed
4799          * - save callee saved regs using moves
4800          */
4801
4802         async_exc_point (code);
4803
4804         if (!cfg->arch.omit_fp) {
4805                 amd64_push_reg (code, AMD64_RBP);
4806                 async_exc_point (code);
4807 #ifdef PLATFORM_WIN32
4808                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4809 #endif
4810
4811                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4812                 async_exc_point (code);
4813 #ifdef PLATFORM_WIN32
4814                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4815 #endif
4816         }
4817
4818         /* Save callee saved registers */
4819         if (!cfg->arch.omit_fp && !method->save_lmf) {
4820                 for (i = 0; i < AMD64_NREG; ++i)
4821                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4822                                 amd64_push_reg (code, i);
4823                                 pos += sizeof (gpointer);
4824                                 async_exc_point (code);
4825                         }
4826         }
4827
4828         if (cfg->arch.omit_fp) {
4829                 /*
4830                  * On enter, the stack is misaligned by the the pushing of the return
4831                  * address. It is either made aligned by the pushing of %rbp, or by
4832                  * this.
4833                  */
4834                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4835                 if ((alloc_size % 16) == 0)
4836                         alloc_size += 8;
4837         } else {
4838                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4839
4840                 alloc_size -= pos;
4841         }
4842
4843         cfg->arch.stack_alloc_size = alloc_size;
4844
4845         /* Allocate stack frame */
4846         if (alloc_size) {
4847                 /* See mono_emit_stack_alloc */
4848 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4849                 guint32 remaining_size = alloc_size;
4850                 while (remaining_size >= 0x1000) {
4851                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4852                         async_exc_point (code);
4853 #ifdef PLATFORM_WIN32
4854                         if (cfg->arch.omit_fp)
4855                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4856 #endif
4857
4858                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4859                         remaining_size -= 0x1000;
4860                 }
4861                 if (remaining_size) {
4862                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4863                         async_exc_point (code);
4864 #ifdef PLATFORM_WIN32
4865                         if (cfg->arch.omit_fp)
4866                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4867 #endif
4868                 }
4869 #else
4870                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4871                 async_exc_point (code);
4872 #endif
4873         }
4874
4875         /* Stack alignment check */
4876 #if 0
4877         {
4878                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4879                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4880                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4881                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4882                 amd64_breakpoint (code);
4883         }
4884 #endif
4885
4886         /* Save LMF */
4887         if (method->save_lmf) {
4888                 /*
4889                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4890                  */
4891                 /* sp is saved right before calls */
4892                 /* Skip method (only needed for trampoline LMF frames) */
4893                 /* Save callee saved regs */
4894                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4895                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4896                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4897                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4898                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4899                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4900         }
4901
4902         /* Save callee saved registers */
4903         if (cfg->arch.omit_fp && !method->save_lmf) {
4904                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4905
4906                 /* Save caller saved registers after sp is adjusted */
4907                 /* The registers are saved at the bottom of the frame */
4908                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4909                 for (i = 0; i < AMD64_NREG; ++i)
4910                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4911                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4912                                 save_area_offset += 8;
4913                                 async_exc_point (code);
4914                         }
4915         }
4916
4917         /* store runtime generic context */
4918         if (cfg->rgctx_var) {
4919                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4920                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4921
4922                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4923         }
4924
4925         /* compute max_offset in order to use short forward jumps */
4926         max_offset = 0;
4927         max_epilog_size = get_max_epilog_size (cfg);
4928         if (cfg->opt & MONO_OPT_BRANCH) {
4929                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4930                         MonoInst *ins;
4931                         bb->max_offset = max_offset;
4932
4933                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4934                                 max_offset += 6;
4935                         /* max alignment for loops */
4936                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4937                                 max_offset += LOOP_ALIGNMENT;
4938
4939                         MONO_BB_FOR_EACH_INS (bb, ins) {
4940                                 if (ins->opcode == OP_LABEL)
4941                                         ins->inst_c1 = max_offset;
4942
4943                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4944                         }
4945
4946                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4947                                 /* The tracing code can be quite large */
4948                                 max_offset += max_epilog_size;
4949                 }
4950         }
4951
4952         sig = mono_method_signature (method);
4953         pos = 0;
4954
4955         cinfo = cfg->arch.cinfo;
4956
4957         if (sig->ret->type != MONO_TYPE_VOID) {
4958                 /* Save volatile arguments to the stack */
4959                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4960                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4961         }
4962
4963         /* Keep this in sync with emit_load_volatile_arguments */
4964         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4965                 ArgInfo *ainfo = cinfo->args + i;
4966                 gint32 stack_offset;
4967                 MonoType *arg_type;
4968
4969                 ins = cfg->args [i];
4970
4971                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4972                         /* Unused arguments */
4973                         continue;
4974
4975                 if (sig->hasthis && (i == 0))
4976                         arg_type = &mono_defaults.object_class->byval_arg;
4977                 else
4978                         arg_type = sig->params [i - sig->hasthis];
4979
4980                 stack_offset = ainfo->offset + ARGS_OFFSET;
4981
4982                 if (cfg->globalra) {
4983                         /* All the other moves are done by the register allocator */
4984                         switch (ainfo->storage) {
4985                         case ArgInFloatSSEReg:
4986                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
4987                                 break;
4988                         case ArgValuetypeInReg:
4989                                 for (quad = 0; quad < 2; quad ++) {
4990                                         switch (ainfo->pair_storage [quad]) {
4991                                         case ArgInIReg:
4992                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4993                                                 break;
4994                                         case ArgInFloatSSEReg:
4995                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4996                                                 break;
4997                                         case ArgInDoubleSSEReg:
4998                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4999                                                 break;
5000                                         case ArgNone:
5001                                                 break;
5002                                         default:
5003                                                 g_assert_not_reached ();
5004                                         }
5005                                 }
5006                                 break;
5007                         default:
5008                                 break;
5009                         }
5010
5011                         continue;
5012                 }
5013
5014                 /* Save volatile arguments to the stack */
5015                 if (ins->opcode != OP_REGVAR) {
5016                         switch (ainfo->storage) {
5017                         case ArgInIReg: {
5018                                 guint32 size = 8;
5019
5020                                 /* FIXME: I1 etc */
5021                                 /*
5022                                 if (stack_offset & 0x1)
5023                                         size = 1;
5024                                 else if (stack_offset & 0x2)
5025                                         size = 2;
5026                                 else if (stack_offset & 0x4)
5027                                         size = 4;
5028                                 else
5029                                         size = 8;
5030                                 */
5031                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5032                                 break;
5033                         }
5034                         case ArgInFloatSSEReg:
5035                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5036                                 break;
5037                         case ArgInDoubleSSEReg:
5038                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5039                                 break;
5040                         case ArgValuetypeInReg:
5041                                 for (quad = 0; quad < 2; quad ++) {
5042                                         switch (ainfo->pair_storage [quad]) {
5043                                         case ArgInIReg:
5044                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5045                                                 break;
5046                                         case ArgInFloatSSEReg:
5047                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5048                                                 break;
5049                                         case ArgInDoubleSSEReg:
5050                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5051                                                 break;
5052                                         case ArgNone:
5053                                                 break;
5054                                         default:
5055                                                 g_assert_not_reached ();
5056                                         }
5057                                 }
5058                                 break;
5059                         case ArgValuetypeAddrInIReg:
5060                                 if (ainfo->pair_storage [0] == ArgInIReg)
5061                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5062                                 break;
5063                         default:
5064                                 break;
5065                         }
5066                 } else {
5067                         /* Argument allocated to (non-volatile) register */
5068                         switch (ainfo->storage) {
5069                         case ArgInIReg:
5070                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5071                                 break;
5072                         case ArgOnStack:
5073                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5074                                 break;
5075                         default:
5076                                 g_assert_not_reached ();
5077                         }
5078                 }
5079         }
5080
5081         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5082         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5083                 guint64 domain = (guint64)cfg->domain;
5084
5085                 args_clobbered = TRUE;
5086
5087                 /*
5088                  * The call might clobber argument registers, but they are already
5089                  * saved to the stack/global regs.
5090                  */
5091                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5092                         guint8 *buf, *no_domain_branch;
5093
5094                         code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5095                         if ((domain >> 32) == 0)
5096                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5097                         else
5098                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5099                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5100                         no_domain_branch = code;
5101                         x86_branch8 (code, X86_CC_NE, 0, 0);
5102                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5103                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5104                         buf = code;
5105                         x86_branch8 (code, X86_CC_NE, 0, 0);
5106                         amd64_patch (no_domain_branch, code);
5107                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5108                                           (gpointer)"mono_jit_thread_attach", TRUE);
5109                         amd64_patch (buf, code);
5110 #ifdef PLATFORM_WIN32
5111                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5112                         /* FIXME: Add a separate key for LMF to avoid this */
5113                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5114 #endif
5115                 } else {
5116                         g_assert (!cfg->compile_aot);
5117                         if ((domain >> 32) == 0)
5118                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5119                         else
5120                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5121                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5122                                           (gpointer)"mono_jit_thread_attach", TRUE);
5123                 }
5124         }
5125
5126         if (method->save_lmf) {
5127                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5128                         /*
5129                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5130                          * through the mono_lmf_addr TLS variable.
5131                          */
5132                         /* %rax = previous_lmf */
5133                         x86_prefix (code, X86_FS_PREFIX);
5134                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5135
5136                         /* Save previous_lmf */
5137                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5138                         /* Set new lmf */
5139                         if (lmf_offset == 0) {
5140                                 x86_prefix (code, X86_FS_PREFIX);
5141                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5142                         } else {
5143                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5144                                 x86_prefix (code, X86_FS_PREFIX);
5145                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5146                         }
5147                 } else {
5148                         if (lmf_addr_tls_offset != -1) {
5149                                 /* Load lmf quicky using the FS register */
5150                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5151 #ifdef PLATFORM_WIN32
5152                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5153                                 /* FIXME: Add a separate key for LMF to avoid this */
5154                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5155 #endif
5156                         }
5157                         else {
5158                                 /*
5159                                  * The call might clobber argument registers, but they are already
5160                                  * saved to the stack/global regs.
5161                                  */
5162                                 args_clobbered = TRUE;
5163                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5164                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
5165                         }
5166
5167                         /* Save lmf_addr */
5168                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5169                         /* Save previous_lmf */
5170                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5171                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5172                         /* Set new lmf */
5173                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5174                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5175                 }
5176         }
5177
5178         if (trace) {
5179                 args_clobbered = TRUE;
5180                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5181         }
5182
5183         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5184                 args_clobbered = TRUE;
5185
5186         /*
5187          * Optimize the common case of the first bblock making a call with the same
5188          * arguments as the method. This works because the arguments are still in their
5189          * original argument registers.
5190          * FIXME: Generalize this
5191          */
5192         if (!args_clobbered) {
5193                 MonoBasicBlock *first_bb = cfg->bb_entry;
5194                 MonoInst *next;
5195
5196                 next = mono_bb_first_ins (first_bb);
5197                 if (!next && first_bb->next_bb) {
5198                         first_bb = first_bb->next_bb;
5199                         next = mono_bb_first_ins (first_bb);
5200                 }
5201
5202                 if (first_bb->in_count > 1)
5203                         next = NULL;
5204
5205                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5206                         ArgInfo *ainfo = cinfo->args + i;
5207                         gboolean match = FALSE;
5208
5209                         ins = cfg->args [i];
5210                         if (ins->opcode != OP_REGVAR) {
5211                                 switch (ainfo->storage) {
5212                                 case ArgInIReg: {
5213                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5214                                                 if (next->dreg == ainfo->reg) {
5215                                                         NULLIFY_INS (next);
5216                                                         match = TRUE;
5217                                                 } else {
5218                                                         next->opcode = OP_MOVE;
5219                                                         next->sreg1 = ainfo->reg;
5220                                                         /* Only continue if the instruction doesn't change argument regs */
5221                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5222                                                                 match = TRUE;
5223                                                 }
5224                                         }
5225                                         break;
5226                                 }
5227                                 default:
5228                                         break;
5229                                 }
5230                         } else {
5231                                 /* Argument allocated to (non-volatile) register */
5232                                 switch (ainfo->storage) {
5233                                 case ArgInIReg:
5234                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5235                                                 NULLIFY_INS (next);
5236                                                 match = TRUE;
5237                                         }
5238                                         break;
5239                                 default:
5240                                         break;
5241                                 }
5242                         }
5243
5244                         if (match) {
5245                                 next = next->next;
5246                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5247                                 if (!next)
5248                                         break;
5249                         }
5250                 }
5251         }
5252
5253         cfg->code_len = code - cfg->native_code;
5254
5255         g_assert (cfg->code_len < cfg->code_size);
5256
5257         return code;
5258 }
5259
5260 void
5261 mono_arch_emit_epilog (MonoCompile *cfg)
5262 {
5263         MonoMethod *method = cfg->method;
5264         int quad, pos, i;
5265         guint8 *code;
5266         int max_epilog_size;
5267         CallInfo *cinfo;
5268         gint32 lmf_offset = cfg->arch.lmf_offset;
5269
5270         max_epilog_size = get_max_epilog_size (cfg);
5271
5272         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5273                 cfg->code_size *= 2;
5274                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5275                 mono_jit_stats.code_reallocs++;
5276         }
5277
5278         code = cfg->native_code + cfg->code_len;
5279
5280         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5281                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5282
5283         /* the code restoring the registers must be kept in sync with OP_JMP */
5284         pos = 0;
5285
5286         if (method->save_lmf) {
5287                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5288                         /*
5289                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5290                          * through the mono_lmf_addr TLS variable.
5291                          */
5292                         /* reg = previous_lmf */
5293                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5294                         x86_prefix (code, X86_FS_PREFIX);
5295                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5296                 } else {
5297                         /* Restore previous lmf */
5298                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5299                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5300                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5301                 }
5302
5303                 /* Restore caller saved regs */
5304                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5305                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5306                 }
5307                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5308                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5309                 }
5310                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5311                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5312                 }
5313                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5314                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5315                 }
5316                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5317                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5318                 }
5319                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5320                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5321                 }
5322         } else {
5323
5324                 if (cfg->arch.omit_fp) {
5325                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5326
5327                         for (i = 0; i < AMD64_NREG; ++i)
5328                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5329                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5330                                         save_area_offset += 8;
5331                                 }
5332                 }
5333                 else {
5334                         for (i = 0; i < AMD64_NREG; ++i)
5335                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5336                                         pos -= sizeof (gpointer);
5337
5338                         if (pos) {
5339                                 if (pos == - sizeof (gpointer)) {
5340                                         /* Only one register, so avoid lea */
5341                                         for (i = AMD64_NREG - 1; i > 0; --i)
5342                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5343                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5344                                                 }
5345                                 }
5346                                 else {
5347                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5348
5349                                         /* Pop registers in reverse order */
5350                                         for (i = AMD64_NREG - 1; i > 0; --i)
5351                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5352                                                         amd64_pop_reg (code, i);
5353                                                 }
5354                                 }
5355                         }
5356                 }
5357         }
5358
5359         /* Load returned vtypes into registers if needed */
5360         cinfo = cfg->arch.cinfo;
5361         if (cinfo->ret.storage == ArgValuetypeInReg) {
5362                 ArgInfo *ainfo = &cinfo->ret;
5363                 MonoInst *inst = cfg->ret;
5364
5365                 for (quad = 0; quad < 2; quad ++) {
5366                         switch (ainfo->pair_storage [quad]) {
5367                         case ArgInIReg:
5368                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5369                                 break;
5370                         case ArgInFloatSSEReg:
5371                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5372                                 break;
5373                         case ArgInDoubleSSEReg:
5374                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5375                                 break;
5376                         case ArgNone:
5377                                 break;
5378                         default:
5379                                 g_assert_not_reached ();
5380                         }
5381                 }
5382         }
5383
5384         if (cfg->arch.omit_fp) {
5385                 if (cfg->arch.stack_alloc_size)
5386                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5387         } else {
5388                 amd64_leave (code);
5389         }
5390         async_exc_point (code);
5391         amd64_ret (code);
5392
5393         cfg->code_len = code - cfg->native_code;
5394
5395         g_assert (cfg->code_len < cfg->code_size);
5396
5397         if (cfg->arch.omit_fp) {
5398                 /*
5399                  * Encode the stack size into used_int_regs so the exception handler
5400                  * can access it.
5401                  */
5402                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5403                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5404         }
5405 }
5406
5407 void
5408 mono_arch_emit_exceptions (MonoCompile *cfg)
5409 {
5410         MonoJumpInfo *patch_info;
5411         int nthrows, i;
5412         guint8 *code;
5413         MonoClass *exc_classes [16];
5414         guint8 *exc_throw_start [16], *exc_throw_end [16];
5415         guint32 code_size = 0;
5416
5417         /* Compute needed space */
5418         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5419                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5420                         code_size += 40;
5421                 if (patch_info->type == MONO_PATCH_INFO_R8)
5422                         code_size += 8 + 15; /* sizeof (double) + alignment */
5423                 if (patch_info->type == MONO_PATCH_INFO_R4)
5424                         code_size += 4 + 15; /* sizeof (float) + alignment */
5425         }
5426
5427         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5428                 cfg->code_size *= 2;
5429                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5430                 mono_jit_stats.code_reallocs++;
5431         }
5432
5433         code = cfg->native_code + cfg->code_len;
5434
5435         /* add code to raise exceptions */
5436         nthrows = 0;
5437         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5438                 switch (patch_info->type) {
5439                 case MONO_PATCH_INFO_EXC: {
5440                         MonoClass *exc_class;
5441                         guint8 *buf, *buf2;
5442                         guint32 throw_ip;
5443
5444                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5445
5446                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5447                         g_assert (exc_class);
5448                         throw_ip = patch_info->ip.i;
5449
5450                         //x86_breakpoint (code);
5451                         /* Find a throw sequence for the same exception class */
5452                         for (i = 0; i < nthrows; ++i)
5453                                 if (exc_classes [i] == exc_class)
5454                                         break;
5455                         if (i < nthrows) {
5456                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5457                                 x86_jump_code (code, exc_throw_start [i]);
5458                                 patch_info->type = MONO_PATCH_INFO_NONE;
5459                         }
5460                         else {
5461                                 buf = code;
5462                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5463                                 buf2 = code;
5464
5465                                 if (nthrows < 16) {
5466                                         exc_classes [nthrows] = exc_class;
5467                                         exc_throw_start [nthrows] = code;
5468                                 }
5469                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5470
5471                                 patch_info->type = MONO_PATCH_INFO_NONE;
5472
5473                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5474
5475                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5476                                 while (buf < buf2)
5477                                         x86_nop (buf);
5478
5479                                 if (nthrows < 16) {
5480                                         exc_throw_end [nthrows] = code;
5481                                         nthrows ++;
5482                                 }
5483                         }
5484                         break;
5485                 }
5486                 default:
5487                         /* do nothing */
5488                         break;
5489                 }
5490         }
5491
5492         /* Handle relocations with RIP relative addressing */
5493         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5494                 gboolean remove = FALSE;
5495
5496                 switch (patch_info->type) {
5497                 case MONO_PATCH_INFO_R8:
5498                 case MONO_PATCH_INFO_R4: {
5499                         guint8 *pos;
5500
5501                         /* The SSE opcodes require a 16 byte alignment */
5502                         code = (guint8*)ALIGN_TO (code, 16);
5503
5504                         pos = cfg->native_code + patch_info->ip.i;
5505
5506                         if (IS_REX (pos [1]))
5507                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5508                         else
5509                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5510
5511                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5512                                 *(double*)code = *(double*)patch_info->data.target;
5513                                 code += sizeof (double);
5514                         } else {
5515                                 *(float*)code = *(float*)patch_info->data.target;
5516                                 code += sizeof (float);
5517                         }
5518
5519                         remove = TRUE;
5520                         break;
5521                 }
5522                 default:
5523                         break;
5524                 }
5525
5526                 if (remove) {
5527                         if (patch_info == cfg->patch_info)
5528                                 cfg->patch_info = patch_info->next;
5529                         else {
5530                                 MonoJumpInfo *tmp;
5531
5532                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5533                                         ;
5534                                 tmp->next = patch_info->next;
5535                         }
5536                 }
5537         }
5538
5539         cfg->code_len = code - cfg->native_code;
5540
5541         g_assert (cfg->code_len < cfg->code_size);
5542
5543 }
5544
5545 void*
5546 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5547 {
5548         guchar *code = p;
5549         CallInfo *cinfo = NULL;
5550         MonoMethodSignature *sig;
5551         MonoInst *inst;
5552         int i, n, stack_area = 0;
5553
5554         /* Keep this in sync with mono_arch_get_argument_info */
5555
5556         if (enable_arguments) {
5557                 /* Allocate a new area on the stack and save arguments there */
5558                 sig = mono_method_signature (cfg->method);
5559
5560                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5561
5562                 n = sig->param_count + sig->hasthis;
5563
5564                 stack_area = ALIGN_TO (n * 8, 16);
5565
5566                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5567
5568                 for (i = 0; i < n; ++i) {
5569                         inst = cfg->args [i];
5570
5571                         if (inst->opcode == OP_REGVAR)
5572                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5573                         else {
5574                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5575                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5576                         }
5577                 }
5578         }
5579
5580         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5581         amd64_set_reg_template (code, AMD64_ARG_REG1);
5582         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5583         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5584
5585         if (enable_arguments)
5586                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5587
5588         return code;
5589 }
5590
5591 enum {
5592         SAVE_NONE,
5593         SAVE_STRUCT,
5594         SAVE_EAX,
5595         SAVE_EAX_EDX,
5596         SAVE_XMM
5597 };
5598
5599 void*
5600 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5601 {
5602         guchar *code = p;
5603         int save_mode = SAVE_NONE;
5604         MonoMethod *method = cfg->method;
5605         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
5606
5607         switch (rtype) {
5608         case MONO_TYPE_VOID:
5609                 /* special case string .ctor icall */
5610                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5611                         save_mode = SAVE_EAX;
5612                 else
5613                         save_mode = SAVE_NONE;
5614                 break;
5615         case MONO_TYPE_I8:
5616         case MONO_TYPE_U8:
5617                 save_mode = SAVE_EAX;
5618                 break;
5619         case MONO_TYPE_R4:
5620         case MONO_TYPE_R8:
5621                 save_mode = SAVE_XMM;
5622                 break;
5623         case MONO_TYPE_GENERICINST:
5624                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5625                         save_mode = SAVE_EAX;
5626                         break;
5627                 }
5628                 /* Fall through */
5629         case MONO_TYPE_VALUETYPE:
5630                 save_mode = SAVE_STRUCT;
5631                 break;
5632         default:
5633                 save_mode = SAVE_EAX;
5634                 break;
5635         }
5636
5637         /* Save the result and copy it into the proper argument register */
5638         switch (save_mode) {
5639         case SAVE_EAX:
5640                 amd64_push_reg (code, AMD64_RAX);
5641                 /* Align stack */
5642                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5643                 if (enable_arguments)
5644                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5645                 break;
5646         case SAVE_STRUCT:
5647                 /* FIXME: */
5648                 if (enable_arguments)
5649                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5650                 break;
5651         case SAVE_XMM:
5652                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5653                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5654                 /* Align stack */
5655                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5656                 /*
5657                  * The result is already in the proper argument register so no copying
5658                  * needed.
5659                  */
5660                 break;
5661         case SAVE_NONE:
5662                 break;
5663         default:
5664                 g_assert_not_reached ();
5665         }
5666
5667         /* Set %al since this is a varargs call */
5668         if (save_mode == SAVE_XMM)
5669                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5670         else
5671                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5672
5673         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5674         amd64_set_reg_template (code, AMD64_ARG_REG1);
5675         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5676
5677         /* Restore result */
5678         switch (save_mode) {
5679         case SAVE_EAX:
5680                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5681                 amd64_pop_reg (code, AMD64_RAX);
5682                 break;
5683         case SAVE_STRUCT:
5684                 /* FIXME: */
5685                 break;
5686         case SAVE_XMM:
5687                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5688                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5689                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5690                 break;
5691         case SAVE_NONE:
5692                 break;
5693         default:
5694                 g_assert_not_reached ();
5695         }
5696
5697         return code;
5698 }
5699
5700 void
5701 mono_arch_flush_icache (guint8 *code, gint size)
5702 {
5703         /* Not needed */
5704 }
5705
5706 void
5707 mono_arch_flush_register_windows (void)
5708 {
5709 }
5710
5711 gboolean
5712 mono_arch_is_inst_imm (gint64 imm)
5713 {
5714         return amd64_is_imm32 (imm);
5715 }
5716
5717 /*
5718  * Determine whenever the trap whose info is in SIGINFO is caused by
5719  * integer overflow.
5720  */
5721 gboolean
5722 mono_arch_is_int_overflow (void *sigctx, void *info)
5723 {
5724         MonoContext ctx;
5725         guint8* rip;
5726         int reg;
5727         gint64 value;
5728
5729         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5730
5731         rip = (guint8*)ctx.rip;
5732
5733         if (IS_REX (rip [0])) {
5734                 reg = amd64_rex_b (rip [0]);
5735                 rip ++;
5736         }
5737         else
5738                 reg = 0;
5739
5740         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5741                 /* idiv REG */
5742                 reg += x86_modrm_rm (rip [1]);
5743
5744                 switch (reg) {
5745                 case AMD64_RAX:
5746                         value = ctx.rax;
5747                         break;
5748                 case AMD64_RBX:
5749                         value = ctx.rbx;
5750                         break;
5751                 case AMD64_RCX:
5752                         value = ctx.rcx;
5753                         break;
5754                 case AMD64_RDX:
5755                         value = ctx.rdx;
5756                         break;
5757                 case AMD64_RBP:
5758                         value = ctx.rbp;
5759                         break;
5760                 case AMD64_RSP:
5761                         value = ctx.rsp;
5762                         break;
5763                 case AMD64_RSI:
5764                         value = ctx.rsi;
5765                         break;
5766                 case AMD64_RDI:
5767                         value = ctx.rdi;
5768                         break;
5769                 case AMD64_R12:
5770                         value = ctx.r12;
5771                         break;
5772                 case AMD64_R13:
5773                         value = ctx.r13;
5774                         break;
5775                 case AMD64_R14:
5776                         value = ctx.r14;
5777                         break;
5778                 case AMD64_R15:
5779                         value = ctx.r15;
5780                         break;
5781                 default:
5782                         g_assert_not_reached ();
5783                         reg = -1;
5784                 }
5785
5786                 if (value == -1)
5787                         return TRUE;
5788         }
5789
5790         return FALSE;
5791 }
5792
5793 guint32
5794 mono_arch_get_patch_offset (guint8 *code)
5795 {
5796         return 3;
5797 }
5798
5799 /**
5800  * mono_breakpoint_clean_code:
5801  *
5802  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5803  * breakpoints in the original code, they are removed in the copy.
5804  *
5805  * Returns TRUE if no sw breakpoint was present.
5806  */
5807 gboolean
5808 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5809 {
5810         int i;
5811         gboolean can_write = TRUE;
5812         /*
5813          * If method_start is non-NULL we need to perform bound checks, since we access memory
5814          * at code - offset we could go before the start of the method and end up in a different
5815          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5816          * instead.
5817          */
5818         if (!method_start || code - offset >= method_start) {
5819                 memcpy (buf, code - offset, size);
5820         } else {
5821                 int diff = code - method_start;
5822                 memset (buf, 0, size);
5823                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5824         }
5825         code -= offset;
5826         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5827                 int idx = mono_breakpoint_info_index [i];
5828                 guint8 *ptr;
5829                 if (idx < 1)
5830                         continue;
5831                 ptr = mono_breakpoint_info [idx].address;
5832                 if (ptr >= code && ptr < code + size) {
5833                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5834                         can_write = FALSE;
5835                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5836                         buf [ptr - code] = saved_byte;
5837                 }
5838         }
5839         return can_write;
5840 }
5841
5842 gpointer
5843 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5844 {
5845         guint8 buf [10];
5846         guint32 reg;
5847         gint32 disp;
5848         guint8 rex = 0;
5849
5850         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5851         code = buf + 9;
5852
5853         *displacement = 0;
5854
5855         /* go to the start of the call instruction
5856          *
5857          * address_byte = (m << 6) | (o << 3) | reg
5858          * call opcode: 0xff address_byte displacement
5859          * 0xff m=1,o=2 imm8
5860          * 0xff m=2,o=2 imm32
5861          */
5862         code -= 7;
5863
5864         /*
5865          * A given byte sequence can match more than case here, so we have to be
5866          * really careful about the ordering of the cases. Longer sequences
5867          * come first.
5868          */
5869 #ifdef MONO_ARCH_HAVE_IMT
5870         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5871                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5872                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5873                  * ff 50 fc                call   *0xfffffffc(%rax)
5874                  */
5875                 reg = amd64_modrm_rm (code [5]);
5876                 disp = (signed char)code [6];
5877                 /* R10 is clobbered by the IMT thunk code */
5878                 g_assert (reg != AMD64_R10);
5879         }
5880 #else
5881         if (0) {
5882         }
5883 #endif
5884         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5885                         /*
5886                          * This is a interface call
5887                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5888                          * ff 10                  callq  *(%rax)
5889                          */
5890                 if (IS_REX (code [4]))
5891                         rex = code [4];
5892                 reg = amd64_modrm_rm (code [6]);
5893                 disp = 0;
5894                 /* R10 is clobbered by the IMT thunk code */
5895                 g_assert (reg != AMD64_R10);
5896         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5897                 /* call OFFSET(%rip) */
5898                 disp = *(guint32*)(code + 3);
5899                 return (gpointer*)(code + disp + 7);
5900         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5901                 /* call *[r12+disp32] */
5902                 if (IS_REX (code [-1]))
5903                         rex = code [-1];
5904                 reg = AMD64_RSP;
5905                 disp = *(gint32*)(code + 3);
5906         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5907                 /* call *[reg+disp32] */
5908                 if (IS_REX (code [0]))
5909                         rex = code [0];
5910                 reg = amd64_modrm_rm (code [2]);
5911                 disp = *(gint32*)(code + 3);
5912                 /* R10 is clobbered by the IMT thunk code */
5913                 g_assert (reg != AMD64_R10);
5914         } else if (code [2] == 0xe8) {
5915                 /* call <ADDR> */
5916                 return NULL;
5917         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5918                 /* call *[r12+disp32] */
5919                 if (IS_REX (code [2]))
5920                         rex = code [2];
5921                 reg = AMD64_RSP;
5922                 disp = *(gint8*)(code + 6);
5923         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5924                 /* call *%reg */
5925                 return NULL;
5926         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5927                 /* call *[reg+disp8] */
5928                 if (IS_REX (code [3]))
5929                         rex = code [3];
5930                 reg = amd64_modrm_rm (code [5]);
5931                 disp = *(gint8*)(code + 6);
5932                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5933         }
5934         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5935                         /*
5936                          * This is a interface call: should check the above code can't catch it earlier
5937                          * 8b 40 30   mov    0x30(%eax),%eax
5938                          * ff 10      call   *(%eax)
5939                          */
5940                 if (IS_REX (code [4]))
5941                         rex = code [4];
5942                 reg = amd64_modrm_rm (code [6]);
5943                 disp = 0;
5944         }
5945         else
5946                 g_assert_not_reached ();
5947
5948         reg += amd64_rex_b (rex);
5949
5950         /* R11 is clobbered by the trampoline code */
5951         g_assert (reg != AMD64_R11);
5952
5953         *displacement = disp;
5954         return regs [reg];
5955 }
5956
5957 gpointer*
5958 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5959 {
5960         gpointer vt;
5961         int displacement;
5962         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5963         if (!vt)
5964                 return NULL;
5965         return (gpointer*)((char*)vt + displacement);
5966 }
5967
5968 int
5969 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5970 {
5971         int this_reg = AMD64_ARG_REG1;
5972
5973         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5974                 CallInfo *cinfo;
5975
5976                 if (!gsctx && code)
5977                         gsctx = mono_get_generic_context_from_code (code);
5978
5979                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5980
5981                 if (cinfo->ret.storage != ArgValuetypeInReg)
5982                         this_reg = AMD64_ARG_REG2;
5983                 g_free (cinfo);
5984         }
5985
5986         return this_reg;
5987 }
5988
5989 gpointer
5990 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5991 {
5992         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
5993 }
5994
5995 #define MAX_ARCH_DELEGATE_PARAMS 10
5996
5997 gpointer
5998 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5999 {
6000         guint8 *code, *start;
6001         int i;
6002
6003         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6004                 return NULL;
6005
6006         /* FIXME: Support more cases */
6007         if (MONO_TYPE_ISSTRUCT (sig->ret))
6008                 return NULL;
6009
6010         if (has_target) {
6011                 static guint8* cached = NULL;
6012
6013                 if (cached)
6014                         return cached;
6015
6016                 start = code = mono_global_codeman_reserve (64);
6017
6018                 /* Replace the this argument with the target */
6019                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6020                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6021                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6022
6023                 g_assert ((code - start) < 64);
6024
6025                 mono_debug_add_delegate_trampoline (start, code - start);
6026
6027                 mono_memory_barrier ();
6028
6029                 cached = start;
6030         } else {
6031                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6032                 for (i = 0; i < sig->param_count; ++i)
6033                         if (!mono_is_regsize_var (sig->params [i]))
6034                                 return NULL;
6035                 if (sig->param_count > 4)
6036                         return NULL;
6037
6038                 code = cache [sig->param_count];
6039                 if (code)
6040                         return code;
6041
6042                 start = code = mono_global_codeman_reserve (64);
6043
6044                 if (sig->param_count == 0) {
6045                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6046                 } else {
6047                         /* We have to shift the arguments left */
6048                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6049                         for (i = 0; i < sig->param_count; ++i)
6050                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6051
6052                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6053                 }
6054                 g_assert ((code - start) < 64);
6055
6056                 mono_debug_add_delegate_trampoline (start, code - start);
6057
6058                 mono_memory_barrier ();
6059
6060                 cache [sig->param_count] = start;
6061         }
6062
6063         return start;
6064 }
6065
6066 /*
6067  * Support for fast access to the thread-local lmf structure using the GS
6068  * segment register on NPTL + kernel 2.6.x.
6069  */
6070
6071 static gboolean tls_offset_inited = FALSE;
6072
6073 void
6074 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6075 {
6076         if (!tls_offset_inited) {
6077 #ifdef PLATFORM_WIN32
6078                 /*
6079                  * We need to init this multiple times, since when we are first called, the key might not
6080                  * be initialized yet.
6081                  */
6082                 appdomain_tls_offset = mono_domain_get_tls_key ();
6083                 lmf_tls_offset = mono_get_jit_tls_key ();
6084                 thread_tls_offset = mono_thread_get_tls_key ();
6085                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6086
6087                 /* Only 64 tls entries can be accessed using inline code */
6088                 if (appdomain_tls_offset >= 64)
6089                         appdomain_tls_offset = -1;
6090                 if (lmf_tls_offset >= 64)
6091                         lmf_tls_offset = -1;
6092                 if (thread_tls_offset >= 64)
6093                         thread_tls_offset = -1;
6094 #else
6095                 tls_offset_inited = TRUE;
6096 #ifdef MONO_XEN_OPT
6097                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6098 #endif
6099                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6100                 lmf_tls_offset = mono_get_lmf_tls_offset ();
6101                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6102                 thread_tls_offset = mono_thread_get_tls_offset ();
6103 #endif
6104         }
6105 }
6106
6107 void
6108 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6109 {
6110 }
6111
6112 void
6113 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
6114 {
6115         MonoCallInst *call = (MonoCallInst*)inst;
6116         CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
6117
6118         if (vt_reg != -1) {
6119                 MonoInst *vtarg;
6120
6121                 if (cinfo->ret.storage == ArgValuetypeInReg) {
6122                         /*
6123                          * The valuetype is in RAX:RDX after the call, need to be copied to
6124                          * the stack. Save the address here, so the call instruction can
6125                          * access it.
6126                          */
6127                         MonoInst *loc = cfg->arch.vret_addr_loc;
6128
6129                         g_assert (loc);
6130                         g_assert (loc->opcode == OP_REGOFFSET);
6131
6132                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, loc->inst_basereg, loc->inst_offset, vt_reg);
6133                 } else {
6134                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
6135                         vtarg->sreg1 = vt_reg;
6136                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
6137                         mono_bblock_add_inst (cfg->cbb, vtarg);
6138
6139                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
6140                 }
6141         }
6142
6143         /* add the this argument */
6144         if (this_reg != -1) {
6145                 MonoInst *this;
6146                 MONO_INST_NEW (cfg, this, OP_MOVE);
6147                 this->type = this_type;
6148                 this->sreg1 = this_reg;
6149                 this->dreg = mono_regstate_next_int (cfg->rs);
6150                 mono_bblock_add_inst (cfg->cbb, this);
6151
6152                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
6153         }
6154 }
6155
6156 #ifdef MONO_ARCH_HAVE_IMT
6157
6158 #define CMP_SIZE (6 + 1)
6159 #define CMP_REG_REG_SIZE (4 + 1)
6160 #define BR_SMALL_SIZE 2
6161 #define BR_LARGE_SIZE 6
6162 #define MOV_REG_IMM_SIZE 10
6163 #define MOV_REG_IMM_32BIT_SIZE 6
6164 #define JUMP_REG_SIZE (2 + 1)
6165
6166 static int
6167 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6168 {
6169         int i, distance = 0;
6170         for (i = start; i < target; ++i)
6171                 distance += imt_entries [i]->chunk_size;
6172         return distance;
6173 }
6174
6175 /*
6176  * LOCKING: called with the domain lock held
6177  */
6178 gpointer
6179 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count)
6180 {
6181         int i;
6182         int size = 0;
6183         guint8 *code, *start;
6184         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6185
6186         for (i = 0; i < count; ++i) {
6187                 MonoIMTCheckItem *item = imt_entries [i];
6188                 if (item->is_equals) {
6189                         if (item->check_target_idx) {
6190                                 if (!item->compare_done) {
6191                                         if (amd64_is_imm32 (item->method))
6192                                                 item->chunk_size += CMP_SIZE;
6193                                         else
6194                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6195                                 }
6196                                 if (vtable_is_32bit)
6197                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6198                                 else
6199                                         item->chunk_size += MOV_REG_IMM_SIZE;
6200                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6201                         } else {
6202                                 if (vtable_is_32bit)
6203                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6204                                 else
6205                                         item->chunk_size += MOV_REG_IMM_SIZE;
6206                                 item->chunk_size += JUMP_REG_SIZE;
6207                                 /* with assert below:
6208                                  * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6209                                  */
6210                         }
6211                 } else {
6212                         if (amd64_is_imm32 (item->method))
6213                                 item->chunk_size += CMP_SIZE;
6214                         else
6215                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6216                         item->chunk_size += BR_LARGE_SIZE;
6217                         imt_entries [item->check_target_idx]->compare_done = TRUE;
6218                 }
6219                 size += item->chunk_size;
6220         }
6221         code = mono_code_manager_reserve (domain->code_mp, size);
6222         start = code;
6223         for (i = 0; i < count; ++i) {
6224                 MonoIMTCheckItem *item = imt_entries [i];
6225                 item->code_target = code;
6226                 if (item->is_equals) {
6227                         if (item->check_target_idx) {
6228                                 if (!item->compare_done) {
6229                                         if (amd64_is_imm32 (item->method))
6230                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6231                                         else {
6232                                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6233                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6234                                         }
6235                                 }
6236                                 item->jmp_code = code;
6237                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6238                                 /* See the comment below about R10 */
6239                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6240                                 amd64_jump_membase (code, AMD64_R10, 0);
6241                         } else {
6242                                 /* enable the commented code to assert on wrong method */
6243 #if 0
6244                                 if (amd64_is_imm32 (item->method))
6245                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6246                                 else {
6247                                         amd64_mov_reg_imm (code, AMD64_R10, item->method);
6248                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6249                                 }
6250                                 item->jmp_code = code;
6251                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6252                                 /* See the comment below about R10 */
6253                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6254                                 amd64_jump_membase (code, AMD64_R10, 0);
6255                                 amd64_patch (item->jmp_code, code);
6256                                 amd64_breakpoint (code);
6257                                 item->jmp_code = NULL;
6258 #else
6259                                 /* We're using R10 here because R11
6260                                    needs to be preserved.  R10 needs
6261                                    to be preserved for calls which
6262                                    require a runtime generic context,
6263                                    but interface calls don't. */
6264                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6265                                 amd64_jump_membase (code, AMD64_R10, 0);
6266 #endif
6267                         }
6268                 } else {
6269                         if (amd64_is_imm32 (item->method))
6270                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6271                         else {
6272                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6273                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6274                         }
6275                         item->jmp_code = code;
6276                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6277                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6278                         else
6279                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6280                 }
6281                 g_assert (code - item->code_target <= item->chunk_size);
6282         }
6283         /* patch the branches to get to the target items */
6284         for (i = 0; i < count; ++i) {
6285                 MonoIMTCheckItem *item = imt_entries [i];
6286                 if (item->jmp_code) {
6287                         if (item->check_target_idx) {
6288                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6289                         }
6290                 }
6291         }
6292
6293         mono_stats.imt_thunks_size += code - start;
6294         g_assert (code - start <= size);
6295
6296         return start;
6297 }
6298
6299 MonoMethod*
6300 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6301 {
6302         return regs [MONO_ARCH_IMT_REG];
6303 }
6304
6305 MonoObject*
6306 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6307 {
6308         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6309 }
6310
6311 void
6312 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call)
6313 {
6314         /* Done by the implementation of the CALL_MEMBASE opcodes */
6315 }
6316 #endif
6317
6318 MonoVTable*
6319 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6320 {
6321         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6322 }
6323
6324 MonoInst*
6325 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6326 {
6327         MonoInst *ins = NULL;
6328
6329         if (cmethod->klass == mono_defaults.math_class) {
6330                 if (strcmp (cmethod->name, "Sin") == 0) {
6331                         MONO_INST_NEW (cfg, ins, OP_SIN);
6332                         ins->inst_i0 = args [0];
6333                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6334                         MONO_INST_NEW (cfg, ins, OP_COS);
6335                         ins->inst_i0 = args [0];
6336                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6337                         MONO_INST_NEW (cfg, ins, OP_SQRT);
6338                         ins->inst_i0 = args [0];
6339                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6340                         MONO_INST_NEW (cfg, ins, OP_ABS);
6341                         ins->inst_i0 = args [0];
6342                 }
6343
6344                 if (cfg->opt & MONO_OPT_CMOV) {
6345                         int opcode = 0;
6346
6347                         if (strcmp (cmethod->name, "Min") == 0) {
6348                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6349                                         opcode = OP_IMIN;
6350                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6351                                         opcode = OP_IMIN_UN;
6352                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6353                                         opcode = OP_LMIN;
6354                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6355                                         opcode = OP_LMIN_UN;
6356                         } else if (strcmp (cmethod->name, "Max") == 0) {
6357                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6358                                         opcode = OP_IMAX;
6359                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6360                                         opcode = OP_IMAX_UN;
6361                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6362                                         opcode = OP_LMAX;
6363                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6364                                         opcode = OP_LMAX_UN;
6365                         }
6366
6367                         if (opcode) {
6368                                 MONO_INST_NEW (cfg, ins, opcode);
6369                                 ins->inst_i0 = args [0];
6370                                 ins->inst_i1 = args [1];
6371                         }
6372                 }
6373
6374 #if 0
6375                 /* OP_FREM is not IEEE compatible */
6376                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6377                         MONO_INST_NEW (cfg, ins, OP_FREM);
6378                         ins->inst_i0 = args [0];
6379                         ins->inst_i1 = args [1];
6380                 }
6381 #endif
6382         }
6383
6384         return ins;
6385 }
6386
6387 MonoInst*
6388 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6389 {
6390         MonoInst *ins = NULL;
6391         int opcode = 0;
6392
6393         if (cmethod->klass == mono_defaults.math_class) {
6394                 if (strcmp (cmethod->name, "Sin") == 0) {
6395                         opcode = OP_SIN;
6396                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6397                         opcode = OP_COS;
6398                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6399                         opcode = OP_SQRT;
6400                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6401                         opcode = OP_ABS;
6402                 }
6403
6404                 if (opcode) {
6405                         MONO_INST_NEW (cfg, ins, opcode);
6406                         ins->type = STACK_R8;
6407                         ins->dreg = mono_alloc_freg (cfg);
6408                         ins->sreg1 = args [0]->dreg;
6409                         MONO_ADD_INS (cfg->cbb, ins);
6410                 }
6411
6412                 opcode = 0;
6413                 if (cfg->opt & MONO_OPT_CMOV) {
6414                         if (strcmp (cmethod->name, "Min") == 0) {
6415                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6416                                         opcode = OP_IMIN;
6417                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6418                                         opcode = OP_IMIN_UN;
6419                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6420                                         opcode = OP_LMIN;
6421                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6422                                         opcode = OP_LMIN_UN;
6423                         } else if (strcmp (cmethod->name, "Max") == 0) {
6424                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6425                                         opcode = OP_IMAX;
6426                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6427                                         opcode = OP_IMAX_UN;
6428                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6429                                         opcode = OP_LMAX;
6430                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6431                                         opcode = OP_LMAX_UN;
6432                         }
6433                 }
6434
6435                 if (opcode) {
6436                         MONO_INST_NEW (cfg, ins, opcode);
6437                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6438                         ins->dreg = mono_alloc_ireg (cfg);
6439                         ins->sreg1 = args [0]->dreg;
6440                         ins->sreg2 = args [1]->dreg;
6441                         MONO_ADD_INS (cfg->cbb, ins);
6442                 }
6443
6444 #if 0
6445                 /* OP_FREM is not IEEE compatible */
6446                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6447                         MONO_INST_NEW (cfg, ins, OP_FREM);
6448                         ins->inst_i0 = args [0];
6449                         ins->inst_i1 = args [1];
6450                 }
6451 #endif
6452         }
6453
6454         /*
6455          * Can't implement CompareExchange methods this way since they have
6456          * three arguments.
6457          */
6458
6459         return ins;
6460 }
6461
6462 gboolean
6463 mono_arch_print_tree (MonoInst *tree, int arity)
6464 {
6465         return 0;
6466 }
6467
6468 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6469 {
6470         MonoInst* ins;
6471
6472         if (appdomain_tls_offset == -1)
6473                 return NULL;
6474
6475         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6476         ins->inst_offset = appdomain_tls_offset;
6477         return ins;
6478 }
6479
6480 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6481 {
6482         MonoInst* ins;
6483
6484         if (thread_tls_offset == -1)
6485                 return NULL;
6486
6487         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6488         ins->inst_offset = thread_tls_offset;
6489         return ins;
6490 }
6491
6492 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6493
6494 gpointer
6495 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6496 {
6497         switch (reg) {
6498         case AMD64_RCX: return (gpointer)ctx->rcx;
6499         case AMD64_RDX: return (gpointer)ctx->rdx;
6500         case AMD64_RBX: return (gpointer)ctx->rbx;
6501         case AMD64_RBP: return (gpointer)ctx->rbp;
6502         case AMD64_RSP: return (gpointer)ctx->rsp;
6503         default:
6504                 if (reg < 8)
6505                         return _CTX_REG (ctx, rax, reg);
6506                 else if (reg >= 12)
6507                         return _CTX_REG (ctx, r12, reg - 12);
6508                 else
6509                         g_assert_not_reached ();
6510         }
6511 }