2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internal.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
35 #include <mono/utils/mono-threads.h>
39 #include "mini-amd64.h"
40 #include "cpu-amd64.h"
41 #include "debugger-agent.h"
45 static gboolean optimize_for_xen = TRUE;
47 #define optimize_for_xen 0
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
66 static mono_mutex_t mini_arch_mutex;
69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 * The code generated for sequence points reads from this location, which is
73 * made read-only when single stepping is enabled.
75 static gpointer ss_trigger_page;
77 /* Enabled breakpoints read from this trigger page */
78 static gpointer bp_trigger_page;
80 /* The size of the breakpoint sequence */
81 static int breakpoint_size;
83 /* The size of the breakpoint instruction causing the actual fault */
84 static int breakpoint_fault_size;
86 /* The size of the single step instruction causing the actual fault */
87 static int single_step_fault_size;
89 /* The single step trampoline */
90 static gpointer ss_trampoline;
92 /* Offset between fp and the first argument in the callee */
93 #define ARGS_OFFSET 16
94 #define GP_SCRATCH_REG AMD64_R11
97 * AMD64 register usage:
98 * - callee saved registers are used for global register allocation
99 * - %r11 is used for materializing 64 bit constants in opcodes
100 * - the rest is used for local allocation
104 * Floating point comparison results:
114 mono_arch_regname (int reg)
117 case AMD64_RAX: return "%rax";
118 case AMD64_RBX: return "%rbx";
119 case AMD64_RCX: return "%rcx";
120 case AMD64_RDX: return "%rdx";
121 case AMD64_RSP: return "%rsp";
122 case AMD64_RBP: return "%rbp";
123 case AMD64_RDI: return "%rdi";
124 case AMD64_RSI: return "%rsi";
125 case AMD64_R8: return "%r8";
126 case AMD64_R9: return "%r9";
127 case AMD64_R10: return "%r10";
128 case AMD64_R11: return "%r11";
129 case AMD64_R12: return "%r12";
130 case AMD64_R13: return "%r13";
131 case AMD64_R14: return "%r14";
132 case AMD64_R15: return "%r15";
137 static const char * packed_xmmregs [] = {
138 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
139 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
142 static const char * single_xmmregs [] = {
143 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
144 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
148 mono_arch_fregname (int reg)
150 if (reg < AMD64_XMM_NREG)
151 return single_xmmregs [reg];
157 mono_arch_xregname (int reg)
159 if (reg < AMD64_XMM_NREG)
160 return packed_xmmregs [reg];
169 return mono_debug_count ();
175 static inline gboolean
176 amd64_is_near_call (guint8 *code)
179 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
182 return code [0] == 0xe8;
185 #ifdef __native_client_codegen__
187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
188 /* for any given instruction. For instance, amd64_call_reg resolves to */
189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
190 /* We only want to force bundle alignment for the top level instruction, */
191 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
192 static MonoNativeTlsKey nacl_instruction_depth;
194 static MonoNativeTlsKey nacl_rex_tag;
195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
198 amd64_nacl_clear_legacy_prefix_tag ()
200 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
204 amd64_nacl_tag_legacy_prefix (guint8* code)
206 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
207 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
211 amd64_nacl_tag_rex (guint8* code)
213 mono_native_tls_set_value (nacl_rex_tag, code);
217 amd64_nacl_get_legacy_prefix_tag ()
219 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
223 amd64_nacl_get_rex_tag ()
225 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
228 /* Increment the instruction "depth" described above */
230 amd64_nacl_instruction_pre ()
232 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
234 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
238 /* alignment if depth == 0 (top level instruction) */
239 /* IN: start, end pointers to instruction beginning and end */
240 /* OUT: start, end pointers to beginning and end after possible alignment */
241 /* GLOBALS: nacl_instruction_depth defined above */
243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
245 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
247 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
249 g_assert ( depth >= 0 );
251 uintptr_t space_in_block;
253 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
254 /* if legacy prefix is present, and if it was emitted before */
255 /* the start of the instruction sequence, adjust the start */
256 if (prefix != NULL && prefix < *start) {
257 g_assert (*start - prefix <= 3);/* only 3 are allowed */
260 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
261 instlen = (uintptr_t)(*end - *start);
262 /* Only check for instructions which are less than */
263 /* kNaClAlignment. The only instructions that should ever */
264 /* be that long are call sequences, which are already */
265 /* padded out to align the return to the next bundle. */
266 if (instlen > space_in_block && instlen < kNaClAlignment) {
267 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
268 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
269 const size_t length = (size_t)((*end)-(*start));
270 g_assert (length < MAX_NACL_INST_LENGTH);
272 memcpy (copy_of_instruction, *start, length);
273 *start = mono_arch_nacl_pad (*start, space_in_block);
274 memcpy (*start, copy_of_instruction, length);
275 *end = *start + length;
277 amd64_nacl_clear_legacy_prefix_tag ();
278 amd64_nacl_tag_rex (NULL);
282 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
283 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
284 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
285 /* make sure the upper 32-bits are cleared, and use that register in the */
286 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
288 /* pointer to current instruction stream (in the */
289 /* middle of an instruction, after opcode is emitted) */
290 /* basereg/offset/dreg */
291 /* operands of normal membase address */
293 /* pointer to the end of the membase/memindex emit */
294 /* GLOBALS: nacl_rex_tag */
295 /* position in instruction stream that rex prefix was emitted */
296 /* nacl_legacy_prefix_tag */
297 /* (possibly NULL) position in instruction of legacy x86 prefix */
299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
301 gint8 true_basereg = basereg;
303 /* Cache these values, they might change */
304 /* as new instructions are emitted below. */
305 guint8* rex_tag = amd64_nacl_get_rex_tag ();
306 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
308 /* 'basereg' is given masked to 0x7 at this point, so check */
309 /* the rex prefix to see if this is an extended register. */
310 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
314 #define X86_LEA_OPCODE (0x8D)
316 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
317 guint8* old_instruction_start;
319 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
320 /* 32-bits of the old base register (new index register) */
322 guint8* buf_ptr = buf;
325 g_assert (rex_tag != NULL);
327 if (IS_REX(*rex_tag)) {
328 /* The old rex.B should be the new rex.X */
329 if (*rex_tag & AMD64_REX_B) {
330 *rex_tag |= AMD64_REX_X;
332 /* Since our new base is %r15 set rex.B */
333 *rex_tag |= AMD64_REX_B;
335 /* Shift the instruction by one byte */
336 /* so we can insert a rex prefix */
337 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
339 /* New rex prefix only needs rex.B for %r15 base */
340 *rex_tag = AMD64_REX(AMD64_REX_B);
343 if (legacy_prefix_tag) {
344 old_instruction_start = legacy_prefix_tag;
346 old_instruction_start = rex_tag;
349 /* Clears the upper 32-bits of the previous base register */
350 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
351 insert_len = buf_ptr - buf;
353 /* Move the old instruction forward to make */
354 /* room for 'mov' stored in 'buf_ptr' */
355 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
357 memcpy (old_instruction_start, buf, insert_len);
359 /* Sandboxed replacement for the normal membase_emit */
360 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
363 /* Normal default behavior, emit membase memory location */
364 x86_membase_emit_body (*code, dreg, basereg, offset);
369 static inline unsigned char*
370 amd64_skip_nops (unsigned char* code)
375 if ( code[0] == 0x90) {
379 if ( code[0] == 0x66 && code[1] == 0x90) {
383 if (code[0] == 0x0f && code[1] == 0x1f
384 && code[2] == 0x00) {
388 if (code[0] == 0x0f && code[1] == 0x1f
389 && code[2] == 0x40 && code[3] == 0x00) {
393 if (code[0] == 0x0f && code[1] == 0x1f
394 && code[2] == 0x44 && code[3] == 0x00
395 && code[4] == 0x00) {
399 if (code[0] == 0x66 && code[1] == 0x0f
400 && code[2] == 0x1f && code[3] == 0x44
401 && code[4] == 0x00 && code[5] == 0x00) {
405 if (code[0] == 0x0f && code[1] == 0x1f
406 && code[2] == 0x80 && code[3] == 0x00
407 && code[4] == 0x00 && code[5] == 0x00
408 && code[6] == 0x00) {
412 if (code[0] == 0x0f && code[1] == 0x1f
413 && code[2] == 0x84 && code[3] == 0x00
414 && code[4] == 0x00 && code[5] == 0x00
415 && code[6] == 0x00 && code[7] == 0x00) {
424 mono_arch_nacl_skip_nops (guint8* code)
426 return amd64_skip_nops(code);
429 #endif /*__native_client_codegen__*/
432 amd64_patch (unsigned char* code, gpointer target)
436 #ifdef __native_client_codegen__
437 code = amd64_skip_nops (code);
439 #if defined(__native_client_codegen__) && defined(__native_client__)
440 if (nacl_is_code_address (code)) {
441 /* For tail calls, code is patched after being installed */
442 /* but not through the normal "patch callsite" method. */
443 unsigned char buf[kNaClAlignment];
444 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
446 memcpy (buf, aligned_code, kNaClAlignment);
447 /* Patch a temp buffer of bundle size, */
448 /* then install to actual location. */
449 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
450 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
454 target = nacl_modify_patch_target (target);
458 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
463 if ((code [0] & 0xf8) == 0xb8) {
464 /* amd64_set_reg_template */
465 *(guint64*)(code + 1) = (guint64)target;
467 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
468 /* mov 0(%rip), %dreg */
469 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
471 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
472 /* call *<OFFSET>(%rip) */
473 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
475 else if (code [0] == 0xe8) {
477 gint64 disp = (guint8*)target - (guint8*)code;
478 g_assert (amd64_is_imm32 (disp));
479 x86_patch (code, (unsigned char*)target);
482 x86_patch (code, (unsigned char*)target);
486 mono_amd64_patch (unsigned char* code, gpointer target)
488 amd64_patch (code, target);
497 ArgValuetypeAddrInIReg,
498 ArgNone /* only in pair_storage */
506 /* Only if storage == ArgValuetypeInReg */
507 ArgStorage pair_storage [2];
509 /* The size of each pair */
519 gboolean need_stack_align;
520 gboolean vtype_retaddr;
521 /* The index of the vret arg in the argument list */
528 #define DEBUG(a) if (cfg->verbose_level > 1) a
531 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
535 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
537 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
541 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
543 ainfo->offset = *stack_size;
545 if (*gr >= PARAM_REGS) {
546 ainfo->storage = ArgOnStack;
547 /* Since the same stack slot size is used for all arg */
548 /* types, it needs to be big enough to hold them all */
549 (*stack_size) += sizeof(mgreg_t);
552 ainfo->storage = ArgInIReg;
553 ainfo->reg = param_regs [*gr];
559 #define FLOAT_PARAM_REGS 4
561 #define FLOAT_PARAM_REGS 8
565 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
567 ainfo->offset = *stack_size;
569 if (*gr >= FLOAT_PARAM_REGS) {
570 ainfo->storage = ArgOnStack;
571 /* Since the same stack slot size is used for both float */
572 /* types, it needs to be big enough to hold them both */
573 (*stack_size) += sizeof(mgreg_t);
576 /* A double register */
578 ainfo->storage = ArgInDoubleSSEReg;
580 ainfo->storage = ArgInFloatSSEReg;
586 typedef enum ArgumentClass {
594 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
596 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
599 ptype = mini_type_get_underlying_type (gsctx, type);
600 switch (ptype->type) {
609 case MONO_TYPE_STRING:
610 case MONO_TYPE_OBJECT:
611 case MONO_TYPE_CLASS:
612 case MONO_TYPE_SZARRAY:
614 case MONO_TYPE_FNPTR:
615 case MONO_TYPE_ARRAY:
618 class2 = ARG_CLASS_INTEGER;
623 class2 = ARG_CLASS_INTEGER;
625 class2 = ARG_CLASS_SSE;
629 case MONO_TYPE_TYPEDBYREF:
630 g_assert_not_reached ();
632 case MONO_TYPE_GENERICINST:
633 if (!mono_type_generic_inst_is_valuetype (ptype)) {
634 class2 = ARG_CLASS_INTEGER;
638 case MONO_TYPE_VALUETYPE: {
639 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
642 for (i = 0; i < info->num_fields; ++i) {
644 class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
649 g_assert_not_reached ();
653 if (class1 == class2)
655 else if (class1 == ARG_CLASS_NO_CLASS)
657 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
658 class1 = ARG_CLASS_MEMORY;
659 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
660 class1 = ARG_CLASS_INTEGER;
662 class1 = ARG_CLASS_SSE;
666 #ifdef __native_client_codegen__
668 /* Default alignment for Native Client is 32-byte. */
669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
672 /* Check that alignment doesn't cross an alignment boundary. */
674 mono_arch_nacl_pad(guint8 *code, int pad)
676 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
678 if (pad == 0) return code;
679 /* assertion: alignment cannot cross a block boundary */
680 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
681 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
682 while (pad >= kMaxPadding) {
683 amd64_padding (code, kMaxPadding);
686 if (pad != 0) amd64_padding (code, pad);
692 count_fields_nested (MonoClass *klass)
694 MonoMarshalType *info;
697 info = mono_marshal_load_type_info (klass);
700 for (i = 0; i < info->num_fields; ++i) {
701 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
702 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
710 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
712 MonoMarshalType *info;
715 info = mono_marshal_load_type_info (klass);
717 for (i = 0; i < info->num_fields; ++i) {
718 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
719 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
721 memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
722 fields [index].offset += offset;
730 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
732 guint32 *gr, guint32 *fr, guint32 *stack_size)
734 guint32 size, quad, nquads, i, nfields;
735 /* Keep track of the size used in each quad so we can */
736 /* use the right size when copying args/return vars. */
737 guint32 quadsize [2] = {8, 8};
738 ArgumentClass args [2];
739 MonoMarshalType *info = NULL;
740 MonoMarshalField *fields = NULL;
742 MonoGenericSharingContext tmp_gsctx;
743 gboolean pass_on_stack = FALSE;
746 * The gsctx currently contains no data, it is only used for checking whenever
747 * open types are allowed, some callers like mono_arch_get_argument_info ()
748 * don't pass it to us, so work around that.
753 klass = mono_class_from_mono_type (type);
754 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
756 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
757 /* We pass and return vtypes of size 8 in a register */
758 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
759 pass_on_stack = TRUE;
763 pass_on_stack = TRUE;
767 /* If this struct can't be split up naturally into 8-byte */
768 /* chunks (registers), pass it on the stack. */
769 if (sig->pinvoke && !pass_on_stack) {
773 info = mono_marshal_load_type_info (klass);
777 * Collect field information recursively to be able to
778 * handle nested structures.
780 nfields = count_fields_nested (klass);
781 fields = g_new0 (MonoMarshalField, nfields);
782 collect_field_info_nested (klass, fields, 0, 0);
784 for (i = 0; i < nfields; ++i) {
785 field_size = mono_marshal_type_size (fields [i].field->type,
787 &align, TRUE, klass->unicode);
788 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
789 pass_on_stack = TRUE;
796 /* Allways pass in memory */
797 ainfo->offset = *stack_size;
798 *stack_size += ALIGN_TO (size, 8);
799 ainfo->storage = ArgOnStack;
805 /* FIXME: Handle structs smaller than 8 bytes */
806 //if ((size % 8) != 0)
815 int n = mono_class_value_size (klass, NULL);
817 quadsize [0] = n >= 8 ? 8 : n;
818 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
820 /* Always pass in 1 or 2 integer registers */
821 args [0] = ARG_CLASS_INTEGER;
822 args [1] = ARG_CLASS_INTEGER;
823 /* Only the simplest cases are supported */
824 if (is_return && nquads != 1) {
825 args [0] = ARG_CLASS_MEMORY;
826 args [1] = ARG_CLASS_MEMORY;
830 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
831 * The X87 and SSEUP stuff is left out since there are no such types in
838 if (info->native_size > 16) {
839 ainfo->offset = *stack_size;
840 *stack_size += ALIGN_TO (info->native_size, 8);
841 ainfo->storage = ArgOnStack;
847 switch (info->native_size) {
848 case 1: case 2: case 4: case 8:
852 ainfo->storage = ArgOnStack;
853 ainfo->offset = *stack_size;
854 *stack_size += ALIGN_TO (info->native_size, 8);
857 ainfo->storage = ArgValuetypeAddrInIReg;
859 if (*gr < PARAM_REGS) {
860 ainfo->pair_storage [0] = ArgInIReg;
861 ainfo->pair_regs [0] = param_regs [*gr];
865 ainfo->pair_storage [0] = ArgOnStack;
866 ainfo->offset = *stack_size;
876 args [0] = ARG_CLASS_NO_CLASS;
877 args [1] = ARG_CLASS_NO_CLASS;
878 for (quad = 0; quad < nquads; ++quad) {
881 ArgumentClass class1;
884 class1 = ARG_CLASS_MEMORY;
886 class1 = ARG_CLASS_NO_CLASS;
887 for (i = 0; i < nfields; ++i) {
888 size = mono_marshal_type_size (fields [i].field->type,
890 &align, TRUE, klass->unicode);
891 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
892 /* Unaligned field */
896 /* Skip fields in other quad */
897 if ((quad == 0) && (fields [i].offset >= 8))
899 if ((quad == 1) && (fields [i].offset < 8))
902 /* How far into this quad this data extends.*/
903 /* (8 is size of quad) */
904 quadsize [quad] = fields [i].offset + size - (quad * 8);
906 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
908 g_assert (class1 != ARG_CLASS_NO_CLASS);
909 args [quad] = class1;
915 /* Post merger cleanup */
916 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
917 args [0] = args [1] = ARG_CLASS_MEMORY;
919 /* Allocate registers */
924 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
926 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
929 ainfo->storage = ArgValuetypeInReg;
930 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
931 g_assert (quadsize [0] <= 8);
932 g_assert (quadsize [1] <= 8);
933 ainfo->pair_size [0] = quadsize [0];
934 ainfo->pair_size [1] = quadsize [1];
935 ainfo->nregs = nquads;
936 for (quad = 0; quad < nquads; ++quad) {
937 switch (args [quad]) {
938 case ARG_CLASS_INTEGER:
939 if (*gr >= PARAM_REGS)
940 args [quad] = ARG_CLASS_MEMORY;
942 ainfo->pair_storage [quad] = ArgInIReg;
944 ainfo->pair_regs [quad] = return_regs [*gr];
946 ainfo->pair_regs [quad] = param_regs [*gr];
951 if (*fr >= FLOAT_PARAM_REGS)
952 args [quad] = ARG_CLASS_MEMORY;
954 if (quadsize[quad] <= 4)
955 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
956 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
957 ainfo->pair_regs [quad] = *fr;
961 case ARG_CLASS_MEMORY:
964 g_assert_not_reached ();
968 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
969 /* Revert possible register assignments */
973 ainfo->offset = *stack_size;
975 *stack_size += ALIGN_TO (info->native_size, 8);
977 *stack_size += nquads * sizeof(mgreg_t);
978 ainfo->storage = ArgOnStack;
986 * Obtain information about a call according to the calling convention.
987 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
988 * Draft Version 0.23" document for more information.
991 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
993 guint32 i, gr, fr, pstart;
995 int n = sig->hasthis + sig->param_count;
996 guint32 stack_size = 0;
998 gboolean is_pinvoke = sig->pinvoke;
1001 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1003 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1011 /* Reserve space where the callee can save the argument registers */
1012 stack_size = 4 * sizeof (mgreg_t);
1016 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1017 switch (ret_type->type) {
1027 case MONO_TYPE_FNPTR:
1028 case MONO_TYPE_CLASS:
1029 case MONO_TYPE_OBJECT:
1030 case MONO_TYPE_SZARRAY:
1031 case MONO_TYPE_ARRAY:
1032 case MONO_TYPE_STRING:
1033 cinfo->ret.storage = ArgInIReg;
1034 cinfo->ret.reg = AMD64_RAX;
1038 cinfo->ret.storage = ArgInIReg;
1039 cinfo->ret.reg = AMD64_RAX;
1042 cinfo->ret.storage = ArgInFloatSSEReg;
1043 cinfo->ret.reg = AMD64_XMM0;
1046 cinfo->ret.storage = ArgInDoubleSSEReg;
1047 cinfo->ret.reg = AMD64_XMM0;
1049 case MONO_TYPE_GENERICINST:
1050 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1051 cinfo->ret.storage = ArgInIReg;
1052 cinfo->ret.reg = AMD64_RAX;
1056 #if defined( __native_client_codegen__ )
1057 case MONO_TYPE_TYPEDBYREF:
1059 case MONO_TYPE_VALUETYPE: {
1060 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062 add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1063 if (cinfo->ret.storage == ArgOnStack) {
1064 cinfo->vtype_retaddr = TRUE;
1065 /* The caller passes the address where the value is stored */
1069 #if !defined( __native_client_codegen__ )
1070 case MONO_TYPE_TYPEDBYREF:
1071 /* Same as a valuetype with size 24 */
1072 cinfo->vtype_retaddr = TRUE;
1075 case MONO_TYPE_VOID:
1078 g_error ("Can't handle as return value 0x%x", ret_type->type);
1083 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1084 * the first argument, allowing 'this' to be always passed in the first arg reg.
1085 * Also do this if the first argument is a reference type, since virtual calls
1086 * are sometimes made using calli without sig->hasthis set, like in the delegate
1089 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1091 add_general (&gr, &stack_size, cinfo->args + 0);
1093 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1096 add_general (&gr, &stack_size, &cinfo->ret);
1097 cinfo->vret_arg_index = 1;
1101 add_general (&gr, &stack_size, cinfo->args + 0);
1103 if (cinfo->vtype_retaddr)
1104 add_general (&gr, &stack_size, &cinfo->ret);
1107 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1109 fr = FLOAT_PARAM_REGS;
1111 /* Emit the signature cookie just before the implicit arguments */
1112 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1115 for (i = pstart; i < sig->param_count; ++i) {
1116 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1120 /* The float param registers and other param registers must be the same index on Windows x64.*/
1127 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1128 /* We allways pass the sig cookie on the stack for simplicity */
1130 * Prevent implicit arguments + the sig cookie from being passed
1134 fr = FLOAT_PARAM_REGS;
1136 /* Emit the signature cookie just before the implicit arguments */
1137 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1140 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1141 switch (ptype->type) {
1144 add_general (&gr, &stack_size, ainfo);
1148 add_general (&gr, &stack_size, ainfo);
1152 add_general (&gr, &stack_size, ainfo);
1157 case MONO_TYPE_FNPTR:
1158 case MONO_TYPE_CLASS:
1159 case MONO_TYPE_OBJECT:
1160 case MONO_TYPE_STRING:
1161 case MONO_TYPE_SZARRAY:
1162 case MONO_TYPE_ARRAY:
1163 add_general (&gr, &stack_size, ainfo);
1165 case MONO_TYPE_GENERICINST:
1166 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1167 add_general (&gr, &stack_size, ainfo);
1171 case MONO_TYPE_VALUETYPE:
1172 case MONO_TYPE_TYPEDBYREF:
1173 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178 add_general (&gr, &stack_size, ainfo);
1181 add_float (&fr, &stack_size, ainfo, FALSE);
1184 add_float (&fr, &stack_size, ainfo, TRUE);
1187 g_assert_not_reached ();
1191 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1193 fr = FLOAT_PARAM_REGS;
1195 /* Emit the signature cookie just before the implicit arguments */
1196 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1199 cinfo->stack_usage = stack_size;
1200 cinfo->reg_usage = gr;
1201 cinfo->freg_usage = fr;
1206 * mono_arch_get_argument_info:
1207 * @csig: a method signature
1208 * @param_count: the number of parameters to consider
1209 * @arg_info: an array to store the result infos
1211 * Gathers information on parameters such as size, alignment and
1212 * padding. arg_info should be large enought to hold param_count + 1 entries.
1214 * Returns the size of the argument area on the stack.
1217 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1220 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1221 guint32 args_size = cinfo->stack_usage;
1223 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1224 if (csig->hasthis) {
1225 arg_info [0].offset = 0;
1228 for (k = 0; k < param_count; k++) {
1229 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1231 arg_info [k + 1].size = 0;
1240 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1244 MonoType *callee_ret;
1246 c1 = get_call_info (NULL, NULL, caller_sig);
1247 c2 = get_call_info (NULL, NULL, callee_sig);
1248 res = c1->stack_usage >= c2->stack_usage;
1249 callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1250 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1251 /* An address on the callee's stack is passed as the first argument */
1261 * Initialize the cpu to execute managed code.
1264 mono_arch_cpu_init (void)
1269 /* spec compliance requires running with double precision */
1270 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1271 fpcw &= ~X86_FPCW_PRECC_MASK;
1272 fpcw |= X86_FPCW_PREC_DOUBLE;
1273 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1274 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1276 /* TODO: This is crashing on Win64 right now.
1277 * _control87 (_PC_53, MCW_PC);
1283 * Initialize architecture specific code.
1286 mono_arch_init (void)
1290 mono_mutex_init_recursive (&mini_arch_mutex);
1291 #if defined(__native_client_codegen__)
1292 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1293 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1294 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1295 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1298 #ifdef MONO_ARCH_NOMAP32BIT
1299 flags = MONO_MMAP_READ;
1300 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1301 breakpoint_size = 13;
1302 breakpoint_fault_size = 3;
1304 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1305 /* amd64_mov_reg_mem () */
1306 breakpoint_size = 8;
1307 breakpoint_fault_size = 8;
1310 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1311 single_step_fault_size = 4;
1313 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1314 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1315 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1317 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1318 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1319 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1323 * Cleanup architecture specific code.
1326 mono_arch_cleanup (void)
1328 mono_mutex_destroy (&mini_arch_mutex);
1329 #if defined(__native_client_codegen__)
1330 mono_native_tls_free (nacl_instruction_depth);
1331 mono_native_tls_free (nacl_rex_tag);
1332 mono_native_tls_free (nacl_legacy_prefix_tag);
1337 * This function returns the optimizations supported on this cpu.
1340 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1346 if (mono_hwcap_x86_has_cmov) {
1347 opts |= MONO_OPT_CMOV;
1349 if (mono_hwcap_x86_has_fcmov)
1350 opts |= MONO_OPT_FCMOV;
1352 *exclude_mask |= MONO_OPT_FCMOV;
1354 *exclude_mask |= MONO_OPT_CMOV;
1361 * This function test for all SSE functions supported.
1363 * Returns a bitmask corresponding to all supported versions.
1367 mono_arch_cpu_enumerate_simd_versions (void)
1369 guint32 sse_opts = 0;
1371 if (mono_hwcap_x86_has_sse1)
1372 sse_opts |= SIMD_VERSION_SSE1;
1374 if (mono_hwcap_x86_has_sse2)
1375 sse_opts |= SIMD_VERSION_SSE2;
1377 if (mono_hwcap_x86_has_sse3)
1378 sse_opts |= SIMD_VERSION_SSE3;
1380 if (mono_hwcap_x86_has_ssse3)
1381 sse_opts |= SIMD_VERSION_SSSE3;
1383 if (mono_hwcap_x86_has_sse41)
1384 sse_opts |= SIMD_VERSION_SSE41;
1386 if (mono_hwcap_x86_has_sse42)
1387 sse_opts |= SIMD_VERSION_SSE42;
1389 if (mono_hwcap_x86_has_sse4a)
1390 sse_opts |= SIMD_VERSION_SSE4a;
1398 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1403 for (i = 0; i < cfg->num_varinfo; i++) {
1404 MonoInst *ins = cfg->varinfo [i];
1405 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1408 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1411 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1412 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1415 if (mono_is_regsize_var (ins->inst_vtype)) {
1416 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1417 g_assert (i == vmv->idx);
1418 vars = g_list_prepend (vars, vmv);
1422 vars = mono_varlist_sort (cfg, vars, 0);
1428 * mono_arch_compute_omit_fp:
1430 * Determine whenever the frame pointer can be eliminated.
1433 mono_arch_compute_omit_fp (MonoCompile *cfg)
1435 MonoMethodSignature *sig;
1436 MonoMethodHeader *header;
1440 if (cfg->arch.omit_fp_computed)
1443 header = cfg->header;
1445 sig = mono_method_signature (cfg->method);
1447 if (!cfg->arch.cinfo)
1448 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1449 cinfo = cfg->arch.cinfo;
1452 * FIXME: Remove some of the restrictions.
1454 cfg->arch.omit_fp = TRUE;
1455 cfg->arch.omit_fp_computed = TRUE;
1457 #ifdef __native_client_codegen__
1458 /* NaCl modules may not change the value of RBP, so it cannot be */
1459 /* used as a normal register, but it can be used as a frame pointer*/
1460 cfg->disable_omit_fp = TRUE;
1461 cfg->arch.omit_fp = FALSE;
1464 if (cfg->disable_omit_fp)
1465 cfg->arch.omit_fp = FALSE;
1467 if (!debug_omit_fp ())
1468 cfg->arch.omit_fp = FALSE;
1470 if (cfg->method->save_lmf)
1471 cfg->arch.omit_fp = FALSE;
1473 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1474 cfg->arch.omit_fp = FALSE;
1475 if (header->num_clauses)
1476 cfg->arch.omit_fp = FALSE;
1477 if (cfg->param_area)
1478 cfg->arch.omit_fp = FALSE;
1479 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1480 cfg->arch.omit_fp = FALSE;
1481 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1482 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1483 cfg->arch.omit_fp = FALSE;
1484 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1485 ArgInfo *ainfo = &cinfo->args [i];
1487 if (ainfo->storage == ArgOnStack) {
1489 * The stack offset can only be determined when the frame
1492 cfg->arch.omit_fp = FALSE;
1497 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1498 MonoInst *ins = cfg->varinfo [i];
1501 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1506 mono_arch_get_global_int_regs (MonoCompile *cfg)
1510 mono_arch_compute_omit_fp (cfg);
1512 if (cfg->arch.omit_fp)
1513 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1515 /* We use the callee saved registers for global allocation */
1516 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1517 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1518 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1519 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1520 #ifndef __native_client_codegen__
1521 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1524 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1525 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1532 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1537 /* All XMM registers */
1538 for (i = 0; i < 16; ++i)
1539 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1545 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1547 static GList *r = NULL;
1552 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1553 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1554 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1555 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1556 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1557 #ifndef __native_client_codegen__
1558 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1561 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1562 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1563 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1564 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1565 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1566 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1567 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1568 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1570 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1577 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1580 static GList *r = NULL;
1585 for (i = 0; i < AMD64_XMM_NREG; ++i)
1586 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1588 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1595 * mono_arch_regalloc_cost:
1597 * Return the cost, in number of memory references, of the action of
1598 * allocating the variable VMV into a register during global register
1602 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1604 MonoInst *ins = cfg->varinfo [vmv->idx];
1606 if (cfg->method->save_lmf)
1607 /* The register is already saved */
1608 /* substract 1 for the invisible store in the prolog */
1609 return (ins->opcode == OP_ARG) ? 0 : 1;
1612 return (ins->opcode == OP_ARG) ? 1 : 2;
1616 * mono_arch_fill_argument_info:
1618 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1622 mono_arch_fill_argument_info (MonoCompile *cfg)
1625 MonoMethodSignature *sig;
1630 sig = mono_method_signature (cfg->method);
1632 cinfo = cfg->arch.cinfo;
1633 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1636 * Contrary to mono_arch_allocate_vars (), the information should describe
1637 * where the arguments are at the beginning of the method, not where they can be
1638 * accessed during the execution of the method. The later makes no sense for the
1639 * global register allocator, since a variable can be in more than one location.
1641 if (sig_ret->type != MONO_TYPE_VOID) {
1642 switch (cinfo->ret.storage) {
1644 case ArgInFloatSSEReg:
1645 case ArgInDoubleSSEReg:
1646 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1647 cfg->vret_addr->opcode = OP_REGVAR;
1648 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1651 cfg->ret->opcode = OP_REGVAR;
1652 cfg->ret->inst_c0 = cinfo->ret.reg;
1655 case ArgValuetypeInReg:
1656 cfg->ret->opcode = OP_REGOFFSET;
1657 cfg->ret->inst_basereg = -1;
1658 cfg->ret->inst_offset = -1;
1661 g_assert_not_reached ();
1665 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1666 ArgInfo *ainfo = &cinfo->args [i];
1668 ins = cfg->args [i];
1670 switch (ainfo->storage) {
1672 case ArgInFloatSSEReg:
1673 case ArgInDoubleSSEReg:
1674 ins->opcode = OP_REGVAR;
1675 ins->inst_c0 = ainfo->reg;
1678 ins->opcode = OP_REGOFFSET;
1679 ins->inst_basereg = -1;
1680 ins->inst_offset = -1;
1682 case ArgValuetypeInReg:
1684 ins->opcode = OP_NOP;
1687 g_assert_not_reached ();
1693 mono_arch_allocate_vars (MonoCompile *cfg)
1696 MonoMethodSignature *sig;
1699 guint32 locals_stack_size, locals_stack_align;
1703 sig = mono_method_signature (cfg->method);
1705 cinfo = cfg->arch.cinfo;
1706 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1708 mono_arch_compute_omit_fp (cfg);
1711 * We use the ABI calling conventions for managed code as well.
1712 * Exception: valuetypes are only sometimes passed or returned in registers.
1716 * The stack looks like this:
1717 * <incoming arguments passed on the stack>
1719 * <lmf/caller saved registers>
1722 * <localloc area> -> grows dynamically
1726 if (cfg->arch.omit_fp) {
1727 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1728 cfg->frame_reg = AMD64_RSP;
1731 /* Locals are allocated backwards from %fp */
1732 cfg->frame_reg = AMD64_RBP;
1736 cfg->arch.saved_iregs = cfg->used_int_regs;
1737 if (cfg->method->save_lmf)
1738 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1739 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1741 if (cfg->arch.omit_fp)
1742 cfg->arch.reg_save_area_offset = offset;
1743 /* Reserve space for callee saved registers */
1744 for (i = 0; i < AMD64_NREG; ++i)
1745 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1746 offset += sizeof(mgreg_t);
1748 if (!cfg->arch.omit_fp)
1749 cfg->arch.reg_save_area_offset = -offset;
1751 if (sig_ret->type != MONO_TYPE_VOID) {
1752 switch (cinfo->ret.storage) {
1754 case ArgInFloatSSEReg:
1755 case ArgInDoubleSSEReg:
1756 if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1757 /* The register is volatile */
1758 cfg->vret_addr->opcode = OP_REGOFFSET;
1759 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1760 if (cfg->arch.omit_fp) {
1761 cfg->vret_addr->inst_offset = offset;
1765 cfg->vret_addr->inst_offset = -offset;
1767 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1768 printf ("vret_addr =");
1769 mono_print_ins (cfg->vret_addr);
1773 cfg->ret->opcode = OP_REGVAR;
1774 cfg->ret->inst_c0 = cinfo->ret.reg;
1777 case ArgValuetypeInReg:
1778 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1779 cfg->ret->opcode = OP_REGOFFSET;
1780 cfg->ret->inst_basereg = cfg->frame_reg;
1781 if (cfg->arch.omit_fp) {
1782 cfg->ret->inst_offset = offset;
1783 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1785 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1786 cfg->ret->inst_offset = - offset;
1790 g_assert_not_reached ();
1792 cfg->ret->dreg = cfg->ret->inst_c0;
1795 /* Allocate locals */
1796 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1797 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1798 char *mname = mono_method_full_name (cfg->method, TRUE);
1799 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1800 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1805 if (locals_stack_align) {
1806 offset += (locals_stack_align - 1);
1807 offset &= ~(locals_stack_align - 1);
1809 if (cfg->arch.omit_fp) {
1810 cfg->locals_min_stack_offset = offset;
1811 cfg->locals_max_stack_offset = offset + locals_stack_size;
1813 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1814 cfg->locals_max_stack_offset = - offset;
1817 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1818 if (offsets [i] != -1) {
1819 MonoInst *ins = cfg->varinfo [i];
1820 ins->opcode = OP_REGOFFSET;
1821 ins->inst_basereg = cfg->frame_reg;
1822 if (cfg->arch.omit_fp)
1823 ins->inst_offset = (offset + offsets [i]);
1825 ins->inst_offset = - (offset + offsets [i]);
1826 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1829 offset += locals_stack_size;
1831 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1832 g_assert (!cfg->arch.omit_fp);
1833 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1834 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1837 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1838 ins = cfg->args [i];
1839 if (ins->opcode != OP_REGVAR) {
1840 ArgInfo *ainfo = &cinfo->args [i];
1841 gboolean inreg = TRUE;
1843 /* FIXME: Allocate volatile arguments to registers */
1844 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1848 * Under AMD64, all registers used to pass arguments to functions
1849 * are volatile across calls.
1850 * FIXME: Optimize this.
1852 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1855 ins->opcode = OP_REGOFFSET;
1857 switch (ainfo->storage) {
1859 case ArgInFloatSSEReg:
1860 case ArgInDoubleSSEReg:
1862 ins->opcode = OP_REGVAR;
1863 ins->dreg = ainfo->reg;
1867 g_assert (!cfg->arch.omit_fp);
1868 ins->opcode = OP_REGOFFSET;
1869 ins->inst_basereg = cfg->frame_reg;
1870 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1872 case ArgValuetypeInReg:
1874 case ArgValuetypeAddrInIReg: {
1876 g_assert (!cfg->arch.omit_fp);
1878 MONO_INST_NEW (cfg, indir, 0);
1879 indir->opcode = OP_REGOFFSET;
1880 if (ainfo->pair_storage [0] == ArgInIReg) {
1881 indir->inst_basereg = cfg->frame_reg;
1882 offset = ALIGN_TO (offset, sizeof (gpointer));
1883 offset += (sizeof (gpointer));
1884 indir->inst_offset = - offset;
1887 indir->inst_basereg = cfg->frame_reg;
1888 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1891 ins->opcode = OP_VTARG_ADDR;
1892 ins->inst_left = indir;
1900 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1901 ins->opcode = OP_REGOFFSET;
1902 ins->inst_basereg = cfg->frame_reg;
1903 /* These arguments are saved to the stack in the prolog */
1904 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1905 if (cfg->arch.omit_fp) {
1906 ins->inst_offset = offset;
1907 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1908 // Arguments are yet supported by the stack map creation code
1909 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1911 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1912 ins->inst_offset = - offset;
1913 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1919 cfg->stack_offset = offset;
1923 mono_arch_create_vars (MonoCompile *cfg)
1925 MonoMethodSignature *sig;
1929 sig = mono_method_signature (cfg->method);
1931 if (!cfg->arch.cinfo)
1932 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1933 cinfo = cfg->arch.cinfo;
1935 if (cinfo->ret.storage == ArgValuetypeInReg)
1936 cfg->ret_var_is_local = TRUE;
1938 sig_ret = mini_get_underlying_type (cfg, sig->ret);
1939 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1940 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1941 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1942 printf ("vret_addr = ");
1943 mono_print_ins (cfg->vret_addr);
1947 if (cfg->gen_sdb_seq_points) {
1950 if (cfg->compile_aot) {
1951 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1952 ins->flags |= MONO_INST_VOLATILE;
1953 cfg->arch.seq_point_info_var = ins;
1955 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1956 ins->flags |= MONO_INST_VOLATILE;
1957 cfg->arch.ss_tramp_var = ins;
1960 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1961 ins->flags |= MONO_INST_VOLATILE;
1962 cfg->arch.ss_trigger_page_var = ins;
1965 if (cfg->method->save_lmf)
1966 cfg->create_lmf_var = TRUE;
1968 if (cfg->method->save_lmf) {
1970 #if !defined(TARGET_WIN32)
1971 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1972 cfg->lmf_ir_mono_lmf = TRUE;
1978 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1984 MONO_INST_NEW (cfg, ins, OP_MOVE);
1985 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1986 ins->sreg1 = tree->dreg;
1987 MONO_ADD_INS (cfg->cbb, ins);
1988 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1990 case ArgInFloatSSEReg:
1991 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1992 ins->dreg = mono_alloc_freg (cfg);
1993 ins->sreg1 = tree->dreg;
1994 MONO_ADD_INS (cfg->cbb, ins);
1996 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1998 case ArgInDoubleSSEReg:
1999 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2000 ins->dreg = mono_alloc_freg (cfg);
2001 ins->sreg1 = tree->dreg;
2002 MONO_ADD_INS (cfg->cbb, ins);
2004 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2008 g_assert_not_reached ();
2013 arg_storage_to_load_membase (ArgStorage storage)
2017 #if defined(__mono_ilp32__)
2018 return OP_LOADI8_MEMBASE;
2020 return OP_LOAD_MEMBASE;
2022 case ArgInDoubleSSEReg:
2023 return OP_LOADR8_MEMBASE;
2024 case ArgInFloatSSEReg:
2025 return OP_LOADR4_MEMBASE;
2027 g_assert_not_reached ();
2034 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2036 MonoMethodSignature *tmp_sig;
2039 if (call->tail_call)
2042 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2045 * mono_ArgIterator_Setup assumes the signature cookie is
2046 * passed first and all the arguments which were before it are
2047 * passed on the stack after the signature. So compensate by
2048 * passing a different signature.
2050 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2051 tmp_sig->param_count -= call->signature->sentinelpos;
2052 tmp_sig->sentinelpos = 0;
2053 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2055 sig_reg = mono_alloc_ireg (cfg);
2056 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2058 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2062 static inline LLVMArgStorage
2063 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2067 return LLVMArgInIReg;
2071 g_assert_not_reached ();
2077 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2083 LLVMCallInfo *linfo;
2084 MonoType *t, *sig_ret;
2086 n = sig->param_count + sig->hasthis;
2087 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2089 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2091 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2094 * LLVM always uses the native ABI while we use our own ABI, the
2095 * only difference is the handling of vtypes:
2096 * - we only pass/receive them in registers in some cases, and only
2097 * in 1 or 2 integer registers.
2099 if (cinfo->ret.storage == ArgValuetypeInReg) {
2101 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2102 cfg->disable_llvm = TRUE;
2106 linfo->ret.storage = LLVMArgVtypeInReg;
2107 for (j = 0; j < 2; ++j)
2108 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2111 if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2112 /* Vtype returned using a hidden argument */
2113 linfo->ret.storage = LLVMArgVtypeRetAddr;
2114 linfo->vret_arg_index = cinfo->vret_arg_index;
2117 for (i = 0; i < n; ++i) {
2118 ainfo = cinfo->args + i;
2120 if (i >= sig->hasthis)
2121 t = sig->params [i - sig->hasthis];
2123 t = &mono_defaults.int_class->byval_arg;
2125 linfo->args [i].storage = LLVMArgNone;
2127 switch (ainfo->storage) {
2129 linfo->args [i].storage = LLVMArgInIReg;
2131 case ArgInDoubleSSEReg:
2132 case ArgInFloatSSEReg:
2133 linfo->args [i].storage = LLVMArgInFPReg;
2136 if (MONO_TYPE_ISSTRUCT (t)) {
2137 linfo->args [i].storage = LLVMArgVtypeByVal;
2139 linfo->args [i].storage = LLVMArgInIReg;
2141 if (t->type == MONO_TYPE_R4)
2142 linfo->args [i].storage = LLVMArgInFPReg;
2143 else if (t->type == MONO_TYPE_R8)
2144 linfo->args [i].storage = LLVMArgInFPReg;
2148 case ArgValuetypeInReg:
2150 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2151 cfg->disable_llvm = TRUE;
2155 linfo->args [i].storage = LLVMArgVtypeInReg;
2156 for (j = 0; j < 2; ++j)
2157 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2160 cfg->exception_message = g_strdup ("ainfo->storage");
2161 cfg->disable_llvm = TRUE;
2171 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2174 MonoMethodSignature *sig;
2180 sig = call->signature;
2181 n = sig->param_count + sig->hasthis;
2183 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2187 if (COMPILE_LLVM (cfg)) {
2188 /* We shouldn't be called in the llvm case */
2189 cfg->disable_llvm = TRUE;
2194 * Emit all arguments which are passed on the stack to prevent register
2195 * allocation problems.
2197 for (i = 0; i < n; ++i) {
2199 ainfo = cinfo->args + i;
2201 in = call->args [i];
2203 if (sig->hasthis && i == 0)
2204 t = &mono_defaults.object_class->byval_arg;
2206 t = sig->params [i - sig->hasthis];
2208 t = mini_get_underlying_type (cfg, t);
2209 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2211 if (t->type == MONO_TYPE_R4)
2212 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2213 else if (t->type == MONO_TYPE_R8)
2214 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2216 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2218 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2220 if (cfg->compute_gc_maps) {
2223 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2229 * Emit all parameters passed in registers in non-reverse order for better readability
2230 * and to help the optimization in emit_prolog ().
2232 for (i = 0; i < n; ++i) {
2233 ainfo = cinfo->args + i;
2235 in = call->args [i];
2237 if (ainfo->storage == ArgInIReg)
2238 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2241 for (i = n - 1; i >= 0; --i) {
2242 ainfo = cinfo->args + i;
2244 in = call->args [i];
2246 switch (ainfo->storage) {
2250 case ArgInFloatSSEReg:
2251 case ArgInDoubleSSEReg:
2252 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2255 case ArgValuetypeInReg:
2256 case ArgValuetypeAddrInIReg:
2257 if (ainfo->storage == ArgOnStack && call->tail_call) {
2258 MonoInst *call_inst = (MonoInst*)call;
2259 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2260 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2261 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2265 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2266 size = sizeof (MonoTypedRef);
2267 align = sizeof (gpointer);
2271 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2274 * Other backends use mono_type_stack_size (), but that
2275 * aligns the size to 8, which is larger than the size of
2276 * the source, leading to reads of invalid memory if the
2277 * source is at the end of address space.
2279 size = mono_class_value_size (in->klass, &align);
2282 g_assert (in->klass);
2284 if (ainfo->storage == ArgOnStack && size >= 10000) {
2285 /* Avoid asserts in emit_memcpy () */
2286 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2287 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2288 /* Continue normally */
2292 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2293 arg->sreg1 = in->dreg;
2294 arg->klass = in->klass;
2295 arg->backend.size = size;
2296 arg->inst_p0 = call;
2297 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2298 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2300 MONO_ADD_INS (cfg->cbb, arg);
2305 g_assert_not_reached ();
2308 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2309 /* Emit the signature cookie just before the implicit arguments */
2310 emit_sig_cookie (cfg, call, cinfo);
2313 /* Handle the case where there are no implicit arguments */
2314 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2315 emit_sig_cookie (cfg, call, cinfo);
2317 sig_ret = mini_get_underlying_type (cfg, sig->ret);
2318 if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2321 if (cinfo->ret.storage == ArgValuetypeInReg) {
2322 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2324 * Tell the JIT to use a more efficient calling convention: call using
2325 * OP_CALL, compute the result location after the call, and save the
2328 call->vret_in_reg = TRUE;
2330 * Nullify the instruction computing the vret addr to enable
2331 * future optimizations.
2334 NULLIFY_INS (call->vret_var);
2336 if (call->tail_call)
2339 * The valuetype is in RAX:RDX after the call, need to be copied to
2340 * the stack. Push the address here, so the call instruction can
2343 if (!cfg->arch.vret_addr_loc) {
2344 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2345 /* Prevent it from being register allocated or optimized away */
2346 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2349 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2353 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2354 vtarg->sreg1 = call->vret_var->dreg;
2355 vtarg->dreg = mono_alloc_preg (cfg);
2356 MONO_ADD_INS (cfg->cbb, vtarg);
2358 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2362 if (cfg->method->save_lmf) {
2363 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2364 MONO_ADD_INS (cfg->cbb, arg);
2367 call->stack_usage = cinfo->stack_usage;
2371 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2374 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2375 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2376 int size = ins->backend.size;
2378 if (ainfo->storage == ArgValuetypeInReg) {
2382 for (part = 0; part < 2; ++part) {
2383 if (ainfo->pair_storage [part] == ArgNone)
2386 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2387 load->inst_basereg = src->dreg;
2388 load->inst_offset = part * sizeof(mgreg_t);
2390 switch (ainfo->pair_storage [part]) {
2392 load->dreg = mono_alloc_ireg (cfg);
2394 case ArgInDoubleSSEReg:
2395 case ArgInFloatSSEReg:
2396 load->dreg = mono_alloc_freg (cfg);
2399 g_assert_not_reached ();
2401 MONO_ADD_INS (cfg->cbb, load);
2403 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2405 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2406 MonoInst *vtaddr, *load;
2407 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2409 MONO_INST_NEW (cfg, load, OP_LDADDR);
2410 cfg->has_indirection = TRUE;
2411 load->inst_p0 = vtaddr;
2412 vtaddr->flags |= MONO_INST_INDIRECT;
2413 load->type = STACK_MP;
2414 load->klass = vtaddr->klass;
2415 load->dreg = mono_alloc_ireg (cfg);
2416 MONO_ADD_INS (cfg->cbb, load);
2417 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2419 if (ainfo->pair_storage [0] == ArgInIReg) {
2420 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2421 arg->dreg = mono_alloc_ireg (cfg);
2422 arg->sreg1 = load->dreg;
2424 MONO_ADD_INS (cfg->cbb, arg);
2425 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2427 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2431 int dreg = mono_alloc_ireg (cfg);
2433 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2434 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2435 } else if (size <= 40) {
2436 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2438 // FIXME: Code growth
2439 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2442 if (cfg->compute_gc_maps) {
2444 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2450 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2452 MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2454 if (ret->type == MONO_TYPE_R4) {
2455 if (COMPILE_LLVM (cfg))
2456 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2458 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2460 } else if (ret->type == MONO_TYPE_R8) {
2461 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2465 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2468 #endif /* DISABLE_JIT */
2470 #define EMIT_COND_BRANCH(ins,cond,sign) \
2471 if (ins->inst_true_bb->native_offset) { \
2472 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2474 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2475 if ((cfg->opt & MONO_OPT_BRANCH) && \
2476 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2477 x86_branch8 (code, cond, 0, sign); \
2479 x86_branch32 (code, cond, 0, sign); \
2483 MonoMethodSignature *sig;
2488 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2496 switch (cinfo->ret.storage) {
2500 case ArgValuetypeInReg: {
2501 ArgInfo *ainfo = &cinfo->ret;
2503 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2505 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2513 for (i = 0; i < cinfo->nargs; ++i) {
2514 ArgInfo *ainfo = &cinfo->args [i];
2515 switch (ainfo->storage) {
2518 case ArgValuetypeInReg:
2519 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2521 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2533 * mono_arch_dyn_call_prepare:
2535 * Return a pointer to an arch-specific structure which contains information
2536 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2537 * supported for SIG.
2538 * This function is equivalent to ffi_prep_cif in libffi.
2541 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2543 ArchDynCallInfo *info;
2546 cinfo = get_call_info (NULL, NULL, sig);
2548 if (!dyn_call_supported (sig, cinfo)) {
2553 info = g_new0 (ArchDynCallInfo, 1);
2554 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2556 info->cinfo = cinfo;
2558 return (MonoDynCallInfo*)info;
2562 * mono_arch_dyn_call_free:
2564 * Free a MonoDynCallInfo structure.
2567 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2569 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2571 g_free (ainfo->cinfo);
2575 #if !defined(__native_client__)
2576 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2577 #define GREG_TO_PTR(greg) (gpointer)(greg)
2579 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2580 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2581 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2585 * mono_arch_get_start_dyn_call:
2587 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2588 * store the result into BUF.
2589 * ARGS should be an array of pointers pointing to the arguments.
2590 * RET should point to a memory buffer large enought to hold the result of the
2592 * This function should be as fast as possible, any work which does not depend
2593 * on the actual values of the arguments should be done in
2594 * mono_arch_dyn_call_prepare ().
2595 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2599 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2601 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2602 DynCallArgs *p = (DynCallArgs*)buf;
2603 int arg_index, greg, i, pindex;
2604 MonoMethodSignature *sig = dinfo->sig;
2606 g_assert (buf_len >= sizeof (DynCallArgs));
2615 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2616 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2621 if (dinfo->cinfo->vtype_retaddr)
2622 p->regs [greg ++] = PTR_TO_GREG(ret);
2624 for (i = pindex; i < sig->param_count; i++) {
2625 MonoType *t = mini_type_get_underlying_type (NULL, sig->params [i]);
2626 gpointer *arg = args [arg_index ++];
2629 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2634 case MONO_TYPE_STRING:
2635 case MONO_TYPE_CLASS:
2636 case MONO_TYPE_ARRAY:
2637 case MONO_TYPE_SZARRAY:
2638 case MONO_TYPE_OBJECT:
2642 #if !defined(__mono_ilp32__)
2646 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2647 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2649 #if defined(__mono_ilp32__)
2652 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2653 p->regs [greg ++] = *(guint64*)(arg);
2657 p->regs [greg ++] = *(guint8*)(arg);
2660 p->regs [greg ++] = *(gint8*)(arg);
2663 p->regs [greg ++] = *(gint16*)(arg);
2666 p->regs [greg ++] = *(guint16*)(arg);
2669 p->regs [greg ++] = *(gint32*)(arg);
2672 p->regs [greg ++] = *(guint32*)(arg);
2674 case MONO_TYPE_GENERICINST:
2675 if (MONO_TYPE_IS_REFERENCE (t)) {
2676 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2681 case MONO_TYPE_VALUETYPE: {
2682 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2684 g_assert (ainfo->storage == ArgValuetypeInReg);
2685 if (ainfo->pair_storage [0] != ArgNone) {
2686 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2687 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2689 if (ainfo->pair_storage [1] != ArgNone) {
2690 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2691 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2696 g_assert_not_reached ();
2700 g_assert (greg <= PARAM_REGS);
2704 * mono_arch_finish_dyn_call:
2706 * Store the result of a dyn call into the return value buffer passed to
2707 * start_dyn_call ().
2708 * This function should be as fast as possible, any work which does not depend
2709 * on the actual values of the arguments should be done in
2710 * mono_arch_dyn_call_prepare ().
2713 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2715 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2716 MonoMethodSignature *sig = dinfo->sig;
2717 guint8 *ret = ((DynCallArgs*)buf)->ret;
2718 mgreg_t res = ((DynCallArgs*)buf)->res;
2719 MonoType *sig_ret = mini_type_get_underlying_type (NULL, sig->ret);
2721 switch (sig_ret->type) {
2722 case MONO_TYPE_VOID:
2723 *(gpointer*)ret = NULL;
2725 case MONO_TYPE_STRING:
2726 case MONO_TYPE_CLASS:
2727 case MONO_TYPE_ARRAY:
2728 case MONO_TYPE_SZARRAY:
2729 case MONO_TYPE_OBJECT:
2733 *(gpointer*)ret = GREG_TO_PTR(res);
2739 *(guint8*)ret = res;
2742 *(gint16*)ret = res;
2745 *(guint16*)ret = res;
2748 *(gint32*)ret = res;
2751 *(guint32*)ret = res;
2754 *(gint64*)ret = res;
2757 *(guint64*)ret = res;
2759 case MONO_TYPE_GENERICINST:
2760 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2761 *(gpointer*)ret = GREG_TO_PTR(res);
2766 case MONO_TYPE_VALUETYPE:
2767 if (dinfo->cinfo->vtype_retaddr) {
2770 ArgInfo *ainfo = &dinfo->cinfo->ret;
2772 g_assert (ainfo->storage == ArgValuetypeInReg);
2774 if (ainfo->pair_storage [0] != ArgNone) {
2775 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2776 ((mgreg_t*)ret)[0] = res;
2779 g_assert (ainfo->pair_storage [1] == ArgNone);
2783 g_assert_not_reached ();
2787 /* emit an exception if condition is fail */
2788 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2790 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2791 if (tins == NULL) { \
2792 mono_add_patch_info (cfg, code - cfg->native_code, \
2793 MONO_PATCH_INFO_EXC, exc_name); \
2794 x86_branch32 (code, cond, 0, signed); \
2796 EMIT_COND_BRANCH (tins, cond, signed); \
2800 #define EMIT_FPCOMPARE(code) do { \
2801 amd64_fcompp (code); \
2802 amd64_fnstsw (code); \
2805 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2806 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2807 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2808 amd64_ ##op (code); \
2809 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2810 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2814 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2816 gboolean no_patch = FALSE;
2819 * FIXME: Add support for thunks
2822 gboolean near_call = FALSE;
2825 * Indirect calls are expensive so try to make a near call if possible.
2826 * The caller memory is allocated by the code manager so it is
2827 * guaranteed to be at a 32 bit offset.
2830 if (patch_type != MONO_PATCH_INFO_ABS) {
2831 /* The target is in memory allocated using the code manager */
2834 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2835 if (((MonoMethod*)data)->klass->image->aot_module)
2836 /* The callee might be an AOT method */
2838 if (((MonoMethod*)data)->dynamic)
2839 /* The target is in malloc-ed memory */
2843 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2845 * The call might go directly to a native function without
2848 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2850 gconstpointer target = mono_icall_get_wrapper (mi);
2851 if ((((guint64)target) >> 32) != 0)
2857 MonoJumpInfo *jinfo = NULL;
2859 if (cfg->abs_patches)
2860 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2862 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2863 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2864 if (mi && (((guint64)mi->func) >> 32) == 0)
2869 * This is not really an optimization, but required because the
2870 * generic class init trampolines use R11 to pass the vtable.
2875 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2877 if (info->func == info->wrapper) {
2879 if ((((guint64)info->func) >> 32) == 0)
2883 /* See the comment in mono_codegen () */
2884 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2888 else if ((((guint64)data) >> 32) == 0) {
2895 if (cfg->method->dynamic)
2896 /* These methods are allocated using malloc */
2899 #ifdef MONO_ARCH_NOMAP32BIT
2902 #if defined(__native_client__)
2903 /* Always use near_call == TRUE for Native Client */
2906 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2907 if (optimize_for_xen)
2910 if (cfg->compile_aot) {
2917 * Align the call displacement to an address divisible by 4 so it does
2918 * not span cache lines. This is required for code patching to work on SMP
2921 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2922 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2923 amd64_padding (code, pad_size);
2925 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2926 amd64_call_code (code, 0);
2929 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2930 amd64_set_reg_template (code, GP_SCRATCH_REG);
2931 amd64_call_reg (code, GP_SCRATCH_REG);
2938 static inline guint8*
2939 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2942 if (win64_adjust_stack)
2943 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2945 code = emit_call_body (cfg, code, patch_type, data);
2947 if (win64_adjust_stack)
2948 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2955 store_membase_imm_to_store_membase_reg (int opcode)
2958 case OP_STORE_MEMBASE_IMM:
2959 return OP_STORE_MEMBASE_REG;
2960 case OP_STOREI4_MEMBASE_IMM:
2961 return OP_STOREI4_MEMBASE_REG;
2962 case OP_STOREI8_MEMBASE_IMM:
2963 return OP_STOREI8_MEMBASE_REG;
2971 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2974 * mono_arch_peephole_pass_1:
2976 * Perform peephole opts which should/can be performed before local regalloc
2979 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2983 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2984 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2986 switch (ins->opcode) {
2990 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2992 * X86_LEA is like ADD, but doesn't have the
2993 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2994 * its operand to 64 bit.
2996 ins->opcode = OP_X86_LEA_MEMBASE;
2997 ins->inst_basereg = ins->sreg1;
3002 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3006 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3007 * the latter has length 2-3 instead of 6 (reverse constant
3008 * propagation). These instruction sequences are very common
3009 * in the initlocals bblock.
3011 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3012 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3013 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3014 ins2->sreg1 = ins->dreg;
3015 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3017 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3020 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3028 case OP_COMPARE_IMM:
3029 case OP_LCOMPARE_IMM:
3030 /* OP_COMPARE_IMM (reg, 0)
3032 * OP_AMD64_TEST_NULL (reg)
3035 ins->opcode = OP_AMD64_TEST_NULL;
3037 case OP_ICOMPARE_IMM:
3039 ins->opcode = OP_X86_TEST_NULL;
3041 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3043 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3044 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3046 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3047 * OP_COMPARE_IMM reg, imm
3049 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3051 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3052 ins->inst_basereg == last_ins->inst_destbasereg &&
3053 ins->inst_offset == last_ins->inst_offset) {
3054 ins->opcode = OP_ICOMPARE_IMM;
3055 ins->sreg1 = last_ins->sreg1;
3057 /* check if we can remove cmp reg,0 with test null */
3059 ins->opcode = OP_X86_TEST_NULL;
3065 mono_peephole_ins (bb, ins);
3070 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3074 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3075 switch (ins->opcode) {
3078 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3079 /* reg = 0 -> XOR (reg, reg) */
3080 /* XOR sets cflags on x86, so we cant do it always */
3081 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3082 ins->opcode = OP_LXOR;
3083 ins->sreg1 = ins->dreg;
3084 ins->sreg2 = ins->dreg;
3092 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3093 * 0 result into 64 bits.
3095 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3096 ins->opcode = OP_IXOR;
3100 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3104 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3105 * the latter has length 2-3 instead of 6 (reverse constant
3106 * propagation). These instruction sequences are very common
3107 * in the initlocals bblock.
3109 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3110 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3111 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3112 ins2->sreg1 = ins->dreg;
3113 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3115 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3118 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3127 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3128 ins->opcode = OP_X86_INC_REG;
3131 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3132 ins->opcode = OP_X86_DEC_REG;
3136 mono_peephole_ins (bb, ins);
3140 #define NEW_INS(cfg,ins,dest,op) do { \
3141 MONO_INST_NEW ((cfg), (dest), (op)); \
3142 (dest)->cil_code = (ins)->cil_code; \
3143 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3147 * mono_arch_lowering_pass:
3149 * Converts complex opcodes into simpler ones so that each IR instruction
3150 * corresponds to one machine instruction.
3153 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3155 MonoInst *ins, *n, *temp;
3158 * FIXME: Need to add more instructions, but the current machine
3159 * description can't model some parts of the composite instructions like
3162 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3163 switch (ins->opcode) {
3167 case OP_IDIV_UN_IMM:
3168 case OP_IREM_UN_IMM:
3171 mono_decompose_op_imm (cfg, bb, ins);
3173 case OP_COMPARE_IMM:
3174 case OP_LCOMPARE_IMM:
3175 if (!amd64_is_imm32 (ins->inst_imm)) {
3176 NEW_INS (cfg, ins, temp, OP_I8CONST);
3177 temp->inst_c0 = ins->inst_imm;
3178 temp->dreg = mono_alloc_ireg (cfg);
3179 ins->opcode = OP_COMPARE;
3180 ins->sreg2 = temp->dreg;
3183 #ifndef __mono_ilp32__
3184 case OP_LOAD_MEMBASE:
3186 case OP_LOADI8_MEMBASE:
3187 #ifndef __native_client_codegen__
3188 /* Don't generate memindex opcodes (to simplify */
3189 /* read sandboxing) */
3190 if (!amd64_is_imm32 (ins->inst_offset)) {
3191 NEW_INS (cfg, ins, temp, OP_I8CONST);
3192 temp->inst_c0 = ins->inst_offset;
3193 temp->dreg = mono_alloc_ireg (cfg);
3194 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3195 ins->inst_indexreg = temp->dreg;
3199 #ifndef __mono_ilp32__
3200 case OP_STORE_MEMBASE_IMM:
3202 case OP_STOREI8_MEMBASE_IMM:
3203 if (!amd64_is_imm32 (ins->inst_imm)) {
3204 NEW_INS (cfg, ins, temp, OP_I8CONST);
3205 temp->inst_c0 = ins->inst_imm;
3206 temp->dreg = mono_alloc_ireg (cfg);
3207 ins->opcode = OP_STOREI8_MEMBASE_REG;
3208 ins->sreg1 = temp->dreg;
3211 #ifdef MONO_ARCH_SIMD_INTRINSICS
3212 case OP_EXPAND_I1: {
3213 int temp_reg1 = mono_alloc_ireg (cfg);
3214 int temp_reg2 = mono_alloc_ireg (cfg);
3215 int original_reg = ins->sreg1;
3217 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3218 temp->sreg1 = original_reg;
3219 temp->dreg = temp_reg1;
3221 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3222 temp->sreg1 = temp_reg1;
3223 temp->dreg = temp_reg2;
3226 NEW_INS (cfg, ins, temp, OP_LOR);
3227 temp->sreg1 = temp->dreg = temp_reg2;
3228 temp->sreg2 = temp_reg1;
3230 ins->opcode = OP_EXPAND_I2;
3231 ins->sreg1 = temp_reg2;
3240 bb->max_vreg = cfg->next_vreg;
3244 branch_cc_table [] = {
3245 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3246 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3247 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3250 /* Maps CMP_... constants to X86_CC_... constants */
3253 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3254 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3258 cc_signed_table [] = {
3259 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3260 FALSE, FALSE, FALSE, FALSE
3263 /*#include "cprop.c"*/
3265 static unsigned char*
3266 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3269 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3271 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3274 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3276 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3280 static unsigned char*
3281 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3283 int sreg = tree->sreg1;
3284 int need_touch = FALSE;
3286 #if defined(TARGET_WIN32)
3288 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3289 if (!tree->flags & MONO_INST_INIT)
3298 * If requested stack size is larger than one page,
3299 * perform stack-touch operation
3302 * Generate stack probe code.
3303 * Under Windows, it is necessary to allocate one page at a time,
3304 * "touching" stack after each successful sub-allocation. This is
3305 * because of the way stack growth is implemented - there is a
3306 * guard page before the lowest stack page that is currently commited.
3307 * Stack normally grows sequentially so OS traps access to the
3308 * guard page and commits more pages when needed.
3310 amd64_test_reg_imm (code, sreg, ~0xFFF);
3311 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3313 br[2] = code; /* loop */
3314 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3315 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3316 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3317 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3318 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3319 amd64_patch (br[3], br[2]);
3320 amd64_test_reg_reg (code, sreg, sreg);
3321 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3322 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3324 br[1] = code; x86_jump8 (code, 0);
3326 amd64_patch (br[0], code);
3327 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3328 amd64_patch (br[1], code);
3329 amd64_patch (br[4], code);
3332 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3334 if (tree->flags & MONO_INST_INIT) {
3336 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3337 amd64_push_reg (code, AMD64_RAX);
3340 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3341 amd64_push_reg (code, AMD64_RCX);
3344 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3345 amd64_push_reg (code, AMD64_RDI);
3349 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3350 if (sreg != AMD64_RCX)
3351 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3352 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3354 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3355 if (cfg->param_area)
3356 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3358 #if defined(__default_codegen__)
3359 amd64_prefix (code, X86_REP_PREFIX);
3361 #elif defined(__native_client_codegen__)
3362 /* NaCl stos pseudo-instruction */
3363 amd64_codegen_pre(code);
3364 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3365 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3366 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3367 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3368 amd64_prefix (code, X86_REP_PREFIX);
3370 amd64_codegen_post(code);
3371 #endif /* __native_client_codegen__ */
3373 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3374 amd64_pop_reg (code, AMD64_RDI);
3375 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3376 amd64_pop_reg (code, AMD64_RCX);
3377 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3378 amd64_pop_reg (code, AMD64_RAX);
3384 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3389 /* Move return value to the target register */
3390 /* FIXME: do this in the local reg allocator */
3391 switch (ins->opcode) {
3394 case OP_CALL_MEMBASE:
3397 case OP_LCALL_MEMBASE:
3398 g_assert (ins->dreg == AMD64_RAX);
3402 case OP_FCALL_MEMBASE: {
3403 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3404 if (rtype->type == MONO_TYPE_R4) {
3405 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3408 if (ins->dreg != AMD64_XMM0)
3409 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3415 case OP_RCALL_MEMBASE:
3416 if (ins->dreg != AMD64_XMM0)
3417 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3421 case OP_VCALL_MEMBASE:
3424 case OP_VCALL2_MEMBASE:
3425 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3426 if (cinfo->ret.storage == ArgValuetypeInReg) {
3427 MonoInst *loc = cfg->arch.vret_addr_loc;
3429 /* Load the destination address */
3430 g_assert (loc->opcode == OP_REGOFFSET);
3431 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3433 for (quad = 0; quad < 2; quad ++) {
3434 switch (cinfo->ret.pair_storage [quad]) {
3436 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3438 case ArgInFloatSSEReg:
3439 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3441 case ArgInDoubleSSEReg:
3442 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3457 #endif /* DISABLE_JIT */
3460 static int tls_gs_offset;
3464 mono_amd64_have_tls_get (void)
3467 static gboolean have_tls_get = FALSE;
3468 static gboolean inited = FALSE;
3472 return have_tls_get;
3474 ins = (guint8*)pthread_getspecific;
3477 * We're looking for these two instructions:
3479 * mov %gs:[offset](,%rdi,8),%rax
3482 have_tls_get = ins [0] == 0x65 &&
3494 tls_gs_offset = ins[5];
3496 return have_tls_get;
3497 #elif defined(TARGET_ANDROID)
3505 mono_amd64_get_tls_gs_offset (void)
3508 return tls_gs_offset;
3510 g_assert_not_reached ();
3516 * mono_amd64_emit_tls_get:
3517 * @code: buffer to store code to
3518 * @dreg: hard register where to place the result
3519 * @tls_offset: offset info
3521 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3522 * the dreg register the item in the thread local storage identified
3525 * Returns: a pointer to the end of the stored code
3528 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3531 if (tls_offset < 64) {
3532 x86_prefix (code, X86_GS_PREFIX);
3533 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3537 g_assert (tls_offset < 0x440);
3538 /* Load TEB->TlsExpansionSlots */
3539 x86_prefix (code, X86_GS_PREFIX);
3540 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3541 amd64_test_reg_reg (code, dreg, dreg);
3543 amd64_branch (code, X86_CC_EQ, code, TRUE);
3544 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3545 amd64_patch (buf [0], code);
3547 #elif defined(__APPLE__)
3548 x86_prefix (code, X86_GS_PREFIX);
3549 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3551 if (optimize_for_xen) {
3552 x86_prefix (code, X86_FS_PREFIX);
3553 amd64_mov_reg_mem (code, dreg, 0, 8);
3554 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3556 x86_prefix (code, X86_FS_PREFIX);
3557 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3564 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3566 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3568 if (dreg != offset_reg)
3569 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3570 amd64_prefix (code, X86_GS_PREFIX);
3571 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3572 #elif defined(__linux__)
3575 if (dreg == offset_reg) {
3576 /* Use a temporary reg by saving it to the redzone */
3577 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3578 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3579 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3580 offset_reg = tmpreg;
3582 x86_prefix (code, X86_FS_PREFIX);
3583 amd64_mov_reg_mem (code, dreg, 0, 8);
3584 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3586 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3588 g_assert_not_reached ();
3594 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3597 g_assert_not_reached ();
3598 #elif defined(__APPLE__)
3599 x86_prefix (code, X86_GS_PREFIX);
3600 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3602 g_assert (!optimize_for_xen);
3603 x86_prefix (code, X86_FS_PREFIX);
3604 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3610 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3612 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3614 g_assert_not_reached ();
3615 #elif defined(__APPLE__)
3616 x86_prefix (code, X86_GS_PREFIX);
3617 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3619 x86_prefix (code, X86_FS_PREFIX);
3620 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3626 * mono_arch_translate_tls_offset:
3628 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3631 mono_arch_translate_tls_offset (int offset)
3634 return tls_gs_offset + (offset * 8);
3643 * Emit code to initialize an LMF structure at LMF_OFFSET.
3646 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3649 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3652 * sp is saved right before calls but we need to save it here too so
3653 * async stack walks would work.
3655 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3657 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3658 if (cfg->arch.omit_fp && cfa_offset != -1)
3659 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3661 /* These can't contain refs */
3662 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3663 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3664 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3665 /* These are handled automatically by the stack marking code */
3666 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3671 #define REAL_PRINT_REG(text,reg) \
3672 mono_assert (reg >= 0); \
3673 amd64_push_reg (code, AMD64_RAX); \
3674 amd64_push_reg (code, AMD64_RDX); \
3675 amd64_push_reg (code, AMD64_RCX); \
3676 amd64_push_reg (code, reg); \
3677 amd64_push_imm (code, reg); \
3678 amd64_push_imm (code, text " %d %p\n"); \
3679 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3680 amd64_call_reg (code, AMD64_RAX); \
3681 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3682 amd64_pop_reg (code, AMD64_RCX); \
3683 amd64_pop_reg (code, AMD64_RDX); \
3684 amd64_pop_reg (code, AMD64_RAX);
3686 /* benchmark and set based on cpu */
3687 #define LOOP_ALIGNMENT 8
3688 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3692 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3697 guint8 *code = cfg->native_code + cfg->code_len;
3700 /* Fix max_offset estimate for each successor bb */
3701 if (cfg->opt & MONO_OPT_BRANCH) {
3702 int current_offset = cfg->code_len;
3703 MonoBasicBlock *current_bb;
3704 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3705 current_bb->max_offset = current_offset;
3706 current_offset += current_bb->max_length;
3710 if (cfg->opt & MONO_OPT_LOOP) {
3711 int pad, align = LOOP_ALIGNMENT;
3712 /* set alignment depending on cpu */
3713 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3715 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3716 amd64_padding (code, pad);
3717 cfg->code_len += pad;
3718 bb->native_offset = cfg->code_len;
3722 #if defined(__native_client_codegen__)
3723 /* For Native Client, all indirect call/jump targets must be */
3724 /* 32-byte aligned. Exception handler blocks are jumped to */
3725 /* indirectly as well. */
3726 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3727 (bb->flags & BB_EXCEPTION_HANDLER);
3729 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3730 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3731 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3732 cfg->code_len += pad;
3733 bb->native_offset = cfg->code_len;
3735 #endif /*__native_client_codegen__*/
3737 if (cfg->verbose_level > 2)
3738 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3740 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3741 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3742 g_assert (!cfg->compile_aot);
3744 cov->data [bb->dfn].cil_code = bb->cil_code;
3745 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3746 /* this is not thread save, but good enough */
3747 amd64_inc_membase (code, AMD64_R11, 0);
3750 offset = code - cfg->native_code;
3752 mono_debug_open_block (cfg, bb, offset);
3754 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3755 x86_breakpoint (code);
3757 MONO_BB_FOR_EACH_INS (bb, ins) {
3758 offset = code - cfg->native_code;
3760 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3762 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3764 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3765 cfg->code_size *= 2;
3766 cfg->native_code = mono_realloc_native_code(cfg);
3767 code = cfg->native_code + offset;
3768 cfg->stat_code_reallocs++;
3771 if (cfg->debug_info)
3772 mono_debug_record_line_number (cfg, ins, offset);
3774 switch (ins->opcode) {
3776 amd64_mul_reg (code, ins->sreg2, TRUE);
3779 amd64_mul_reg (code, ins->sreg2, FALSE);
3781 case OP_X86_SETEQ_MEMBASE:
3782 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3784 case OP_STOREI1_MEMBASE_IMM:
3785 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3787 case OP_STOREI2_MEMBASE_IMM:
3788 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3790 case OP_STOREI4_MEMBASE_IMM:
3791 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3793 case OP_STOREI1_MEMBASE_REG:
3794 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3796 case OP_STOREI2_MEMBASE_REG:
3797 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3799 /* In AMD64 NaCl, pointers are 4 bytes, */
3800 /* so STORE_* != STOREI8_*. Likewise below. */
3801 case OP_STORE_MEMBASE_REG:
3802 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3804 case OP_STOREI8_MEMBASE_REG:
3805 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3807 case OP_STOREI4_MEMBASE_REG:
3808 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3810 case OP_STORE_MEMBASE_IMM:
3811 #ifndef __native_client_codegen__
3812 /* In NaCl, this could be a PCONST type, which could */
3813 /* mean a pointer type was copied directly into the */
3814 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3815 /* the value would be 0x00000000FFFFFFFF which is */
3816 /* not proper for an imm32 unless you cast it. */
3817 g_assert (amd64_is_imm32 (ins->inst_imm));
3819 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3821 case OP_STOREI8_MEMBASE_IMM:
3822 g_assert (amd64_is_imm32 (ins->inst_imm));
3823 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3826 #ifdef __mono_ilp32__
3827 /* In ILP32, pointers are 4 bytes, so separate these */
3828 /* cases, use literal 8 below where we really want 8 */
3829 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3830 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3834 // FIXME: Decompose this earlier
3835 if (amd64_is_imm32 (ins->inst_imm))
3836 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3838 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3839 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3843 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3844 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3847 // FIXME: Decompose this earlier
3848 if (amd64_is_imm32 (ins->inst_imm))
3849 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3851 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3852 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3856 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3857 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3860 /* For NaCl, pointers are 4 bytes, so separate these */
3861 /* cases, use literal 8 below where we really want 8 */
3862 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3863 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3865 case OP_LOAD_MEMBASE:
3866 g_assert (amd64_is_imm32 (ins->inst_offset));
3867 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3869 case OP_LOADI8_MEMBASE:
3870 /* Use literal 8 instead of sizeof pointer or */
3871 /* register, we really want 8 for this opcode */
3872 g_assert (amd64_is_imm32 (ins->inst_offset));
3873 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3875 case OP_LOADI4_MEMBASE:
3876 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3878 case OP_LOADU4_MEMBASE:
3879 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3881 case OP_LOADU1_MEMBASE:
3882 /* The cpu zero extends the result into 64 bits */
3883 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3885 case OP_LOADI1_MEMBASE:
3886 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3888 case OP_LOADU2_MEMBASE:
3889 /* The cpu zero extends the result into 64 bits */
3890 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3892 case OP_LOADI2_MEMBASE:
3893 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3895 case OP_AMD64_LOADI8_MEMINDEX:
3896 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3898 case OP_LCONV_TO_I1:
3899 case OP_ICONV_TO_I1:
3901 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3903 case OP_LCONV_TO_I2:
3904 case OP_ICONV_TO_I2:
3906 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3908 case OP_LCONV_TO_U1:
3909 case OP_ICONV_TO_U1:
3910 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3912 case OP_LCONV_TO_U2:
3913 case OP_ICONV_TO_U2:
3914 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3917 /* Clean out the upper word */
3918 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3921 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3925 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3927 case OP_COMPARE_IMM:
3928 #if defined(__mono_ilp32__)
3929 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3930 g_assert (amd64_is_imm32 (ins->inst_imm));
3931 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3934 case OP_LCOMPARE_IMM:
3935 g_assert (amd64_is_imm32 (ins->inst_imm));
3936 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3938 case OP_X86_COMPARE_REG_MEMBASE:
3939 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3941 case OP_X86_TEST_NULL:
3942 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3944 case OP_AMD64_TEST_NULL:
3945 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3948 case OP_X86_ADD_REG_MEMBASE:
3949 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3951 case OP_X86_SUB_REG_MEMBASE:
3952 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3954 case OP_X86_AND_REG_MEMBASE:
3955 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3957 case OP_X86_OR_REG_MEMBASE:
3958 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3960 case OP_X86_XOR_REG_MEMBASE:
3961 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3964 case OP_X86_ADD_MEMBASE_IMM:
3965 /* FIXME: Make a 64 version too */
3966 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3968 case OP_X86_SUB_MEMBASE_IMM:
3969 g_assert (amd64_is_imm32 (ins->inst_imm));
3970 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3972 case OP_X86_AND_MEMBASE_IMM:
3973 g_assert (amd64_is_imm32 (ins->inst_imm));
3974 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3976 case OP_X86_OR_MEMBASE_IMM:
3977 g_assert (amd64_is_imm32 (ins->inst_imm));
3978 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3980 case OP_X86_XOR_MEMBASE_IMM:
3981 g_assert (amd64_is_imm32 (ins->inst_imm));
3982 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3984 case OP_X86_ADD_MEMBASE_REG:
3985 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3987 case OP_X86_SUB_MEMBASE_REG:
3988 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3990 case OP_X86_AND_MEMBASE_REG:
3991 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3993 case OP_X86_OR_MEMBASE_REG:
3994 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3996 case OP_X86_XOR_MEMBASE_REG:
3997 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3999 case OP_X86_INC_MEMBASE:
4000 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4002 case OP_X86_INC_REG:
4003 amd64_inc_reg_size (code, ins->dreg, 4);
4005 case OP_X86_DEC_MEMBASE:
4006 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4008 case OP_X86_DEC_REG:
4009 amd64_dec_reg_size (code, ins->dreg, 4);
4011 case OP_X86_MUL_REG_MEMBASE:
4012 case OP_X86_MUL_MEMBASE_REG:
4013 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4015 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4016 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4018 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4019 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4021 case OP_AMD64_COMPARE_MEMBASE_REG:
4022 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4024 case OP_AMD64_COMPARE_MEMBASE_IMM:
4025 g_assert (amd64_is_imm32 (ins->inst_imm));
4026 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4028 case OP_X86_COMPARE_MEMBASE8_IMM:
4029 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4031 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4032 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4034 case OP_AMD64_COMPARE_REG_MEMBASE:
4035 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4038 case OP_AMD64_ADD_REG_MEMBASE:
4039 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4041 case OP_AMD64_SUB_REG_MEMBASE:
4042 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4044 case OP_AMD64_AND_REG_MEMBASE:
4045 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4047 case OP_AMD64_OR_REG_MEMBASE:
4048 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4050 case OP_AMD64_XOR_REG_MEMBASE:
4051 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4054 case OP_AMD64_ADD_MEMBASE_REG:
4055 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4057 case OP_AMD64_SUB_MEMBASE_REG:
4058 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4060 case OP_AMD64_AND_MEMBASE_REG:
4061 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4063 case OP_AMD64_OR_MEMBASE_REG:
4064 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4066 case OP_AMD64_XOR_MEMBASE_REG:
4067 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4070 case OP_AMD64_ADD_MEMBASE_IMM:
4071 g_assert (amd64_is_imm32 (ins->inst_imm));
4072 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4074 case OP_AMD64_SUB_MEMBASE_IMM:
4075 g_assert (amd64_is_imm32 (ins->inst_imm));
4076 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4078 case OP_AMD64_AND_MEMBASE_IMM:
4079 g_assert (amd64_is_imm32 (ins->inst_imm));
4080 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4082 case OP_AMD64_OR_MEMBASE_IMM:
4083 g_assert (amd64_is_imm32 (ins->inst_imm));
4084 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4086 case OP_AMD64_XOR_MEMBASE_IMM:
4087 g_assert (amd64_is_imm32 (ins->inst_imm));
4088 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4092 amd64_breakpoint (code);
4094 case OP_RELAXED_NOP:
4095 x86_prefix (code, X86_REP_PREFIX);
4103 case OP_DUMMY_STORE:
4104 case OP_DUMMY_ICONST:
4105 case OP_DUMMY_R8CONST:
4106 case OP_NOT_REACHED:
4109 case OP_IL_SEQ_POINT:
4110 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4112 case OP_SEQ_POINT: {
4115 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4116 if (cfg->compile_aot) {
4117 MonoInst *var = cfg->arch.ss_tramp_var;
4120 /* Load ss_tramp_var */
4121 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4122 /* Load the trampoline address */
4123 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4124 /* Call it if it is non-null */
4125 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4127 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4128 amd64_call_reg (code, AMD64_R11);
4129 amd64_patch (label, code);
4132 * Read from the single stepping trigger page. This will cause a
4133 * SIGSEGV when single stepping is enabled.
4134 * We do this _before_ the breakpoint, so single stepping after
4135 * a breakpoint is hit will step to the next IL offset.
4137 MonoInst *var = cfg->arch.ss_trigger_page_var;
4139 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4140 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4145 * This is the address which is saved in seq points,
4147 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4149 if (cfg->compile_aot) {
4150 guint32 offset = code - cfg->native_code;
4152 MonoInst *info_var = cfg->arch.seq_point_info_var;
4156 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4157 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4158 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4159 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4160 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4162 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4163 /* Call the trampoline */
4164 amd64_call_reg (code, AMD64_R11);
4165 amd64_patch (label, code);
4168 * A placeholder for a possible breakpoint inserted by
4169 * mono_arch_set_breakpoint ().
4171 for (i = 0; i < breakpoint_size; ++i)
4175 * Add an additional nop so skipping the bp doesn't cause the ip to point
4176 * to another IL offset.
4184 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4187 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4191 g_assert (amd64_is_imm32 (ins->inst_imm));
4192 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4195 g_assert (amd64_is_imm32 (ins->inst_imm));
4196 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4201 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4204 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4208 g_assert (amd64_is_imm32 (ins->inst_imm));
4209 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4212 g_assert (amd64_is_imm32 (ins->inst_imm));
4213 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4216 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4220 g_assert (amd64_is_imm32 (ins->inst_imm));
4221 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4224 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4229 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4231 switch (ins->inst_imm) {
4235 if (ins->dreg != ins->sreg1)
4236 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4237 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4240 /* LEA r1, [r2 + r2*2] */
4241 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4244 /* LEA r1, [r2 + r2*4] */
4245 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4248 /* LEA r1, [r2 + r2*2] */
4250 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4251 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4254 /* LEA r1, [r2 + r2*8] */
4255 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4258 /* LEA r1, [r2 + r2*4] */
4260 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4261 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4264 /* LEA r1, [r2 + r2*2] */
4266 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4267 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4270 /* LEA r1, [r2 + r2*4] */
4271 /* LEA r1, [r1 + r1*4] */
4272 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4273 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4276 /* LEA r1, [r2 + r2*4] */
4278 /* LEA r1, [r1 + r1*4] */
4279 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4280 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4281 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4284 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4291 #if defined( __native_client_codegen__ )
4292 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4293 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4295 /* Regalloc magic makes the div/rem cases the same */
4296 if (ins->sreg2 == AMD64_RDX) {
4297 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4299 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4302 amd64_div_reg (code, ins->sreg2, TRUE);
4307 #if defined( __native_client_codegen__ )
4308 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4309 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4311 if (ins->sreg2 == AMD64_RDX) {
4312 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4313 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4314 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4316 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4317 amd64_div_reg (code, ins->sreg2, FALSE);
4322 #if defined( __native_client_codegen__ )
4323 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4324 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4326 if (ins->sreg2 == AMD64_RDX) {
4327 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4328 amd64_cdq_size (code, 4);
4329 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4331 amd64_cdq_size (code, 4);
4332 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4337 #if defined( __native_client_codegen__ )
4338 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4339 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4341 if (ins->sreg2 == AMD64_RDX) {
4342 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4343 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4344 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4346 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4347 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4351 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4352 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4355 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4359 g_assert (amd64_is_imm32 (ins->inst_imm));
4360 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4363 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4367 g_assert (amd64_is_imm32 (ins->inst_imm));
4368 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4371 g_assert (ins->sreg2 == AMD64_RCX);
4372 amd64_shift_reg (code, X86_SHL, ins->dreg);
4375 g_assert (ins->sreg2 == AMD64_RCX);
4376 amd64_shift_reg (code, X86_SAR, ins->dreg);
4380 g_assert (amd64_is_imm32 (ins->inst_imm));
4381 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4384 g_assert (amd64_is_imm32 (ins->inst_imm));
4385 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4387 case OP_LSHR_UN_IMM:
4388 g_assert (amd64_is_imm32 (ins->inst_imm));
4389 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4392 g_assert (ins->sreg2 == AMD64_RCX);
4393 amd64_shift_reg (code, X86_SHR, ins->dreg);
4397 g_assert (amd64_is_imm32 (ins->inst_imm));
4398 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4403 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4406 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4409 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4412 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4416 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4419 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4422 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4425 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4428 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4431 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4434 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4437 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4440 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4443 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4446 amd64_neg_reg_size (code, ins->sreg1, 4);
4449 amd64_not_reg_size (code, ins->sreg1, 4);
4452 g_assert (ins->sreg2 == AMD64_RCX);
4453 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4456 g_assert (ins->sreg2 == AMD64_RCX);
4457 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4460 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4462 case OP_ISHR_UN_IMM:
4463 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4466 g_assert (ins->sreg2 == AMD64_RCX);
4467 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4470 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4473 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4476 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4477 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4479 case OP_IMUL_OVF_UN:
4480 case OP_LMUL_OVF_UN: {
4481 /* the mul operation and the exception check should most likely be split */
4482 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4483 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4484 /*g_assert (ins->sreg2 == X86_EAX);
4485 g_assert (ins->dreg == X86_EAX);*/
4486 if (ins->sreg2 == X86_EAX) {
4487 non_eax_reg = ins->sreg1;
4488 } else if (ins->sreg1 == X86_EAX) {
4489 non_eax_reg = ins->sreg2;
4491 /* no need to save since we're going to store to it anyway */
4492 if (ins->dreg != X86_EAX) {
4494 amd64_push_reg (code, X86_EAX);
4496 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4497 non_eax_reg = ins->sreg2;
4499 if (ins->dreg == X86_EDX) {
4502 amd64_push_reg (code, X86_EAX);
4506 amd64_push_reg (code, X86_EDX);
4508 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4509 /* save before the check since pop and mov don't change the flags */
4510 if (ins->dreg != X86_EAX)
4511 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4513 amd64_pop_reg (code, X86_EDX);
4515 amd64_pop_reg (code, X86_EAX);
4516 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4520 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4522 case OP_ICOMPARE_IMM:
4523 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4545 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4553 case OP_CMOV_INE_UN:
4554 case OP_CMOV_IGE_UN:
4555 case OP_CMOV_IGT_UN:
4556 case OP_CMOV_ILE_UN:
4557 case OP_CMOV_ILT_UN:
4563 case OP_CMOV_LNE_UN:
4564 case OP_CMOV_LGE_UN:
4565 case OP_CMOV_LGT_UN:
4566 case OP_CMOV_LLE_UN:
4567 case OP_CMOV_LLT_UN:
4568 g_assert (ins->dreg == ins->sreg1);
4569 /* This needs to operate on 64 bit values */
4570 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4574 amd64_not_reg (code, ins->sreg1);
4577 amd64_neg_reg (code, ins->sreg1);
4582 if ((((guint64)ins->inst_c0) >> 32) == 0)
4583 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4585 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4588 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4589 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4592 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4593 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4596 if (ins->dreg != ins->sreg1)
4597 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4599 case OP_AMD64_SET_XMMREG_R4: {
4601 if (ins->dreg != ins->sreg1)
4602 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4604 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4608 case OP_AMD64_SET_XMMREG_R8: {
4609 if (ins->dreg != ins->sreg1)
4610 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4614 MonoCallInst *call = (MonoCallInst*)ins;
4615 int i, save_area_offset;
4617 g_assert (!cfg->method->save_lmf);
4619 /* Restore callee saved registers */
4620 save_area_offset = cfg->arch.reg_save_area_offset;
4621 for (i = 0; i < AMD64_NREG; ++i)
4622 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4623 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4624 save_area_offset += 8;
4627 if (cfg->arch.omit_fp) {
4628 if (cfg->arch.stack_alloc_size)
4629 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4631 if (call->stack_usage)
4634 /* Copy arguments on the stack to our argument area */
4635 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4636 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4637 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4643 offset = code - cfg->native_code;
4644 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4645 if (cfg->compile_aot)
4646 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4648 amd64_set_reg_template (code, AMD64_R11);
4649 amd64_jump_reg (code, AMD64_R11);
4650 ins->flags |= MONO_INST_GC_CALLSITE;
4651 ins->backend.pc_offset = code - cfg->native_code;
4655 /* ensure ins->sreg1 is not NULL */
4656 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4659 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4660 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4670 call = (MonoCallInst*)ins;
4672 * The AMD64 ABI forces callers to know about varargs.
4674 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4675 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4676 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4678 * Since the unmanaged calling convention doesn't contain a
4679 * 'vararg' entry, we have to treat every pinvoke call as a
4680 * potential vararg call.
4684 for (i = 0; i < AMD64_XMM_NREG; ++i)
4685 if (call->used_fregs & (1 << i))
4688 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4690 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4693 if (ins->flags & MONO_INST_HAS_METHOD)
4694 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4696 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4697 ins->flags |= MONO_INST_GC_CALLSITE;
4698 ins->backend.pc_offset = code - cfg->native_code;
4699 code = emit_move_return_value (cfg, ins, code);
4706 case OP_VOIDCALL_REG:
4708 call = (MonoCallInst*)ins;
4710 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4711 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4712 ins->sreg1 = AMD64_R11;
4716 * The AMD64 ABI forces callers to know about varargs.
4718 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4719 if (ins->sreg1 == AMD64_RAX) {
4720 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4721 ins->sreg1 = AMD64_R11;
4723 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4724 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4726 * Since the unmanaged calling convention doesn't contain a
4727 * 'vararg' entry, we have to treat every pinvoke call as a
4728 * potential vararg call.
4732 for (i = 0; i < AMD64_XMM_NREG; ++i)
4733 if (call->used_fregs & (1 << i))
4735 if (ins->sreg1 == AMD64_RAX) {
4736 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4737 ins->sreg1 = AMD64_R11;
4740 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4742 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4745 amd64_call_reg (code, ins->sreg1);
4746 ins->flags |= MONO_INST_GC_CALLSITE;
4747 ins->backend.pc_offset = code - cfg->native_code;
4748 code = emit_move_return_value (cfg, ins, code);
4750 case OP_FCALL_MEMBASE:
4751 case OP_RCALL_MEMBASE:
4752 case OP_LCALL_MEMBASE:
4753 case OP_VCALL_MEMBASE:
4754 case OP_VCALL2_MEMBASE:
4755 case OP_VOIDCALL_MEMBASE:
4756 case OP_CALL_MEMBASE:
4757 call = (MonoCallInst*)ins;
4759 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4760 ins->flags |= MONO_INST_GC_CALLSITE;
4761 ins->backend.pc_offset = code - cfg->native_code;
4762 code = emit_move_return_value (cfg, ins, code);
4766 MonoInst *var = cfg->dyn_call_var;
4768 g_assert (var->opcode == OP_REGOFFSET);
4770 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4771 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4773 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4775 /* Save args buffer */
4776 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4778 /* Set argument registers */
4779 for (i = 0; i < PARAM_REGS; ++i)
4780 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4783 amd64_call_reg (code, AMD64_R10);
4785 ins->flags |= MONO_INST_GC_CALLSITE;
4786 ins->backend.pc_offset = code - cfg->native_code;
4789 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4790 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4793 case OP_AMD64_SAVE_SP_TO_LMF: {
4794 MonoInst *lmf_var = cfg->lmf_var;
4795 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4799 g_assert_not_reached ();
4800 amd64_push_reg (code, ins->sreg1);
4802 case OP_X86_PUSH_IMM:
4803 g_assert_not_reached ();
4804 g_assert (amd64_is_imm32 (ins->inst_imm));
4805 amd64_push_imm (code, ins->inst_imm);
4807 case OP_X86_PUSH_MEMBASE:
4808 g_assert_not_reached ();
4809 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4811 case OP_X86_PUSH_OBJ: {
4812 int size = ALIGN_TO (ins->inst_imm, 8);
4814 g_assert_not_reached ();
4816 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4817 amd64_push_reg (code, AMD64_RDI);
4818 amd64_push_reg (code, AMD64_RSI);
4819 amd64_push_reg (code, AMD64_RCX);
4820 if (ins->inst_offset)
4821 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4823 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4824 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4825 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4827 amd64_prefix (code, X86_REP_PREFIX);
4829 amd64_pop_reg (code, AMD64_RCX);
4830 amd64_pop_reg (code, AMD64_RSI);
4831 amd64_pop_reg (code, AMD64_RDI);
4835 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4837 case OP_X86_LEA_MEMBASE:
4838 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4841 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4844 /* keep alignment */
4845 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4846 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4847 code = mono_emit_stack_alloc (cfg, code, ins);
4848 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4849 if (cfg->param_area)
4850 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4852 case OP_LOCALLOC_IMM: {
4853 guint32 size = ins->inst_imm;
4854 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4856 if (ins->flags & MONO_INST_INIT) {
4860 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4861 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4863 for (i = 0; i < size; i += 8)
4864 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4865 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4867 amd64_mov_reg_imm (code, ins->dreg, size);
4868 ins->sreg1 = ins->dreg;
4870 code = mono_emit_stack_alloc (cfg, code, ins);
4871 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4874 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4875 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4877 if (cfg->param_area)
4878 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4882 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4883 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4884 (gpointer)"mono_arch_throw_exception", FALSE);
4885 ins->flags |= MONO_INST_GC_CALLSITE;
4886 ins->backend.pc_offset = code - cfg->native_code;
4890 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4891 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4892 (gpointer)"mono_arch_rethrow_exception", FALSE);
4893 ins->flags |= MONO_INST_GC_CALLSITE;
4894 ins->backend.pc_offset = code - cfg->native_code;
4897 case OP_CALL_HANDLER:
4899 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4900 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4901 amd64_call_imm (code, 0);
4902 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4903 /* Restore stack alignment */
4904 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4906 case OP_START_HANDLER: {
4907 /* Even though we're saving RSP, use sizeof */
4908 /* gpointer because spvar is of type IntPtr */
4909 /* see: mono_create_spvar_for_region */
4910 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4911 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4913 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4914 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4916 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4920 case OP_ENDFINALLY: {
4921 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4922 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4926 case OP_ENDFILTER: {
4927 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4928 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4929 /* The local allocator will put the result into RAX */
4934 if (ins->dreg != AMD64_RAX)
4935 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4938 ins->inst_c0 = code - cfg->native_code;
4941 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4942 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4944 if (ins->inst_target_bb->native_offset) {
4945 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4947 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4948 if ((cfg->opt & MONO_OPT_BRANCH) &&
4949 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4950 x86_jump8 (code, 0);
4952 x86_jump32 (code, 0);
4956 amd64_jump_reg (code, ins->sreg1);
4979 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4980 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4982 case OP_COND_EXC_EQ:
4983 case OP_COND_EXC_NE_UN:
4984 case OP_COND_EXC_LT:
4985 case OP_COND_EXC_LT_UN:
4986 case OP_COND_EXC_GT:
4987 case OP_COND_EXC_GT_UN:
4988 case OP_COND_EXC_GE:
4989 case OP_COND_EXC_GE_UN:
4990 case OP_COND_EXC_LE:
4991 case OP_COND_EXC_LE_UN:
4992 case OP_COND_EXC_IEQ:
4993 case OP_COND_EXC_INE_UN:
4994 case OP_COND_EXC_ILT:
4995 case OP_COND_EXC_ILT_UN:
4996 case OP_COND_EXC_IGT:
4997 case OP_COND_EXC_IGT_UN:
4998 case OP_COND_EXC_IGE:
4999 case OP_COND_EXC_IGE_UN:
5000 case OP_COND_EXC_ILE:
5001 case OP_COND_EXC_ILE_UN:
5002 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5004 case OP_COND_EXC_OV:
5005 case OP_COND_EXC_NO:
5007 case OP_COND_EXC_NC:
5008 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5009 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5011 case OP_COND_EXC_IOV:
5012 case OP_COND_EXC_INO:
5013 case OP_COND_EXC_IC:
5014 case OP_COND_EXC_INC:
5015 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5016 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5019 /* floating point opcodes */
5021 double d = *(double *)ins->inst_p0;
5023 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5024 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5027 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5028 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5033 float f = *(float *)ins->inst_p0;
5035 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5037 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5039 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5042 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5043 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5045 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5049 case OP_STORER8_MEMBASE_REG:
5050 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5052 case OP_LOADR8_MEMBASE:
5053 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5055 case OP_STORER4_MEMBASE_REG:
5057 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5059 /* This requires a double->single conversion */
5060 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5061 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5064 case OP_LOADR4_MEMBASE:
5066 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5068 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5069 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5072 case OP_ICONV_TO_R4:
5074 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5076 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5077 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5080 case OP_ICONV_TO_R8:
5081 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5083 case OP_LCONV_TO_R4:
5085 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5087 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5088 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5091 case OP_LCONV_TO_R8:
5092 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5094 case OP_FCONV_TO_R4:
5096 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5098 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5099 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5102 case OP_FCONV_TO_I1:
5103 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5105 case OP_FCONV_TO_U1:
5106 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5108 case OP_FCONV_TO_I2:
5109 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5111 case OP_FCONV_TO_U2:
5112 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5114 case OP_FCONV_TO_U4:
5115 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5117 case OP_FCONV_TO_I4:
5119 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5121 case OP_FCONV_TO_I8:
5122 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5125 case OP_RCONV_TO_I1:
5126 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5127 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5129 case OP_RCONV_TO_U1:
5130 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5131 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5133 case OP_RCONV_TO_I2:
5134 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5135 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5137 case OP_RCONV_TO_U2:
5138 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5139 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5141 case OP_RCONV_TO_I4:
5142 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5144 case OP_RCONV_TO_U4:
5145 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5147 case OP_RCONV_TO_I8:
5148 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5150 case OP_RCONV_TO_R8:
5151 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5153 case OP_RCONV_TO_R4:
5154 if (ins->dreg != ins->sreg1)
5155 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5158 case OP_LCONV_TO_R_UN: {
5161 /* Based on gcc code */
5162 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5163 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5166 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5167 br [1] = code; x86_jump8 (code, 0);
5168 amd64_patch (br [0], code);
5171 /* Save to the red zone */
5172 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5173 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5174 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5175 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5176 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5177 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5178 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5179 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5180 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5182 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5183 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5184 amd64_patch (br [1], code);
5187 case OP_LCONV_TO_OVF_U4:
5188 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5189 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5190 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5192 case OP_LCONV_TO_OVF_I4_UN:
5193 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5194 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5195 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5198 if (ins->dreg != ins->sreg1)
5199 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5202 if (ins->dreg != ins->sreg1)
5203 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5205 case OP_MOVE_F_TO_I4:
5207 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5209 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5210 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5213 case OP_MOVE_I4_TO_F:
5214 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5216 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5218 case OP_MOVE_F_TO_I8:
5219 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5221 case OP_MOVE_I8_TO_F:
5222 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5225 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5228 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5231 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5234 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5237 static double r8_0 = -0.0;
5239 g_assert (ins->sreg1 == ins->dreg);
5241 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5242 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5246 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5249 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5252 static guint64 d = 0x7fffffffffffffffUL;
5254 g_assert (ins->sreg1 == ins->dreg);
5256 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5257 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5261 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5265 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5268 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5271 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5274 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5277 static float r4_0 = -0.0;
5279 g_assert (ins->sreg1 == ins->dreg);
5281 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5282 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5283 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5288 g_assert (cfg->opt & MONO_OPT_CMOV);
5289 g_assert (ins->dreg == ins->sreg1);
5290 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5291 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5294 g_assert (cfg->opt & MONO_OPT_CMOV);
5295 g_assert (ins->dreg == ins->sreg1);
5296 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5297 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5300 g_assert (cfg->opt & MONO_OPT_CMOV);
5301 g_assert (ins->dreg == ins->sreg1);
5302 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5303 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5306 g_assert (cfg->opt & MONO_OPT_CMOV);
5307 g_assert (ins->dreg == ins->sreg1);
5308 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5309 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5312 g_assert (cfg->opt & MONO_OPT_CMOV);
5313 g_assert (ins->dreg == ins->sreg1);
5314 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5315 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5318 g_assert (cfg->opt & MONO_OPT_CMOV);
5319 g_assert (ins->dreg == ins->sreg1);
5320 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5321 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5324 g_assert (cfg->opt & MONO_OPT_CMOV);
5325 g_assert (ins->dreg == ins->sreg1);
5326 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5327 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5330 g_assert (cfg->opt & MONO_OPT_CMOV);
5331 g_assert (ins->dreg == ins->sreg1);
5332 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5333 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5339 * The two arguments are swapped because the fbranch instructions
5340 * depend on this for the non-sse case to work.
5342 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5346 * FIXME: Get rid of this.
5347 * The two arguments are swapped because the fbranch instructions
5348 * depend on this for the non-sse case to work.
5350 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5354 /* zeroing the register at the start results in
5355 * shorter and faster code (we can also remove the widening op)
5357 guchar *unordered_check;
5359 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5360 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5361 unordered_check = code;
5362 x86_branch8 (code, X86_CC_P, 0, FALSE);
5364 if (ins->opcode == OP_FCEQ) {
5365 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5366 amd64_patch (unordered_check, code);
5368 guchar *jump_to_end;
5369 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5371 x86_jump8 (code, 0);
5372 amd64_patch (unordered_check, code);
5373 amd64_inc_reg (code, ins->dreg);
5374 amd64_patch (jump_to_end, code);
5380 /* zeroing the register at the start results in
5381 * shorter and faster code (we can also remove the widening op)
5383 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5384 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5385 if (ins->opcode == OP_FCLT_UN) {
5386 guchar *unordered_check = code;
5387 guchar *jump_to_end;
5388 x86_branch8 (code, X86_CC_P, 0, FALSE);
5389 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5391 x86_jump8 (code, 0);
5392 amd64_patch (unordered_check, code);
5393 amd64_inc_reg (code, ins->dreg);
5394 amd64_patch (jump_to_end, code);
5396 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5401 guchar *unordered_check;
5402 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5403 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5404 unordered_check = code;
5405 x86_branch8 (code, X86_CC_P, 0, FALSE);
5406 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5407 amd64_patch (unordered_check, code);
5412 /* zeroing the register at the start results in
5413 * shorter and faster code (we can also remove the widening op)
5415 guchar *unordered_check;
5417 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5418 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5419 if (ins->opcode == OP_FCGT) {
5420 unordered_check = code;
5421 x86_branch8 (code, X86_CC_P, 0, FALSE);
5422 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5423 amd64_patch (unordered_check, code);
5425 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5430 guchar *unordered_check;
5431 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5432 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5433 unordered_check = code;
5434 x86_branch8 (code, X86_CC_P, 0, FALSE);
5435 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5436 amd64_patch (unordered_check, code);
5446 gboolean unordered = FALSE;
5448 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5449 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5451 switch (ins->opcode) {
5453 x86_cond = X86_CC_EQ;
5456 x86_cond = X86_CC_LT;
5459 x86_cond = X86_CC_GT;
5462 x86_cond = X86_CC_GT;
5466 x86_cond = X86_CC_LT;
5470 g_assert_not_reached ();
5475 guchar *unordered_check;
5476 guchar *jump_to_end;
5478 unordered_check = code;
5479 x86_branch8 (code, X86_CC_P, 0, FALSE);
5480 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5482 x86_jump8 (code, 0);
5483 amd64_patch (unordered_check, code);
5484 amd64_inc_reg (code, ins->dreg);
5485 amd64_patch (jump_to_end, code);
5487 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5491 case OP_FCLT_MEMBASE:
5492 case OP_FCGT_MEMBASE:
5493 case OP_FCLT_UN_MEMBASE:
5494 case OP_FCGT_UN_MEMBASE:
5495 case OP_FCEQ_MEMBASE: {
5496 guchar *unordered_check, *jump_to_end;
5499 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5500 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5502 switch (ins->opcode) {
5503 case OP_FCEQ_MEMBASE:
5504 x86_cond = X86_CC_EQ;
5506 case OP_FCLT_MEMBASE:
5507 case OP_FCLT_UN_MEMBASE:
5508 x86_cond = X86_CC_LT;
5510 case OP_FCGT_MEMBASE:
5511 case OP_FCGT_UN_MEMBASE:
5512 x86_cond = X86_CC_GT;
5515 g_assert_not_reached ();
5518 unordered_check = code;
5519 x86_branch8 (code, X86_CC_P, 0, FALSE);
5520 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5522 switch (ins->opcode) {
5523 case OP_FCEQ_MEMBASE:
5524 case OP_FCLT_MEMBASE:
5525 case OP_FCGT_MEMBASE:
5526 amd64_patch (unordered_check, code);
5528 case OP_FCLT_UN_MEMBASE:
5529 case OP_FCGT_UN_MEMBASE:
5531 x86_jump8 (code, 0);
5532 amd64_patch (unordered_check, code);
5533 amd64_inc_reg (code, ins->dreg);
5534 amd64_patch (jump_to_end, code);
5542 guchar *jump = code;
5543 x86_branch8 (code, X86_CC_P, 0, TRUE);
5544 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5545 amd64_patch (jump, code);
5549 /* Branch if C013 != 100 */
5550 /* branch if !ZF or (PF|CF) */
5551 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5552 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5553 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5556 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5559 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5560 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5564 if (ins->opcode == OP_FBGT) {
5567 /* skip branch if C1=1 */
5569 x86_branch8 (code, X86_CC_P, 0, FALSE);
5570 /* branch if (C0 | C3) = 1 */
5571 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5572 amd64_patch (br1, code);
5575 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5579 /* Branch if C013 == 100 or 001 */
5582 /* skip branch if C1=1 */
5584 x86_branch8 (code, X86_CC_P, 0, FALSE);
5585 /* branch if (C0 | C3) = 1 */
5586 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5587 amd64_patch (br1, code);
5591 /* Branch if C013 == 000 */
5592 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5595 /* Branch if C013=000 or 100 */
5598 /* skip branch if C1=1 */
5600 x86_branch8 (code, X86_CC_P, 0, FALSE);
5601 /* branch if C0=0 */
5602 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5603 amd64_patch (br1, code);
5607 /* Branch if C013 != 001 */
5608 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5609 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5612 /* Transfer value to the fp stack */
5613 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5614 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5615 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5617 amd64_push_reg (code, AMD64_RAX);
5619 amd64_fnstsw (code);
5620 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5621 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5622 amd64_pop_reg (code, AMD64_RAX);
5623 amd64_fstp (code, 0);
5624 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5625 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5628 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5631 case OP_TLS_GET_REG:
5632 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5635 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5638 case OP_TLS_SET_REG: {
5639 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5642 case OP_MEMORY_BARRIER: {
5643 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5647 case OP_ATOMIC_ADD_I4:
5648 case OP_ATOMIC_ADD_I8: {
5649 int dreg = ins->dreg;
5650 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5652 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5655 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5656 amd64_prefix (code, X86_LOCK_PREFIX);
5657 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5658 /* dreg contains the old value, add with sreg2 value */
5659 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5661 if (ins->dreg != dreg)
5662 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5666 case OP_ATOMIC_EXCHANGE_I4:
5667 case OP_ATOMIC_EXCHANGE_I8: {
5668 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5670 /* LOCK prefix is implied. */
5671 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5672 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5673 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5676 case OP_ATOMIC_CAS_I4:
5677 case OP_ATOMIC_CAS_I8: {
5680 if (ins->opcode == OP_ATOMIC_CAS_I8)
5686 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5687 * an explanation of how this works.
5689 g_assert (ins->sreg3 == AMD64_RAX);
5690 g_assert (ins->sreg1 != AMD64_RAX);
5691 g_assert (ins->sreg1 != ins->sreg2);
5693 amd64_prefix (code, X86_LOCK_PREFIX);
5694 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5696 if (ins->dreg != AMD64_RAX)
5697 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5700 case OP_ATOMIC_LOAD_I1: {
5701 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5704 case OP_ATOMIC_LOAD_U1: {
5705 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5708 case OP_ATOMIC_LOAD_I2: {
5709 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5712 case OP_ATOMIC_LOAD_U2: {
5713 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5716 case OP_ATOMIC_LOAD_I4: {
5717 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5720 case OP_ATOMIC_LOAD_U4:
5721 case OP_ATOMIC_LOAD_I8:
5722 case OP_ATOMIC_LOAD_U8: {
5723 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5726 case OP_ATOMIC_LOAD_R4: {
5727 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5728 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5731 case OP_ATOMIC_LOAD_R8: {
5732 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5735 case OP_ATOMIC_STORE_I1:
5736 case OP_ATOMIC_STORE_U1:
5737 case OP_ATOMIC_STORE_I2:
5738 case OP_ATOMIC_STORE_U2:
5739 case OP_ATOMIC_STORE_I4:
5740 case OP_ATOMIC_STORE_U4:
5741 case OP_ATOMIC_STORE_I8:
5742 case OP_ATOMIC_STORE_U8: {
5745 switch (ins->opcode) {
5746 case OP_ATOMIC_STORE_I1:
5747 case OP_ATOMIC_STORE_U1:
5750 case OP_ATOMIC_STORE_I2:
5751 case OP_ATOMIC_STORE_U2:
5754 case OP_ATOMIC_STORE_I4:
5755 case OP_ATOMIC_STORE_U4:
5758 case OP_ATOMIC_STORE_I8:
5759 case OP_ATOMIC_STORE_U8:
5764 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5766 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5770 case OP_ATOMIC_STORE_R4: {
5771 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5772 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5774 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5778 case OP_ATOMIC_STORE_R8: {
5781 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5785 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5789 case OP_CARD_TABLE_WBARRIER: {
5790 int ptr = ins->sreg1;
5791 int value = ins->sreg2;
5793 int nursery_shift, card_table_shift;
5794 gpointer card_table_mask;
5795 size_t nursery_size;
5797 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5798 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5799 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5801 /*If either point to the stack we can simply avoid the WB. This happens due to
5802 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5804 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5808 * We need one register we can clobber, we choose EDX and make sreg1
5809 * fixed EAX to work around limitations in the local register allocator.
5810 * sreg2 might get allocated to EDX, but that is not a problem since
5811 * we use it before clobbering EDX.
5813 g_assert (ins->sreg1 == AMD64_RAX);
5816 * This is the code we produce:
5819 * edx >>= nursery_shift
5820 * cmp edx, (nursery_start >> nursery_shift)
5823 * edx >>= card_table_shift
5829 if (mono_gc_card_table_nursery_check ()) {
5830 if (value != AMD64_RDX)
5831 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5832 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5833 if (shifted_nursery_start >> 31) {
5835 * The value we need to compare against is 64 bits, so we need
5836 * another spare register. We use RBX, which we save and
5839 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5840 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5841 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5842 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5844 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5846 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5848 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5849 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5850 if (card_table_mask)
5851 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5853 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5854 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5856 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5858 if (mono_gc_card_table_nursery_check ())
5859 x86_patch (br, code);
5862 #ifdef MONO_ARCH_SIMD_INTRINSICS
5863 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5865 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5868 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5871 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5874 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5877 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5880 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5883 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5884 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5887 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5890 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5893 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5896 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5899 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5902 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5905 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5908 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5911 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5914 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5917 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5920 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5923 case OP_PSHUFLEW_HIGH:
5924 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5925 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5927 case OP_PSHUFLEW_LOW:
5928 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5929 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5932 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5933 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5936 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5937 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5940 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5941 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5945 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5948 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5951 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5954 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5957 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5960 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5963 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5964 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5967 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5970 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5973 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5976 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5979 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5982 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5985 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5988 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5991 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5994 case OP_EXTRACT_MASK:
5995 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5999 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6002 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6005 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6009 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6015 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6018 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6022 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6025 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6028 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6031 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6035 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6038 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6041 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6045 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6048 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6051 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6055 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6058 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6062 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6065 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6068 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6072 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6075 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6078 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6082 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6085 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6088 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6091 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6095 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6098 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6101 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6104 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6107 case OP_PSUM_ABS_DIFF:
6108 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6111 case OP_UNPACK_LOWB:
6112 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6114 case OP_UNPACK_LOWW:
6115 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6117 case OP_UNPACK_LOWD:
6118 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6120 case OP_UNPACK_LOWQ:
6121 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6123 case OP_UNPACK_LOWPS:
6124 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6126 case OP_UNPACK_LOWPD:
6127 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6130 case OP_UNPACK_HIGHB:
6131 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6133 case OP_UNPACK_HIGHW:
6134 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6136 case OP_UNPACK_HIGHD:
6137 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6139 case OP_UNPACK_HIGHQ:
6140 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6142 case OP_UNPACK_HIGHPS:
6143 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6145 case OP_UNPACK_HIGHPD:
6146 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6150 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6153 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6156 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6159 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6162 case OP_PADDB_SAT_UN:
6163 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6165 case OP_PSUBB_SAT_UN:
6166 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6168 case OP_PADDW_SAT_UN:
6169 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6171 case OP_PSUBW_SAT_UN:
6172 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6176 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6179 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6182 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6185 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6189 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6192 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6195 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6197 case OP_PMULW_HIGH_UN:
6198 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6201 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6205 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6208 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6212 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6215 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6219 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6222 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6226 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6229 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6233 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6236 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6240 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6243 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6247 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6250 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6253 /*TODO: This is appart of the sse spec but not added
6255 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6258 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6263 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6266 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6269 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6272 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6275 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6278 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6281 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6284 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6287 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6290 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6294 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6297 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6301 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6302 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6304 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6309 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6311 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6312 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6316 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6318 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6319 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6320 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6324 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6326 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6329 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6331 case OP_EXTRACTX_U2:
6332 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6334 case OP_INSERTX_U1_SLOW:
6335 /*sreg1 is the extracted ireg (scratch)
6336 /sreg2 is the to be inserted ireg (scratch)
6337 /dreg is the xreg to receive the value*/
6339 /*clear the bits from the extracted word*/
6340 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6341 /*shift the value to insert if needed*/
6342 if (ins->inst_c0 & 1)
6343 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6344 /*join them together*/
6345 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6346 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6348 case OP_INSERTX_I4_SLOW:
6349 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6350 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6351 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6353 case OP_INSERTX_I8_SLOW:
6354 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6356 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6358 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6361 case OP_INSERTX_R4_SLOW:
6362 switch (ins->inst_c0) {
6365 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6367 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6370 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6372 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6374 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6375 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6378 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6380 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6382 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6383 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6386 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6388 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6390 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6391 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6395 case OP_INSERTX_R8_SLOW:
6397 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6399 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6401 case OP_STOREX_MEMBASE_REG:
6402 case OP_STOREX_MEMBASE:
6403 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6405 case OP_LOADX_MEMBASE:
6406 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6408 case OP_LOADX_ALIGNED_MEMBASE:
6409 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6411 case OP_STOREX_ALIGNED_MEMBASE_REG:
6412 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6414 case OP_STOREX_NTA_MEMBASE_REG:
6415 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6417 case OP_PREFETCH_MEMBASE:
6418 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6422 /*FIXME the peephole pass should have killed this*/
6423 if (ins->dreg != ins->sreg1)
6424 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6427 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6429 case OP_ICONV_TO_R4_RAW:
6430 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6433 case OP_FCONV_TO_R8_X:
6434 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6437 case OP_XCONV_R8_TO_I4:
6438 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6439 switch (ins->backend.source_opcode) {
6440 case OP_FCONV_TO_I1:
6441 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6443 case OP_FCONV_TO_U1:
6444 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6446 case OP_FCONV_TO_I2:
6447 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6449 case OP_FCONV_TO_U2:
6450 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6456 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6457 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6458 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6461 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6462 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6465 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6466 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6470 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6472 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6473 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6475 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6478 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6479 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6482 case OP_LIVERANGE_START: {
6483 if (cfg->verbose_level > 1)
6484 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6485 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6488 case OP_LIVERANGE_END: {
6489 if (cfg->verbose_level > 1)
6490 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6491 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6494 case OP_GC_SAFE_POINT: {
6495 const char *polling_func = NULL;
6496 int compare_val = 0;
6499 #if defined (USE_COOP_GC)
6500 polling_func = "mono_threads_state_poll";
6502 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6503 polling_func = "mono_nacl_gc";
6504 compare_val = 0xFFFFFFFF;
6509 amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6510 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6511 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6512 amd64_patch (br[0], code);
6516 case OP_GC_LIVENESS_DEF:
6517 case OP_GC_LIVENESS_USE:
6518 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6519 ins->backend.pc_offset = code - cfg->native_code;
6521 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6522 ins->backend.pc_offset = code - cfg->native_code;
6523 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6526 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6527 g_assert_not_reached ();
6530 if ((code - cfg->native_code - offset) > max_len) {
6531 #if !defined(__native_client_codegen__)
6532 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6533 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6534 g_assert_not_reached ();
6539 cfg->code_len = code - cfg->native_code;
6542 #endif /* DISABLE_JIT */
6545 mono_arch_register_lowlevel_calls (void)
6547 /* The signature doesn't matter */
6548 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6552 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6554 unsigned char *ip = ji->ip.i + code;
6557 * Debug code to help track down problems where the target of a near call is
6560 if (amd64_is_near_call (ip)) {
6561 gint64 disp = (guint8*)target - (guint8*)ip;
6563 if (!amd64_is_imm32 (disp)) {
6564 printf ("TYPE: %d\n", ji->type);
6566 case MONO_PATCH_INFO_INTERNAL_METHOD:
6567 printf ("V: %s\n", ji->data.name);
6569 case MONO_PATCH_INFO_METHOD_JUMP:
6570 case MONO_PATCH_INFO_METHOD:
6571 printf ("V: %s\n", ji->data.method->name);
6579 amd64_patch (ip, (gpointer)target);
6585 get_max_epilog_size (MonoCompile *cfg)
6587 int max_epilog_size = 16;
6589 if (cfg->method->save_lmf)
6590 max_epilog_size += 256;
6592 if (mono_jit_trace_calls != NULL)
6593 max_epilog_size += 50;
6595 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6596 max_epilog_size += 50;
6598 max_epilog_size += (AMD64_NREG * 2);
6600 return max_epilog_size;
6604 * This macro is used for testing whenever the unwinder works correctly at every point
6605 * where an async exception can happen.
6607 /* This will generate a SIGSEGV at the given point in the code */
6608 #define async_exc_point(code) do { \
6609 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6610 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6611 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6612 cfg->arch.async_point_count ++; \
6617 mono_arch_emit_prolog (MonoCompile *cfg)
6619 MonoMethod *method = cfg->method;
6621 MonoMethodSignature *sig;
6623 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6626 MonoInst *lmf_var = cfg->lmf_var;
6627 gboolean args_clobbered = FALSE;
6628 gboolean trace = FALSE;
6629 #ifdef __native_client_codegen__
6630 guint alignment_check;
6633 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6635 #if defined(__default_codegen__)
6636 code = cfg->native_code = g_malloc (cfg->code_size);
6637 #elif defined(__native_client_codegen__)
6638 /* native_code_alloc is not 32-byte aligned, native_code is. */
6639 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6641 /* Align native_code to next nearest kNaclAlignment byte. */
6642 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6643 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6645 code = cfg->native_code;
6647 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6648 g_assert (alignment_check == 0);
6651 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6654 /* Amount of stack space allocated by register saving code */
6657 /* Offset between RSP and the CFA */
6661 * The prolog consists of the following parts:
6663 * - push rbp, mov rbp, rsp
6664 * - save callee saved regs using pushes
6666 * - save rgctx if needed
6667 * - save lmf if needed
6670 * - save rgctx if needed
6671 * - save lmf if needed
6672 * - save callee saved regs using moves
6677 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6678 // IP saved at CFA - 8
6679 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6680 async_exc_point (code);
6681 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6683 if (!cfg->arch.omit_fp) {
6684 amd64_push_reg (code, AMD64_RBP);
6686 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6687 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6688 async_exc_point (code);
6690 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6692 /* These are handled automatically by the stack marking code */
6693 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6695 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6696 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6697 async_exc_point (code);
6699 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6703 /* The param area is always at offset 0 from sp */
6704 /* This needs to be allocated here, since it has to come after the spill area */
6705 if (cfg->param_area) {
6706 if (cfg->arch.omit_fp)
6708 g_assert_not_reached ();
6709 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6712 if (cfg->arch.omit_fp) {
6714 * On enter, the stack is misaligned by the pushing of the return
6715 * address. It is either made aligned by the pushing of %rbp, or by
6718 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6719 if ((alloc_size % 16) == 0) {
6721 /* Mark the padding slot as NOREF */
6722 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6725 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6726 if (cfg->stack_offset != alloc_size) {
6727 /* Mark the padding slot as NOREF */
6728 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6730 cfg->arch.sp_fp_offset = alloc_size;
6734 cfg->arch.stack_alloc_size = alloc_size;
6736 /* Allocate stack frame */
6738 /* See mono_emit_stack_alloc */
6739 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6740 guint32 remaining_size = alloc_size;
6741 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6742 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6743 guint32 offset = code - cfg->native_code;
6744 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6745 while (required_code_size >= (cfg->code_size - offset))
6746 cfg->code_size *= 2;
6747 cfg->native_code = mono_realloc_native_code (cfg);
6748 code = cfg->native_code + offset;
6749 cfg->stat_code_reallocs++;
6752 while (remaining_size >= 0x1000) {
6753 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6754 if (cfg->arch.omit_fp) {
6755 cfa_offset += 0x1000;
6756 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6758 async_exc_point (code);
6760 if (cfg->arch.omit_fp)
6761 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6764 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6765 remaining_size -= 0x1000;
6767 if (remaining_size) {
6768 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6769 if (cfg->arch.omit_fp) {
6770 cfa_offset += remaining_size;
6771 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6772 async_exc_point (code);
6775 if (cfg->arch.omit_fp)
6776 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6780 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6781 if (cfg->arch.omit_fp) {
6782 cfa_offset += alloc_size;
6783 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6784 async_exc_point (code);
6789 /* Stack alignment check */
6792 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6793 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6794 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6795 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6796 amd64_breakpoint (code);
6800 if (mini_get_debug_options ()->init_stacks) {
6801 /* Fill the stack frame with a dummy value to force deterministic behavior */
6803 /* Save registers to the red zone */
6804 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6805 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6807 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6808 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6809 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6812 #if defined(__default_codegen__)
6813 amd64_prefix (code, X86_REP_PREFIX);
6815 #elif defined(__native_client_codegen__)
6816 /* NaCl stos pseudo-instruction */
6817 amd64_codegen_pre (code);
6818 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6819 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6820 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6821 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6822 amd64_prefix (code, X86_REP_PREFIX);
6824 amd64_codegen_post (code);
6825 #endif /* __native_client_codegen__ */
6827 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6828 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6832 if (method->save_lmf)
6833 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6835 /* Save callee saved registers */
6836 if (cfg->arch.omit_fp) {
6837 save_area_offset = cfg->arch.reg_save_area_offset;
6838 /* Save caller saved registers after sp is adjusted */
6839 /* The registers are saved at the bottom of the frame */
6840 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6842 /* The registers are saved just below the saved rbp */
6843 save_area_offset = cfg->arch.reg_save_area_offset;
6846 for (i = 0; i < AMD64_NREG; ++i) {
6847 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6848 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6850 if (cfg->arch.omit_fp) {
6851 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6852 /* These are handled automatically by the stack marking code */
6853 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6855 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6859 save_area_offset += 8;
6860 async_exc_point (code);
6864 /* store runtime generic context */
6865 if (cfg->rgctx_var) {
6866 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6867 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6869 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6871 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6872 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6875 /* compute max_length in order to use short forward jumps */
6876 max_epilog_size = get_max_epilog_size (cfg);
6877 if (cfg->opt & MONO_OPT_BRANCH) {
6878 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6882 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6884 /* max alignment for loops */
6885 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6886 max_length += LOOP_ALIGNMENT;
6887 #ifdef __native_client_codegen__
6888 /* max alignment for native client */
6889 max_length += kNaClAlignment;
6892 MONO_BB_FOR_EACH_INS (bb, ins) {
6893 #ifdef __native_client_codegen__
6895 int space_in_block = kNaClAlignment -
6896 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6897 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6898 if (space_in_block < max_len && max_len < kNaClAlignment) {
6899 max_length += space_in_block;
6902 #endif /*__native_client_codegen__*/
6903 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6906 /* Take prolog and epilog instrumentation into account */
6907 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6908 max_length += max_epilog_size;
6910 bb->max_length = max_length;
6914 sig = mono_method_signature (method);
6917 cinfo = cfg->arch.cinfo;
6919 if (sig->ret->type != MONO_TYPE_VOID) {
6920 /* Save volatile arguments to the stack */
6921 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6922 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6925 /* Keep this in sync with emit_load_volatile_arguments */
6926 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6927 ArgInfo *ainfo = cinfo->args + i;
6929 ins = cfg->args [i];
6931 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6932 /* Unused arguments */
6935 /* Save volatile arguments to the stack */
6936 if (ins->opcode != OP_REGVAR) {
6937 switch (ainfo->storage) {
6943 if (stack_offset & 0x1)
6945 else if (stack_offset & 0x2)
6947 else if (stack_offset & 0x4)
6952 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6955 * Save the original location of 'this',
6956 * get_generic_info_from_stack_frame () needs this to properly look up
6957 * the argument value during the handling of async exceptions.
6959 if (ins == cfg->args [0]) {
6960 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6961 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6965 case ArgInFloatSSEReg:
6966 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6968 case ArgInDoubleSSEReg:
6969 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6971 case ArgValuetypeInReg:
6972 for (quad = 0; quad < 2; quad ++) {
6973 switch (ainfo->pair_storage [quad]) {
6975 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6977 case ArgInFloatSSEReg:
6978 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6980 case ArgInDoubleSSEReg:
6981 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6986 g_assert_not_reached ();
6990 case ArgValuetypeAddrInIReg:
6991 if (ainfo->pair_storage [0] == ArgInIReg)
6992 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6998 /* Argument allocated to (non-volatile) register */
6999 switch (ainfo->storage) {
7001 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7004 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7007 g_assert_not_reached ();
7010 if (ins == cfg->args [0]) {
7011 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7012 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7017 if (cfg->method->save_lmf)
7018 args_clobbered = TRUE;
7021 args_clobbered = TRUE;
7022 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7025 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7026 args_clobbered = TRUE;
7029 * Optimize the common case of the first bblock making a call with the same
7030 * arguments as the method. This works because the arguments are still in their
7031 * original argument registers.
7032 * FIXME: Generalize this
7034 if (!args_clobbered) {
7035 MonoBasicBlock *first_bb = cfg->bb_entry;
7037 int filter = FILTER_IL_SEQ_POINT;
7039 next = mono_bb_first_inst (first_bb, filter);
7040 if (!next && first_bb->next_bb) {
7041 first_bb = first_bb->next_bb;
7042 next = mono_bb_first_inst (first_bb, filter);
7045 if (first_bb->in_count > 1)
7048 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7049 ArgInfo *ainfo = cinfo->args + i;
7050 gboolean match = FALSE;
7052 ins = cfg->args [i];
7053 if (ins->opcode != OP_REGVAR) {
7054 switch (ainfo->storage) {
7056 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7057 if (next->dreg == ainfo->reg) {
7061 next->opcode = OP_MOVE;
7062 next->sreg1 = ainfo->reg;
7063 /* Only continue if the instruction doesn't change argument regs */
7064 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7074 /* Argument allocated to (non-volatile) register */
7075 switch (ainfo->storage) {
7077 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7088 next = mono_inst_next (next, filter);
7089 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7096 if (cfg->gen_sdb_seq_points) {
7097 MonoInst *info_var = cfg->arch.seq_point_info_var;
7099 /* Initialize seq_point_info_var */
7100 if (cfg->compile_aot) {
7101 /* Initialize the variable from a GOT slot */
7102 /* Same as OP_AOTCONST */
7103 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7104 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7105 g_assert (info_var->opcode == OP_REGOFFSET);
7106 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7109 if (cfg->compile_aot) {
7110 /* Initialize ss_tramp_var */
7111 ins = cfg->arch.ss_tramp_var;
7112 g_assert (ins->opcode == OP_REGOFFSET);
7114 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7115 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7116 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7118 /* Initialize ss_trigger_page_var */
7119 ins = cfg->arch.ss_trigger_page_var;
7121 g_assert (ins->opcode == OP_REGOFFSET);
7123 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7124 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7128 cfg->code_len = code - cfg->native_code;
7130 g_assert (cfg->code_len < cfg->code_size);
7136 mono_arch_emit_epilog (MonoCompile *cfg)
7138 MonoMethod *method = cfg->method;
7141 int max_epilog_size;
7143 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7144 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7146 max_epilog_size = get_max_epilog_size (cfg);
7148 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7149 cfg->code_size *= 2;
7150 cfg->native_code = mono_realloc_native_code (cfg);
7151 cfg->stat_code_reallocs++;
7153 code = cfg->native_code + cfg->code_len;
7155 cfg->has_unwind_info_for_epilog = TRUE;
7157 /* Mark the start of the epilog */
7158 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7160 /* Save the uwind state which is needed by the out-of-line code */
7161 mono_emit_unwind_op_remember_state (cfg, code);
7163 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7164 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7166 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7168 if (method->save_lmf) {
7169 /* check if we need to restore protection of the stack after a stack overflow */
7170 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7172 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7173 /* we load the value in a separate instruction: this mechanism may be
7174 * used later as a safer way to do thread interruption
7176 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7177 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7179 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7180 /* note that the call trampoline will preserve eax/edx */
7181 x86_call_reg (code, X86_ECX);
7182 x86_patch (patch, code);
7184 /* FIXME: maybe save the jit tls in the prolog */
7186 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7187 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7191 /* Restore callee saved regs */
7192 for (i = 0; i < AMD64_NREG; ++i) {
7193 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7194 /* Restore only used_int_regs, not arch.saved_iregs */
7195 if (cfg->used_int_regs & (1 << i)) {
7196 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7197 mono_emit_unwind_op_same_value (cfg, code, i);
7198 async_exc_point (code);
7200 save_area_offset += 8;
7204 /* Load returned vtypes into registers if needed */
7205 cinfo = cfg->arch.cinfo;
7206 if (cinfo->ret.storage == ArgValuetypeInReg) {
7207 ArgInfo *ainfo = &cinfo->ret;
7208 MonoInst *inst = cfg->ret;
7210 for (quad = 0; quad < 2; quad ++) {
7211 switch (ainfo->pair_storage [quad]) {
7213 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7215 case ArgInFloatSSEReg:
7216 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7218 case ArgInDoubleSSEReg:
7219 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7224 g_assert_not_reached ();
7229 if (cfg->arch.omit_fp) {
7230 if (cfg->arch.stack_alloc_size) {
7231 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7235 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7237 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7238 async_exc_point (code);
7241 /* Restore the unwind state to be the same as before the epilog */
7242 mono_emit_unwind_op_restore_state (cfg, code);
7244 cfg->code_len = code - cfg->native_code;
7246 g_assert (cfg->code_len < cfg->code_size);
7250 mono_arch_emit_exceptions (MonoCompile *cfg)
7252 MonoJumpInfo *patch_info;
7255 MonoClass *exc_classes [16];
7256 guint8 *exc_throw_start [16], *exc_throw_end [16];
7257 guint32 code_size = 0;
7259 /* Compute needed space */
7260 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7261 if (patch_info->type == MONO_PATCH_INFO_EXC)
7263 if (patch_info->type == MONO_PATCH_INFO_R8)
7264 code_size += 8 + 15; /* sizeof (double) + alignment */
7265 if (patch_info->type == MONO_PATCH_INFO_R4)
7266 code_size += 4 + 15; /* sizeof (float) + alignment */
7267 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7268 code_size += 8 + 7; /*sizeof (void*) + alignment */
7271 #ifdef __native_client_codegen__
7272 /* Give us extra room on Native Client. This could be */
7273 /* more carefully calculated, but bundle alignment makes */
7274 /* it much trickier, so *2 like other places is good. */
7278 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7279 cfg->code_size *= 2;
7280 cfg->native_code = mono_realloc_native_code (cfg);
7281 cfg->stat_code_reallocs++;
7284 code = cfg->native_code + cfg->code_len;
7286 /* add code to raise exceptions */
7288 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7289 switch (patch_info->type) {
7290 case MONO_PATCH_INFO_EXC: {
7291 MonoClass *exc_class;
7295 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7297 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7298 g_assert (exc_class);
7299 throw_ip = patch_info->ip.i;
7301 //x86_breakpoint (code);
7302 /* Find a throw sequence for the same exception class */
7303 for (i = 0; i < nthrows; ++i)
7304 if (exc_classes [i] == exc_class)
7307 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7308 x86_jump_code (code, exc_throw_start [i]);
7309 patch_info->type = MONO_PATCH_INFO_NONE;
7313 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7317 exc_classes [nthrows] = exc_class;
7318 exc_throw_start [nthrows] = code;
7320 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7322 patch_info->type = MONO_PATCH_INFO_NONE;
7324 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7326 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7331 exc_throw_end [nthrows] = code;
7341 g_assert(code < cfg->native_code + cfg->code_size);
7344 /* Handle relocations with RIP relative addressing */
7345 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7346 gboolean remove = FALSE;
7347 guint8 *orig_code = code;
7349 switch (patch_info->type) {
7350 case MONO_PATCH_INFO_R8:
7351 case MONO_PATCH_INFO_R4: {
7352 guint8 *pos, *patch_pos;
7355 /* The SSE opcodes require a 16 byte alignment */
7356 #if defined(__default_codegen__)
7357 code = (guint8*)ALIGN_TO (code, 16);
7358 #elif defined(__native_client_codegen__)
7360 /* Pad this out with HLT instructions */
7361 /* or we can get garbage bytes emitted */
7362 /* which will fail validation */
7363 guint8 *aligned_code;
7364 /* extra align to make room for */
7365 /* mov/push below */
7366 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7367 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7368 /* The technique of hiding data in an */
7369 /* instruction has a problem here: we */
7370 /* need the data aligned to a 16-byte */
7371 /* boundary but the instruction cannot */
7372 /* cross the bundle boundary. so only */
7373 /* odd multiples of 16 can be used */
7374 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7377 while (code < aligned_code) {
7378 *(code++) = 0xf4; /* hlt */
7383 pos = cfg->native_code + patch_info->ip.i;
7384 if (IS_REX (pos [1])) {
7385 patch_pos = pos + 5;
7386 target_pos = code - pos - 9;
7389 patch_pos = pos + 4;
7390 target_pos = code - pos - 8;
7393 if (patch_info->type == MONO_PATCH_INFO_R8) {
7394 #ifdef __native_client_codegen__
7395 /* Hide 64-bit data in a */
7396 /* "mov imm64, r11" instruction. */
7397 /* write it before the start of */
7399 *(code-2) = 0x49; /* prefix */
7400 *(code-1) = 0xbb; /* mov X, %r11 */
7402 *(double*)code = *(double*)patch_info->data.target;
7403 code += sizeof (double);
7405 #ifdef __native_client_codegen__
7406 /* Hide 32-bit data in a */
7407 /* "push imm32" instruction. */
7408 *(code-1) = 0x68; /* push */
7410 *(float*)code = *(float*)patch_info->data.target;
7411 code += sizeof (float);
7414 *(guint32*)(patch_pos) = target_pos;
7419 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7422 if (cfg->compile_aot)
7425 /*loading is faster against aligned addresses.*/
7426 code = (guint8*)ALIGN_TO (code, 8);
7427 memset (orig_code, 0, code - orig_code);
7429 pos = cfg->native_code + patch_info->ip.i;
7431 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7432 if (IS_REX (pos [1]))
7433 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7435 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7437 *(gpointer*)code = (gpointer)patch_info->data.target;
7438 code += sizeof (gpointer);
7448 if (patch_info == cfg->patch_info)
7449 cfg->patch_info = patch_info->next;
7453 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7455 tmp->next = patch_info->next;
7458 g_assert (code < cfg->native_code + cfg->code_size);
7461 cfg->code_len = code - cfg->native_code;
7463 g_assert (cfg->code_len < cfg->code_size);
7467 #endif /* DISABLE_JIT */
7470 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7473 MonoMethodSignature *sig;
7475 int i, n, stack_area = 0;
7477 /* Keep this in sync with mono_arch_get_argument_info */
7479 if (enable_arguments) {
7480 /* Allocate a new area on the stack and save arguments there */
7481 sig = mono_method_signature (cfg->method);
7483 n = sig->param_count + sig->hasthis;
7485 stack_area = ALIGN_TO (n * 8, 16);
7487 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7489 for (i = 0; i < n; ++i) {
7490 inst = cfg->args [i];
7492 if (inst->opcode == OP_REGVAR)
7493 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7495 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7496 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7501 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7502 amd64_set_reg_template (code, AMD64_ARG_REG1);
7503 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7504 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7506 if (enable_arguments)
7507 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7521 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7524 int save_mode = SAVE_NONE;
7525 MonoMethod *method = cfg->method;
7526 MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7529 switch (ret_type->type) {
7530 case MONO_TYPE_VOID:
7531 /* special case string .ctor icall */
7532 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7533 save_mode = SAVE_EAX;
7535 save_mode = SAVE_NONE;
7539 save_mode = SAVE_EAX;
7543 save_mode = SAVE_XMM;
7545 case MONO_TYPE_GENERICINST:
7546 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7547 save_mode = SAVE_EAX;
7551 case MONO_TYPE_VALUETYPE:
7552 save_mode = SAVE_STRUCT;
7555 save_mode = SAVE_EAX;
7559 /* Save the result and copy it into the proper argument register */
7560 switch (save_mode) {
7562 amd64_push_reg (code, AMD64_RAX);
7564 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7565 if (enable_arguments)
7566 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7570 if (enable_arguments)
7571 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7574 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7575 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7577 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7579 * The result is already in the proper argument register so no copying
7586 g_assert_not_reached ();
7589 /* Set %al since this is a varargs call */
7590 if (save_mode == SAVE_XMM)
7591 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7593 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7595 if (preserve_argument_registers) {
7596 for (i = 0; i < PARAM_REGS; ++i)
7597 amd64_push_reg (code, param_regs [i]);
7600 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7601 amd64_set_reg_template (code, AMD64_ARG_REG1);
7602 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7604 if (preserve_argument_registers) {
7605 for (i = PARAM_REGS - 1; i >= 0; --i)
7606 amd64_pop_reg (code, param_regs [i]);
7609 /* Restore result */
7610 switch (save_mode) {
7612 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7613 amd64_pop_reg (code, AMD64_RAX);
7619 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7620 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7621 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7626 g_assert_not_reached ();
7633 mono_arch_flush_icache (guint8 *code, gint size)
7639 mono_arch_flush_register_windows (void)
7644 mono_arch_is_inst_imm (gint64 imm)
7646 return amd64_is_imm32 (imm);
7650 * Determine whenever the trap whose info is in SIGINFO is caused by
7654 mono_arch_is_int_overflow (void *sigctx, void *info)
7661 mono_sigctx_to_monoctx (sigctx, &ctx);
7663 rip = (guint8*)ctx.rip;
7665 if (IS_REX (rip [0])) {
7666 reg = amd64_rex_b (rip [0]);
7672 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7674 reg += x86_modrm_rm (rip [1]);
7714 g_assert_not_reached ();
7726 mono_arch_get_patch_offset (guint8 *code)
7732 * mono_breakpoint_clean_code:
7734 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7735 * breakpoints in the original code, they are removed in the copy.
7737 * Returns TRUE if no sw breakpoint was present.
7740 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7743 * If method_start is non-NULL we need to perform bound checks, since we access memory
7744 * at code - offset we could go before the start of the method and end up in a different
7745 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7748 if (!method_start || code - offset >= method_start) {
7749 memcpy (buf, code - offset, size);
7751 int diff = code - method_start;
7752 memset (buf, 0, size);
7753 memcpy (buf + offset - diff, method_start, diff + size - offset);
7758 #if defined(__native_client_codegen__)
7759 /* For membase calls, we want the base register. for Native Client, */
7760 /* all indirect calls have the following sequence with the given sizes: */
7761 /* mov %eXX,%eXX [2-3] */
7762 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7763 /* and $0xffffffffffffffe0,%r11d [4] */
7764 /* add %r15,%r11 [3] */
7765 /* callq *%r11 [3] */
7768 /* Determine if code points to a NaCl call-through-register sequence, */
7769 /* (i.e., the last 3 instructions listed above) */
7771 is_nacl_call_reg_sequence(guint8* code)
7773 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7774 "\x4d\x03\xdf" /* add */
7775 "\x41\xff\xd3"; /* call */
7776 return memcmp(code, sequence, 10) == 0;
7779 /* Determine if code points to the first opcode of the mov membase component */
7780 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7781 /* (there could be a REX prefix before the opcode but it is ignored) */
7783 is_nacl_indirect_call_membase_sequence(guint8* code)
7785 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7786 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7787 /* and that src reg = dest reg */
7788 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7789 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7791 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7792 /* and has dst of r11 and base of r15 */
7793 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7794 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7796 #endif /* __native_client_codegen__ */
7799 mono_arch_get_this_arg_reg (guint8 *code)
7801 return AMD64_ARG_REG1;
7805 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7807 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7810 #define MAX_ARCH_DELEGATE_PARAMS 10
7813 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7815 guint8 *code, *start;
7819 start = code = mono_global_codeman_reserve (64);
7821 /* Replace the this argument with the target */
7822 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7823 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7824 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7826 g_assert ((code - start) < 64);
7828 start = code = mono_global_codeman_reserve (64);
7830 if (param_count == 0) {
7831 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7833 /* We have to shift the arguments left */
7834 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7835 for (i = 0; i < param_count; ++i) {
7838 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7840 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7842 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7846 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7848 g_assert ((code - start) < 64);
7851 nacl_global_codeman_validate (&start, 64, &code);
7852 mono_arch_flush_icache (start, code - start);
7855 *code_len = code - start;
7857 if (mono_jit_map_is_enabled ()) {
7860 buff = (char*)"delegate_invoke_has_target";
7862 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7863 mono_emit_jit_tramp (start, code - start, buff);
7867 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7873 * mono_arch_get_delegate_invoke_impls:
7875 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7879 mono_arch_get_delegate_invoke_impls (void)
7887 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7888 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7890 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7891 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7892 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7893 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7894 g_free (tramp_name);
7901 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7903 guint8 *code, *start;
7906 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7909 /* FIXME: Support more cases */
7910 if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7914 static guint8* cached = NULL;
7920 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7922 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7924 mono_memory_barrier ();
7928 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7929 for (i = 0; i < sig->param_count; ++i)
7930 if (!mono_is_regsize_var (sig->params [i]))
7932 if (sig->param_count > 4)
7935 code = cache [sig->param_count];
7939 if (mono_aot_only) {
7940 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7941 start = mono_aot_get_trampoline (name);
7944 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7947 mono_memory_barrier ();
7949 cache [sig->param_count] = start;
7956 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7958 guint8 *code, *start;
7961 start = code = mono_global_codeman_reserve (size);
7963 /* Replace the this argument with the target */
7964 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7965 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7968 /* Load the IMT reg */
7969 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7972 /* Load the vtable */
7973 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7974 amd64_jump_membase (code, AMD64_RAX, offset);
7975 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7981 mono_arch_finish_init (void)
7983 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7984 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7989 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7993 #if defined(__default_codegen__)
7994 #define CMP_SIZE (6 + 1)
7995 #define CMP_REG_REG_SIZE (4 + 1)
7996 #define BR_SMALL_SIZE 2
7997 #define BR_LARGE_SIZE 6
7998 #define MOV_REG_IMM_SIZE 10
7999 #define MOV_REG_IMM_32BIT_SIZE 6
8000 #define JUMP_REG_SIZE (2 + 1)
8001 #elif defined(__native_client_codegen__)
8002 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8003 #define CMP_SIZE ((6 + 1) * 2 - 1)
8004 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8005 #define BR_SMALL_SIZE (2 * 2 - 1)
8006 #define BR_LARGE_SIZE (6 * 2 - 1)
8007 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8008 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8009 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8010 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8011 /* Jump membase's size is large and unpredictable */
8012 /* in native client, just pad it out a whole bundle. */
8013 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8017 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8019 int i, distance = 0;
8020 for (i = start; i < target; ++i)
8021 distance += imt_entries [i]->chunk_size;
8026 * LOCKING: called with the domain lock held
8029 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8030 gpointer fail_tramp)
8034 guint8 *code, *start;
8035 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8037 for (i = 0; i < count; ++i) {
8038 MonoIMTCheckItem *item = imt_entries [i];
8039 if (item->is_equals) {
8040 if (item->check_target_idx) {
8041 if (!item->compare_done) {
8042 if (amd64_is_imm32 (item->key))
8043 item->chunk_size += CMP_SIZE;
8045 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8047 if (item->has_target_code) {
8048 item->chunk_size += MOV_REG_IMM_SIZE;
8050 if (vtable_is_32bit)
8051 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8053 item->chunk_size += MOV_REG_IMM_SIZE;
8054 #ifdef __native_client_codegen__
8055 item->chunk_size += JUMP_MEMBASE_SIZE;
8058 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8061 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8062 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8064 if (vtable_is_32bit)
8065 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8067 item->chunk_size += MOV_REG_IMM_SIZE;
8068 item->chunk_size += JUMP_REG_SIZE;
8069 /* with assert below:
8070 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8072 #ifdef __native_client_codegen__
8073 item->chunk_size += JUMP_MEMBASE_SIZE;
8078 if (amd64_is_imm32 (item->key))
8079 item->chunk_size += CMP_SIZE;
8081 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8082 item->chunk_size += BR_LARGE_SIZE;
8083 imt_entries [item->check_target_idx]->compare_done = TRUE;
8085 size += item->chunk_size;
8087 #if defined(__native_client__) && defined(__native_client_codegen__)
8088 /* In Native Client, we don't re-use thunks, allocate from the */
8089 /* normal code manager paths. */
8090 code = mono_domain_code_reserve (domain, size);
8093 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8095 code = mono_domain_code_reserve (domain, size);
8098 for (i = 0; i < count; ++i) {
8099 MonoIMTCheckItem *item = imt_entries [i];
8100 item->code_target = code;
8101 if (item->is_equals) {
8102 gboolean fail_case = !item->check_target_idx && fail_tramp;
8104 if (item->check_target_idx || fail_case) {
8105 if (!item->compare_done || fail_case) {
8106 if (amd64_is_imm32 (item->key))
8107 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8109 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8110 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8113 item->jmp_code = code;
8114 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8115 if (item->has_target_code) {
8116 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8117 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8119 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8120 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8124 amd64_patch (item->jmp_code, code);
8125 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8126 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8127 item->jmp_code = NULL;
8130 /* enable the commented code to assert on wrong method */
8132 if (amd64_is_imm32 (item->key))
8133 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8135 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8136 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8138 item->jmp_code = code;
8139 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8140 /* See the comment below about R10 */
8141 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8142 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8143 amd64_patch (item->jmp_code, code);
8144 amd64_breakpoint (code);
8145 item->jmp_code = NULL;
8147 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8148 needs to be preserved. R10 needs
8149 to be preserved for calls which
8150 require a runtime generic context,
8151 but interface calls don't. */
8152 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8153 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8157 if (amd64_is_imm32 (item->key))
8158 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8160 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8161 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8163 item->jmp_code = code;
8164 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8165 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8167 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8169 g_assert (code - item->code_target <= item->chunk_size);
8171 /* patch the branches to get to the target items */
8172 for (i = 0; i < count; ++i) {
8173 MonoIMTCheckItem *item = imt_entries [i];
8174 if (item->jmp_code) {
8175 if (item->check_target_idx) {
8176 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8182 mono_stats.imt_thunks_size += code - start;
8183 g_assert (code - start <= size);
8185 nacl_domain_code_validate(domain, &start, size, &code);
8186 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8192 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8194 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8198 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8200 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8204 mono_arch_get_cie_program (void)
8208 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8209 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8217 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8219 MonoInst *ins = NULL;
8222 if (cmethod->klass == mono_defaults.math_class) {
8223 if (strcmp (cmethod->name, "Sin") == 0) {
8225 } else if (strcmp (cmethod->name, "Cos") == 0) {
8227 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8229 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8233 if (opcode && fsig->param_count == 1) {
8234 MONO_INST_NEW (cfg, ins, opcode);
8235 ins->type = STACK_R8;
8236 ins->dreg = mono_alloc_freg (cfg);
8237 ins->sreg1 = args [0]->dreg;
8238 MONO_ADD_INS (cfg->cbb, ins);
8242 if (cfg->opt & MONO_OPT_CMOV) {
8243 if (strcmp (cmethod->name, "Min") == 0) {
8244 if (fsig->params [0]->type == MONO_TYPE_I4)
8246 if (fsig->params [0]->type == MONO_TYPE_U4)
8247 opcode = OP_IMIN_UN;
8248 else if (fsig->params [0]->type == MONO_TYPE_I8)
8250 else if (fsig->params [0]->type == MONO_TYPE_U8)
8251 opcode = OP_LMIN_UN;
8252 } else if (strcmp (cmethod->name, "Max") == 0) {
8253 if (fsig->params [0]->type == MONO_TYPE_I4)
8255 if (fsig->params [0]->type == MONO_TYPE_U4)
8256 opcode = OP_IMAX_UN;
8257 else if (fsig->params [0]->type == MONO_TYPE_I8)
8259 else if (fsig->params [0]->type == MONO_TYPE_U8)
8260 opcode = OP_LMAX_UN;
8264 if (opcode && fsig->param_count == 2) {
8265 MONO_INST_NEW (cfg, ins, opcode);
8266 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8267 ins->dreg = mono_alloc_ireg (cfg);
8268 ins->sreg1 = args [0]->dreg;
8269 ins->sreg2 = args [1]->dreg;
8270 MONO_ADD_INS (cfg->cbb, ins);
8274 /* OP_FREM is not IEEE compatible */
8275 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8276 MONO_INST_NEW (cfg, ins, OP_FREM);
8277 ins->inst_i0 = args [0];
8278 ins->inst_i1 = args [1];
8288 mono_arch_print_tree (MonoInst *tree, int arity)
8293 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8296 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8299 case AMD64_RCX: return ctx->rcx;
8300 case AMD64_RDX: return ctx->rdx;
8301 case AMD64_RBX: return ctx->rbx;
8302 case AMD64_RBP: return ctx->rbp;
8303 case AMD64_RSP: return ctx->rsp;
8305 return _CTX_REG (ctx, rax, reg);
8310 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8329 _CTX_REG (ctx, rax, reg) = val;
8334 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8336 gpointer *sp, old_value;
8340 bp = MONO_CONTEXT_GET_BP (ctx);
8341 sp = *(gpointer*)(bp + clause->exvar_offset);
8344 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8353 * mono_arch_emit_load_aotconst:
8355 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8356 * TARGET from the mscorlib GOT in full-aot code.
8357 * On AMD64, the result is placed into R11.
8360 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8362 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8363 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8369 * mono_arch_get_trampolines:
8371 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8375 mono_arch_get_trampolines (gboolean aot)
8377 return mono_amd64_get_exception_trampolines (aot);
8380 /* Soft Debug support */
8381 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8384 * mono_arch_set_breakpoint:
8386 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8387 * The location should contain code emitted by OP_SEQ_POINT.
8390 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8393 guint8 *orig_code = code;
8396 guint32 native_offset = ip - (guint8*)ji->code_start;
8397 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8399 g_assert (info->bp_addrs [native_offset] == 0);
8400 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8403 * In production, we will use int3 (has to fix the size in the md
8404 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8407 g_assert (code [0] == 0x90);
8408 if (breakpoint_size == 8) {
8409 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8411 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8412 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8415 g_assert (code - orig_code == breakpoint_size);
8420 * mono_arch_clear_breakpoint:
8422 * Clear the breakpoint at IP.
8425 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8431 guint32 native_offset = ip - (guint8*)ji->code_start;
8432 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8434 info->bp_addrs [native_offset] = NULL;
8436 for (i = 0; i < breakpoint_size; ++i)
8442 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8445 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8446 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8451 siginfo_t* sinfo = (siginfo_t*) info;
8452 /* Sometimes the address is off by 4 */
8453 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8461 * mono_arch_skip_breakpoint:
8463 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8464 * we resume, the instruction is not executed again.
8467 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8470 /* The breakpoint instruction is a call */
8472 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8477 * mono_arch_start_single_stepping:
8479 * Start single stepping.
8482 mono_arch_start_single_stepping (void)
8484 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8485 ss_trampoline = mini_get_single_step_trampoline ();
8489 * mono_arch_stop_single_stepping:
8491 * Stop single stepping.
8494 mono_arch_stop_single_stepping (void)
8496 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8497 ss_trampoline = NULL;
8501 * mono_arch_is_single_step_event:
8503 * Return whenever the machine state in SIGCTX corresponds to a single
8507 mono_arch_is_single_step_event (void *info, void *sigctx)
8510 EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8511 if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8516 siginfo_t* sinfo = (siginfo_t*) info;
8517 /* Sometimes the address is off by 4 */
8518 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8526 * mono_arch_skip_single_step:
8528 * Modify CTX so the ip is placed after the single step trigger instruction,
8529 * we resume, the instruction is not executed again.
8532 mono_arch_skip_single_step (MonoContext *ctx)
8534 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8538 * mono_arch_create_seq_point_info:
8540 * Return a pointer to a data structure which is used by the sequence
8541 * point implementation in AOTed code.
8544 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8549 // FIXME: Add a free function
8551 mono_domain_lock (domain);
8552 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8554 mono_domain_unlock (domain);
8557 ji = mono_jit_info_table_find (domain, (char*)code);
8560 // FIXME: Optimize the size
8561 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8563 info->ss_tramp_addr = &ss_trampoline;
8565 mono_domain_lock (domain);
8566 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8568 mono_domain_unlock (domain);
8575 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8577 ext->lmf.previous_lmf = prev_lmf;
8578 /* Mark that this is a MonoLMFExt */
8579 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8580 ext->lmf.rsp = (gssize)ext;
8586 mono_arch_opcode_supported (int opcode)
8589 case OP_ATOMIC_ADD_I4:
8590 case OP_ATOMIC_ADD_I8:
8591 case OP_ATOMIC_EXCHANGE_I4:
8592 case OP_ATOMIC_EXCHANGE_I8:
8593 case OP_ATOMIC_CAS_I4:
8594 case OP_ATOMIC_CAS_I8:
8595 case OP_ATOMIC_LOAD_I1:
8596 case OP_ATOMIC_LOAD_I2:
8597 case OP_ATOMIC_LOAD_I4:
8598 case OP_ATOMIC_LOAD_I8:
8599 case OP_ATOMIC_LOAD_U1:
8600 case OP_ATOMIC_LOAD_U2:
8601 case OP_ATOMIC_LOAD_U4:
8602 case OP_ATOMIC_LOAD_U8:
8603 case OP_ATOMIC_LOAD_R4:
8604 case OP_ATOMIC_LOAD_R8:
8605 case OP_ATOMIC_STORE_I1:
8606 case OP_ATOMIC_STORE_I2:
8607 case OP_ATOMIC_STORE_I4:
8608 case OP_ATOMIC_STORE_I8:
8609 case OP_ATOMIC_STORE_U1:
8610 case OP_ATOMIC_STORE_U2:
8611 case OP_ATOMIC_STORE_U4:
8612 case OP_ATOMIC_STORE_U8:
8613 case OP_ATOMIC_STORE_R4:
8614 case OP_ATOMIC_STORE_R8: