2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internal.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-tls.h>
33 #include <mono/utils/mono-hwcap-x86.h>
37 #include "mini-amd64.h"
38 #include "cpu-amd64.h"
39 #include "debugger-agent.h"
42 static gint lmf_tls_offset = -1;
43 static gint lmf_addr_tls_offset = -1;
44 static gint appdomain_tls_offset = -1;
47 static gboolean optimize_for_xen = TRUE;
49 #define optimize_for_xen 0
52 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
54 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
56 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
59 /* Under windows, the calling convention is never stdcall */
60 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
62 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
65 /* This mutex protects architecture specific caches */
66 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
67 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
68 static CRITICAL_SECTION mini_arch_mutex;
71 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
73 /* Structure used by the sequence points in AOTed code */
75 gpointer ss_trigger_page;
76 gpointer bp_trigger_page;
77 gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
81 * The code generated for sequence points reads from this location, which is
82 * made read-only when single stepping is enabled.
84 static gpointer ss_trigger_page;
86 /* Enabled breakpoints read from this trigger page */
87 static gpointer bp_trigger_page;
89 /* The size of the breakpoint sequence */
90 static int breakpoint_size;
92 /* The size of the breakpoint instruction causing the actual fault */
93 static int breakpoint_fault_size;
95 /* The size of the single step instruction causing the actual fault */
96 static int single_step_fault_size;
99 /* On Win64 always reserve first 32 bytes for first four arguments */
100 #define ARGS_OFFSET 48
102 #define ARGS_OFFSET 16
104 #define GP_SCRATCH_REG AMD64_R11
107 * AMD64 register usage:
108 * - callee saved registers are used for global register allocation
109 * - %r11 is used for materializing 64 bit constants in opcodes
110 * - the rest is used for local allocation
114 * Floating point comparison results:
124 mono_arch_regname (int reg)
127 case AMD64_RAX: return "%rax";
128 case AMD64_RBX: return "%rbx";
129 case AMD64_RCX: return "%rcx";
130 case AMD64_RDX: return "%rdx";
131 case AMD64_RSP: return "%rsp";
132 case AMD64_RBP: return "%rbp";
133 case AMD64_RDI: return "%rdi";
134 case AMD64_RSI: return "%rsi";
135 case AMD64_R8: return "%r8";
136 case AMD64_R9: return "%r9";
137 case AMD64_R10: return "%r10";
138 case AMD64_R11: return "%r11";
139 case AMD64_R12: return "%r12";
140 case AMD64_R13: return "%r13";
141 case AMD64_R14: return "%r14";
142 case AMD64_R15: return "%r15";
147 static const char * packed_xmmregs [] = {
148 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
149 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
152 static const char * single_xmmregs [] = {
153 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
154 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
158 mono_arch_fregname (int reg)
160 if (reg < AMD64_XMM_NREG)
161 return single_xmmregs [reg];
167 mono_arch_xregname (int reg)
169 if (reg < AMD64_XMM_NREG)
170 return packed_xmmregs [reg];
179 return mono_debug_count ();
185 static inline gboolean
186 amd64_is_near_call (guint8 *code)
189 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
192 return code [0] == 0xe8;
195 #ifdef __native_client_codegen__
197 /* Keep track of instruction "depth", that is, the level of sub-instruction */
198 /* for any given instruction. For instance, amd64_call_reg resolves to */
199 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
200 /* We only want to force bundle alignment for the top level instruction, */
201 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
202 static MonoNativeTlsKey nacl_instruction_depth;
204 static MonoNativeTlsKey nacl_rex_tag;
205 static MonoNativeTlsKey nacl_legacy_prefix_tag;
208 amd64_nacl_clear_legacy_prefix_tag ()
210 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
214 amd64_nacl_tag_legacy_prefix (guint8* code)
216 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
217 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
221 amd64_nacl_tag_rex (guint8* code)
223 mono_native_tls_set_value (nacl_rex_tag, code);
227 amd64_nacl_get_legacy_prefix_tag ()
229 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
233 amd64_nacl_get_rex_tag ()
235 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
238 /* Increment the instruction "depth" described above */
240 amd64_nacl_instruction_pre ()
242 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
244 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
247 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
248 /* alignment if depth == 0 (top level instruction) */
249 /* IN: start, end pointers to instruction beginning and end */
250 /* OUT: start, end pointers to beginning and end after possible alignment */
251 /* GLOBALS: nacl_instruction_depth defined above */
253 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
255 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
257 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
259 g_assert ( depth >= 0 );
261 uintptr_t space_in_block;
263 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
264 /* if legacy prefix is present, and if it was emitted before */
265 /* the start of the instruction sequence, adjust the start */
266 if (prefix != NULL && prefix < *start) {
267 g_assert (*start - prefix <= 3);/* only 3 are allowed */
270 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
271 instlen = (uintptr_t)(*end - *start);
272 /* Only check for instructions which are less than */
273 /* kNaClAlignment. The only instructions that should ever */
274 /* be that long are call sequences, which are already */
275 /* padded out to align the return to the next bundle. */
276 if (instlen > space_in_block && instlen < kNaClAlignment) {
277 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
278 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
279 const size_t length = (size_t)((*end)-(*start));
280 g_assert (length < MAX_NACL_INST_LENGTH);
282 memcpy (copy_of_instruction, *start, length);
283 *start = mono_arch_nacl_pad (*start, space_in_block);
284 memcpy (*start, copy_of_instruction, length);
285 *end = *start + length;
287 amd64_nacl_clear_legacy_prefix_tag ();
288 amd64_nacl_tag_rex (NULL);
292 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
293 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
294 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
295 /* make sure the upper 32-bits are cleared, and use that register in the */
296 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
298 /* pointer to current instruction stream (in the */
299 /* middle of an instruction, after opcode is emitted) */
300 /* basereg/offset/dreg */
301 /* operands of normal membase address */
303 /* pointer to the end of the membase/memindex emit */
304 /* GLOBALS: nacl_rex_tag */
305 /* position in instruction stream that rex prefix was emitted */
306 /* nacl_legacy_prefix_tag */
307 /* (possibly NULL) position in instruction of legacy x86 prefix */
309 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
311 gint8 true_basereg = basereg;
313 /* Cache these values, they might change */
314 /* as new instructions are emitted below. */
315 guint8* rex_tag = amd64_nacl_get_rex_tag ();
316 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
318 /* 'basereg' is given masked to 0x7 at this point, so check */
319 /* the rex prefix to see if this is an extended register. */
320 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
324 #define X86_LEA_OPCODE (0x8D)
326 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
327 guint8* old_instruction_start;
329 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
330 /* 32-bits of the old base register (new index register) */
332 guint8* buf_ptr = buf;
335 g_assert (rex_tag != NULL);
337 if (IS_REX(*rex_tag)) {
338 /* The old rex.B should be the new rex.X */
339 if (*rex_tag & AMD64_REX_B) {
340 *rex_tag |= AMD64_REX_X;
342 /* Since our new base is %r15 set rex.B */
343 *rex_tag |= AMD64_REX_B;
345 /* Shift the instruction by one byte */
346 /* so we can insert a rex prefix */
347 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
349 /* New rex prefix only needs rex.B for %r15 base */
350 *rex_tag = AMD64_REX(AMD64_REX_B);
353 if (legacy_prefix_tag) {
354 old_instruction_start = legacy_prefix_tag;
356 old_instruction_start = rex_tag;
359 /* Clears the upper 32-bits of the previous base register */
360 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
361 insert_len = buf_ptr - buf;
363 /* Move the old instruction forward to make */
364 /* room for 'mov' stored in 'buf_ptr' */
365 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
367 memcpy (old_instruction_start, buf, insert_len);
369 /* Sandboxed replacement for the normal membase_emit */
370 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
373 /* Normal default behavior, emit membase memory location */
374 x86_membase_emit_body (*code, dreg, basereg, offset);
379 static inline unsigned char*
380 amd64_skip_nops (unsigned char* code)
385 if ( code[0] == 0x90) {
389 if ( code[0] == 0x66 && code[1] == 0x90) {
393 if (code[0] == 0x0f && code[1] == 0x1f
394 && code[2] == 0x00) {
398 if (code[0] == 0x0f && code[1] == 0x1f
399 && code[2] == 0x40 && code[3] == 0x00) {
403 if (code[0] == 0x0f && code[1] == 0x1f
404 && code[2] == 0x44 && code[3] == 0x00
405 && code[4] == 0x00) {
409 if (code[0] == 0x66 && code[1] == 0x0f
410 && code[2] == 0x1f && code[3] == 0x44
411 && code[4] == 0x00 && code[5] == 0x00) {
415 if (code[0] == 0x0f && code[1] == 0x1f
416 && code[2] == 0x80 && code[3] == 0x00
417 && code[4] == 0x00 && code[5] == 0x00
418 && code[6] == 0x00) {
422 if (code[0] == 0x0f && code[1] == 0x1f
423 && code[2] == 0x84 && code[3] == 0x00
424 && code[4] == 0x00 && code[5] == 0x00
425 && code[6] == 0x00 && code[7] == 0x00) {
434 mono_arch_nacl_skip_nops (guint8* code)
436 return amd64_skip_nops(code);
439 #endif /*__native_client_codegen__*/
442 amd64_patch (unsigned char* code, gpointer target)
446 #ifdef __native_client_codegen__
447 code = amd64_skip_nops (code);
449 #if defined(__native_client_codegen__) && defined(__native_client__)
450 if (nacl_is_code_address (code)) {
451 /* For tail calls, code is patched after being installed */
452 /* but not through the normal "patch callsite" method. */
453 unsigned char buf[kNaClAlignment];
454 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
456 memcpy (buf, aligned_code, kNaClAlignment);
457 /* Patch a temp buffer of bundle size, */
458 /* then install to actual location. */
459 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
460 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
464 target = nacl_modify_patch_target (target);
468 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
473 if ((code [0] & 0xf8) == 0xb8) {
474 /* amd64_set_reg_template */
475 *(guint64*)(code + 1) = (guint64)target;
477 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
478 /* mov 0(%rip), %dreg */
479 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
481 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
482 /* call *<OFFSET>(%rip) */
483 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
485 else if (code [0] == 0xe8) {
487 gint64 disp = (guint8*)target - (guint8*)code;
488 g_assert (amd64_is_imm32 (disp));
489 x86_patch (code, (unsigned char*)target);
492 x86_patch (code, (unsigned char*)target);
496 mono_amd64_patch (unsigned char* code, gpointer target)
498 amd64_patch (code, target);
507 ArgValuetypeAddrInIReg,
508 ArgNone /* only in pair_storage */
516 /* Only if storage == ArgValuetypeInReg */
517 ArgStorage pair_storage [2];
527 gboolean need_stack_align;
528 gboolean vtype_retaddr;
529 /* The index of the vret arg in the argument list */
536 #define DEBUG(a) if (cfg->verbose_level > 1) a
541 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
543 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
547 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
549 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
553 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
555 ainfo->offset = *stack_size;
557 if (*gr >= PARAM_REGS) {
558 ainfo->storage = ArgOnStack;
559 /* Since the same stack slot size is used for all arg */
560 /* types, it needs to be big enough to hold them all */
561 (*stack_size) += sizeof(mgreg_t);
564 ainfo->storage = ArgInIReg;
565 ainfo->reg = param_regs [*gr];
571 #define FLOAT_PARAM_REGS 4
573 #define FLOAT_PARAM_REGS 8
577 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
579 ainfo->offset = *stack_size;
581 if (*gr >= FLOAT_PARAM_REGS) {
582 ainfo->storage = ArgOnStack;
583 /* Since the same stack slot size is used for both float */
584 /* types, it needs to be big enough to hold them both */
585 (*stack_size) += sizeof(mgreg_t);
588 /* A double register */
590 ainfo->storage = ArgInDoubleSSEReg;
592 ainfo->storage = ArgInFloatSSEReg;
598 typedef enum ArgumentClass {
606 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
608 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
611 ptype = mini_type_get_underlying_type (NULL, type);
612 switch (ptype->type) {
613 case MONO_TYPE_BOOLEAN:
623 case MONO_TYPE_STRING:
624 case MONO_TYPE_OBJECT:
625 case MONO_TYPE_CLASS:
626 case MONO_TYPE_SZARRAY:
628 case MONO_TYPE_FNPTR:
629 case MONO_TYPE_ARRAY:
632 class2 = ARG_CLASS_INTEGER;
637 class2 = ARG_CLASS_INTEGER;
639 class2 = ARG_CLASS_SSE;
643 case MONO_TYPE_TYPEDBYREF:
644 g_assert_not_reached ();
646 case MONO_TYPE_GENERICINST:
647 if (!mono_type_generic_inst_is_valuetype (ptype)) {
648 class2 = ARG_CLASS_INTEGER;
652 case MONO_TYPE_VALUETYPE: {
653 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
656 for (i = 0; i < info->num_fields; ++i) {
658 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
663 g_assert_not_reached ();
667 if (class1 == class2)
669 else if (class1 == ARG_CLASS_NO_CLASS)
671 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
672 class1 = ARG_CLASS_MEMORY;
673 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
674 class1 = ARG_CLASS_INTEGER;
676 class1 = ARG_CLASS_SSE;
680 #ifdef __native_client_codegen__
682 /* Default alignment for Native Client is 32-byte. */
683 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
685 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
686 /* Check that alignment doesn't cross an alignment boundary. */
688 mono_arch_nacl_pad(guint8 *code, int pad)
690 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
692 if (pad == 0) return code;
693 /* assertion: alignment cannot cross a block boundary */
694 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
695 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
696 while (pad >= kMaxPadding) {
697 amd64_padding (code, kMaxPadding);
700 if (pad != 0) amd64_padding (code, pad);
706 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
708 guint32 *gr, guint32 *fr, guint32 *stack_size)
710 guint32 size, quad, nquads, i;
711 /* Keep track of the size used in each quad so we can */
712 /* use the right size when copying args/return vars. */
713 guint32 quadsize [2] = {8, 8};
714 ArgumentClass args [2];
715 MonoMarshalType *info = NULL;
717 MonoGenericSharingContext tmp_gsctx;
718 gboolean pass_on_stack = FALSE;
721 * The gsctx currently contains no data, it is only used for checking whenever
722 * open types are allowed, some callers like mono_arch_get_argument_info ()
723 * don't pass it to us, so work around that.
728 klass = mono_class_from_mono_type (type);
729 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
731 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
732 /* We pass and return vtypes of size 8 in a register */
733 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
734 pass_on_stack = TRUE;
738 pass_on_stack = TRUE;
742 /* If this struct can't be split up naturally into 8-byte */
743 /* chunks (registers), pass it on the stack. */
744 if (sig->pinvoke && !pass_on_stack) {
748 info = mono_marshal_load_type_info (klass);
750 for (i = 0; i < info->num_fields; ++i) {
751 field_size = mono_marshal_type_size (info->fields [i].field->type,
752 info->fields [i].mspec,
753 &align, TRUE, klass->unicode);
754 if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
755 pass_on_stack = TRUE;
762 /* Allways pass in memory */
763 ainfo->offset = *stack_size;
764 *stack_size += ALIGN_TO (size, 8);
765 ainfo->storage = ArgOnStack;
770 /* FIXME: Handle structs smaller than 8 bytes */
771 //if ((size % 8) != 0)
780 /* Always pass in 1 or 2 integer registers */
781 args [0] = ARG_CLASS_INTEGER;
782 args [1] = ARG_CLASS_INTEGER;
783 /* Only the simplest cases are supported */
784 if (is_return && nquads != 1) {
785 args [0] = ARG_CLASS_MEMORY;
786 args [1] = ARG_CLASS_MEMORY;
790 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
791 * The X87 and SSEUP stuff is left out since there are no such types in
794 info = mono_marshal_load_type_info (klass);
798 if (info->native_size > 16) {
799 ainfo->offset = *stack_size;
800 *stack_size += ALIGN_TO (info->native_size, 8);
801 ainfo->storage = ArgOnStack;
806 switch (info->native_size) {
807 case 1: case 2: case 4: case 8:
811 ainfo->storage = ArgOnStack;
812 ainfo->offset = *stack_size;
813 *stack_size += ALIGN_TO (info->native_size, 8);
816 ainfo->storage = ArgValuetypeAddrInIReg;
818 if (*gr < PARAM_REGS) {
819 ainfo->pair_storage [0] = ArgInIReg;
820 ainfo->pair_regs [0] = param_regs [*gr];
824 ainfo->pair_storage [0] = ArgOnStack;
825 ainfo->offset = *stack_size;
834 args [0] = ARG_CLASS_NO_CLASS;
835 args [1] = ARG_CLASS_NO_CLASS;
836 for (quad = 0; quad < nquads; ++quad) {
839 ArgumentClass class1;
841 if (info->num_fields == 0)
842 class1 = ARG_CLASS_MEMORY;
844 class1 = ARG_CLASS_NO_CLASS;
845 for (i = 0; i < info->num_fields; ++i) {
846 size = mono_marshal_type_size (info->fields [i].field->type,
847 info->fields [i].mspec,
848 &align, TRUE, klass->unicode);
849 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
850 /* Unaligned field */
854 /* Skip fields in other quad */
855 if ((quad == 0) && (info->fields [i].offset >= 8))
857 if ((quad == 1) && (info->fields [i].offset < 8))
860 /* How far into this quad this data extends.*/
861 /* (8 is size of quad) */
862 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
864 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
866 g_assert (class1 != ARG_CLASS_NO_CLASS);
867 args [quad] = class1;
871 /* Post merger cleanup */
872 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
873 args [0] = args [1] = ARG_CLASS_MEMORY;
875 /* Allocate registers */
880 ainfo->storage = ArgValuetypeInReg;
881 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
882 ainfo->nregs = nquads;
883 for (quad = 0; quad < nquads; ++quad) {
884 switch (args [quad]) {
885 case ARG_CLASS_INTEGER:
886 if (*gr >= PARAM_REGS)
887 args [quad] = ARG_CLASS_MEMORY;
889 ainfo->pair_storage [quad] = ArgInIReg;
891 ainfo->pair_regs [quad] = return_regs [*gr];
893 ainfo->pair_regs [quad] = param_regs [*gr];
898 if (*fr >= FLOAT_PARAM_REGS)
899 args [quad] = ARG_CLASS_MEMORY;
901 if (quadsize[quad] <= 4)
902 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
903 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
904 ainfo->pair_regs [quad] = *fr;
908 case ARG_CLASS_MEMORY:
911 g_assert_not_reached ();
915 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
916 /* Revert possible register assignments */
920 ainfo->offset = *stack_size;
922 *stack_size += ALIGN_TO (info->native_size, 8);
924 *stack_size += nquads * sizeof(mgreg_t);
925 ainfo->storage = ArgOnStack;
933 * Obtain information about a call according to the calling convention.
934 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
935 * Draft Version 0.23" document for more information.
938 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
940 guint32 i, gr, fr, pstart;
942 int n = sig->hasthis + sig->param_count;
943 guint32 stack_size = 0;
945 gboolean is_pinvoke = sig->pinvoke;
948 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
950 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
959 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
960 switch (ret_type->type) {
961 case MONO_TYPE_BOOLEAN:
972 case MONO_TYPE_FNPTR:
973 case MONO_TYPE_CLASS:
974 case MONO_TYPE_OBJECT:
975 case MONO_TYPE_SZARRAY:
976 case MONO_TYPE_ARRAY:
977 case MONO_TYPE_STRING:
978 cinfo->ret.storage = ArgInIReg;
979 cinfo->ret.reg = AMD64_RAX;
983 cinfo->ret.storage = ArgInIReg;
984 cinfo->ret.reg = AMD64_RAX;
987 cinfo->ret.storage = ArgInFloatSSEReg;
988 cinfo->ret.reg = AMD64_XMM0;
991 cinfo->ret.storage = ArgInDoubleSSEReg;
992 cinfo->ret.reg = AMD64_XMM0;
994 case MONO_TYPE_GENERICINST:
995 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
996 cinfo->ret.storage = ArgInIReg;
997 cinfo->ret.reg = AMD64_RAX;
1001 #if defined( __native_client_codegen__ )
1002 case MONO_TYPE_TYPEDBYREF:
1004 case MONO_TYPE_VALUETYPE: {
1005 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1007 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1008 if (cinfo->ret.storage == ArgOnStack) {
1009 cinfo->vtype_retaddr = TRUE;
1010 /* The caller passes the address where the value is stored */
1014 #if !defined( __native_client_codegen__ )
1015 case MONO_TYPE_TYPEDBYREF:
1016 /* Same as a valuetype with size 24 */
1017 cinfo->vtype_retaddr = TRUE;
1020 case MONO_TYPE_VOID:
1023 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1029 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1030 * the first argument, allowing 'this' to be always passed in the first arg reg.
1031 * Also do this if the first argument is a reference type, since virtual calls
1032 * are sometimes made using calli without sig->hasthis set, like in the delegate
1035 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1037 add_general (&gr, &stack_size, cinfo->args + 0);
1039 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1042 add_general (&gr, &stack_size, &cinfo->ret);
1043 cinfo->vret_arg_index = 1;
1047 add_general (&gr, &stack_size, cinfo->args + 0);
1049 if (cinfo->vtype_retaddr)
1050 add_general (&gr, &stack_size, &cinfo->ret);
1053 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1055 fr = FLOAT_PARAM_REGS;
1057 /* Emit the signature cookie just before the implicit arguments */
1058 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1061 for (i = pstart; i < sig->param_count; ++i) {
1062 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1066 /* The float param registers and other param registers must be the same index on Windows x64.*/
1073 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1074 /* We allways pass the sig cookie on the stack for simplicity */
1076 * Prevent implicit arguments + the sig cookie from being passed
1080 fr = FLOAT_PARAM_REGS;
1082 /* Emit the signature cookie just before the implicit arguments */
1083 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1086 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1087 switch (ptype->type) {
1088 case MONO_TYPE_BOOLEAN:
1091 add_general (&gr, &stack_size, ainfo);
1095 case MONO_TYPE_CHAR:
1096 add_general (&gr, &stack_size, ainfo);
1100 add_general (&gr, &stack_size, ainfo);
1105 case MONO_TYPE_FNPTR:
1106 case MONO_TYPE_CLASS:
1107 case MONO_TYPE_OBJECT:
1108 case MONO_TYPE_STRING:
1109 case MONO_TYPE_SZARRAY:
1110 case MONO_TYPE_ARRAY:
1111 add_general (&gr, &stack_size, ainfo);
1113 case MONO_TYPE_GENERICINST:
1114 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1115 add_general (&gr, &stack_size, ainfo);
1119 case MONO_TYPE_VALUETYPE:
1120 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1122 case MONO_TYPE_TYPEDBYREF:
1123 #if defined( HOST_WIN32 ) || defined( __native_client_codegen__ )
1124 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1126 stack_size += sizeof (MonoTypedRef);
1127 ainfo->storage = ArgOnStack;
1132 add_general (&gr, &stack_size, ainfo);
1135 add_float (&fr, &stack_size, ainfo, FALSE);
1138 add_float (&fr, &stack_size, ainfo, TRUE);
1141 g_assert_not_reached ();
1145 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1147 fr = FLOAT_PARAM_REGS;
1149 /* Emit the signature cookie just before the implicit arguments */
1150 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1154 // There always is 32 bytes reserved on the stack when calling on Winx64
1158 #ifndef MONO_AMD64_NO_PUSHES
1159 if (stack_size & 0x8) {
1160 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1161 cinfo->need_stack_align = TRUE;
1166 cinfo->stack_usage = stack_size;
1167 cinfo->reg_usage = gr;
1168 cinfo->freg_usage = fr;
1173 * mono_arch_get_argument_info:
1174 * @csig: a method signature
1175 * @param_count: the number of parameters to consider
1176 * @arg_info: an array to store the result infos
1178 * Gathers information on parameters such as size, alignment and
1179 * padding. arg_info should be large enought to hold param_count + 1 entries.
1181 * Returns the size of the argument area on the stack.
1184 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1187 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1188 guint32 args_size = cinfo->stack_usage;
1190 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1191 if (csig->hasthis) {
1192 arg_info [0].offset = 0;
1195 for (k = 0; k < param_count; k++) {
1196 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1198 arg_info [k + 1].size = 0;
1207 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1212 c1 = get_call_info (NULL, NULL, caller_sig);
1213 c2 = get_call_info (NULL, NULL, callee_sig);
1214 res = c1->stack_usage >= c2->stack_usage;
1215 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
1216 /* An address on the callee's stack is passed as the first argument */
1226 * Initialize the cpu to execute managed code.
1229 mono_arch_cpu_init (void)
1234 /* spec compliance requires running with double precision */
1235 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1236 fpcw &= ~X86_FPCW_PRECC_MASK;
1237 fpcw |= X86_FPCW_PREC_DOUBLE;
1238 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1239 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1241 /* TODO: This is crashing on Win64 right now.
1242 * _control87 (_PC_53, MCW_PC);
1248 * Initialize architecture specific code.
1251 mono_arch_init (void)
1255 InitializeCriticalSection (&mini_arch_mutex);
1256 #if defined(__native_client_codegen__)
1257 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1258 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1259 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1260 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1263 #ifdef MONO_ARCH_NOMAP32BIT
1264 flags = MONO_MMAP_READ;
1265 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1266 breakpoint_size = 13;
1267 breakpoint_fault_size = 3;
1269 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1270 /* amd64_mov_reg_mem () */
1271 breakpoint_size = 8;
1272 breakpoint_fault_size = 8;
1275 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1276 single_step_fault_size = 4;
1278 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1279 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1280 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1282 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1283 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1284 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1288 * Cleanup architecture specific code.
1291 mono_arch_cleanup (void)
1293 DeleteCriticalSection (&mini_arch_mutex);
1294 #if defined(__native_client_codegen__)
1295 mono_native_tls_free (nacl_instruction_depth);
1296 mono_native_tls_free (nacl_rex_tag);
1297 mono_native_tls_free (nacl_legacy_prefix_tag);
1302 * This function returns the optimizations supported on this cpu.
1305 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1311 if (mono_hwcap_x86_has_cmov) {
1312 opts |= MONO_OPT_CMOV;
1314 if (mono_hwcap_x86_has_fcmov)
1315 opts |= MONO_OPT_FCMOV;
1317 *exclude_mask |= MONO_OPT_FCMOV;
1319 *exclude_mask |= MONO_OPT_CMOV;
1326 * This function test for all SSE functions supported.
1328 * Returns a bitmask corresponding to all supported versions.
1332 mono_arch_cpu_enumerate_simd_versions (void)
1334 guint32 sse_opts = 0;
1336 if (mono_hwcap_x86_has_sse1)
1337 sse_opts |= SIMD_VERSION_SSE1;
1339 if (mono_hwcap_x86_has_sse2)
1340 sse_opts |= SIMD_VERSION_SSE2;
1342 if (mono_hwcap_x86_has_sse3)
1343 sse_opts |= SIMD_VERSION_SSE3;
1345 if (mono_hwcap_x86_has_ssse3)
1346 sse_opts |= SIMD_VERSION_SSSE3;
1348 if (mono_hwcap_x86_has_sse41)
1349 sse_opts |= SIMD_VERSION_SSE41;
1351 if (mono_hwcap_x86_has_sse42)
1352 sse_opts |= SIMD_VERSION_SSE42;
1354 if (mono_hwcap_x86_has_sse4a)
1355 sse_opts |= SIMD_VERSION_SSE4a;
1363 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1368 for (i = 0; i < cfg->num_varinfo; i++) {
1369 MonoInst *ins = cfg->varinfo [i];
1370 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1373 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1376 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1377 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1380 if (mono_is_regsize_var (ins->inst_vtype)) {
1381 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1382 g_assert (i == vmv->idx);
1383 vars = g_list_prepend (vars, vmv);
1387 vars = mono_varlist_sort (cfg, vars, 0);
1393 * mono_arch_compute_omit_fp:
1395 * Determine whenever the frame pointer can be eliminated.
1398 mono_arch_compute_omit_fp (MonoCompile *cfg)
1400 MonoMethodSignature *sig;
1401 MonoMethodHeader *header;
1405 if (cfg->arch.omit_fp_computed)
1408 header = cfg->header;
1410 sig = mono_method_signature (cfg->method);
1412 if (!cfg->arch.cinfo)
1413 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1414 cinfo = cfg->arch.cinfo;
1417 * FIXME: Remove some of the restrictions.
1419 cfg->arch.omit_fp = TRUE;
1420 cfg->arch.omit_fp_computed = TRUE;
1422 #ifdef __native_client_codegen__
1423 /* NaCl modules may not change the value of RBP, so it cannot be */
1424 /* used as a normal register, but it can be used as a frame pointer*/
1425 cfg->disable_omit_fp = TRUE;
1426 cfg->arch.omit_fp = FALSE;
1429 if (cfg->disable_omit_fp)
1430 cfg->arch.omit_fp = FALSE;
1432 if (!debug_omit_fp ())
1433 cfg->arch.omit_fp = FALSE;
1435 if (cfg->method->save_lmf)
1436 cfg->arch.omit_fp = FALSE;
1438 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1439 cfg->arch.omit_fp = FALSE;
1440 if (header->num_clauses)
1441 cfg->arch.omit_fp = FALSE;
1442 if (cfg->param_area)
1443 cfg->arch.omit_fp = FALSE;
1444 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1445 cfg->arch.omit_fp = FALSE;
1446 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1447 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1448 cfg->arch.omit_fp = FALSE;
1449 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1450 ArgInfo *ainfo = &cinfo->args [i];
1452 if (ainfo->storage == ArgOnStack) {
1454 * The stack offset can only be determined when the frame
1457 cfg->arch.omit_fp = FALSE;
1462 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1463 MonoInst *ins = cfg->varinfo [i];
1466 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1471 mono_arch_get_global_int_regs (MonoCompile *cfg)
1475 mono_arch_compute_omit_fp (cfg);
1477 if (cfg->globalra) {
1478 if (cfg->arch.omit_fp)
1479 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1481 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1482 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1483 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1484 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1485 #ifndef __native_client_codegen__
1486 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1489 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1490 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1491 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1492 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1493 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1494 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1495 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1496 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1498 if (cfg->arch.omit_fp)
1499 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1501 /* We use the callee saved registers for global allocation */
1502 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1503 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1504 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1505 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1506 #ifndef __native_client_codegen__
1507 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1510 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1511 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1519 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1524 /* All XMM registers */
1525 for (i = 0; i < 16; ++i)
1526 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1532 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1534 static GList *r = NULL;
1539 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1540 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1541 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1542 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1543 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1544 #ifndef __native_client_codegen__
1545 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1548 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1549 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1550 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1551 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1552 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1553 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1554 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1555 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1557 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1564 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1567 static GList *r = NULL;
1572 for (i = 0; i < AMD64_XMM_NREG; ++i)
1573 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1575 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1582 * mono_arch_regalloc_cost:
1584 * Return the cost, in number of memory references, of the action of
1585 * allocating the variable VMV into a register during global register
1589 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1591 MonoInst *ins = cfg->varinfo [vmv->idx];
1593 if (cfg->method->save_lmf)
1594 /* The register is already saved */
1595 /* substract 1 for the invisible store in the prolog */
1596 return (ins->opcode == OP_ARG) ? 0 : 1;
1599 return (ins->opcode == OP_ARG) ? 1 : 2;
1603 * mono_arch_fill_argument_info:
1605 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1609 mono_arch_fill_argument_info (MonoCompile *cfg)
1611 MonoMethodSignature *sig;
1612 MonoMethodHeader *header;
1617 header = cfg->header;
1619 sig = mono_method_signature (cfg->method);
1621 cinfo = cfg->arch.cinfo;
1624 * Contrary to mono_arch_allocate_vars (), the information should describe
1625 * where the arguments are at the beginning of the method, not where they can be
1626 * accessed during the execution of the method. The later makes no sense for the
1627 * global register allocator, since a variable can be in more than one location.
1629 if (sig->ret->type != MONO_TYPE_VOID) {
1630 switch (cinfo->ret.storage) {
1632 case ArgInFloatSSEReg:
1633 case ArgInDoubleSSEReg:
1634 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || ((sig->ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1635 cfg->vret_addr->opcode = OP_REGVAR;
1636 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1639 cfg->ret->opcode = OP_REGVAR;
1640 cfg->ret->inst_c0 = cinfo->ret.reg;
1643 case ArgValuetypeInReg:
1644 cfg->ret->opcode = OP_REGOFFSET;
1645 cfg->ret->inst_basereg = -1;
1646 cfg->ret->inst_offset = -1;
1649 g_assert_not_reached ();
1653 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1654 ArgInfo *ainfo = &cinfo->args [i];
1657 ins = cfg->args [i];
1659 if (sig->hasthis && (i == 0))
1660 arg_type = &mono_defaults.object_class->byval_arg;
1662 arg_type = sig->params [i - sig->hasthis];
1664 switch (ainfo->storage) {
1666 case ArgInFloatSSEReg:
1667 case ArgInDoubleSSEReg:
1668 ins->opcode = OP_REGVAR;
1669 ins->inst_c0 = ainfo->reg;
1672 ins->opcode = OP_REGOFFSET;
1673 ins->inst_basereg = -1;
1674 ins->inst_offset = -1;
1676 case ArgValuetypeInReg:
1678 ins->opcode = OP_NOP;
1681 g_assert_not_reached ();
1687 mono_arch_allocate_vars (MonoCompile *cfg)
1689 MonoMethodSignature *sig;
1690 MonoMethodHeader *header;
1693 guint32 locals_stack_size, locals_stack_align;
1697 header = cfg->header;
1699 sig = mono_method_signature (cfg->method);
1701 cinfo = cfg->arch.cinfo;
1703 mono_arch_compute_omit_fp (cfg);
1706 * We use the ABI calling conventions for managed code as well.
1707 * Exception: valuetypes are only sometimes passed or returned in registers.
1711 * The stack looks like this:
1712 * <incoming arguments passed on the stack>
1714 * <lmf/caller saved registers>
1717 * <localloc area> -> grows dynamically
1721 if (cfg->arch.omit_fp) {
1722 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1723 cfg->frame_reg = AMD64_RSP;
1726 /* Locals are allocated backwards from %fp */
1727 cfg->frame_reg = AMD64_RBP;
1731 if (cfg->method->save_lmf) {
1732 /* The LMF var is allocated normally */
1734 if (cfg->arch.omit_fp)
1735 cfg->arch.reg_save_area_offset = offset;
1736 /* Reserve space for callee saved registers */
1737 for (i = 0; i < AMD64_NREG; ++i)
1738 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1739 offset += sizeof(mgreg_t);
1743 if (sig->ret->type != MONO_TYPE_VOID) {
1744 switch (cinfo->ret.storage) {
1746 case ArgInFloatSSEReg:
1747 case ArgInDoubleSSEReg:
1748 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || ((sig->ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1749 if (cfg->globalra) {
1750 cfg->vret_addr->opcode = OP_REGVAR;
1751 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1753 /* The register is volatile */
1754 cfg->vret_addr->opcode = OP_REGOFFSET;
1755 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1756 if (cfg->arch.omit_fp) {
1757 cfg->vret_addr->inst_offset = offset;
1761 cfg->vret_addr->inst_offset = -offset;
1763 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1764 printf ("vret_addr =");
1765 mono_print_ins (cfg->vret_addr);
1770 cfg->ret->opcode = OP_REGVAR;
1771 cfg->ret->inst_c0 = cinfo->ret.reg;
1774 case ArgValuetypeInReg:
1775 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1776 cfg->ret->opcode = OP_REGOFFSET;
1777 cfg->ret->inst_basereg = cfg->frame_reg;
1778 if (cfg->arch.omit_fp) {
1779 cfg->ret->inst_offset = offset;
1780 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1782 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1783 cfg->ret->inst_offset = - offset;
1787 g_assert_not_reached ();
1790 cfg->ret->dreg = cfg->ret->inst_c0;
1793 /* Allocate locals */
1794 if (!cfg->globalra) {
1795 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1796 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1797 char *mname = mono_method_full_name (cfg->method, TRUE);
1798 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1799 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1804 if (locals_stack_align) {
1805 offset += (locals_stack_align - 1);
1806 offset &= ~(locals_stack_align - 1);
1808 if (cfg->arch.omit_fp) {
1809 cfg->locals_min_stack_offset = offset;
1810 cfg->locals_max_stack_offset = offset + locals_stack_size;
1812 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1813 cfg->locals_max_stack_offset = - offset;
1816 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1817 if (offsets [i] != -1) {
1818 MonoInst *ins = cfg->varinfo [i];
1819 ins->opcode = OP_REGOFFSET;
1820 ins->inst_basereg = cfg->frame_reg;
1821 if (cfg->arch.omit_fp)
1822 ins->inst_offset = (offset + offsets [i]);
1824 ins->inst_offset = - (offset + offsets [i]);
1825 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1828 offset += locals_stack_size;
1831 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1832 g_assert (!cfg->arch.omit_fp);
1833 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1834 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1837 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1838 ins = cfg->args [i];
1839 if (ins->opcode != OP_REGVAR) {
1840 ArgInfo *ainfo = &cinfo->args [i];
1841 gboolean inreg = TRUE;
1844 if (sig->hasthis && (i == 0))
1845 arg_type = &mono_defaults.object_class->byval_arg;
1847 arg_type = sig->params [i - sig->hasthis];
1849 if (cfg->globalra) {
1850 /* The new allocator needs info about the original locations of the arguments */
1851 switch (ainfo->storage) {
1853 case ArgInFloatSSEReg:
1854 case ArgInDoubleSSEReg:
1855 ins->opcode = OP_REGVAR;
1856 ins->inst_c0 = ainfo->reg;
1859 g_assert (!cfg->arch.omit_fp);
1860 ins->opcode = OP_REGOFFSET;
1861 ins->inst_basereg = cfg->frame_reg;
1862 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1864 case ArgValuetypeInReg:
1865 ins->opcode = OP_REGOFFSET;
1866 ins->inst_basereg = cfg->frame_reg;
1867 /* These arguments are saved to the stack in the prolog */
1868 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1869 if (cfg->arch.omit_fp) {
1870 ins->inst_offset = offset;
1871 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1873 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1874 ins->inst_offset = - offset;
1878 g_assert_not_reached ();
1884 /* FIXME: Allocate volatile arguments to registers */
1885 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1889 * Under AMD64, all registers used to pass arguments to functions
1890 * are volatile across calls.
1891 * FIXME: Optimize this.
1893 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1896 ins->opcode = OP_REGOFFSET;
1898 switch (ainfo->storage) {
1900 case ArgInFloatSSEReg:
1901 case ArgInDoubleSSEReg:
1903 ins->opcode = OP_REGVAR;
1904 ins->dreg = ainfo->reg;
1908 g_assert (!cfg->arch.omit_fp);
1909 ins->opcode = OP_REGOFFSET;
1910 ins->inst_basereg = cfg->frame_reg;
1911 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1913 case ArgValuetypeInReg:
1915 case ArgValuetypeAddrInIReg: {
1917 g_assert (!cfg->arch.omit_fp);
1919 MONO_INST_NEW (cfg, indir, 0);
1920 indir->opcode = OP_REGOFFSET;
1921 if (ainfo->pair_storage [0] == ArgInIReg) {
1922 indir->inst_basereg = cfg->frame_reg;
1923 offset = ALIGN_TO (offset, sizeof (gpointer));
1924 offset += (sizeof (gpointer));
1925 indir->inst_offset = - offset;
1928 indir->inst_basereg = cfg->frame_reg;
1929 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1932 ins->opcode = OP_VTARG_ADDR;
1933 ins->inst_left = indir;
1941 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1942 ins->opcode = OP_REGOFFSET;
1943 ins->inst_basereg = cfg->frame_reg;
1944 /* These arguments are saved to the stack in the prolog */
1945 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1946 if (cfg->arch.omit_fp) {
1947 ins->inst_offset = offset;
1948 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1949 // Arguments are yet supported by the stack map creation code
1950 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1952 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1953 ins->inst_offset = - offset;
1954 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1960 cfg->stack_offset = offset;
1964 mono_arch_create_vars (MonoCompile *cfg)
1966 MonoMethodSignature *sig;
1969 sig = mono_method_signature (cfg->method);
1971 if (!cfg->arch.cinfo)
1972 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1973 cinfo = cfg->arch.cinfo;
1975 if (cinfo->ret.storage == ArgValuetypeInReg)
1976 cfg->ret_var_is_local = TRUE;
1978 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1979 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1980 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1981 printf ("vret_addr = ");
1982 mono_print_ins (cfg->vret_addr);
1986 if (cfg->gen_seq_points) {
1989 if (cfg->compile_aot) {
1990 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1991 ins->flags |= MONO_INST_VOLATILE;
1992 cfg->arch.seq_point_info_var = ins;
1995 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1996 ins->flags |= MONO_INST_VOLATILE;
1997 cfg->arch.ss_trigger_page_var = ins;
2000 #ifdef MONO_AMD64_NO_PUSHES
2002 * When this is set, we pass arguments on the stack by moves, and by allocating
2003 * a bigger stack frame, instead of pushes.
2004 * Pushes complicate exception handling because the arguments on the stack have
2005 * to be popped each time a frame is unwound. They also make fp elimination
2007 * FIXME: This doesn't work inside filter/finally clauses, since those execute
2008 * on a new frame which doesn't include a param area.
2010 cfg->arch.no_pushes = TRUE;
2013 if (cfg->method->save_lmf) {
2014 MonoInst *lmf_var = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2015 lmf_var->flags |= MONO_INST_VOLATILE;
2016 lmf_var->flags |= MONO_INST_LMF;
2017 cfg->arch.lmf_var = lmf_var;
2020 #ifndef MONO_AMD64_NO_PUSHES
2021 cfg->arch_eh_jit_info = 1;
2026 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2032 MONO_INST_NEW (cfg, ins, OP_MOVE);
2033 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2034 ins->sreg1 = tree->dreg;
2035 MONO_ADD_INS (cfg->cbb, ins);
2036 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2038 case ArgInFloatSSEReg:
2039 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2040 ins->dreg = mono_alloc_freg (cfg);
2041 ins->sreg1 = tree->dreg;
2042 MONO_ADD_INS (cfg->cbb, ins);
2044 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2046 case ArgInDoubleSSEReg:
2047 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2048 ins->dreg = mono_alloc_freg (cfg);
2049 ins->sreg1 = tree->dreg;
2050 MONO_ADD_INS (cfg->cbb, ins);
2052 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2056 g_assert_not_reached ();
2061 arg_storage_to_load_membase (ArgStorage storage)
2065 #if defined(__mono_ilp32__)
2066 return OP_LOADI8_MEMBASE;
2068 return OP_LOAD_MEMBASE;
2070 case ArgInDoubleSSEReg:
2071 return OP_LOADR8_MEMBASE;
2072 case ArgInFloatSSEReg:
2073 return OP_LOADR4_MEMBASE;
2075 g_assert_not_reached ();
2082 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2085 MonoMethodSignature *tmp_sig;
2088 if (call->tail_call)
2091 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2094 * mono_ArgIterator_Setup assumes the signature cookie is
2095 * passed first and all the arguments which were before it are
2096 * passed on the stack after the signature. So compensate by
2097 * passing a different signature.
2099 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2100 tmp_sig->param_count -= call->signature->sentinelpos;
2101 tmp_sig->sentinelpos = 0;
2102 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2104 sig_reg = mono_alloc_ireg (cfg);
2105 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2107 if (cfg->arch.no_pushes) {
2108 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2110 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2111 arg->sreg1 = sig_reg;
2112 MONO_ADD_INS (cfg->cbb, arg);
2116 static inline LLVMArgStorage
2117 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2121 return LLVMArgInIReg;
2125 g_assert_not_reached ();
2132 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2138 LLVMCallInfo *linfo;
2141 n = sig->param_count + sig->hasthis;
2143 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2145 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2148 * LLVM always uses the native ABI while we use our own ABI, the
2149 * only difference is the handling of vtypes:
2150 * - we only pass/receive them in registers in some cases, and only
2151 * in 1 or 2 integer registers.
2153 if (cinfo->ret.storage == ArgValuetypeInReg) {
2155 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2156 cfg->disable_llvm = TRUE;
2160 linfo->ret.storage = LLVMArgVtypeInReg;
2161 for (j = 0; j < 2; ++j)
2162 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2165 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
2166 /* Vtype returned using a hidden argument */
2167 linfo->ret.storage = LLVMArgVtypeRetAddr;
2168 linfo->vret_arg_index = cinfo->vret_arg_index;
2171 for (i = 0; i < n; ++i) {
2172 ainfo = cinfo->args + i;
2174 if (i >= sig->hasthis)
2175 t = sig->params [i - sig->hasthis];
2177 t = &mono_defaults.int_class->byval_arg;
2179 linfo->args [i].storage = LLVMArgNone;
2181 switch (ainfo->storage) {
2183 linfo->args [i].storage = LLVMArgInIReg;
2185 case ArgInDoubleSSEReg:
2186 case ArgInFloatSSEReg:
2187 linfo->args [i].storage = LLVMArgInFPReg;
2190 if (MONO_TYPE_ISSTRUCT (t)) {
2191 linfo->args [i].storage = LLVMArgVtypeByVal;
2193 linfo->args [i].storage = LLVMArgInIReg;
2195 if (t->type == MONO_TYPE_R4)
2196 linfo->args [i].storage = LLVMArgInFPReg;
2197 else if (t->type == MONO_TYPE_R8)
2198 linfo->args [i].storage = LLVMArgInFPReg;
2202 case ArgValuetypeInReg:
2204 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2205 cfg->disable_llvm = TRUE;
2209 linfo->args [i].storage = LLVMArgVtypeInReg;
2210 for (j = 0; j < 2; ++j)
2211 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2214 cfg->exception_message = g_strdup ("ainfo->storage");
2215 cfg->disable_llvm = TRUE;
2225 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2228 MonoMethodSignature *sig;
2229 int i, n, stack_size;
2235 sig = call->signature;
2236 n = sig->param_count + sig->hasthis;
2238 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2240 if (COMPILE_LLVM (cfg)) {
2241 /* We shouldn't be called in the llvm case */
2242 cfg->disable_llvm = TRUE;
2246 if (cinfo->need_stack_align) {
2247 if (!cfg->arch.no_pushes)
2248 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2252 * Emit all arguments which are passed on the stack to prevent register
2253 * allocation problems.
2255 if (cfg->arch.no_pushes) {
2256 for (i = 0; i < n; ++i) {
2258 ainfo = cinfo->args + i;
2260 in = call->args [i];
2262 if (sig->hasthis && i == 0)
2263 t = &mono_defaults.object_class->byval_arg;
2265 t = sig->params [i - sig->hasthis];
2267 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2269 if (t->type == MONO_TYPE_R4)
2270 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2271 else if (t->type == MONO_TYPE_R8)
2272 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2274 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2276 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2278 if (cfg->compute_gc_maps) {
2281 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2288 * Emit all parameters passed in registers in non-reverse order for better readability
2289 * and to help the optimization in emit_prolog ().
2291 for (i = 0; i < n; ++i) {
2292 ainfo = cinfo->args + i;
2294 in = call->args [i];
2296 if (ainfo->storage == ArgInIReg)
2297 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2300 for (i = n - 1; i >= 0; --i) {
2301 ainfo = cinfo->args + i;
2303 in = call->args [i];
2305 switch (ainfo->storage) {
2309 case ArgInFloatSSEReg:
2310 case ArgInDoubleSSEReg:
2311 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2314 case ArgValuetypeInReg:
2315 case ArgValuetypeAddrInIReg:
2316 if (ainfo->storage == ArgOnStack && call->tail_call) {
2317 MonoInst *call_inst = (MonoInst*)call;
2318 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2319 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2320 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2324 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2325 size = sizeof (MonoTypedRef);
2326 align = sizeof (gpointer);
2330 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2333 * Other backends use mono_type_stack_size (), but that
2334 * aligns the size to 8, which is larger than the size of
2335 * the source, leading to reads of invalid memory if the
2336 * source is at the end of address space.
2338 size = mono_class_value_size (in->klass, &align);
2341 g_assert (in->klass);
2343 if (ainfo->storage == ArgOnStack && size >= 10000) {
2344 /* Avoid asserts in emit_memcpy () */
2345 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2346 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2347 /* Continue normally */
2351 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2352 arg->sreg1 = in->dreg;
2353 arg->klass = in->klass;
2354 arg->backend.size = size;
2355 arg->inst_p0 = call;
2356 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2357 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2359 MONO_ADD_INS (cfg->cbb, arg);
2362 if (cfg->arch.no_pushes) {
2365 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2366 arg->sreg1 = in->dreg;
2367 if (!sig->params [i - sig->hasthis]->byref) {
2368 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2369 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2370 arg->opcode = OP_STORER4_MEMBASE_REG;
2371 arg->inst_destbasereg = X86_ESP;
2372 arg->inst_offset = 0;
2373 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2374 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2375 arg->opcode = OP_STORER8_MEMBASE_REG;
2376 arg->inst_destbasereg = X86_ESP;
2377 arg->inst_offset = 0;
2380 MONO_ADD_INS (cfg->cbb, arg);
2385 g_assert_not_reached ();
2388 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2389 /* Emit the signature cookie just before the implicit arguments */
2390 emit_sig_cookie (cfg, call, cinfo);
2393 /* Handle the case where there are no implicit arguments */
2394 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2395 emit_sig_cookie (cfg, call, cinfo);
2397 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2400 if (cinfo->ret.storage == ArgValuetypeInReg) {
2401 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2403 * Tell the JIT to use a more efficient calling convention: call using
2404 * OP_CALL, compute the result location after the call, and save the
2407 call->vret_in_reg = TRUE;
2409 * Nullify the instruction computing the vret addr to enable
2410 * future optimizations.
2413 NULLIFY_INS (call->vret_var);
2415 if (call->tail_call)
2418 * The valuetype is in RAX:RDX after the call, need to be copied to
2419 * the stack. Push the address here, so the call instruction can
2422 if (!cfg->arch.vret_addr_loc) {
2423 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2424 /* Prevent it from being register allocated or optimized away */
2425 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2428 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2432 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2433 vtarg->sreg1 = call->vret_var->dreg;
2434 vtarg->dreg = mono_alloc_preg (cfg);
2435 MONO_ADD_INS (cfg->cbb, vtarg);
2437 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2442 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2443 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2447 if (cfg->method->save_lmf) {
2448 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2449 MONO_ADD_INS (cfg->cbb, arg);
2452 call->stack_usage = cinfo->stack_usage;
2456 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2459 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2460 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2461 int size = ins->backend.size;
2463 if (ainfo->storage == ArgValuetypeInReg) {
2467 for (part = 0; part < 2; ++part) {
2468 if (ainfo->pair_storage [part] == ArgNone)
2471 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2472 load->inst_basereg = src->dreg;
2473 load->inst_offset = part * sizeof(mgreg_t);
2475 switch (ainfo->pair_storage [part]) {
2477 load->dreg = mono_alloc_ireg (cfg);
2479 case ArgInDoubleSSEReg:
2480 case ArgInFloatSSEReg:
2481 load->dreg = mono_alloc_freg (cfg);
2484 g_assert_not_reached ();
2486 MONO_ADD_INS (cfg->cbb, load);
2488 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2490 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2491 MonoInst *vtaddr, *load;
2492 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2494 g_assert (!cfg->arch.no_pushes);
2496 MONO_INST_NEW (cfg, load, OP_LDADDR);
2497 load->inst_p0 = vtaddr;
2498 vtaddr->flags |= MONO_INST_INDIRECT;
2499 load->type = STACK_MP;
2500 load->klass = vtaddr->klass;
2501 load->dreg = mono_alloc_ireg (cfg);
2502 MONO_ADD_INS (cfg->cbb, load);
2503 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2505 if (ainfo->pair_storage [0] == ArgInIReg) {
2506 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2507 arg->dreg = mono_alloc_ireg (cfg);
2508 arg->sreg1 = load->dreg;
2510 MONO_ADD_INS (cfg->cbb, arg);
2511 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2513 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2514 arg->sreg1 = load->dreg;
2515 MONO_ADD_INS (cfg->cbb, arg);
2519 if (cfg->arch.no_pushes) {
2520 int dreg = mono_alloc_ireg (cfg);
2522 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2523 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2525 /* Can't use this for < 8 since it does an 8 byte memory load */
2526 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2527 arg->inst_basereg = src->dreg;
2528 arg->inst_offset = 0;
2529 MONO_ADD_INS (cfg->cbb, arg);
2531 } else if (size <= 40) {
2532 if (cfg->arch.no_pushes) {
2533 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2535 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2536 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2539 if (cfg->arch.no_pushes) {
2540 // FIXME: Code growth
2541 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2543 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2544 arg->inst_basereg = src->dreg;
2545 arg->inst_offset = 0;
2546 arg->inst_imm = size;
2547 MONO_ADD_INS (cfg->cbb, arg);
2551 if (cfg->compute_gc_maps) {
2553 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2559 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2561 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2563 if (ret->type == MONO_TYPE_R4) {
2564 if (COMPILE_LLVM (cfg))
2565 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2567 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2569 } else if (ret->type == MONO_TYPE_R8) {
2570 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2574 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2577 #endif /* DISABLE_JIT */
2579 #define EMIT_COND_BRANCH(ins,cond,sign) \
2580 if (ins->inst_true_bb->native_offset) { \
2581 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2583 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2584 if ((cfg->opt & MONO_OPT_BRANCH) && \
2585 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2586 x86_branch8 (code, cond, 0, sign); \
2588 x86_branch32 (code, cond, 0, sign); \
2592 MonoMethodSignature *sig;
2597 mgreg_t regs [PARAM_REGS];
2603 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2611 switch (cinfo->ret.storage) {
2615 case ArgValuetypeInReg: {
2616 ArgInfo *ainfo = &cinfo->ret;
2618 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2620 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2628 for (i = 0; i < cinfo->nargs; ++i) {
2629 ArgInfo *ainfo = &cinfo->args [i];
2630 switch (ainfo->storage) {
2633 case ArgValuetypeInReg:
2634 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2636 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2648 * mono_arch_dyn_call_prepare:
2650 * Return a pointer to an arch-specific structure which contains information
2651 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2652 * supported for SIG.
2653 * This function is equivalent to ffi_prep_cif in libffi.
2656 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2658 ArchDynCallInfo *info;
2661 cinfo = get_call_info (NULL, NULL, sig);
2663 if (!dyn_call_supported (sig, cinfo)) {
2668 info = g_new0 (ArchDynCallInfo, 1);
2669 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2671 info->cinfo = cinfo;
2673 return (MonoDynCallInfo*)info;
2677 * mono_arch_dyn_call_free:
2679 * Free a MonoDynCallInfo structure.
2682 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2684 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2686 g_free (ainfo->cinfo);
2690 #if !defined(__native_client__)
2691 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2692 #define GREG_TO_PTR(greg) (gpointer)(greg)
2694 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2695 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2696 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2700 * mono_arch_get_start_dyn_call:
2702 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2703 * store the result into BUF.
2704 * ARGS should be an array of pointers pointing to the arguments.
2705 * RET should point to a memory buffer large enought to hold the result of the
2707 * This function should be as fast as possible, any work which does not depend
2708 * on the actual values of the arguments should be done in
2709 * mono_arch_dyn_call_prepare ().
2710 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2714 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2716 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2717 DynCallArgs *p = (DynCallArgs*)buf;
2718 int arg_index, greg, i, pindex;
2719 MonoMethodSignature *sig = dinfo->sig;
2721 g_assert (buf_len >= sizeof (DynCallArgs));
2730 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2731 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2736 if (dinfo->cinfo->vtype_retaddr)
2737 p->regs [greg ++] = PTR_TO_GREG(ret);
2739 for (i = pindex; i < sig->param_count; i++) {
2740 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2741 gpointer *arg = args [arg_index ++];
2744 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2749 case MONO_TYPE_STRING:
2750 case MONO_TYPE_CLASS:
2751 case MONO_TYPE_ARRAY:
2752 case MONO_TYPE_SZARRAY:
2753 case MONO_TYPE_OBJECT:
2757 #if !defined(__mono_ilp32__)
2761 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2762 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2764 #if defined(__mono_ilp32__)
2767 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2768 p->regs [greg ++] = *(guint64*)(arg);
2771 case MONO_TYPE_BOOLEAN:
2773 p->regs [greg ++] = *(guint8*)(arg);
2776 p->regs [greg ++] = *(gint8*)(arg);
2779 p->regs [greg ++] = *(gint16*)(arg);
2782 case MONO_TYPE_CHAR:
2783 p->regs [greg ++] = *(guint16*)(arg);
2786 p->regs [greg ++] = *(gint32*)(arg);
2789 p->regs [greg ++] = *(guint32*)(arg);
2791 case MONO_TYPE_GENERICINST:
2792 if (MONO_TYPE_IS_REFERENCE (t)) {
2793 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2798 case MONO_TYPE_VALUETYPE: {
2799 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2801 g_assert (ainfo->storage == ArgValuetypeInReg);
2802 if (ainfo->pair_storage [0] != ArgNone) {
2803 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2804 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2806 if (ainfo->pair_storage [1] != ArgNone) {
2807 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2808 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2813 g_assert_not_reached ();
2817 g_assert (greg <= PARAM_REGS);
2821 * mono_arch_finish_dyn_call:
2823 * Store the result of a dyn call into the return value buffer passed to
2824 * start_dyn_call ().
2825 * This function should be as fast as possible, any work which does not depend
2826 * on the actual values of the arguments should be done in
2827 * mono_arch_dyn_call_prepare ().
2830 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2832 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2833 MonoMethodSignature *sig = dinfo->sig;
2834 guint8 *ret = ((DynCallArgs*)buf)->ret;
2835 mgreg_t res = ((DynCallArgs*)buf)->res;
2837 switch (mono_type_get_underlying_type (sig->ret)->type) {
2838 case MONO_TYPE_VOID:
2839 *(gpointer*)ret = NULL;
2841 case MONO_TYPE_STRING:
2842 case MONO_TYPE_CLASS:
2843 case MONO_TYPE_ARRAY:
2844 case MONO_TYPE_SZARRAY:
2845 case MONO_TYPE_OBJECT:
2849 *(gpointer*)ret = GREG_TO_PTR(res);
2855 case MONO_TYPE_BOOLEAN:
2856 *(guint8*)ret = res;
2859 *(gint16*)ret = res;
2862 case MONO_TYPE_CHAR:
2863 *(guint16*)ret = res;
2866 *(gint32*)ret = res;
2869 *(guint32*)ret = res;
2872 *(gint64*)ret = res;
2875 *(guint64*)ret = res;
2877 case MONO_TYPE_GENERICINST:
2878 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2879 *(gpointer*)ret = GREG_TO_PTR(res);
2884 case MONO_TYPE_VALUETYPE:
2885 if (dinfo->cinfo->vtype_retaddr) {
2888 ArgInfo *ainfo = &dinfo->cinfo->ret;
2890 g_assert (ainfo->storage == ArgValuetypeInReg);
2892 if (ainfo->pair_storage [0] != ArgNone) {
2893 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2894 ((mgreg_t*)ret)[0] = res;
2897 g_assert (ainfo->pair_storage [1] == ArgNone);
2901 g_assert_not_reached ();
2905 /* emit an exception if condition is fail */
2906 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2908 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2909 if (tins == NULL) { \
2910 mono_add_patch_info (cfg, code - cfg->native_code, \
2911 MONO_PATCH_INFO_EXC, exc_name); \
2912 x86_branch32 (code, cond, 0, signed); \
2914 EMIT_COND_BRANCH (tins, cond, signed); \
2918 #define EMIT_FPCOMPARE(code) do { \
2919 amd64_fcompp (code); \
2920 amd64_fnstsw (code); \
2923 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2924 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2925 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2926 amd64_ ##op (code); \
2927 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2928 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2932 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2934 gboolean no_patch = FALSE;
2937 * FIXME: Add support for thunks
2940 gboolean near_call = FALSE;
2943 * Indirect calls are expensive so try to make a near call if possible.
2944 * The caller memory is allocated by the code manager so it is
2945 * guaranteed to be at a 32 bit offset.
2948 if (patch_type != MONO_PATCH_INFO_ABS) {
2949 /* The target is in memory allocated using the code manager */
2952 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2953 if (((MonoMethod*)data)->klass->image->aot_module)
2954 /* The callee might be an AOT method */
2956 if (((MonoMethod*)data)->dynamic)
2957 /* The target is in malloc-ed memory */
2961 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2963 * The call might go directly to a native function without
2966 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2968 gconstpointer target = mono_icall_get_wrapper (mi);
2969 if ((((guint64)target) >> 32) != 0)
2975 MonoJumpInfo *jinfo = NULL;
2977 if (cfg->abs_patches)
2978 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2980 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2981 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2982 if (mi && (((guint64)mi->func) >> 32) == 0)
2987 * This is not really an optimization, but required because the
2988 * generic class init trampolines use R11 to pass the vtable.
2993 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2995 if (info->func == info->wrapper) {
2997 if ((((guint64)info->func) >> 32) == 0)
3001 /* See the comment in mono_codegen () */
3002 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3006 else if ((((guint64)data) >> 32) == 0) {
3013 if (cfg->method->dynamic)
3014 /* These methods are allocated using malloc */
3017 #ifdef MONO_ARCH_NOMAP32BIT
3020 #if defined(__native_client__)
3021 /* Always use near_call == TRUE for Native Client */
3024 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3025 if (optimize_for_xen)
3028 if (cfg->compile_aot) {
3035 * Align the call displacement to an address divisible by 4 so it does
3036 * not span cache lines. This is required for code patching to work on SMP
3039 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3040 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3041 amd64_padding (code, pad_size);
3043 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3044 amd64_call_code (code, 0);
3047 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3048 amd64_set_reg_template (code, GP_SCRATCH_REG);
3049 amd64_call_reg (code, GP_SCRATCH_REG);
3056 static inline guint8*
3057 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3060 if (win64_adjust_stack)
3061 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3063 code = emit_call_body (cfg, code, patch_type, data);
3065 if (win64_adjust_stack)
3066 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3073 store_membase_imm_to_store_membase_reg (int opcode)
3076 case OP_STORE_MEMBASE_IMM:
3077 return OP_STORE_MEMBASE_REG;
3078 case OP_STOREI4_MEMBASE_IMM:
3079 return OP_STOREI4_MEMBASE_REG;
3080 case OP_STOREI8_MEMBASE_IMM:
3081 return OP_STOREI8_MEMBASE_REG;
3089 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3092 * mono_arch_peephole_pass_1:
3094 * Perform peephole opts which should/can be performed before local regalloc
3097 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3101 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3102 MonoInst *last_ins = ins->prev;
3104 switch (ins->opcode) {
3108 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3110 * X86_LEA is like ADD, but doesn't have the
3111 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3112 * its operand to 64 bit.
3114 ins->opcode = OP_X86_LEA_MEMBASE;
3115 ins->inst_basereg = ins->sreg1;
3120 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3124 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3125 * the latter has length 2-3 instead of 6 (reverse constant
3126 * propagation). These instruction sequences are very common
3127 * in the initlocals bblock.
3129 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3130 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3131 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3132 ins2->sreg1 = ins->dreg;
3133 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3135 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3144 case OP_COMPARE_IMM:
3145 case OP_LCOMPARE_IMM:
3146 /* OP_COMPARE_IMM (reg, 0)
3148 * OP_AMD64_TEST_NULL (reg)
3151 ins->opcode = OP_AMD64_TEST_NULL;
3153 case OP_ICOMPARE_IMM:
3155 ins->opcode = OP_X86_TEST_NULL;
3157 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3159 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3160 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3162 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3163 * OP_COMPARE_IMM reg, imm
3165 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3167 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3168 ins->inst_basereg == last_ins->inst_destbasereg &&
3169 ins->inst_offset == last_ins->inst_offset) {
3170 ins->opcode = OP_ICOMPARE_IMM;
3171 ins->sreg1 = last_ins->sreg1;
3173 /* check if we can remove cmp reg,0 with test null */
3175 ins->opcode = OP_X86_TEST_NULL;
3181 mono_peephole_ins (bb, ins);
3186 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3190 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3191 switch (ins->opcode) {
3194 /* reg = 0 -> XOR (reg, reg) */
3195 /* XOR sets cflags on x86, so we cant do it always */
3196 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3197 ins->opcode = OP_LXOR;
3198 ins->sreg1 = ins->dreg;
3199 ins->sreg2 = ins->dreg;
3207 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3208 * 0 result into 64 bits.
3210 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3211 ins->opcode = OP_IXOR;
3215 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3219 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3220 * the latter has length 2-3 instead of 6 (reverse constant
3221 * propagation). These instruction sequences are very common
3222 * in the initlocals bblock.
3224 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3225 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3226 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3227 ins2->sreg1 = ins->dreg;
3228 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3230 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3240 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3241 ins->opcode = OP_X86_INC_REG;
3244 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3245 ins->opcode = OP_X86_DEC_REG;
3249 mono_peephole_ins (bb, ins);
3253 #define NEW_INS(cfg,ins,dest,op) do { \
3254 MONO_INST_NEW ((cfg), (dest), (op)); \
3255 (dest)->cil_code = (ins)->cil_code; \
3256 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3260 * mono_arch_lowering_pass:
3262 * Converts complex opcodes into simpler ones so that each IR instruction
3263 * corresponds to one machine instruction.
3266 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3268 MonoInst *ins, *n, *temp;
3271 * FIXME: Need to add more instructions, but the current machine
3272 * description can't model some parts of the composite instructions like
3275 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3276 switch (ins->opcode) {
3280 case OP_IDIV_UN_IMM:
3281 case OP_IREM_UN_IMM:
3282 mono_decompose_op_imm (cfg, bb, ins);
3285 /* Keep the opcode if we can implement it efficiently */
3286 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3287 mono_decompose_op_imm (cfg, bb, ins);
3289 case OP_COMPARE_IMM:
3290 case OP_LCOMPARE_IMM:
3291 if (!amd64_is_imm32 (ins->inst_imm)) {
3292 NEW_INS (cfg, ins, temp, OP_I8CONST);
3293 temp->inst_c0 = ins->inst_imm;
3294 temp->dreg = mono_alloc_ireg (cfg);
3295 ins->opcode = OP_COMPARE;
3296 ins->sreg2 = temp->dreg;
3299 #ifndef __mono_ilp32__
3300 case OP_LOAD_MEMBASE:
3302 case OP_LOADI8_MEMBASE:
3303 #ifndef __native_client_codegen__
3304 /* Don't generate memindex opcodes (to simplify */
3305 /* read sandboxing) */
3306 if (!amd64_is_imm32 (ins->inst_offset)) {
3307 NEW_INS (cfg, ins, temp, OP_I8CONST);
3308 temp->inst_c0 = ins->inst_offset;
3309 temp->dreg = mono_alloc_ireg (cfg);
3310 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3311 ins->inst_indexreg = temp->dreg;
3315 #ifndef __mono_ilp32__
3316 case OP_STORE_MEMBASE_IMM:
3318 case OP_STOREI8_MEMBASE_IMM:
3319 if (!amd64_is_imm32 (ins->inst_imm)) {
3320 NEW_INS (cfg, ins, temp, OP_I8CONST);
3321 temp->inst_c0 = ins->inst_imm;
3322 temp->dreg = mono_alloc_ireg (cfg);
3323 ins->opcode = OP_STOREI8_MEMBASE_REG;
3324 ins->sreg1 = temp->dreg;
3327 #ifdef MONO_ARCH_SIMD_INTRINSICS
3328 case OP_EXPAND_I1: {
3329 int temp_reg1 = mono_alloc_ireg (cfg);
3330 int temp_reg2 = mono_alloc_ireg (cfg);
3331 int original_reg = ins->sreg1;
3333 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3334 temp->sreg1 = original_reg;
3335 temp->dreg = temp_reg1;
3337 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3338 temp->sreg1 = temp_reg1;
3339 temp->dreg = temp_reg2;
3342 NEW_INS (cfg, ins, temp, OP_LOR);
3343 temp->sreg1 = temp->dreg = temp_reg2;
3344 temp->sreg2 = temp_reg1;
3346 ins->opcode = OP_EXPAND_I2;
3347 ins->sreg1 = temp_reg2;
3356 bb->max_vreg = cfg->next_vreg;
3360 branch_cc_table [] = {
3361 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3362 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3363 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3366 /* Maps CMP_... constants to X86_CC_... constants */
3369 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3370 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3374 cc_signed_table [] = {
3375 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3376 FALSE, FALSE, FALSE, FALSE
3379 /*#include "cprop.c"*/
3381 static unsigned char*
3382 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3384 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3387 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3389 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3393 static unsigned char*
3394 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3396 int sreg = tree->sreg1;
3397 int need_touch = FALSE;
3399 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3400 if (!tree->flags & MONO_INST_INIT)
3409 * If requested stack size is larger than one page,
3410 * perform stack-touch operation
3413 * Generate stack probe code.
3414 * Under Windows, it is necessary to allocate one page at a time,
3415 * "touching" stack after each successful sub-allocation. This is
3416 * because of the way stack growth is implemented - there is a
3417 * guard page before the lowest stack page that is currently commited.
3418 * Stack normally grows sequentially so OS traps access to the
3419 * guard page and commits more pages when needed.
3421 amd64_test_reg_imm (code, sreg, ~0xFFF);
3422 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3424 br[2] = code; /* loop */
3425 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3426 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3427 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3428 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3429 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3430 amd64_patch (br[3], br[2]);
3431 amd64_test_reg_reg (code, sreg, sreg);
3432 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3433 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3435 br[1] = code; x86_jump8 (code, 0);
3437 amd64_patch (br[0], code);
3438 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3439 amd64_patch (br[1], code);
3440 amd64_patch (br[4], code);
3443 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3445 if (tree->flags & MONO_INST_INIT) {
3447 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3448 amd64_push_reg (code, AMD64_RAX);
3451 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3452 amd64_push_reg (code, AMD64_RCX);
3455 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3456 amd64_push_reg (code, AMD64_RDI);
3460 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3461 if (sreg != AMD64_RCX)
3462 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3463 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3465 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3466 if (cfg->param_area && cfg->arch.no_pushes)
3467 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3469 #if defined(__default_codegen__)
3470 amd64_prefix (code, X86_REP_PREFIX);
3472 #elif defined(__native_client_codegen__)
3473 /* NaCl stos pseudo-instruction */
3474 amd64_codegen_pre(code);
3475 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3476 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3477 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3478 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3479 amd64_prefix (code, X86_REP_PREFIX);
3481 amd64_codegen_post(code);
3482 #endif /* __native_client_codegen__ */
3484 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3485 amd64_pop_reg (code, AMD64_RDI);
3486 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3487 amd64_pop_reg (code, AMD64_RCX);
3488 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3489 amd64_pop_reg (code, AMD64_RAX);
3495 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3500 /* Move return value to the target register */
3501 /* FIXME: do this in the local reg allocator */
3502 switch (ins->opcode) {
3505 case OP_CALL_MEMBASE:
3508 case OP_LCALL_MEMBASE:
3509 g_assert (ins->dreg == AMD64_RAX);
3513 case OP_FCALL_MEMBASE:
3514 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3515 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3518 if (ins->dreg != AMD64_XMM0)
3519 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3524 case OP_VCALL_MEMBASE:
3527 case OP_VCALL2_MEMBASE:
3528 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3529 if (cinfo->ret.storage == ArgValuetypeInReg) {
3530 MonoInst *loc = cfg->arch.vret_addr_loc;
3532 /* Load the destination address */
3533 g_assert (loc->opcode == OP_REGOFFSET);
3534 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3536 for (quad = 0; quad < 2; quad ++) {
3537 switch (cinfo->ret.pair_storage [quad]) {
3539 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3541 case ArgInFloatSSEReg:
3542 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3544 case ArgInDoubleSSEReg:
3545 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3560 #endif /* DISABLE_JIT */
3563 static int tls_gs_offset;
3567 mono_amd64_have_tls_get (void)
3570 static gboolean have_tls_get = FALSE;
3571 static gboolean inited = FALSE;
3575 return have_tls_get;
3577 ins = (guint8*)pthread_getspecific;
3580 * We're looking for these two instructions:
3582 * mov %gs:[offset](,%rdi,8),%rax
3585 have_tls_get = ins [0] == 0x65 &&
3597 tls_gs_offset = ins[5];
3599 return have_tls_get;
3606 * mono_amd64_emit_tls_get:
3607 * @code: buffer to store code to
3608 * @dreg: hard register where to place the result
3609 * @tls_offset: offset info
3611 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3612 * the dreg register the item in the thread local storage identified
3615 * Returns: a pointer to the end of the stored code
3618 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3621 g_assert (tls_offset < 64);
3622 x86_prefix (code, X86_GS_PREFIX);
3623 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3624 #elif defined(__APPLE__)
3625 x86_prefix (code, X86_GS_PREFIX);
3626 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3628 if (optimize_for_xen) {
3629 x86_prefix (code, X86_FS_PREFIX);
3630 amd64_mov_reg_mem (code, dreg, 0, 8);
3631 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3633 x86_prefix (code, X86_FS_PREFIX);
3634 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3643 * Emit code to initialize an LMF structure at LMF_OFFSET.
3646 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3651 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3654 * sp is saved right before calls but we need to save it here too so
3655 * async stack walks would work.
3657 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3658 /* Skip method (only needed for trampoline LMF frames) */
3659 /* Save callee saved regs */
3660 for (i = 0; i < MONO_MAX_IREGS; ++i) {
3664 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3665 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3666 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3667 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3668 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3669 #ifndef __native_client_codegen__
3670 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3673 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3674 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3682 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3683 if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3684 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3688 /* These can't contain refs */
3689 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3690 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3691 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
3692 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3693 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3695 /* These are handled automatically by the stack marking code */
3696 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3697 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3698 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3699 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3700 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3701 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3703 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3704 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3713 * Emit code to push an LMF structure on the LMF stack.
3716 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3718 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3720 * Optimized version which uses the mono_lmf TLS variable instead of
3721 * indirection through the mono_lmf_addr TLS variable.
3723 /* %rax = previous_lmf */
3724 x86_prefix (code, X86_FS_PREFIX);
3725 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
3727 /* Save previous_lmf */
3728 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
3730 if (lmf_offset == 0) {
3731 x86_prefix (code, X86_FS_PREFIX);
3732 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
3734 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3735 x86_prefix (code, X86_FS_PREFIX);
3736 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3739 if (lmf_addr_tls_offset != -1) {
3740 /* Load lmf quicky using the FS register */
3741 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
3743 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
3744 /* FIXME: Add a separate key for LMF to avoid this */
3745 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3750 * The call might clobber argument registers, but they are already
3751 * saved to the stack/global regs.
3754 *args_clobbered = TRUE;
3755 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3756 (gpointer)"mono_get_lmf_addr", TRUE);
3760 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3761 /* Save previous_lmf */
3762 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3763 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3765 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3766 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3775 * Emit code to pop an LMF structure from the LMF stack.
3778 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3780 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3782 * Optimized version which uses the mono_lmf TLS variable instead of indirection
3783 * through the mono_lmf_addr TLS variable.
3785 /* reg = previous_lmf */
3786 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3787 x86_prefix (code, X86_FS_PREFIX);
3788 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3790 /* Restore previous lmf */
3791 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3792 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3793 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3799 #define REAL_PRINT_REG(text,reg) \
3800 mono_assert (reg >= 0); \
3801 amd64_push_reg (code, AMD64_RAX); \
3802 amd64_push_reg (code, AMD64_RDX); \
3803 amd64_push_reg (code, AMD64_RCX); \
3804 amd64_push_reg (code, reg); \
3805 amd64_push_imm (code, reg); \
3806 amd64_push_imm (code, text " %d %p\n"); \
3807 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3808 amd64_call_reg (code, AMD64_RAX); \
3809 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3810 amd64_pop_reg (code, AMD64_RCX); \
3811 amd64_pop_reg (code, AMD64_RDX); \
3812 amd64_pop_reg (code, AMD64_RAX);
3814 /* benchmark and set based on cpu */
3815 #define LOOP_ALIGNMENT 8
3816 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3820 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3825 guint8 *code = cfg->native_code + cfg->code_len;
3826 MonoInst *last_ins = NULL;
3827 guint last_offset = 0;
3830 /* Fix max_offset estimate for each successor bb */
3831 if (cfg->opt & MONO_OPT_BRANCH) {
3832 int current_offset = cfg->code_len;
3833 MonoBasicBlock *current_bb;
3834 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3835 current_bb->max_offset = current_offset;
3836 current_offset += current_bb->max_length;
3840 if (cfg->opt & MONO_OPT_LOOP) {
3841 int pad, align = LOOP_ALIGNMENT;
3842 /* set alignment depending on cpu */
3843 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3845 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3846 amd64_padding (code, pad);
3847 cfg->code_len += pad;
3848 bb->native_offset = cfg->code_len;
3852 #if defined(__native_client_codegen__)
3853 /* For Native Client, all indirect call/jump targets must be */
3854 /* 32-byte aligned. Exception handler blocks are jumped to */
3855 /* indirectly as well. */
3856 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3857 (bb->flags & BB_EXCEPTION_HANDLER);
3859 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3860 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3861 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3862 cfg->code_len += pad;
3863 bb->native_offset = cfg->code_len;
3865 #endif /*__native_client_codegen__*/
3867 if (cfg->verbose_level > 2)
3868 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3870 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3871 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3872 g_assert (!cfg->compile_aot);
3874 cov->data [bb->dfn].cil_code = bb->cil_code;
3875 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3876 /* this is not thread save, but good enough */
3877 amd64_inc_membase (code, AMD64_R11, 0);
3880 offset = code - cfg->native_code;
3882 mono_debug_open_block (cfg, bb, offset);
3884 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3885 x86_breakpoint (code);
3887 MONO_BB_FOR_EACH_INS (bb, ins) {
3888 offset = code - cfg->native_code;
3890 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3892 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3894 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3895 cfg->code_size *= 2;
3896 cfg->native_code = mono_realloc_native_code(cfg);
3897 code = cfg->native_code + offset;
3898 cfg->stat_code_reallocs++;
3901 if (cfg->debug_info)
3902 mono_debug_record_line_number (cfg, ins, offset);
3904 switch (ins->opcode) {
3906 amd64_mul_reg (code, ins->sreg2, TRUE);
3909 amd64_mul_reg (code, ins->sreg2, FALSE);
3911 case OP_X86_SETEQ_MEMBASE:
3912 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3914 case OP_STOREI1_MEMBASE_IMM:
3915 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3917 case OP_STOREI2_MEMBASE_IMM:
3918 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3920 case OP_STOREI4_MEMBASE_IMM:
3921 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3923 case OP_STOREI1_MEMBASE_REG:
3924 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3926 case OP_STOREI2_MEMBASE_REG:
3927 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3929 /* In AMD64 NaCl, pointers are 4 bytes, */
3930 /* so STORE_* != STOREI8_*. Likewise below. */
3931 case OP_STORE_MEMBASE_REG:
3932 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3934 case OP_STOREI8_MEMBASE_REG:
3935 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3937 case OP_STOREI4_MEMBASE_REG:
3938 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3940 case OP_STORE_MEMBASE_IMM:
3941 #ifndef __native_client_codegen__
3942 /* In NaCl, this could be a PCONST type, which could */
3943 /* mean a pointer type was copied directly into the */
3944 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3945 /* the value would be 0x00000000FFFFFFFF which is */
3946 /* not proper for an imm32 unless you cast it. */
3947 g_assert (amd64_is_imm32 (ins->inst_imm));
3949 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3951 case OP_STOREI8_MEMBASE_IMM:
3952 g_assert (amd64_is_imm32 (ins->inst_imm));
3953 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3956 #ifdef __mono_ilp32__
3957 /* In ILP32, pointers are 4 bytes, so separate these */
3958 /* cases, use literal 8 below where we really want 8 */
3959 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3960 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3964 // FIXME: Decompose this earlier
3965 if (amd64_is_imm32 (ins->inst_imm))
3966 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3968 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3969 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3973 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3974 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3977 // FIXME: Decompose this earlier
3978 if (amd64_is_imm32 (ins->inst_imm))
3979 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3981 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3982 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3986 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3987 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3990 /* For NaCl, pointers are 4 bytes, so separate these */
3991 /* cases, use literal 8 below where we really want 8 */
3992 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3993 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3995 case OP_LOAD_MEMBASE:
3996 g_assert (amd64_is_imm32 (ins->inst_offset));
3997 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3999 case OP_LOADI8_MEMBASE:
4000 /* Use literal 8 instead of sizeof pointer or */
4001 /* register, we really want 8 for this opcode */
4002 g_assert (amd64_is_imm32 (ins->inst_offset));
4003 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4005 case OP_LOADI4_MEMBASE:
4006 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4008 case OP_LOADU4_MEMBASE:
4009 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4011 case OP_LOADU1_MEMBASE:
4012 /* The cpu zero extends the result into 64 bits */
4013 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4015 case OP_LOADI1_MEMBASE:
4016 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4018 case OP_LOADU2_MEMBASE:
4019 /* The cpu zero extends the result into 64 bits */
4020 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4022 case OP_LOADI2_MEMBASE:
4023 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4025 case OP_AMD64_LOADI8_MEMINDEX:
4026 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4028 case OP_LCONV_TO_I1:
4029 case OP_ICONV_TO_I1:
4031 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4033 case OP_LCONV_TO_I2:
4034 case OP_ICONV_TO_I2:
4036 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4038 case OP_LCONV_TO_U1:
4039 case OP_ICONV_TO_U1:
4040 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4042 case OP_LCONV_TO_U2:
4043 case OP_ICONV_TO_U2:
4044 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4047 /* Clean out the upper word */
4048 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4051 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4055 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4057 case OP_COMPARE_IMM:
4058 #if defined(__mono_ilp32__)
4059 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4060 g_assert (amd64_is_imm32 (ins->inst_imm));
4061 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4064 case OP_LCOMPARE_IMM:
4065 g_assert (amd64_is_imm32 (ins->inst_imm));
4066 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4068 case OP_X86_COMPARE_REG_MEMBASE:
4069 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4071 case OP_X86_TEST_NULL:
4072 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4074 case OP_AMD64_TEST_NULL:
4075 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4078 case OP_X86_ADD_REG_MEMBASE:
4079 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4081 case OP_X86_SUB_REG_MEMBASE:
4082 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4084 case OP_X86_AND_REG_MEMBASE:
4085 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4087 case OP_X86_OR_REG_MEMBASE:
4088 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4090 case OP_X86_XOR_REG_MEMBASE:
4091 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4094 case OP_X86_ADD_MEMBASE_IMM:
4095 /* FIXME: Make a 64 version too */
4096 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4098 case OP_X86_SUB_MEMBASE_IMM:
4099 g_assert (amd64_is_imm32 (ins->inst_imm));
4100 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4102 case OP_X86_AND_MEMBASE_IMM:
4103 g_assert (amd64_is_imm32 (ins->inst_imm));
4104 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4106 case OP_X86_OR_MEMBASE_IMM:
4107 g_assert (amd64_is_imm32 (ins->inst_imm));
4108 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4110 case OP_X86_XOR_MEMBASE_IMM:
4111 g_assert (amd64_is_imm32 (ins->inst_imm));
4112 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4114 case OP_X86_ADD_MEMBASE_REG:
4115 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4117 case OP_X86_SUB_MEMBASE_REG:
4118 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4120 case OP_X86_AND_MEMBASE_REG:
4121 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4123 case OP_X86_OR_MEMBASE_REG:
4124 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4126 case OP_X86_XOR_MEMBASE_REG:
4127 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4129 case OP_X86_INC_MEMBASE:
4130 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4132 case OP_X86_INC_REG:
4133 amd64_inc_reg_size (code, ins->dreg, 4);
4135 case OP_X86_DEC_MEMBASE:
4136 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4138 case OP_X86_DEC_REG:
4139 amd64_dec_reg_size (code, ins->dreg, 4);
4141 case OP_X86_MUL_REG_MEMBASE:
4142 case OP_X86_MUL_MEMBASE_REG:
4143 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4145 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4146 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4148 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4149 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4151 case OP_AMD64_COMPARE_MEMBASE_REG:
4152 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4154 case OP_AMD64_COMPARE_MEMBASE_IMM:
4155 g_assert (amd64_is_imm32 (ins->inst_imm));
4156 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4158 case OP_X86_COMPARE_MEMBASE8_IMM:
4159 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4161 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4162 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4164 case OP_AMD64_COMPARE_REG_MEMBASE:
4165 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4168 case OP_AMD64_ADD_REG_MEMBASE:
4169 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4171 case OP_AMD64_SUB_REG_MEMBASE:
4172 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4174 case OP_AMD64_AND_REG_MEMBASE:
4175 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4177 case OP_AMD64_OR_REG_MEMBASE:
4178 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4180 case OP_AMD64_XOR_REG_MEMBASE:
4181 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4184 case OP_AMD64_ADD_MEMBASE_REG:
4185 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4187 case OP_AMD64_SUB_MEMBASE_REG:
4188 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4190 case OP_AMD64_AND_MEMBASE_REG:
4191 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4193 case OP_AMD64_OR_MEMBASE_REG:
4194 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4196 case OP_AMD64_XOR_MEMBASE_REG:
4197 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4200 case OP_AMD64_ADD_MEMBASE_IMM:
4201 g_assert (amd64_is_imm32 (ins->inst_imm));
4202 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4204 case OP_AMD64_SUB_MEMBASE_IMM:
4205 g_assert (amd64_is_imm32 (ins->inst_imm));
4206 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4208 case OP_AMD64_AND_MEMBASE_IMM:
4209 g_assert (amd64_is_imm32 (ins->inst_imm));
4210 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4212 case OP_AMD64_OR_MEMBASE_IMM:
4213 g_assert (amd64_is_imm32 (ins->inst_imm));
4214 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4216 case OP_AMD64_XOR_MEMBASE_IMM:
4217 g_assert (amd64_is_imm32 (ins->inst_imm));
4218 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4222 amd64_breakpoint (code);
4224 case OP_RELAXED_NOP:
4225 x86_prefix (code, X86_REP_PREFIX);
4233 case OP_DUMMY_STORE:
4234 case OP_NOT_REACHED:
4237 case OP_SEQ_POINT: {
4241 * Read from the single stepping trigger page. This will cause a
4242 * SIGSEGV when single stepping is enabled.
4243 * We do this _before_ the breakpoint, so single stepping after
4244 * a breakpoint is hit will step to the next IL offset.
4246 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4247 MonoInst *var = cfg->arch.ss_trigger_page_var;
4249 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4250 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4254 * This is the address which is saved in seq points,
4256 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4258 if (cfg->compile_aot) {
4259 guint32 offset = code - cfg->native_code;
4261 MonoInst *info_var = cfg->arch.seq_point_info_var;
4264 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4265 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4266 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4267 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4268 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4271 * A placeholder for a possible breakpoint inserted by
4272 * mono_arch_set_breakpoint ().
4274 for (i = 0; i < breakpoint_size; ++i)
4278 * Add an additional nop so skipping the bp doesn't cause the ip to point
4279 * to another IL offset.
4287 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4290 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4294 g_assert (amd64_is_imm32 (ins->inst_imm));
4295 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4298 g_assert (amd64_is_imm32 (ins->inst_imm));
4299 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4304 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4307 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4311 g_assert (amd64_is_imm32 (ins->inst_imm));
4312 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4315 g_assert (amd64_is_imm32 (ins->inst_imm));
4316 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4319 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4323 g_assert (amd64_is_imm32 (ins->inst_imm));
4324 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4327 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4332 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4334 switch (ins->inst_imm) {
4338 if (ins->dreg != ins->sreg1)
4339 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4340 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4343 /* LEA r1, [r2 + r2*2] */
4344 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4347 /* LEA r1, [r2 + r2*4] */
4348 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4351 /* LEA r1, [r2 + r2*2] */
4353 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4354 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4357 /* LEA r1, [r2 + r2*8] */
4358 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4361 /* LEA r1, [r2 + r2*4] */
4363 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4364 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4367 /* LEA r1, [r2 + r2*2] */
4369 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4370 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4373 /* LEA r1, [r2 + r2*4] */
4374 /* LEA r1, [r1 + r1*4] */
4375 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4376 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4379 /* LEA r1, [r2 + r2*4] */
4381 /* LEA r1, [r1 + r1*4] */
4382 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4383 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4384 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4387 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4394 #if defined( __native_client_codegen__ )
4395 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4396 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4398 /* Regalloc magic makes the div/rem cases the same */
4399 if (ins->sreg2 == AMD64_RDX) {
4400 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4402 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4405 amd64_div_reg (code, ins->sreg2, TRUE);
4410 #if defined( __native_client_codegen__ )
4411 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4412 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4414 if (ins->sreg2 == AMD64_RDX) {
4415 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4416 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4417 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4419 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4420 amd64_div_reg (code, ins->sreg2, FALSE);
4425 #if defined( __native_client_codegen__ )
4426 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4427 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4429 if (ins->sreg2 == AMD64_RDX) {
4430 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4431 amd64_cdq_size (code, 4);
4432 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4434 amd64_cdq_size (code, 4);
4435 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4440 #if defined( __native_client_codegen__ )
4441 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4442 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4444 if (ins->sreg2 == AMD64_RDX) {
4445 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4446 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4447 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4449 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4450 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4454 int power = mono_is_power_of_two (ins->inst_imm);
4456 g_assert (ins->sreg1 == X86_EAX);
4457 g_assert (ins->dreg == X86_EAX);
4458 g_assert (power >= 0);
4461 amd64_mov_reg_imm (code, ins->dreg, 0);
4465 /* Based on gcc code */
4467 /* Add compensation for negative dividents */
4468 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4470 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4471 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4472 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4473 /* Compute remainder */
4474 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4475 /* Remove compensation */
4476 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4480 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4481 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4484 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4488 g_assert (amd64_is_imm32 (ins->inst_imm));
4489 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4492 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4496 g_assert (amd64_is_imm32 (ins->inst_imm));
4497 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4500 g_assert (ins->sreg2 == AMD64_RCX);
4501 amd64_shift_reg (code, X86_SHL, ins->dreg);
4504 g_assert (ins->sreg2 == AMD64_RCX);
4505 amd64_shift_reg (code, X86_SAR, ins->dreg);
4508 g_assert (amd64_is_imm32 (ins->inst_imm));
4509 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4512 g_assert (amd64_is_imm32 (ins->inst_imm));
4513 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4516 g_assert (amd64_is_imm32 (ins->inst_imm));
4517 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4519 case OP_LSHR_UN_IMM:
4520 g_assert (amd64_is_imm32 (ins->inst_imm));
4521 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4524 g_assert (ins->sreg2 == AMD64_RCX);
4525 amd64_shift_reg (code, X86_SHR, ins->dreg);
4528 g_assert (amd64_is_imm32 (ins->inst_imm));
4529 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4532 g_assert (amd64_is_imm32 (ins->inst_imm));
4533 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4538 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4541 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4544 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4547 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4551 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4554 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4557 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4560 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4563 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4566 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4569 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4572 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4575 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4578 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4581 amd64_neg_reg_size (code, ins->sreg1, 4);
4584 amd64_not_reg_size (code, ins->sreg1, 4);
4587 g_assert (ins->sreg2 == AMD64_RCX);
4588 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4591 g_assert (ins->sreg2 == AMD64_RCX);
4592 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4595 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4597 case OP_ISHR_UN_IMM:
4598 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4601 g_assert (ins->sreg2 == AMD64_RCX);
4602 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4605 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4608 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4611 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4612 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4614 case OP_IMUL_OVF_UN:
4615 case OP_LMUL_OVF_UN: {
4616 /* the mul operation and the exception check should most likely be split */
4617 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4618 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4619 /*g_assert (ins->sreg2 == X86_EAX);
4620 g_assert (ins->dreg == X86_EAX);*/
4621 if (ins->sreg2 == X86_EAX) {
4622 non_eax_reg = ins->sreg1;
4623 } else if (ins->sreg1 == X86_EAX) {
4624 non_eax_reg = ins->sreg2;
4626 /* no need to save since we're going to store to it anyway */
4627 if (ins->dreg != X86_EAX) {
4629 amd64_push_reg (code, X86_EAX);
4631 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4632 non_eax_reg = ins->sreg2;
4634 if (ins->dreg == X86_EDX) {
4637 amd64_push_reg (code, X86_EAX);
4641 amd64_push_reg (code, X86_EDX);
4643 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4644 /* save before the check since pop and mov don't change the flags */
4645 if (ins->dreg != X86_EAX)
4646 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4648 amd64_pop_reg (code, X86_EDX);
4650 amd64_pop_reg (code, X86_EAX);
4651 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4655 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4657 case OP_ICOMPARE_IMM:
4658 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4680 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4688 case OP_CMOV_INE_UN:
4689 case OP_CMOV_IGE_UN:
4690 case OP_CMOV_IGT_UN:
4691 case OP_CMOV_ILE_UN:
4692 case OP_CMOV_ILT_UN:
4698 case OP_CMOV_LNE_UN:
4699 case OP_CMOV_LGE_UN:
4700 case OP_CMOV_LGT_UN:
4701 case OP_CMOV_LLE_UN:
4702 case OP_CMOV_LLT_UN:
4703 g_assert (ins->dreg == ins->sreg1);
4704 /* This needs to operate on 64 bit values */
4705 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4709 amd64_not_reg (code, ins->sreg1);
4712 amd64_neg_reg (code, ins->sreg1);
4717 if ((((guint64)ins->inst_c0) >> 32) == 0)
4718 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4720 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4723 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4724 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4727 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4728 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4731 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4733 case OP_AMD64_SET_XMMREG_R4: {
4734 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4737 case OP_AMD64_SET_XMMREG_R8: {
4738 if (ins->dreg != ins->sreg1)
4739 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4743 MonoCallInst *call = (MonoCallInst*)ins;
4746 /* FIXME: no tracing support... */
4747 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4748 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, TRUE);
4750 g_assert (!cfg->method->save_lmf);
4752 if (cfg->arch.omit_fp) {
4753 guint32 save_offset = 0;
4754 /* Pop callee-saved registers */
4755 for (i = 0; i < AMD64_NREG; ++i)
4756 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4757 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4760 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4763 if (call->stack_usage)
4767 for (i = 0; i < AMD64_NREG; ++i)
4768 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4769 pos -= sizeof(mgreg_t);
4771 /* Restore callee-saved registers */
4772 for (i = AMD64_NREG - 1; i > 0; --i) {
4773 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4774 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, sizeof(mgreg_t));
4775 pos += sizeof(mgreg_t);
4779 /* Copy arguments on the stack to our argument area */
4780 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4781 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4782 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4786 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4791 offset = code - cfg->native_code;
4792 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4793 if (cfg->compile_aot)
4794 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4796 amd64_set_reg_template (code, AMD64_R11);
4797 amd64_jump_reg (code, AMD64_R11);
4798 ins->flags |= MONO_INST_GC_CALLSITE;
4799 ins->backend.pc_offset = code - cfg->native_code;
4803 /* ensure ins->sreg1 is not NULL */
4804 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4807 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4808 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4817 call = (MonoCallInst*)ins;
4819 * The AMD64 ABI forces callers to know about varargs.
4821 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4822 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4823 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4825 * Since the unmanaged calling convention doesn't contain a
4826 * 'vararg' entry, we have to treat every pinvoke call as a
4827 * potential vararg call.
4831 for (i = 0; i < AMD64_XMM_NREG; ++i)
4832 if (call->used_fregs & (1 << i))
4835 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4837 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4840 if (ins->flags & MONO_INST_HAS_METHOD)
4841 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4843 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4844 ins->flags |= MONO_INST_GC_CALLSITE;
4845 ins->backend.pc_offset = code - cfg->native_code;
4846 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4847 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4848 code = emit_move_return_value (cfg, ins, code);
4854 case OP_VOIDCALL_REG:
4856 call = (MonoCallInst*)ins;
4858 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4859 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4860 ins->sreg1 = AMD64_R11;
4864 * The AMD64 ABI forces callers to know about varargs.
4866 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4867 if (ins->sreg1 == AMD64_RAX) {
4868 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4869 ins->sreg1 = AMD64_R11;
4871 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4872 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4874 * Since the unmanaged calling convention doesn't contain a
4875 * 'vararg' entry, we have to treat every pinvoke call as a
4876 * potential vararg call.
4880 for (i = 0; i < AMD64_XMM_NREG; ++i)
4881 if (call->used_fregs & (1 << i))
4883 if (ins->sreg1 == AMD64_RAX) {
4884 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4885 ins->sreg1 = AMD64_R11;
4888 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4890 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4893 amd64_call_reg (code, ins->sreg1);
4894 ins->flags |= MONO_INST_GC_CALLSITE;
4895 ins->backend.pc_offset = code - cfg->native_code;
4896 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4897 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4898 code = emit_move_return_value (cfg, ins, code);
4900 case OP_FCALL_MEMBASE:
4901 case OP_LCALL_MEMBASE:
4902 case OP_VCALL_MEMBASE:
4903 case OP_VCALL2_MEMBASE:
4904 case OP_VOIDCALL_MEMBASE:
4905 case OP_CALL_MEMBASE:
4906 call = (MonoCallInst*)ins;
4908 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4909 ins->flags |= MONO_INST_GC_CALLSITE;
4910 ins->backend.pc_offset = code - cfg->native_code;
4911 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4912 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4913 code = emit_move_return_value (cfg, ins, code);
4917 MonoInst *var = cfg->dyn_call_var;
4919 g_assert (var->opcode == OP_REGOFFSET);
4921 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4922 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4924 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4926 /* Save args buffer */
4927 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4929 /* Set argument registers */
4930 for (i = 0; i < PARAM_REGS; ++i)
4931 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4934 amd64_call_reg (code, AMD64_R10);
4936 ins->flags |= MONO_INST_GC_CALLSITE;
4937 ins->backend.pc_offset = code - cfg->native_code;
4940 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4941 amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4944 case OP_AMD64_SAVE_SP_TO_LMF: {
4945 MonoInst *lmf_var = cfg->arch.lmf_var;
4946 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4950 g_assert (!cfg->arch.no_pushes);
4951 amd64_push_reg (code, ins->sreg1);
4953 case OP_X86_PUSH_IMM:
4954 g_assert (!cfg->arch.no_pushes);
4955 g_assert (amd64_is_imm32 (ins->inst_imm));
4956 amd64_push_imm (code, ins->inst_imm);
4958 case OP_X86_PUSH_MEMBASE:
4959 g_assert (!cfg->arch.no_pushes);
4960 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4962 case OP_X86_PUSH_OBJ: {
4963 int size = ALIGN_TO (ins->inst_imm, 8);
4965 g_assert (!cfg->arch.no_pushes);
4967 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4968 amd64_push_reg (code, AMD64_RDI);
4969 amd64_push_reg (code, AMD64_RSI);
4970 amd64_push_reg (code, AMD64_RCX);
4971 if (ins->inst_offset)
4972 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4974 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4975 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4976 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4978 amd64_prefix (code, X86_REP_PREFIX);
4980 amd64_pop_reg (code, AMD64_RCX);
4981 amd64_pop_reg (code, AMD64_RSI);
4982 amd64_pop_reg (code, AMD64_RDI);
4986 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4988 case OP_X86_LEA_MEMBASE:
4989 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4992 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4995 /* keep alignment */
4996 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4997 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4998 code = mono_emit_stack_alloc (cfg, code, ins);
4999 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5000 if (cfg->param_area && cfg->arch.no_pushes)
5001 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5003 case OP_LOCALLOC_IMM: {
5004 guint32 size = ins->inst_imm;
5005 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5007 if (ins->flags & MONO_INST_INIT) {
5011 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5012 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5014 for (i = 0; i < size; i += 8)
5015 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5016 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5018 amd64_mov_reg_imm (code, ins->dreg, size);
5019 ins->sreg1 = ins->dreg;
5021 code = mono_emit_stack_alloc (cfg, code, ins);
5022 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5025 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5026 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5028 if (cfg->param_area && cfg->arch.no_pushes)
5029 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5033 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5034 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5035 (gpointer)"mono_arch_throw_exception", FALSE);
5036 ins->flags |= MONO_INST_GC_CALLSITE;
5037 ins->backend.pc_offset = code - cfg->native_code;
5041 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5042 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5043 (gpointer)"mono_arch_rethrow_exception", FALSE);
5044 ins->flags |= MONO_INST_GC_CALLSITE;
5045 ins->backend.pc_offset = code - cfg->native_code;
5048 case OP_CALL_HANDLER:
5050 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5051 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5052 amd64_call_imm (code, 0);
5053 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5054 /* Restore stack alignment */
5055 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5057 case OP_START_HANDLER: {
5058 /* Even though we're saving RSP, use sizeof */
5059 /* gpointer because spvar is of type IntPtr */
5060 /* see: mono_create_spvar_for_region */
5061 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5062 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5064 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5065 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5066 cfg->param_area && cfg->arch.no_pushes) {
5067 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5071 case OP_ENDFINALLY: {
5072 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5073 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5077 case OP_ENDFILTER: {
5078 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5079 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5080 /* The local allocator will put the result into RAX */
5086 ins->inst_c0 = code - cfg->native_code;
5089 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5090 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5092 if (ins->inst_target_bb->native_offset) {
5093 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5095 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5096 if ((cfg->opt & MONO_OPT_BRANCH) &&
5097 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5098 x86_jump8 (code, 0);
5100 x86_jump32 (code, 0);
5104 amd64_jump_reg (code, ins->sreg1);
5121 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5122 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5124 case OP_COND_EXC_EQ:
5125 case OP_COND_EXC_NE_UN:
5126 case OP_COND_EXC_LT:
5127 case OP_COND_EXC_LT_UN:
5128 case OP_COND_EXC_GT:
5129 case OP_COND_EXC_GT_UN:
5130 case OP_COND_EXC_GE:
5131 case OP_COND_EXC_GE_UN:
5132 case OP_COND_EXC_LE:
5133 case OP_COND_EXC_LE_UN:
5134 case OP_COND_EXC_IEQ:
5135 case OP_COND_EXC_INE_UN:
5136 case OP_COND_EXC_ILT:
5137 case OP_COND_EXC_ILT_UN:
5138 case OP_COND_EXC_IGT:
5139 case OP_COND_EXC_IGT_UN:
5140 case OP_COND_EXC_IGE:
5141 case OP_COND_EXC_IGE_UN:
5142 case OP_COND_EXC_ILE:
5143 case OP_COND_EXC_ILE_UN:
5144 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5146 case OP_COND_EXC_OV:
5147 case OP_COND_EXC_NO:
5149 case OP_COND_EXC_NC:
5150 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5151 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5153 case OP_COND_EXC_IOV:
5154 case OP_COND_EXC_INO:
5155 case OP_COND_EXC_IC:
5156 case OP_COND_EXC_INC:
5157 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5158 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5161 /* floating point opcodes */
5163 double d = *(double *)ins->inst_p0;
5165 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5166 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5169 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5170 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5175 float f = *(float *)ins->inst_p0;
5177 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5178 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5181 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5182 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5183 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5187 case OP_STORER8_MEMBASE_REG:
5188 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5190 case OP_LOADR8_MEMBASE:
5191 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5193 case OP_STORER4_MEMBASE_REG:
5194 /* This requires a double->single conversion */
5195 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5196 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5198 case OP_LOADR4_MEMBASE:
5199 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5200 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5202 case OP_ICONV_TO_R4: /* FIXME: change precision */
5203 case OP_ICONV_TO_R8:
5204 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5206 case OP_LCONV_TO_R4: /* FIXME: change precision */
5207 case OP_LCONV_TO_R8:
5208 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5210 case OP_FCONV_TO_R4:
5211 /* FIXME: nothing to do ?? */
5213 case OP_FCONV_TO_I1:
5214 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5216 case OP_FCONV_TO_U1:
5217 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5219 case OP_FCONV_TO_I2:
5220 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5222 case OP_FCONV_TO_U2:
5223 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5225 case OP_FCONV_TO_U4:
5226 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5228 case OP_FCONV_TO_I4:
5230 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5232 case OP_FCONV_TO_I8:
5233 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5235 case OP_LCONV_TO_R_UN: {
5238 /* Based on gcc code */
5239 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5240 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5243 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5244 br [1] = code; x86_jump8 (code, 0);
5245 amd64_patch (br [0], code);
5248 /* Save to the red zone */
5249 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5250 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5251 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5252 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5253 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5254 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5255 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5256 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5257 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5259 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5260 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5261 amd64_patch (br [1], code);
5264 case OP_LCONV_TO_OVF_U4:
5265 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5266 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5267 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5269 case OP_LCONV_TO_OVF_I4_UN:
5270 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5271 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5272 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5275 if (ins->dreg != ins->sreg1)
5276 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5279 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5282 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5285 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5288 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5291 static double r8_0 = -0.0;
5293 g_assert (ins->sreg1 == ins->dreg);
5295 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5296 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5300 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5303 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5306 static guint64 d = 0x7fffffffffffffffUL;
5308 g_assert (ins->sreg1 == ins->dreg);
5310 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5311 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5315 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5318 g_assert (cfg->opt & MONO_OPT_CMOV);
5319 g_assert (ins->dreg == ins->sreg1);
5320 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5321 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5324 g_assert (cfg->opt & MONO_OPT_CMOV);
5325 g_assert (ins->dreg == ins->sreg1);
5326 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5327 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5330 g_assert (cfg->opt & MONO_OPT_CMOV);
5331 g_assert (ins->dreg == ins->sreg1);
5332 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5333 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5336 g_assert (cfg->opt & MONO_OPT_CMOV);
5337 g_assert (ins->dreg == ins->sreg1);
5338 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5339 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5342 g_assert (cfg->opt & MONO_OPT_CMOV);
5343 g_assert (ins->dreg == ins->sreg1);
5344 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5345 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5348 g_assert (cfg->opt & MONO_OPT_CMOV);
5349 g_assert (ins->dreg == ins->sreg1);
5350 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5351 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5354 g_assert (cfg->opt & MONO_OPT_CMOV);
5355 g_assert (ins->dreg == ins->sreg1);
5356 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5357 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5360 g_assert (cfg->opt & MONO_OPT_CMOV);
5361 g_assert (ins->dreg == ins->sreg1);
5362 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5363 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5369 * The two arguments are swapped because the fbranch instructions
5370 * depend on this for the non-sse case to work.
5372 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5375 /* zeroing the register at the start results in
5376 * shorter and faster code (we can also remove the widening op)
5378 guchar *unordered_check;
5379 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5380 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5381 unordered_check = code;
5382 x86_branch8 (code, X86_CC_P, 0, FALSE);
5383 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5384 amd64_patch (unordered_check, code);
5389 /* zeroing the register at the start results in
5390 * shorter and faster code (we can also remove the widening op)
5392 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5393 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5394 if (ins->opcode == OP_FCLT_UN) {
5395 guchar *unordered_check = code;
5396 guchar *jump_to_end;
5397 x86_branch8 (code, X86_CC_P, 0, FALSE);
5398 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5400 x86_jump8 (code, 0);
5401 amd64_patch (unordered_check, code);
5402 amd64_inc_reg (code, ins->dreg);
5403 amd64_patch (jump_to_end, code);
5405 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5410 /* zeroing the register at the start results in
5411 * shorter and faster code (we can also remove the widening op)
5413 guchar *unordered_check;
5414 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5415 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5416 if (ins->opcode == OP_FCGT) {
5417 unordered_check = code;
5418 x86_branch8 (code, X86_CC_P, 0, FALSE);
5419 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5420 amd64_patch (unordered_check, code);
5422 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5426 case OP_FCLT_MEMBASE:
5427 case OP_FCGT_MEMBASE:
5428 case OP_FCLT_UN_MEMBASE:
5429 case OP_FCGT_UN_MEMBASE:
5430 case OP_FCEQ_MEMBASE: {
5431 guchar *unordered_check, *jump_to_end;
5434 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5435 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5437 switch (ins->opcode) {
5438 case OP_FCEQ_MEMBASE:
5439 x86_cond = X86_CC_EQ;
5441 case OP_FCLT_MEMBASE:
5442 case OP_FCLT_UN_MEMBASE:
5443 x86_cond = X86_CC_LT;
5445 case OP_FCGT_MEMBASE:
5446 case OP_FCGT_UN_MEMBASE:
5447 x86_cond = X86_CC_GT;
5450 g_assert_not_reached ();
5453 unordered_check = code;
5454 x86_branch8 (code, X86_CC_P, 0, FALSE);
5455 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5457 switch (ins->opcode) {
5458 case OP_FCEQ_MEMBASE:
5459 case OP_FCLT_MEMBASE:
5460 case OP_FCGT_MEMBASE:
5461 amd64_patch (unordered_check, code);
5463 case OP_FCLT_UN_MEMBASE:
5464 case OP_FCGT_UN_MEMBASE:
5466 x86_jump8 (code, 0);
5467 amd64_patch (unordered_check, code);
5468 amd64_inc_reg (code, ins->dreg);
5469 amd64_patch (jump_to_end, code);
5477 guchar *jump = code;
5478 x86_branch8 (code, X86_CC_P, 0, TRUE);
5479 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5480 amd64_patch (jump, code);
5484 /* Branch if C013 != 100 */
5485 /* branch if !ZF or (PF|CF) */
5486 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5487 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5488 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5491 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5494 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5495 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5499 if (ins->opcode == OP_FBGT) {
5502 /* skip branch if C1=1 */
5504 x86_branch8 (code, X86_CC_P, 0, FALSE);
5505 /* branch if (C0 | C3) = 1 */
5506 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5507 amd64_patch (br1, code);
5510 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5514 /* Branch if C013 == 100 or 001 */
5517 /* skip branch if C1=1 */
5519 x86_branch8 (code, X86_CC_P, 0, FALSE);
5520 /* branch if (C0 | C3) = 1 */
5521 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5522 amd64_patch (br1, code);
5526 /* Branch if C013 == 000 */
5527 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5530 /* Branch if C013=000 or 100 */
5533 /* skip branch if C1=1 */
5535 x86_branch8 (code, X86_CC_P, 0, FALSE);
5536 /* branch if C0=0 */
5537 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5538 amd64_patch (br1, code);
5542 /* Branch if C013 != 001 */
5543 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5544 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5547 /* Transfer value to the fp stack */
5548 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5549 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5550 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5552 amd64_push_reg (code, AMD64_RAX);
5554 amd64_fnstsw (code);
5555 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5556 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5557 amd64_pop_reg (code, AMD64_RAX);
5558 amd64_fstp (code, 0);
5559 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5560 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5563 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5566 case OP_TLS_GET_REG:
5568 // FIXME: tls_gs_offset can change too, do these when calculating the tls offset
5569 if (ins->dreg != ins->sreg1)
5570 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
5571 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 3);
5573 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, tls_gs_offset);
5574 x86_prefix (code, X86_GS_PREFIX);
5575 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof (gpointer));
5577 g_assert_not_reached ();
5580 case OP_MEMORY_BARRIER: {
5581 switch (ins->backend.memory_barrier_kind) {
5582 case StoreLoadBarrier:
5584 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5585 x86_prefix (code, X86_LOCK_PREFIX);
5586 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5591 case OP_ATOMIC_ADD_I4:
5592 case OP_ATOMIC_ADD_I8: {
5593 int dreg = ins->dreg;
5594 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5596 if (dreg == ins->inst_basereg)
5599 if (dreg != ins->sreg2)
5600 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5602 x86_prefix (code, X86_LOCK_PREFIX);
5603 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5605 if (dreg != ins->dreg)
5606 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5610 case OP_ATOMIC_ADD_NEW_I4:
5611 case OP_ATOMIC_ADD_NEW_I8: {
5612 int dreg = ins->dreg;
5613 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5615 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5618 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5619 amd64_prefix (code, X86_LOCK_PREFIX);
5620 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5621 /* dreg contains the old value, add with sreg2 value */
5622 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5624 if (ins->dreg != dreg)
5625 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5629 case OP_ATOMIC_EXCHANGE_I4:
5630 case OP_ATOMIC_EXCHANGE_I8: {
5632 int sreg2 = ins->sreg2;
5633 int breg = ins->inst_basereg;
5635 gboolean need_push = FALSE, rdx_pushed = FALSE;
5637 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5643 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5644 * an explanation of how this works.
5647 /* cmpxchg uses eax as comperand, need to make sure we can use it
5648 * hack to overcome limits in x86 reg allocator
5649 * (req: dreg == eax and sreg2 != eax and breg != eax)
5651 g_assert (ins->dreg == AMD64_RAX);
5653 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5654 /* Highly unlikely, but possible */
5657 /* The pushes invalidate rsp */
5658 if ((breg == AMD64_RAX) || need_push) {
5659 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5663 /* We need the EAX reg for the comparand */
5664 if (ins->sreg2 == AMD64_RAX) {
5665 if (breg != AMD64_R11) {
5666 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5669 g_assert (need_push);
5670 amd64_push_reg (code, AMD64_RDX);
5671 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5677 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5679 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5680 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5681 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5682 amd64_patch (br [1], br [0]);
5685 amd64_pop_reg (code, AMD64_RDX);
5689 case OP_ATOMIC_CAS_I4:
5690 case OP_ATOMIC_CAS_I8: {
5693 if (ins->opcode == OP_ATOMIC_CAS_I8)
5699 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5700 * an explanation of how this works.
5702 g_assert (ins->sreg3 == AMD64_RAX);
5703 g_assert (ins->sreg1 != AMD64_RAX);
5704 g_assert (ins->sreg1 != ins->sreg2);
5706 amd64_prefix (code, X86_LOCK_PREFIX);
5707 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5709 if (ins->dreg != AMD64_RAX)
5710 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5713 case OP_CARD_TABLE_WBARRIER: {
5714 int ptr = ins->sreg1;
5715 int value = ins->sreg2;
5717 int nursery_shift, card_table_shift;
5718 gpointer card_table_mask;
5719 size_t nursery_size;
5721 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5722 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5723 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5725 /*If either point to the stack we can simply avoid the WB. This happens due to
5726 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5728 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5732 * We need one register we can clobber, we choose EDX and make sreg1
5733 * fixed EAX to work around limitations in the local register allocator.
5734 * sreg2 might get allocated to EDX, but that is not a problem since
5735 * we use it before clobbering EDX.
5737 g_assert (ins->sreg1 == AMD64_RAX);
5740 * This is the code we produce:
5743 * edx >>= nursery_shift
5744 * cmp edx, (nursery_start >> nursery_shift)
5747 * edx >>= card_table_shift
5753 if (mono_gc_card_table_nursery_check ()) {
5754 if (value != AMD64_RDX)
5755 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5756 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5757 if (shifted_nursery_start >> 31) {
5759 * The value we need to compare against is 64 bits, so we need
5760 * another spare register. We use RBX, which we save and
5763 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5764 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5765 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5766 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5768 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5770 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5772 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5773 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5774 if (card_table_mask)
5775 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5777 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5778 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5780 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5782 if (mono_gc_card_table_nursery_check ())
5783 x86_patch (br, code);
5786 #ifdef MONO_ARCH_SIMD_INTRINSICS
5787 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5789 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5792 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5795 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5798 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5801 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5804 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5807 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5808 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5811 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5814 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5817 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5820 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5823 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5826 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5829 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5832 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5835 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5838 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5841 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5844 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5847 case OP_PSHUFLEW_HIGH:
5848 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5849 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5851 case OP_PSHUFLEW_LOW:
5852 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5853 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5856 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5857 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5860 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5861 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5864 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5865 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5869 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5872 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5875 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5878 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5881 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5884 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5887 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5888 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5891 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5894 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5897 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5900 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5903 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5906 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5909 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5912 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5915 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5918 case OP_EXTRACT_MASK:
5919 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5923 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5926 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5929 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5933 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5936 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5939 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5942 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5946 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5949 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5952 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5955 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5959 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5962 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5965 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5969 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5972 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5975 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5979 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5982 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5986 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5989 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5992 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5996 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5999 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6002 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6006 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6009 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6015 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6019 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6022 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6025 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6028 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6031 case OP_PSUM_ABS_DIFF:
6032 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6035 case OP_UNPACK_LOWB:
6036 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6038 case OP_UNPACK_LOWW:
6039 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6041 case OP_UNPACK_LOWD:
6042 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6044 case OP_UNPACK_LOWQ:
6045 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6047 case OP_UNPACK_LOWPS:
6048 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6050 case OP_UNPACK_LOWPD:
6051 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6054 case OP_UNPACK_HIGHB:
6055 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6057 case OP_UNPACK_HIGHW:
6058 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6060 case OP_UNPACK_HIGHD:
6061 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6063 case OP_UNPACK_HIGHQ:
6064 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6066 case OP_UNPACK_HIGHPS:
6067 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6069 case OP_UNPACK_HIGHPD:
6070 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6074 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6077 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6080 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6083 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6086 case OP_PADDB_SAT_UN:
6087 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6089 case OP_PSUBB_SAT_UN:
6090 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6092 case OP_PADDW_SAT_UN:
6093 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6095 case OP_PSUBW_SAT_UN:
6096 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6100 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6103 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6106 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6109 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6113 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6116 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6119 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6121 case OP_PMULW_HIGH_UN:
6122 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6125 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6129 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6132 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6136 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6139 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6143 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6146 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6150 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6153 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6157 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6160 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6164 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6167 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6171 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6174 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6177 /*TODO: This is appart of the sse spec but not added
6179 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6182 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6187 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6190 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6193 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6196 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6199 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6202 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6205 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6208 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6211 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6214 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6218 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6221 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6225 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6226 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6228 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6233 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6235 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6236 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6240 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6242 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6243 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6244 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6248 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6250 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6253 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6255 case OP_EXTRACTX_U2:
6256 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6258 case OP_INSERTX_U1_SLOW:
6259 /*sreg1 is the extracted ireg (scratch)
6260 /sreg2 is the to be inserted ireg (scratch)
6261 /dreg is the xreg to receive the value*/
6263 /*clear the bits from the extracted word*/
6264 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6265 /*shift the value to insert if needed*/
6266 if (ins->inst_c0 & 1)
6267 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6268 /*join them together*/
6269 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6270 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6272 case OP_INSERTX_I4_SLOW:
6273 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6274 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6275 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6277 case OP_INSERTX_I8_SLOW:
6278 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6280 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6282 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6285 case OP_INSERTX_R4_SLOW:
6286 switch (ins->inst_c0) {
6288 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6291 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6292 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6293 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6296 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6297 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6298 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6301 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6302 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6303 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6307 case OP_INSERTX_R8_SLOW:
6309 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6311 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6313 case OP_STOREX_MEMBASE_REG:
6314 case OP_STOREX_MEMBASE:
6315 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6317 case OP_LOADX_MEMBASE:
6318 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6320 case OP_LOADX_ALIGNED_MEMBASE:
6321 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6323 case OP_STOREX_ALIGNED_MEMBASE_REG:
6324 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6326 case OP_STOREX_NTA_MEMBASE_REG:
6327 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6329 case OP_PREFETCH_MEMBASE:
6330 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6334 /*FIXME the peephole pass should have killed this*/
6335 if (ins->dreg != ins->sreg1)
6336 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6339 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6341 case OP_ICONV_TO_R8_RAW:
6342 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6343 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6346 case OP_FCONV_TO_R8_X:
6347 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6350 case OP_XCONV_R8_TO_I4:
6351 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6352 switch (ins->backend.source_opcode) {
6353 case OP_FCONV_TO_I1:
6354 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6356 case OP_FCONV_TO_U1:
6357 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6359 case OP_FCONV_TO_I2:
6360 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6362 case OP_FCONV_TO_U2:
6363 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6369 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6370 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6371 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6374 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6375 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6378 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6379 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6382 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6383 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6384 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6387 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6388 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6391 case OP_LIVERANGE_START: {
6392 if (cfg->verbose_level > 1)
6393 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6394 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6397 case OP_LIVERANGE_END: {
6398 if (cfg->verbose_level > 1)
6399 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6400 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6403 case OP_NACL_GC_SAFE_POINT: {
6404 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6405 if (cfg->compile_aot)
6406 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6410 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6411 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6412 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6413 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6414 amd64_patch (br[0], code);
6419 case OP_GC_LIVENESS_DEF:
6420 case OP_GC_LIVENESS_USE:
6421 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6422 ins->backend.pc_offset = code - cfg->native_code;
6424 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6425 ins->backend.pc_offset = code - cfg->native_code;
6426 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6429 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6430 g_assert_not_reached ();
6433 if ((code - cfg->native_code - offset) > max_len) {
6434 #if !defined(__native_client_codegen__)
6435 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6436 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6437 g_assert_not_reached ();
6442 last_offset = offset;
6445 cfg->code_len = code - cfg->native_code;
6448 #endif /* DISABLE_JIT */
6451 mono_arch_register_lowlevel_calls (void)
6453 /* The signature doesn't matter */
6454 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6458 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6460 MonoJumpInfo *patch_info;
6461 gboolean compile_aot = !run_cctors;
6463 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6464 unsigned char *ip = patch_info->ip.i + code;
6465 unsigned char *target;
6467 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6470 switch (patch_info->type) {
6471 case MONO_PATCH_INFO_BB:
6472 case MONO_PATCH_INFO_LABEL:
6475 /* No need to patch these */
6480 switch (patch_info->type) {
6481 case MONO_PATCH_INFO_NONE:
6483 case MONO_PATCH_INFO_METHOD_REL:
6484 case MONO_PATCH_INFO_R8:
6485 case MONO_PATCH_INFO_R4:
6486 g_assert_not_reached ();
6488 case MONO_PATCH_INFO_BB:
6495 * Debug code to help track down problems where the target of a near call is
6498 if (amd64_is_near_call (ip)) {
6499 gint64 disp = (guint8*)target - (guint8*)ip;
6501 if (!amd64_is_imm32 (disp)) {
6502 printf ("TYPE: %d\n", patch_info->type);
6503 switch (patch_info->type) {
6504 case MONO_PATCH_INFO_INTERNAL_METHOD:
6505 printf ("V: %s\n", patch_info->data.name);
6507 case MONO_PATCH_INFO_METHOD_JUMP:
6508 case MONO_PATCH_INFO_METHOD:
6509 printf ("V: %s\n", patch_info->data.method->name);
6517 amd64_patch (ip, (gpointer)target);
6524 get_max_epilog_size (MonoCompile *cfg)
6526 int max_epilog_size = 16;
6528 if (cfg->method->save_lmf)
6529 max_epilog_size += 256;
6531 if (mono_jit_trace_calls != NULL)
6532 max_epilog_size += 50;
6534 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6535 max_epilog_size += 50;
6537 max_epilog_size += (AMD64_NREG * 2);
6539 return max_epilog_size;
6543 * This macro is used for testing whenever the unwinder works correctly at every point
6544 * where an async exception can happen.
6546 /* This will generate a SIGSEGV at the given point in the code */
6547 #define async_exc_point(code) do { \
6548 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6549 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6550 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6551 cfg->arch.async_point_count ++; \
6556 mono_arch_emit_prolog (MonoCompile *cfg)
6558 MonoMethod *method = cfg->method;
6560 MonoMethodSignature *sig;
6562 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6565 MonoInst *lmf_var = cfg->arch.lmf_var;
6566 gboolean args_clobbered = FALSE;
6567 gboolean trace = FALSE;
6568 #ifdef __native_client_codegen__
6569 guint alignment_check;
6572 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
6574 #if defined(__default_codegen__)
6575 code = cfg->native_code = g_malloc (cfg->code_size);
6576 #elif defined(__native_client_codegen__)
6577 /* native_code_alloc is not 32-byte aligned, native_code is. */
6578 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6580 /* Align native_code to next nearest kNaclAlignment byte. */
6581 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6582 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6584 code = cfg->native_code;
6586 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6587 g_assert (alignment_check == 0);
6590 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6593 /* Amount of stack space allocated by register saving code */
6596 /* Offset between RSP and the CFA */
6600 * The prolog consists of the following parts:
6602 * - push rbp, mov rbp, rsp
6603 * - save callee saved regs using pushes
6605 * - save rgctx if needed
6606 * - save lmf if needed
6609 * - save rgctx if needed
6610 * - save lmf if needed
6611 * - save callee saved regs using moves
6616 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6617 // IP saved at CFA - 8
6618 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6619 async_exc_point (code);
6620 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6622 if (!cfg->arch.omit_fp) {
6623 amd64_push_reg (code, AMD64_RBP);
6625 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6626 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6627 async_exc_point (code);
6629 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6631 /* These are handled automatically by the stack marking code */
6632 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6634 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6635 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6636 async_exc_point (code);
6638 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6642 /* Save callee saved registers */
6643 if (!cfg->arch.omit_fp && !method->save_lmf) {
6644 int offset = cfa_offset;
6646 for (i = 0; i < AMD64_NREG; ++i)
6647 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6648 amd64_push_reg (code, i);
6649 pos += 8; /* AMD64 push inst is always 8 bytes, no way to change it */
6651 mono_emit_unwind_op_offset (cfg, code, i, - offset);
6652 async_exc_point (code);
6654 /* These are handled automatically by the stack marking code */
6655 mini_gc_set_slot_type_from_cfa (cfg, - offset, SLOT_NOREF);
6659 /* The param area is always at offset 0 from sp */
6660 /* This needs to be allocated here, since it has to come after the spill area */
6661 if (cfg->arch.no_pushes && cfg->param_area) {
6662 if (cfg->arch.omit_fp)
6664 g_assert_not_reached ();
6665 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6668 if (cfg->arch.omit_fp) {
6670 * On enter, the stack is misaligned by the pushing of the return
6671 * address. It is either made aligned by the pushing of %rbp, or by
6674 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6675 if ((alloc_size % 16) == 0) {
6677 /* Mark the padding slot as NOREF */
6678 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6681 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6682 if (cfg->stack_offset != alloc_size) {
6683 /* Mark the padding slot as NOREF */
6684 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6686 cfg->arch.sp_fp_offset = alloc_size;
6690 cfg->arch.stack_alloc_size = alloc_size;
6692 /* Allocate stack frame */
6694 /* See mono_emit_stack_alloc */
6695 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6696 guint32 remaining_size = alloc_size;
6697 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6698 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6699 guint32 offset = code - cfg->native_code;
6700 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6701 while (required_code_size >= (cfg->code_size - offset))
6702 cfg->code_size *= 2;
6703 cfg->native_code = mono_realloc_native_code (cfg);
6704 code = cfg->native_code + offset;
6705 cfg->stat_code_reallocs++;
6708 while (remaining_size >= 0x1000) {
6709 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6710 if (cfg->arch.omit_fp) {
6711 cfa_offset += 0x1000;
6712 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6714 async_exc_point (code);
6716 if (cfg->arch.omit_fp)
6717 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6720 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6721 remaining_size -= 0x1000;
6723 if (remaining_size) {
6724 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6725 if (cfg->arch.omit_fp) {
6726 cfa_offset += remaining_size;
6727 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6728 async_exc_point (code);
6731 if (cfg->arch.omit_fp)
6732 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6736 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6737 if (cfg->arch.omit_fp) {
6738 cfa_offset += alloc_size;
6739 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6740 async_exc_point (code);
6745 /* Stack alignment check */
6748 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6749 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6750 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6751 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6752 amd64_breakpoint (code);
6756 #ifndef TARGET_WIN32
6757 if (mini_get_debug_options ()->init_stacks) {
6758 /* Fill the stack frame with a dummy value to force deterministic behavior */
6760 /* Save registers to the red zone */
6761 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6762 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6764 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6765 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6766 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6769 #if defined(__default_codegen__)
6770 amd64_prefix (code, X86_REP_PREFIX);
6772 #elif defined(__native_client_codegen__)
6773 /* NaCl stos pseudo-instruction */
6774 amd64_codegen_pre (code);
6775 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6776 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6777 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6778 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6779 amd64_prefix (code, X86_REP_PREFIX);
6781 amd64_codegen_post (code);
6782 #endif /* __native_client_codegen__ */
6784 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6785 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6790 if (method->save_lmf) {
6791 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6794 /* Save callee saved registers */
6795 if (cfg->arch.omit_fp && !method->save_lmf) {
6796 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6798 /* Save caller saved registers after sp is adjusted */
6799 /* The registers are saved at the bottom of the frame */
6800 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6801 for (i = 0; i < AMD64_NREG; ++i)
6802 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6803 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6804 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6806 /* These are handled automatically by the stack marking code */
6807 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6809 save_area_offset += 8;
6810 async_exc_point (code);
6814 /* store runtime generic context */
6815 if (cfg->rgctx_var) {
6816 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6817 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6819 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6821 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6822 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6825 /* compute max_length in order to use short forward jumps */
6826 max_epilog_size = get_max_epilog_size (cfg);
6827 if (cfg->opt & MONO_OPT_BRANCH) {
6828 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6832 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6834 /* max alignment for loops */
6835 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6836 max_length += LOOP_ALIGNMENT;
6837 #ifdef __native_client_codegen__
6838 /* max alignment for native client */
6839 max_length += kNaClAlignment;
6842 MONO_BB_FOR_EACH_INS (bb, ins) {
6843 #ifdef __native_client_codegen__
6845 int space_in_block = kNaClAlignment -
6846 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6847 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6848 if (space_in_block < max_len && max_len < kNaClAlignment) {
6849 max_length += space_in_block;
6852 #endif /*__native_client_codegen__*/
6853 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6856 /* Take prolog and epilog instrumentation into account */
6857 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6858 max_length += max_epilog_size;
6860 bb->max_length = max_length;
6864 sig = mono_method_signature (method);
6867 cinfo = cfg->arch.cinfo;
6869 if (sig->ret->type != MONO_TYPE_VOID) {
6870 /* Save volatile arguments to the stack */
6871 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6872 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6875 /* Keep this in sync with emit_load_volatile_arguments */
6876 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6877 ArgInfo *ainfo = cinfo->args + i;
6878 gint32 stack_offset;
6881 ins = cfg->args [i];
6883 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6884 /* Unused arguments */
6887 if (sig->hasthis && (i == 0))
6888 arg_type = &mono_defaults.object_class->byval_arg;
6890 arg_type = sig->params [i - sig->hasthis];
6892 stack_offset = ainfo->offset + ARGS_OFFSET;
6894 if (cfg->globalra) {
6895 /* All the other moves are done by the register allocator */
6896 switch (ainfo->storage) {
6897 case ArgInFloatSSEReg:
6898 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6900 case ArgValuetypeInReg:
6901 for (quad = 0; quad < 2; quad ++) {
6902 switch (ainfo->pair_storage [quad]) {
6904 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6906 case ArgInFloatSSEReg:
6907 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6909 case ArgInDoubleSSEReg:
6910 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6915 g_assert_not_reached ();
6926 /* Save volatile arguments to the stack */
6927 if (ins->opcode != OP_REGVAR) {
6928 switch (ainfo->storage) {
6934 if (stack_offset & 0x1)
6936 else if (stack_offset & 0x2)
6938 else if (stack_offset & 0x4)
6943 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6946 * Save the original location of 'this',
6947 * get_generic_info_from_stack_frame () needs this to properly look up
6948 * the argument value during the handling of async exceptions.
6950 if (ins == cfg->args [0]) {
6951 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6952 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6956 case ArgInFloatSSEReg:
6957 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6959 case ArgInDoubleSSEReg:
6960 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6962 case ArgValuetypeInReg:
6963 for (quad = 0; quad < 2; quad ++) {
6964 switch (ainfo->pair_storage [quad]) {
6966 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6968 case ArgInFloatSSEReg:
6969 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6971 case ArgInDoubleSSEReg:
6972 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6977 g_assert_not_reached ();
6981 case ArgValuetypeAddrInIReg:
6982 if (ainfo->pair_storage [0] == ArgInIReg)
6983 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6989 /* Argument allocated to (non-volatile) register */
6990 switch (ainfo->storage) {
6992 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6995 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6998 g_assert_not_reached ();
7001 if (ins == cfg->args [0]) {
7002 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7003 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7008 if (method->save_lmf) {
7009 code = emit_save_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7013 args_clobbered = TRUE;
7014 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7017 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7018 args_clobbered = TRUE;
7021 * Optimize the common case of the first bblock making a call with the same
7022 * arguments as the method. This works because the arguments are still in their
7023 * original argument registers.
7024 * FIXME: Generalize this
7026 if (!args_clobbered) {
7027 MonoBasicBlock *first_bb = cfg->bb_entry;
7030 next = mono_bb_first_ins (first_bb);
7031 if (!next && first_bb->next_bb) {
7032 first_bb = first_bb->next_bb;
7033 next = mono_bb_first_ins (first_bb);
7036 if (first_bb->in_count > 1)
7039 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7040 ArgInfo *ainfo = cinfo->args + i;
7041 gboolean match = FALSE;
7043 ins = cfg->args [i];
7044 if (ins->opcode != OP_REGVAR) {
7045 switch (ainfo->storage) {
7047 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7048 if (next->dreg == ainfo->reg) {
7052 next->opcode = OP_MOVE;
7053 next->sreg1 = ainfo->reg;
7054 /* Only continue if the instruction doesn't change argument regs */
7055 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7065 /* Argument allocated to (non-volatile) register */
7066 switch (ainfo->storage) {
7068 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7080 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7087 if (cfg->gen_seq_points) {
7088 MonoInst *info_var = cfg->arch.seq_point_info_var;
7090 /* Initialize seq_point_info_var */
7091 if (cfg->compile_aot) {
7092 /* Initialize the variable from a GOT slot */
7093 /* Same as OP_AOTCONST */
7094 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7095 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7096 g_assert (info_var->opcode == OP_REGOFFSET);
7097 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7100 /* Initialize ss_trigger_page_var */
7101 ins = cfg->arch.ss_trigger_page_var;
7103 g_assert (ins->opcode == OP_REGOFFSET);
7105 if (cfg->compile_aot) {
7106 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7107 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7109 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7111 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7114 cfg->code_len = code - cfg->native_code;
7116 g_assert (cfg->code_len < cfg->code_size);
7122 mono_arch_emit_epilog (MonoCompile *cfg)
7124 MonoMethod *method = cfg->method;
7127 int max_epilog_size;
7129 gint32 lmf_offset = cfg->arch.lmf_var ? ((MonoInst*)cfg->arch.lmf_var)->inst_offset : -1;
7131 max_epilog_size = get_max_epilog_size (cfg);
7133 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7134 cfg->code_size *= 2;
7135 cfg->native_code = mono_realloc_native_code (cfg);
7136 cfg->stat_code_reallocs++;
7139 code = cfg->native_code + cfg->code_len;
7141 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7142 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7144 /* the code restoring the registers must be kept in sync with OP_JMP */
7147 if (method->save_lmf) {
7148 /* check if we need to restore protection of the stack after a stack overflow */
7149 if (mono_get_jit_tls_offset () != -1) {
7151 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7152 /* we load the value in a separate instruction: this mechanism may be
7153 * used later as a safer way to do thread interruption
7155 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7156 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7158 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7159 /* note that the call trampoline will preserve eax/edx */
7160 x86_call_reg (code, X86_ECX);
7161 x86_patch (patch, code);
7163 /* FIXME: maybe save the jit tls in the prolog */
7166 code = emit_restore_lmf (cfg, code, lmf_offset);
7168 /* Restore caller saved regs */
7169 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7170 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7172 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7173 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7175 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7176 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7178 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7179 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7181 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7182 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7184 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7185 #if defined(__default_codegen__)
7186 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7187 #elif defined(__native_client_codegen__)
7188 g_assert_not_reached();
7192 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7193 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7195 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7196 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7201 if (cfg->arch.omit_fp) {
7202 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7204 for (i = 0; i < AMD64_NREG; ++i)
7205 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7206 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
7207 save_area_offset += 8;
7211 for (i = 0; i < AMD64_NREG; ++i)
7212 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
7213 pos -= sizeof(mgreg_t);
7216 if (pos == - sizeof(mgreg_t)) {
7217 /* Only one register, so avoid lea */
7218 for (i = AMD64_NREG - 1; i > 0; --i)
7219 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7220 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
7224 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
7226 /* Pop registers in reverse order */
7227 for (i = AMD64_NREG - 1; i > 0; --i)
7228 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7229 amd64_pop_reg (code, i);
7236 /* Load returned vtypes into registers if needed */
7237 cinfo = cfg->arch.cinfo;
7238 if (cinfo->ret.storage == ArgValuetypeInReg) {
7239 ArgInfo *ainfo = &cinfo->ret;
7240 MonoInst *inst = cfg->ret;
7242 for (quad = 0; quad < 2; quad ++) {
7243 switch (ainfo->pair_storage [quad]) {
7245 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7247 case ArgInFloatSSEReg:
7248 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7250 case ArgInDoubleSSEReg:
7251 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7256 g_assert_not_reached ();
7261 if (cfg->arch.omit_fp) {
7262 if (cfg->arch.stack_alloc_size)
7263 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7267 async_exc_point (code);
7270 cfg->code_len = code - cfg->native_code;
7272 g_assert (cfg->code_len < cfg->code_size);
7276 mono_arch_emit_exceptions (MonoCompile *cfg)
7278 MonoJumpInfo *patch_info;
7281 MonoClass *exc_classes [16];
7282 guint8 *exc_throw_start [16], *exc_throw_end [16];
7283 guint32 code_size = 0;
7285 /* Compute needed space */
7286 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7287 if (patch_info->type == MONO_PATCH_INFO_EXC)
7289 if (patch_info->type == MONO_PATCH_INFO_R8)
7290 code_size += 8 + 15; /* sizeof (double) + alignment */
7291 if (patch_info->type == MONO_PATCH_INFO_R4)
7292 code_size += 4 + 15; /* sizeof (float) + alignment */
7293 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7294 code_size += 8 + 7; /*sizeof (void*) + alignment */
7297 #ifdef __native_client_codegen__
7298 /* Give us extra room on Native Client. This could be */
7299 /* more carefully calculated, but bundle alignment makes */
7300 /* it much trickier, so *2 like other places is good. */
7304 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7305 cfg->code_size *= 2;
7306 cfg->native_code = mono_realloc_native_code (cfg);
7307 cfg->stat_code_reallocs++;
7310 code = cfg->native_code + cfg->code_len;
7312 /* add code to raise exceptions */
7314 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7315 switch (patch_info->type) {
7316 case MONO_PATCH_INFO_EXC: {
7317 MonoClass *exc_class;
7321 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7323 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7324 g_assert (exc_class);
7325 throw_ip = patch_info->ip.i;
7327 //x86_breakpoint (code);
7328 /* Find a throw sequence for the same exception class */
7329 for (i = 0; i < nthrows; ++i)
7330 if (exc_classes [i] == exc_class)
7333 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7334 x86_jump_code (code, exc_throw_start [i]);
7335 patch_info->type = MONO_PATCH_INFO_NONE;
7339 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7343 exc_classes [nthrows] = exc_class;
7344 exc_throw_start [nthrows] = code;
7346 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7348 patch_info->type = MONO_PATCH_INFO_NONE;
7350 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7352 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7357 exc_throw_end [nthrows] = code;
7367 g_assert(code < cfg->native_code + cfg->code_size);
7370 /* Handle relocations with RIP relative addressing */
7371 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7372 gboolean remove = FALSE;
7373 guint8 *orig_code = code;
7375 switch (patch_info->type) {
7376 case MONO_PATCH_INFO_R8:
7377 case MONO_PATCH_INFO_R4: {
7378 guint8 *pos, *patch_pos;
7381 /* The SSE opcodes require a 16 byte alignment */
7382 #if defined(__default_codegen__)
7383 code = (guint8*)ALIGN_TO (code, 16);
7384 #elif defined(__native_client_codegen__)
7386 /* Pad this out with HLT instructions */
7387 /* or we can get garbage bytes emitted */
7388 /* which will fail validation */
7389 guint8 *aligned_code;
7390 /* extra align to make room for */
7391 /* mov/push below */
7392 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7393 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7394 /* The technique of hiding data in an */
7395 /* instruction has a problem here: we */
7396 /* need the data aligned to a 16-byte */
7397 /* boundary but the instruction cannot */
7398 /* cross the bundle boundary. so only */
7399 /* odd multiples of 16 can be used */
7400 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7403 while (code < aligned_code) {
7404 *(code++) = 0xf4; /* hlt */
7409 pos = cfg->native_code + patch_info->ip.i;
7410 if (IS_REX (pos [1])) {
7411 patch_pos = pos + 5;
7412 target_pos = code - pos - 9;
7415 patch_pos = pos + 4;
7416 target_pos = code - pos - 8;
7419 if (patch_info->type == MONO_PATCH_INFO_R8) {
7420 #ifdef __native_client_codegen__
7421 /* Hide 64-bit data in a */
7422 /* "mov imm64, r11" instruction. */
7423 /* write it before the start of */
7425 *(code-2) = 0x49; /* prefix */
7426 *(code-1) = 0xbb; /* mov X, %r11 */
7428 *(double*)code = *(double*)patch_info->data.target;
7429 code += sizeof (double);
7431 #ifdef __native_client_codegen__
7432 /* Hide 32-bit data in a */
7433 /* "push imm32" instruction. */
7434 *(code-1) = 0x68; /* push */
7436 *(float*)code = *(float*)patch_info->data.target;
7437 code += sizeof (float);
7440 *(guint32*)(patch_pos) = target_pos;
7445 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7448 if (cfg->compile_aot)
7451 /*loading is faster against aligned addresses.*/
7452 code = (guint8*)ALIGN_TO (code, 8);
7453 memset (orig_code, 0, code - orig_code);
7455 pos = cfg->native_code + patch_info->ip.i;
7457 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7458 if (IS_REX (pos [1]))
7459 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7461 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7463 *(gpointer*)code = (gpointer)patch_info->data.target;
7464 code += sizeof (gpointer);
7474 if (patch_info == cfg->patch_info)
7475 cfg->patch_info = patch_info->next;
7479 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7481 tmp->next = patch_info->next;
7484 g_assert (code < cfg->native_code + cfg->code_size);
7487 cfg->code_len = code - cfg->native_code;
7489 g_assert (cfg->code_len < cfg->code_size);
7493 #endif /* DISABLE_JIT */
7496 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7499 CallInfo *cinfo = NULL;
7500 MonoMethodSignature *sig;
7502 int i, n, stack_area = 0;
7504 /* Keep this in sync with mono_arch_get_argument_info */
7506 if (enable_arguments) {
7507 /* Allocate a new area on the stack and save arguments there */
7508 sig = mono_method_signature (cfg->method);
7510 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7512 n = sig->param_count + sig->hasthis;
7514 stack_area = ALIGN_TO (n * 8, 16);
7516 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7518 for (i = 0; i < n; ++i) {
7519 inst = cfg->args [i];
7521 if (inst->opcode == OP_REGVAR)
7522 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7524 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7525 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7530 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7531 amd64_set_reg_template (code, AMD64_ARG_REG1);
7532 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7533 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7535 if (enable_arguments)
7536 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7550 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7553 int save_mode = SAVE_NONE;
7554 MonoMethod *method = cfg->method;
7555 MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
7558 switch (ret_type->type) {
7559 case MONO_TYPE_VOID:
7560 /* special case string .ctor icall */
7561 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7562 save_mode = SAVE_EAX;
7564 save_mode = SAVE_NONE;
7568 save_mode = SAVE_EAX;
7572 save_mode = SAVE_XMM;
7574 case MONO_TYPE_GENERICINST:
7575 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7576 save_mode = SAVE_EAX;
7580 case MONO_TYPE_VALUETYPE:
7581 save_mode = SAVE_STRUCT;
7584 save_mode = SAVE_EAX;
7588 /* Save the result and copy it into the proper argument register */
7589 switch (save_mode) {
7591 amd64_push_reg (code, AMD64_RAX);
7593 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7594 if (enable_arguments)
7595 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7599 if (enable_arguments)
7600 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7603 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7604 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7606 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7608 * The result is already in the proper argument register so no copying
7615 g_assert_not_reached ();
7618 /* Set %al since this is a varargs call */
7619 if (save_mode == SAVE_XMM)
7620 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7622 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7624 if (preserve_argument_registers) {
7625 for (i = 0; i < PARAM_REGS; ++i)
7626 amd64_push_reg (code, param_regs [i]);
7629 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7630 amd64_set_reg_template (code, AMD64_ARG_REG1);
7631 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7633 if (preserve_argument_registers) {
7634 for (i = PARAM_REGS - 1; i >= 0; --i)
7635 amd64_pop_reg (code, param_regs [i]);
7638 /* Restore result */
7639 switch (save_mode) {
7641 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7642 amd64_pop_reg (code, AMD64_RAX);
7648 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7649 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7650 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7655 g_assert_not_reached ();
7662 mono_arch_flush_icache (guint8 *code, gint size)
7668 mono_arch_flush_register_windows (void)
7673 mono_arch_is_inst_imm (gint64 imm)
7675 return amd64_is_imm32 (imm);
7679 * Determine whenever the trap whose info is in SIGINFO is caused by
7683 mono_arch_is_int_overflow (void *sigctx, void *info)
7690 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7692 rip = (guint8*)ctx.rip;
7694 if (IS_REX (rip [0])) {
7695 reg = amd64_rex_b (rip [0]);
7701 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7703 reg += x86_modrm_rm (rip [1]);
7743 g_assert_not_reached ();
7755 mono_arch_get_patch_offset (guint8 *code)
7761 * mono_breakpoint_clean_code:
7763 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7764 * breakpoints in the original code, they are removed in the copy.
7766 * Returns TRUE if no sw breakpoint was present.
7769 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7772 gboolean can_write = TRUE;
7774 * If method_start is non-NULL we need to perform bound checks, since we access memory
7775 * at code - offset we could go before the start of the method and end up in a different
7776 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7779 if (!method_start || code - offset >= method_start) {
7780 memcpy (buf, code - offset, size);
7782 int diff = code - method_start;
7783 memset (buf, 0, size);
7784 memcpy (buf + offset - diff, method_start, diff + size - offset);
7787 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7788 int idx = mono_breakpoint_info_index [i];
7792 ptr = mono_breakpoint_info [idx].address;
7793 if (ptr >= code && ptr < code + size) {
7794 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7796 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7797 buf [ptr - code] = saved_byte;
7803 #if defined(__native_client_codegen__)
7804 /* For membase calls, we want the base register. for Native Client, */
7805 /* all indirect calls have the following sequence with the given sizes: */
7806 /* mov %eXX,%eXX [2-3] */
7807 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7808 /* and $0xffffffffffffffe0,%r11d [4] */
7809 /* add %r15,%r11 [3] */
7810 /* callq *%r11 [3] */
7813 /* Determine if code points to a NaCl call-through-register sequence, */
7814 /* (i.e., the last 3 instructions listed above) */
7816 is_nacl_call_reg_sequence(guint8* code)
7818 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7819 "\x4d\x03\xdf" /* add */
7820 "\x41\xff\xd3"; /* call */
7821 return memcmp(code, sequence, 10) == 0;
7824 /* Determine if code points to the first opcode of the mov membase component */
7825 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7826 /* (there could be a REX prefix before the opcode but it is ignored) */
7828 is_nacl_indirect_call_membase_sequence(guint8* code)
7830 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7831 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7832 /* and that src reg = dest reg */
7833 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7834 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7836 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7837 /* and has dst of r11 and base of r15 */
7838 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7839 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7841 #endif /* __native_client_codegen__ */
7844 mono_arch_get_this_arg_reg (guint8 *code)
7846 return AMD64_ARG_REG1;
7850 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7852 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7855 #define MAX_ARCH_DELEGATE_PARAMS 10
7858 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7860 guint8 *code, *start;
7864 start = code = mono_global_codeman_reserve (64);
7866 /* Replace the this argument with the target */
7867 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7868 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7869 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7871 g_assert ((code - start) < 64);
7873 start = code = mono_global_codeman_reserve (64);
7875 if (param_count == 0) {
7876 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7878 /* We have to shift the arguments left */
7879 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7880 for (i = 0; i < param_count; ++i) {
7883 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7885 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7887 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7891 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7893 g_assert ((code - start) < 64);
7896 nacl_global_codeman_validate(&start, 64, &code);
7898 mono_debug_add_delegate_trampoline (start, code - start);
7901 *code_len = code - start;
7904 if (mono_jit_map_is_enabled ()) {
7907 buff = (char*)"delegate_invoke_has_target";
7909 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7910 mono_emit_jit_tramp (start, code - start, buff);
7919 * mono_arch_get_delegate_invoke_impls:
7921 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7925 mono_arch_get_delegate_invoke_impls (void)
7933 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7934 res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7936 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7937 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7938 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7939 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7940 g_free (tramp_name);
7947 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7949 guint8 *code, *start;
7952 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7955 /* FIXME: Support more cases */
7956 if (MONO_TYPE_ISSTRUCT (sig->ret))
7960 static guint8* cached = NULL;
7966 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7968 start = get_delegate_invoke_impl (TRUE, 0, NULL);
7970 mono_memory_barrier ();
7974 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7975 for (i = 0; i < sig->param_count; ++i)
7976 if (!mono_is_regsize_var (sig->params [i]))
7978 if (sig->param_count > 4)
7981 code = cache [sig->param_count];
7985 if (mono_aot_only) {
7986 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7987 start = mono_aot_get_trampoline (name);
7990 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7993 mono_memory_barrier ();
7995 cache [sig->param_count] = start;
8001 mono_arch_finish_init (void)
8005 * We need to init this multiple times, since when we are first called, the key might not
8006 * be initialized yet.
8008 appdomain_tls_offset = mono_domain_get_tls_key ();
8009 lmf_tls_offset = mono_get_jit_tls_key ();
8010 lmf_addr_tls_offset = mono_get_jit_tls_key ();
8012 /* Only 64 tls entries can be accessed using inline code */
8013 if (appdomain_tls_offset >= 64)
8014 appdomain_tls_offset = -1;
8015 if (lmf_tls_offset >= 64)
8016 lmf_tls_offset = -1;
8017 if (lmf_addr_tls_offset >= 64)
8018 lmf_addr_tls_offset = -1;
8021 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8023 appdomain_tls_offset = mono_domain_get_tls_offset ();
8024 lmf_tls_offset = mono_get_lmf_tls_offset ();
8025 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
8030 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8034 #ifdef MONO_ARCH_HAVE_IMT
8036 #if defined(__default_codegen__)
8037 #define CMP_SIZE (6 + 1)
8038 #define CMP_REG_REG_SIZE (4 + 1)
8039 #define BR_SMALL_SIZE 2
8040 #define BR_LARGE_SIZE 6
8041 #define MOV_REG_IMM_SIZE 10
8042 #define MOV_REG_IMM_32BIT_SIZE 6
8043 #define JUMP_REG_SIZE (2 + 1)
8044 #elif defined(__native_client_codegen__)
8045 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8046 #define CMP_SIZE ((6 + 1) * 2 - 1)
8047 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8048 #define BR_SMALL_SIZE (2 * 2 - 1)
8049 #define BR_LARGE_SIZE (6 * 2 - 1)
8050 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8051 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8052 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8053 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8054 /* Jump membase's size is large and unpredictable */
8055 /* in native client, just pad it out a whole bundle. */
8056 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8060 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8062 int i, distance = 0;
8063 for (i = start; i < target; ++i)
8064 distance += imt_entries [i]->chunk_size;
8069 * LOCKING: called with the domain lock held
8072 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8073 gpointer fail_tramp)
8077 guint8 *code, *start;
8078 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8080 for (i = 0; i < count; ++i) {
8081 MonoIMTCheckItem *item = imt_entries [i];
8082 if (item->is_equals) {
8083 if (item->check_target_idx) {
8084 if (!item->compare_done) {
8085 if (amd64_is_imm32 (item->key))
8086 item->chunk_size += CMP_SIZE;
8088 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8090 if (item->has_target_code) {
8091 item->chunk_size += MOV_REG_IMM_SIZE;
8093 if (vtable_is_32bit)
8094 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8096 item->chunk_size += MOV_REG_IMM_SIZE;
8097 #ifdef __native_client_codegen__
8098 item->chunk_size += JUMP_MEMBASE_SIZE;
8101 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8104 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8105 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8107 if (vtable_is_32bit)
8108 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8110 item->chunk_size += MOV_REG_IMM_SIZE;
8111 item->chunk_size += JUMP_REG_SIZE;
8112 /* with assert below:
8113 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8115 #ifdef __native_client_codegen__
8116 item->chunk_size += JUMP_MEMBASE_SIZE;
8121 if (amd64_is_imm32 (item->key))
8122 item->chunk_size += CMP_SIZE;
8124 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8125 item->chunk_size += BR_LARGE_SIZE;
8126 imt_entries [item->check_target_idx]->compare_done = TRUE;
8128 size += item->chunk_size;
8130 #if defined(__native_client__) && defined(__native_client_codegen__)
8131 /* In Native Client, we don't re-use thunks, allocate from the */
8132 /* normal code manager paths. */
8133 code = mono_domain_code_reserve (domain, size);
8136 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8138 code = mono_domain_code_reserve (domain, size);
8141 for (i = 0; i < count; ++i) {
8142 MonoIMTCheckItem *item = imt_entries [i];
8143 item->code_target = code;
8144 if (item->is_equals) {
8145 gboolean fail_case = !item->check_target_idx && fail_tramp;
8147 if (item->check_target_idx || fail_case) {
8148 if (!item->compare_done || fail_case) {
8149 if (amd64_is_imm32 (item->key))
8150 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8152 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8153 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8156 item->jmp_code = code;
8157 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8158 if (item->has_target_code) {
8159 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8160 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8162 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8163 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8167 amd64_patch (item->jmp_code, code);
8168 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8169 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8170 item->jmp_code = NULL;
8173 /* enable the commented code to assert on wrong method */
8175 if (amd64_is_imm32 (item->key))
8176 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8178 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8179 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8181 item->jmp_code = code;
8182 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8183 /* See the comment below about R10 */
8184 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8185 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8186 amd64_patch (item->jmp_code, code);
8187 amd64_breakpoint (code);
8188 item->jmp_code = NULL;
8190 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8191 needs to be preserved. R10 needs
8192 to be preserved for calls which
8193 require a runtime generic context,
8194 but interface calls don't. */
8195 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8196 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8200 if (amd64_is_imm32 (item->key))
8201 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8203 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8204 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8206 item->jmp_code = code;
8207 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8208 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8210 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8212 g_assert (code - item->code_target <= item->chunk_size);
8214 /* patch the branches to get to the target items */
8215 for (i = 0; i < count; ++i) {
8216 MonoIMTCheckItem *item = imt_entries [i];
8217 if (item->jmp_code) {
8218 if (item->check_target_idx) {
8219 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8225 mono_stats.imt_thunks_size += code - start;
8226 g_assert (code - start <= size);
8228 nacl_domain_code_validate(domain, &start, size, &code);
8234 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8236 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8241 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8243 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8247 mono_arch_get_cie_program (void)
8251 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8252 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8258 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8260 MonoInst *ins = NULL;
8263 if (cmethod->klass == mono_defaults.math_class) {
8264 if (strcmp (cmethod->name, "Sin") == 0) {
8266 } else if (strcmp (cmethod->name, "Cos") == 0) {
8268 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8270 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8275 MONO_INST_NEW (cfg, ins, opcode);
8276 ins->type = STACK_R8;
8277 ins->dreg = mono_alloc_freg (cfg);
8278 ins->sreg1 = args [0]->dreg;
8279 MONO_ADD_INS (cfg->cbb, ins);
8283 if (cfg->opt & MONO_OPT_CMOV) {
8284 if (strcmp (cmethod->name, "Min") == 0) {
8285 if (fsig->params [0]->type == MONO_TYPE_I4)
8287 if (fsig->params [0]->type == MONO_TYPE_U4)
8288 opcode = OP_IMIN_UN;
8289 else if (fsig->params [0]->type == MONO_TYPE_I8)
8291 else if (fsig->params [0]->type == MONO_TYPE_U8)
8292 opcode = OP_LMIN_UN;
8293 } else if (strcmp (cmethod->name, "Max") == 0) {
8294 if (fsig->params [0]->type == MONO_TYPE_I4)
8296 if (fsig->params [0]->type == MONO_TYPE_U4)
8297 opcode = OP_IMAX_UN;
8298 else if (fsig->params [0]->type == MONO_TYPE_I8)
8300 else if (fsig->params [0]->type == MONO_TYPE_U8)
8301 opcode = OP_LMAX_UN;
8306 MONO_INST_NEW (cfg, ins, opcode);
8307 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8308 ins->dreg = mono_alloc_ireg (cfg);
8309 ins->sreg1 = args [0]->dreg;
8310 ins->sreg2 = args [1]->dreg;
8311 MONO_ADD_INS (cfg->cbb, ins);
8315 /* OP_FREM is not IEEE compatible */
8316 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8317 MONO_INST_NEW (cfg, ins, OP_FREM);
8318 ins->inst_i0 = args [0];
8319 ins->inst_i1 = args [1];
8325 * Can't implement CompareExchange methods this way since they have
8333 mono_arch_print_tree (MonoInst *tree, int arity)
8338 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
8342 if (appdomain_tls_offset == -1)
8345 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
8346 ins->inst_offset = appdomain_tls_offset;
8350 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8353 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8356 case AMD64_RCX: return ctx->rcx;
8357 case AMD64_RDX: return ctx->rdx;
8358 case AMD64_RBX: return ctx->rbx;
8359 case AMD64_RBP: return ctx->rbp;
8360 case AMD64_RSP: return ctx->rsp;
8363 return _CTX_REG (ctx, rax, reg);
8365 return _CTX_REG (ctx, r12, reg - 12);
8367 g_assert_not_reached ();
8372 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8392 _CTX_REG (ctx, rax, reg) = val;
8394 _CTX_REG (ctx, r12, reg - 12) = val;
8396 g_assert_not_reached ();
8400 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8402 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8405 gpointer *sp, old_value;
8407 const unsigned char *handler;
8409 /*Decode the first instruction to figure out where did we store the spvar*/
8410 /*Our jit MUST generate the following:
8413 Which is encoded as: REX.W 0x89 mod_rm
8414 mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8415 mod (reg + imm8): 01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8416 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8418 FIXME can we generate frameless methods on this case?
8421 handler = clause->handler_start;
8424 if (*handler != 0x48)
8429 if (*handler != 0x89)
8433 if (*handler == 0x65)
8434 offset = *(signed char*)(handler + 1);
8435 else if (*handler == 0xA5)
8436 offset = *(int*)(handler + 1);
8441 bp = MONO_CONTEXT_GET_BP (ctx);
8442 sp = *(gpointer*)(bp + offset);
8445 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8454 * mono_arch_emit_load_aotconst:
8456 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8457 * TARGET from the mscorlib GOT in full-aot code.
8458 * On AMD64, the result is placed into R11.
8461 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8463 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8464 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8470 * mono_arch_get_trampolines:
8472 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8476 mono_arch_get_trampolines (gboolean aot)
8478 return mono_amd64_get_exception_trampolines (aot);
8481 /* Soft Debug support */
8482 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8485 * mono_arch_set_breakpoint:
8487 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8488 * The location should contain code emitted by OP_SEQ_POINT.
8491 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8494 guint8 *orig_code = code;
8497 guint32 native_offset = ip - (guint8*)ji->code_start;
8498 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8500 g_assert (info->bp_addrs [native_offset] == 0);
8501 info->bp_addrs [native_offset] = bp_trigger_page;
8504 * In production, we will use int3 (has to fix the size in the md
8505 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8508 g_assert (code [0] == 0x90);
8509 if (breakpoint_size == 8) {
8510 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8512 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8513 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8516 g_assert (code - orig_code == breakpoint_size);
8521 * mono_arch_clear_breakpoint:
8523 * Clear the breakpoint at IP.
8526 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8532 guint32 native_offset = ip - (guint8*)ji->code_start;
8533 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8535 g_assert (info->bp_addrs [native_offset] == 0);
8536 info->bp_addrs [native_offset] = info;
8538 for (i = 0; i < breakpoint_size; ++i)
8544 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8547 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8550 siginfo_t* sinfo = (siginfo_t*) info;
8551 /* Sometimes the address is off by 4 */
8552 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8560 * mono_arch_skip_breakpoint:
8562 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8563 * we resume, the instruction is not executed again.
8566 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8569 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8570 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8572 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8577 * mono_arch_start_single_stepping:
8579 * Start single stepping.
8582 mono_arch_start_single_stepping (void)
8584 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8588 * mono_arch_stop_single_stepping:
8590 * Stop single stepping.
8593 mono_arch_stop_single_stepping (void)
8595 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8599 * mono_arch_is_single_step_event:
8601 * Return whenever the machine state in SIGCTX corresponds to a single
8605 mono_arch_is_single_step_event (void *info, void *sigctx)
8608 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8611 siginfo_t* sinfo = (siginfo_t*) info;
8612 /* Sometimes the address is off by 4 */
8613 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8621 * mono_arch_skip_single_step:
8623 * Modify CTX so the ip is placed after the single step trigger instruction,
8624 * we resume, the instruction is not executed again.
8627 mono_arch_skip_single_step (MonoContext *ctx)
8629 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8633 * mono_arch_create_seq_point_info:
8635 * Return a pointer to a data structure which is used by the sequence
8636 * point implementation in AOTed code.
8639 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8645 // FIXME: Add a free function
8647 mono_domain_lock (domain);
8648 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8650 mono_domain_unlock (domain);
8653 ji = mono_jit_info_table_find (domain, (char*)code);
8656 // FIXME: Optimize the size
8657 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8659 info->ss_trigger_page = ss_trigger_page;
8660 info->bp_trigger_page = bp_trigger_page;
8661 /* Initialize to a valid address */
8662 for (i = 0; i < ji->code_size; ++i)
8663 info->bp_addrs [i] = info;
8665 mono_domain_lock (domain);
8666 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8668 mono_domain_unlock (domain);