2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/appdomain.h>
24 #include <mono/metadata/debug-helpers.h>
25 #include <mono/metadata/threads.h>
26 #include <mono/metadata/profiler-private.h>
27 #include <mono/metadata/mono-debug.h>
28 #include <mono/metadata/gc-internal.h>
29 #include <mono/utils/mono-math.h>
30 #include <mono/utils/mono-mmap.h>
31 #include <mono/utils/mono-memory-model.h>
32 #include <mono/utils/mono-tls.h>
36 #include "mini-amd64.h"
37 #include "cpu-amd64.h"
38 #include "debugger-agent.h"
41 static gint lmf_tls_offset = -1;
42 static gint lmf_addr_tls_offset = -1;
43 static gint appdomain_tls_offset = -1;
46 static gboolean optimize_for_xen = TRUE;
48 #define optimize_for_xen 0
51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
58 /* Under windows, the calling convention is never stdcall */
59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
64 /* This mutex protects architecture specific caches */
65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
67 static CRITICAL_SECTION mini_arch_mutex;
70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 /* Structure used by the sequence points in AOTed code */
74 gpointer ss_trigger_page;
75 gpointer bp_trigger_page;
76 gpointer bp_addrs [MONO_ZERO_LEN_ARRAY];
80 * The code generated for sequence points reads from this location, which is
81 * made read-only when single stepping is enabled.
83 static gpointer ss_trigger_page;
85 /* Enabled breakpoints read from this trigger page */
86 static gpointer bp_trigger_page;
88 /* The size of the breakpoint sequence */
89 static int breakpoint_size;
91 /* The size of the breakpoint instruction causing the actual fault */
92 static int breakpoint_fault_size;
94 /* The size of the single step instruction causing the actual fault */
95 static int single_step_fault_size;
98 /* On Win64 always reserve first 32 bytes for first four arguments */
99 #define ARGS_OFFSET 48
101 #define ARGS_OFFSET 16
103 #define GP_SCRATCH_REG AMD64_R11
106 * AMD64 register usage:
107 * - callee saved registers are used for global register allocation
108 * - %r11 is used for materializing 64 bit constants in opcodes
109 * - the rest is used for local allocation
113 * Floating point comparison results:
123 mono_arch_regname (int reg)
126 case AMD64_RAX: return "%rax";
127 case AMD64_RBX: return "%rbx";
128 case AMD64_RCX: return "%rcx";
129 case AMD64_RDX: return "%rdx";
130 case AMD64_RSP: return "%rsp";
131 case AMD64_RBP: return "%rbp";
132 case AMD64_RDI: return "%rdi";
133 case AMD64_RSI: return "%rsi";
134 case AMD64_R8: return "%r8";
135 case AMD64_R9: return "%r9";
136 case AMD64_R10: return "%r10";
137 case AMD64_R11: return "%r11";
138 case AMD64_R12: return "%r12";
139 case AMD64_R13: return "%r13";
140 case AMD64_R14: return "%r14";
141 case AMD64_R15: return "%r15";
146 static const char * packed_xmmregs [] = {
147 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
148 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
151 static const char * single_xmmregs [] = {
152 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
153 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
157 mono_arch_fregname (int reg)
159 if (reg < AMD64_XMM_NREG)
160 return single_xmmregs [reg];
166 mono_arch_xregname (int reg)
168 if (reg < AMD64_XMM_NREG)
169 return packed_xmmregs [reg];
174 G_GNUC_UNUSED static void
179 G_GNUC_UNUSED static gboolean
182 static int count = 0;
185 if (!getenv ("COUNT"))
188 if (count == atoi (getenv ("COUNT"))) {
192 if (count > atoi (getenv ("COUNT"))) {
203 return debug_count ();
209 static inline gboolean
210 amd64_is_near_call (guint8 *code)
213 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
216 return code [0] == 0xe8;
219 #ifdef __native_client_codegen__
221 /* Keep track of instruction "depth", that is, the level of sub-instruction */
222 /* for any given instruction. For instance, amd64_call_reg resolves to */
223 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
224 /* We only want to force bundle alignment for the top level instruction, */
225 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
226 static MonoNativeTlsKey nacl_instruction_depth;
228 static MonoNativeTlsKey nacl_rex_tag;
229 static MonoNativeTlsKey nacl_legacy_prefix_tag;
232 amd64_nacl_clear_legacy_prefix_tag ()
234 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
238 amd64_nacl_tag_legacy_prefix (guint8* code)
240 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
241 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
245 amd64_nacl_tag_rex (guint8* code)
247 mono_native_tls_set_value (nacl_rex_tag, code);
251 amd64_nacl_get_legacy_prefix_tag ()
253 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
257 amd64_nacl_get_rex_tag ()
259 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
262 /* Increment the instruction "depth" described above */
264 amd64_nacl_instruction_pre ()
266 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
268 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
271 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
272 /* alignment if depth == 0 (top level instruction) */
273 /* IN: start, end pointers to instruction beginning and end */
274 /* OUT: start, end pointers to beginning and end after possible alignment */
275 /* GLOBALS: nacl_instruction_depth defined above */
277 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
279 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
281 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
283 g_assert ( depth >= 0 );
285 uintptr_t space_in_block;
287 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
288 /* if legacy prefix is present, and if it was emitted before */
289 /* the start of the instruction sequence, adjust the start */
290 if (prefix != NULL && prefix < *start) {
291 g_assert (*start - prefix <= 3);/* only 3 are allowed */
294 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
295 instlen = (uintptr_t)(*end - *start);
296 /* Only check for instructions which are less than */
297 /* kNaClAlignment. The only instructions that should ever */
298 /* be that long are call sequences, which are already */
299 /* padded out to align the return to the next bundle. */
300 if (instlen > space_in_block && instlen < kNaClAlignment) {
301 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
302 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
303 const size_t length = (size_t)((*end)-(*start));
304 g_assert (length < MAX_NACL_INST_LENGTH);
306 memcpy (copy_of_instruction, *start, length);
307 *start = mono_arch_nacl_pad (*start, space_in_block);
308 memcpy (*start, copy_of_instruction, length);
309 *end = *start + length;
311 amd64_nacl_clear_legacy_prefix_tag ();
312 amd64_nacl_tag_rex (NULL);
316 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
317 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
318 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
319 /* make sure the upper 32-bits are cleared, and use that register in the */
320 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
322 /* pointer to current instruction stream (in the */
323 /* middle of an instruction, after opcode is emitted) */
324 /* basereg/offset/dreg */
325 /* operands of normal membase address */
327 /* pointer to the end of the membase/memindex emit */
328 /* GLOBALS: nacl_rex_tag */
329 /* position in instruction stream that rex prefix was emitted */
330 /* nacl_legacy_prefix_tag */
331 /* (possibly NULL) position in instruction of legacy x86 prefix */
333 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
335 gint8 true_basereg = basereg;
337 /* Cache these values, they might change */
338 /* as new instructions are emitted below. */
339 guint8* rex_tag = amd64_nacl_get_rex_tag ();
340 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
342 /* 'basereg' is given masked to 0x7 at this point, so check */
343 /* the rex prefix to see if this is an extended register. */
344 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
348 #define X86_LEA_OPCODE (0x8D)
350 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
351 guint8* old_instruction_start;
353 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
354 /* 32-bits of the old base register (new index register) */
356 guint8* buf_ptr = buf;
359 g_assert (rex_tag != NULL);
361 if (IS_REX(*rex_tag)) {
362 /* The old rex.B should be the new rex.X */
363 if (*rex_tag & AMD64_REX_B) {
364 *rex_tag |= AMD64_REX_X;
366 /* Since our new base is %r15 set rex.B */
367 *rex_tag |= AMD64_REX_B;
369 /* Shift the instruction by one byte */
370 /* so we can insert a rex prefix */
371 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
373 /* New rex prefix only needs rex.B for %r15 base */
374 *rex_tag = AMD64_REX(AMD64_REX_B);
377 if (legacy_prefix_tag) {
378 old_instruction_start = legacy_prefix_tag;
380 old_instruction_start = rex_tag;
383 /* Clears the upper 32-bits of the previous base register */
384 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
385 insert_len = buf_ptr - buf;
387 /* Move the old instruction forward to make */
388 /* room for 'mov' stored in 'buf_ptr' */
389 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
391 memcpy (old_instruction_start, buf, insert_len);
393 /* Sandboxed replacement for the normal membase_emit */
394 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
397 /* Normal default behavior, emit membase memory location */
398 x86_membase_emit_body (*code, dreg, basereg, offset);
403 static inline unsigned char*
404 amd64_skip_nops (unsigned char* code)
409 if ( code[0] == 0x90) {
413 if ( code[0] == 0x66 && code[1] == 0x90) {
417 if (code[0] == 0x0f && code[1] == 0x1f
418 && code[2] == 0x00) {
422 if (code[0] == 0x0f && code[1] == 0x1f
423 && code[2] == 0x40 && code[3] == 0x00) {
427 if (code[0] == 0x0f && code[1] == 0x1f
428 && code[2] == 0x44 && code[3] == 0x00
429 && code[4] == 0x00) {
433 if (code[0] == 0x66 && code[1] == 0x0f
434 && code[2] == 0x1f && code[3] == 0x44
435 && code[4] == 0x00 && code[5] == 0x00) {
439 if (code[0] == 0x0f && code[1] == 0x1f
440 && code[2] == 0x80 && code[3] == 0x00
441 && code[4] == 0x00 && code[5] == 0x00
442 && code[6] == 0x00) {
446 if (code[0] == 0x0f && code[1] == 0x1f
447 && code[2] == 0x84 && code[3] == 0x00
448 && code[4] == 0x00 && code[5] == 0x00
449 && code[6] == 0x00 && code[7] == 0x00) {
458 mono_arch_nacl_skip_nops (guint8* code)
460 return amd64_skip_nops(code);
463 #endif /*__native_client_codegen__*/
466 amd64_patch (unsigned char* code, gpointer target)
470 #ifdef __native_client_codegen__
471 code = amd64_skip_nops (code);
473 #if defined(__native_client_codegen__) && defined(__native_client__)
474 if (nacl_is_code_address (code)) {
475 /* For tail calls, code is patched after being installed */
476 /* but not through the normal "patch callsite" method. */
477 unsigned char buf[kNaClAlignment];
478 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
480 memcpy (buf, aligned_code, kNaClAlignment);
481 /* Patch a temp buffer of bundle size, */
482 /* then install to actual location. */
483 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
484 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
488 target = nacl_modify_patch_target (target);
492 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
497 if ((code [0] & 0xf8) == 0xb8) {
498 /* amd64_set_reg_template */
499 *(guint64*)(code + 1) = (guint64)target;
501 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
502 /* mov 0(%rip), %dreg */
503 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
505 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
506 /* call *<OFFSET>(%rip) */
507 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
509 else if (code [0] == 0xe8) {
511 gint64 disp = (guint8*)target - (guint8*)code;
512 g_assert (amd64_is_imm32 (disp));
513 x86_patch (code, (unsigned char*)target);
516 x86_patch (code, (unsigned char*)target);
520 mono_amd64_patch (unsigned char* code, gpointer target)
522 amd64_patch (code, target);
531 ArgValuetypeAddrInIReg,
532 ArgNone /* only in pair_storage */
540 /* Only if storage == ArgValuetypeInReg */
541 ArgStorage pair_storage [2];
551 gboolean need_stack_align;
552 gboolean vtype_retaddr;
553 /* The index of the vret arg in the argument list */
560 #define DEBUG(a) if (cfg->verbose_level > 1) a
565 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
567 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
571 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
573 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
577 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
579 ainfo->offset = *stack_size;
581 if (*gr >= PARAM_REGS) {
582 ainfo->storage = ArgOnStack;
583 /* Since the same stack slot size is used for all arg */
584 /* types, it needs to be big enough to hold them all */
585 (*stack_size) += sizeof(mgreg_t);
588 ainfo->storage = ArgInIReg;
589 ainfo->reg = param_regs [*gr];
595 #define FLOAT_PARAM_REGS 4
597 #define FLOAT_PARAM_REGS 8
601 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
603 ainfo->offset = *stack_size;
605 if (*gr >= FLOAT_PARAM_REGS) {
606 ainfo->storage = ArgOnStack;
607 /* Since the same stack slot size is used for both float */
608 /* types, it needs to be big enough to hold them both */
609 (*stack_size) += sizeof(mgreg_t);
612 /* A double register */
614 ainfo->storage = ArgInDoubleSSEReg;
616 ainfo->storage = ArgInFloatSSEReg;
622 typedef enum ArgumentClass {
630 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
632 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
635 ptype = mini_type_get_underlying_type (NULL, type);
636 switch (ptype->type) {
637 case MONO_TYPE_BOOLEAN:
647 case MONO_TYPE_STRING:
648 case MONO_TYPE_OBJECT:
649 case MONO_TYPE_CLASS:
650 case MONO_TYPE_SZARRAY:
652 case MONO_TYPE_FNPTR:
653 case MONO_TYPE_ARRAY:
656 class2 = ARG_CLASS_INTEGER;
661 class2 = ARG_CLASS_INTEGER;
663 class2 = ARG_CLASS_SSE;
667 case MONO_TYPE_TYPEDBYREF:
668 g_assert_not_reached ();
670 case MONO_TYPE_GENERICINST:
671 if (!mono_type_generic_inst_is_valuetype (ptype)) {
672 class2 = ARG_CLASS_INTEGER;
676 case MONO_TYPE_VALUETYPE: {
677 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
680 for (i = 0; i < info->num_fields; ++i) {
682 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
687 g_assert_not_reached ();
691 if (class1 == class2)
693 else if (class1 == ARG_CLASS_NO_CLASS)
695 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
696 class1 = ARG_CLASS_MEMORY;
697 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
698 class1 = ARG_CLASS_INTEGER;
700 class1 = ARG_CLASS_SSE;
704 #ifdef __native_client_codegen__
705 const guint kNaClAlignment = kNaClAlignmentAMD64;
706 const guint kNaClAlignmentMask = kNaClAlignmentMaskAMD64;
708 /* Default alignment for Native Client is 32-byte. */
709 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
711 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
712 /* Check that alignment doesn't cross an alignment boundary. */
714 mono_arch_nacl_pad(guint8 *code, int pad)
716 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
718 if (pad == 0) return code;
719 /* assertion: alignment cannot cross a block boundary */
720 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
721 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
722 while (pad >= kMaxPadding) {
723 amd64_padding (code, kMaxPadding);
726 if (pad != 0) amd64_padding (code, pad);
732 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
734 guint32 *gr, guint32 *fr, guint32 *stack_size)
736 guint32 size, quad, nquads, i;
737 /* Keep track of the size used in each quad so we can */
738 /* use the right size when copying args/return vars. */
739 guint32 quadsize [2] = {8, 8};
740 ArgumentClass args [2];
741 MonoMarshalType *info = NULL;
743 MonoGenericSharingContext tmp_gsctx;
744 gboolean pass_on_stack = FALSE;
747 * The gsctx currently contains no data, it is only used for checking whenever
748 * open types are allowed, some callers like mono_arch_get_argument_info ()
749 * don't pass it to us, so work around that.
754 klass = mono_class_from_mono_type (type);
755 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
757 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
758 /* We pass and return vtypes of size 8 in a register */
759 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
760 pass_on_stack = TRUE;
764 pass_on_stack = TRUE;
768 /* If this struct can't be split up naturally into 8-byte */
769 /* chunks (registers), pass it on the stack. */
770 if (sig->pinvoke && !pass_on_stack) {
774 info = mono_marshal_load_type_info (klass);
776 for (i = 0; i < info->num_fields; ++i) {
777 field_size = mono_marshal_type_size (info->fields [i].field->type,
778 info->fields [i].mspec,
779 &align, TRUE, klass->unicode);
780 if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
781 pass_on_stack = TRUE;
788 /* Allways pass in memory */
789 ainfo->offset = *stack_size;
790 *stack_size += ALIGN_TO (size, 8);
791 ainfo->storage = ArgOnStack;
796 /* FIXME: Handle structs smaller than 8 bytes */
797 //if ((size % 8) != 0)
806 /* Always pass in 1 or 2 integer registers */
807 args [0] = ARG_CLASS_INTEGER;
808 args [1] = ARG_CLASS_INTEGER;
809 /* Only the simplest cases are supported */
810 if (is_return && nquads != 1) {
811 args [0] = ARG_CLASS_MEMORY;
812 args [1] = ARG_CLASS_MEMORY;
816 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
817 * The X87 and SSEUP stuff is left out since there are no such types in
820 info = mono_marshal_load_type_info (klass);
824 if (info->native_size > 16) {
825 ainfo->offset = *stack_size;
826 *stack_size += ALIGN_TO (info->native_size, 8);
827 ainfo->storage = ArgOnStack;
832 switch (info->native_size) {
833 case 1: case 2: case 4: case 8:
837 ainfo->storage = ArgOnStack;
838 ainfo->offset = *stack_size;
839 *stack_size += ALIGN_TO (info->native_size, 8);
842 ainfo->storage = ArgValuetypeAddrInIReg;
844 if (*gr < PARAM_REGS) {
845 ainfo->pair_storage [0] = ArgInIReg;
846 ainfo->pair_regs [0] = param_regs [*gr];
850 ainfo->pair_storage [0] = ArgOnStack;
851 ainfo->offset = *stack_size;
860 args [0] = ARG_CLASS_NO_CLASS;
861 args [1] = ARG_CLASS_NO_CLASS;
862 for (quad = 0; quad < nquads; ++quad) {
865 ArgumentClass class1;
867 if (info->num_fields == 0)
868 class1 = ARG_CLASS_MEMORY;
870 class1 = ARG_CLASS_NO_CLASS;
871 for (i = 0; i < info->num_fields; ++i) {
872 size = mono_marshal_type_size (info->fields [i].field->type,
873 info->fields [i].mspec,
874 &align, TRUE, klass->unicode);
875 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
876 /* Unaligned field */
880 /* Skip fields in other quad */
881 if ((quad == 0) && (info->fields [i].offset >= 8))
883 if ((quad == 1) && (info->fields [i].offset < 8))
886 /* How far into this quad this data extends.*/
887 /* (8 is size of quad) */
888 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
890 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
892 g_assert (class1 != ARG_CLASS_NO_CLASS);
893 args [quad] = class1;
897 /* Post merger cleanup */
898 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
899 args [0] = args [1] = ARG_CLASS_MEMORY;
901 /* Allocate registers */
906 ainfo->storage = ArgValuetypeInReg;
907 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
908 ainfo->nregs = nquads;
909 for (quad = 0; quad < nquads; ++quad) {
910 switch (args [quad]) {
911 case ARG_CLASS_INTEGER:
912 if (*gr >= PARAM_REGS)
913 args [quad] = ARG_CLASS_MEMORY;
915 ainfo->pair_storage [quad] = ArgInIReg;
917 ainfo->pair_regs [quad] = return_regs [*gr];
919 ainfo->pair_regs [quad] = param_regs [*gr];
924 if (*fr >= FLOAT_PARAM_REGS)
925 args [quad] = ARG_CLASS_MEMORY;
927 if (quadsize[quad] <= 4)
928 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
929 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
930 ainfo->pair_regs [quad] = *fr;
934 case ARG_CLASS_MEMORY:
937 g_assert_not_reached ();
941 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
942 /* Revert possible register assignments */
946 ainfo->offset = *stack_size;
948 *stack_size += ALIGN_TO (info->native_size, 8);
950 *stack_size += nquads * sizeof(mgreg_t);
951 ainfo->storage = ArgOnStack;
959 * Obtain information about a call according to the calling convention.
960 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
961 * Draft Version 0.23" document for more information.
964 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
966 guint32 i, gr, fr, pstart;
968 int n = sig->hasthis + sig->param_count;
969 guint32 stack_size = 0;
971 gboolean is_pinvoke = sig->pinvoke;
974 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
976 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
985 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
986 switch (ret_type->type) {
987 case MONO_TYPE_BOOLEAN:
998 case MONO_TYPE_FNPTR:
999 case MONO_TYPE_CLASS:
1000 case MONO_TYPE_OBJECT:
1001 case MONO_TYPE_SZARRAY:
1002 case MONO_TYPE_ARRAY:
1003 case MONO_TYPE_STRING:
1004 cinfo->ret.storage = ArgInIReg;
1005 cinfo->ret.reg = AMD64_RAX;
1009 cinfo->ret.storage = ArgInIReg;
1010 cinfo->ret.reg = AMD64_RAX;
1013 cinfo->ret.storage = ArgInFloatSSEReg;
1014 cinfo->ret.reg = AMD64_XMM0;
1017 cinfo->ret.storage = ArgInDoubleSSEReg;
1018 cinfo->ret.reg = AMD64_XMM0;
1020 case MONO_TYPE_GENERICINST:
1021 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1022 cinfo->ret.storage = ArgInIReg;
1023 cinfo->ret.reg = AMD64_RAX;
1027 case MONO_TYPE_VALUETYPE: {
1028 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1030 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1031 if (cinfo->ret.storage == ArgOnStack) {
1032 cinfo->vtype_retaddr = TRUE;
1033 /* The caller passes the address where the value is stored */
1037 case MONO_TYPE_TYPEDBYREF:
1038 /* Same as a valuetype with size 24 */
1039 cinfo->vtype_retaddr = TRUE;
1041 case MONO_TYPE_VOID:
1044 g_error ("Can't handle as return value 0x%x", sig->ret->type);
1050 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1051 * the first argument, allowing 'this' to be always passed in the first arg reg.
1052 * Also do this if the first argument is a reference type, since virtual calls
1053 * are sometimes made using calli without sig->hasthis set, like in the delegate
1056 if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1058 add_general (&gr, &stack_size, cinfo->args + 0);
1060 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1063 add_general (&gr, &stack_size, &cinfo->ret);
1064 cinfo->vret_arg_index = 1;
1068 add_general (&gr, &stack_size, cinfo->args + 0);
1070 if (cinfo->vtype_retaddr)
1071 add_general (&gr, &stack_size, &cinfo->ret);
1074 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1076 fr = FLOAT_PARAM_REGS;
1078 /* Emit the signature cookie just before the implicit arguments */
1079 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1082 for (i = pstart; i < sig->param_count; ++i) {
1083 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1087 /* The float param registers and other param registers must be the same index on Windows x64.*/
1094 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1095 /* We allways pass the sig cookie on the stack for simplicity */
1097 * Prevent implicit arguments + the sig cookie from being passed
1101 fr = FLOAT_PARAM_REGS;
1103 /* Emit the signature cookie just before the implicit arguments */
1104 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1107 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1108 switch (ptype->type) {
1109 case MONO_TYPE_BOOLEAN:
1112 add_general (&gr, &stack_size, ainfo);
1116 case MONO_TYPE_CHAR:
1117 add_general (&gr, &stack_size, ainfo);
1121 add_general (&gr, &stack_size, ainfo);
1126 case MONO_TYPE_FNPTR:
1127 case MONO_TYPE_CLASS:
1128 case MONO_TYPE_OBJECT:
1129 case MONO_TYPE_STRING:
1130 case MONO_TYPE_SZARRAY:
1131 case MONO_TYPE_ARRAY:
1132 add_general (&gr, &stack_size, ainfo);
1134 case MONO_TYPE_GENERICINST:
1135 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1136 add_general (&gr, &stack_size, ainfo);
1140 case MONO_TYPE_VALUETYPE:
1141 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1143 case MONO_TYPE_TYPEDBYREF:
1145 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1147 stack_size += sizeof (MonoTypedRef);
1148 ainfo->storage = ArgOnStack;
1153 add_general (&gr, &stack_size, ainfo);
1156 add_float (&fr, &stack_size, ainfo, FALSE);
1159 add_float (&fr, &stack_size, ainfo, TRUE);
1162 g_assert_not_reached ();
1166 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1168 fr = FLOAT_PARAM_REGS;
1170 /* Emit the signature cookie just before the implicit arguments */
1171 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1175 // There always is 32 bytes reserved on the stack when calling on Winx64
1179 #ifndef MONO_AMD64_NO_PUSHES
1180 if (stack_size & 0x8) {
1181 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1182 cinfo->need_stack_align = TRUE;
1187 cinfo->stack_usage = stack_size;
1188 cinfo->reg_usage = gr;
1189 cinfo->freg_usage = fr;
1194 * mono_arch_get_argument_info:
1195 * @csig: a method signature
1196 * @param_count: the number of parameters to consider
1197 * @arg_info: an array to store the result infos
1199 * Gathers information on parameters such as size, alignment and
1200 * padding. arg_info should be large enought to hold param_count + 1 entries.
1202 * Returns the size of the argument area on the stack.
1205 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1208 CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1209 guint32 args_size = cinfo->stack_usage;
1211 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1212 if (csig->hasthis) {
1213 arg_info [0].offset = 0;
1216 for (k = 0; k < param_count; k++) {
1217 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1219 arg_info [k + 1].size = 0;
1228 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1233 c1 = get_call_info (NULL, NULL, caller_sig);
1234 c2 = get_call_info (NULL, NULL, callee_sig);
1235 res = c1->stack_usage >= c2->stack_usage;
1236 if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
1237 /* An address on the callee's stack is passed as the first argument */
1247 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
1249 #if defined(MONO_CROSS_COMPILE)
1253 __asm__ __volatile__ ("cpuid"
1254 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
1269 * Initialize the cpu to execute managed code.
1272 mono_arch_cpu_init (void)
1277 /* spec compliance requires running with double precision */
1278 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 fpcw &= ~X86_FPCW_PRECC_MASK;
1280 fpcw |= X86_FPCW_PREC_DOUBLE;
1281 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1282 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1284 /* TODO: This is crashing on Win64 right now.
1285 * _control87 (_PC_53, MCW_PC);
1291 * Initialize architecture specific code.
1294 mono_arch_init (void)
1298 InitializeCriticalSection (&mini_arch_mutex);
1299 #if defined(__native_client_codegen__)
1300 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1301 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1302 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1303 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1306 #ifdef MONO_ARCH_NOMAP32BIT
1307 flags = MONO_MMAP_READ;
1308 /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1309 breakpoint_size = 13;
1310 breakpoint_fault_size = 3;
1312 flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1313 /* amd64_mov_reg_mem () */
1314 breakpoint_size = 8;
1315 breakpoint_fault_size = 8;
1318 /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1319 single_step_fault_size = 4;
1321 ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1322 bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1323 mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1325 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1326 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1327 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1331 * Cleanup architecture specific code.
1334 mono_arch_cleanup (void)
1336 DeleteCriticalSection (&mini_arch_mutex);
1337 #if defined(__native_client_codegen__)
1338 mono_native_tls_free (nacl_instruction_depth);
1339 mono_native_tls_free (nacl_rex_tag);
1340 mono_native_tls_free (nacl_legacy_prefix_tag);
1345 * This function returns the optimizations supported on this cpu.
1348 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
1350 int eax, ebx, ecx, edx;
1354 /* Feature Flags function, flags returned in EDX. */
1355 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1356 if (edx & (1 << 15)) {
1357 opts |= MONO_OPT_CMOV;
1359 opts |= MONO_OPT_FCMOV;
1361 *exclude_mask |= MONO_OPT_FCMOV;
1363 *exclude_mask |= MONO_OPT_CMOV;
1370 * This function test for all SSE functions supported.
1372 * Returns a bitmask corresponding to all supported versions.
1376 mono_arch_cpu_enumerate_simd_versions (void)
1378 int eax, ebx, ecx, edx;
1379 guint32 sse_opts = 0;
1381 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1382 if (edx & (1 << 25))
1383 sse_opts |= SIMD_VERSION_SSE1;
1384 if (edx & (1 << 26))
1385 sse_opts |= SIMD_VERSION_SSE2;
1387 sse_opts |= SIMD_VERSION_SSE3;
1389 sse_opts |= SIMD_VERSION_SSSE3;
1390 if (ecx & (1 << 19))
1391 sse_opts |= SIMD_VERSION_SSE41;
1392 if (ecx & (1 << 20))
1393 sse_opts |= SIMD_VERSION_SSE42;
1396 /* Yes, all this needs to be done to check for sse4a.
1397 See: "Amd: CPUID Specification"
1399 if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1400 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1401 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1402 cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1404 sse_opts |= SIMD_VERSION_SSE4a;
1414 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1419 for (i = 0; i < cfg->num_varinfo; i++) {
1420 MonoInst *ins = cfg->varinfo [i];
1421 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1424 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1427 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1428 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1431 if (mono_is_regsize_var (ins->inst_vtype)) {
1432 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1433 g_assert (i == vmv->idx);
1434 vars = g_list_prepend (vars, vmv);
1438 vars = mono_varlist_sort (cfg, vars, 0);
1444 * mono_arch_compute_omit_fp:
1446 * Determine whenever the frame pointer can be eliminated.
1449 mono_arch_compute_omit_fp (MonoCompile *cfg)
1451 MonoMethodSignature *sig;
1452 MonoMethodHeader *header;
1456 if (cfg->arch.omit_fp_computed)
1459 header = cfg->header;
1461 sig = mono_method_signature (cfg->method);
1463 if (!cfg->arch.cinfo)
1464 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1465 cinfo = cfg->arch.cinfo;
1468 * FIXME: Remove some of the restrictions.
1470 cfg->arch.omit_fp = TRUE;
1471 cfg->arch.omit_fp_computed = TRUE;
1473 #ifdef __native_client_codegen__
1474 /* NaCl modules may not change the value of RBP, so it cannot be */
1475 /* used as a normal register, but it can be used as a frame pointer*/
1476 cfg->disable_omit_fp = TRUE;
1477 cfg->arch.omit_fp = FALSE;
1480 if (cfg->disable_omit_fp)
1481 cfg->arch.omit_fp = FALSE;
1483 if (!debug_omit_fp ())
1484 cfg->arch.omit_fp = FALSE;
1486 if (cfg->method->save_lmf)
1487 cfg->arch.omit_fp = FALSE;
1489 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1490 cfg->arch.omit_fp = FALSE;
1491 if (header->num_clauses)
1492 cfg->arch.omit_fp = FALSE;
1493 if (cfg->param_area)
1494 cfg->arch.omit_fp = FALSE;
1495 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1496 cfg->arch.omit_fp = FALSE;
1497 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1498 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1499 cfg->arch.omit_fp = FALSE;
1500 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1501 ArgInfo *ainfo = &cinfo->args [i];
1503 if (ainfo->storage == ArgOnStack) {
1505 * The stack offset can only be determined when the frame
1508 cfg->arch.omit_fp = FALSE;
1513 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1514 MonoInst *ins = cfg->varinfo [i];
1517 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1522 mono_arch_get_global_int_regs (MonoCompile *cfg)
1526 mono_arch_compute_omit_fp (cfg);
1528 if (cfg->globalra) {
1529 if (cfg->arch.omit_fp)
1530 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1532 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1533 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1534 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1535 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1536 #ifndef __native_client_codegen__
1537 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1540 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1541 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1542 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1543 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1544 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1545 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1546 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1547 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1549 if (cfg->arch.omit_fp)
1550 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1552 /* We use the callee saved registers for global allocation */
1553 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1554 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1555 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1556 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1557 #ifndef __native_client_codegen__
1558 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1561 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1562 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1570 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1575 /* All XMM registers */
1576 for (i = 0; i < 16; ++i)
1577 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1583 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1585 static GList *r = NULL;
1590 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1591 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1592 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1593 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1594 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1595 #ifndef __native_client_codegen__
1596 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1599 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1600 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1601 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1602 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1603 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1604 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1605 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1606 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1608 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1615 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1618 static GList *r = NULL;
1623 for (i = 0; i < AMD64_XMM_NREG; ++i)
1624 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1626 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1633 * mono_arch_regalloc_cost:
1635 * Return the cost, in number of memory references, of the action of
1636 * allocating the variable VMV into a register during global register
1640 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1642 MonoInst *ins = cfg->varinfo [vmv->idx];
1644 if (cfg->method->save_lmf)
1645 /* The register is already saved */
1646 /* substract 1 for the invisible store in the prolog */
1647 return (ins->opcode == OP_ARG) ? 0 : 1;
1650 return (ins->opcode == OP_ARG) ? 1 : 2;
1654 * mono_arch_fill_argument_info:
1656 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1660 mono_arch_fill_argument_info (MonoCompile *cfg)
1662 MonoMethodSignature *sig;
1663 MonoMethodHeader *header;
1668 header = cfg->header;
1670 sig = mono_method_signature (cfg->method);
1672 cinfo = cfg->arch.cinfo;
1675 * Contrary to mono_arch_allocate_vars (), the information should describe
1676 * where the arguments are at the beginning of the method, not where they can be
1677 * accessed during the execution of the method. The later makes no sense for the
1678 * global register allocator, since a variable can be in more than one location.
1680 if (sig->ret->type != MONO_TYPE_VOID) {
1681 switch (cinfo->ret.storage) {
1683 case ArgInFloatSSEReg:
1684 case ArgInDoubleSSEReg:
1685 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1686 cfg->vret_addr->opcode = OP_REGVAR;
1687 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1690 cfg->ret->opcode = OP_REGVAR;
1691 cfg->ret->inst_c0 = cinfo->ret.reg;
1694 case ArgValuetypeInReg:
1695 cfg->ret->opcode = OP_REGOFFSET;
1696 cfg->ret->inst_basereg = -1;
1697 cfg->ret->inst_offset = -1;
1700 g_assert_not_reached ();
1704 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1705 ArgInfo *ainfo = &cinfo->args [i];
1708 ins = cfg->args [i];
1710 if (sig->hasthis && (i == 0))
1711 arg_type = &mono_defaults.object_class->byval_arg;
1713 arg_type = sig->params [i - sig->hasthis];
1715 switch (ainfo->storage) {
1717 case ArgInFloatSSEReg:
1718 case ArgInDoubleSSEReg:
1719 ins->opcode = OP_REGVAR;
1720 ins->inst_c0 = ainfo->reg;
1723 ins->opcode = OP_REGOFFSET;
1724 ins->inst_basereg = -1;
1725 ins->inst_offset = -1;
1727 case ArgValuetypeInReg:
1729 ins->opcode = OP_NOP;
1732 g_assert_not_reached ();
1738 mono_arch_allocate_vars (MonoCompile *cfg)
1740 MonoMethodSignature *sig;
1741 MonoMethodHeader *header;
1744 guint32 locals_stack_size, locals_stack_align;
1748 header = cfg->header;
1750 sig = mono_method_signature (cfg->method);
1752 cinfo = cfg->arch.cinfo;
1754 mono_arch_compute_omit_fp (cfg);
1757 * We use the ABI calling conventions for managed code as well.
1758 * Exception: valuetypes are only sometimes passed or returned in registers.
1762 * The stack looks like this:
1763 * <incoming arguments passed on the stack>
1765 * <lmf/caller saved registers>
1768 * <localloc area> -> grows dynamically
1772 if (cfg->arch.omit_fp) {
1773 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1774 cfg->frame_reg = AMD64_RSP;
1777 /* Locals are allocated backwards from %fp */
1778 cfg->frame_reg = AMD64_RBP;
1782 if (cfg->method->save_lmf) {
1783 /* The LMF var is allocated normally */
1785 if (cfg->arch.omit_fp)
1786 cfg->arch.reg_save_area_offset = offset;
1787 /* Reserve space for caller saved registers */
1788 for (i = 0; i < AMD64_NREG; ++i)
1789 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1790 offset += sizeof(mgreg_t);
1794 if (sig->ret->type != MONO_TYPE_VOID) {
1795 switch (cinfo->ret.storage) {
1797 case ArgInFloatSSEReg:
1798 case ArgInDoubleSSEReg:
1799 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1800 if (cfg->globalra) {
1801 cfg->vret_addr->opcode = OP_REGVAR;
1802 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1804 /* The register is volatile */
1805 cfg->vret_addr->opcode = OP_REGOFFSET;
1806 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1807 if (cfg->arch.omit_fp) {
1808 cfg->vret_addr->inst_offset = offset;
1812 cfg->vret_addr->inst_offset = -offset;
1814 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1815 printf ("vret_addr =");
1816 mono_print_ins (cfg->vret_addr);
1821 cfg->ret->opcode = OP_REGVAR;
1822 cfg->ret->inst_c0 = cinfo->ret.reg;
1825 case ArgValuetypeInReg:
1826 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1827 cfg->ret->opcode = OP_REGOFFSET;
1828 cfg->ret->inst_basereg = cfg->frame_reg;
1829 if (cfg->arch.omit_fp) {
1830 cfg->ret->inst_offset = offset;
1831 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1833 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1834 cfg->ret->inst_offset = - offset;
1838 g_assert_not_reached ();
1841 cfg->ret->dreg = cfg->ret->inst_c0;
1844 /* Allocate locals */
1845 if (!cfg->globalra) {
1846 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1847 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1848 char *mname = mono_method_full_name (cfg->method, TRUE);
1849 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1850 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1855 if (locals_stack_align) {
1856 offset += (locals_stack_align - 1);
1857 offset &= ~(locals_stack_align - 1);
1859 if (cfg->arch.omit_fp) {
1860 cfg->locals_min_stack_offset = offset;
1861 cfg->locals_max_stack_offset = offset + locals_stack_size;
1863 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1864 cfg->locals_max_stack_offset = - offset;
1867 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1868 if (offsets [i] != -1) {
1869 MonoInst *ins = cfg->varinfo [i];
1870 ins->opcode = OP_REGOFFSET;
1871 ins->inst_basereg = cfg->frame_reg;
1872 if (cfg->arch.omit_fp)
1873 ins->inst_offset = (offset + offsets [i]);
1875 ins->inst_offset = - (offset + offsets [i]);
1876 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1879 offset += locals_stack_size;
1882 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1883 g_assert (!cfg->arch.omit_fp);
1884 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1885 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1888 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1889 ins = cfg->args [i];
1890 if (ins->opcode != OP_REGVAR) {
1891 ArgInfo *ainfo = &cinfo->args [i];
1892 gboolean inreg = TRUE;
1895 if (sig->hasthis && (i == 0))
1896 arg_type = &mono_defaults.object_class->byval_arg;
1898 arg_type = sig->params [i - sig->hasthis];
1900 if (cfg->globalra) {
1901 /* The new allocator needs info about the original locations of the arguments */
1902 switch (ainfo->storage) {
1904 case ArgInFloatSSEReg:
1905 case ArgInDoubleSSEReg:
1906 ins->opcode = OP_REGVAR;
1907 ins->inst_c0 = ainfo->reg;
1910 g_assert (!cfg->arch.omit_fp);
1911 ins->opcode = OP_REGOFFSET;
1912 ins->inst_basereg = cfg->frame_reg;
1913 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1915 case ArgValuetypeInReg:
1916 ins->opcode = OP_REGOFFSET;
1917 ins->inst_basereg = cfg->frame_reg;
1918 /* These arguments are saved to the stack in the prolog */
1919 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1920 if (cfg->arch.omit_fp) {
1921 ins->inst_offset = offset;
1922 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1924 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1925 ins->inst_offset = - offset;
1929 g_assert_not_reached ();
1935 /* FIXME: Allocate volatile arguments to registers */
1936 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1940 * Under AMD64, all registers used to pass arguments to functions
1941 * are volatile across calls.
1942 * FIXME: Optimize this.
1944 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1947 ins->opcode = OP_REGOFFSET;
1949 switch (ainfo->storage) {
1951 case ArgInFloatSSEReg:
1952 case ArgInDoubleSSEReg:
1954 ins->opcode = OP_REGVAR;
1955 ins->dreg = ainfo->reg;
1959 g_assert (!cfg->arch.omit_fp);
1960 ins->opcode = OP_REGOFFSET;
1961 ins->inst_basereg = cfg->frame_reg;
1962 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1964 case ArgValuetypeInReg:
1966 case ArgValuetypeAddrInIReg: {
1968 g_assert (!cfg->arch.omit_fp);
1970 MONO_INST_NEW (cfg, indir, 0);
1971 indir->opcode = OP_REGOFFSET;
1972 if (ainfo->pair_storage [0] == ArgInIReg) {
1973 indir->inst_basereg = cfg->frame_reg;
1974 offset = ALIGN_TO (offset, sizeof (gpointer));
1975 offset += (sizeof (gpointer));
1976 indir->inst_offset = - offset;
1979 indir->inst_basereg = cfg->frame_reg;
1980 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1983 ins->opcode = OP_VTARG_ADDR;
1984 ins->inst_left = indir;
1992 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1993 ins->opcode = OP_REGOFFSET;
1994 ins->inst_basereg = cfg->frame_reg;
1995 /* These arguments are saved to the stack in the prolog */
1996 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1997 if (cfg->arch.omit_fp) {
1998 ins->inst_offset = offset;
1999 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2000 // Arguments are yet supported by the stack map creation code
2001 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2003 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2004 ins->inst_offset = - offset;
2005 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2011 cfg->stack_offset = offset;
2015 mono_arch_create_vars (MonoCompile *cfg)
2017 MonoMethodSignature *sig;
2020 sig = mono_method_signature (cfg->method);
2022 if (!cfg->arch.cinfo)
2023 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2024 cinfo = cfg->arch.cinfo;
2026 if (cinfo->ret.storage == ArgValuetypeInReg)
2027 cfg->ret_var_is_local = TRUE;
2029 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
2030 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2031 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2032 printf ("vret_addr = ");
2033 mono_print_ins (cfg->vret_addr);
2037 if (cfg->gen_seq_points) {
2040 if (cfg->compile_aot) {
2041 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2042 ins->flags |= MONO_INST_VOLATILE;
2043 cfg->arch.seq_point_info_var = ins;
2046 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2047 ins->flags |= MONO_INST_VOLATILE;
2048 cfg->arch.ss_trigger_page_var = ins;
2051 #ifdef MONO_AMD64_NO_PUSHES
2053 * When this is set, we pass arguments on the stack by moves, and by allocating
2054 * a bigger stack frame, instead of pushes.
2055 * Pushes complicate exception handling because the arguments on the stack have
2056 * to be popped each time a frame is unwound. They also make fp elimination
2058 * FIXME: This doesn't work inside filter/finally clauses, since those execute
2059 * on a new frame which doesn't include a param area.
2061 cfg->arch.no_pushes = TRUE;
2064 if (cfg->method->save_lmf) {
2065 MonoInst *lmf_var = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2066 lmf_var->flags |= MONO_INST_VOLATILE;
2067 lmf_var->flags |= MONO_INST_LMF;
2068 cfg->arch.lmf_var = lmf_var;
2071 #ifndef MONO_AMD64_NO_PUSHES
2072 cfg->arch_eh_jit_info = 1;
2077 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2083 MONO_INST_NEW (cfg, ins, OP_MOVE);
2084 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2085 ins->sreg1 = tree->dreg;
2086 MONO_ADD_INS (cfg->cbb, ins);
2087 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2089 case ArgInFloatSSEReg:
2090 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2091 ins->dreg = mono_alloc_freg (cfg);
2092 ins->sreg1 = tree->dreg;
2093 MONO_ADD_INS (cfg->cbb, ins);
2095 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2097 case ArgInDoubleSSEReg:
2098 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2099 ins->dreg = mono_alloc_freg (cfg);
2100 ins->sreg1 = tree->dreg;
2101 MONO_ADD_INS (cfg->cbb, ins);
2103 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2107 g_assert_not_reached ();
2112 arg_storage_to_load_membase (ArgStorage storage)
2116 #if defined(__mono_ilp32__)
2117 return OP_LOADI8_MEMBASE;
2119 return OP_LOAD_MEMBASE;
2121 case ArgInDoubleSSEReg:
2122 return OP_LOADR8_MEMBASE;
2123 case ArgInFloatSSEReg:
2124 return OP_LOADR4_MEMBASE;
2126 g_assert_not_reached ();
2133 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2136 MonoMethodSignature *tmp_sig;
2139 if (call->tail_call)
2142 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2145 * mono_ArgIterator_Setup assumes the signature cookie is
2146 * passed first and all the arguments which were before it are
2147 * passed on the stack after the signature. So compensate by
2148 * passing a different signature.
2150 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2151 tmp_sig->param_count -= call->signature->sentinelpos;
2152 tmp_sig->sentinelpos = 0;
2153 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2155 sig_reg = mono_alloc_ireg (cfg);
2156 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2158 if (cfg->arch.no_pushes) {
2159 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2161 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2162 arg->sreg1 = sig_reg;
2163 MONO_ADD_INS (cfg->cbb, arg);
2167 static inline LLVMArgStorage
2168 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2172 return LLVMArgInIReg;
2176 g_assert_not_reached ();
2183 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2189 LLVMCallInfo *linfo;
2192 n = sig->param_count + sig->hasthis;
2194 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2196 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2199 * LLVM always uses the native ABI while we use our own ABI, the
2200 * only difference is the handling of vtypes:
2201 * - we only pass/receive them in registers in some cases, and only
2202 * in 1 or 2 integer registers.
2204 if (cinfo->ret.storage == ArgValuetypeInReg) {
2206 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2207 cfg->disable_llvm = TRUE;
2211 linfo->ret.storage = LLVMArgVtypeInReg;
2212 for (j = 0; j < 2; ++j)
2213 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2216 if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
2217 /* Vtype returned using a hidden argument */
2218 linfo->ret.storage = LLVMArgVtypeRetAddr;
2219 linfo->vret_arg_index = cinfo->vret_arg_index;
2222 for (i = 0; i < n; ++i) {
2223 ainfo = cinfo->args + i;
2225 if (i >= sig->hasthis)
2226 t = sig->params [i - sig->hasthis];
2228 t = &mono_defaults.int_class->byval_arg;
2230 linfo->args [i].storage = LLVMArgNone;
2232 switch (ainfo->storage) {
2234 linfo->args [i].storage = LLVMArgInIReg;
2236 case ArgInDoubleSSEReg:
2237 case ArgInFloatSSEReg:
2238 linfo->args [i].storage = LLVMArgInFPReg;
2241 if (MONO_TYPE_ISSTRUCT (t)) {
2242 linfo->args [i].storage = LLVMArgVtypeByVal;
2244 linfo->args [i].storage = LLVMArgInIReg;
2246 if (t->type == MONO_TYPE_R4)
2247 linfo->args [i].storage = LLVMArgInFPReg;
2248 else if (t->type == MONO_TYPE_R8)
2249 linfo->args [i].storage = LLVMArgInFPReg;
2253 case ArgValuetypeInReg:
2255 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2256 cfg->disable_llvm = TRUE;
2260 linfo->args [i].storage = LLVMArgVtypeInReg;
2261 for (j = 0; j < 2; ++j)
2262 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2265 cfg->exception_message = g_strdup ("ainfo->storage");
2266 cfg->disable_llvm = TRUE;
2276 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2279 MonoMethodSignature *sig;
2280 int i, n, stack_size;
2286 sig = call->signature;
2287 n = sig->param_count + sig->hasthis;
2289 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2291 if (COMPILE_LLVM (cfg)) {
2292 /* We shouldn't be called in the llvm case */
2293 cfg->disable_llvm = TRUE;
2297 if (cinfo->need_stack_align) {
2298 if (!cfg->arch.no_pushes)
2299 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2303 * Emit all arguments which are passed on the stack to prevent register
2304 * allocation problems.
2306 if (cfg->arch.no_pushes) {
2307 for (i = 0; i < n; ++i) {
2309 ainfo = cinfo->args + i;
2311 in = call->args [i];
2313 if (sig->hasthis && i == 0)
2314 t = &mono_defaults.object_class->byval_arg;
2316 t = sig->params [i - sig->hasthis];
2318 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2320 if (t->type == MONO_TYPE_R4)
2321 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2322 else if (t->type == MONO_TYPE_R8)
2323 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2325 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2327 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2329 if (cfg->compute_gc_maps) {
2332 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2339 * Emit all parameters passed in registers in non-reverse order for better readability
2340 * and to help the optimization in emit_prolog ().
2342 for (i = 0; i < n; ++i) {
2343 ainfo = cinfo->args + i;
2345 in = call->args [i];
2347 if (ainfo->storage == ArgInIReg)
2348 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2351 for (i = n - 1; i >= 0; --i) {
2352 ainfo = cinfo->args + i;
2354 in = call->args [i];
2356 switch (ainfo->storage) {
2360 case ArgInFloatSSEReg:
2361 case ArgInDoubleSSEReg:
2362 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2365 case ArgValuetypeInReg:
2366 case ArgValuetypeAddrInIReg:
2367 if (ainfo->storage == ArgOnStack && call->tail_call) {
2368 MonoInst *call_inst = (MonoInst*)call;
2369 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2370 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2371 } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2375 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2376 size = sizeof (MonoTypedRef);
2377 align = sizeof (gpointer);
2381 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2384 * Other backends use mono_type_stack_size (), but that
2385 * aligns the size to 8, which is larger than the size of
2386 * the source, leading to reads of invalid memory if the
2387 * source is at the end of address space.
2389 size = mono_class_value_size (in->klass, &align);
2392 g_assert (in->klass);
2394 if (ainfo->storage == ArgOnStack && size >= 10000) {
2395 /* Avoid asserts in emit_memcpy () */
2396 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2397 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2398 /* Continue normally */
2402 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2403 arg->sreg1 = in->dreg;
2404 arg->klass = in->klass;
2405 arg->backend.size = size;
2406 arg->inst_p0 = call;
2407 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2408 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2410 MONO_ADD_INS (cfg->cbb, arg);
2413 if (cfg->arch.no_pushes) {
2416 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2417 arg->sreg1 = in->dreg;
2418 if (!sig->params [i - sig->hasthis]->byref) {
2419 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2420 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2421 arg->opcode = OP_STORER4_MEMBASE_REG;
2422 arg->inst_destbasereg = X86_ESP;
2423 arg->inst_offset = 0;
2424 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2425 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2426 arg->opcode = OP_STORER8_MEMBASE_REG;
2427 arg->inst_destbasereg = X86_ESP;
2428 arg->inst_offset = 0;
2431 MONO_ADD_INS (cfg->cbb, arg);
2436 g_assert_not_reached ();
2439 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2440 /* Emit the signature cookie just before the implicit arguments */
2441 emit_sig_cookie (cfg, call, cinfo);
2444 /* Handle the case where there are no implicit arguments */
2445 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2446 emit_sig_cookie (cfg, call, cinfo);
2448 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2451 if (cinfo->ret.storage == ArgValuetypeInReg) {
2452 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2454 * Tell the JIT to use a more efficient calling convention: call using
2455 * OP_CALL, compute the result location after the call, and save the
2458 call->vret_in_reg = TRUE;
2460 * Nullify the instruction computing the vret addr to enable
2461 * future optimizations.
2464 NULLIFY_INS (call->vret_var);
2466 if (call->tail_call)
2469 * The valuetype is in RAX:RDX after the call, need to be copied to
2470 * the stack. Push the address here, so the call instruction can
2473 if (!cfg->arch.vret_addr_loc) {
2474 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2475 /* Prevent it from being register allocated or optimized away */
2476 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2479 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2483 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2484 vtarg->sreg1 = call->vret_var->dreg;
2485 vtarg->dreg = mono_alloc_preg (cfg);
2486 MONO_ADD_INS (cfg->cbb, vtarg);
2488 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2493 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2494 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2498 if (cfg->method->save_lmf) {
2499 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2500 MONO_ADD_INS (cfg->cbb, arg);
2503 call->stack_usage = cinfo->stack_usage;
2507 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2510 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2511 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2512 int size = ins->backend.size;
2514 if (ainfo->storage == ArgValuetypeInReg) {
2518 for (part = 0; part < 2; ++part) {
2519 if (ainfo->pair_storage [part] == ArgNone)
2522 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2523 load->inst_basereg = src->dreg;
2524 load->inst_offset = part * sizeof(mgreg_t);
2526 switch (ainfo->pair_storage [part]) {
2528 load->dreg = mono_alloc_ireg (cfg);
2530 case ArgInDoubleSSEReg:
2531 case ArgInFloatSSEReg:
2532 load->dreg = mono_alloc_freg (cfg);
2535 g_assert_not_reached ();
2537 MONO_ADD_INS (cfg->cbb, load);
2539 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2541 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2542 MonoInst *vtaddr, *load;
2543 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2545 g_assert (!cfg->arch.no_pushes);
2547 MONO_INST_NEW (cfg, load, OP_LDADDR);
2548 load->inst_p0 = vtaddr;
2549 vtaddr->flags |= MONO_INST_INDIRECT;
2550 load->type = STACK_MP;
2551 load->klass = vtaddr->klass;
2552 load->dreg = mono_alloc_ireg (cfg);
2553 MONO_ADD_INS (cfg->cbb, load);
2554 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2556 if (ainfo->pair_storage [0] == ArgInIReg) {
2557 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2558 arg->dreg = mono_alloc_ireg (cfg);
2559 arg->sreg1 = load->dreg;
2561 MONO_ADD_INS (cfg->cbb, arg);
2562 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2564 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2565 arg->sreg1 = load->dreg;
2566 MONO_ADD_INS (cfg->cbb, arg);
2570 if (cfg->arch.no_pushes) {
2571 int dreg = mono_alloc_ireg (cfg);
2573 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2574 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2576 /* Can't use this for < 8 since it does an 8 byte memory load */
2577 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2578 arg->inst_basereg = src->dreg;
2579 arg->inst_offset = 0;
2580 MONO_ADD_INS (cfg->cbb, arg);
2582 } else if (size <= 40) {
2583 if (cfg->arch.no_pushes) {
2584 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2586 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2587 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2590 if (cfg->arch.no_pushes) {
2591 // FIXME: Code growth
2592 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2594 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2595 arg->inst_basereg = src->dreg;
2596 arg->inst_offset = 0;
2597 arg->inst_imm = size;
2598 MONO_ADD_INS (cfg->cbb, arg);
2602 if (cfg->compute_gc_maps) {
2604 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2610 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2612 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2614 if (ret->type == MONO_TYPE_R4) {
2615 if (COMPILE_LLVM (cfg))
2616 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2618 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2620 } else if (ret->type == MONO_TYPE_R8) {
2621 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2625 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2628 #endif /* DISABLE_JIT */
2630 #define EMIT_COND_BRANCH(ins,cond,sign) \
2631 if (ins->inst_true_bb->native_offset) { \
2632 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2634 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2635 if ((cfg->opt & MONO_OPT_BRANCH) && \
2636 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2637 x86_branch8 (code, cond, 0, sign); \
2639 x86_branch32 (code, cond, 0, sign); \
2643 MonoMethodSignature *sig;
2648 mgreg_t regs [PARAM_REGS];
2654 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2662 switch (cinfo->ret.storage) {
2666 case ArgValuetypeInReg: {
2667 ArgInfo *ainfo = &cinfo->ret;
2669 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2671 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2679 for (i = 0; i < cinfo->nargs; ++i) {
2680 ArgInfo *ainfo = &cinfo->args [i];
2681 switch (ainfo->storage) {
2684 case ArgValuetypeInReg:
2685 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2687 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2699 * mono_arch_dyn_call_prepare:
2701 * Return a pointer to an arch-specific structure which contains information
2702 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2703 * supported for SIG.
2704 * This function is equivalent to ffi_prep_cif in libffi.
2707 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2709 ArchDynCallInfo *info;
2712 cinfo = get_call_info (NULL, NULL, sig);
2714 if (!dyn_call_supported (sig, cinfo)) {
2719 info = g_new0 (ArchDynCallInfo, 1);
2720 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2722 info->cinfo = cinfo;
2724 return (MonoDynCallInfo*)info;
2728 * mono_arch_dyn_call_free:
2730 * Free a MonoDynCallInfo structure.
2733 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2735 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2737 g_free (ainfo->cinfo);
2741 #if !defined(__native_client__)
2742 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2743 #define GREG_TO_PTR(greg) (gpointer)(greg)
2745 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2746 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2747 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2751 * mono_arch_get_start_dyn_call:
2753 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2754 * store the result into BUF.
2755 * ARGS should be an array of pointers pointing to the arguments.
2756 * RET should point to a memory buffer large enought to hold the result of the
2758 * This function should be as fast as possible, any work which does not depend
2759 * on the actual values of the arguments should be done in
2760 * mono_arch_dyn_call_prepare ().
2761 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2765 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2767 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2768 DynCallArgs *p = (DynCallArgs*)buf;
2769 int arg_index, greg, i, pindex;
2770 MonoMethodSignature *sig = dinfo->sig;
2772 g_assert (buf_len >= sizeof (DynCallArgs));
2781 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2782 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2787 if (dinfo->cinfo->vtype_retaddr)
2788 p->regs [greg ++] = PTR_TO_GREG(ret);
2790 for (i = pindex; i < sig->param_count; i++) {
2791 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2792 gpointer *arg = args [arg_index ++];
2795 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2800 case MONO_TYPE_STRING:
2801 case MONO_TYPE_CLASS:
2802 case MONO_TYPE_ARRAY:
2803 case MONO_TYPE_SZARRAY:
2804 case MONO_TYPE_OBJECT:
2808 #if !defined(__mono_ilp32__)
2812 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2813 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2815 #if defined(__mono_ilp32__)
2818 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2819 p->regs [greg ++] = *(guint64*)(arg);
2822 case MONO_TYPE_BOOLEAN:
2824 p->regs [greg ++] = *(guint8*)(arg);
2827 p->regs [greg ++] = *(gint8*)(arg);
2830 p->regs [greg ++] = *(gint16*)(arg);
2833 case MONO_TYPE_CHAR:
2834 p->regs [greg ++] = *(guint16*)(arg);
2837 p->regs [greg ++] = *(gint32*)(arg);
2840 p->regs [greg ++] = *(guint32*)(arg);
2842 case MONO_TYPE_GENERICINST:
2843 if (MONO_TYPE_IS_REFERENCE (t)) {
2844 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2849 case MONO_TYPE_VALUETYPE: {
2850 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2852 g_assert (ainfo->storage == ArgValuetypeInReg);
2853 if (ainfo->pair_storage [0] != ArgNone) {
2854 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2855 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2857 if (ainfo->pair_storage [1] != ArgNone) {
2858 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2859 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2864 g_assert_not_reached ();
2868 g_assert (greg <= PARAM_REGS);
2872 * mono_arch_finish_dyn_call:
2874 * Store the result of a dyn call into the return value buffer passed to
2875 * start_dyn_call ().
2876 * This function should be as fast as possible, any work which does not depend
2877 * on the actual values of the arguments should be done in
2878 * mono_arch_dyn_call_prepare ().
2881 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2883 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2884 MonoMethodSignature *sig = dinfo->sig;
2885 guint8 *ret = ((DynCallArgs*)buf)->ret;
2886 mgreg_t res = ((DynCallArgs*)buf)->res;
2888 switch (mono_type_get_underlying_type (sig->ret)->type) {
2889 case MONO_TYPE_VOID:
2890 *(gpointer*)ret = NULL;
2892 case MONO_TYPE_STRING:
2893 case MONO_TYPE_CLASS:
2894 case MONO_TYPE_ARRAY:
2895 case MONO_TYPE_SZARRAY:
2896 case MONO_TYPE_OBJECT:
2900 *(gpointer*)ret = GREG_TO_PTR(res);
2906 case MONO_TYPE_BOOLEAN:
2907 *(guint8*)ret = res;
2910 *(gint16*)ret = res;
2913 case MONO_TYPE_CHAR:
2914 *(guint16*)ret = res;
2917 *(gint32*)ret = res;
2920 *(guint32*)ret = res;
2923 *(gint64*)ret = res;
2926 *(guint64*)ret = res;
2928 case MONO_TYPE_GENERICINST:
2929 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2930 *(gpointer*)ret = GREG_TO_PTR(res);
2935 case MONO_TYPE_VALUETYPE:
2936 if (dinfo->cinfo->vtype_retaddr) {
2939 ArgInfo *ainfo = &dinfo->cinfo->ret;
2941 g_assert (ainfo->storage == ArgValuetypeInReg);
2943 if (ainfo->pair_storage [0] != ArgNone) {
2944 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2945 ((mgreg_t*)ret)[0] = res;
2948 g_assert (ainfo->pair_storage [1] == ArgNone);
2952 g_assert_not_reached ();
2956 /* emit an exception if condition is fail */
2957 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2959 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2960 if (tins == NULL) { \
2961 mono_add_patch_info (cfg, code - cfg->native_code, \
2962 MONO_PATCH_INFO_EXC, exc_name); \
2963 x86_branch32 (code, cond, 0, signed); \
2965 EMIT_COND_BRANCH (tins, cond, signed); \
2969 #define EMIT_FPCOMPARE(code) do { \
2970 amd64_fcompp (code); \
2971 amd64_fnstsw (code); \
2974 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2975 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2976 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2977 amd64_ ##op (code); \
2978 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2979 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2983 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2985 gboolean no_patch = FALSE;
2988 * FIXME: Add support for thunks
2991 gboolean near_call = FALSE;
2994 * Indirect calls are expensive so try to make a near call if possible.
2995 * The caller memory is allocated by the code manager so it is
2996 * guaranteed to be at a 32 bit offset.
2999 if (patch_type != MONO_PATCH_INFO_ABS) {
3000 /* The target is in memory allocated using the code manager */
3003 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3004 if (((MonoMethod*)data)->klass->image->aot_module)
3005 /* The callee might be an AOT method */
3007 if (((MonoMethod*)data)->dynamic)
3008 /* The target is in malloc-ed memory */
3012 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3014 * The call might go directly to a native function without
3017 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
3019 gconstpointer target = mono_icall_get_wrapper (mi);
3020 if ((((guint64)target) >> 32) != 0)
3026 if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
3028 * This is not really an optimization, but required because the
3029 * generic class init trampolines use R11 to pass the vtable.
3033 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3035 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
3036 strstr (cfg->method->name, info->name)) {
3037 /* A call to the wrapped function */
3038 if ((((guint64)data) >> 32) == 0)
3042 else if (info->func == info->wrapper) {
3044 if ((((guint64)info->func) >> 32) == 0)
3048 /* See the comment in mono_codegen () */
3049 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3053 else if ((((guint64)data) >> 32) == 0) {
3060 if (cfg->method->dynamic)
3061 /* These methods are allocated using malloc */
3064 #ifdef MONO_ARCH_NOMAP32BIT
3068 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3069 if (optimize_for_xen)
3072 if (cfg->compile_aot) {
3079 * Align the call displacement to an address divisible by 4 so it does
3080 * not span cache lines. This is required for code patching to work on SMP
3083 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3084 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3085 amd64_padding (code, pad_size);
3087 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3088 amd64_call_code (code, 0);
3091 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3092 amd64_set_reg_template (code, GP_SCRATCH_REG);
3093 amd64_call_reg (code, GP_SCRATCH_REG);
3100 static inline guint8*
3101 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3104 if (win64_adjust_stack)
3105 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3107 code = emit_call_body (cfg, code, patch_type, data);
3109 if (win64_adjust_stack)
3110 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3117 store_membase_imm_to_store_membase_reg (int opcode)
3120 case OP_STORE_MEMBASE_IMM:
3121 return OP_STORE_MEMBASE_REG;
3122 case OP_STOREI4_MEMBASE_IMM:
3123 return OP_STOREI4_MEMBASE_REG;
3124 case OP_STOREI8_MEMBASE_IMM:
3125 return OP_STOREI8_MEMBASE_REG;
3133 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3136 * mono_arch_peephole_pass_1:
3138 * Perform peephole opts which should/can be performed before local regalloc
3141 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3145 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3146 MonoInst *last_ins = ins->prev;
3148 switch (ins->opcode) {
3152 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3154 * X86_LEA is like ADD, but doesn't have the
3155 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3156 * its operand to 64 bit.
3158 ins->opcode = OP_X86_LEA_MEMBASE;
3159 ins->inst_basereg = ins->sreg1;
3164 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3168 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3169 * the latter has length 2-3 instead of 6 (reverse constant
3170 * propagation). These instruction sequences are very common
3171 * in the initlocals bblock.
3173 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3174 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3175 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3176 ins2->sreg1 = ins->dreg;
3177 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3179 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3188 case OP_COMPARE_IMM:
3189 case OP_LCOMPARE_IMM:
3190 /* OP_COMPARE_IMM (reg, 0)
3192 * OP_AMD64_TEST_NULL (reg)
3195 ins->opcode = OP_AMD64_TEST_NULL;
3197 case OP_ICOMPARE_IMM:
3199 ins->opcode = OP_X86_TEST_NULL;
3201 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3203 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3204 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3206 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3207 * OP_COMPARE_IMM reg, imm
3209 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3211 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3212 ins->inst_basereg == last_ins->inst_destbasereg &&
3213 ins->inst_offset == last_ins->inst_offset) {
3214 ins->opcode = OP_ICOMPARE_IMM;
3215 ins->sreg1 = last_ins->sreg1;
3217 /* check if we can remove cmp reg,0 with test null */
3219 ins->opcode = OP_X86_TEST_NULL;
3225 mono_peephole_ins (bb, ins);
3230 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3234 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3235 switch (ins->opcode) {
3238 /* reg = 0 -> XOR (reg, reg) */
3239 /* XOR sets cflags on x86, so we cant do it always */
3240 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3241 ins->opcode = OP_LXOR;
3242 ins->sreg1 = ins->dreg;
3243 ins->sreg2 = ins->dreg;
3251 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3252 * 0 result into 64 bits.
3254 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3255 ins->opcode = OP_IXOR;
3259 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3263 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3264 * the latter has length 2-3 instead of 6 (reverse constant
3265 * propagation). These instruction sequences are very common
3266 * in the initlocals bblock.
3268 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3269 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3270 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3271 ins2->sreg1 = ins->dreg;
3272 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3274 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3284 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3285 ins->opcode = OP_X86_INC_REG;
3288 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3289 ins->opcode = OP_X86_DEC_REG;
3293 mono_peephole_ins (bb, ins);
3297 #define NEW_INS(cfg,ins,dest,op) do { \
3298 MONO_INST_NEW ((cfg), (dest), (op)); \
3299 (dest)->cil_code = (ins)->cil_code; \
3300 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3304 * mono_arch_lowering_pass:
3306 * Converts complex opcodes into simpler ones so that each IR instruction
3307 * corresponds to one machine instruction.
3310 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3312 MonoInst *ins, *n, *temp;
3315 * FIXME: Need to add more instructions, but the current machine
3316 * description can't model some parts of the composite instructions like
3319 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3320 switch (ins->opcode) {
3324 case OP_IDIV_UN_IMM:
3325 case OP_IREM_UN_IMM:
3326 mono_decompose_op_imm (cfg, bb, ins);
3329 /* Keep the opcode if we can implement it efficiently */
3330 if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
3331 mono_decompose_op_imm (cfg, bb, ins);
3333 case OP_COMPARE_IMM:
3334 case OP_LCOMPARE_IMM:
3335 if (!amd64_is_imm32 (ins->inst_imm)) {
3336 NEW_INS (cfg, ins, temp, OP_I8CONST);
3337 temp->inst_c0 = ins->inst_imm;
3338 temp->dreg = mono_alloc_ireg (cfg);
3339 ins->opcode = OP_COMPARE;
3340 ins->sreg2 = temp->dreg;
3343 #ifndef __mono_ilp32__
3344 case OP_LOAD_MEMBASE:
3346 case OP_LOADI8_MEMBASE:
3347 #ifndef __native_client_codegen__
3348 /* Don't generate memindex opcodes (to simplify */
3349 /* read sandboxing) */
3350 if (!amd64_is_imm32 (ins->inst_offset)) {
3351 NEW_INS (cfg, ins, temp, OP_I8CONST);
3352 temp->inst_c0 = ins->inst_offset;
3353 temp->dreg = mono_alloc_ireg (cfg);
3354 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3355 ins->inst_indexreg = temp->dreg;
3359 #ifndef __mono_ilp32__
3360 case OP_STORE_MEMBASE_IMM:
3362 case OP_STOREI8_MEMBASE_IMM:
3363 if (!amd64_is_imm32 (ins->inst_imm)) {
3364 NEW_INS (cfg, ins, temp, OP_I8CONST);
3365 temp->inst_c0 = ins->inst_imm;
3366 temp->dreg = mono_alloc_ireg (cfg);
3367 ins->opcode = OP_STOREI8_MEMBASE_REG;
3368 ins->sreg1 = temp->dreg;
3371 #ifdef MONO_ARCH_SIMD_INTRINSICS
3372 case OP_EXPAND_I1: {
3373 int temp_reg1 = mono_alloc_ireg (cfg);
3374 int temp_reg2 = mono_alloc_ireg (cfg);
3375 int original_reg = ins->sreg1;
3377 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3378 temp->sreg1 = original_reg;
3379 temp->dreg = temp_reg1;
3381 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3382 temp->sreg1 = temp_reg1;
3383 temp->dreg = temp_reg2;
3386 NEW_INS (cfg, ins, temp, OP_LOR);
3387 temp->sreg1 = temp->dreg = temp_reg2;
3388 temp->sreg2 = temp_reg1;
3390 ins->opcode = OP_EXPAND_I2;
3391 ins->sreg1 = temp_reg2;
3400 bb->max_vreg = cfg->next_vreg;
3404 branch_cc_table [] = {
3405 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3406 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3407 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3410 /* Maps CMP_... constants to X86_CC_... constants */
3413 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3414 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3418 cc_signed_table [] = {
3419 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3420 FALSE, FALSE, FALSE, FALSE
3423 /*#include "cprop.c"*/
3425 static unsigned char*
3426 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3428 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3431 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3433 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3437 static unsigned char*
3438 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3440 int sreg = tree->sreg1;
3441 int need_touch = FALSE;
3443 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3444 if (!tree->flags & MONO_INST_INIT)
3453 * If requested stack size is larger than one page,
3454 * perform stack-touch operation
3457 * Generate stack probe code.
3458 * Under Windows, it is necessary to allocate one page at a time,
3459 * "touching" stack after each successful sub-allocation. This is
3460 * because of the way stack growth is implemented - there is a
3461 * guard page before the lowest stack page that is currently commited.
3462 * Stack normally grows sequentially so OS traps access to the
3463 * guard page and commits more pages when needed.
3465 amd64_test_reg_imm (code, sreg, ~0xFFF);
3466 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3468 br[2] = code; /* loop */
3469 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3470 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3471 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3472 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3473 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3474 amd64_patch (br[3], br[2]);
3475 amd64_test_reg_reg (code, sreg, sreg);
3476 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3477 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3479 br[1] = code; x86_jump8 (code, 0);
3481 amd64_patch (br[0], code);
3482 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3483 amd64_patch (br[1], code);
3484 amd64_patch (br[4], code);
3487 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3489 if (tree->flags & MONO_INST_INIT) {
3491 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3492 amd64_push_reg (code, AMD64_RAX);
3495 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3496 amd64_push_reg (code, AMD64_RCX);
3499 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3500 amd64_push_reg (code, AMD64_RDI);
3504 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3505 if (sreg != AMD64_RCX)
3506 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3507 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3509 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3510 if (cfg->param_area && cfg->arch.no_pushes)
3511 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3513 #if defined(__default_codegen__)
3514 amd64_prefix (code, X86_REP_PREFIX);
3516 #elif defined(__native_client_codegen__)
3517 /* NaCl stos pseudo-instruction */
3518 amd64_codegen_pre(code);
3519 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3520 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3521 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3522 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3523 amd64_prefix (code, X86_REP_PREFIX);
3525 amd64_codegen_post(code);
3526 #endif /* __native_client_codegen__ */
3528 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3529 amd64_pop_reg (code, AMD64_RDI);
3530 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3531 amd64_pop_reg (code, AMD64_RCX);
3532 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3533 amd64_pop_reg (code, AMD64_RAX);
3539 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3544 /* Move return value to the target register */
3545 /* FIXME: do this in the local reg allocator */
3546 switch (ins->opcode) {
3549 case OP_CALL_MEMBASE:
3552 case OP_LCALL_MEMBASE:
3553 g_assert (ins->dreg == AMD64_RAX);
3557 case OP_FCALL_MEMBASE:
3558 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3559 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3562 if (ins->dreg != AMD64_XMM0)
3563 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3568 case OP_VCALL_MEMBASE:
3571 case OP_VCALL2_MEMBASE:
3572 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3573 if (cinfo->ret.storage == ArgValuetypeInReg) {
3574 MonoInst *loc = cfg->arch.vret_addr_loc;
3576 /* Load the destination address */
3577 g_assert (loc->opcode == OP_REGOFFSET);
3578 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3580 for (quad = 0; quad < 2; quad ++) {
3581 switch (cinfo->ret.pair_storage [quad]) {
3583 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3585 case ArgInFloatSSEReg:
3586 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3588 case ArgInDoubleSSEReg:
3589 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3604 #endif /* DISABLE_JIT */
3607 static int tls_gs_offset;
3611 mono_amd64_have_tls_get (void)
3614 static gboolean have_tls_get = FALSE;
3615 static gboolean inited = FALSE;
3618 return have_tls_get;
3620 guint8 *ins = (guint8*)pthread_getspecific;
3623 * We're looking for these two instructions:
3625 * mov %gs:[offset](,%rdi,8),%rax
3628 have_tls_get = ins [0] == 0x65 &&
3640 tls_gs_offset = ins[5];
3642 return have_tls_get;
3649 * mono_amd64_emit_tls_get:
3650 * @code: buffer to store code to
3651 * @dreg: hard register where to place the result
3652 * @tls_offset: offset info
3654 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3655 * the dreg register the item in the thread local storage identified
3658 * Returns: a pointer to the end of the stored code
3661 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3664 g_assert (tls_offset < 64);
3665 x86_prefix (code, X86_GS_PREFIX);
3666 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3667 #elif defined(__APPLE__)
3668 x86_prefix (code, X86_GS_PREFIX);
3669 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3671 if (optimize_for_xen) {
3672 x86_prefix (code, X86_FS_PREFIX);
3673 amd64_mov_reg_mem (code, dreg, 0, 8);
3674 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3676 x86_prefix (code, X86_FS_PREFIX);
3677 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3686 * Emit code to initialize an LMF structure at LMF_OFFSET.
3689 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3694 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3697 * sp is saved right before calls but we need to save it here too so
3698 * async stack walks would work.
3700 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3701 /* Skip method (only needed for trampoline LMF frames) */
3702 /* Save callee saved regs */
3703 for (i = 0; i < MONO_MAX_IREGS; ++i) {
3707 case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
3708 case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
3709 case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
3710 case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
3711 case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
3712 #ifndef __native_client_codegen__
3713 case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
3716 case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
3717 case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
3725 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
3726 if ((cfg->arch.omit_fp || (i != AMD64_RBP)) && cfa_offset != -1)
3727 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
3731 /* These can't contain refs */
3732 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3733 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
3734 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
3735 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3736 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3738 /* These are handled automatically by the stack marking code */
3739 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
3740 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3741 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
3742 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
3743 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
3744 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
3746 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
3747 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
3756 * Emit code to push an LMF structure on the LMF stack.
3759 emit_save_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, gboolean *args_clobbered)
3761 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3763 * Optimized version which uses the mono_lmf TLS variable instead of
3764 * indirection through the mono_lmf_addr TLS variable.
3766 /* %rax = previous_lmf */
3767 x86_prefix (code, X86_FS_PREFIX);
3768 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
3770 /* Save previous_lmf */
3771 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
3773 if (lmf_offset == 0) {
3774 x86_prefix (code, X86_FS_PREFIX);
3775 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
3777 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3778 x86_prefix (code, X86_FS_PREFIX);
3779 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3782 if (lmf_addr_tls_offset != -1) {
3783 /* Load lmf quicky using the FS register */
3784 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
3786 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
3787 /* FIXME: Add a separate key for LMF to avoid this */
3788 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
3793 * The call might clobber argument registers, but they are already
3794 * saved to the stack/global regs.
3797 *args_clobbered = TRUE;
3798 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3799 (gpointer)"mono_get_lmf_addr", TRUE);
3803 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, sizeof(gpointer));
3804 /* Save previous_lmf */
3805 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, sizeof(gpointer));
3806 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, sizeof(gpointer));
3808 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
3809 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, sizeof(gpointer));
3818 * Emit code to pop an LMF structure from the LMF stack.
3821 emit_restore_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset)
3823 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
3825 * Optimized version which uses the mono_lmf TLS variable instead of indirection
3826 * through the mono_lmf_addr TLS variable.
3828 /* reg = previous_lmf */
3829 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3830 x86_prefix (code, X86_FS_PREFIX);
3831 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
3833 /* Restore previous lmf */
3834 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), sizeof(gpointer));
3835 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), sizeof(gpointer));
3836 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, sizeof(gpointer));
3842 #define REAL_PRINT_REG(text,reg) \
3843 mono_assert (reg >= 0); \
3844 amd64_push_reg (code, AMD64_RAX); \
3845 amd64_push_reg (code, AMD64_RDX); \
3846 amd64_push_reg (code, AMD64_RCX); \
3847 amd64_push_reg (code, reg); \
3848 amd64_push_imm (code, reg); \
3849 amd64_push_imm (code, text " %d %p\n"); \
3850 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3851 amd64_call_reg (code, AMD64_RAX); \
3852 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3853 amd64_pop_reg (code, AMD64_RCX); \
3854 amd64_pop_reg (code, AMD64_RDX); \
3855 amd64_pop_reg (code, AMD64_RAX);
3857 /* benchmark and set based on cpu */
3858 #define LOOP_ALIGNMENT 8
3859 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3863 #if defined(__native_client__) || defined(__native_client_codegen__)
3866 #ifdef __native_client_gc__
3867 __nacl_suspend_thread_if_needed();
3873 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3878 guint8 *code = cfg->native_code + cfg->code_len;
3879 MonoInst *last_ins = NULL;
3880 guint last_offset = 0;
3883 /* Fix max_offset estimate for each successor bb */
3884 if (cfg->opt & MONO_OPT_BRANCH) {
3885 int current_offset = cfg->code_len;
3886 MonoBasicBlock *current_bb;
3887 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3888 current_bb->max_offset = current_offset;
3889 current_offset += current_bb->max_length;
3893 if (cfg->opt & MONO_OPT_LOOP) {
3894 int pad, align = LOOP_ALIGNMENT;
3895 /* set alignment depending on cpu */
3896 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3898 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3899 amd64_padding (code, pad);
3900 cfg->code_len += pad;
3901 bb->native_offset = cfg->code_len;
3905 #if defined(__native_client_codegen__)
3906 /* For Native Client, all indirect call/jump targets must be */
3907 /* 32-byte aligned. Exception handler blocks are jumped to */
3908 /* indirectly as well. */
3909 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3910 (bb->flags & BB_EXCEPTION_HANDLER);
3912 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3913 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3914 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3915 cfg->code_len += pad;
3916 bb->native_offset = cfg->code_len;
3918 #endif /*__native_client_codegen__*/
3920 if (cfg->verbose_level > 2)
3921 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3923 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3924 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3925 g_assert (!cfg->compile_aot);
3927 cov->data [bb->dfn].cil_code = bb->cil_code;
3928 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3929 /* this is not thread save, but good enough */
3930 amd64_inc_membase (code, AMD64_R11, 0);
3933 offset = code - cfg->native_code;
3935 mono_debug_open_block (cfg, bb, offset);
3937 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3938 x86_breakpoint (code);
3940 MONO_BB_FOR_EACH_INS (bb, ins) {
3941 offset = code - cfg->native_code;
3943 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3945 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3947 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3948 cfg->code_size *= 2;
3949 cfg->native_code = mono_realloc_native_code(cfg);
3950 code = cfg->native_code + offset;
3951 cfg->stat_code_reallocs++;
3954 if (cfg->debug_info)
3955 mono_debug_record_line_number (cfg, ins, offset);
3957 switch (ins->opcode) {
3959 amd64_mul_reg (code, ins->sreg2, TRUE);
3962 amd64_mul_reg (code, ins->sreg2, FALSE);
3964 case OP_X86_SETEQ_MEMBASE:
3965 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3967 case OP_STOREI1_MEMBASE_IMM:
3968 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3970 case OP_STOREI2_MEMBASE_IMM:
3971 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3973 case OP_STOREI4_MEMBASE_IMM:
3974 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3976 case OP_STOREI1_MEMBASE_REG:
3977 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3979 case OP_STOREI2_MEMBASE_REG:
3980 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3982 /* In AMD64 NaCl, pointers are 4 bytes, */
3983 /* so STORE_* != STOREI8_*. Likewise below. */
3984 case OP_STORE_MEMBASE_REG:
3985 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3987 case OP_STOREI8_MEMBASE_REG:
3988 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3990 case OP_STOREI4_MEMBASE_REG:
3991 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3993 case OP_STORE_MEMBASE_IMM:
3994 #ifndef __native_client_codegen__
3995 /* In NaCl, this could be a PCONST type, which could */
3996 /* mean a pointer type was copied directly into the */
3997 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
3998 /* the value would be 0x00000000FFFFFFFF which is */
3999 /* not proper for an imm32 unless you cast it. */
4000 g_assert (amd64_is_imm32 (ins->inst_imm));
4002 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4004 case OP_STOREI8_MEMBASE_IMM:
4005 g_assert (amd64_is_imm32 (ins->inst_imm));
4006 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4009 #ifdef __mono_ilp32__
4010 /* In ILP32, pointers are 4 bytes, so separate these */
4011 /* cases, use literal 8 below where we really want 8 */
4012 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4013 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4017 // FIXME: Decompose this earlier
4018 if (amd64_is_imm32 (ins->inst_imm))
4019 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4021 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4022 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4026 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4027 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4030 // FIXME: Decompose this earlier
4031 if (amd64_is_imm32 (ins->inst_imm))
4032 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4034 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4035 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4039 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4040 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4043 /* For NaCl, pointers are 4 bytes, so separate these */
4044 /* cases, use literal 8 below where we really want 8 */
4045 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4046 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4048 case OP_LOAD_MEMBASE:
4049 g_assert (amd64_is_imm32 (ins->inst_offset));
4050 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4052 case OP_LOADI8_MEMBASE:
4053 /* Use literal 8 instead of sizeof pointer or */
4054 /* register, we really want 8 for this opcode */
4055 g_assert (amd64_is_imm32 (ins->inst_offset));
4056 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4058 case OP_LOADI4_MEMBASE:
4059 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4061 case OP_LOADU4_MEMBASE:
4062 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4064 case OP_LOADU1_MEMBASE:
4065 /* The cpu zero extends the result into 64 bits */
4066 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4068 case OP_LOADI1_MEMBASE:
4069 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4071 case OP_LOADU2_MEMBASE:
4072 /* The cpu zero extends the result into 64 bits */
4073 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4075 case OP_LOADI2_MEMBASE:
4076 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4078 case OP_AMD64_LOADI8_MEMINDEX:
4079 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4081 case OP_LCONV_TO_I1:
4082 case OP_ICONV_TO_I1:
4084 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4086 case OP_LCONV_TO_I2:
4087 case OP_ICONV_TO_I2:
4089 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4091 case OP_LCONV_TO_U1:
4092 case OP_ICONV_TO_U1:
4093 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4095 case OP_LCONV_TO_U2:
4096 case OP_ICONV_TO_U2:
4097 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4100 /* Clean out the upper word */
4101 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4104 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4108 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4110 case OP_COMPARE_IMM:
4111 case OP_LCOMPARE_IMM:
4112 g_assert (amd64_is_imm32 (ins->inst_imm));
4113 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4115 case OP_X86_COMPARE_REG_MEMBASE:
4116 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4118 case OP_X86_TEST_NULL:
4119 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4121 case OP_AMD64_TEST_NULL:
4122 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4125 case OP_X86_ADD_REG_MEMBASE:
4126 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4128 case OP_X86_SUB_REG_MEMBASE:
4129 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4131 case OP_X86_AND_REG_MEMBASE:
4132 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4134 case OP_X86_OR_REG_MEMBASE:
4135 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4137 case OP_X86_XOR_REG_MEMBASE:
4138 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4141 case OP_X86_ADD_MEMBASE_IMM:
4142 /* FIXME: Make a 64 version too */
4143 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4145 case OP_X86_SUB_MEMBASE_IMM:
4146 g_assert (amd64_is_imm32 (ins->inst_imm));
4147 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4149 case OP_X86_AND_MEMBASE_IMM:
4150 g_assert (amd64_is_imm32 (ins->inst_imm));
4151 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4153 case OP_X86_OR_MEMBASE_IMM:
4154 g_assert (amd64_is_imm32 (ins->inst_imm));
4155 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4157 case OP_X86_XOR_MEMBASE_IMM:
4158 g_assert (amd64_is_imm32 (ins->inst_imm));
4159 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4161 case OP_X86_ADD_MEMBASE_REG:
4162 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4164 case OP_X86_SUB_MEMBASE_REG:
4165 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4167 case OP_X86_AND_MEMBASE_REG:
4168 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4170 case OP_X86_OR_MEMBASE_REG:
4171 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4173 case OP_X86_XOR_MEMBASE_REG:
4174 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4176 case OP_X86_INC_MEMBASE:
4177 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4179 case OP_X86_INC_REG:
4180 amd64_inc_reg_size (code, ins->dreg, 4);
4182 case OP_X86_DEC_MEMBASE:
4183 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4185 case OP_X86_DEC_REG:
4186 amd64_dec_reg_size (code, ins->dreg, 4);
4188 case OP_X86_MUL_REG_MEMBASE:
4189 case OP_X86_MUL_MEMBASE_REG:
4190 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4192 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4193 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4195 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4196 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4198 case OP_AMD64_COMPARE_MEMBASE_REG:
4199 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4201 case OP_AMD64_COMPARE_MEMBASE_IMM:
4202 g_assert (amd64_is_imm32 (ins->inst_imm));
4203 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4205 case OP_X86_COMPARE_MEMBASE8_IMM:
4206 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4208 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4209 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4211 case OP_AMD64_COMPARE_REG_MEMBASE:
4212 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4215 case OP_AMD64_ADD_REG_MEMBASE:
4216 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4218 case OP_AMD64_SUB_REG_MEMBASE:
4219 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4221 case OP_AMD64_AND_REG_MEMBASE:
4222 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4224 case OP_AMD64_OR_REG_MEMBASE:
4225 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4227 case OP_AMD64_XOR_REG_MEMBASE:
4228 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4231 case OP_AMD64_ADD_MEMBASE_REG:
4232 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4234 case OP_AMD64_SUB_MEMBASE_REG:
4235 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4237 case OP_AMD64_AND_MEMBASE_REG:
4238 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4240 case OP_AMD64_OR_MEMBASE_REG:
4241 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4243 case OP_AMD64_XOR_MEMBASE_REG:
4244 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4247 case OP_AMD64_ADD_MEMBASE_IMM:
4248 g_assert (amd64_is_imm32 (ins->inst_imm));
4249 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4251 case OP_AMD64_SUB_MEMBASE_IMM:
4252 g_assert (amd64_is_imm32 (ins->inst_imm));
4253 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4255 case OP_AMD64_AND_MEMBASE_IMM:
4256 g_assert (amd64_is_imm32 (ins->inst_imm));
4257 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4259 case OP_AMD64_OR_MEMBASE_IMM:
4260 g_assert (amd64_is_imm32 (ins->inst_imm));
4261 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4263 case OP_AMD64_XOR_MEMBASE_IMM:
4264 g_assert (amd64_is_imm32 (ins->inst_imm));
4265 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4269 amd64_breakpoint (code);
4271 case OP_RELAXED_NOP:
4272 x86_prefix (code, X86_REP_PREFIX);
4280 case OP_DUMMY_STORE:
4281 case OP_NOT_REACHED:
4284 case OP_SEQ_POINT: {
4288 * Read from the single stepping trigger page. This will cause a
4289 * SIGSEGV when single stepping is enabled.
4290 * We do this _before_ the breakpoint, so single stepping after
4291 * a breakpoint is hit will step to the next IL offset.
4293 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4294 MonoInst *var = cfg->arch.ss_trigger_page_var;
4296 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4297 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4301 * This is the address which is saved in seq points,
4303 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4305 if (cfg->compile_aot) {
4306 guint32 offset = code - cfg->native_code;
4308 MonoInst *info_var = cfg->arch.seq_point_info_var;
4311 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4312 val = ((offset) * sizeof (guint8*)) + G_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4313 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4314 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4315 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4318 * A placeholder for a possible breakpoint inserted by
4319 * mono_arch_set_breakpoint ().
4321 for (i = 0; i < breakpoint_size; ++i)
4328 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4331 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4335 g_assert (amd64_is_imm32 (ins->inst_imm));
4336 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4339 g_assert (amd64_is_imm32 (ins->inst_imm));
4340 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4344 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4347 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4351 g_assert (amd64_is_imm32 (ins->inst_imm));
4352 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4355 g_assert (amd64_is_imm32 (ins->inst_imm));
4356 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4359 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4363 g_assert (amd64_is_imm32 (ins->inst_imm));
4364 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4367 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4372 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4374 switch (ins->inst_imm) {
4378 if (ins->dreg != ins->sreg1)
4379 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4380 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4383 /* LEA r1, [r2 + r2*2] */
4384 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4387 /* LEA r1, [r2 + r2*4] */
4388 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4391 /* LEA r1, [r2 + r2*2] */
4393 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4394 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4397 /* LEA r1, [r2 + r2*8] */
4398 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4401 /* LEA r1, [r2 + r2*4] */
4403 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4404 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4407 /* LEA r1, [r2 + r2*2] */
4409 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4410 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4413 /* LEA r1, [r2 + r2*4] */
4414 /* LEA r1, [r1 + r1*4] */
4415 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4416 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4419 /* LEA r1, [r2 + r2*4] */
4421 /* LEA r1, [r1 + r1*4] */
4422 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4423 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4424 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4427 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4434 /* Regalloc magic makes the div/rem cases the same */
4435 if (ins->sreg2 == AMD64_RDX) {
4436 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4438 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4441 amd64_div_reg (code, ins->sreg2, TRUE);
4446 if (ins->sreg2 == AMD64_RDX) {
4447 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4448 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4449 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4451 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4452 amd64_div_reg (code, ins->sreg2, FALSE);
4457 if (ins->sreg2 == AMD64_RDX) {
4458 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4459 amd64_cdq_size (code, 4);
4460 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4462 amd64_cdq_size (code, 4);
4463 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4468 if (ins->sreg2 == AMD64_RDX) {
4469 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4470 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4471 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4473 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4474 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4478 int power = mono_is_power_of_two (ins->inst_imm);
4480 g_assert (ins->sreg1 == X86_EAX);
4481 g_assert (ins->dreg == X86_EAX);
4482 g_assert (power >= 0);
4485 amd64_mov_reg_imm (code, ins->dreg, 0);
4489 /* Based on gcc code */
4491 /* Add compensation for negative dividents */
4492 amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
4494 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
4495 amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
4496 amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
4497 /* Compute remainder */
4498 amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
4499 /* Remove compensation */
4500 amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
4504 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4505 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4508 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4512 g_assert (amd64_is_imm32 (ins->inst_imm));
4513 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4516 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4520 g_assert (amd64_is_imm32 (ins->inst_imm));
4521 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4524 g_assert (ins->sreg2 == AMD64_RCX);
4525 amd64_shift_reg (code, X86_SHL, ins->dreg);
4528 g_assert (ins->sreg2 == AMD64_RCX);
4529 amd64_shift_reg (code, X86_SAR, ins->dreg);
4532 g_assert (amd64_is_imm32 (ins->inst_imm));
4533 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4536 g_assert (amd64_is_imm32 (ins->inst_imm));
4537 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4540 g_assert (amd64_is_imm32 (ins->inst_imm));
4541 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4543 case OP_LSHR_UN_IMM:
4544 g_assert (amd64_is_imm32 (ins->inst_imm));
4545 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4548 g_assert (ins->sreg2 == AMD64_RCX);
4549 amd64_shift_reg (code, X86_SHR, ins->dreg);
4552 g_assert (amd64_is_imm32 (ins->inst_imm));
4553 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4556 g_assert (amd64_is_imm32 (ins->inst_imm));
4557 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4562 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4565 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4568 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4571 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4575 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4578 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4581 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4584 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4587 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4590 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4593 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4596 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4599 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4602 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4605 amd64_neg_reg_size (code, ins->sreg1, 4);
4608 amd64_not_reg_size (code, ins->sreg1, 4);
4611 g_assert (ins->sreg2 == AMD64_RCX);
4612 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4615 g_assert (ins->sreg2 == AMD64_RCX);
4616 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4619 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4621 case OP_ISHR_UN_IMM:
4622 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4625 g_assert (ins->sreg2 == AMD64_RCX);
4626 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4629 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4632 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4635 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4636 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4638 case OP_IMUL_OVF_UN:
4639 case OP_LMUL_OVF_UN: {
4640 /* the mul operation and the exception check should most likely be split */
4641 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4642 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4643 /*g_assert (ins->sreg2 == X86_EAX);
4644 g_assert (ins->dreg == X86_EAX);*/
4645 if (ins->sreg2 == X86_EAX) {
4646 non_eax_reg = ins->sreg1;
4647 } else if (ins->sreg1 == X86_EAX) {
4648 non_eax_reg = ins->sreg2;
4650 /* no need to save since we're going to store to it anyway */
4651 if (ins->dreg != X86_EAX) {
4653 amd64_push_reg (code, X86_EAX);
4655 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4656 non_eax_reg = ins->sreg2;
4658 if (ins->dreg == X86_EDX) {
4661 amd64_push_reg (code, X86_EAX);
4665 amd64_push_reg (code, X86_EDX);
4667 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4668 /* save before the check since pop and mov don't change the flags */
4669 if (ins->dreg != X86_EAX)
4670 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4672 amd64_pop_reg (code, X86_EDX);
4674 amd64_pop_reg (code, X86_EAX);
4675 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4679 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4681 case OP_ICOMPARE_IMM:
4682 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4704 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4712 case OP_CMOV_INE_UN:
4713 case OP_CMOV_IGE_UN:
4714 case OP_CMOV_IGT_UN:
4715 case OP_CMOV_ILE_UN:
4716 case OP_CMOV_ILT_UN:
4722 case OP_CMOV_LNE_UN:
4723 case OP_CMOV_LGE_UN:
4724 case OP_CMOV_LGT_UN:
4725 case OP_CMOV_LLE_UN:
4726 case OP_CMOV_LLT_UN:
4727 g_assert (ins->dreg == ins->sreg1);
4728 /* This needs to operate on 64 bit values */
4729 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4733 amd64_not_reg (code, ins->sreg1);
4736 amd64_neg_reg (code, ins->sreg1);
4741 if ((((guint64)ins->inst_c0) >> 32) == 0)
4742 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4744 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4747 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4748 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4751 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4752 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4755 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4757 case OP_AMD64_SET_XMMREG_R4: {
4758 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4761 case OP_AMD64_SET_XMMREG_R8: {
4762 if (ins->dreg != ins->sreg1)
4763 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4767 MonoCallInst *call = (MonoCallInst*)ins;
4770 /* FIXME: no tracing support... */
4771 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4772 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, TRUE);
4774 g_assert (!cfg->method->save_lmf);
4776 if (cfg->arch.omit_fp) {
4777 guint32 save_offset = 0;
4778 /* Pop callee-saved registers */
4779 for (i = 0; i < AMD64_NREG; ++i)
4780 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4781 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4784 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4787 if (call->stack_usage)
4791 for (i = 0; i < AMD64_NREG; ++i)
4792 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4793 pos -= sizeof(mgreg_t);
4795 /* Restore callee-saved registers */
4796 for (i = AMD64_NREG - 1; i > 0; --i) {
4797 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4798 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, sizeof(mgreg_t));
4799 pos += sizeof(mgreg_t);
4803 /* Copy arguments on the stack to our argument area */
4804 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4805 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4806 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4810 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4815 offset = code - cfg->native_code;
4816 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4817 if (cfg->compile_aot)
4818 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4820 amd64_set_reg_template (code, AMD64_R11);
4821 amd64_jump_reg (code, AMD64_R11);
4822 ins->flags |= MONO_INST_GC_CALLSITE;
4823 ins->backend.pc_offset = code - cfg->native_code;
4827 /* ensure ins->sreg1 is not NULL */
4828 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4831 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4832 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4841 call = (MonoCallInst*)ins;
4843 * The AMD64 ABI forces callers to know about varargs.
4845 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4846 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4847 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4849 * Since the unmanaged calling convention doesn't contain a
4850 * 'vararg' entry, we have to treat every pinvoke call as a
4851 * potential vararg call.
4855 for (i = 0; i < AMD64_XMM_NREG; ++i)
4856 if (call->used_fregs & (1 << i))
4859 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4861 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4864 if (ins->flags & MONO_INST_HAS_METHOD)
4865 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4867 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4868 ins->flags |= MONO_INST_GC_CALLSITE;
4869 ins->backend.pc_offset = code - cfg->native_code;
4870 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4871 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4872 code = emit_move_return_value (cfg, ins, code);
4878 case OP_VOIDCALL_REG:
4880 call = (MonoCallInst*)ins;
4882 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4883 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4884 ins->sreg1 = AMD64_R11;
4888 * The AMD64 ABI forces callers to know about varargs.
4890 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4891 if (ins->sreg1 == AMD64_RAX) {
4892 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4893 ins->sreg1 = AMD64_R11;
4895 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4896 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4898 * Since the unmanaged calling convention doesn't contain a
4899 * 'vararg' entry, we have to treat every pinvoke call as a
4900 * potential vararg call.
4904 for (i = 0; i < AMD64_XMM_NREG; ++i)
4905 if (call->used_fregs & (1 << i))
4907 if (ins->sreg1 == AMD64_RAX) {
4908 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4909 ins->sreg1 = AMD64_R11;
4912 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4914 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4917 amd64_call_reg (code, ins->sreg1);
4918 ins->flags |= MONO_INST_GC_CALLSITE;
4919 ins->backend.pc_offset = code - cfg->native_code;
4920 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4921 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4922 code = emit_move_return_value (cfg, ins, code);
4924 case OP_FCALL_MEMBASE:
4925 case OP_LCALL_MEMBASE:
4926 case OP_VCALL_MEMBASE:
4927 case OP_VCALL2_MEMBASE:
4928 case OP_VOIDCALL_MEMBASE:
4929 case OP_CALL_MEMBASE:
4930 call = (MonoCallInst*)ins;
4932 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4933 ins->flags |= MONO_INST_GC_CALLSITE;
4934 ins->backend.pc_offset = code - cfg->native_code;
4935 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4936 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4937 code = emit_move_return_value (cfg, ins, code);
4941 MonoInst *var = cfg->dyn_call_var;
4943 g_assert (var->opcode == OP_REGOFFSET);
4945 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4946 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4948 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4950 /* Save args buffer */
4951 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4953 /* Set argument registers */
4954 for (i = 0; i < PARAM_REGS; ++i)
4955 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4958 amd64_call_reg (code, AMD64_R10);
4960 ins->flags |= MONO_INST_GC_CALLSITE;
4961 ins->backend.pc_offset = code - cfg->native_code;
4964 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4965 amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4968 case OP_AMD64_SAVE_SP_TO_LMF: {
4969 MonoInst *lmf_var = cfg->arch.lmf_var;
4970 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_var->inst_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4974 g_assert (!cfg->arch.no_pushes);
4975 amd64_push_reg (code, ins->sreg1);
4977 case OP_X86_PUSH_IMM:
4978 g_assert (!cfg->arch.no_pushes);
4979 g_assert (amd64_is_imm32 (ins->inst_imm));
4980 amd64_push_imm (code, ins->inst_imm);
4982 case OP_X86_PUSH_MEMBASE:
4983 g_assert (!cfg->arch.no_pushes);
4984 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4986 case OP_X86_PUSH_OBJ: {
4987 int size = ALIGN_TO (ins->inst_imm, 8);
4989 g_assert (!cfg->arch.no_pushes);
4991 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4992 amd64_push_reg (code, AMD64_RDI);
4993 amd64_push_reg (code, AMD64_RSI);
4994 amd64_push_reg (code, AMD64_RCX);
4995 if (ins->inst_offset)
4996 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4998 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4999 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5000 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5002 amd64_prefix (code, X86_REP_PREFIX);
5004 amd64_pop_reg (code, AMD64_RCX);
5005 amd64_pop_reg (code, AMD64_RSI);
5006 amd64_pop_reg (code, AMD64_RDI);
5010 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5012 case OP_X86_LEA_MEMBASE:
5013 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5016 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5019 /* keep alignment */
5020 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5021 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5022 code = mono_emit_stack_alloc (cfg, code, ins);
5023 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5024 if (cfg->param_area && cfg->arch.no_pushes)
5025 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5027 case OP_LOCALLOC_IMM: {
5028 guint32 size = ins->inst_imm;
5029 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5031 if (ins->flags & MONO_INST_INIT) {
5035 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5036 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5038 for (i = 0; i < size; i += 8)
5039 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5040 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5042 amd64_mov_reg_imm (code, ins->dreg, size);
5043 ins->sreg1 = ins->dreg;
5045 code = mono_emit_stack_alloc (cfg, code, ins);
5046 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5049 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5050 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5052 if (cfg->param_area && cfg->arch.no_pushes)
5053 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5057 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5058 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5059 (gpointer)"mono_arch_throw_exception", FALSE);
5060 ins->flags |= MONO_INST_GC_CALLSITE;
5061 ins->backend.pc_offset = code - cfg->native_code;
5065 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5066 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5067 (gpointer)"mono_arch_rethrow_exception", FALSE);
5068 ins->flags |= MONO_INST_GC_CALLSITE;
5069 ins->backend.pc_offset = code - cfg->native_code;
5072 case OP_CALL_HANDLER:
5074 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5075 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5076 amd64_call_imm (code, 0);
5077 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5078 /* Restore stack alignment */
5079 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5081 case OP_START_HANDLER: {
5082 /* Even though we're saving RSP, use sizeof */
5083 /* gpointer because spvar is of type IntPtr */
5084 /* see: mono_create_spvar_for_region */
5085 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5086 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5088 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5089 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5090 cfg->param_area && cfg->arch.no_pushes) {
5091 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5095 case OP_ENDFINALLY: {
5096 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5097 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5101 case OP_ENDFILTER: {
5102 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5103 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5104 /* The local allocator will put the result into RAX */
5110 ins->inst_c0 = code - cfg->native_code;
5113 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5114 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5116 if (ins->inst_target_bb->native_offset) {
5117 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5119 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5120 if ((cfg->opt & MONO_OPT_BRANCH) &&
5121 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5122 x86_jump8 (code, 0);
5124 x86_jump32 (code, 0);
5128 amd64_jump_reg (code, ins->sreg1);
5145 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5146 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5148 case OP_COND_EXC_EQ:
5149 case OP_COND_EXC_NE_UN:
5150 case OP_COND_EXC_LT:
5151 case OP_COND_EXC_LT_UN:
5152 case OP_COND_EXC_GT:
5153 case OP_COND_EXC_GT_UN:
5154 case OP_COND_EXC_GE:
5155 case OP_COND_EXC_GE_UN:
5156 case OP_COND_EXC_LE:
5157 case OP_COND_EXC_LE_UN:
5158 case OP_COND_EXC_IEQ:
5159 case OP_COND_EXC_INE_UN:
5160 case OP_COND_EXC_ILT:
5161 case OP_COND_EXC_ILT_UN:
5162 case OP_COND_EXC_IGT:
5163 case OP_COND_EXC_IGT_UN:
5164 case OP_COND_EXC_IGE:
5165 case OP_COND_EXC_IGE_UN:
5166 case OP_COND_EXC_ILE:
5167 case OP_COND_EXC_ILE_UN:
5168 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5170 case OP_COND_EXC_OV:
5171 case OP_COND_EXC_NO:
5173 case OP_COND_EXC_NC:
5174 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5175 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5177 case OP_COND_EXC_IOV:
5178 case OP_COND_EXC_INO:
5179 case OP_COND_EXC_IC:
5180 case OP_COND_EXC_INC:
5181 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5182 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5185 /* floating point opcodes */
5187 double d = *(double *)ins->inst_p0;
5189 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5190 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5193 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5194 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5199 float f = *(float *)ins->inst_p0;
5201 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5202 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5205 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5206 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5207 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5211 case OP_STORER8_MEMBASE_REG:
5212 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5214 case OP_LOADR8_MEMBASE:
5215 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5217 case OP_STORER4_MEMBASE_REG:
5218 /* This requires a double->single conversion */
5219 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5220 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5222 case OP_LOADR4_MEMBASE:
5223 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5224 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5226 case OP_ICONV_TO_R4: /* FIXME: change precision */
5227 case OP_ICONV_TO_R8:
5228 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5230 case OP_LCONV_TO_R4: /* FIXME: change precision */
5231 case OP_LCONV_TO_R8:
5232 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5234 case OP_FCONV_TO_R4:
5235 /* FIXME: nothing to do ?? */
5237 case OP_FCONV_TO_I1:
5238 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5240 case OP_FCONV_TO_U1:
5241 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5243 case OP_FCONV_TO_I2:
5244 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5246 case OP_FCONV_TO_U2:
5247 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5249 case OP_FCONV_TO_U4:
5250 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5252 case OP_FCONV_TO_I4:
5254 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5256 case OP_FCONV_TO_I8:
5257 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5259 case OP_LCONV_TO_R_UN: {
5262 /* Based on gcc code */
5263 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5264 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5267 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5268 br [1] = code; x86_jump8 (code, 0);
5269 amd64_patch (br [0], code);
5272 /* Save to the red zone */
5273 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5274 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5275 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5276 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5277 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5278 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5279 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5280 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5281 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5283 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5284 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5285 amd64_patch (br [1], code);
5288 case OP_LCONV_TO_OVF_U4:
5289 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5290 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5291 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5293 case OP_LCONV_TO_OVF_I4_UN:
5294 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5295 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5296 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5299 if (ins->dreg != ins->sreg1)
5300 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5303 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5306 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5309 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5312 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5315 static double r8_0 = -0.0;
5317 g_assert (ins->sreg1 == ins->dreg);
5319 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5320 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5324 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5327 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5330 static guint64 d = 0x7fffffffffffffffUL;
5332 g_assert (ins->sreg1 == ins->dreg);
5334 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5335 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5339 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5342 g_assert (cfg->opt & MONO_OPT_CMOV);
5343 g_assert (ins->dreg == ins->sreg1);
5344 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5345 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5348 g_assert (cfg->opt & MONO_OPT_CMOV);
5349 g_assert (ins->dreg == ins->sreg1);
5350 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5351 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5354 g_assert (cfg->opt & MONO_OPT_CMOV);
5355 g_assert (ins->dreg == ins->sreg1);
5356 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5357 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5360 g_assert (cfg->opt & MONO_OPT_CMOV);
5361 g_assert (ins->dreg == ins->sreg1);
5362 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5363 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5366 g_assert (cfg->opt & MONO_OPT_CMOV);
5367 g_assert (ins->dreg == ins->sreg1);
5368 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5369 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5372 g_assert (cfg->opt & MONO_OPT_CMOV);
5373 g_assert (ins->dreg == ins->sreg1);
5374 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5375 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5378 g_assert (cfg->opt & MONO_OPT_CMOV);
5379 g_assert (ins->dreg == ins->sreg1);
5380 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5381 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5384 g_assert (cfg->opt & MONO_OPT_CMOV);
5385 g_assert (ins->dreg == ins->sreg1);
5386 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5387 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5393 * The two arguments are swapped because the fbranch instructions
5394 * depend on this for the non-sse case to work.
5396 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5399 /* zeroing the register at the start results in
5400 * shorter and faster code (we can also remove the widening op)
5402 guchar *unordered_check;
5403 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5404 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5405 unordered_check = code;
5406 x86_branch8 (code, X86_CC_P, 0, FALSE);
5407 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5408 amd64_patch (unordered_check, code);
5413 /* zeroing the register at the start results in
5414 * shorter and faster code (we can also remove the widening op)
5416 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5417 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5418 if (ins->opcode == OP_FCLT_UN) {
5419 guchar *unordered_check = code;
5420 guchar *jump_to_end;
5421 x86_branch8 (code, X86_CC_P, 0, FALSE);
5422 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5424 x86_jump8 (code, 0);
5425 amd64_patch (unordered_check, code);
5426 amd64_inc_reg (code, ins->dreg);
5427 amd64_patch (jump_to_end, code);
5429 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5434 /* zeroing the register at the start results in
5435 * shorter and faster code (we can also remove the widening op)
5437 guchar *unordered_check;
5438 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5439 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5440 if (ins->opcode == OP_FCGT) {
5441 unordered_check = code;
5442 x86_branch8 (code, X86_CC_P, 0, FALSE);
5443 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5444 amd64_patch (unordered_check, code);
5446 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5450 case OP_FCLT_MEMBASE:
5451 case OP_FCGT_MEMBASE:
5452 case OP_FCLT_UN_MEMBASE:
5453 case OP_FCGT_UN_MEMBASE:
5454 case OP_FCEQ_MEMBASE: {
5455 guchar *unordered_check, *jump_to_end;
5458 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5459 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5461 switch (ins->opcode) {
5462 case OP_FCEQ_MEMBASE:
5463 x86_cond = X86_CC_EQ;
5465 case OP_FCLT_MEMBASE:
5466 case OP_FCLT_UN_MEMBASE:
5467 x86_cond = X86_CC_LT;
5469 case OP_FCGT_MEMBASE:
5470 case OP_FCGT_UN_MEMBASE:
5471 x86_cond = X86_CC_GT;
5474 g_assert_not_reached ();
5477 unordered_check = code;
5478 x86_branch8 (code, X86_CC_P, 0, FALSE);
5479 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5481 switch (ins->opcode) {
5482 case OP_FCEQ_MEMBASE:
5483 case OP_FCLT_MEMBASE:
5484 case OP_FCGT_MEMBASE:
5485 amd64_patch (unordered_check, code);
5487 case OP_FCLT_UN_MEMBASE:
5488 case OP_FCGT_UN_MEMBASE:
5490 x86_jump8 (code, 0);
5491 amd64_patch (unordered_check, code);
5492 amd64_inc_reg (code, ins->dreg);
5493 amd64_patch (jump_to_end, code);
5501 guchar *jump = code;
5502 x86_branch8 (code, X86_CC_P, 0, TRUE);
5503 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5504 amd64_patch (jump, code);
5508 /* Branch if C013 != 100 */
5509 /* branch if !ZF or (PF|CF) */
5510 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5511 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5512 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5515 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5518 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5519 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5523 if (ins->opcode == OP_FBGT) {
5526 /* skip branch if C1=1 */
5528 x86_branch8 (code, X86_CC_P, 0, FALSE);
5529 /* branch if (C0 | C3) = 1 */
5530 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5531 amd64_patch (br1, code);
5534 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5538 /* Branch if C013 == 100 or 001 */
5541 /* skip branch if C1=1 */
5543 x86_branch8 (code, X86_CC_P, 0, FALSE);
5544 /* branch if (C0 | C3) = 1 */
5545 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5546 amd64_patch (br1, code);
5550 /* Branch if C013 == 000 */
5551 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5554 /* Branch if C013=000 or 100 */
5557 /* skip branch if C1=1 */
5559 x86_branch8 (code, X86_CC_P, 0, FALSE);
5560 /* branch if C0=0 */
5561 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5562 amd64_patch (br1, code);
5566 /* Branch if C013 != 001 */
5567 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5568 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5571 /* Transfer value to the fp stack */
5572 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5573 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5574 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5576 amd64_push_reg (code, AMD64_RAX);
5578 amd64_fnstsw (code);
5579 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5580 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5581 amd64_pop_reg (code, AMD64_RAX);
5582 amd64_fstp (code, 0);
5583 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5584 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5587 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5590 case OP_MEMORY_BARRIER: {
5591 switch (ins->backend.memory_barrier_kind) {
5592 case StoreLoadBarrier:
5594 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5595 x86_prefix (code, X86_LOCK_PREFIX);
5596 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5601 case OP_ATOMIC_ADD_I4:
5602 case OP_ATOMIC_ADD_I8: {
5603 int dreg = ins->dreg;
5604 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5606 if (dreg == ins->inst_basereg)
5609 if (dreg != ins->sreg2)
5610 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
5612 x86_prefix (code, X86_LOCK_PREFIX);
5613 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5615 if (dreg != ins->dreg)
5616 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5620 case OP_ATOMIC_ADD_NEW_I4:
5621 case OP_ATOMIC_ADD_NEW_I8: {
5622 int dreg = ins->dreg;
5623 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
5625 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5628 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5629 amd64_prefix (code, X86_LOCK_PREFIX);
5630 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5631 /* dreg contains the old value, add with sreg2 value */
5632 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5634 if (ins->dreg != dreg)
5635 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5639 case OP_ATOMIC_EXCHANGE_I4:
5640 case OP_ATOMIC_EXCHANGE_I8: {
5642 int sreg2 = ins->sreg2;
5643 int breg = ins->inst_basereg;
5645 gboolean need_push = FALSE, rdx_pushed = FALSE;
5647 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5653 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5654 * an explanation of how this works.
5657 /* cmpxchg uses eax as comperand, need to make sure we can use it
5658 * hack to overcome limits in x86 reg allocator
5659 * (req: dreg == eax and sreg2 != eax and breg != eax)
5661 g_assert (ins->dreg == AMD64_RAX);
5663 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5664 /* Highly unlikely, but possible */
5667 /* The pushes invalidate rsp */
5668 if ((breg == AMD64_RAX) || need_push) {
5669 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5673 /* We need the EAX reg for the comparand */
5674 if (ins->sreg2 == AMD64_RAX) {
5675 if (breg != AMD64_R11) {
5676 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5679 g_assert (need_push);
5680 amd64_push_reg (code, AMD64_RDX);
5681 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5687 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5689 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5690 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5691 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5692 amd64_patch (br [1], br [0]);
5695 amd64_pop_reg (code, AMD64_RDX);
5699 case OP_ATOMIC_CAS_I4:
5700 case OP_ATOMIC_CAS_I8: {
5703 if (ins->opcode == OP_ATOMIC_CAS_I8)
5709 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5710 * an explanation of how this works.
5712 g_assert (ins->sreg3 == AMD64_RAX);
5713 g_assert (ins->sreg1 != AMD64_RAX);
5714 g_assert (ins->sreg1 != ins->sreg2);
5716 amd64_prefix (code, X86_LOCK_PREFIX);
5717 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5719 if (ins->dreg != AMD64_RAX)
5720 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5723 case OP_CARD_TABLE_WBARRIER: {
5724 int ptr = ins->sreg1;
5725 int value = ins->sreg2;
5727 int nursery_shift, card_table_shift;
5728 gpointer card_table_mask;
5729 size_t nursery_size;
5731 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5732 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5733 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5735 /*If either point to the stack we can simply avoid the WB. This happens due to
5736 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5738 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5742 * We need one register we can clobber, we choose EDX and make sreg1
5743 * fixed EAX to work around limitations in the local register allocator.
5744 * sreg2 might get allocated to EDX, but that is not a problem since
5745 * we use it before clobbering EDX.
5747 g_assert (ins->sreg1 == AMD64_RAX);
5750 * This is the code we produce:
5753 * edx >>= nursery_shift
5754 * cmp edx, (nursery_start >> nursery_shift)
5757 * edx >>= card_table_shift
5763 if (value != AMD64_RDX)
5764 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5765 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5766 if (shifted_nursery_start >> 31) {
5768 * The value we need to compare against is 64 bits, so we need
5769 * another spare register. We use RBX, which we save and
5772 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5773 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5774 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5775 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5777 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5779 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5780 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5781 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5782 if (card_table_mask)
5783 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5785 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5786 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5788 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5789 x86_patch (br, code);
5792 #ifdef MONO_ARCH_SIMD_INTRINSICS
5793 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5795 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5798 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5801 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5804 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5807 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5810 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5813 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5814 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5817 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5820 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5823 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5826 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5829 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5832 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5835 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5838 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5841 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5844 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5847 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5850 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5853 case OP_PSHUFLEW_HIGH:
5854 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5855 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5857 case OP_PSHUFLEW_LOW:
5858 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5859 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5862 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5863 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5866 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5867 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5870 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5871 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5875 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5878 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5881 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5884 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5887 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5890 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5893 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5894 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5897 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5900 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5903 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5906 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5909 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5912 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5915 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5918 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5921 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5924 case OP_EXTRACT_MASK:
5925 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5929 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5932 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5935 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5939 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5942 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5945 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5948 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5952 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5955 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5958 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5961 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5965 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5968 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5971 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5975 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5978 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5981 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5985 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5988 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5992 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5995 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5998 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6002 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6005 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6008 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6012 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6015 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6018 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6021 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6025 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6028 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6031 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6034 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6037 case OP_PSUM_ABS_DIFF:
6038 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6041 case OP_UNPACK_LOWB:
6042 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6044 case OP_UNPACK_LOWW:
6045 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6047 case OP_UNPACK_LOWD:
6048 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6050 case OP_UNPACK_LOWQ:
6051 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6053 case OP_UNPACK_LOWPS:
6054 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6056 case OP_UNPACK_LOWPD:
6057 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6060 case OP_UNPACK_HIGHB:
6061 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6063 case OP_UNPACK_HIGHW:
6064 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6066 case OP_UNPACK_HIGHD:
6067 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6069 case OP_UNPACK_HIGHQ:
6070 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6072 case OP_UNPACK_HIGHPS:
6073 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6075 case OP_UNPACK_HIGHPD:
6076 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6080 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6083 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6086 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6089 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6092 case OP_PADDB_SAT_UN:
6093 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6095 case OP_PSUBB_SAT_UN:
6096 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6098 case OP_PADDW_SAT_UN:
6099 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6101 case OP_PSUBW_SAT_UN:
6102 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6106 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6109 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6112 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6115 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6119 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6122 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6125 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6127 case OP_PMULW_HIGH_UN:
6128 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6131 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6135 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6138 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6142 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6145 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6149 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6152 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6156 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6159 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6163 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6166 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6170 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6173 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6177 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6180 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6183 /*TODO: This is appart of the sse spec but not added
6185 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6188 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6193 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6196 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6199 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6202 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6205 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6208 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6211 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6214 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6217 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6220 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6224 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6227 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6231 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6232 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6234 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6239 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6241 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6242 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6246 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6248 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6249 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6250 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6254 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6256 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6259 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6261 case OP_EXTRACTX_U2:
6262 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6264 case OP_INSERTX_U1_SLOW:
6265 /*sreg1 is the extracted ireg (scratch)
6266 /sreg2 is the to be inserted ireg (scratch)
6267 /dreg is the xreg to receive the value*/
6269 /*clear the bits from the extracted word*/
6270 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6271 /*shift the value to insert if needed*/
6272 if (ins->inst_c0 & 1)
6273 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6274 /*join them together*/
6275 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6276 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6278 case OP_INSERTX_I4_SLOW:
6279 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6280 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6281 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6283 case OP_INSERTX_I8_SLOW:
6284 amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6286 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6288 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6291 case OP_INSERTX_R4_SLOW:
6292 switch (ins->inst_c0) {
6294 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6297 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6298 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6299 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6302 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6303 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6304 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6307 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6308 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6309 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6313 case OP_INSERTX_R8_SLOW:
6315 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6317 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6319 case OP_STOREX_MEMBASE_REG:
6320 case OP_STOREX_MEMBASE:
6321 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6323 case OP_LOADX_MEMBASE:
6324 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6326 case OP_LOADX_ALIGNED_MEMBASE:
6327 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6329 case OP_STOREX_ALIGNED_MEMBASE_REG:
6330 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6332 case OP_STOREX_NTA_MEMBASE_REG:
6333 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6335 case OP_PREFETCH_MEMBASE:
6336 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6340 /*FIXME the peephole pass should have killed this*/
6341 if (ins->dreg != ins->sreg1)
6342 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6345 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6347 case OP_ICONV_TO_R8_RAW:
6348 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6349 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6352 case OP_FCONV_TO_R8_X:
6353 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6356 case OP_XCONV_R8_TO_I4:
6357 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6358 switch (ins->backend.source_opcode) {
6359 case OP_FCONV_TO_I1:
6360 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6362 case OP_FCONV_TO_U1:
6363 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6365 case OP_FCONV_TO_I2:
6366 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6368 case OP_FCONV_TO_U2:
6369 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6375 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6376 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6377 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6380 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6381 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6384 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6385 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6388 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6389 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6390 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6393 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6394 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6397 case OP_LIVERANGE_START: {
6398 if (cfg->verbose_level > 1)
6399 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6400 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6403 case OP_LIVERANGE_END: {
6404 if (cfg->verbose_level > 1)
6405 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6406 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6409 case OP_NACL_GC_SAFE_POINT: {
6410 #if defined(__native_client_codegen__)
6411 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6415 case OP_GC_LIVENESS_DEF:
6416 case OP_GC_LIVENESS_USE:
6417 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6418 ins->backend.pc_offset = code - cfg->native_code;
6420 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6421 ins->backend.pc_offset = code - cfg->native_code;
6422 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6425 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6426 g_assert_not_reached ();
6429 if ((code - cfg->native_code - offset) > max_len) {
6430 #if !defined(__native_client_codegen__)
6431 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6432 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6433 g_assert_not_reached ();
6438 last_offset = offset;
6441 cfg->code_len = code - cfg->native_code;
6444 #endif /* DISABLE_JIT */
6447 mono_arch_register_lowlevel_calls (void)
6449 /* The signature doesn't matter */
6450 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6454 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6456 MonoJumpInfo *patch_info;
6457 gboolean compile_aot = !run_cctors;
6459 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6460 unsigned char *ip = patch_info->ip.i + code;
6461 unsigned char *target;
6463 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6466 switch (patch_info->type) {
6467 case MONO_PATCH_INFO_BB:
6468 case MONO_PATCH_INFO_LABEL:
6471 /* No need to patch these */
6476 switch (patch_info->type) {
6477 case MONO_PATCH_INFO_NONE:
6479 case MONO_PATCH_INFO_METHOD_REL:
6480 case MONO_PATCH_INFO_R8:
6481 case MONO_PATCH_INFO_R4:
6482 g_assert_not_reached ();
6484 case MONO_PATCH_INFO_BB:
6491 * Debug code to help track down problems where the target of a near call is
6494 if (amd64_is_near_call (ip)) {
6495 gint64 disp = (guint8*)target - (guint8*)ip;
6497 if (!amd64_is_imm32 (disp)) {
6498 printf ("TYPE: %d\n", patch_info->type);
6499 switch (patch_info->type) {
6500 case MONO_PATCH_INFO_INTERNAL_METHOD:
6501 printf ("V: %s\n", patch_info->data.name);
6503 case MONO_PATCH_INFO_METHOD_JUMP:
6504 case MONO_PATCH_INFO_METHOD:
6505 printf ("V: %s\n", patch_info->data.method->name);
6513 amd64_patch (ip, (gpointer)target);
6520 get_max_epilog_size (MonoCompile *cfg)
6522 int max_epilog_size = 16;
6524 if (cfg->method->save_lmf)
6525 max_epilog_size += 256;
6527 if (mono_jit_trace_calls != NULL)
6528 max_epilog_size += 50;
6530 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6531 max_epilog_size += 50;
6533 max_epilog_size += (AMD64_NREG * 2);
6535 return max_epilog_size;
6539 * This macro is used for testing whenever the unwinder works correctly at every point
6540 * where an async exception can happen.
6542 /* This will generate a SIGSEGV at the given point in the code */
6543 #define async_exc_point(code) do { \
6544 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6545 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6546 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6547 cfg->arch.async_point_count ++; \
6552 mono_arch_emit_prolog (MonoCompile *cfg)
6554 MonoMethod *method = cfg->method;
6556 MonoMethodSignature *sig;
6558 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
6561 MonoInst *lmf_var = cfg->arch.lmf_var;
6562 gboolean args_clobbered = FALSE;
6563 gboolean trace = FALSE;
6564 #ifdef __native_client_codegen__
6565 guint alignment_check;
6568 cfg->code_size = MAX (cfg->header->code_size * 4, 10240);
6570 #if defined(__default_codegen__)
6571 code = cfg->native_code = g_malloc (cfg->code_size);
6572 #elif defined(__native_client_codegen__)
6573 /* native_code_alloc is not 32-byte aligned, native_code is. */
6574 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6576 /* Align native_code to next nearest kNaclAlignment byte. */
6577 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6578 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6580 code = cfg->native_code;
6582 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6583 g_assert (alignment_check == 0);
6586 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6589 /* Amount of stack space allocated by register saving code */
6592 /* Offset between RSP and the CFA */
6596 * The prolog consists of the following parts:
6598 * - push rbp, mov rbp, rsp
6599 * - save callee saved regs using pushes
6601 * - save rgctx if needed
6602 * - save lmf if needed
6605 * - save rgctx if needed
6606 * - save lmf if needed
6607 * - save callee saved regs using moves
6612 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6613 // IP saved at CFA - 8
6614 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6615 async_exc_point (code);
6616 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6618 if (!cfg->arch.omit_fp) {
6619 amd64_push_reg (code, AMD64_RBP);
6621 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6622 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6623 async_exc_point (code);
6625 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6627 /* These are handled automatically by the stack marking code */
6628 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6630 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6631 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6632 async_exc_point (code);
6634 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6638 /* Save callee saved registers */
6639 if (!cfg->arch.omit_fp && !method->save_lmf) {
6640 int offset = cfa_offset;
6642 for (i = 0; i < AMD64_NREG; ++i)
6643 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6644 amd64_push_reg (code, i);
6645 pos += 8; /* AMD64 push inst is always 8 bytes, no way to change it */
6647 mono_emit_unwind_op_offset (cfg, code, i, - offset);
6648 async_exc_point (code);
6650 /* These are handled automatically by the stack marking code */
6651 mini_gc_set_slot_type_from_cfa (cfg, - offset, SLOT_NOREF);
6655 /* The param area is always at offset 0 from sp */
6656 /* This needs to be allocated here, since it has to come after the spill area */
6657 if (cfg->arch.no_pushes && cfg->param_area) {
6658 if (cfg->arch.omit_fp)
6660 g_assert_not_reached ();
6661 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6664 if (cfg->arch.omit_fp) {
6666 * On enter, the stack is misaligned by the pushing of the return
6667 * address. It is either made aligned by the pushing of %rbp, or by
6670 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6671 if ((alloc_size % 16) == 0) {
6673 /* Mark the padding slot as NOREF */
6674 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6677 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6678 if (cfg->stack_offset != alloc_size) {
6679 /* Mark the padding slot as NOREF */
6680 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6682 cfg->arch.sp_fp_offset = alloc_size;
6686 cfg->arch.stack_alloc_size = alloc_size;
6688 /* Allocate stack frame */
6690 /* See mono_emit_stack_alloc */
6691 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6692 guint32 remaining_size = alloc_size;
6693 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6694 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6695 guint32 offset = code - cfg->native_code;
6696 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6697 while (required_code_size >= (cfg->code_size - offset))
6698 cfg->code_size *= 2;
6699 cfg->native_code = mono_realloc_native_code (cfg);
6700 code = cfg->native_code + offset;
6701 cfg->stat_code_reallocs++;
6704 while (remaining_size >= 0x1000) {
6705 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6706 if (cfg->arch.omit_fp) {
6707 cfa_offset += 0x1000;
6708 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6710 async_exc_point (code);
6712 if (cfg->arch.omit_fp)
6713 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6716 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6717 remaining_size -= 0x1000;
6719 if (remaining_size) {
6720 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6721 if (cfg->arch.omit_fp) {
6722 cfa_offset += remaining_size;
6723 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6724 async_exc_point (code);
6727 if (cfg->arch.omit_fp)
6728 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6732 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6733 if (cfg->arch.omit_fp) {
6734 cfa_offset += alloc_size;
6735 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6736 async_exc_point (code);
6741 /* Stack alignment check */
6744 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6745 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6746 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6747 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6748 amd64_breakpoint (code);
6752 #ifndef TARGET_WIN32
6753 if (mini_get_debug_options ()->init_stacks) {
6754 /* Fill the stack frame with a dummy value to force deterministic behavior */
6756 /* Save registers to the red zone */
6757 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6758 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6760 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6761 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6762 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6765 #if defined(__default_codegen__)
6766 amd64_prefix (code, X86_REP_PREFIX);
6768 #elif defined(__native_client_codegen__)
6769 /* NaCl stos pseudo-instruction */
6770 amd64_codegen_pre (code);
6771 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
6772 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6773 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6774 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6775 amd64_prefix (code, X86_REP_PREFIX);
6777 amd64_codegen_post (code);
6778 #endif /* __native_client_codegen__ */
6780 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6781 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6786 if (method->save_lmf) {
6787 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6790 /* Save callee saved registers */
6791 if (cfg->arch.omit_fp && !method->save_lmf) {
6792 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6794 /* Save caller saved registers after sp is adjusted */
6795 /* The registers are saved at the bottom of the frame */
6796 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6797 for (i = 0; i < AMD64_NREG; ++i)
6798 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6799 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6800 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6802 /* These are handled automatically by the stack marking code */
6803 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6805 save_area_offset += 8;
6806 async_exc_point (code);
6810 /* store runtime generic context */
6811 if (cfg->rgctx_var) {
6812 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6813 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6815 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6817 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6818 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6821 /* compute max_length in order to use short forward jumps */
6822 max_epilog_size = get_max_epilog_size (cfg);
6823 if (cfg->opt & MONO_OPT_BRANCH) {
6824 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6828 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6830 /* max alignment for loops */
6831 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6832 max_length += LOOP_ALIGNMENT;
6833 #ifdef __native_client_codegen__
6834 /* max alignment for native client */
6835 max_length += kNaClAlignment;
6838 MONO_BB_FOR_EACH_INS (bb, ins) {
6839 #ifdef __native_client_codegen__
6841 int space_in_block = kNaClAlignment -
6842 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6843 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6844 if (space_in_block < max_len && max_len < kNaClAlignment) {
6845 max_length += space_in_block;
6848 #endif /*__native_client_codegen__*/
6849 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6852 /* Take prolog and epilog instrumentation into account */
6853 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6854 max_length += max_epilog_size;
6856 bb->max_length = max_length;
6860 sig = mono_method_signature (method);
6863 cinfo = cfg->arch.cinfo;
6865 if (sig->ret->type != MONO_TYPE_VOID) {
6866 /* Save volatile arguments to the stack */
6867 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6868 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6871 /* Keep this in sync with emit_load_volatile_arguments */
6872 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6873 ArgInfo *ainfo = cinfo->args + i;
6874 gint32 stack_offset;
6877 ins = cfg->args [i];
6879 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6880 /* Unused arguments */
6883 if (sig->hasthis && (i == 0))
6884 arg_type = &mono_defaults.object_class->byval_arg;
6886 arg_type = sig->params [i - sig->hasthis];
6888 stack_offset = ainfo->offset + ARGS_OFFSET;
6890 if (cfg->globalra) {
6891 /* All the other moves are done by the register allocator */
6892 switch (ainfo->storage) {
6893 case ArgInFloatSSEReg:
6894 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6896 case ArgValuetypeInReg:
6897 for (quad = 0; quad < 2; quad ++) {
6898 switch (ainfo->pair_storage [quad]) {
6900 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6902 case ArgInFloatSSEReg:
6903 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6905 case ArgInDoubleSSEReg:
6906 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6911 g_assert_not_reached ();
6922 /* Save volatile arguments to the stack */
6923 if (ins->opcode != OP_REGVAR) {
6924 switch (ainfo->storage) {
6930 if (stack_offset & 0x1)
6932 else if (stack_offset & 0x2)
6934 else if (stack_offset & 0x4)
6939 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6942 * Save the original location of 'this',
6943 * get_generic_info_from_stack_frame () needs this to properly look up
6944 * the argument value during the handling of async exceptions.
6946 if (ins == cfg->args [0]) {
6947 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6948 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6952 case ArgInFloatSSEReg:
6953 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6955 case ArgInDoubleSSEReg:
6956 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6958 case ArgValuetypeInReg:
6959 for (quad = 0; quad < 2; quad ++) {
6960 switch (ainfo->pair_storage [quad]) {
6962 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6964 case ArgInFloatSSEReg:
6965 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6967 case ArgInDoubleSSEReg:
6968 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6973 g_assert_not_reached ();
6977 case ArgValuetypeAddrInIReg:
6978 if (ainfo->pair_storage [0] == ArgInIReg)
6979 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
6985 /* Argument allocated to (non-volatile) register */
6986 switch (ainfo->storage) {
6988 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6991 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6994 g_assert_not_reached ();
6997 if (ins == cfg->args [0]) {
6998 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6999 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7004 /* Might need to attach the thread to the JIT or change the domain for the callback */
7005 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
7006 guint64 domain = (guint64)cfg->domain;
7008 args_clobbered = TRUE;
7011 * The call might clobber argument registers, but they are already
7012 * saved to the stack/global regs.
7014 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
7015 guint8 *buf, *no_domain_branch;
7017 code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
7018 if (cfg->compile_aot) {
7019 /* AOT code is only used in the root domain */
7020 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
7022 if ((domain >> 32) == 0)
7023 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
7025 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
7027 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
7028 no_domain_branch = code;
7029 x86_branch8 (code, X86_CC_NE, 0, 0);
7030 code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
7031 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
7033 x86_branch8 (code, X86_CC_NE, 0, 0);
7034 amd64_patch (no_domain_branch, code);
7035 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
7036 (gpointer)"mono_jit_thread_attach", TRUE);
7037 amd64_patch (buf, code);
7039 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
7040 /* FIXME: Add a separate key for LMF to avoid this */
7041 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
7044 g_assert (!cfg->compile_aot);
7045 if (cfg->compile_aot) {
7046 /* AOT code is only used in the root domain */
7047 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
7049 if ((domain >> 32) == 0)
7050 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
7052 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
7054 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
7055 (gpointer)"mono_jit_thread_attach", TRUE);
7059 if (method->save_lmf) {
7060 code = emit_save_lmf (cfg, code, lmf_var->inst_offset, &args_clobbered);
7064 args_clobbered = TRUE;
7065 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7068 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7069 args_clobbered = TRUE;
7072 * Optimize the common case of the first bblock making a call with the same
7073 * arguments as the method. This works because the arguments are still in their
7074 * original argument registers.
7075 * FIXME: Generalize this
7077 if (!args_clobbered) {
7078 MonoBasicBlock *first_bb = cfg->bb_entry;
7081 next = mono_bb_first_ins (first_bb);
7082 if (!next && first_bb->next_bb) {
7083 first_bb = first_bb->next_bb;
7084 next = mono_bb_first_ins (first_bb);
7087 if (first_bb->in_count > 1)
7090 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7091 ArgInfo *ainfo = cinfo->args + i;
7092 gboolean match = FALSE;
7094 ins = cfg->args [i];
7095 if (ins->opcode != OP_REGVAR) {
7096 switch (ainfo->storage) {
7098 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7099 if (next->dreg == ainfo->reg) {
7103 next->opcode = OP_MOVE;
7104 next->sreg1 = ainfo->reg;
7105 /* Only continue if the instruction doesn't change argument regs */
7106 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7116 /* Argument allocated to (non-volatile) register */
7117 switch (ainfo->storage) {
7119 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7131 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7138 if (cfg->gen_seq_points) {
7139 MonoInst *info_var = cfg->arch.seq_point_info_var;
7141 /* Initialize seq_point_info_var */
7142 if (cfg->compile_aot) {
7143 /* Initialize the variable from a GOT slot */
7144 /* Same as OP_AOTCONST */
7145 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7146 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7147 g_assert (info_var->opcode == OP_REGOFFSET);
7148 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7151 /* Initialize ss_trigger_page_var */
7152 ins = cfg->arch.ss_trigger_page_var;
7154 g_assert (ins->opcode == OP_REGOFFSET);
7156 if (cfg->compile_aot) {
7157 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7158 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, G_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7160 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7162 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7165 cfg->code_len = code - cfg->native_code;
7167 g_assert (cfg->code_len < cfg->code_size);
7173 mono_arch_emit_epilog (MonoCompile *cfg)
7175 MonoMethod *method = cfg->method;
7178 int max_epilog_size;
7180 gint32 lmf_offset = cfg->arch.lmf_var ? ((MonoInst*)cfg->arch.lmf_var)->inst_offset : -1;
7182 max_epilog_size = get_max_epilog_size (cfg);
7184 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7185 cfg->code_size *= 2;
7186 cfg->native_code = mono_realloc_native_code (cfg);
7187 cfg->stat_code_reallocs++;
7190 code = cfg->native_code + cfg->code_len;
7192 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7193 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7195 /* the code restoring the registers must be kept in sync with OP_JMP */
7198 if (method->save_lmf) {
7199 /* check if we need to restore protection of the stack after a stack overflow */
7200 if (mono_get_jit_tls_offset () != -1) {
7202 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7203 /* we load the value in a separate instruction: this mechanism may be
7204 * used later as a safer way to do thread interruption
7206 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7207 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7209 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7210 /* note that the call trampoline will preserve eax/edx */
7211 x86_call_reg (code, X86_ECX);
7212 x86_patch (patch, code);
7214 /* FIXME: maybe save the jit tls in the prolog */
7217 code = emit_restore_lmf (cfg, code, lmf_offset);
7219 /* Restore caller saved regs */
7220 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7221 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
7223 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
7224 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
7226 if (cfg->used_int_regs & (1 << AMD64_R12)) {
7227 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
7229 if (cfg->used_int_regs & (1 << AMD64_R13)) {
7230 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
7232 if (cfg->used_int_regs & (1 << AMD64_R14)) {
7233 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
7235 if (cfg->used_int_regs & (1 << AMD64_R15)) {
7236 #if defined(__default_codegen__)
7237 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
7238 #elif defined(__native_client_codegen__)
7239 g_assert_not_reached();
7243 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
7244 amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
7246 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
7247 amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
7252 if (cfg->arch.omit_fp) {
7253 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7255 for (i = 0; i < AMD64_NREG; ++i)
7256 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7257 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
7258 save_area_offset += 8;
7262 for (i = 0; i < AMD64_NREG; ++i)
7263 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
7264 pos -= sizeof(mgreg_t);
7267 if (pos == - sizeof(mgreg_t)) {
7268 /* Only one register, so avoid lea */
7269 for (i = AMD64_NREG - 1; i > 0; --i)
7270 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7271 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
7275 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
7277 /* Pop registers in reverse order */
7278 for (i = AMD64_NREG - 1; i > 0; --i)
7279 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
7280 amd64_pop_reg (code, i);
7287 /* Load returned vtypes into registers if needed */
7288 cinfo = cfg->arch.cinfo;
7289 if (cinfo->ret.storage == ArgValuetypeInReg) {
7290 ArgInfo *ainfo = &cinfo->ret;
7291 MonoInst *inst = cfg->ret;
7293 for (quad = 0; quad < 2; quad ++) {
7294 switch (ainfo->pair_storage [quad]) {
7296 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7298 case ArgInFloatSSEReg:
7299 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7301 case ArgInDoubleSSEReg:
7302 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7307 g_assert_not_reached ();
7312 if (cfg->arch.omit_fp) {
7313 if (cfg->arch.stack_alloc_size)
7314 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7318 async_exc_point (code);
7321 cfg->code_len = code - cfg->native_code;
7323 g_assert (cfg->code_len < cfg->code_size);
7327 mono_arch_emit_exceptions (MonoCompile *cfg)
7329 MonoJumpInfo *patch_info;
7332 MonoClass *exc_classes [16];
7333 guint8 *exc_throw_start [16], *exc_throw_end [16];
7334 guint32 code_size = 0;
7336 /* Compute needed space */
7337 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7338 if (patch_info->type == MONO_PATCH_INFO_EXC)
7340 if (patch_info->type == MONO_PATCH_INFO_R8)
7341 code_size += 8 + 15; /* sizeof (double) + alignment */
7342 if (patch_info->type == MONO_PATCH_INFO_R4)
7343 code_size += 4 + 15; /* sizeof (float) + alignment */
7344 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7345 code_size += 8 + 7; /*sizeof (void*) + alignment */
7348 #ifdef __native_client_codegen__
7349 /* Give us extra room on Native Client. This could be */
7350 /* more carefully calculated, but bundle alignment makes */
7351 /* it much trickier, so *2 like other places is good. */
7355 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7356 cfg->code_size *= 2;
7357 cfg->native_code = mono_realloc_native_code (cfg);
7358 cfg->stat_code_reallocs++;
7361 code = cfg->native_code + cfg->code_len;
7363 /* add code to raise exceptions */
7365 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7366 switch (patch_info->type) {
7367 case MONO_PATCH_INFO_EXC: {
7368 MonoClass *exc_class;
7372 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7374 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7375 g_assert (exc_class);
7376 throw_ip = patch_info->ip.i;
7378 //x86_breakpoint (code);
7379 /* Find a throw sequence for the same exception class */
7380 for (i = 0; i < nthrows; ++i)
7381 if (exc_classes [i] == exc_class)
7384 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7385 x86_jump_code (code, exc_throw_start [i]);
7386 patch_info->type = MONO_PATCH_INFO_NONE;
7390 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7394 exc_classes [nthrows] = exc_class;
7395 exc_throw_start [nthrows] = code;
7397 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7399 patch_info->type = MONO_PATCH_INFO_NONE;
7401 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7403 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7408 exc_throw_end [nthrows] = code;
7418 g_assert(code < cfg->native_code + cfg->code_size);
7421 /* Handle relocations with RIP relative addressing */
7422 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7423 gboolean remove = FALSE;
7424 guint8 *orig_code = code;
7426 switch (patch_info->type) {
7427 case MONO_PATCH_INFO_R8:
7428 case MONO_PATCH_INFO_R4: {
7429 guint8 *pos, *patch_pos;
7432 /* The SSE opcodes require a 16 byte alignment */
7433 #if defined(__default_codegen__)
7434 code = (guint8*)ALIGN_TO (code, 16);
7435 #elif defined(__native_client_codegen__)
7437 /* Pad this out with HLT instructions */
7438 /* or we can get garbage bytes emitted */
7439 /* which will fail validation */
7440 guint8 *aligned_code;
7441 /* extra align to make room for */
7442 /* mov/push below */
7443 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7444 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7445 /* The technique of hiding data in an */
7446 /* instruction has a problem here: we */
7447 /* need the data aligned to a 16-byte */
7448 /* boundary but the instruction cannot */
7449 /* cross the bundle boundary. so only */
7450 /* odd multiples of 16 can be used */
7451 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7454 while (code < aligned_code) {
7455 *(code++) = 0xf4; /* hlt */
7460 pos = cfg->native_code + patch_info->ip.i;
7461 if (IS_REX (pos [1])) {
7462 patch_pos = pos + 5;
7463 target_pos = code - pos - 9;
7466 patch_pos = pos + 4;
7467 target_pos = code - pos - 8;
7470 if (patch_info->type == MONO_PATCH_INFO_R8) {
7471 #ifdef __native_client_codegen__
7472 /* Hide 64-bit data in a */
7473 /* "mov imm64, r11" instruction. */
7474 /* write it before the start of */
7476 *(code-2) = 0x49; /* prefix */
7477 *(code-1) = 0xbb; /* mov X, %r11 */
7479 *(double*)code = *(double*)patch_info->data.target;
7480 code += sizeof (double);
7482 #ifdef __native_client_codegen__
7483 /* Hide 32-bit data in a */
7484 /* "push imm32" instruction. */
7485 *(code-1) = 0x68; /* push */
7487 *(float*)code = *(float*)patch_info->data.target;
7488 code += sizeof (float);
7491 *(guint32*)(patch_pos) = target_pos;
7496 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7499 if (cfg->compile_aot)
7502 /*loading is faster against aligned addresses.*/
7503 code = (guint8*)ALIGN_TO (code, 8);
7504 memset (orig_code, 0, code - orig_code);
7506 pos = cfg->native_code + patch_info->ip.i;
7508 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7509 if (IS_REX (pos [1]))
7510 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7512 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7514 *(gpointer*)code = (gpointer)patch_info->data.target;
7515 code += sizeof (gpointer);
7525 if (patch_info == cfg->patch_info)
7526 cfg->patch_info = patch_info->next;
7530 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7532 tmp->next = patch_info->next;
7535 g_assert (code < cfg->native_code + cfg->code_size);
7538 cfg->code_len = code - cfg->native_code;
7540 g_assert (cfg->code_len < cfg->code_size);
7544 #endif /* DISABLE_JIT */
7547 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7550 CallInfo *cinfo = NULL;
7551 MonoMethodSignature *sig;
7553 int i, n, stack_area = 0;
7555 /* Keep this in sync with mono_arch_get_argument_info */
7557 if (enable_arguments) {
7558 /* Allocate a new area on the stack and save arguments there */
7559 sig = mono_method_signature (cfg->method);
7561 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7563 n = sig->param_count + sig->hasthis;
7565 stack_area = ALIGN_TO (n * 8, 16);
7567 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7569 for (i = 0; i < n; ++i) {
7570 inst = cfg->args [i];
7572 if (inst->opcode == OP_REGVAR)
7573 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7575 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7576 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7581 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7582 amd64_set_reg_template (code, AMD64_ARG_REG1);
7583 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7584 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7586 if (enable_arguments)
7587 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7601 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7604 int save_mode = SAVE_NONE;
7605 MonoMethod *method = cfg->method;
7606 MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
7609 switch (ret_type->type) {
7610 case MONO_TYPE_VOID:
7611 /* special case string .ctor icall */
7612 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7613 save_mode = SAVE_EAX;
7615 save_mode = SAVE_NONE;
7619 save_mode = SAVE_EAX;
7623 save_mode = SAVE_XMM;
7625 case MONO_TYPE_GENERICINST:
7626 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7627 save_mode = SAVE_EAX;
7631 case MONO_TYPE_VALUETYPE:
7632 save_mode = SAVE_STRUCT;
7635 save_mode = SAVE_EAX;
7639 /* Save the result and copy it into the proper argument register */
7640 switch (save_mode) {
7642 amd64_push_reg (code, AMD64_RAX);
7644 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7645 if (enable_arguments)
7646 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7650 if (enable_arguments)
7651 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7654 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7655 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7657 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7659 * The result is already in the proper argument register so no copying
7666 g_assert_not_reached ();
7669 /* Set %al since this is a varargs call */
7670 if (save_mode == SAVE_XMM)
7671 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7673 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7675 if (preserve_argument_registers) {
7676 for (i = 0; i < PARAM_REGS; ++i)
7677 amd64_push_reg (code, param_regs [i]);
7680 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7681 amd64_set_reg_template (code, AMD64_ARG_REG1);
7682 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7684 if (preserve_argument_registers) {
7685 for (i = PARAM_REGS - 1; i >= 0; --i)
7686 amd64_pop_reg (code, param_regs [i]);
7689 /* Restore result */
7690 switch (save_mode) {
7692 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7693 amd64_pop_reg (code, AMD64_RAX);
7699 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7700 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7701 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7706 g_assert_not_reached ();
7713 mono_arch_flush_icache (guint8 *code, gint size)
7719 mono_arch_flush_register_windows (void)
7724 mono_arch_is_inst_imm (gint64 imm)
7726 return amd64_is_imm32 (imm);
7730 * Determine whenever the trap whose info is in SIGINFO is caused by
7734 mono_arch_is_int_overflow (void *sigctx, void *info)
7741 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7743 rip = (guint8*)ctx.rip;
7745 if (IS_REX (rip [0])) {
7746 reg = amd64_rex_b (rip [0]);
7752 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7754 reg += x86_modrm_rm (rip [1]);
7794 g_assert_not_reached ();
7806 mono_arch_get_patch_offset (guint8 *code)
7812 * mono_breakpoint_clean_code:
7814 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7815 * breakpoints in the original code, they are removed in the copy.
7817 * Returns TRUE if no sw breakpoint was present.
7820 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7823 gboolean can_write = TRUE;
7825 * If method_start is non-NULL we need to perform bound checks, since we access memory
7826 * at code - offset we could go before the start of the method and end up in a different
7827 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7830 if (!method_start || code - offset >= method_start) {
7831 memcpy (buf, code - offset, size);
7833 int diff = code - method_start;
7834 memset (buf, 0, size);
7835 memcpy (buf + offset - diff, method_start, diff + size - offset);
7838 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7839 int idx = mono_breakpoint_info_index [i];
7843 ptr = mono_breakpoint_info [idx].address;
7844 if (ptr >= code && ptr < code + size) {
7845 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7847 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7848 buf [ptr - code] = saved_byte;
7854 #if defined(__native_client_codegen__)
7855 /* For membase calls, we want the base register. for Native Client, */
7856 /* all indirect calls have the following sequence with the given sizes: */
7857 /* mov %eXX,%eXX [2-3] */
7858 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
7859 /* and $0xffffffffffffffe0,%r11d [4] */
7860 /* add %r15,%r11 [3] */
7861 /* callq *%r11 [3] */
7864 /* Determine if code points to a NaCl call-through-register sequence, */
7865 /* (i.e., the last 3 instructions listed above) */
7867 is_nacl_call_reg_sequence(guint8* code)
7869 const char *sequence = "\x41\x83\xe3\xe0" /* and */
7870 "\x4d\x03\xdf" /* add */
7871 "\x41\xff\xd3"; /* call */
7872 return memcmp(code, sequence, 10) == 0;
7875 /* Determine if code points to the first opcode of the mov membase component */
7876 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7877 /* (there could be a REX prefix before the opcode but it is ignored) */
7879 is_nacl_indirect_call_membase_sequence(guint8* code)
7881 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7882 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7883 /* and that src reg = dest reg */
7884 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7885 /* Check that next inst is mov, uses SIB byte (rm = 4), */
7887 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7888 /* and has dst of r11 and base of r15 */
7889 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7890 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7892 #endif /* __native_client_codegen__ */
7895 mono_arch_get_this_arg_reg (guint8 *code)
7897 return AMD64_ARG_REG1;
7901 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7903 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7906 #define MAX_ARCH_DELEGATE_PARAMS 10
7909 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7911 guint8 *code, *start;
7915 start = code = mono_global_codeman_reserve (64);
7917 /* Replace the this argument with the target */
7918 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7919 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7920 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7922 g_assert ((code - start) < 64);
7924 start = code = mono_global_codeman_reserve (64);
7926 if (param_count == 0) {
7927 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7929 /* We have to shift the arguments left */
7930 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7931 for (i = 0; i < param_count; ++i) {
7934 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7936 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7938 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7942 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7944 g_assert ((code - start) < 64);
7947 nacl_global_codeman_validate(&start, 64, &code);
7949 mono_debug_add_delegate_trampoline (start, code - start);
7952 *code_len = code - start;
7955 if (mono_jit_map_is_enabled ()) {
7958 buff = (char*)"delegate_invoke_has_target";
7960 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7961 mono_emit_jit_tramp (start, code - start, buff);
7970 * mono_arch_get_delegate_invoke_impls:
7972 * Return a list of MonoTrampInfo structures for the delegate invoke impl
7976 mono_arch_get_delegate_invoke_impls (void)
7983 code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7984 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7986 for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7987 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7988 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7995 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7997 guint8 *code, *start;
8000 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8003 /* FIXME: Support more cases */
8004 if (MONO_TYPE_ISSTRUCT (sig->ret))
8008 static guint8* cached = NULL;
8014 start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8016 start = get_delegate_invoke_impl (TRUE, 0, NULL);
8018 mono_memory_barrier ();
8022 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8023 for (i = 0; i < sig->param_count; ++i)
8024 if (!mono_is_regsize_var (sig->params [i]))
8026 if (sig->param_count > 4)
8029 code = cache [sig->param_count];
8033 if (mono_aot_only) {
8034 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8035 start = mono_aot_get_trampoline (name);
8038 start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8041 mono_memory_barrier ();
8043 cache [sig->param_count] = start;
8049 mono_arch_finish_init (void)
8053 * We need to init this multiple times, since when we are first called, the key might not
8054 * be initialized yet.
8056 appdomain_tls_offset = mono_domain_get_tls_key ();
8057 lmf_tls_offset = mono_get_jit_tls_key ();
8058 lmf_addr_tls_offset = mono_get_jit_tls_key ();
8060 /* Only 64 tls entries can be accessed using inline code */
8061 if (appdomain_tls_offset >= 64)
8062 appdomain_tls_offset = -1;
8063 if (lmf_tls_offset >= 64)
8064 lmf_tls_offset = -1;
8067 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8069 appdomain_tls_offset = mono_domain_get_tls_offset ();
8070 lmf_tls_offset = mono_get_lmf_tls_offset ();
8071 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
8076 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8080 #ifdef MONO_ARCH_HAVE_IMT
8082 #if defined(__default_codegen__)
8083 #define CMP_SIZE (6 + 1)
8084 #define CMP_REG_REG_SIZE (4 + 1)
8085 #define BR_SMALL_SIZE 2
8086 #define BR_LARGE_SIZE 6
8087 #define MOV_REG_IMM_SIZE 10
8088 #define MOV_REG_IMM_32BIT_SIZE 6
8089 #define JUMP_REG_SIZE (2 + 1)
8090 #elif defined(__native_client_codegen__)
8091 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8092 #define CMP_SIZE ((6 + 1) * 2 - 1)
8093 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8094 #define BR_SMALL_SIZE (2 * 2 - 1)
8095 #define BR_LARGE_SIZE (6 * 2 - 1)
8096 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8097 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8098 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8099 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8100 /* Jump membase's size is large and unpredictable */
8101 /* in native client, just pad it out a whole bundle. */
8102 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8106 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8108 int i, distance = 0;
8109 for (i = start; i < target; ++i)
8110 distance += imt_entries [i]->chunk_size;
8115 * LOCKING: called with the domain lock held
8118 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8119 gpointer fail_tramp)
8123 guint8 *code, *start;
8124 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8126 for (i = 0; i < count; ++i) {
8127 MonoIMTCheckItem *item = imt_entries [i];
8128 if (item->is_equals) {
8129 if (item->check_target_idx) {
8130 if (!item->compare_done) {
8131 if (amd64_is_imm32 (item->key))
8132 item->chunk_size += CMP_SIZE;
8134 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8136 if (item->has_target_code) {
8137 item->chunk_size += MOV_REG_IMM_SIZE;
8139 if (vtable_is_32bit)
8140 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8142 item->chunk_size += MOV_REG_IMM_SIZE;
8143 #ifdef __native_client_codegen__
8144 item->chunk_size += JUMP_MEMBASE_SIZE;
8147 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8150 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8151 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8153 if (vtable_is_32bit)
8154 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8156 item->chunk_size += MOV_REG_IMM_SIZE;
8157 item->chunk_size += JUMP_REG_SIZE;
8158 /* with assert below:
8159 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8161 #ifdef __native_client_codegen__
8162 item->chunk_size += JUMP_MEMBASE_SIZE;
8167 if (amd64_is_imm32 (item->key))
8168 item->chunk_size += CMP_SIZE;
8170 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8171 item->chunk_size += BR_LARGE_SIZE;
8172 imt_entries [item->check_target_idx]->compare_done = TRUE;
8174 size += item->chunk_size;
8176 #if defined(__native_client__) && defined(__native_client_codegen__)
8177 /* In Native Client, we don't re-use thunks, allocate from the */
8178 /* normal code manager paths. */
8179 code = mono_domain_code_reserve (domain, size);
8182 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8184 code = mono_domain_code_reserve (domain, size);
8187 for (i = 0; i < count; ++i) {
8188 MonoIMTCheckItem *item = imt_entries [i];
8189 item->code_target = code;
8190 if (item->is_equals) {
8191 gboolean fail_case = !item->check_target_idx && fail_tramp;
8193 if (item->check_target_idx || fail_case) {
8194 if (!item->compare_done || fail_case) {
8195 if (amd64_is_imm32 (item->key))
8196 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8198 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8199 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8202 item->jmp_code = code;
8203 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8204 if (item->has_target_code) {
8205 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8206 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8208 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8209 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8213 amd64_patch (item->jmp_code, code);
8214 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8215 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8216 item->jmp_code = NULL;
8219 /* enable the commented code to assert on wrong method */
8221 if (amd64_is_imm32 (item->key))
8222 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8224 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8225 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8227 item->jmp_code = code;
8228 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8229 /* See the comment below about R10 */
8230 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8231 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8232 amd64_patch (item->jmp_code, code);
8233 amd64_breakpoint (code);
8234 item->jmp_code = NULL;
8236 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8237 needs to be preserved. R10 needs
8238 to be preserved for calls which
8239 require a runtime generic context,
8240 but interface calls don't. */
8241 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8242 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8246 if (amd64_is_imm32 (item->key))
8247 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
8249 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8250 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8252 item->jmp_code = code;
8253 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8254 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8256 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8258 g_assert (code - item->code_target <= item->chunk_size);
8260 /* patch the branches to get to the target items */
8261 for (i = 0; i < count; ++i) {
8262 MonoIMTCheckItem *item = imt_entries [i];
8263 if (item->jmp_code) {
8264 if (item->check_target_idx) {
8265 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8271 mono_stats.imt_thunks_size += code - start;
8272 g_assert (code - start <= size);
8274 nacl_domain_code_validate(domain, &start, size, &code);
8280 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8282 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8287 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8289 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8293 mono_arch_get_cie_program (void)
8297 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8298 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8304 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8306 MonoInst *ins = NULL;
8309 if (cmethod->klass == mono_defaults.math_class) {
8310 if (strcmp (cmethod->name, "Sin") == 0) {
8312 } else if (strcmp (cmethod->name, "Cos") == 0) {
8314 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8316 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8321 MONO_INST_NEW (cfg, ins, opcode);
8322 ins->type = STACK_R8;
8323 ins->dreg = mono_alloc_freg (cfg);
8324 ins->sreg1 = args [0]->dreg;
8325 MONO_ADD_INS (cfg->cbb, ins);
8329 if (cfg->opt & MONO_OPT_CMOV) {
8330 if (strcmp (cmethod->name, "Min") == 0) {
8331 if (fsig->params [0]->type == MONO_TYPE_I4)
8333 if (fsig->params [0]->type == MONO_TYPE_U4)
8334 opcode = OP_IMIN_UN;
8335 else if (fsig->params [0]->type == MONO_TYPE_I8)
8337 else if (fsig->params [0]->type == MONO_TYPE_U8)
8338 opcode = OP_LMIN_UN;
8339 } else if (strcmp (cmethod->name, "Max") == 0) {
8340 if (fsig->params [0]->type == MONO_TYPE_I4)
8342 if (fsig->params [0]->type == MONO_TYPE_U4)
8343 opcode = OP_IMAX_UN;
8344 else if (fsig->params [0]->type == MONO_TYPE_I8)
8346 else if (fsig->params [0]->type == MONO_TYPE_U8)
8347 opcode = OP_LMAX_UN;
8352 MONO_INST_NEW (cfg, ins, opcode);
8353 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8354 ins->dreg = mono_alloc_ireg (cfg);
8355 ins->sreg1 = args [0]->dreg;
8356 ins->sreg2 = args [1]->dreg;
8357 MONO_ADD_INS (cfg->cbb, ins);
8361 /* OP_FREM is not IEEE compatible */
8362 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8363 MONO_INST_NEW (cfg, ins, OP_FREM);
8364 ins->inst_i0 = args [0];
8365 ins->inst_i1 = args [1];
8371 * Can't implement CompareExchange methods this way since they have
8379 mono_arch_print_tree (MonoInst *tree, int arity)
8384 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
8388 if (appdomain_tls_offset == -1)
8391 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
8392 ins->inst_offset = appdomain_tls_offset;
8396 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8399 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8402 case AMD64_RCX: return ctx->rcx;
8403 case AMD64_RDX: return ctx->rdx;
8404 case AMD64_RBX: return ctx->rbx;
8405 case AMD64_RBP: return ctx->rbp;
8406 case AMD64_RSP: return ctx->rsp;
8409 return _CTX_REG (ctx, rax, reg);
8411 return _CTX_REG (ctx, r12, reg - 12);
8413 g_assert_not_reached ();
8418 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8438 _CTX_REG (ctx, rax, reg) = val;
8440 _CTX_REG (ctx, r12, reg - 12) = val;
8442 g_assert_not_reached ();
8446 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8448 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8451 gpointer *sp, old_value;
8453 const unsigned char *handler;
8455 /*Decode the first instruction to figure out where did we store the spvar*/
8456 /*Our jit MUST generate the following:
8459 Which is encoded as: REX.W 0x89 mod_rm
8460 mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8461 mod (reg + imm8): 01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8462 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8464 FIXME can we generate frameless methods on this case?
8467 handler = clause->handler_start;
8470 if (*handler != 0x48)
8475 if (*handler != 0x89)
8479 if (*handler == 0x65)
8480 offset = *(signed char*)(handler + 1);
8481 else if (*handler == 0xA5)
8482 offset = *(int*)(handler + 1);
8487 bp = MONO_CONTEXT_GET_BP (ctx);
8488 sp = *(gpointer*)(bp + offset);
8491 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8500 * mono_arch_emit_load_aotconst:
8502 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8503 * TARGET from the mscorlib GOT in full-aot code.
8504 * On AMD64, the result is placed into R11.
8507 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8509 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8510 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8516 * mono_arch_get_trampolines:
8518 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8522 mono_arch_get_trampolines (gboolean aot)
8524 return mono_amd64_get_exception_trampolines (aot);
8527 /* Soft Debug support */
8528 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8531 * mono_arch_set_breakpoint:
8533 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8534 * The location should contain code emitted by OP_SEQ_POINT.
8537 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8540 guint8 *orig_code = code;
8543 guint32 native_offset = ip - (guint8*)ji->code_start;
8544 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8546 g_assert (info->bp_addrs [native_offset] == 0);
8547 info->bp_addrs [native_offset] = bp_trigger_page;
8550 * In production, we will use int3 (has to fix the size in the md
8551 * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8554 g_assert (code [0] == 0x90);
8555 if (breakpoint_size == 8) {
8556 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8558 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8559 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8562 g_assert (code - orig_code == breakpoint_size);
8567 * mono_arch_clear_breakpoint:
8569 * Clear the breakpoint at IP.
8572 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8578 guint32 native_offset = ip - (guint8*)ji->code_start;
8579 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8581 g_assert (info->bp_addrs [native_offset] == 0);
8582 info->bp_addrs [native_offset] = info;
8584 for (i = 0; i < breakpoint_size; ++i)
8590 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8593 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8596 siginfo_t* sinfo = (siginfo_t*) info;
8597 /* Sometimes the address is off by 4 */
8598 if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8606 * mono_arch_skip_breakpoint:
8608 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8609 * we resume, the instruction is not executed again.
8612 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8615 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8616 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8618 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8623 * mono_arch_start_single_stepping:
8625 * Start single stepping.
8628 mono_arch_start_single_stepping (void)
8630 mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8634 * mono_arch_stop_single_stepping:
8636 * Stop single stepping.
8639 mono_arch_stop_single_stepping (void)
8641 mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8645 * mono_arch_is_single_step_event:
8647 * Return whenever the machine state in SIGCTX corresponds to a single
8651 mono_arch_is_single_step_event (void *info, void *sigctx)
8654 EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8657 siginfo_t* sinfo = (siginfo_t*) info;
8658 /* Sometimes the address is off by 4 */
8659 if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8667 * mono_arch_skip_single_step:
8669 * Modify CTX so the ip is placed after the single step trigger instruction,
8670 * we resume, the instruction is not executed again.
8673 mono_arch_skip_single_step (MonoContext *ctx)
8675 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8679 * mono_arch_create_seq_point_info:
8681 * Return a pointer to a data structure which is used by the sequence
8682 * point implementation in AOTed code.
8685 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8691 // FIXME: Add a free function
8693 mono_domain_lock (domain);
8694 info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8696 mono_domain_unlock (domain);
8699 ji = mono_jit_info_table_find (domain, (char*)code);
8702 // FIXME: Optimize the size
8703 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8705 info->ss_trigger_page = ss_trigger_page;
8706 info->bp_trigger_page = bp_trigger_page;
8707 /* Initialize to a valid address */
8708 for (i = 0; i < ji->code_size; ++i)
8709 info->bp_addrs [i] = info;
8711 mono_domain_lock (domain);
8712 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8714 mono_domain_unlock (domain);