mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 static gint lmf_tls_offset = -1;
  34 static gint lmf_addr_tls_offset = -1;
  35 static gint appdomain_tls_offset = -1;
  36 static gint thread_tls_offset = -1;
  37
  38 #ifdef MONO_XEN_OPT
  39 static gboolean optimize_for_xen = TRUE;
  40 #else
  41 #define optimize_for_xen 0
  42 #endif
  43
  44 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  45
  46 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  47
  48 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  49
  50 #ifdef PLATFORM_WIN32
  51 /* Under windows, the default pinvoke calling convention is stdcall */
  52 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  53 #else
  54 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  55 #endif
  56
  57 /* This mutex protects architecture specific caches */
  58 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  59 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  60 static CRITICAL_SECTION mini_arch_mutex;
  61
  62 MonoBreakpointInfo
  63 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  64
  65 #define ARGS_OFFSET 16
  66 #define GP_SCRATCH_REG AMD64_R11
  67
  68 /*
  69  * AMD64 register usage:
  70  * - callee saved registers are used for global register allocation
  71  * - %r11 is used for materializing 64 bit constants in opcodes
  72  * - the rest is used for local allocation
  73  */
  74
  75 /*
  76  * Floating point comparison results:
  77  *                  ZF PF CF
  78  * A > B            0  0  0
  79  * A < B            0  0  1
  80  * A = B            1  0  0
  81  * A > B            0  0  0
  82  * UNORDERED        1  1  1
  83  */
  84
  85 const char*
  86 mono_arch_regname (int reg)
  87 {
  88         switch (reg) {
  89         case AMD64_RAX: return "%rax";
  90         case AMD64_RBX: return "%rbx";
  91         case AMD64_RCX: return "%rcx";
  92         case AMD64_RDX: return "%rdx";
  93         case AMD64_RSP: return "%rsp";
  94         case AMD64_RBP: return "%rbp";
  95         case AMD64_RDI: return "%rdi";
  96         case AMD64_RSI: return "%rsi";
  97         case AMD64_R8: return "%r8";
  98         case AMD64_R9: return "%r9";
  99         case AMD64_R10: return "%r10";
 100         case AMD64_R11: return "%r11";
 101         case AMD64_R12: return "%r12";
 102         case AMD64_R13: return "%r13";
 103         case AMD64_R14: return "%r14";
 104         case AMD64_R15: return "%r15";
 105         }
 106         return "unknown";
 107 }
 108
 109 static const char * xmmregs [] = {
 110         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 111         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 112 };
 113
 114 const char*
 115 mono_arch_fregname (int reg)
 116 {
 117         if (reg < AMD64_XMM_NREG)
 118                 return xmmregs [reg];
 119         else
 120                 return "unknown";
 121 }
 122
 123 G_GNUC_UNUSED static void
 124 break_count (void)
 125 {
 126 }
 127
 128 G_GNUC_UNUSED static gboolean
 129 debug_count (void)
 130 {
 131         static int count = 0;
 132         count ++;
 133
 134         if (!getenv ("COUNT"))
 135                 return TRUE;
 136
 137         if (count == atoi (getenv ("COUNT"))) {
 138                 break_count ();
 139         }
 140
 141         if (count > atoi (getenv ("COUNT"))) {
 142                 return FALSE;
 143         }
 144
 145         return TRUE;
 146 }
 147
 148 static gboolean
 149 debug_omit_fp (void)
 150 {
 151 #if 0
 152         return debug_count ();
 153 #else
 154         return TRUE;
 155 #endif
 156 }
 157
 158 static inline gboolean
 159 amd64_is_near_call (guint8 *code)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         return code [0] == 0xe8;
 166 }
 167
 168 static inline void
 169 amd64_patch (unsigned char* code, gpointer target)
 170 {
 171         /* Skip REX */
 172         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 173                 code += 1;
 174
 175         if ((code [0] & 0xf8) == 0xb8) {
 176                 /* amd64_set_reg_template */
 177                 *(guint64*)(code + 1) = (guint64)target;
 178         }
 179         else if (code [0] == 0x8b) {
 180                 /* mov 0(%rip), %dreg */
 181                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 182         }
 183         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 184                 /* call *<OFFSET>(%rip) */
 185                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 186         }
 187         else if ((code [0] == 0xe8)) {
 188                 /* call <DISP> */
 189                 gint64 disp = (guint8*)target - (guint8*)code;
 190                 g_assert (amd64_is_imm32 (disp));
 191                 x86_patch (code, (unsigned char*)target);
 192         }
 193         else
 194                 x86_patch (code, (unsigned char*)target);
 195 }
 196
 197 void
 198 mono_amd64_patch (unsigned char* code, gpointer target)
 199 {
 200         amd64_patch (code, target);
 201 }
 202
 203 typedef enum {
 204         ArgInIReg,
 205         ArgInFloatSSEReg,
 206         ArgInDoubleSSEReg,
 207         ArgOnStack,
 208         ArgValuetypeInReg,
 209         ArgNone /* only in pair_storage */
 210 } ArgStorage;
 211
 212 typedef struct {
 213         gint16 offset;
 214         gint8  reg;
 215         ArgStorage storage;
 216
 217         /* Only if storage == ArgValuetypeInReg */
 218         ArgStorage pair_storage [2];
 219         gint8 pair_regs [2];
 220 } ArgInfo;
 221
 222 typedef struct {
 223         int nargs;
 224         guint32 stack_usage;
 225         guint32 reg_usage;
 226         guint32 freg_usage;
 227         gboolean need_stack_align;
 228         ArgInfo ret;
 229         ArgInfo sig_cookie;
 230         ArgInfo args [1];
 231 } CallInfo;
 232
 233 #define DEBUG(a) if (cfg->verbose_level > 1) a
 234
 235 #define NEW_ICONST(cfg,dest,val) do {   \
 236                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 237                 (dest)->opcode = OP_ICONST;     \
 238                 (dest)->inst_c0 = (val);        \
 239                 (dest)->type = STACK_I4;        \
 240         } while (0)
 241
 242 #ifdef PLATFORM_WIN32
 243 #define PARAM_REGS 4
 244
 245 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 246
 247 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 248 #else
 249 #define PARAM_REGS 6
 250
 251 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 252
 253  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 254 #endif
 255
 256 static void inline
 257 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 258 {
 259     ainfo->offset = *stack_size;
 260
 261     if (*gr >= PARAM_REGS) {
 262                 ainfo->storage = ArgOnStack;
 263                 (*stack_size) += sizeof (gpointer);
 264     }
 265     else {
 266                 ainfo->storage = ArgInIReg;
 267                 ainfo->reg = param_regs [*gr];
 268                 (*gr) ++;
 269     }
 270 }
 271
 272 #ifdef PLATFORM_WIN32
 273 #define FLOAT_PARAM_REGS 4
 274 #else
 275 #define FLOAT_PARAM_REGS 8
 276 #endif
 277
 278 static void inline
 279 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 280 {
 281     ainfo->offset = *stack_size;
 282
 283     if (*gr >= FLOAT_PARAM_REGS) {
 284                 ainfo->storage = ArgOnStack;
 285                 (*stack_size) += sizeof (gpointer);
 286     }
 287     else {
 288                 /* A double register */
 289                 if (is_double)
 290                         ainfo->storage = ArgInDoubleSSEReg;
 291                 else
 292                         ainfo->storage = ArgInFloatSSEReg;
 293                 ainfo->reg = *gr;
 294                 (*gr) += 1;
 295     }
 296 }
 297
 298 typedef enum ArgumentClass {
 299         ARG_CLASS_NO_CLASS,
 300         ARG_CLASS_MEMORY,
 301         ARG_CLASS_INTEGER,
 302         ARG_CLASS_SSE
 303 } ArgumentClass;
 304
 305 static ArgumentClass
 306 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 307 {
 308         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 309         MonoType *ptype;
 310
 311         ptype = mono_type_get_underlying_type (type);
 312         switch (ptype->type) {
 313         case MONO_TYPE_BOOLEAN:
 314         case MONO_TYPE_CHAR:
 315         case MONO_TYPE_I1:
 316         case MONO_TYPE_U1:
 317         case MONO_TYPE_I2:
 318         case MONO_TYPE_U2:
 319         case MONO_TYPE_I4:
 320         case MONO_TYPE_U4:
 321         case MONO_TYPE_I:
 322         case MONO_TYPE_U:
 323         case MONO_TYPE_STRING:
 324         case MONO_TYPE_OBJECT:
 325         case MONO_TYPE_CLASS:
 326         case MONO_TYPE_SZARRAY:
 327         case MONO_TYPE_PTR:
 328         case MONO_TYPE_FNPTR:
 329         case MONO_TYPE_ARRAY:
 330         case MONO_TYPE_I8:
 331         case MONO_TYPE_U8:
 332                 class2 = ARG_CLASS_INTEGER;
 333                 break;
 334         case MONO_TYPE_R4:
 335         case MONO_TYPE_R8:
 336                 class2 = ARG_CLASS_SSE;
 337                 break;
 338
 339         case MONO_TYPE_TYPEDBYREF:
 340                 g_assert_not_reached ();
 341
 342         case MONO_TYPE_GENERICINST:
 343                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 344                         class2 = ARG_CLASS_INTEGER;
 345                         break;
 346                 }
 347                 /* fall through */
 348         case MONO_TYPE_VALUETYPE: {
 349                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 350                 int i;
 351
 352                 for (i = 0; i < info->num_fields; ++i) {
 353                         class2 = class1;
 354                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 355                 }
 356                 break;
 357         }
 358         default:
 359                 g_assert_not_reached ();
 360         }
 361
 362         /* Merge */
 363         if (class1 == class2)
 364                 ;
 365         else if (class1 == ARG_CLASS_NO_CLASS)
 366                 class1 = class2;
 367         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 368                 class1 = ARG_CLASS_MEMORY;
 369         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 370                 class1 = ARG_CLASS_INTEGER;
 371         else
 372                 class1 = ARG_CLASS_SSE;
 373
 374         return class1;
 375 }
 376
 377 static void
 378 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 379                gboolean is_return,
 380                guint32 *gr, guint32 *fr, guint32 *stack_size)
 381 {
 382         guint32 size, quad, nquads, i;
 383         ArgumentClass args [2];
 384         MonoMarshalType *info;
 385         MonoClass *klass;
 386
 387         klass = mono_class_from_mono_type (type);
 388         if (sig->pinvoke)
 389                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 390         else
 391                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 392
 393         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 394                 /* Allways pass in memory */
 395                 ainfo->offset = *stack_size;
 396                 *stack_size += ALIGN_TO (size, 8);
 397                 ainfo->storage = ArgOnStack;
 398
 399                 return;
 400         }
 401
 402         /* FIXME: Handle structs smaller than 8 bytes */
 403         //if ((size % 8) != 0)
 404         //      NOT_IMPLEMENTED;
 405
 406         if (size > 8)
 407                 nquads = 2;
 408         else
 409                 nquads = 1;
 410
 411         /*
 412          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 413          * The X87 and SSEUP stuff is left out since there are no such types in
 414          * the CLR.
 415          */
 416         info = mono_marshal_load_type_info (klass);
 417         g_assert (info);
 418         if (info->native_size > 16) {
 419                 ainfo->offset = *stack_size;
 420                 *stack_size += ALIGN_TO (info->native_size, 8);
 421                 ainfo->storage = ArgOnStack;
 422
 423                 return;
 424         }
 425
 426         args [0] = ARG_CLASS_NO_CLASS;
 427         args [1] = ARG_CLASS_NO_CLASS;
 428         for (quad = 0; quad < nquads; ++quad) {
 429                 int size;
 430                 guint32 align;
 431                 ArgumentClass class1;
 432
 433                 class1 = ARG_CLASS_NO_CLASS;
 434                 for (i = 0; i < info->num_fields; ++i) {
 435                         size = mono_marshal_type_size (info->fields [i].field->type,
 436                                                                                    info->fields [i].mspec,
 437                                                                                    &align, TRUE, klass->unicode);
 438                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 439                                 /* Unaligned field */
 440                                 NOT_IMPLEMENTED;
 441                         }
 442
 443                         /* Skip fields in other quad */
 444                         if ((quad == 0) && (info->fields [i].offset >= 8))
 445                                 continue;
 446                         if ((quad == 1) && (info->fields [i].offset < 8))
 447                                 continue;
 448
 449                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 450                 }
 451                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 452                 args [quad] = class1;
 453         }
 454
 455         /* Post merger cleanup */
 456         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 457                 args [0] = args [1] = ARG_CLASS_MEMORY;
 458
 459         /* Allocate registers */
 460         {
 461                 int orig_gr = *gr;
 462                 int orig_fr = *fr;
 463
 464                 ainfo->storage = ArgValuetypeInReg;
 465                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 466                 for (quad = 0; quad < nquads; ++quad) {
 467                         switch (args [quad]) {
 468                         case ARG_CLASS_INTEGER:
 469                                 if (*gr >= PARAM_REGS)
 470                                         args [quad] = ARG_CLASS_MEMORY;
 471                                 else {
 472                                         ainfo->pair_storage [quad] = ArgInIReg;
 473                                         if (is_return)
 474                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 475                                         else
 476                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 477                                         (*gr) ++;
 478                                 }
 479                                 break;
 480                         case ARG_CLASS_SSE:
 481                                 if (*fr >= FLOAT_PARAM_REGS)
 482                                         args [quad] = ARG_CLASS_MEMORY;
 483                                 else {
 484                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 485                                         ainfo->pair_regs [quad] = *fr;
 486                                         (*fr) ++;
 487                                 }
 488                                 break;
 489                         case ARG_CLASS_MEMORY:
 490                                 break;
 491                         default:
 492                                 g_assert_not_reached ();
 493                         }
 494                 }
 495
 496                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 497                         /* Revert possible register assignments */
 498                         *gr = orig_gr;
 499                         *fr = orig_fr;
 500
 501                         ainfo->offset = *stack_size;
 502                         *stack_size += ALIGN_TO (info->native_size, 8);
 503                         ainfo->storage = ArgOnStack;
 504                 }
 505         }
 506 }
 507
 508 /*
 509  * get_call_info:
 510  *
 511  *  Obtain information about a call according to the calling convention.
 512  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 513  * Draft Version 0.23" document for more information.
 514  */
 515 static CallInfo*
 516 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 517 {
 518         guint32 i, gr, fr;
 519         MonoType *ret_type;
 520         int n = sig->hasthis + sig->param_count;
 521         guint32 stack_size = 0;
 522         CallInfo *cinfo;
 523
 524         if (mp)
 525                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 526         else
 527                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 528
 529         gr = 0;
 530         fr = 0;
 531
 532         /* return value */
 533         {
 534                 ret_type = mono_type_get_underlying_type (sig->ret);
 535                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 536                 switch (ret_type->type) {
 537                 case MONO_TYPE_BOOLEAN:
 538                 case MONO_TYPE_I1:
 539                 case MONO_TYPE_U1:
 540                 case MONO_TYPE_I2:
 541                 case MONO_TYPE_U2:
 542                 case MONO_TYPE_CHAR:
 543                 case MONO_TYPE_I4:
 544                 case MONO_TYPE_U4:
 545                 case MONO_TYPE_I:
 546                 case MONO_TYPE_U:
 547                 case MONO_TYPE_PTR:
 548                 case MONO_TYPE_FNPTR:
 549                 case MONO_TYPE_CLASS:
 550                 case MONO_TYPE_OBJECT:
 551                 case MONO_TYPE_SZARRAY:
 552                 case MONO_TYPE_ARRAY:
 553                 case MONO_TYPE_STRING:
 554                         cinfo->ret.storage = ArgInIReg;
 555                         cinfo->ret.reg = AMD64_RAX;
 556                         break;
 557                 case MONO_TYPE_U8:
 558                 case MONO_TYPE_I8:
 559                         cinfo->ret.storage = ArgInIReg;
 560                         cinfo->ret.reg = AMD64_RAX;
 561                         break;
 562                 case MONO_TYPE_R4:
 563                         cinfo->ret.storage = ArgInFloatSSEReg;
 564                         cinfo->ret.reg = AMD64_XMM0;
 565                         break;
 566                 case MONO_TYPE_R8:
 567                         cinfo->ret.storage = ArgInDoubleSSEReg;
 568                         cinfo->ret.reg = AMD64_XMM0;
 569                         break;
 570                 case MONO_TYPE_GENERICINST:
 571                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 572                                 cinfo->ret.storage = ArgInIReg;
 573                                 cinfo->ret.reg = AMD64_RAX;
 574                                 break;
 575                         }
 576                         /* fall through */
 577                 case MONO_TYPE_VALUETYPE: {
 578                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 579
 580                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 581                         if (cinfo->ret.storage == ArgOnStack)
 582                                 /* The caller passes the address where the value is stored */
 583                                 add_general (&gr, &stack_size, &cinfo->ret);
 584                         break;
 585                 }
 586                 case MONO_TYPE_TYPEDBYREF:
 587                         /* Same as a valuetype with size 24 */
 588                         add_general (&gr, &stack_size, &cinfo->ret);
 589                         ;
 590                         break;
 591                 case MONO_TYPE_VOID:
 592                         break;
 593                 default:
 594                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 595                 }
 596         }
 597
 598         /* this */
 599         if (sig->hasthis)
 600                 add_general (&gr, &stack_size, cinfo->args + 0);
 601
 602         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 603                 gr = PARAM_REGS;
 604                 fr = FLOAT_PARAM_REGS;
 605
 606                 /* Emit the signature cookie just before the implicit arguments */
 607                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 608         }
 609
 610         for (i = 0; i < sig->param_count; ++i) {
 611                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 612                 MonoType *ptype;
 613
 614                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 615                         /* We allways pass the sig cookie on the stack for simplicity */
 616                         /*
 617                          * Prevent implicit arguments + the sig cookie from being passed
 618                          * in registers.
 619                          */
 620                         gr = PARAM_REGS;
 621                         fr = FLOAT_PARAM_REGS;
 622
 623                         /* Emit the signature cookie just before the implicit arguments */
 624                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 625                 }
 626
 627                 if (sig->params [i]->byref) {
 628                         add_general (&gr, &stack_size, ainfo);
 629                         continue;
 630                 }
 631                 ptype = mono_type_get_underlying_type (sig->params [i]);
 632                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 633                 switch (ptype->type) {
 634                 case MONO_TYPE_BOOLEAN:
 635                 case MONO_TYPE_I1:
 636                 case MONO_TYPE_U1:
 637                         add_general (&gr, &stack_size, ainfo);
 638                         break;
 639                 case MONO_TYPE_I2:
 640                 case MONO_TYPE_U2:
 641                 case MONO_TYPE_CHAR:
 642                         add_general (&gr, &stack_size, ainfo);
 643                         break;
 644                 case MONO_TYPE_I4:
 645                 case MONO_TYPE_U4:
 646                         add_general (&gr, &stack_size, ainfo);
 647                         break;
 648                 case MONO_TYPE_I:
 649                 case MONO_TYPE_U:
 650                 case MONO_TYPE_PTR:
 651                 case MONO_TYPE_FNPTR:
 652                 case MONO_TYPE_CLASS:
 653                 case MONO_TYPE_OBJECT:
 654                 case MONO_TYPE_STRING:
 655                 case MONO_TYPE_SZARRAY:
 656                 case MONO_TYPE_ARRAY:
 657                         add_general (&gr, &stack_size, ainfo);
 658                         break;
 659                 case MONO_TYPE_GENERICINST:
 660                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 661                                 add_general (&gr, &stack_size, ainfo);
 662                                 break;
 663                         }
 664                         /* fall through */
 665                 case MONO_TYPE_VALUETYPE:
 666                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 667                         break;
 668                 case MONO_TYPE_TYPEDBYREF:
 669                         stack_size += sizeof (MonoTypedRef);
 670                         ainfo->storage = ArgOnStack;
 671                         break;
 672                 case MONO_TYPE_U8:
 673                 case MONO_TYPE_I8:
 674                         add_general (&gr, &stack_size, ainfo);
 675                         break;
 676                 case MONO_TYPE_R4:
 677                         add_float (&fr, &stack_size, ainfo, FALSE);
 678                         break;
 679                 case MONO_TYPE_R8:
 680                         add_float (&fr, &stack_size, ainfo, TRUE);
 681                         break;
 682                 default:
 683                         g_assert_not_reached ();
 684                 }
 685         }
 686
 687         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 688                 gr = PARAM_REGS;
 689                 fr = FLOAT_PARAM_REGS;
 690
 691                 /* Emit the signature cookie just before the implicit arguments */
 692                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 693         }
 694
 695 #ifdef PLATFORM_WIN32
 696         if (stack_size < 32) {
 697                 /* The Win64 ABI requires 32 bits  */
 698                 stack_size = 32;
 699         }
 700 #endif
 701
 702         if (stack_size & 0x8) {
 703                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 704                 cinfo->need_stack_align = TRUE;
 705                 stack_size += 8;
 706         }
 707
 708         cinfo->stack_usage = stack_size;
 709         cinfo->reg_usage = gr;
 710         cinfo->freg_usage = fr;
 711         return cinfo;
 712 }
 713
 714 /*
 715  * mono_arch_get_argument_info:
 716  * @csig:  a method signature
 717  * @param_count: the number of parameters to consider
 718  * @arg_info: an array to store the result infos
 719  *
 720  * Gathers information on parameters such as size, alignment and
 721  * padding. arg_info should be large enought to hold param_count + 1 entries.
 722  *
 723  * Returns the size of the argument area on the stack.
 724  */
 725 int
 726 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 727 {
 728         int k;
 729         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 730         guint32 args_size = cinfo->stack_usage;
 731
 732         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 733         if (csig->hasthis) {
 734                 arg_info [0].offset = 0;
 735         }
 736
 737         for (k = 0; k < param_count; k++) {
 738                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 739                 /* FIXME: */
 740                 arg_info [k + 1].size = 0;
 741         }
 742
 743         g_free (cinfo);
 744
 745         return args_size;
 746 }
 747
 748 static int
 749 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 750 {
 751         __asm__ __volatile__ ("cpuid"
 752                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 753                 : "a" (id));
 754         return 1;
 755 }
 756
 757 /*
 758  * Initialize the cpu to execute managed code.
 759  */
 760 void
 761 mono_arch_cpu_init (void)
 762 {
 763 #ifndef _MSC_VER
 764         guint16 fpcw;
 765
 766         /* spec compliance requires running with double precision */
 767         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 768         fpcw &= ~X86_FPCW_PRECC_MASK;
 769         fpcw |= X86_FPCW_PREC_DOUBLE;
 770         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 771         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 772 #else
 773         _control87 (_PC_53, MCW_PC);
 774 #endif
 775 }
 776
 777 /*
 778  * Initialize architecture specific code.
 779  */
 780 void
 781 mono_arch_init (void)
 782 {
 783         InitializeCriticalSection (&mini_arch_mutex);
 784 }
 785
 786 /*
 787  * Cleanup architecture specific code.
 788  */
 789 void
 790 mono_arch_cleanup (void)
 791 {
 792         DeleteCriticalSection (&mini_arch_mutex);
 793 }
 794
 795 /*
 796  * This function returns the optimizations supported on this cpu.
 797  */
 798 guint32
 799 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 800 {
 801         int eax, ebx, ecx, edx;
 802         guint32 opts = 0;
 803
 804         /* FIXME: AMD64 */
 805
 806         *exclude_mask = 0;
 807         /* Feature Flags function, flags returned in EDX. */
 808         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 809                 if (edx & (1 << 15)) {
 810                         opts |= MONO_OPT_CMOV;
 811                         if (edx & 1)
 812                                 opts |= MONO_OPT_FCMOV;
 813                         else
 814                                 *exclude_mask |= MONO_OPT_FCMOV;
 815                 } else
 816                         *exclude_mask |= MONO_OPT_CMOV;
 817         }
 818         return opts;
 819 }
 820
 821 GList *
 822 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 823 {
 824         GList *vars = NULL;
 825         int i;
 826
 827         for (i = 0; i < cfg->num_varinfo; i++) {
 828                 MonoInst *ins = cfg->varinfo [i];
 829                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 830
 831                 /* unused vars */
 832                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 833                         continue;
 834
 835                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 836                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 837                         continue;
 838
 839                 if (mono_is_regsize_var (ins->inst_vtype)) {
 840                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 841                         g_assert (i == vmv->idx);
 842                         vars = g_list_prepend (vars, vmv);
 843                 }
 844         }
 845
 846         vars = mono_varlist_sort (cfg, vars, 0);
 847
 848         return vars;
 849 }
 850
 851 /**
 852  * mono_arch_compute_omit_fp:
 853  *
 854  *   Determine whenever the frame pointer can be eliminated.
 855  */
 856 static void
 857 mono_arch_compute_omit_fp (MonoCompile *cfg)
 858 {
 859         MonoMethodSignature *sig;
 860         MonoMethodHeader *header;
 861         int i, locals_size;
 862         CallInfo *cinfo;
 863
 864         if (cfg->arch.omit_fp_computed)
 865                 return;
 866
 867         header = mono_method_get_header (cfg->method);
 868
 869         sig = mono_method_signature (cfg->method);
 870
 871         if (!cfg->arch.cinfo)
 872                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 873         cinfo = cfg->arch.cinfo;
 874
 875         /*
 876          * FIXME: Remove some of the restrictions.
 877          */
 878         cfg->arch.omit_fp = TRUE;
 879         cfg->arch.omit_fp_computed = TRUE;
 880
 881         /* Temporarily disable this when running in the debugger until we have support
 882          * for this in the debugger. */
 883         if (mono_debug_using_mono_debugger ())
 884                 cfg->arch.omit_fp = FALSE;
 885
 886         if (!debug_omit_fp ())
 887                 cfg->arch.omit_fp = FALSE;
 888         /*
 889         if (cfg->method->save_lmf)
 890                 cfg->arch.omit_fp = FALSE;
 891         */
 892         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 893                 cfg->arch.omit_fp = FALSE;
 894         if (header->num_clauses)
 895                 cfg->arch.omit_fp = FALSE;
 896         if (cfg->param_area)
 897                 cfg->arch.omit_fp = FALSE;
 898         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 899                 cfg->arch.omit_fp = FALSE;
 900         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 901                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 902                 cfg->arch.omit_fp = FALSE;
 903         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 904                 ArgInfo *ainfo = &cinfo->args [i];
 905
 906                 if (ainfo->storage == ArgOnStack) {
 907                         /*
 908                          * The stack offset can only be determined when the frame
 909                          * size is known.
 910                          */
 911                         cfg->arch.omit_fp = FALSE;
 912                 }
 913         }
 914
 915         locals_size = 0;
 916         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 917                 MonoInst *ins = cfg->varinfo [i];
 918                 int ialign;
 919
 920                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
 921         }
 922
 923         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
 924                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 925                 cfg->arch.omit_fp = FALSE;
 926         }
 927 }
 928
 929 GList *
 930 mono_arch_get_global_int_regs (MonoCompile *cfg)
 931 {
 932         GList *regs = NULL;
 933
 934         mono_arch_compute_omit_fp (cfg);
 935
 936         if (cfg->arch.omit_fp)
 937                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 938
 939         /* We use the callee saved registers for global allocation */
 940         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 941         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 942         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 943         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 944         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 945
 946         return regs;
 947 }
 948
 949 /*
 950  * mono_arch_regalloc_cost:
 951  *
 952  *  Return the cost, in number of memory references, of the action of
 953  * allocating the variable VMV into a register during global register
 954  * allocation.
 955  */
 956 guint32
 957 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 958 {
 959         MonoInst *ins = cfg->varinfo [vmv->idx];
 960
 961         if (cfg->method->save_lmf)
 962                 /* The register is already saved */
 963                 /* substract 1 for the invisible store in the prolog */
 964                 return (ins->opcode == OP_ARG) ? 0 : 1;
 965         else
 966                 /* push+pop */
 967                 return (ins->opcode == OP_ARG) ? 1 : 2;
 968 }
 969
 970 void
 971 mono_arch_allocate_vars (MonoCompile *cfg)
 972 {
 973         MonoMethodSignature *sig;
 974         MonoMethodHeader *header;
 975         MonoInst *inst;
 976         int i, offset;
 977         guint32 locals_stack_size, locals_stack_align;
 978         gint32 *offsets;
 979         CallInfo *cinfo;
 980
 981         header = mono_method_get_header (cfg->method);
 982
 983         sig = mono_method_signature (cfg->method);
 984
 985         cinfo = cfg->arch.cinfo;
 986
 987         mono_arch_compute_omit_fp (cfg);
 988
 989         /*
 990          * We use the ABI calling conventions for managed code as well.
 991          * Exception: valuetypes are never passed or returned in registers.
 992          */
 993
 994         if (cfg->arch.omit_fp) {
 995                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 996                 cfg->frame_reg = AMD64_RSP;
 997                 offset = 0;
 998         } else {
 999                 /* Locals are allocated backwards from %fp */
1000                 cfg->frame_reg = AMD64_RBP;
1001                 offset = 0;
1002         }
1003
1004         if (cfg->method->save_lmf) {
1005                 /* Reserve stack space for saving LMF */
1006                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1007                 g_assert (offset == 0);
1008                 if (cfg->arch.omit_fp) {
1009                         cfg->arch.lmf_offset = offset;
1010                         offset += sizeof (MonoLMF);
1011                 }
1012                 else {
1013                         offset += sizeof (MonoLMF);
1014                         cfg->arch.lmf_offset = -offset;
1015                 }
1016         } else {
1017                 /* Reserve space for caller saved registers */
1018                 for (i = 0; i < AMD64_NREG; ++i)
1019                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1020                                 offset += sizeof (gpointer);
1021                         }
1022         }
1023
1024         if (sig->ret->type != MONO_TYPE_VOID) {
1025                 switch (cinfo->ret.storage) {
1026                 case ArgInIReg:
1027                 case ArgInFloatSSEReg:
1028                 case ArgInDoubleSSEReg:
1029                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1030                                 /* The register is volatile */
1031                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1032                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1033                                 if (cfg->arch.omit_fp) {
1034                                         cfg->vret_addr->inst_offset = offset;
1035                                         offset += 8;
1036                                 } else {
1037                                         offset += 8;
1038                                         cfg->vret_addr->inst_offset = -offset;
1039                                 }
1040                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1041                                         printf ("vret_addr =");
1042                                         mono_print_ins (cfg->vret_addr);
1043                                 }
1044                         }
1045                         else {
1046                                 cfg->ret->opcode = OP_REGVAR;
1047                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1048                         }
1049                         break;
1050                 case ArgValuetypeInReg:
1051                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1052                         cfg->ret->opcode = OP_REGOFFSET;
1053                         cfg->ret->inst_basereg = cfg->frame_reg;
1054                         if (cfg->arch.omit_fp) {
1055                                 cfg->ret->inst_offset = offset;
1056                                 offset += 16;
1057                         } else {
1058                                 offset += 16;
1059                                 cfg->ret->inst_offset = - offset;
1060                         }
1061                         break;
1062                 default:
1063                         g_assert_not_reached ();
1064                 }
1065                 cfg->ret->dreg = cfg->ret->inst_c0;
1066         }
1067
1068         /* Allocate locals */
1069         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1070         if (locals_stack_align) {
1071                 offset += (locals_stack_align - 1);
1072                 offset &= ~(locals_stack_align - 1);
1073         }
1074         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1075                 if (offsets [i] != -1) {
1076                         MonoInst *inst = cfg->varinfo [i];
1077                         inst->opcode = OP_REGOFFSET;
1078                         inst->inst_basereg = cfg->frame_reg;
1079                         if (cfg->arch.omit_fp)
1080                                 inst->inst_offset = (offset + offsets [i]);
1081                         else
1082                                 inst->inst_offset = - (offset + offsets [i]);
1083                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1084                 }
1085         }
1086         offset += locals_stack_size;
1087
1088         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1089                 g_assert (!cfg->arch.omit_fp);
1090                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1091                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1092         }
1093
1094         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1095                 inst = cfg->args [i];
1096                 if (inst->opcode != OP_REGVAR) {
1097                         ArgInfo *ainfo = &cinfo->args [i];
1098                         gboolean inreg = TRUE;
1099                         MonoType *arg_type;
1100
1101                         if (sig->hasthis && (i == 0))
1102                                 arg_type = &mono_defaults.object_class->byval_arg;
1103                         else
1104                                 arg_type = sig->params [i - sig->hasthis];
1105
1106                         /* FIXME: Allocate volatile arguments to registers */
1107                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1108                                 inreg = FALSE;
1109
1110                         /*
1111                          * Under AMD64, all registers used to pass arguments to functions
1112                          * are volatile across calls.
1113                          * FIXME: Optimize this.
1114                          */
1115                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1116                                 inreg = FALSE;
1117
1118                         inst->opcode = OP_REGOFFSET;
1119
1120                         switch (ainfo->storage) {
1121                         case ArgInIReg:
1122                         case ArgInFloatSSEReg:
1123                         case ArgInDoubleSSEReg:
1124                                 inst->opcode = OP_REGVAR;
1125                                 inst->dreg = ainfo->reg;
1126                                 break;
1127                         case ArgOnStack:
1128                                 g_assert (!cfg->arch.omit_fp);
1129                                 inst->opcode = OP_REGOFFSET;
1130                                 inst->inst_basereg = cfg->frame_reg;
1131                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1132                                 break;
1133                         case ArgValuetypeInReg:
1134                                 break;
1135                         default:
1136                                 NOT_IMPLEMENTED;
1137                         }
1138
1139                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1140                                 inst->opcode = OP_REGOFFSET;
1141                                 inst->inst_basereg = cfg->frame_reg;
1142                                 /* These arguments are saved to the stack in the prolog */
1143                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1144                                 if (cfg->arch.omit_fp) {
1145                                         inst->inst_offset = offset;
1146                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1147                                 } else {
1148                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1149                                         inst->inst_offset = - offset;
1150                                 }
1151                         }
1152                 }
1153         }
1154
1155         cfg->stack_offset = offset;
1156 }
1157
1158 void
1159 mono_arch_create_vars (MonoCompile *cfg)
1160 {
1161         MonoMethodSignature *sig;
1162         CallInfo *cinfo;
1163
1164         sig = mono_method_signature (cfg->method);
1165
1166         if (!cfg->arch.cinfo)
1167                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1168         cinfo = cfg->arch.cinfo;
1169
1170         if (cinfo->ret.storage == ArgValuetypeInReg)
1171                 cfg->ret_var_is_local = TRUE;
1172
1173         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1174                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1175                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1176                         printf ("vret_addr = ");
1177                         mono_print_ins (cfg->vret_addr);
1178                 }
1179         }
1180 }
1181
1182 static void
1183 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1184 {
1185         switch (storage) {
1186         case ArgInIReg:
1187                 arg->opcode = OP_OUTARG_REG;
1188                 arg->inst_left = tree;
1189                 arg->inst_call = call;
1190                 arg->backend.reg3 = reg;
1191                 break;
1192         case ArgInFloatSSEReg:
1193                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1194                 arg->inst_left = tree;
1195                 arg->inst_call = call;
1196                 arg->backend.reg3 = reg;
1197                 break;
1198         case ArgInDoubleSSEReg:
1199                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1200                 arg->inst_left = tree;
1201                 arg->inst_call = call;
1202                 arg->backend.reg3 = reg;
1203                 break;
1204         default:
1205                 g_assert_not_reached ();
1206         }
1207 }
1208
1209 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1210  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1211  */
1212
1213 static int
1214 arg_storage_to_ldind (ArgStorage storage)
1215 {
1216         switch (storage) {
1217         case ArgInIReg:
1218                 return CEE_LDIND_I;
1219         case ArgInDoubleSSEReg:
1220                 return CEE_LDIND_R8;
1221         case ArgInFloatSSEReg:
1222                 return CEE_LDIND_R4;
1223         default:
1224                 g_assert_not_reached ();
1225         }
1226
1227         return -1;
1228 }
1229
1230 static void
1231 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1232 {
1233         MonoInst *arg;
1234         MonoMethodSignature *tmp_sig;
1235         MonoInst *sig_arg;
1236
1237         /* FIXME: Add support for signature tokens to AOT */
1238         cfg->disable_aot = TRUE;
1239
1240         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1241
1242         /*
1243          * mono_ArgIterator_Setup assumes the signature cookie is
1244          * passed first and all the arguments which were before it are
1245          * passed on the stack after the signature. So compensate by
1246          * passing a different signature.
1247          */
1248         tmp_sig = mono_metadata_signature_dup (call->signature);
1249         tmp_sig->param_count -= call->signature->sentinelpos;
1250         tmp_sig->sentinelpos = 0;
1251         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1252
1253         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1254         sig_arg->inst_p0 = tmp_sig;
1255
1256         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1257         arg->inst_left = sig_arg;
1258         arg->type = STACK_PTR;
1259         MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1260 }
1261
1262 /*
1263  * take the arguments and generate the arch-specific
1264  * instructions to properly call the function in call.
1265  * This includes pushing, moving arguments to the right register
1266  * etc.
1267  * Issue: who does the spilling if needed, and when?
1268  */
1269 MonoCallInst*
1270 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1271         MonoInst *arg, *in;
1272         MonoMethodSignature *sig;
1273         int i, n, stack_size;
1274         CallInfo *cinfo;
1275         ArgInfo *ainfo;
1276
1277         stack_size = 0;
1278
1279         sig = call->signature;
1280         n = sig->param_count + sig->hasthis;
1281
1282         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1283
1284         for (i = 0; i < n; ++i) {
1285                 ainfo = cinfo->args + i;
1286
1287                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1288                         /* Emit the signature cookie just before the implicit arguments */
1289                         emit_sig_cookie (cfg, call, cinfo);
1290                 }
1291
1292                 if (is_virtual && i == 0) {
1293                         /* the argument will be attached to the call instruction */
1294                         in = call->args [i];
1295                 } else {
1296                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1297                         in = call->args [i];
1298                         arg->cil_code = in->cil_code;
1299                         arg->inst_left = in;
1300                         arg->type = in->type;
1301                         if (!cinfo->stack_usage)
1302                                 /* Keep the assignments to the arg registers in order if possible */
1303                                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1304                         else
1305                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1306
1307                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1308                                 guint32 align;
1309                                 guint32 size;
1310
1311                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1312                                         size = sizeof (MonoTypedRef);
1313                                         align = sizeof (gpointer);
1314                                 }
1315                                 else
1316                                 if (sig->pinvoke)
1317                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1318                                 else {
1319                                         /*
1320                                          * Other backends use mini_type_stack_size (), but that
1321                                          * aligns the size to 8, which is larger than the size of
1322                                          * the source, leading to reads of invalid memory if the
1323                                          * source is at the end of address space.
1324                                          */
1325                                         size = mono_class_value_size (in->klass, &align);
1326                                 }
1327                                 if (ainfo->storage == ArgValuetypeInReg) {
1328                                         if (ainfo->pair_storage [1] == ArgNone) {
1329                                                 MonoInst *load;
1330
1331                                                 /* Simpler case */
1332
1333                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1334                                                 load->inst_left = in;
1335
1336                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1337                                         }
1338                                         else {
1339                                                 /* Trees can't be shared so make a copy */
1340                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1341                                                 MonoInst *load, *load2, *offset_ins;
1342
1343                                                 /* Reg1 */
1344                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1345                                                 load->ssa_op = MONO_SSA_LOAD;
1346                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1347
1348                                                 NEW_ICONST (cfg, offset_ins, 0);
1349                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1350                                                 load2->inst_left = load;
1351                                                 load2->inst_right = offset_ins;
1352
1353                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1354                                                 load->inst_left = load2;
1355
1356                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1357
1358                                                 /* Reg2 */
1359                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1360                                                 load->ssa_op = MONO_SSA_LOAD;
1361                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1362
1363                                                 NEW_ICONST (cfg, offset_ins, 8);
1364                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1365                                                 load2->inst_left = load;
1366                                                 load2->inst_right = offset_ins;
1367
1368                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1369                                                 load->inst_left = load2;
1370
1371                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1372                                                 arg->cil_code = in->cil_code;
1373                                                 arg->type = in->type;
1374                                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1375
1376                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1377
1378                                                 /* Prepend a copy inst */
1379                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1380                                                 arg->cil_code = in->cil_code;
1381                                                 arg->ssa_op = MONO_SSA_STORE;
1382                                                 arg->inst_left = vtaddr;
1383                                                 arg->inst_right = in;
1384                                                 arg->type = in->type;
1385
1386                                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1387                                         }
1388                                 }
1389                                 else {
1390                                         arg->opcode = OP_OUTARG_VT;
1391                                         arg->klass = in->klass;
1392                                         arg->backend.is_pinvoke = sig->pinvoke;
1393                                         arg->inst_imm = size;
1394                                 }
1395                         }
1396                         else {
1397                                 switch (ainfo->storage) {
1398                                 case ArgInIReg:
1399                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1400                                         break;
1401                                 case ArgInFloatSSEReg:
1402                                 case ArgInDoubleSSEReg:
1403                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1404                                         break;
1405                                 case ArgOnStack:
1406                                         arg->opcode = OP_OUTARG;
1407                                         if (!sig->params [i - sig->hasthis]->byref) {
1408                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1409                                                         arg->opcode = OP_OUTARG_R4;
1410                                                 else
1411                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1412                                                                 arg->opcode = OP_OUTARG_R8;
1413                                         }
1414                                         break;
1415                                 default:
1416                                         g_assert_not_reached ();
1417                                 }
1418                         }
1419                 }
1420         }
1421
1422         /* Handle the case where there are no implicit arguments */
1423         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1424                 emit_sig_cookie (cfg, call, cinfo);
1425         }
1426
1427         if (cinfo->need_stack_align) {
1428                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1429                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1430         }
1431
1432         if (cfg->method->save_lmf) {
1433                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1434                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1435         }
1436
1437         call->stack_usage = cinfo->stack_usage;
1438         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1439         cfg->flags |= MONO_CFG_HAS_CALLS;
1440
1441         return call;
1442 }
1443
1444 #define EMIT_COND_BRANCH(ins,cond,sign) \
1445 if (ins->flags & MONO_INST_BRLABEL) { \
1446         if (ins->inst_i0->inst_c0) { \
1447                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1448         } else { \
1449                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1450                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1451                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1452                         x86_branch8 (code, cond, 0, sign); \
1453                 else \
1454                         x86_branch32 (code, cond, 0, sign); \
1455         } \
1456 } else { \
1457         if (ins->inst_true_bb->native_offset) { \
1458                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1459         } else { \
1460                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1461                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1462                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1463                         x86_branch8 (code, cond, 0, sign); \
1464                 else \
1465                         x86_branch32 (code, cond, 0, sign); \
1466         } \
1467 }
1468
1469 /* emit an exception if condition is fail */
1470 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1471         do {                                                        \
1472                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1473                 if (tins == NULL) {                                                                             \
1474                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1475                                         MONO_PATCH_INFO_EXC, exc_name);  \
1476                         x86_branch32 (code, cond, 0, signed);               \
1477                 } else {        \
1478                         EMIT_COND_BRANCH (tins, cond, signed);  \
1479                 }                       \
1480         } while (0);
1481
1482 #define EMIT_FPCOMPARE(code) do { \
1483         amd64_fcompp (code); \
1484         amd64_fnstsw (code); \
1485 } while (0);
1486
1487 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1488     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1489         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1490         amd64_ ##op (code); \
1491         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1492         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1493 } while (0);
1494
1495 static guint8*
1496 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1497 {
1498         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1499
1500         /*
1501          * FIXME: Add support for thunks
1502          */
1503         {
1504                 gboolean near_call = FALSE;
1505
1506                 /*
1507                  * Indirect calls are expensive so try to make a near call if possible.
1508                  * The caller memory is allocated by the code manager so it is
1509                  * guaranteed to be at a 32 bit offset.
1510                  */
1511
1512                 if (patch_type != MONO_PATCH_INFO_ABS) {
1513                         /* The target is in memory allocated using the code manager */
1514                         near_call = TRUE;
1515
1516                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1517                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1518                                         /* The callee might be an AOT method */
1519                                         near_call = FALSE;
1520                                 if (((MonoMethod*)data)->dynamic)
1521                                         /* The target is in malloc-ed memory */
1522                                         near_call = FALSE;
1523                         }
1524
1525                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1526                                 /*
1527                                  * The call might go directly to a native function without
1528                                  * the wrapper.
1529                                  */
1530                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1531                                 if (mi) {
1532                                         gconstpointer target = mono_icall_get_wrapper (mi);
1533                                         if ((((guint64)target) >> 32) != 0)
1534                                                 near_call = FALSE;
1535                                 }
1536                         }
1537                 }
1538                 else {
1539                         if (mono_find_class_init_trampoline_by_addr (data))
1540                                 near_call = TRUE;
1541                         else {
1542                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1543                                 if (info) {
1544                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1545                                                 strstr (cfg->method->name, info->name)) {
1546                                                 /* A call to the wrapped function */
1547                                                 if ((((guint64)data) >> 32) == 0)
1548                                                         near_call = TRUE;
1549                                         }
1550                                         else if (info->func == info->wrapper) {
1551                                                 /* No wrapper */
1552                                                 if ((((guint64)info->func) >> 32) == 0)
1553                                                         near_call = TRUE;
1554                                         }
1555                                         else {
1556                                                 /* See the comment in mono_codegen () */
1557                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1558                                                         near_call = TRUE;
1559                                         }
1560                                 }
1561                                 else if ((((guint64)data) >> 32) == 0)
1562                                         near_call = TRUE;
1563                         }
1564                 }
1565
1566                 if (cfg->method->dynamic)
1567                         /* These methods are allocated using malloc */
1568                         near_call = FALSE;
1569
1570                 if (cfg->compile_aot)
1571                         near_call = TRUE;
1572
1573 #ifdef MONO_ARCH_NOMAP32BIT
1574                 near_call = FALSE;
1575 #endif
1576
1577                 if (near_call) {
1578                         amd64_call_code (code, 0);
1579                 }
1580                 else {
1581                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1582                         amd64_call_reg (code, GP_SCRATCH_REG);
1583                 }
1584         }
1585
1586         return code;
1587 }
1588
1589 static inline guint8*
1590 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1591 {
1592         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1593
1594         return emit_call_body (cfg, code, patch_type, data);
1595 }
1596
1597 static inline int
1598 store_membase_imm_to_store_membase_reg (int opcode)
1599 {
1600         switch (opcode) {
1601         case OP_STORE_MEMBASE_IMM:
1602                 return OP_STORE_MEMBASE_REG;
1603         case OP_STOREI4_MEMBASE_IMM:
1604                 return OP_STOREI4_MEMBASE_REG;
1605         case OP_STOREI8_MEMBASE_IMM:
1606                 return OP_STOREI8_MEMBASE_REG;
1607         }
1608
1609         return -1;
1610 }
1611
1612 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
1613
1614 /*
1615  * mono_arch_peephole_pass_1:
1616  *
1617  *   Perform peephole opts which should/can be performed before local regalloc
1618  */
1619 void
1620 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1621 {
1622         MonoInst *ins, *n;
1623
1624         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1625                 MonoInst *last_ins = mono_inst_list_prev (&ins->node, &bb->ins_list);
1626
1627                 switch (ins->opcode) {
1628                 case OP_ADD_IMM:
1629                 case OP_IADD_IMM:
1630                 case OP_LADD_IMM:
1631                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
1632                                 /*
1633                                  * X86_LEA is like ADD, but doesn't have the
1634                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
1635                                  * its operand to 64 bit.
1636                                  */
1637                                 ins->opcode = OP_X86_LEA_MEMBASE;
1638                                 ins->inst_basereg = ins->sreg1;
1639                         }
1640                         break;
1641                 case OP_LXOR:
1642                 case OP_IXOR:
1643                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1644                                 MonoInst *ins2;
1645
1646                                 /*
1647                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1648                                  * the latter has length 2-3 instead of 6 (reverse constant
1649                                  * propagation). These instruction sequences are very common
1650                                  * in the initlocals bblock.
1651                                  */
1652                                 for (ins2 = mono_inst_list_next (&ins->node, &bb->ins_list); ins2;
1653                                                 ins2 = mono_inst_list_next (&ins2->node, &bb->ins_list)) {
1654                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1655                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1656                                                 ins2->sreg1 = ins->dreg;
1657                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1658                                                 /* Continue */
1659                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1660                                                 NULLIFY_INS (ins2);
1661                                                 /* Continue */
1662                                         } else {
1663                                                 break;
1664                                         }
1665                                 }
1666                         }
1667                         break;
1668                 case OP_COMPARE_IMM:
1669                 case OP_LCOMPARE_IMM:
1670                         /* OP_COMPARE_IMM (reg, 0)
1671                          * -->
1672                          * OP_AMD64_TEST_NULL (reg)
1673                          */
1674                         if (!ins->inst_imm)
1675                                 ins->opcode = OP_AMD64_TEST_NULL;
1676                         break;
1677                 case OP_ICOMPARE_IMM:
1678                         if (!ins->inst_imm)
1679                                 ins->opcode = OP_X86_TEST_NULL;
1680                         break;
1681                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1682                         /*
1683                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1684                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1685                          * -->
1686                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1687                          * OP_COMPARE_IMM reg, imm
1688                          *
1689                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1690                          */
1691                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1692                             ins->inst_basereg == last_ins->inst_destbasereg &&
1693                             ins->inst_offset == last_ins->inst_offset) {
1694                                         ins->opcode = OP_ICOMPARE_IMM;
1695                                         ins->sreg1 = last_ins->sreg1;
1696
1697                                         /* check if we can remove cmp reg,0 with test null */
1698                                         if (!ins->inst_imm)
1699                                                 ins->opcode = OP_X86_TEST_NULL;
1700                                 }
1701
1702                         break;
1703                 }
1704
1705                 mono_peephole_ins (bb, ins);
1706         }
1707 }
1708
1709 void
1710 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1711 {
1712         MonoInst *ins, *n;
1713
1714         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1715                 switch (ins->opcode) {
1716                 case OP_ICONST:
1717                 case OP_I8CONST: {
1718                         MonoInst *next;
1719
1720                         /* reg = 0 -> XOR (reg, reg) */
1721                         /* XOR sets cflags on x86, so we cant do it always */
1722                         next = mono_inst_list_next (&ins->node, &bb->ins_list);
1723                         if (ins->inst_c0 == 0 && (!next ||
1724                                         (next && INST_IGNORES_CFLAGS (next->opcode)))) {
1725                                 ins->opcode = OP_LXOR;
1726                                 ins->sreg1 = ins->dreg;
1727                                 ins->sreg2 = ins->dreg;
1728                                 /* Fall through */
1729                         } else {
1730                                 break;
1731                         }
1732                 }
1733                 case OP_LXOR:
1734                         /*
1735                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
1736                          * 0 result into 64 bits.
1737                          */
1738                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1739                                 ins->opcode = OP_IXOR;
1740                         }
1741                         /* Fall through */
1742                 case OP_IXOR:
1743                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1744                                 MonoInst *ins2;
1745
1746                                 /*
1747                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1748                                  * the latter has length 2-3 instead of 6 (reverse constant
1749                                  * propagation). These instruction sequences are very common
1750                                  * in the initlocals bblock.
1751                                  */
1752                                 for (ins2 = mono_inst_list_next (&ins->node, &bb->ins_list); ins2;
1753                                                 ins2 = mono_inst_list_next (&ins2->node, &bb->ins_list)) {
1754                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1755                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1756                                                 ins2->sreg1 = ins->dreg;
1757                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1758                                                 /* Continue */
1759                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1760                                                 NULLIFY_INS (ins2);
1761                                                 /* Continue */
1762                                         } else {
1763                                                 break;
1764                                         }
1765                                 }
1766                         }
1767                         break;
1768                 case OP_IADD_IMM:
1769                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1770                                 ins->opcode = OP_X86_INC_REG;
1771                         break;
1772                 case OP_ISUB_IMM:
1773                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1774                                 ins->opcode = OP_X86_DEC_REG;
1775                         break;
1776                 }
1777
1778                 mono_peephole_ins (bb, ins);
1779         }
1780 }
1781
1782 #define NEW_INS(cfg,ins,dest,op) do {   \
1783                 MONO_INST_NEW ((cfg), (dest), (op)); \
1784                 MONO_INST_LIST_ADD_TAIL (&(dest)->node, &(ins)->node); \
1785         } while (0)
1786
1787 /*
1788  * mono_arch_lowering_pass:
1789  *
1790  *  Converts complex opcodes into simpler ones so that each IR instruction
1791  * corresponds to one machine instruction.
1792  */
1793 void
1794 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1795 {
1796         MonoInst *ins, *n, *temp;
1797
1798         if (bb->max_vreg > cfg->rs->next_vreg)
1799                 cfg->rs->next_vreg = bb->max_vreg;
1800
1801         /*
1802          * FIXME: Need to add more instructions, but the current machine
1803          * description can't model some parts of the composite instructions like
1804          * cdq.
1805          */
1806         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1807                 switch (ins->opcode) {
1808                 case OP_DIV_IMM:
1809                 case OP_REM_IMM:
1810                 case OP_IDIV_IMM:
1811                 case OP_IREM_IMM:
1812                 case OP_IDIV_UN_IMM:
1813                 case OP_IREM_UN_IMM:
1814                         mono_decompose_op_imm (cfg, ins);
1815                         break;
1816                 case OP_COMPARE_IMM:
1817                 case OP_LCOMPARE_IMM:
1818                         if (!amd64_is_imm32 (ins->inst_imm)) {
1819                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
1820                                 temp->inst_c0 = ins->inst_imm;
1821                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1822                                 ins->opcode = OP_COMPARE;
1823                                 ins->sreg2 = temp->dreg;
1824                         }
1825                         break;
1826                 case OP_LOAD_MEMBASE:
1827                 case OP_LOADI8_MEMBASE:
1828                         if (!amd64_is_imm32 (ins->inst_offset)) {
1829                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
1830                                 temp->inst_c0 = ins->inst_offset;
1831                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1832                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1833                                 ins->inst_indexreg = temp->dreg;
1834                         }
1835                         break;
1836                 case OP_STORE_MEMBASE_IMM:
1837                 case OP_STOREI8_MEMBASE_IMM:
1838                         if (!amd64_is_imm32 (ins->inst_imm)) {
1839                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
1840                                 temp->inst_c0 = ins->inst_imm;
1841                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1842                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1843                                 ins->sreg1 = temp->dreg;
1844                         }
1845                         break;
1846                 default:
1847                         break;
1848                 }
1849         }
1850
1851         bb->max_vreg = cfg->rs->next_vreg;
1852 }
1853
1854 static const int
1855 branch_cc_table [] = {
1856         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1857         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1858         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1859 };
1860
1861 /* Maps CMP_... constants to X86_CC_... constants */
1862 static const int
1863 cc_table [] = {
1864         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1865         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1866 };
1867
1868 static const int
1869 cc_signed_table [] = {
1870         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1871         FALSE, FALSE, FALSE, FALSE
1872 };
1873
1874 /*#include "cprop.c"*/
1875
1876 static unsigned char*
1877 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1878 {
1879         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
1880
1881         if (size == 1)
1882                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
1883         else if (size == 2)
1884                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
1885         return code;
1886 }
1887
1888 static unsigned char*
1889 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1890 {
1891         int sreg = tree->sreg1;
1892         int need_touch = FALSE;
1893
1894 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1895         if (!tree->flags & MONO_INST_INIT)
1896                 need_touch = TRUE;
1897 #endif
1898
1899         if (need_touch) {
1900                 guint8* br[5];
1901
1902                 /*
1903                  * Under Windows:
1904                  * If requested stack size is larger than one page,
1905                  * perform stack-touch operation
1906                  */
1907                 /*
1908                  * Generate stack probe code.
1909                  * Under Windows, it is necessary to allocate one page at a time,
1910                  * "touching" stack after each successful sub-allocation. This is
1911                  * because of the way stack growth is implemented - there is a
1912                  * guard page before the lowest stack page that is currently commited.
1913                  * Stack normally grows sequentially so OS traps access to the
1914                  * guard page and commits more pages when needed.
1915                  */
1916                 amd64_test_reg_imm (code, sreg, ~0xFFF);
1917                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1918
1919                 br[2] = code; /* loop */
1920                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
1921                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
1922                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
1923                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
1924                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
1925                 amd64_patch (br[3], br[2]);
1926                 amd64_test_reg_reg (code, sreg, sreg);
1927                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
1928                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
1929
1930                 br[1] = code; x86_jump8 (code, 0);
1931
1932                 amd64_patch (br[0], code);
1933                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
1934                 amd64_patch (br[1], code);
1935                 amd64_patch (br[4], code);
1936         }
1937         else
1938                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
1939
1940         if (tree->flags & MONO_INST_INIT) {
1941                 int offset = 0;
1942                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
1943                         amd64_push_reg (code, AMD64_RAX);
1944                         offset += 8;
1945                 }
1946                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
1947                         amd64_push_reg (code, AMD64_RCX);
1948                         offset += 8;
1949                 }
1950                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
1951                         amd64_push_reg (code, AMD64_RDI);
1952                         offset += 8;
1953                 }
1954
1955                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
1956                 if (sreg != AMD64_RCX)
1957                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
1958                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
1959
1960                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
1961                 amd64_cld (code);
1962                 amd64_prefix (code, X86_REP_PREFIX);
1963                 amd64_stosl (code);
1964
1965                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
1966                         amd64_pop_reg (code, AMD64_RDI);
1967                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
1968                         amd64_pop_reg (code, AMD64_RCX);
1969                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
1970                         amd64_pop_reg (code, AMD64_RAX);
1971         }
1972         return code;
1973 }
1974
1975 static guint8*
1976 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
1977 {
1978         CallInfo *cinfo;
1979         guint32 quad;
1980
1981         /* Move return value to the target register */
1982         /* FIXME: do this in the local reg allocator */
1983         switch (ins->opcode) {
1984         case OP_CALL:
1985         case OP_CALL_REG:
1986         case OP_CALL_MEMBASE:
1987         case OP_LCALL:
1988         case OP_LCALL_REG:
1989         case OP_LCALL_MEMBASE:
1990                 g_assert (ins->dreg == AMD64_RAX);
1991                 break;
1992         case OP_FCALL:
1993         case OP_FCALL_REG:
1994         case OP_FCALL_MEMBASE:
1995                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
1996                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
1997                 }
1998                 else {
1999                         if (ins->dreg != AMD64_XMM0)
2000                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2001                 }
2002                 break;
2003         case OP_VCALL:
2004         case OP_VCALL_REG:
2005         case OP_VCALL_MEMBASE:
2006                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2007                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2008                         /* Pop the destination address from the stack */
2009                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2010                         amd64_pop_reg (code, AMD64_RCX);
2011
2012                         for (quad = 0; quad < 2; quad ++) {
2013                                 switch (cinfo->ret.pair_storage [quad]) {
2014                                 case ArgInIReg:
2015                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2016                                         break;
2017                                 case ArgInFloatSSEReg:
2018                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2019                                         break;
2020                                 case ArgInDoubleSSEReg:
2021                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2022                                         break;
2023                                 case ArgNone:
2024                                         break;
2025                                 default:
2026                                         NOT_IMPLEMENTED;
2027                                 }
2028                         }
2029                 }
2030                 break;
2031         }
2032
2033         return code;
2034 }
2035
2036 /*
2037  * emit_tls_get:
2038  * @code: buffer to store code to
2039  * @dreg: hard register where to place the result
2040  * @tls_offset: offset info
2041  *
2042  * emit_tls_get emits in @code the native code that puts in the dreg register
2043  * the item in the thread local storage identified by tls_offset.
2044  *
2045  * Returns: a pointer to the end of the stored code
2046  */
2047 static guint8*
2048 emit_tls_get (guint8* code, int dreg, int tls_offset)
2049 {
2050         if (optimize_for_xen) {
2051                 x86_prefix (code, X86_FS_PREFIX);
2052                 amd64_mov_reg_mem (code, dreg, 0, 8);
2053                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2054         } else {
2055                 x86_prefix (code, X86_FS_PREFIX);
2056                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2057         }
2058         return code;
2059 }
2060
2061 /*
2062  * emit_load_volatile_arguments:
2063  *
2064  *  Load volatile arguments from the stack to the original input registers.
2065  * Required before a tail call.
2066  */
2067 static guint8*
2068 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2069 {
2070         MonoMethod *method = cfg->method;
2071         MonoMethodSignature *sig;
2072         MonoInst *ins;
2073         CallInfo *cinfo;
2074         guint32 i, quad;
2075
2076         /* FIXME: Generate intermediate code instead */
2077
2078         sig = mono_method_signature (method);
2079
2080         cinfo = cfg->arch.cinfo;
2081
2082         /* This is the opposite of the code in emit_prolog */
2083         if (sig->ret->type != MONO_TYPE_VOID) {
2084                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2085                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2086         }
2087
2088         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2089                 ArgInfo *ainfo = cinfo->args + i;
2090                 MonoType *arg_type;
2091                 ins = cfg->args [i];
2092
2093                 if (sig->hasthis && (i == 0))
2094                         arg_type = &mono_defaults.object_class->byval_arg;
2095                 else
2096                         arg_type = sig->params [i - sig->hasthis];
2097
2098                 if (ins->opcode != OP_REGVAR) {
2099                         switch (ainfo->storage) {
2100                         case ArgInIReg: {
2101                                 guint32 size = 8;
2102
2103                                 /* FIXME: I1 etc */
2104                                 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2105                                 break;
2106                         }
2107                         case ArgInFloatSSEReg:
2108                                 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2109                                 break;
2110                         case ArgInDoubleSSEReg:
2111                                 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2112                                 break;
2113                         case ArgValuetypeInReg:
2114                                 for (quad = 0; quad < 2; quad ++) {
2115                                         switch (ainfo->pair_storage [quad]) {
2116                                         case ArgInIReg:
2117                                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2118                                                 break;
2119                                         case ArgInFloatSSEReg:
2120                                         case ArgInDoubleSSEReg:
2121                                                 g_assert_not_reached ();
2122                                                 break;
2123                                         case ArgNone:
2124                                                 break;
2125                                         default:
2126                                                 g_assert_not_reached ();
2127                                         }
2128                                 }
2129                                 break;
2130                         default:
2131                                 break;
2132                         }
2133                 }
2134                 else {
2135                         g_assert (ainfo->storage == ArgInIReg);
2136
2137                         amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2138                 }
2139         }
2140
2141         return code;
2142 }
2143
2144 #define REAL_PRINT_REG(text,reg) \
2145 mono_assert (reg >= 0); \
2146 amd64_push_reg (code, AMD64_RAX); \
2147 amd64_push_reg (code, AMD64_RDX); \
2148 amd64_push_reg (code, AMD64_RCX); \
2149 amd64_push_reg (code, reg); \
2150 amd64_push_imm (code, reg); \
2151 amd64_push_imm (code, text " %d %p\n"); \
2152 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2153 amd64_call_reg (code, AMD64_RAX); \
2154 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2155 amd64_pop_reg (code, AMD64_RCX); \
2156 amd64_pop_reg (code, AMD64_RDX); \
2157 amd64_pop_reg (code, AMD64_RAX);
2158
2159 /* benchmark and set based on cpu */
2160 #define LOOP_ALIGNMENT 8
2161 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2162
2163 void
2164 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2165 {
2166         MonoInst *ins;
2167         MonoCallInst *call;
2168         guint offset;
2169         guint8 *code = cfg->native_code + cfg->code_len;
2170         guint last_offset = 0;
2171         int max_len, cpos;
2172
2173         if (cfg->opt & MONO_OPT_LOOP) {
2174                 int pad, align = LOOP_ALIGNMENT;
2175                 /* set alignment depending on cpu */
2176                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2177                         pad = align - pad;
2178                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2179                         amd64_padding (code, pad);
2180                         cfg->code_len += pad;
2181                         bb->native_offset = cfg->code_len;
2182                 }
2183         }
2184
2185         if (cfg->verbose_level > 2)
2186                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2187
2188         cpos = bb->max_offset;
2189
2190         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2191                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2192                 g_assert (!cfg->compile_aot);
2193                 cpos += 6;
2194
2195                 cov->data [bb->dfn].cil_code = bb->cil_code;
2196                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2197                 /* this is not thread save, but good enough */
2198                 amd64_inc_membase (code, AMD64_R11, 0);
2199         }
2200
2201         offset = code - cfg->native_code;
2202
2203         mono_debug_open_block (cfg, bb, offset);
2204
2205         MONO_BB_FOR_EACH_INS (bb, ins) {
2206                 offset = code - cfg->native_code;
2207
2208                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2209
2210                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2211                         cfg->code_size *= 2;
2212                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2213                         code = cfg->native_code + offset;
2214                         mono_jit_stats.code_reallocs++;
2215                 }
2216
2217                 if (cfg->debug_info)
2218                         mono_debug_record_line_number (cfg, ins, offset);
2219
2220                 switch (ins->opcode) {
2221                 case OP_BIGMUL:
2222                         amd64_mul_reg (code, ins->sreg2, TRUE);
2223                         break;
2224                 case OP_BIGMUL_UN:
2225                         amd64_mul_reg (code, ins->sreg2, FALSE);
2226                         break;
2227                 case OP_X86_SETEQ_MEMBASE:
2228                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2229                         break;
2230                 case OP_STOREI1_MEMBASE_IMM:
2231                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2232                         break;
2233                 case OP_STOREI2_MEMBASE_IMM:
2234                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2235                         break;
2236                 case OP_STOREI4_MEMBASE_IMM:
2237                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2238                         break;
2239                 case OP_STOREI1_MEMBASE_REG:
2240                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2241                         break;
2242                 case OP_STOREI2_MEMBASE_REG:
2243                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2244                         break;
2245                 case OP_STORE_MEMBASE_REG:
2246                 case OP_STOREI8_MEMBASE_REG:
2247                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2248                         break;
2249                 case OP_STOREI4_MEMBASE_REG:
2250                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2251                         break;
2252                 case OP_STORE_MEMBASE_IMM:
2253                 case OP_STOREI8_MEMBASE_IMM:
2254                         g_assert (amd64_is_imm32 (ins->inst_imm));
2255                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2256                         break;
2257                 case OP_LOAD_MEM:
2258                 case OP_LOADI8_MEM:
2259                         // FIXME: Decompose this earlier
2260                         if (amd64_is_imm32 (ins->inst_imm))
2261                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2262                         else {
2263                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2264                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2265                         }
2266                         break;
2267                 case OP_LOADI4_MEM:
2268                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2269                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2270                         break;
2271                 case OP_LOADU4_MEM:
2272                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2273                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2274                         break;
2275                 case OP_LOADU1_MEM:
2276                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2277                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2278                         break;
2279                 case OP_LOADU2_MEM:
2280                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2281                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2282                         break;
2283                 case OP_LOAD_MEMBASE:
2284                 case OP_LOADI8_MEMBASE:
2285                         g_assert (amd64_is_imm32 (ins->inst_offset));
2286                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2287                         break;
2288                 case OP_LOADI4_MEMBASE:
2289                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2290                         break;
2291                 case OP_LOADU4_MEMBASE:
2292                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2293                         break;
2294                 case OP_LOADU1_MEMBASE:
2295                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2296                         break;
2297                 case OP_LOADI1_MEMBASE:
2298                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2299                         break;
2300                 case OP_LOADU2_MEMBASE:
2301                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2302                         break;
2303                 case OP_LOADI2_MEMBASE:
2304                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2305                         break;
2306                 case OP_AMD64_LOADI8_MEMINDEX:
2307                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2308                         break;
2309                 case OP_LCONV_TO_I1:
2310                 case OP_ICONV_TO_I1:
2311                 case OP_SEXT_I1:
2312                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2313                         break;
2314                 case OP_LCONV_TO_I2:
2315                 case OP_ICONV_TO_I2:
2316                 case OP_SEXT_I2:
2317                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2318                         break;
2319                 case OP_LCONV_TO_U1:
2320                 case OP_ICONV_TO_U1:
2321                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2322                         break;
2323                 case OP_LCONV_TO_U2:
2324                 case OP_ICONV_TO_U2:
2325                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2326                         break;
2327                 case OP_ZEXT_I4:
2328                         /* Clean out the upper word */
2329                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2330                         break;
2331                 case OP_SEXT_I4:
2332                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2333                         break;
2334                 case OP_COMPARE:
2335                 case OP_LCOMPARE:
2336                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2337                         break;
2338                 case OP_COMPARE_IMM:
2339                 case OP_LCOMPARE_IMM:
2340                         g_assert (amd64_is_imm32 (ins->inst_imm));
2341                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2342                         break;
2343                 case OP_X86_COMPARE_REG_MEMBASE:
2344                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2345                         break;
2346                 case OP_X86_TEST_NULL:
2347                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2348                         break;
2349                 case OP_AMD64_TEST_NULL:
2350                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2351                         break;
2352
2353                 case OP_X86_ADD_REG_MEMBASE:
2354                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2355                         break;
2356                 case OP_X86_SUB_REG_MEMBASE:
2357                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2358                         break;
2359                 case OP_X86_AND_REG_MEMBASE:
2360                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2361                         break;
2362                 case OP_X86_OR_REG_MEMBASE:
2363                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2364                         break;
2365                 case OP_X86_XOR_REG_MEMBASE:
2366                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2367                         break;
2368
2369                 case OP_X86_ADD_MEMBASE_IMM:
2370                         /* FIXME: Make a 64 version too */
2371                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2372                         break;
2373                 case OP_X86_SUB_MEMBASE_IMM:
2374                         g_assert (amd64_is_imm32 (ins->inst_imm));
2375                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2376                         break;
2377                 case OP_X86_AND_MEMBASE_IMM:
2378                         g_assert (amd64_is_imm32 (ins->inst_imm));
2379                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2380                         break;
2381                 case OP_X86_OR_MEMBASE_IMM:
2382                         g_assert (amd64_is_imm32 (ins->inst_imm));
2383                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2384                         break;
2385                 case OP_X86_XOR_MEMBASE_IMM:
2386                         g_assert (amd64_is_imm32 (ins->inst_imm));
2387                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2388                         break;
2389                 case OP_X86_ADD_MEMBASE_REG:
2390                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2391                         break;
2392                 case OP_X86_SUB_MEMBASE_REG:
2393                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2394                         break;
2395                 case OP_X86_AND_MEMBASE_REG:
2396                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2397                         break;
2398                 case OP_X86_OR_MEMBASE_REG:
2399                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2400                         break;
2401                 case OP_X86_XOR_MEMBASE_REG:
2402                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2403                         break;
2404                 case OP_X86_INC_MEMBASE:
2405                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2406                         break;
2407                 case OP_X86_INC_REG:
2408                         amd64_inc_reg_size (code, ins->dreg, 4);
2409                         break;
2410                 case OP_X86_DEC_MEMBASE:
2411                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2412                         break;
2413                 case OP_X86_DEC_REG:
2414                         amd64_dec_reg_size (code, ins->dreg, 4);
2415                         break;
2416                 case OP_X86_MUL_REG_MEMBASE:
2417                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2418                         break;
2419                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2420                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2421                         break;
2422                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2423                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2424                         break;
2425                 case OP_AMD64_COMPARE_MEMBASE_REG:
2426                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2427                         break;
2428                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2429                         g_assert (amd64_is_imm32 (ins->inst_imm));
2430                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2431                         break;
2432                 case OP_X86_COMPARE_MEMBASE8_IMM:
2433                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2434                         break;
2435                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2436                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2437                         break;
2438                 case OP_AMD64_COMPARE_REG_MEMBASE:
2439                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2440                         break;
2441
2442                 case OP_AMD64_ADD_REG_MEMBASE:
2443                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2444                         break;
2445                 case OP_AMD64_SUB_REG_MEMBASE:
2446                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2447                         break;
2448                 case OP_AMD64_AND_REG_MEMBASE:
2449                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2450                         break;
2451                 case OP_AMD64_OR_REG_MEMBASE:
2452                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2453                         break;
2454                 case OP_AMD64_XOR_REG_MEMBASE:
2455                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2456                         break;
2457
2458                 case OP_AMD64_ADD_MEMBASE_REG:
2459                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2460                         break;
2461                 case OP_AMD64_SUB_MEMBASE_REG:
2462                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2463                         break;
2464                 case OP_AMD64_AND_MEMBASE_REG:
2465                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2466                         break;
2467                 case OP_AMD64_OR_MEMBASE_REG:
2468                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2469                         break;
2470                 case OP_AMD64_XOR_MEMBASE_REG:
2471                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2472                         break;
2473
2474                 case OP_AMD64_ADD_MEMBASE_IMM:
2475                         g_assert (amd64_is_imm32 (ins->inst_imm));
2476                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2477                         break;
2478                 case OP_AMD64_SUB_MEMBASE_IMM:
2479                         g_assert (amd64_is_imm32 (ins->inst_imm));
2480                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2481                         break;
2482                 case OP_AMD64_AND_MEMBASE_IMM:
2483                         g_assert (amd64_is_imm32 (ins->inst_imm));
2484                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2485                         break;
2486                 case OP_AMD64_OR_MEMBASE_IMM:
2487                         g_assert (amd64_is_imm32 (ins->inst_imm));
2488                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2489                         break;
2490                 case OP_AMD64_XOR_MEMBASE_IMM:
2491                         g_assert (amd64_is_imm32 (ins->inst_imm));
2492                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2493                         break;
2494
2495                 case OP_BREAK:
2496                         amd64_breakpoint (code);
2497                         break;
2498                 case OP_NOP:
2499                 case OP_DUMMY_USE:
2500                 case OP_DUMMY_STORE:
2501                 case OP_NOT_REACHED:
2502                 case OP_NOT_NULL:
2503                         break;
2504                 case OP_ADDCC:
2505                 case OP_LADD:
2506                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2507                         break;
2508                 case OP_ADC:
2509                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2510                         break;
2511                 case OP_ADD_IMM:
2512                 case OP_LADD_IMM:
2513                         g_assert (amd64_is_imm32 (ins->inst_imm));
2514                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2515                         break;
2516                 case OP_ADC_IMM:
2517                         g_assert (amd64_is_imm32 (ins->inst_imm));
2518                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2519                         break;
2520                 case OP_SUBCC:
2521                 case OP_LSUB:
2522                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2523                         break;
2524                 case OP_SBB:
2525                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2526                         break;
2527                 case OP_SUB_IMM:
2528                 case OP_LSUB_IMM:
2529                         g_assert (amd64_is_imm32 (ins->inst_imm));
2530                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2531                         break;
2532                 case OP_SBB_IMM:
2533                         g_assert (amd64_is_imm32 (ins->inst_imm));
2534                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2535                         break;
2536                 case OP_LAND:
2537                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2538                         break;
2539                 case OP_AND_IMM:
2540                 case OP_LAND_IMM:
2541                         g_assert (amd64_is_imm32 (ins->inst_imm));
2542                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2543                         break;
2544                 case OP_LMUL:
2545                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2546                         break;
2547                 case OP_MUL_IMM:
2548                 case OP_LMUL_IMM:
2549                 case OP_IMUL_IMM: {
2550                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2551
2552                         switch (ins->inst_imm) {
2553                         case 2:
2554                                 /* MOV r1, r2 */
2555                                 /* ADD r1, r1 */
2556                                 if (ins->dreg != ins->sreg1)
2557                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2558                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2559                                 break;
2560                         case 3:
2561                                 /* LEA r1, [r2 + r2*2] */
2562                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2563                                 break;
2564                         case 5:
2565                                 /* LEA r1, [r2 + r2*4] */
2566                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2567                                 break;
2568                         case 6:
2569                                 /* LEA r1, [r2 + r2*2] */
2570                                 /* ADD r1, r1          */
2571                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2572                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2573                                 break;
2574                         case 9:
2575                                 /* LEA r1, [r2 + r2*8] */
2576                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2577                                 break;
2578                         case 10:
2579                                 /* LEA r1, [r2 + r2*4] */
2580                                 /* ADD r1, r1          */
2581                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2582                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2583                                 break;
2584                         case 12:
2585                                 /* LEA r1, [r2 + r2*2] */
2586                                 /* SHL r1, 2           */
2587                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2588                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2589                                 break;
2590                         case 25:
2591                                 /* LEA r1, [r2 + r2*4] */
2592                                 /* LEA r1, [r1 + r1*4] */
2593                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2594                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2595                                 break;
2596                         case 100:
2597                                 /* LEA r1, [r2 + r2*4] */
2598                                 /* SHL r1, 2           */
2599                                 /* LEA r1, [r1 + r1*4] */
2600                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2601                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2602                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2603                                 break;
2604                         default:
2605                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2606                                 break;
2607                         }
2608                         break;
2609                 }
2610                 case OP_LDIV:
2611                 case OP_LREM:
2612                         /* Regalloc magic makes the div/rem cases the same */
2613                         if (ins->sreg2 == AMD64_RDX) {
2614                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2615                                 amd64_cdq (code);
2616                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
2617                         } else {
2618                                 amd64_cdq (code);
2619                                 amd64_div_reg (code, ins->sreg2, TRUE);
2620                         }
2621                         break;
2622                 case OP_LDIV_UN:
2623                 case OP_LREM_UN:
2624                         if (ins->sreg2 == AMD64_RDX) {
2625                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2626                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2627                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
2628                         } else {
2629                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2630                                 amd64_div_reg (code, ins->sreg2, FALSE);
2631                         }
2632                         break;
2633                 case OP_IDIV:
2634                 case OP_IREM:
2635                         if (ins->sreg2 == AMD64_RDX) {
2636                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2637                                 amd64_cdq_size (code, 4);
2638                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
2639                         } else {
2640                                 amd64_cdq_size (code, 4);
2641                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2642                         }
2643                         break;
2644                 case OP_IDIV_UN:
2645                 case OP_IREM_UN:
2646                         if (ins->sreg2 == AMD64_RDX) {
2647                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2648                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2649                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
2650                         } else {
2651                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2652                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2653                         }
2654                         break;
2655                 case OP_LMUL_OVF:
2656                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2657                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2658                         break;
2659                 case OP_LOR:
2660                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2661                         break;
2662                 case OP_OR_IMM:
2663                 case OP_LOR_IMM:
2664                         g_assert (amd64_is_imm32 (ins->inst_imm));
2665                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2666                         break;
2667                 case OP_LXOR:
2668                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2669                         break;
2670                 case OP_XOR_IMM:
2671                 case OP_LXOR_IMM:
2672                         g_assert (amd64_is_imm32 (ins->inst_imm));
2673                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2674                         break;
2675                 case OP_LSHL:
2676                         g_assert (ins->sreg2 == AMD64_RCX);
2677                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2678                         break;
2679                 case OP_LSHR:
2680                         g_assert (ins->sreg2 == AMD64_RCX);
2681                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2682                         break;
2683                 case OP_SHR_IMM:
2684                         g_assert (amd64_is_imm32 (ins->inst_imm));
2685                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2686                         break;
2687                 case OP_LSHR_IMM:
2688                         g_assert (amd64_is_imm32 (ins->inst_imm));
2689                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2690                         break;
2691                 case OP_SHR_UN_IMM:
2692                         g_assert (amd64_is_imm32 (ins->inst_imm));
2693                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2694                         break;
2695                 case OP_LSHR_UN_IMM:
2696                         g_assert (amd64_is_imm32 (ins->inst_imm));
2697                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2698                         break;
2699                 case OP_LSHR_UN:
2700                         g_assert (ins->sreg2 == AMD64_RCX);
2701                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2702                         break;
2703                 case OP_SHL_IMM:
2704                         g_assert (amd64_is_imm32 (ins->inst_imm));
2705                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2706                         break;
2707                 case OP_LSHL_IMM:
2708                         g_assert (amd64_is_imm32 (ins->inst_imm));
2709                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2710                         break;
2711
2712                 case OP_IADDCC:
2713                 case OP_IADD:
2714                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2715                         break;
2716                 case OP_IADC:
2717                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2718                         break;
2719                 case OP_IADD_IMM:
2720                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2721                         break;
2722                 case OP_IADC_IMM:
2723                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2724                         break;
2725                 case OP_ISUBCC:
2726                 case OP_ISUB:
2727                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2728                         break;
2729                 case OP_ISBB:
2730                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2731                         break;
2732                 case OP_ISUB_IMM:
2733                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2734                         break;
2735                 case OP_ISBB_IMM:
2736                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2737                         break;
2738                 case OP_IAND:
2739                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2740                         break;
2741                 case OP_IAND_IMM:
2742                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2743                         break;
2744                 case OP_IOR:
2745                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2746                         break;
2747                 case OP_IOR_IMM:
2748                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2749                         break;
2750                 case OP_IXOR:
2751                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2752                         break;
2753                 case OP_IXOR_IMM:
2754                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2755                         break;
2756                 case OP_INEG:
2757                         amd64_neg_reg_size (code, ins->sreg1, 4);
2758                         break;
2759                 case OP_INOT:
2760                         amd64_not_reg_size (code, ins->sreg1, 4);
2761                         break;
2762                 case OP_ISHL:
2763                         g_assert (ins->sreg2 == AMD64_RCX);
2764                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2765                         break;
2766                 case OP_ISHR:
2767                         g_assert (ins->sreg2 == AMD64_RCX);
2768                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2769                         break;
2770                 case OP_ISHR_IMM:
2771                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2772                         break;
2773                 case OP_ISHR_UN_IMM:
2774                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2775                         break;
2776                 case OP_ISHR_UN:
2777                         g_assert (ins->sreg2 == AMD64_RCX);
2778                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2779                         break;
2780                 case OP_ISHL_IMM:
2781                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2782                         break;
2783                 case OP_IMUL:
2784                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2785                         break;
2786                 case OP_IMUL_OVF:
2787                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2788                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2789                         break;
2790                 case OP_IMUL_OVF_UN:
2791                 case OP_LMUL_OVF_UN: {
2792                         /* the mul operation and the exception check should most likely be split */
2793                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2794                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2795                         /*g_assert (ins->sreg2 == X86_EAX);
2796                         g_assert (ins->dreg == X86_EAX);*/
2797                         if (ins->sreg2 == X86_EAX) {
2798                                 non_eax_reg = ins->sreg1;
2799                         } else if (ins->sreg1 == X86_EAX) {
2800                                 non_eax_reg = ins->sreg2;
2801                         } else {
2802                                 /* no need to save since we're going to store to it anyway */
2803                                 if (ins->dreg != X86_EAX) {
2804                                         saved_eax = TRUE;
2805                                         amd64_push_reg (code, X86_EAX);
2806                                 }
2807                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2808                                 non_eax_reg = ins->sreg2;
2809                         }
2810                         if (ins->dreg == X86_EDX) {
2811                                 if (!saved_eax) {
2812                                         saved_eax = TRUE;
2813                                         amd64_push_reg (code, X86_EAX);
2814                                 }
2815                         } else {
2816                                 saved_edx = TRUE;
2817                                 amd64_push_reg (code, X86_EDX);
2818                         }
2819                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2820                         /* save before the check since pop and mov don't change the flags */
2821                         if (ins->dreg != X86_EAX)
2822                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2823                         if (saved_edx)
2824                                 amd64_pop_reg (code, X86_EDX);
2825                         if (saved_eax)
2826                                 amd64_pop_reg (code, X86_EAX);
2827                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2828                         break;
2829                 }
2830                 case OP_ICOMPARE:
2831                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2832                         break;
2833                 case OP_ICOMPARE_IMM:
2834                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2835                         break;
2836                 case OP_IBEQ:
2837                 case OP_IBLT:
2838                 case OP_IBGT:
2839                 case OP_IBGE:
2840                 case OP_IBLE:
2841                 case OP_LBEQ:
2842                 case OP_LBLT:
2843                 case OP_LBGT:
2844                 case OP_LBGE:
2845                 case OP_LBLE:
2846                 case OP_IBNE_UN:
2847                 case OP_IBLT_UN:
2848                 case OP_IBGT_UN:
2849                 case OP_IBGE_UN:
2850                 case OP_IBLE_UN:
2851                 case OP_LBNE_UN:
2852                 case OP_LBLT_UN:
2853                 case OP_LBGT_UN:
2854                 case OP_LBGE_UN:
2855                 case OP_LBLE_UN:
2856                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
2857                         break;
2858
2859                 case OP_LNOT:
2860                         amd64_not_reg (code, ins->sreg1);
2861                         break;
2862                 case OP_LNEG:
2863                         amd64_neg_reg (code, ins->sreg1);
2864                         break;
2865
2866                 case OP_ICONST:
2867                 case OP_I8CONST:
2868                         if ((((guint64)ins->inst_c0) >> 32) == 0)
2869                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2870                         else
2871                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2872                         break;
2873                 case OP_AOTCONST:
2874                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2875                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2876                         break;
2877                 case OP_MOVE:
2878                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2879                         break;
2880                 case OP_AMD64_SET_XMMREG_R4: {
2881                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
2882                         break;
2883                 }
2884                 case OP_AMD64_SET_XMMREG_R8: {
2885                         if (ins->dreg != ins->sreg1)
2886                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
2887                         break;
2888                 }
2889                 case OP_JMP: {
2890                         /*
2891                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2892                          * Keep in sync with the code in emit_epilog.
2893                          */
2894                         int pos = 0, i;
2895
2896                         /* FIXME: no tracing support... */
2897                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2898                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2899
2900                         g_assert (!cfg->method->save_lmf);
2901
2902                         code = emit_load_volatile_arguments (cfg, code);
2903
2904                         if (cfg->arch.omit_fp) {
2905                                 guint32 save_offset = 0;
2906                                 /* Pop callee-saved registers */
2907                                 for (i = 0; i < AMD64_NREG; ++i)
2908                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2909                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
2910                                                 save_offset += 8;
2911                                         }
2912                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
2913                         }
2914                         else {
2915                                 for (i = 0; i < AMD64_NREG; ++i)
2916                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
2917                                                 pos -= sizeof (gpointer);
2918
2919                                 if (pos)
2920                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
2921
2922                                 /* Pop registers in reverse order */
2923                                 for (i = AMD64_NREG - 1; i > 0; --i)
2924                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2925                                                 amd64_pop_reg (code, i);
2926                                         }
2927
2928                                 amd64_leave (code);
2929                         }
2930
2931                         offset = code - cfg->native_code;
2932                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2933                         if (cfg->compile_aot)
2934                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
2935                         else
2936                                 amd64_set_reg_template (code, AMD64_R11);
2937                         amd64_jump_reg (code, AMD64_R11);
2938                         break;
2939                 }
2940                 case OP_CHECK_THIS:
2941                         /* ensure ins->sreg1 is not NULL */
2942                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
2943                         break;
2944                 case OP_ARGLIST: {
2945                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
2946                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
2947                         break;
2948                 }
2949                 case OP_FCALL:
2950                 case OP_LCALL:
2951                 case OP_VCALL:
2952                 case OP_VOIDCALL:
2953                 case OP_CALL:
2954                         call = (MonoCallInst*)ins;
2955                         /*
2956                          * The AMD64 ABI forces callers to know about varargs.
2957                          */
2958                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
2959                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2960                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
2961                                 /*
2962                                  * Since the unmanaged calling convention doesn't contain a
2963                                  * 'vararg' entry, we have to treat every pinvoke call as a
2964                                  * potential vararg call.
2965                                  */
2966                                 guint32 nregs, i;
2967                                 nregs = 0;
2968                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
2969                                         if (call->used_fregs & (1 << i))
2970                                                 nregs ++;
2971                                 if (!nregs)
2972                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2973                                 else
2974                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
2975                         }
2976
2977                         if (ins->flags & MONO_INST_HAS_METHOD)
2978                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2979                         else
2980                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2981                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2982                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2983                         code = emit_move_return_value (cfg, ins, code);
2984                         break;
2985                 case OP_FCALL_REG:
2986                 case OP_LCALL_REG:
2987                 case OP_VCALL_REG:
2988                 case OP_VOIDCALL_REG:
2989                 case OP_CALL_REG:
2990                         call = (MonoCallInst*)ins;
2991
2992                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2993                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
2994                                 ins->sreg1 = AMD64_R11;
2995                         }
2996
2997                         /*
2998                          * The AMD64 ABI forces callers to know about varargs.
2999                          */
3000                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3001                                 if (ins->sreg1 == AMD64_RAX) {
3002                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3003                                         ins->sreg1 = AMD64_R11;
3004                                 }
3005                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3006                         }
3007                         amd64_call_reg (code, ins->sreg1);
3008                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3009                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3010                         code = emit_move_return_value (cfg, ins, code);
3011                         break;
3012                 case OP_FCALL_MEMBASE:
3013                 case OP_LCALL_MEMBASE:
3014                 case OP_VCALL_MEMBASE:
3015                 case OP_VOIDCALL_MEMBASE:
3016                 case OP_CALL_MEMBASE:
3017                         call = (MonoCallInst*)ins;
3018
3019                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3020                                 /*
3021                                  * Can't use R11 because it is clobbered by the trampoline
3022                                  * code, and the reg value is needed by get_vcall_slot_addr.
3023                                  */
3024                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3025                                 ins->sreg1 = AMD64_RAX;
3026                         }
3027
3028                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3029                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3030                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3031                         code = emit_move_return_value (cfg, ins, code);
3032                         break;
3033                 case OP_AMD64_SAVE_SP_TO_LMF:
3034                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3035                         break;
3036                 case OP_OUTARG:
3037                 case OP_X86_PUSH:
3038                         amd64_push_reg (code, ins->sreg1);
3039                         break;
3040                 case OP_X86_PUSH_IMM:
3041                         g_assert (amd64_is_imm32 (ins->inst_imm));
3042                         amd64_push_imm (code, ins->inst_imm);
3043                         break;
3044                 case OP_X86_PUSH_MEMBASE:
3045                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3046                         break;
3047                 case OP_X86_PUSH_OBJ:
3048                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3049                         amd64_push_reg (code, AMD64_RDI);
3050                         amd64_push_reg (code, AMD64_RSI);
3051                         amd64_push_reg (code, AMD64_RCX);
3052                         if (ins->inst_offset)
3053                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3054                         else
3055                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3056                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3057                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3058                         amd64_cld (code);
3059                         amd64_prefix (code, X86_REP_PREFIX);
3060                         amd64_movsd (code);
3061                         amd64_pop_reg (code, AMD64_RCX);
3062                         amd64_pop_reg (code, AMD64_RSI);
3063                         amd64_pop_reg (code, AMD64_RDI);
3064                         break;
3065                 case OP_X86_LEA:
3066                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3067                         break;
3068                 case OP_X86_LEA_MEMBASE:
3069                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3070                         break;
3071                 case OP_X86_XCHG:
3072                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3073                         break;
3074                 case OP_LOCALLOC:
3075                         /* keep alignment */
3076                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3077                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3078                         code = mono_emit_stack_alloc (code, ins);
3079                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3080                         break;
3081                 case OP_LOCALLOC_IMM: {
3082                         guint32 size = ins->inst_imm;
3083                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3084
3085                         if (ins->flags & MONO_INST_INIT) {
3086                                 /* FIXME: Optimize this */
3087                                 amd64_mov_reg_imm (code, ins->dreg, size);
3088                                 ins->sreg1 = ins->dreg;
3089
3090                                 code = mono_emit_stack_alloc (code, ins);
3091                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3092                         } else {
3093                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3094                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3095                         }
3096                         break;
3097                 }
3098                 case OP_THROW: {
3099                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3100                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3101                                              (gpointer)"mono_arch_throw_exception");
3102                         break;
3103                 }
3104                 case OP_RETHROW: {
3105                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3106                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3107                                              (gpointer)"mono_arch_rethrow_exception");
3108                         break;
3109                 }
3110                 case OP_CALL_HANDLER:
3111                         /* Align stack */
3112                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3113                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3114                         amd64_call_imm (code, 0);
3115                         /* Restore stack alignment */
3116                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3117                         break;
3118                 case OP_START_HANDLER: {
3119                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3120                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3121                         break;
3122                 }
3123                 case OP_ENDFINALLY: {
3124                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3125                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3126                         amd64_ret (code);
3127                         break;
3128                 }
3129                 case OP_ENDFILTER: {
3130                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3131                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3132                         /* The local allocator will put the result into RAX */
3133                         amd64_ret (code);
3134                         break;
3135                 }
3136
3137                 case OP_LABEL:
3138                         ins->inst_c0 = code - cfg->native_code;
3139                         break;
3140                 case OP_BR:
3141                         if (ins->flags & MONO_INST_BRLABEL) {
3142                                 if (ins->inst_i0->inst_c0) {
3143                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3144                                 } else {
3145                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3146                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3147                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3148                                                 x86_jump8 (code, 0);
3149                                         else
3150                                                 x86_jump32 (code, 0);
3151                                 }
3152                         } else {
3153                                 if (ins->inst_target_bb->native_offset) {
3154                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3155                                 } else {
3156                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3157                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3158                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3159                                                 x86_jump8 (code, 0);
3160                                         else
3161                                                 x86_jump32 (code, 0);
3162                                 }
3163                         }
3164                         break;
3165                 case OP_BR_REG:
3166                         amd64_jump_reg (code, ins->sreg1);
3167                         break;
3168                 case OP_CEQ:
3169                 case OP_LCEQ:
3170                 case OP_ICEQ:
3171                 case OP_CLT:
3172                 case OP_LCLT:
3173                 case OP_ICLT:
3174                 case OP_CGT:
3175                 case OP_ICGT:
3176                 case OP_LCGT:
3177                 case OP_CLT_UN:
3178                 case OP_LCLT_UN:
3179                 case OP_ICLT_UN:
3180                 case OP_CGT_UN:
3181                 case OP_LCGT_UN:
3182                 case OP_ICGT_UN:
3183                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3184                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3185                         break;
3186                 case OP_COND_EXC_EQ:
3187                 case OP_COND_EXC_NE_UN:
3188                 case OP_COND_EXC_LT:
3189                 case OP_COND_EXC_LT_UN:
3190                 case OP_COND_EXC_GT:
3191                 case OP_COND_EXC_GT_UN:
3192                 case OP_COND_EXC_GE:
3193                 case OP_COND_EXC_GE_UN:
3194                 case OP_COND_EXC_LE:
3195                 case OP_COND_EXC_LE_UN:
3196                 case OP_COND_EXC_IEQ:
3197                 case OP_COND_EXC_INE_UN:
3198                 case OP_COND_EXC_ILT:
3199                 case OP_COND_EXC_ILT_UN:
3200                 case OP_COND_EXC_IGT:
3201                 case OP_COND_EXC_IGT_UN:
3202                 case OP_COND_EXC_IGE:
3203                 case OP_COND_EXC_IGE_UN:
3204                 case OP_COND_EXC_ILE:
3205                 case OP_COND_EXC_ILE_UN:
3206                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3207                         break;
3208                 case OP_COND_EXC_OV:
3209                 case OP_COND_EXC_NO:
3210                 case OP_COND_EXC_C:
3211                 case OP_COND_EXC_NC:
3212                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3213                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3214                         break;
3215                 case OP_COND_EXC_IOV:
3216                 case OP_COND_EXC_INO:
3217                 case OP_COND_EXC_IC:
3218                 case OP_COND_EXC_INC:
3219                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3220                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3221                         break;
3222
3223                 /* floating point opcodes */
3224                 case OP_R8CONST: {
3225                         double d = *(double *)ins->inst_p0;
3226
3227                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
3228                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3229                         }
3230                         else {
3231                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3232                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3233                         }
3234                         break;
3235                 }
3236                 case OP_R4CONST: {
3237                         float f = *(float *)ins->inst_p0;
3238
3239                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
3240                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3241                         }
3242                         else {
3243                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3244                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3245                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3246                         }
3247                         break;
3248                 }
3249                 case OP_STORER8_MEMBASE_REG:
3250                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3251                         break;
3252                 case OP_LOADR8_SPILL_MEMBASE:
3253                         g_assert_not_reached ();
3254                         break;
3255                 case OP_LOADR8_MEMBASE:
3256                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3257                         break;
3258                 case OP_STORER4_MEMBASE_REG:
3259                         /* This requires a double->single conversion */
3260                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3261                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3262                         break;
3263                 case OP_LOADR4_MEMBASE:
3264                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3265                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3266                         break;
3267                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3268                 case OP_ICONV_TO_R8:
3269                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3270                         break;
3271                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3272                 case OP_LCONV_TO_R8:
3273                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3274                         break;
3275                 case OP_FCONV_TO_R4:
3276                         /* FIXME: nothing to do ?? */
3277                         break;
3278                 case OP_FCONV_TO_I1:
3279                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3280                         break;
3281                 case OP_FCONV_TO_U1:
3282                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3283                         break;
3284                 case OP_FCONV_TO_I2:
3285                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3286                         break;
3287                 case OP_FCONV_TO_U2:
3288                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3289                         break;
3290                 case OP_FCONV_TO_U4:
3291                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3292                         break;
3293                 case OP_FCONV_TO_I4:
3294                 case OP_FCONV_TO_I:
3295                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3296                         break;
3297                 case OP_FCONV_TO_I8:
3298                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3299                         break;
3300                 case OP_LCONV_TO_R_UN: {
3301                         guint8 *br [2];
3302
3303                         /* Based on gcc code */
3304                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3305                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3306
3307                         /* Positive case */
3308                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3309                         br [1] = code; x86_jump8 (code, 0);
3310                         amd64_patch (br [0], code);
3311
3312                         /* Negative case */
3313                         /* Save to the red zone */
3314                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3315                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3316                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3317                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3318                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3319                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3320                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3321                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3322                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3323                         /* Restore */
3324                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3325                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3326                         amd64_patch (br [1], code);
3327                         break;
3328                 }
3329                 case OP_LCONV_TO_OVF_U4:
3330                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3331                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3332                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3333                         break;
3334                 case OP_LCONV_TO_OVF_I4_UN:
3335                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3336                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3337                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3338                         break;
3339                 case OP_FMOVE:
3340                         if (ins->dreg != ins->sreg1)
3341                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3342                         break;
3343                 case OP_FADD:
3344                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3345                         break;
3346                 case OP_FSUB:
3347                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3348                         break;
3349                 case OP_FMUL:
3350                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3351                         break;
3352                 case OP_FDIV:
3353                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3354                         break;
3355                 case OP_FNEG: {
3356                         static double r8_0 = -0.0;
3357
3358                         g_assert (ins->sreg1 == ins->dreg);
3359
3360                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3361                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3362                         break;
3363                 }
3364                 case OP_SIN:
3365                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3366                         break;
3367                 case OP_COS:
3368                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3369                         break;
3370                 case OP_ABS:
3371                         EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3372                         break;
3373                 case OP_SQRT:
3374                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3375                         break;
3376                 case OP_IMIN:
3377                         g_assert (cfg->opt & MONO_OPT_CMOV);
3378                         g_assert (ins->dreg == ins->sreg1);
3379                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3380                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3381                         break;
3382                 case OP_IMAX:
3383                         g_assert (cfg->opt & MONO_OPT_CMOV);
3384                         g_assert (ins->dreg == ins->sreg1);
3385                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3386                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3387                         break;
3388                 case OP_LMIN:
3389                         g_assert (cfg->opt & MONO_OPT_CMOV);
3390                         g_assert (ins->dreg == ins->sreg1);
3391                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3392                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3393                         break;
3394                 case OP_LMAX:
3395                         g_assert (cfg->opt & MONO_OPT_CMOV);
3396                         g_assert (ins->dreg == ins->sreg1);
3397                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3398                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3399                         break;
3400                 case OP_X86_FPOP:
3401                         break;
3402                 case OP_FCOMPARE:
3403                         /*
3404                          * The two arguments are swapped because the fbranch instructions
3405                          * depend on this for the non-sse case to work.
3406                          */
3407                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3408                         break;
3409                 case OP_FCEQ: {
3410                         /* zeroing the register at the start results in
3411                          * shorter and faster code (we can also remove the widening op)
3412                          */
3413                         guchar *unordered_check;
3414                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3415                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3416                         unordered_check = code;
3417                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3418                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3419                         amd64_patch (unordered_check, code);
3420                         break;
3421                 }
3422                 case OP_FCLT:
3423                 case OP_FCLT_UN:
3424                         /* zeroing the register at the start results in
3425                          * shorter and faster code (we can also remove the widening op)
3426                          */
3427                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3428                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3429                         if (ins->opcode == OP_FCLT_UN) {
3430                                 guchar *unordered_check = code;
3431                                 guchar *jump_to_end;
3432                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3433                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3434                                 jump_to_end = code;
3435                                 x86_jump8 (code, 0);
3436                                 amd64_patch (unordered_check, code);
3437                                 amd64_inc_reg (code, ins->dreg);
3438                                 amd64_patch (jump_to_end, code);
3439                         } else {
3440                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3441                         }
3442                         break;
3443                 case OP_FCGT:
3444                 case OP_FCGT_UN: {
3445                         /* zeroing the register at the start results in
3446                          * shorter and faster code (we can also remove the widening op)
3447                          */
3448                         guchar *unordered_check;
3449                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3450                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3451                         if (ins->opcode == OP_FCGT) {
3452                                 unordered_check = code;
3453                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3454                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3455                                 amd64_patch (unordered_check, code);
3456                         } else {
3457                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3458                         }
3459                         break;
3460                 }
3461                 case OP_FCLT_MEMBASE:
3462                 case OP_FCGT_MEMBASE:
3463                 case OP_FCLT_UN_MEMBASE:
3464                 case OP_FCGT_UN_MEMBASE:
3465                 case OP_FCEQ_MEMBASE: {
3466                         guchar *unordered_check, *jump_to_end;
3467                         int x86_cond;
3468
3469                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3470                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3471
3472                         switch (ins->opcode) {
3473                         case OP_FCEQ_MEMBASE:
3474                                 x86_cond = X86_CC_EQ;
3475                                 break;
3476                         case OP_FCLT_MEMBASE:
3477                         case OP_FCLT_UN_MEMBASE:
3478                                 x86_cond = X86_CC_LT;
3479                                 break;
3480                         case OP_FCGT_MEMBASE:
3481                         case OP_FCGT_UN_MEMBASE:
3482                                 x86_cond = X86_CC_GT;
3483                                 break;
3484                         default:
3485                                 g_assert_not_reached ();
3486                         }
3487
3488                         unordered_check = code;
3489                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3490                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3491
3492                         switch (ins->opcode) {
3493                         case OP_FCEQ_MEMBASE:
3494                         case OP_FCLT_MEMBASE:
3495                         case OP_FCGT_MEMBASE:
3496                                 amd64_patch (unordered_check, code);
3497                                 break;
3498                         case OP_FCLT_UN_MEMBASE:
3499                         case OP_FCGT_UN_MEMBASE:
3500                                 jump_to_end = code;
3501                                 x86_jump8 (code, 0);
3502                                 amd64_patch (unordered_check, code);
3503                                 amd64_inc_reg (code, ins->dreg);
3504                                 amd64_patch (jump_to_end, code);
3505                                 break;
3506                         default:
3507                                 break;
3508                         }
3509                         break;
3510                 }
3511                 case OP_FBEQ: {
3512                         guchar *jump = code;
3513                         x86_branch8 (code, X86_CC_P, 0, TRUE);
3514                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3515                         amd64_patch (jump, code);
3516                         break;
3517                 }
3518                 case OP_FBNE_UN:
3519                         /* Branch if C013 != 100 */
3520                         /* branch if !ZF or (PF|CF) */
3521                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3522                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3523                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3524                         break;
3525                 case OP_FBLT:
3526                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3527                         break;
3528                 case OP_FBLT_UN:
3529                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3530                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3531                         break;
3532                 case OP_FBGT:
3533                 case OP_FBGT_UN:
3534                         if (ins->opcode == OP_FBGT) {
3535                                 guchar *br1;
3536
3537                                 /* skip branch if C1=1 */
3538                                 br1 = code;
3539                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3540                                 /* branch if (C0 | C3) = 1 */
3541                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3542                                 amd64_patch (br1, code);
3543                                 break;
3544                         } else {
3545                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3546                         }
3547                         break;
3548                 case OP_FBGE: {
3549                         /* Branch if C013 == 100 or 001 */
3550                         guchar *br1;
3551
3552                         /* skip branch if C1=1 */
3553                         br1 = code;
3554                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3555                         /* branch if (C0 | C3) = 1 */
3556                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3557                         amd64_patch (br1, code);
3558                         break;
3559                 }
3560                 case OP_FBGE_UN:
3561                         /* Branch if C013 == 000 */
3562                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3563                         break;
3564                 case OP_FBLE: {
3565                         /* Branch if C013=000 or 100 */
3566                         guchar *br1;
3567
3568                         /* skip branch if C1=1 */
3569                         br1 = code;
3570                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3571                         /* branch if C0=0 */
3572                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3573                         amd64_patch (br1, code);
3574                         break;
3575                 }
3576                 case OP_FBLE_UN:
3577                         /* Branch if C013 != 001 */
3578                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3579                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3580                         break;
3581                 case OP_CKFINITE:
3582                         /* Transfer value to the fp stack */
3583                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3584                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3585                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3586
3587                         amd64_push_reg (code, AMD64_RAX);
3588                         amd64_fxam (code);
3589                         amd64_fnstsw (code);
3590                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3591                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3592                         amd64_pop_reg (code, AMD64_RAX);
3593                         amd64_fstp (code, 0);
3594                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3595                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3596                         break;
3597                 case OP_TLS_GET: {
3598                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
3599                         break;
3600                 }
3601                 case OP_MEMORY_BARRIER: {
3602                         /* Not needed on amd64 */
3603                         break;
3604                 }
3605                 case OP_ATOMIC_ADD_I4:
3606                 case OP_ATOMIC_ADD_I8: {
3607                         int dreg = ins->dreg;
3608                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3609
3610                         if (dreg == ins->inst_basereg)
3611                                 dreg = AMD64_R11;
3612
3613                         if (dreg != ins->sreg2)
3614                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3615
3616                         x86_prefix (code, X86_LOCK_PREFIX);
3617                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3618
3619                         if (dreg != ins->dreg)
3620                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3621
3622                         break;
3623                 }
3624                 case OP_ATOMIC_ADD_NEW_I4:
3625                 case OP_ATOMIC_ADD_NEW_I8: {
3626                         int dreg = ins->dreg;
3627                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3628
3629                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3630                                 dreg = AMD64_R11;
3631
3632                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3633                         amd64_prefix (code, X86_LOCK_PREFIX);
3634                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3635                         /* dreg contains the old value, add with sreg2 value */
3636                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3637
3638                         if (ins->dreg != dreg)
3639                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3640
3641                         break;
3642                 }
3643                 case OP_ATOMIC_EXCHANGE_I4:
3644                 case OP_ATOMIC_EXCHANGE_I8: {
3645                         guchar *br[2];
3646                         int sreg2 = ins->sreg2;
3647                         int breg = ins->inst_basereg;
3648                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
3649
3650                         /*
3651                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
3652                          * an explanation of how this works.
3653                          */
3654
3655                         /* cmpxchg uses eax as comperand, need to make sure we can use it
3656                          * hack to overcome limits in x86 reg allocator
3657                          * (req: dreg == eax and sreg2 != eax and breg != eax)
3658                          */
3659                         /* The pushes invalidate rsp */
3660                         if ((breg == AMD64_RAX) || (breg == AMD64_RSP)) {
3661                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
3662                                 breg = AMD64_R11;
3663                         }
3664
3665                         if (ins->dreg != AMD64_RAX)
3666                                 amd64_push_reg (code, AMD64_RAX);
3667
3668                         /* We need the EAX reg for the cmpxchg */
3669                         if (ins->sreg2 == AMD64_RAX) {
3670                                 amd64_push_reg (code, AMD64_RDX);
3671                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3672                                 sreg2 = AMD64_RDX;
3673                         }
3674
3675                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3676
3677                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3678                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3679                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3680                         amd64_patch (br [1], br [0]);
3681
3682                         if (ins->dreg != AMD64_RAX) {
3683                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
3684                                 amd64_pop_reg (code, AMD64_RAX);
3685                         }
3686
3687                         if (ins->sreg2 != sreg2)
3688                                 amd64_pop_reg (code, AMD64_RDX);
3689
3690                         break;
3691                 }
3692                 default:
3693                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3694                         g_assert_not_reached ();
3695                 }
3696
3697                 if ((code - cfg->native_code - offset) > max_len) {
3698                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3699                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3700                         g_assert_not_reached ();
3701                 }
3702
3703                 cpos += max_len;
3704
3705                 last_offset = offset;
3706         }
3707
3708         cfg->code_len = code - cfg->native_code;
3709 }
3710
3711 void
3712 mono_arch_register_lowlevel_calls (void)
3713 {
3714 }
3715
3716 void
3717 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3718 {
3719         MonoJumpInfo *patch_info;
3720         gboolean compile_aot = !run_cctors;
3721
3722         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3723                 unsigned char *ip = patch_info->ip.i + code;
3724                 unsigned char *target;
3725
3726                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3727
3728                 if (compile_aot) {
3729                         switch (patch_info->type) {
3730                         case MONO_PATCH_INFO_BB:
3731                         case MONO_PATCH_INFO_LABEL:
3732                                 break;
3733                         default:
3734                                 /* No need to patch these */
3735                                 continue;
3736                         }
3737                 }
3738
3739                 switch (patch_info->type) {
3740                 case MONO_PATCH_INFO_NONE:
3741                         continue;
3742                 case MONO_PATCH_INFO_METHOD_REL:
3743                 case MONO_PATCH_INFO_R8:
3744                 case MONO_PATCH_INFO_R4:
3745                         g_assert_not_reached ();
3746                         continue;
3747                 case MONO_PATCH_INFO_BB:
3748                         break;
3749                 default:
3750                         break;
3751                 }
3752
3753                 /*
3754                  * Debug code to help track down problems where the target of a near call is
3755                  * is not valid.
3756                  */
3757                 if (amd64_is_near_call (ip)) {
3758                         gint64 disp = (guint8*)target - (guint8*)ip;
3759
3760                         if (!amd64_is_imm32 (disp)) {
3761                                 printf ("TYPE: %d\n", patch_info->type);
3762                                 switch (patch_info->type) {
3763                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
3764                                         printf ("V: %s\n", patch_info->data.name);
3765                                         break;
3766                                 case MONO_PATCH_INFO_METHOD_JUMP:
3767                                 case MONO_PATCH_INFO_METHOD:
3768                                         printf ("V: %s\n", patch_info->data.method->name);
3769                                         break;
3770                                 default:
3771                                         break;
3772                                 }
3773                         }
3774                 }
3775
3776                 amd64_patch (ip, (gpointer)target);
3777         }
3778 }
3779
3780 /*
3781  * This macro is used for testing whenever the unwinder works correctly at every point
3782  * where an async exception can happen.
3783  */
3784 /* This will generate a SIGSEGV at the given point in the code */
3785 #define async_exc_point(code) do { \
3786     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
3787          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
3788              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
3789          cfg->arch.async_point_count ++; \
3790     } \
3791 } while (0)
3792
3793 guint8 *
3794 mono_arch_emit_prolog (MonoCompile *cfg)
3795 {
3796         MonoMethod *method = cfg->method;
3797         MonoBasicBlock *bb;
3798         MonoMethodSignature *sig;
3799         MonoInst *ins;
3800         int alloc_size, pos, max_offset, i, quad;
3801         guint8 *code;
3802         CallInfo *cinfo;
3803         gint32 lmf_offset = cfg->arch.lmf_offset;
3804         gboolean args_clobbered = FALSE;
3805         gboolean trace = FALSE;
3806
3807         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
3808
3809         code = cfg->native_code = g_malloc (cfg->code_size);
3810
3811         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
3812                 trace = TRUE;
3813
3814         /* Amount of stack space allocated by register saving code */
3815         pos = 0;
3816
3817         /*
3818          * The prolog consists of the following parts:
3819          * FP present:
3820          * - push rbp, mov rbp, rsp
3821          * - save callee saved regs using pushes
3822          * - allocate frame
3823          * - save rgctx if needed
3824          * - save lmf if needed
3825          * FP not present:
3826          * - allocate frame
3827          * - save rgctx if needed
3828          * - save lmf if needed
3829          * - save callee saved regs using moves
3830          */
3831
3832         async_exc_point (code);
3833
3834         if (!cfg->arch.omit_fp) {
3835                 amd64_push_reg (code, AMD64_RBP);
3836                 async_exc_point (code);
3837                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
3838                 async_exc_point (code);
3839         }
3840
3841         /* Save callee saved registers */
3842         if (!cfg->arch.omit_fp && !method->save_lmf) {
3843                 for (i = 0; i < AMD64_NREG; ++i)
3844                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3845                                 amd64_push_reg (code, i);
3846                                 pos += sizeof (gpointer);
3847                                 async_exc_point (code);
3848                         }
3849         }
3850
3851         if (cfg->arch.omit_fp) {
3852                 /*
3853                  * On enter, the stack is misaligned by the the pushing of the return
3854                  * address. It is either made aligned by the pushing of %rbp, or by
3855                  * this.
3856                  */
3857                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
3858                 if ((alloc_size % 16) == 0)
3859                         alloc_size += 8;
3860         } else {
3861                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
3862
3863                 alloc_size -= pos;
3864         }
3865
3866         cfg->arch.stack_alloc_size = alloc_size;
3867
3868         /* Allocate stack frame */
3869         if (alloc_size) {
3870                 /* See mono_emit_stack_alloc */
3871 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3872                 guint32 remaining_size = alloc_size;
3873                 while (remaining_size >= 0x1000) {
3874                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3875                         async_exc_point (code);
3876                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3877                         remaining_size -= 0x1000;
3878                 }
3879                 if (remaining_size) {
3880                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
3881                         async_exc_point (code);
3882                 }
3883 #else
3884                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
3885                 async_exc_point (code);
3886 #endif
3887         }
3888
3889         /* Stack alignment check */
3890 #if 0
3891         {
3892                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
3893                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
3894                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3895                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
3896                 amd64_breakpoint (code);
3897         }
3898 #endif
3899
3900         /* Save LMF */
3901         if (method->save_lmf) {
3902                 /*
3903                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3904                  */
3905                 /* sp is saved right before calls */
3906                 /* Skip method (only needed for trampoline LMF frames) */
3907                 /* Save callee saved regs */
3908                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
3909                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3910                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
3911                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
3912                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
3913                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
3914         }
3915
3916         /* Save callee saved registers */
3917         if (cfg->arch.omit_fp && !method->save_lmf) {
3918                 gint32 save_area_offset = 0;
3919
3920                 /* Save caller saved registers after sp is adjusted */
3921                 /* The registers are saved at the bottom of the frame */
3922                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
3923                 for (i = 0; i < AMD64_NREG; ++i)
3924                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3925                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
3926                                 save_area_offset += 8;
3927                                 async_exc_point (code);
3928                         }
3929         }
3930
3931         /* store runtime generic context */
3932         if (cfg->rgctx_var) {
3933                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
3934                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
3935
3936                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
3937         }
3938
3939         /* compute max_offset in order to use short forward jumps */
3940         max_offset = 0;
3941         if (cfg->opt & MONO_OPT_BRANCH) {
3942                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
3943                         bb->max_offset = max_offset;
3944
3945                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
3946                                 max_offset += 6;
3947                         /* max alignment for loops */
3948                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
3949                                 max_offset += LOOP_ALIGNMENT;
3950
3951                         MONO_BB_FOR_EACH_INS (bb, ins) {
3952                                 if (ins->opcode == OP_LABEL)
3953                                         ins->inst_c1 = max_offset;
3954
3955                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3956                         }
3957                 }
3958         }
3959
3960         sig = mono_method_signature (method);
3961         pos = 0;
3962
3963         cinfo = cfg->arch.cinfo;
3964
3965         if (sig->ret->type != MONO_TYPE_VOID) {
3966                 /* Save volatile arguments to the stack */
3967                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
3968                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
3969         }
3970
3971         /* Keep this in sync with emit_load_volatile_arguments */
3972         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3973                 ArgInfo *ainfo = cinfo->args + i;
3974                 gint32 stack_offset;
3975                 MonoType *arg_type;
3976
3977                 ins = cfg->args [i];
3978
3979                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
3980                         /* Unused arguments */
3981                         continue;
3982
3983                 if (sig->hasthis && (i == 0))
3984                         arg_type = &mono_defaults.object_class->byval_arg;
3985                 else
3986                         arg_type = sig->params [i - sig->hasthis];
3987
3988                 stack_offset = ainfo->offset + ARGS_OFFSET;
3989
3990                 /* Save volatile arguments to the stack */
3991                 if (ins->opcode != OP_REGVAR) {
3992                         switch (ainfo->storage) {
3993                         case ArgInIReg: {
3994                                 guint32 size = 8;
3995
3996                                 /* FIXME: I1 etc */
3997                                 /*
3998                                 if (stack_offset & 0x1)
3999                                         size = 1;
4000                                 else if (stack_offset & 0x2)
4001                                         size = 2;
4002                                 else if (stack_offset & 0x4)
4003                                         size = 4;
4004                                 else
4005                                         size = 8;
4006                                 */
4007                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4008                                 break;
4009                         }
4010                         case ArgInFloatSSEReg:
4011                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4012                                 break;
4013                         case ArgInDoubleSSEReg:
4014                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4015                                 break;
4016                         case ArgValuetypeInReg:
4017                                 for (quad = 0; quad < 2; quad ++) {
4018                                         switch (ainfo->pair_storage [quad]) {
4019                                         case ArgInIReg:
4020                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4021                                                 break;
4022                                         case ArgInFloatSSEReg:
4023                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4024                                                 break;
4025                                         case ArgInDoubleSSEReg:
4026                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4027                                                 break;
4028                                         case ArgNone:
4029                                                 break;
4030                                         default:
4031                                                 g_assert_not_reached ();
4032                                         }
4033                                 }
4034                                 break;
4035                         default:
4036                                 break;
4037                         }
4038                 } else {
4039                         /* Argument allocated to (non-volatile) register */
4040                         switch (ainfo->storage) {
4041                         case ArgInIReg:
4042                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4043                                 break;
4044                         case ArgOnStack:
4045                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4046                                 break;
4047                         default:
4048                                 g_assert_not_reached ();
4049                         }
4050                 }
4051         }
4052
4053         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4054         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4055                 guint64 domain = (guint64)cfg->domain;
4056
4057                 args_clobbered = TRUE;
4058
4059                 /*
4060                  * The call might clobber argument registers, but they are already
4061                  * saved to the stack/global regs.
4062                  */
4063                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4064                         guint8 *buf, *no_domain_branch;
4065
4066                         code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4067                         if ((domain >> 32) == 0)
4068                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4069                         else
4070                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4071                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4072                         no_domain_branch = code;
4073                         x86_branch8 (code, X86_CC_NE, 0, 0);
4074                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4075                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4076                         buf = code;
4077                         x86_branch8 (code, X86_CC_NE, 0, 0);
4078                         amd64_patch (no_domain_branch, code);
4079                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4080                         amd64_patch (buf, code);
4081                 } else {
4082                         g_assert (!cfg->compile_aot);
4083                         if ((domain >> 32) == 0)
4084                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4085                         else
4086                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4087                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4088                 }
4089         }
4090
4091         if (method->save_lmf) {
4092                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4093                         /*
4094                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4095                          * through the mono_lmf_addr TLS variable.
4096                          */
4097                         /* %rax = previous_lmf */
4098                         x86_prefix (code, X86_FS_PREFIX);
4099                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4100
4101                         /* Save previous_lmf */
4102                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4103                         /* Set new lmf */
4104                         if (lmf_offset == 0) {
4105                                 x86_prefix (code, X86_FS_PREFIX);
4106                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4107                         } else {
4108                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4109                                 x86_prefix (code, X86_FS_PREFIX);
4110                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4111                         }
4112                 } else {
4113                         if (lmf_addr_tls_offset != -1) {
4114                                 /* Load lmf quicky using the FS register */
4115                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4116                         }
4117                         else {
4118                                 /*
4119                                  * The call might clobber argument registers, but they are already
4120                                  * saved to the stack/global regs.
4121                                  */
4122                                 args_clobbered = TRUE;
4123                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4124                                                                   (gpointer)"mono_get_lmf_addr");
4125                         }
4126
4127                         /* Save lmf_addr */
4128                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4129                         /* Save previous_lmf */
4130                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4131                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4132                         /* Set new lmf */
4133                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4134                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4135                 }
4136         }
4137
4138         if (trace) {
4139                 args_clobbered = TRUE;
4140                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4141         }
4142
4143         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4144                 args_clobbered = TRUE;
4145
4146         /*
4147          * Optimize the common case of the first bblock making a call with the same
4148          * arguments as the method. This works because the arguments are still in their
4149          * original argument registers.
4150          * FIXME: Generalize this
4151          */
4152         if (!args_clobbered) {
4153                 MonoBasicBlock *first_bb = cfg->bb_entry;
4154                 MonoInst *next;
4155
4156                 next = mono_inst_list_first (&first_bb->ins_list);
4157                 if (!next && first_bb->next_bb) {
4158                         first_bb = first_bb->next_bb;
4159                         next = mono_inst_list_first (&first_bb->ins_list);
4160                 }
4161
4162                 if (first_bb->in_count > 1)
4163                         next = NULL;
4164
4165                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4166                         ArgInfo *ainfo = cinfo->args + i;
4167                         gboolean match = FALSE;
4168
4169                         ins = cfg->args [i];
4170                         if (ins->opcode != OP_REGVAR) {
4171                                 switch (ainfo->storage) {
4172                                 case ArgInIReg: {
4173                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4174                                                 if (next->dreg == ainfo->reg) {
4175                                                         NULLIFY_INS (next);
4176                                                         match = TRUE;
4177                                                 } else {
4178                                                         next->opcode = OP_MOVE;
4179                                                         next->sreg1 = ainfo->reg;
4180                                                         /* Only continue if the instruction doesn't change argument regs */
4181                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4182                                                                 match = TRUE;
4183                                                 }
4184                                         }
4185                                         break;
4186                                 }
4187                                 default:
4188                                         break;
4189                                 }
4190                         } else {
4191                                 /* Argument allocated to (non-volatile) register */
4192                                 switch (ainfo->storage) {
4193                                 case ArgInIReg:
4194                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4195                                                 NULLIFY_INS (next);
4196                                                 match = TRUE;
4197                                         }
4198                                         break;
4199                                 default:
4200                                         break;
4201                                 }
4202                         }
4203
4204                         if (match) {
4205                                 next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4206                                 if (!next)
4207                                         break;
4208                         }
4209                 }
4210         }
4211
4212         cfg->code_len = code - cfg->native_code;
4213
4214         g_assert (cfg->code_len < cfg->code_size);
4215
4216         return code;
4217 }
4218
4219 void
4220 mono_arch_emit_epilog (MonoCompile *cfg)
4221 {
4222         MonoMethod *method = cfg->method;
4223         int quad, pos, i;
4224         guint8 *code;
4225         int max_epilog_size = 16;
4226         CallInfo *cinfo;
4227         gint32 lmf_offset = cfg->arch.lmf_offset;
4228
4229         if (cfg->method->save_lmf)
4230                 max_epilog_size += 256;
4231
4232         if (mono_jit_trace_calls != NULL)
4233                 max_epilog_size += 50;
4234
4235         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4236                 max_epilog_size += 50;
4237
4238         max_epilog_size += (AMD64_NREG * 2);
4239
4240         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4241                 cfg->code_size *= 2;
4242                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4243                 mono_jit_stats.code_reallocs++;
4244         }
4245
4246         code = cfg->native_code + cfg->code_len;
4247
4248         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4249                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4250
4251         /* the code restoring the registers must be kept in sync with OP_JMP */
4252         pos = 0;
4253
4254         if (method->save_lmf) {
4255                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4256                         /*
4257                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4258                          * through the mono_lmf_addr TLS variable.
4259                          */
4260                         /* reg = previous_lmf */
4261                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4262                         x86_prefix (code, X86_FS_PREFIX);
4263                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4264                 } else {
4265                         /* Restore previous lmf */
4266                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4267                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4268                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4269                 }
4270
4271                 /* Restore caller saved regs */
4272                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4273                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
4274                 }
4275                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4276                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4277                 }
4278                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4279                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4280                 }
4281                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4282                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4283                 }
4284                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4285                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4286                 }
4287                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4288                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4289                 }
4290         } else {
4291
4292                 if (cfg->arch.omit_fp) {
4293                         gint32 save_area_offset = 0;
4294
4295                         for (i = 0; i < AMD64_NREG; ++i)
4296                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4297                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4298                                         save_area_offset += 8;
4299                                 }
4300                 }
4301                 else {
4302                         for (i = 0; i < AMD64_NREG; ++i)
4303                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4304                                         pos -= sizeof (gpointer);
4305
4306                         if (pos) {
4307                                 if (pos == - sizeof (gpointer)) {
4308                                         /* Only one register, so avoid lea */
4309                                         for (i = AMD64_NREG - 1; i > 0; --i)
4310                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4311                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4312                                                 }
4313                                 }
4314                                 else {
4315                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4316
4317                                         /* Pop registers in reverse order */
4318                                         for (i = AMD64_NREG - 1; i > 0; --i)
4319                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4320                                                         amd64_pop_reg (code, i);
4321                                                 }
4322                                 }
4323                         }
4324                 }
4325         }
4326
4327         /* Load returned vtypes into registers if needed */
4328         cinfo = cfg->arch.cinfo;
4329         if (cinfo->ret.storage == ArgValuetypeInReg) {
4330                 ArgInfo *ainfo = &cinfo->ret;
4331                 MonoInst *inst = cfg->ret;
4332
4333                 for (quad = 0; quad < 2; quad ++) {
4334                         switch (ainfo->pair_storage [quad]) {
4335                         case ArgInIReg:
4336                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4337                                 break;
4338                         case ArgInFloatSSEReg:
4339                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4340                                 break;
4341                         case ArgInDoubleSSEReg:
4342                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4343                                 break;
4344                         case ArgNone:
4345                                 break;
4346                         default:
4347                                 g_assert_not_reached ();
4348                         }
4349                 }
4350         }
4351
4352         if (cfg->arch.omit_fp) {
4353                 if (cfg->arch.stack_alloc_size)
4354                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4355         } else {
4356                 amd64_leave (code);
4357         }
4358         async_exc_point (code);
4359         amd64_ret (code);
4360
4361         cfg->code_len = code - cfg->native_code;
4362
4363         g_assert (cfg->code_len < cfg->code_size);
4364
4365         if (cfg->arch.omit_fp) {
4366                 /*
4367                  * Encode the stack size into used_int_regs so the exception handler
4368                  * can access it.
4369                  */
4370                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4371                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4372         }
4373 }
4374
4375 void
4376 mono_arch_emit_exceptions (MonoCompile *cfg)
4377 {
4378         MonoJumpInfo *patch_info;
4379         int nthrows, i;
4380         guint8 *code;
4381         MonoClass *exc_classes [16];
4382         guint8 *exc_throw_start [16], *exc_throw_end [16];
4383         guint32 code_size = 0;
4384
4385         /* Compute needed space */
4386         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4387                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4388                         code_size += 40;
4389                 if (patch_info->type == MONO_PATCH_INFO_R8)
4390                         code_size += 8 + 15; /* sizeof (double) + alignment */
4391                 if (patch_info->type == MONO_PATCH_INFO_R4)
4392                         code_size += 4 + 15; /* sizeof (float) + alignment */
4393         }
4394
4395         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4396                 cfg->code_size *= 2;
4397                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4398                 mono_jit_stats.code_reallocs++;
4399         }
4400
4401         code = cfg->native_code + cfg->code_len;
4402
4403         /* add code to raise exceptions */
4404         nthrows = 0;
4405         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4406                 switch (patch_info->type) {
4407                 case MONO_PATCH_INFO_EXC: {
4408                         MonoClass *exc_class;
4409                         guint8 *buf, *buf2;
4410                         guint32 throw_ip;
4411
4412                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4413
4414                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4415                         g_assert (exc_class);
4416                         throw_ip = patch_info->ip.i;
4417
4418                         //x86_breakpoint (code);
4419                         /* Find a throw sequence for the same exception class */
4420                         for (i = 0; i < nthrows; ++i)
4421                                 if (exc_classes [i] == exc_class)
4422                                         break;
4423                         if (i < nthrows) {
4424                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4425                                 x86_jump_code (code, exc_throw_start [i]);
4426                                 patch_info->type = MONO_PATCH_INFO_NONE;
4427                         }
4428                         else {
4429                                 buf = code;
4430                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
4431                                 buf2 = code;
4432
4433                                 if (nthrows < 16) {
4434                                         exc_classes [nthrows] = exc_class;
4435                                         exc_throw_start [nthrows] = code;
4436                                 }
4437                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
4438                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4439                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4440                                 patch_info->ip.i = code - cfg->native_code;
4441
4442                                 code = emit_call_body (cfg, code, patch_info->type, patch_info->data.name);
4443
4444                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
4445                                 while (buf < buf2)
4446                                         x86_nop (buf);
4447
4448                                 if (nthrows < 16) {
4449                                         exc_throw_end [nthrows] = code;
4450                                         nthrows ++;
4451                                 }
4452                         }
4453                         break;
4454                 }
4455                 default:
4456                         /* do nothing */
4457                         break;
4458                 }
4459         }
4460
4461         /* Handle relocations with RIP relative addressing */
4462         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4463                 gboolean remove = FALSE;
4464
4465                 switch (patch_info->type) {
4466                 case MONO_PATCH_INFO_R8:
4467                 case MONO_PATCH_INFO_R4: {
4468                         guint8 *pos;
4469
4470                         /* The SSE opcodes require a 16 byte alignment */
4471                         code = (guint8*)ALIGN_TO (code, 16);
4472
4473                         pos = cfg->native_code + patch_info->ip.i;
4474
4475                         if (IS_REX (pos [1]))
4476                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
4477                         else
4478                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4479
4480                         if (patch_info->type == MONO_PATCH_INFO_R8) {
4481                                 *(double*)code = *(double*)patch_info->data.target;
4482                                 code += sizeof (double);
4483                         } else {
4484                                 *(float*)code = *(float*)patch_info->data.target;
4485                                 code += sizeof (float);
4486                         }
4487
4488                         remove = TRUE;
4489                         break;
4490                 }
4491                 default:
4492                         break;
4493                 }
4494
4495                 if (remove) {
4496                         if (patch_info == cfg->patch_info)
4497                                 cfg->patch_info = patch_info->next;
4498                         else {
4499                                 MonoJumpInfo *tmp;
4500
4501                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4502                                         ;
4503                                 tmp->next = patch_info->next;
4504                         }
4505                 }
4506         }
4507
4508         cfg->code_len = code - cfg->native_code;
4509
4510         g_assert (cfg->code_len < cfg->code_size);
4511
4512 }
4513
4514 void*
4515 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4516 {
4517         guchar *code = p;
4518         CallInfo *cinfo = NULL;
4519         MonoMethodSignature *sig;
4520         MonoInst *inst;
4521         int i, n, stack_area = 0;
4522
4523         /* Keep this in sync with mono_arch_get_argument_info */
4524
4525         if (enable_arguments) {
4526                 /* Allocate a new area on the stack and save arguments there */
4527                 sig = mono_method_signature (cfg->method);
4528
4529                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
4530
4531                 n = sig->param_count + sig->hasthis;
4532
4533                 stack_area = ALIGN_TO (n * 8, 16);
4534
4535                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4536
4537                 for (i = 0; i < n; ++i) {
4538                         inst = cfg->args [i];
4539
4540                         if (inst->opcode == OP_REGVAR)
4541                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4542                         else {
4543                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4544                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4545                         }
4546                 }
4547         }
4548
4549         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4550         amd64_set_reg_template (code, AMD64_ARG_REG1);
4551         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
4552         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4553
4554         if (enable_arguments)
4555                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4556
4557         return code;
4558 }
4559
4560 enum {
4561         SAVE_NONE,
4562         SAVE_STRUCT,
4563         SAVE_EAX,
4564         SAVE_EAX_EDX,
4565         SAVE_XMM
4566 };
4567
4568 void*
4569 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4570 {
4571         guchar *code = p;
4572         int save_mode = SAVE_NONE;
4573         MonoMethod *method = cfg->method;
4574         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4575
4576         switch (rtype) {
4577         case MONO_TYPE_VOID:
4578                 /* special case string .ctor icall */
4579                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4580                         save_mode = SAVE_EAX;
4581                 else
4582                         save_mode = SAVE_NONE;
4583                 break;
4584         case MONO_TYPE_I8:
4585         case MONO_TYPE_U8:
4586                 save_mode = SAVE_EAX;
4587                 break;
4588         case MONO_TYPE_R4:
4589         case MONO_TYPE_R8:
4590                 save_mode = SAVE_XMM;
4591                 break;
4592         case MONO_TYPE_GENERICINST:
4593                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
4594                         save_mode = SAVE_EAX;
4595                         break;
4596                 }
4597                 /* Fall through */
4598         case MONO_TYPE_VALUETYPE:
4599                 save_mode = SAVE_STRUCT;
4600                 break;
4601         default:
4602                 save_mode = SAVE_EAX;
4603                 break;
4604         }
4605
4606         /* Save the result and copy it into the proper argument register */
4607         switch (save_mode) {
4608         case SAVE_EAX:
4609                 amd64_push_reg (code, AMD64_RAX);
4610                 /* Align stack */
4611                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4612                 if (enable_arguments)
4613                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
4614                 break;
4615         case SAVE_STRUCT:
4616                 /* FIXME: */
4617                 if (enable_arguments)
4618                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
4619                 break;
4620         case SAVE_XMM:
4621                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4622                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4623                 /* Align stack */
4624                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4625                 /*
4626                  * The result is already in the proper argument register so no copying
4627                  * needed.
4628                  */
4629                 break;
4630         case SAVE_NONE:
4631                 break;
4632         default:
4633                 g_assert_not_reached ();
4634         }
4635
4636         /* Set %al since this is a varargs call */
4637         if (save_mode == SAVE_XMM)
4638                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4639         else
4640                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4641
4642         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4643         amd64_set_reg_template (code, AMD64_ARG_REG1);
4644         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4645
4646         /* Restore result */
4647         switch (save_mode) {
4648         case SAVE_EAX:
4649                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4650                 amd64_pop_reg (code, AMD64_RAX);
4651                 break;
4652         case SAVE_STRUCT:
4653                 /* FIXME: */
4654                 break;
4655         case SAVE_XMM:
4656                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4657                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4658                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4659                 break;
4660         case SAVE_NONE:
4661                 break;
4662         default:
4663                 g_assert_not_reached ();
4664         }
4665
4666         return code;
4667 }
4668
4669 void
4670 mono_arch_flush_icache (guint8 *code, gint size)
4671 {
4672         /* Not needed */
4673 }
4674
4675 void
4676 mono_arch_flush_register_windows (void)
4677 {
4678 }
4679
4680 gboolean
4681 mono_arch_is_inst_imm (gint64 imm)
4682 {
4683         return amd64_is_imm32 (imm);
4684 }
4685
4686 /*
4687  * Determine whenever the trap whose info is in SIGINFO is caused by
4688  * integer overflow.
4689  */
4690 gboolean
4691 mono_arch_is_int_overflow (void *sigctx, void *info)
4692 {
4693         MonoContext ctx;
4694         guint8* rip;
4695         int reg;
4696         gint64 value;
4697
4698         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
4699
4700         rip = (guint8*)ctx.rip;
4701
4702         if (IS_REX (rip [0])) {
4703                 reg = amd64_rex_b (rip [0]);
4704                 rip ++;
4705         }
4706         else
4707                 reg = 0;
4708
4709         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4710                 /* idiv REG */
4711                 reg += x86_modrm_rm (rip [1]);
4712
4713                 switch (reg) {
4714                 case AMD64_RAX:
4715                         value = ctx.rax;
4716                         break;
4717                 case AMD64_RBX:
4718                         value = ctx.rbx;
4719                         break;
4720                 case AMD64_RCX:
4721                         value = ctx.rcx;
4722                         break;
4723                 case AMD64_RDX:
4724                         value = ctx.rdx;
4725                         break;
4726                 case AMD64_RBP:
4727                         value = ctx.rbp;
4728                         break;
4729                 case AMD64_RSP:
4730                         value = ctx.rsp;
4731                         break;
4732                 case AMD64_RSI:
4733                         value = ctx.rsi;
4734                         break;
4735                 case AMD64_RDI:
4736                         value = ctx.rdi;
4737                         break;
4738                 case AMD64_R12:
4739                         value = ctx.r12;
4740                         break;
4741                 case AMD64_R13:
4742                         value = ctx.r13;
4743                         break;
4744                 case AMD64_R14:
4745                         value = ctx.r14;
4746                         break;
4747                 case AMD64_R15:
4748                         value = ctx.r15;
4749                         break;
4750                 default:
4751                         g_assert_not_reached ();
4752                         reg = -1;
4753                 }
4754
4755                 if (value == -1)
4756                         return TRUE;
4757         }
4758
4759         return FALSE;
4760 }
4761
4762 guint32
4763 mono_arch_get_patch_offset (guint8 *code)
4764 {
4765         return 3;
4766 }
4767
4768 /**
4769  * mono_breakpoint_clean_code:
4770  *
4771  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
4772  * breakpoints in the original code, they are removed in the copy.
4773  *
4774  * Returns TRUE if no sw breakpoint was present.
4775  */
4776 gboolean
4777 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
4778 {
4779         int i;
4780         gboolean can_write = TRUE;
4781         /*
4782          * If method_start is non-NULL we need to perform bound checks, since we access memory
4783          * at code - offset we could go before the start of the method and end up in a different
4784          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
4785          * instead.
4786          */
4787         if (!method_start || code - offset >= method_start) {
4788                 memcpy (buf, code - offset, size);
4789         } else {
4790                 int diff = code - method_start;
4791                 memset (buf, 0, size);
4792                 memcpy (buf + offset - diff, method_start, diff + size - offset);
4793         }
4794         code -= offset;
4795         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
4796                 int idx = mono_breakpoint_info_index [i];
4797                 guint8 *ptr;
4798                 if (idx < 1)
4799                         continue;
4800                 ptr = mono_breakpoint_info [idx].address;
4801                 if (ptr >= code && ptr < code + size) {
4802                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
4803                         can_write = FALSE;
4804                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
4805                         buf [ptr - code] = saved_byte;
4806                 }
4807         }
4808         return can_write;
4809 }
4810
4811 gpointer
4812 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
4813 {
4814         guint8 buf [10];
4815         guint32 reg;
4816         gint32 disp;
4817         guint8 rex = 0;
4818
4819         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
4820         code = buf + 9;
4821
4822         *displacement = 0;
4823
4824         /* go to the start of the call instruction
4825          *
4826          * address_byte = (m << 6) | (o << 3) | reg
4827          * call opcode: 0xff address_byte displacement
4828          * 0xff m=1,o=2 imm8
4829          * 0xff m=2,o=2 imm32
4830          */
4831         code -= 7;
4832
4833         /*
4834          * A given byte sequence can match more than case here, so we have to be
4835          * really careful about the ordering of the cases. Longer sequences
4836          * come first.
4837          */
4838 #ifdef MONO_ARCH_HAVE_IMT
4839         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
4840                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
4841                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
4842                  * ff 50 fc                call   *0xfffffffc(%rax)
4843                  */
4844                 reg = amd64_modrm_rm (code [5]);
4845                 disp = (signed char)code [6];
4846                 /* R10 is clobbered by the IMT thunk code */
4847                 g_assert (reg != AMD64_R10);
4848         }
4849 #else
4850         if (0) {
4851         }
4852 #endif
4853         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4854                         /*
4855                          * This is a interface call
4856                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
4857                          * ff 10                  callq  *(%rax)
4858                          */
4859                 if (IS_REX (code [4]))
4860                         rex = code [4];
4861                 reg = amd64_modrm_rm (code [6]);
4862                 disp = 0;
4863                 /* R10 is clobbered by the IMT thunk code */
4864                 g_assert (reg != AMD64_R10);
4865         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
4866                 /* call OFFSET(%rip) */
4867                 disp = *(guint32*)(code + 3);
4868                 return (gpointer*)(code + disp + 7);
4869         }
4870         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
4871                 /* call *[reg+disp32] */
4872                 if (IS_REX (code [0]))
4873                         rex = code [0];
4874                 reg = amd64_modrm_rm (code [2]);
4875                 disp = *(gint32*)(code + 3);
4876                 /* R10 is clobbered by the IMT thunk code */
4877                 g_assert (reg != AMD64_R10);
4878         }
4879         else if (code [2] == 0xe8) {
4880                 /* call <ADDR> */
4881                 return NULL;
4882         }
4883         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
4884                 /* call *%reg */
4885                 return NULL;
4886         }
4887         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
4888                 /* call *[reg+disp8] */
4889                 if (IS_REX (code [3]))
4890                         rex = code [3];
4891                 reg = amd64_modrm_rm (code [5]);
4892                 disp = *(gint8*)(code + 6);
4893                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4894         }
4895         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4896                         /*
4897                          * This is a interface call: should check the above code can't catch it earlier
4898                          * 8b 40 30   mov    0x30(%eax),%eax
4899                          * ff 10      call   *(%eax)
4900                          */
4901                 if (IS_REX (code [4]))
4902                         rex = code [4];
4903                 reg = amd64_modrm_rm (code [6]);
4904                 disp = 0;
4905         }
4906         else
4907                 g_assert_not_reached ();
4908
4909         reg += amd64_rex_b (rex);
4910
4911         /* R11 is clobbered by the trampoline code */
4912         g_assert (reg != AMD64_R11);
4913
4914         *displacement = disp;
4915         return regs [reg];
4916 }
4917
4918 gpointer*
4919 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4920 {
4921         gpointer vt;
4922         int displacement;
4923         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
4924         if (!vt)
4925                 return NULL;
4926         return (gpointer*)((char*)vt + displacement);
4927 }
4928
4929 int
4930 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx)
4931 {
4932         int this_reg = AMD64_ARG_REG1;
4933
4934         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
4935                 CallInfo *cinfo = get_call_info (gsctx, NULL, sig, FALSE);
4936
4937                 if (cinfo->ret.storage != ArgValuetypeInReg)
4938                         this_reg = AMD64_ARG_REG2;
4939                 g_free (cinfo);
4940         }
4941
4942         return this_reg;
4943 }
4944
4945 gpointer
4946 mono_arch_get_this_arg_from_call (MonoMethodSignature *sig, gssize *regs, guint8 *code)
4947 {
4948         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, NULL)];
4949 }
4950
4951 #define MAX_ARCH_DELEGATE_PARAMS 10
4952
4953 gpointer
4954 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
4955 {
4956         guint8 *code, *start;
4957         int i;
4958
4959         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
4960                 return NULL;
4961
4962         /* FIXME: Support more cases */
4963         if (MONO_TYPE_ISSTRUCT (sig->ret))
4964                 return NULL;
4965
4966         if (has_target) {
4967                 static guint8* cached = NULL;
4968                 mono_mini_arch_lock ();
4969                 if (cached) {
4970                         mono_mini_arch_unlock ();
4971                         return cached;
4972                 }
4973
4974                 start = code = mono_global_codeman_reserve (64);
4975
4976                 /* Replace the this argument with the target */
4977                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
4978                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
4979                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
4980
4981                 g_assert ((code - start) < 64);
4982
4983                 cached = start;
4984                 mono_debug_add_delegate_trampoline (start, code - start);
4985                 mono_mini_arch_unlock ();
4986         } else {
4987                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
4988                 for (i = 0; i < sig->param_count; ++i)
4989                         if (!mono_is_regsize_var (sig->params [i]))
4990                                 return NULL;
4991                 if (sig->param_count > 4)
4992                         return NULL;
4993
4994                 mono_mini_arch_lock ();
4995                 code = cache [sig->param_count];
4996                 if (code) {
4997                         mono_mini_arch_unlock ();
4998                         return code;
4999                 }
5000
5001                 start = code = mono_global_codeman_reserve (64);
5002
5003                 if (sig->param_count == 0) {
5004                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5005                 } else {
5006                         /* We have to shift the arguments left */
5007                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5008                         for (i = 0; i < sig->param_count; ++i)
5009                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5010
5011                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5012                 }
5013                 g_assert ((code - start) < 64);
5014
5015                 cache [sig->param_count] = start;
5016
5017                 mono_debug_add_delegate_trampoline (start, code - start);
5018                 mono_mini_arch_unlock ();
5019         }
5020
5021         return start;
5022 }
5023
5024 /*
5025  * Support for fast access to the thread-local lmf structure using the GS
5026  * segment register on NPTL + kernel 2.6.x.
5027  */
5028
5029 static gboolean tls_offset_inited = FALSE;
5030
5031 void
5032 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5033 {
5034         if (!tls_offset_inited) {
5035                 tls_offset_inited = TRUE;
5036 #ifdef MONO_XEN_OPT
5037                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5038 #endif
5039                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5040                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5041                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5042                 thread_tls_offset = mono_thread_get_tls_offset ();
5043         }
5044 }
5045
5046 void
5047 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5048 {
5049 }
5050
5051 void
5052 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5053 {
5054         MonoCallInst *call = (MonoCallInst*)inst;
5055         CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
5056
5057         if (vt_reg != -1) {
5058                 MonoInst *vtarg;
5059
5060                 if (cinfo->ret.storage == ArgValuetypeInReg) {
5061                         /*
5062                          * The valuetype is in RAX:RDX after the call, need to be copied to
5063                          * the stack. Push the address here, so the call instruction can
5064                          * access it.
5065                          */
5066                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5067                         vtarg->sreg1 = vt_reg;
5068                         mono_bblock_add_inst (cfg->cbb, vtarg);
5069
5070                         /* Align stack */
5071                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5072                 }
5073                 else {
5074                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
5075                         vtarg->sreg1 = vt_reg;
5076                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
5077                         mono_bblock_add_inst (cfg->cbb, vtarg);
5078
5079                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
5080                 }
5081         }
5082
5083         /* add the this argument */
5084         if (this_reg != -1) {
5085                 MonoInst *this;
5086                 MONO_INST_NEW (cfg, this, OP_MOVE);
5087                 this->type = this_type;
5088                 this->sreg1 = this_reg;
5089                 this->dreg = mono_regstate_next_int (cfg->rs);
5090                 mono_bblock_add_inst (cfg->cbb, this);
5091
5092                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
5093         }
5094 }
5095
5096 #ifdef MONO_ARCH_HAVE_IMT
5097
5098 #define CMP_SIZE (6 + 1)
5099 #define CMP_REG_REG_SIZE (4 + 1)
5100 #define BR_SMALL_SIZE 2
5101 #define BR_LARGE_SIZE 6
5102 #define MOV_REG_IMM_SIZE 10
5103 #define MOV_REG_IMM_32BIT_SIZE 6
5104 #define JUMP_REG_SIZE (2 + 1)
5105
5106 static int
5107 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5108 {
5109         int i, distance = 0;
5110         for (i = start; i < target; ++i)
5111                 distance += imt_entries [i]->chunk_size;
5112         return distance;
5113 }
5114
5115 /*
5116  * LOCKING: called with the domain lock held
5117  */
5118 gpointer
5119 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count)
5120 {
5121         int i;
5122         int size = 0;
5123         guint8 *code, *start;
5124         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5125
5126         for (i = 0; i < count; ++i) {
5127                 MonoIMTCheckItem *item = imt_entries [i];
5128                 if (item->is_equals) {
5129                         if (item->check_target_idx) {
5130                                 if (!item->compare_done) {
5131                                         if (amd64_is_imm32 (item->method))
5132                                                 item->chunk_size += CMP_SIZE;
5133                                         else
5134                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5135                                 }
5136                                 if (vtable_is_32bit)
5137                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5138                                 else
5139                                         item->chunk_size += MOV_REG_IMM_SIZE;
5140                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5141                         } else {
5142                                 if (vtable_is_32bit)
5143                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5144                                 else
5145                                         item->chunk_size += MOV_REG_IMM_SIZE;
5146                                 item->chunk_size += JUMP_REG_SIZE;
5147                                 /* with assert below:
5148                                  * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5149                                  */
5150                         }
5151                 } else {
5152                         if (amd64_is_imm32 (item->method))
5153                                 item->chunk_size += CMP_SIZE;
5154                         else
5155                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5156                         item->chunk_size += BR_LARGE_SIZE;
5157                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5158                 }
5159                 size += item->chunk_size;
5160         }
5161         code = mono_code_manager_reserve (domain->code_mp, size);
5162         start = code;
5163         for (i = 0; i < count; ++i) {
5164                 MonoIMTCheckItem *item = imt_entries [i];
5165                 item->code_target = code;
5166                 if (item->is_equals) {
5167                         if (item->check_target_idx) {
5168                                 if (!item->compare_done) {
5169                                         if (amd64_is_imm32 (item->method))
5170                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5171                                         else {
5172                                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
5173                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5174                                         }
5175                                 }
5176                                 item->jmp_code = code;
5177                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5178                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->vtable_slot]));
5179                                 amd64_jump_membase (code, AMD64_R11, 0);
5180                         } else {
5181                                 /* enable the commented code to assert on wrong method */
5182 #if 0
5183                                 if (amd64_is_imm32 (item->method))
5184                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5185                                 else {
5186                                         amd64_mov_reg_imm (code, AMD64_R10, item->method);
5187                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5188                                 }
5189                                 item->jmp_code = code;
5190                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5191                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->vtable_slot]));
5192                                 amd64_jump_membase (code, AMD64_R11, 0);
5193                                 amd64_patch (item->jmp_code, code);
5194                                 amd64_breakpoint (code);
5195                                 item->jmp_code = NULL;
5196 #else
5197                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->vtable_slot]));
5198                                 amd64_jump_membase (code, AMD64_R11, 0);
5199 #endif
5200                         }
5201                 } else {
5202                         if (amd64_is_imm32 (item->method))
5203                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5204                         else {
5205                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
5206                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5207                         }
5208                         item->jmp_code = code;
5209                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5210                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5211                         else
5212                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5213                 }
5214                 g_assert (code - item->code_target <= item->chunk_size);
5215         }
5216         /* patch the branches to get to the target items */
5217         for (i = 0; i < count; ++i) {
5218                 MonoIMTCheckItem *item = imt_entries [i];
5219                 if (item->jmp_code) {
5220                         if (item->check_target_idx) {
5221                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5222                         }
5223                 }
5224         }
5225
5226         mono_stats.imt_thunks_size += code - start;
5227         g_assert (code - start <= size);
5228
5229         return start;
5230 }
5231
5232 MonoMethod*
5233 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
5234 {
5235         /*
5236          * R11 is clobbered by the trampoline code, so we have to retrieve the method
5237          * from the code.
5238          * 41 bb c0 f7 89 00     mov    $0x89f7c0,%r11d
5239          * ff 90 68 ff ff ff     callq  *0xffffffffffffff68(%rax)
5240          */
5241         /* Similar to get_vcall_slot_addr () */
5242
5243         /* Find the start of the call instruction */
5244         code -= 7;
5245         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5246                 /* IMT-based interface calls
5247                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11
5248                  * ff 50 fc                call   *0xfffffffc(%rax)
5249                  */
5250                 code += 4;
5251         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5252                 /* call *[reg+disp32] */
5253                 code += 1;
5254         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5255                 /* call *[reg+disp8] */
5256                 code += 4;
5257         } else
5258                 g_assert_not_reached ();
5259
5260         /* Find the start of the mov instruction */
5261         code -= 10;
5262         if (code [0] == 0x49 && code [1] == 0xbb) {
5263                 return (MonoMethod*)*(gssize*)(code + 2);
5264         } else if (code [3] == 0x4d && code [4] == 0x8b && code [5] == 0x1d) {
5265                 /* mov    <OFFSET>(%rip),%r11 */
5266                 return (MonoMethod*)*(gssize*)(code + 10 + *(guint32*)(code + 6));
5267         } else if (code [4] == 0x41 && code [5] == 0xbb) {
5268                 return (MonoMethod*)(gssize)*(guint32*)(code + 6);
5269         } else {
5270                 int i;
5271
5272                 printf ("Unknown call sequence: ");
5273                 for (i = -10; i < 20; ++i)
5274                         printf ("%x ", code [i]);
5275                 g_assert_not_reached ();
5276                 return NULL;
5277         }
5278 }
5279
5280 MonoObject*
5281 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
5282 {
5283         return regs [mono_arch_get_this_arg_reg (mono_method_signature (method), gsctx)];
5284 }
5285 #endif
5286
5287 MonoRuntimeGenericContext*
5288 mono_arch_find_static_call_rgctx (gpointer *regs, guint8 *code)
5289 {
5290         return (MonoRuntimeGenericContext*) regs [MONO_ARCH_RGCTX_REG];
5291 }
5292
5293 MonoInst*
5294 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5295 {
5296         MonoInst *ins = NULL;
5297
5298         if (cmethod->klass == mono_defaults.math_class) {
5299                 if (strcmp (cmethod->name, "Sin") == 0) {
5300                         MONO_INST_NEW (cfg, ins, OP_SIN);
5301                         ins->inst_i0 = args [0];
5302                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5303                         MONO_INST_NEW (cfg, ins, OP_COS);
5304                         ins->inst_i0 = args [0];
5305                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5306                         MONO_INST_NEW (cfg, ins, OP_SQRT);
5307                         ins->inst_i0 = args [0];
5308                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5309                         MONO_INST_NEW (cfg, ins, OP_ABS);
5310                         ins->inst_i0 = args [0];
5311                 }
5312
5313                 if (cfg->opt & MONO_OPT_CMOV) {
5314                         int opcode = 0;
5315
5316                         if (strcmp (cmethod->name, "Min") == 0) {
5317                                 if (fsig->params [0]->type == MONO_TYPE_I4)
5318                                         opcode = OP_IMIN;
5319                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
5320                                         opcode = OP_LMIN;
5321                         } else if (strcmp (cmethod->name, "Max") == 0) {
5322                                 if (fsig->params [0]->type == MONO_TYPE_I4)
5323                                         opcode = OP_IMAX;
5324                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
5325                                         opcode = OP_LMAX;
5326                         }
5327
5328                         if (opcode) {
5329                                 MONO_INST_NEW (cfg, ins, opcode);
5330                                 ins->inst_i0 = args [0];
5331                                 ins->inst_i1 = args [1];
5332                         }
5333                 }
5334
5335 #if 0
5336                 /* OP_FREM is not IEEE compatible */
5337                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5338                         MONO_INST_NEW (cfg, ins, OP_FREM);
5339                         ins->inst_i0 = args [0];
5340                         ins->inst_i1 = args [1];
5341                 }
5342 #endif
5343         } else if(cmethod->klass->image == mono_defaults.corlib &&
5344                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
5345                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
5346                 /*
5347                  * Can't implement CompareExchange methods this way since they have
5348                  * three arguments.
5349                  */
5350         }
5351
5352         return ins;
5353 }
5354
5355 gboolean
5356 mono_arch_print_tree (MonoInst *tree, int arity)
5357 {
5358         return 0;
5359 }
5360
5361 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5362 {
5363         MonoInst* ins;
5364
5365         if (appdomain_tls_offset == -1)
5366                 return NULL;
5367
5368         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5369         ins->inst_offset = appdomain_tls_offset;
5370         return ins;
5371 }
5372
5373 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5374 {
5375         MonoInst* ins;
5376
5377         if (thread_tls_offset == -1)
5378                 return NULL;
5379
5380         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5381         ins->inst_offset = thread_tls_offset;
5382         return ins;
5383 }
5384
5385 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
5386
5387 gpointer
5388 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5389 {
5390         switch (reg) {
5391         case AMD64_RCX: return (gpointer)ctx->rcx;
5392         case AMD64_RDX: return (gpointer)ctx->rdx;
5393         case AMD64_RBX: return (gpointer)ctx->rbx;
5394         case AMD64_RBP: return (gpointer)ctx->rbp;
5395         case AMD64_RSP: return (gpointer)ctx->rsp;
5396         default:
5397                 if (reg < 8)
5398                         return _CTX_REG (ctx, rax, reg);
5399                 else if (reg >= 12)
5400                         return _CTX_REG (ctx, r12, reg - 12);
5401                 else
5402                         g_assert_not_reached ();
5403         }
5404 }