mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 /*
  72  * The code generated for sequence points reads from this location, which is
  73  * made read-only when single stepping is enabled.
  74  */
  75 static gpointer ss_trigger_page;
  76
  77 /* Enabled breakpoints read from this trigger page */
  78 static gpointer bp_trigger_page;
  79
  80 /* The size of the breakpoint sequence */
  81 static int breakpoint_size;
  82
  83 /* The size of the breakpoint instruction causing the actual fault */
  84 static int breakpoint_fault_size;
  85
  86 /* The size of the single step instruction causing the actual fault */
  87 static int single_step_fault_size;
  88
  89 /* The single step trampoline */
  90 static gpointer ss_trampoline;
  91
  92 /* Offset between fp and the first argument in the callee */
  93 #define ARGS_OFFSET 16
  94 #define GP_SCRATCH_REG AMD64_R11
  95
  96 /*
  97  * AMD64 register usage:
  98  * - callee saved registers are used for global register allocation
  99  * - %r11 is used for materializing 64 bit constants in opcodes
 100  * - the rest is used for local allocation
 101  */
 102
 103 /*
 104  * Floating point comparison results:
 105  *                  ZF PF CF
 106  * A > B            0  0  0
 107  * A < B            0  0  1
 108  * A = B            1  0  0
 109  * A > B            0  0  0
 110  * UNORDERED        1  1  1
 111  */
 112
 113 const char*
 114 mono_arch_regname (int reg)
 115 {
 116         switch (reg) {
 117         case AMD64_RAX: return "%rax";
 118         case AMD64_RBX: return "%rbx";
 119         case AMD64_RCX: return "%rcx";
 120         case AMD64_RDX: return "%rdx";
 121         case AMD64_RSP: return "%rsp";
 122         case AMD64_RBP: return "%rbp";
 123         case AMD64_RDI: return "%rdi";
 124         case AMD64_RSI: return "%rsi";
 125         case AMD64_R8: return "%r8";
 126         case AMD64_R9: return "%r9";
 127         case AMD64_R10: return "%r10";
 128         case AMD64_R11: return "%r11";
 129         case AMD64_R12: return "%r12";
 130         case AMD64_R13: return "%r13";
 131         case AMD64_R14: return "%r14";
 132         case AMD64_R15: return "%r15";
 133         }
 134         return "unknown";
 135 }
 136
 137 static const char * packed_xmmregs [] = {
 138         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 139         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 140 };
 141
 142 static const char * single_xmmregs [] = {
 143         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 144         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 145 };
 146
 147 const char*
 148 mono_arch_fregname (int reg)
 149 {
 150         if (reg < AMD64_XMM_NREG)
 151                 return single_xmmregs [reg];
 152         else
 153                 return "unknown";
 154 }
 155
 156 const char *
 157 mono_arch_xregname (int reg)
 158 {
 159         if (reg < AMD64_XMM_NREG)
 160                 return packed_xmmregs [reg];
 161         else
 162                 return "unknown";
 163 }
 164
 165 static gboolean
 166 debug_omit_fp (void)
 167 {
 168 #if 0
 169         return mono_debug_count ();
 170 #else
 171         return TRUE;
 172 #endif
 173 }
 174
 175 static inline gboolean
 176 amd64_is_near_call (guint8 *code)
 177 {
 178         /* Skip REX */
 179         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 180                 code += 1;
 181
 182         return code [0] == 0xe8;
 183 }
 184
 185 static inline gboolean
 186 amd64_use_imm32 (gint64 val)
 187 {
 188         if (mini_get_debug_options()->single_imm_size)
 189                 return FALSE;
 190
 191         return amd64_is_imm32 (val);
 192 }
 193
 194 #ifdef __native_client_codegen__
 195
 196 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 197 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 198 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 199 /* We only want to force bundle alignment for the top level instruction,    */
 200 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 201 static MonoNativeTlsKey nacl_instruction_depth;
 202
 203 static MonoNativeTlsKey nacl_rex_tag;
 204 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 205
 206 void
 207 amd64_nacl_clear_legacy_prefix_tag ()
 208 {
 209         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 210 }
 211
 212 void
 213 amd64_nacl_tag_legacy_prefix (guint8* code)
 214 {
 215         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 216                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 217 }
 218
 219 void
 220 amd64_nacl_tag_rex (guint8* code)
 221 {
 222         mono_native_tls_set_value (nacl_rex_tag, code);
 223 }
 224
 225 guint8*
 226 amd64_nacl_get_legacy_prefix_tag ()
 227 {
 228         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 229 }
 230
 231 guint8*
 232 amd64_nacl_get_rex_tag ()
 233 {
 234         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 235 }
 236
 237 /* Increment the instruction "depth" described above */
 238 void
 239 amd64_nacl_instruction_pre ()
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth++;
 243         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 244 }
 245
 246 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 247 /* alignment if depth == 0 (top level instruction)                          */
 248 /* IN: start, end    pointers to instruction beginning and end              */
 249 /* OUT: start, end   pointers to beginning and end after possible alignment */
 250 /* GLOBALS: nacl_instruction_depth     defined above                        */
 251 void
 252 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 253 {
 254         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 255         depth--;
 256         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 257
 258         g_assert ( depth >= 0 );
 259         if (depth == 0) {
 260                 uintptr_t space_in_block;
 261                 uintptr_t instlen;
 262                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 263                 /* if legacy prefix is present, and if it was emitted before */
 264                 /* the start of the instruction sequence, adjust the start   */
 265                 if (prefix != NULL && prefix < *start) {
 266                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 267                         *start = prefix;
 268                 }
 269                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 270                 instlen = (uintptr_t)(*end - *start);
 271                 /* Only check for instructions which are less than        */
 272                 /* kNaClAlignment. The only instructions that should ever */
 273                 /* be that long are call sequences, which are already     */
 274                 /* padded out to align the return to the next bundle.     */
 275                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 276                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 277                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 278                         const size_t length = (size_t)((*end)-(*start));
 279                         g_assert (length < MAX_NACL_INST_LENGTH);
 280
 281                         memcpy (copy_of_instruction, *start, length);
 282                         *start = mono_arch_nacl_pad (*start, space_in_block);
 283                         memcpy (*start, copy_of_instruction, length);
 284                         *end = *start + length;
 285                 }
 286                 amd64_nacl_clear_legacy_prefix_tag ();
 287                 amd64_nacl_tag_rex (NULL);
 288         }
 289 }
 290
 291 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 292 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 293 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 294 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 295 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 296 /* IN:      code                                                            */
 297 /*             pointer to current instruction stream (in the                */
 298 /*             middle of an instruction, after opcode is emitted)           */
 299 /*          basereg/offset/dreg                                             */
 300 /*             operands of normal membase address                           */
 301 /* OUT:     code                                                            */
 302 /*             pointer to the end of the membase/memindex emit              */
 303 /* GLOBALS: nacl_rex_tag                                                    */
 304 /*             position in instruction stream that rex prefix was emitted   */
 305 /*          nacl_legacy_prefix_tag                                          */
 306 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 307 void
 308 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 309 {
 310         gint8 true_basereg = basereg;
 311
 312         /* Cache these values, they might change  */
 313         /* as new instructions are emitted below. */
 314         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 315         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 316
 317         /* 'basereg' is given masked to 0x7 at this point, so check */
 318         /* the rex prefix to see if this is an extended register.   */
 319         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 320                 true_basereg |= 0x8;
 321         }
 322
 323 #define X86_LEA_OPCODE (0x8D)
 324
 325         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 326                 guint8* old_instruction_start;
 327
 328                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 329                 /* 32-bits of the old base register (new index register)     */
 330                 guint8 buf[32];
 331                 guint8* buf_ptr = buf;
 332                 size_t insert_len;
 333
 334                 g_assert (rex_tag != NULL);
 335
 336                 if (IS_REX(*rex_tag)) {
 337                         /* The old rex.B should be the new rex.X */
 338                         if (*rex_tag & AMD64_REX_B) {
 339                                 *rex_tag |= AMD64_REX_X;
 340                         }
 341                         /* Since our new base is %r15 set rex.B */
 342                         *rex_tag |= AMD64_REX_B;
 343                 } else {
 344                         /* Shift the instruction by one byte  */
 345                         /* so we can insert a rex prefix      */
 346                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 347                         *code += 1;
 348                         /* New rex prefix only needs rex.B for %r15 base */
 349                         *rex_tag = AMD64_REX(AMD64_REX_B);
 350                 }
 351
 352                 if (legacy_prefix_tag) {
 353                         old_instruction_start = legacy_prefix_tag;
 354                 } else {
 355                         old_instruction_start = rex_tag;
 356                 }
 357
 358                 /* Clears the upper 32-bits of the previous base register */
 359                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 360                 insert_len = buf_ptr - buf;
 361
 362                 /* Move the old instruction forward to make */
 363                 /* room for 'mov' stored in 'buf_ptr'       */
 364                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 365                 *code += insert_len;
 366                 memcpy (old_instruction_start, buf, insert_len);
 367
 368                 /* Sandboxed replacement for the normal membase_emit */
 369                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 370
 371         } else {
 372                 /* Normal default behavior, emit membase memory location */
 373                 x86_membase_emit_body (*code, dreg, basereg, offset);
 374         }
 375 }
 376
 377
 378 static inline unsigned char*
 379 amd64_skip_nops (unsigned char* code)
 380 {
 381         guint8 in_nop;
 382         do {
 383                 in_nop = 0;
 384                 if (   code[0] == 0x90) {
 385                         in_nop = 1;
 386                         code += 1;
 387                 }
 388                 if (   code[0] == 0x66 && code[1] == 0x90) {
 389                         in_nop = 1;
 390                         code += 2;
 391                 }
 392                 if (code[0] == 0x0f && code[1] == 0x1f
 393                  && code[2] == 0x00) {
 394                         in_nop = 1;
 395                         code += 3;
 396                 }
 397                 if (code[0] == 0x0f && code[1] == 0x1f
 398                  && code[2] == 0x40 && code[3] == 0x00) {
 399                         in_nop = 1;
 400                         code += 4;
 401                 }
 402                 if (code[0] == 0x0f && code[1] == 0x1f
 403                  && code[2] == 0x44 && code[3] == 0x00
 404                  && code[4] == 0x00) {
 405                         in_nop = 1;
 406                         code += 5;
 407                 }
 408                 if (code[0] == 0x66 && code[1] == 0x0f
 409                  && code[2] == 0x1f && code[3] == 0x44
 410                  && code[4] == 0x00 && code[5] == 0x00) {
 411                         in_nop = 1;
 412                         code += 6;
 413                 }
 414                 if (code[0] == 0x0f && code[1] == 0x1f
 415                  && code[2] == 0x80 && code[3] == 0x00
 416                  && code[4] == 0x00 && code[5] == 0x00
 417                  && code[6] == 0x00) {
 418                         in_nop = 1;
 419                         code += 7;
 420                 }
 421                 if (code[0] == 0x0f && code[1] == 0x1f
 422                  && code[2] == 0x84 && code[3] == 0x00
 423                  && code[4] == 0x00 && code[5] == 0x00
 424                  && code[6] == 0x00 && code[7] == 0x00) {
 425                         in_nop = 1;
 426                         code += 8;
 427                 }
 428         } while ( in_nop );
 429         return code;
 430 }
 431
 432 guint8*
 433 mono_arch_nacl_skip_nops (guint8* code)
 434 {
 435   return amd64_skip_nops(code);
 436 }
 437
 438 #endif /*__native_client_codegen__*/
 439
 440 static inline void
 441 amd64_patch (unsigned char* code, gpointer target)
 442 {
 443         guint8 rex = 0;
 444
 445 #ifdef __native_client_codegen__
 446         code = amd64_skip_nops (code);
 447 #endif
 448 #if defined(__native_client_codegen__) && defined(__native_client__)
 449         if (nacl_is_code_address (code)) {
 450                 /* For tail calls, code is patched after being installed */
 451                 /* but not through the normal "patch callsite" method.   */
 452                 unsigned char buf[kNaClAlignment];
 453                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 454                 int ret;
 455                 memcpy (buf, aligned_code, kNaClAlignment);
 456                 /* Patch a temp buffer of bundle size, */
 457                 /* then install to actual location.    */
 458                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 459                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 460                 g_assert (ret == 0);
 461                 return;
 462         }
 463         target = nacl_modify_patch_target (target);
 464 #endif
 465
 466         /* Skip REX */
 467         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 468                 rex = code [0];
 469                 code += 1;
 470         }
 471
 472         if ((code [0] & 0xf8) == 0xb8) {
 473                 /* amd64_set_reg_template */
 474                 *(guint64*)(code + 1) = (guint64)target;
 475         }
 476         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 477                 /* mov 0(%rip), %dreg */
 478                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 479         }
 480         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 481                 /* call *<OFFSET>(%rip) */
 482                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 483         }
 484         else if (code [0] == 0xe8) {
 485                 /* call <DISP> */
 486                 gint64 disp = (guint8*)target - (guint8*)code;
 487                 g_assert (amd64_is_imm32 (disp));
 488                 x86_patch (code, (unsigned char*)target);
 489         }
 490         else
 491                 x86_patch (code, (unsigned char*)target);
 492 }
 493
 494 void
 495 mono_amd64_patch (unsigned char* code, gpointer target)
 496 {
 497         amd64_patch (code, target);
 498 }
 499
 500 typedef enum {
 501         ArgInIReg,
 502         ArgInFloatSSEReg,
 503         ArgInDoubleSSEReg,
 504         ArgOnStack,
 505         ArgValuetypeInReg,
 506         ArgValuetypeAddrInIReg,
 507         ArgNone /* only in pair_storage */
 508 } ArgStorage;
 509
 510 typedef struct {
 511         gint16 offset;
 512         gint8  reg;
 513         ArgStorage storage;
 514
 515         /* Only if storage == ArgValuetypeInReg */
 516         ArgStorage pair_storage [2];
 517         gint8 pair_regs [2];
 518         /* The size of each pair */
 519         int pair_size [2];
 520         int nregs;
 521 } ArgInfo;
 522
 523 typedef struct {
 524         int nargs;
 525         guint32 stack_usage;
 526         guint32 reg_usage;
 527         guint32 freg_usage;
 528         gboolean need_stack_align;
 529         gboolean vtype_retaddr;
 530         /* The index of the vret arg in the argument list */
 531         int vret_arg_index;
 532         ArgInfo ret;
 533         ArgInfo sig_cookie;
 534         ArgInfo args [1];
 535 } CallInfo;
 536
 537 #define DEBUG(a) if (cfg->verbose_level > 1) a
 538
 539 #ifdef TARGET_WIN32
 540 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 541
 542 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 543 #else
 544 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 545
 546  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 547 #endif
 548
 549 static void inline
 550 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 551 {
 552     ainfo->offset = *stack_size;
 553
 554     if (*gr >= PARAM_REGS) {
 555                 ainfo->storage = ArgOnStack;
 556                 /* Since the same stack slot size is used for all arg */
 557                 /*  types, it needs to be big enough to hold them all */
 558                 (*stack_size) += sizeof(mgreg_t);
 559     }
 560     else {
 561                 ainfo->storage = ArgInIReg;
 562                 ainfo->reg = param_regs [*gr];
 563                 (*gr) ++;
 564     }
 565 }
 566
 567 #ifdef TARGET_WIN32
 568 #define FLOAT_PARAM_REGS 4
 569 #else
 570 #define FLOAT_PARAM_REGS 8
 571 #endif
 572
 573 static void inline
 574 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 575 {
 576     ainfo->offset = *stack_size;
 577
 578     if (*gr >= FLOAT_PARAM_REGS) {
 579                 ainfo->storage = ArgOnStack;
 580                 /* Since the same stack slot size is used for both float */
 581                 /*  types, it needs to be big enough to hold them both */
 582                 (*stack_size) += sizeof(mgreg_t);
 583     }
 584     else {
 585                 /* A double register */
 586                 if (is_double)
 587                         ainfo->storage = ArgInDoubleSSEReg;
 588                 else
 589                         ainfo->storage = ArgInFloatSSEReg;
 590                 ainfo->reg = *gr;
 591                 (*gr) += 1;
 592     }
 593 }
 594
 595 typedef enum ArgumentClass {
 596         ARG_CLASS_NO_CLASS,
 597         ARG_CLASS_MEMORY,
 598         ARG_CLASS_INTEGER,
 599         ARG_CLASS_SSE
 600 } ArgumentClass;
 601
 602 static ArgumentClass
 603 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 604 {
 605         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 606         MonoType *ptype;
 607
 608         ptype = mini_get_underlying_type (type);
 609         switch (ptype->type) {
 610         case MONO_TYPE_I1:
 611         case MONO_TYPE_U1:
 612         case MONO_TYPE_I2:
 613         case MONO_TYPE_U2:
 614         case MONO_TYPE_I4:
 615         case MONO_TYPE_U4:
 616         case MONO_TYPE_I:
 617         case MONO_TYPE_U:
 618         case MONO_TYPE_STRING:
 619         case MONO_TYPE_OBJECT:
 620         case MONO_TYPE_CLASS:
 621         case MONO_TYPE_SZARRAY:
 622         case MONO_TYPE_PTR:
 623         case MONO_TYPE_FNPTR:
 624         case MONO_TYPE_ARRAY:
 625         case MONO_TYPE_I8:
 626         case MONO_TYPE_U8:
 627                 class2 = ARG_CLASS_INTEGER;
 628                 break;
 629         case MONO_TYPE_R4:
 630         case MONO_TYPE_R8:
 631 #ifdef TARGET_WIN32
 632                 class2 = ARG_CLASS_INTEGER;
 633 #else
 634                 class2 = ARG_CLASS_SSE;
 635 #endif
 636                 break;
 637
 638         case MONO_TYPE_TYPEDBYREF:
 639                 g_assert_not_reached ();
 640
 641         case MONO_TYPE_GENERICINST:
 642                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 643                         class2 = ARG_CLASS_INTEGER;
 644                         break;
 645                 }
 646                 /* fall through */
 647         case MONO_TYPE_VALUETYPE: {
 648                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 649                 int i;
 650
 651                 for (i = 0; i < info->num_fields; ++i) {
 652                         class2 = class1;
 653                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 654                 }
 655                 break;
 656         }
 657         default:
 658                 g_assert_not_reached ();
 659         }
 660
 661         /* Merge */
 662         if (class1 == class2)
 663                 ;
 664         else if (class1 == ARG_CLASS_NO_CLASS)
 665                 class1 = class2;
 666         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 667                 class1 = ARG_CLASS_MEMORY;
 668         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 669                 class1 = ARG_CLASS_INTEGER;
 670         else
 671                 class1 = ARG_CLASS_SSE;
 672
 673         return class1;
 674 }
 675 #ifdef __native_client_codegen__
 676
 677 /* Default alignment for Native Client is 32-byte. */
 678 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 679
 680 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 681 /* Check that alignment doesn't cross an alignment boundary.             */
 682 guint8*
 683 mono_arch_nacl_pad(guint8 *code, int pad)
 684 {
 685         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 686
 687         if (pad == 0) return code;
 688         /* assertion: alignment cannot cross a block boundary */
 689         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 690                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 691         while (pad >= kMaxPadding) {
 692                 amd64_padding (code, kMaxPadding);
 693                 pad -= kMaxPadding;
 694         }
 695         if (pad != 0) amd64_padding (code, pad);
 696         return code;
 697 }
 698 #endif
 699
 700 static int
 701 count_fields_nested (MonoClass *klass)
 702 {
 703         MonoMarshalType *info;
 704         int i, count;
 705
 706         info = mono_marshal_load_type_info (klass);
 707         g_assert(info);
 708         count = 0;
 709         for (i = 0; i < info->num_fields; ++i) {
 710                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 711                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 712                 else
 713                         count ++;
 714         }
 715         return count;
 716 }
 717
 718 static int
 719 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 720 {
 721         MonoMarshalType *info;
 722         int i;
 723
 724         info = mono_marshal_load_type_info (klass);
 725         g_assert(info);
 726         for (i = 0; i < info->num_fields; ++i) {
 727                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 728                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 729                 } else {
 730                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 731                         fields [index].offset += offset;
 732                         index ++;
 733                 }
 734         }
 735         return index;
 736 }
 737
 738 static void
 739 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 740                            gboolean is_return,
 741                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 742 {
 743         guint32 size, quad, nquads, i, nfields;
 744         /* Keep track of the size used in each quad so we can */
 745         /* use the right size when copying args/return vars.  */
 746         guint32 quadsize [2] = {8, 8};
 747         ArgumentClass args [2];
 748         MonoMarshalType *info = NULL;
 749         MonoMarshalField *fields = NULL;
 750         MonoClass *klass;
 751         gboolean pass_on_stack = FALSE;
 752
 753         klass = mono_class_from_mono_type (type);
 754         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 755 #ifndef TARGET_WIN32
 756         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 757                 /* We pass and return vtypes of size 8 in a register */
 758         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 759                 pass_on_stack = TRUE;
 760         }
 761 #else
 762         if (!sig->pinvoke) {
 763                 pass_on_stack = TRUE;
 764         }
 765 #endif
 766
 767         /* If this struct can't be split up naturally into 8-byte */
 768         /* chunks (registers), pass it on the stack.              */
 769         if (sig->pinvoke && !pass_on_stack) {
 770                 guint32 align;
 771                 guint32 field_size;
 772
 773                 info = mono_marshal_load_type_info (klass);
 774                 g_assert (info);
 775
 776                 /*
 777                  * Collect field information recursively to be able to
 778                  * handle nested structures.
 779                  */
 780                 nfields = count_fields_nested (klass);
 781                 fields = g_new0 (MonoMarshalField, nfields);
 782                 collect_field_info_nested (klass, fields, 0, 0);
 783
 784                 for (i = 0; i < nfields; ++i) {
 785                         field_size = mono_marshal_type_size (fields [i].field->type,
 786                                                            fields [i].mspec,
 787                                                            &align, TRUE, klass->unicode);
 788                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 789                                 pass_on_stack = TRUE;
 790                                 break;
 791                         }
 792                 }
 793         }
 794
 795 #ifndef TARGET_WIN32
 796         if (size == 0) {
 797                 ainfo->storage = ArgValuetypeInReg;
 798                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 799                 return;
 800         }
 801 #endif
 802
 803         if (pass_on_stack) {
 804                 /* Allways pass in memory */
 805                 ainfo->offset = *stack_size;
 806                 *stack_size += ALIGN_TO (size, 8);
 807                 ainfo->storage = ArgOnStack;
 808
 809                 g_free (fields);
 810                 return;
 811         }
 812
 813         /* FIXME: Handle structs smaller than 8 bytes */
 814         //if ((size % 8) != 0)
 815         //      NOT_IMPLEMENTED;
 816
 817         if (size > 8)
 818                 nquads = 2;
 819         else
 820                 nquads = 1;
 821
 822         if (!sig->pinvoke) {
 823                 int n = mono_class_value_size (klass, NULL);
 824
 825                 quadsize [0] = n >= 8 ? 8 : n;
 826                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 827
 828                 /* Always pass in 1 or 2 integer registers */
 829                 args [0] = ARG_CLASS_INTEGER;
 830                 args [1] = ARG_CLASS_INTEGER;
 831                 /* Only the simplest cases are supported */
 832                 if (is_return && nquads != 1) {
 833                         args [0] = ARG_CLASS_MEMORY;
 834                         args [1] = ARG_CLASS_MEMORY;
 835                 }
 836         } else {
 837                 /*
 838                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 839                  * The X87 and SSEUP stuff is left out since there are no such types in
 840                  * the CLR.
 841                  */
 842                 g_assert (info);
 843
 844                 if (!fields) {
 845                         ainfo->storage = ArgValuetypeInReg;
 846                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 847                         return;
 848                 }
 849
 850 #ifndef TARGET_WIN32
 851                 if (info->native_size > 16) {
 852                         ainfo->offset = *stack_size;
 853                         *stack_size += ALIGN_TO (info->native_size, 8);
 854                         ainfo->storage = ArgOnStack;
 855
 856                         g_free (fields);
 857                         return;
 858                 }
 859 #else
 860                 switch (info->native_size) {
 861                 case 1: case 2: case 4: case 8:
 862                         break;
 863                 default:
 864                         if (is_return) {
 865                                 ainfo->storage = ArgOnStack;
 866                                 ainfo->offset = *stack_size;
 867                                 *stack_size += ALIGN_TO (info->native_size, 8);
 868                         }
 869                         else {
 870                                 ainfo->storage = ArgValuetypeAddrInIReg;
 871
 872                                 if (*gr < PARAM_REGS) {
 873                                         ainfo->pair_storage [0] = ArgInIReg;
 874                                         ainfo->pair_regs [0] = param_regs [*gr];
 875                                         (*gr) ++;
 876                                 }
 877                                 else {
 878                                         ainfo->pair_storage [0] = ArgOnStack;
 879                                         ainfo->offset = *stack_size;
 880                                         *stack_size += 8;
 881                                 }
 882                         }
 883
 884                         g_free (fields);
 885                         return;
 886                 }
 887 #endif
 888
 889                 args [0] = ARG_CLASS_NO_CLASS;
 890                 args [1] = ARG_CLASS_NO_CLASS;
 891                 for (quad = 0; quad < nquads; ++quad) {
 892                         int size;
 893                         guint32 align;
 894                         ArgumentClass class1;
 895
 896                         if (nfields == 0)
 897                                 class1 = ARG_CLASS_MEMORY;
 898                         else
 899                                 class1 = ARG_CLASS_NO_CLASS;
 900                         for (i = 0; i < nfields; ++i) {
 901                                 size = mono_marshal_type_size (fields [i].field->type,
 902                                                                                            fields [i].mspec,
 903                                                                                            &align, TRUE, klass->unicode);
 904                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 905                                         /* Unaligned field */
 906                                         NOT_IMPLEMENTED;
 907                                 }
 908
 909                                 /* Skip fields in other quad */
 910                                 if ((quad == 0) && (fields [i].offset >= 8))
 911                                         continue;
 912                                 if ((quad == 1) && (fields [i].offset < 8))
 913                                         continue;
 914
 915                                 /* How far into this quad this data extends.*/
 916                                 /* (8 is size of quad) */
 917                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 918
 919                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 920                         }
 921                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 922                         args [quad] = class1;
 923                 }
 924         }
 925
 926         g_free (fields);
 927
 928         /* Post merger cleanup */
 929         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 930                 args [0] = args [1] = ARG_CLASS_MEMORY;
 931
 932         /* Allocate registers */
 933         {
 934                 int orig_gr = *gr;
 935                 int orig_fr = *fr;
 936
 937                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 938                         quadsize [0] ++;
 939                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 940                         quadsize [1] ++;
 941
 942                 ainfo->storage = ArgValuetypeInReg;
 943                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 944                 g_assert (quadsize [0] <= 8);
 945                 g_assert (quadsize [1] <= 8);
 946                 ainfo->pair_size [0] = quadsize [0];
 947                 ainfo->pair_size [1] = quadsize [1];
 948                 ainfo->nregs = nquads;
 949                 for (quad = 0; quad < nquads; ++quad) {
 950                         switch (args [quad]) {
 951                         case ARG_CLASS_INTEGER:
 952                                 if (*gr >= PARAM_REGS)
 953                                         args [quad] = ARG_CLASS_MEMORY;
 954                                 else {
 955                                         ainfo->pair_storage [quad] = ArgInIReg;
 956                                         if (is_return)
 957                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 958                                         else
 959                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 960                                         (*gr) ++;
 961                                 }
 962                                 break;
 963                         case ARG_CLASS_SSE:
 964                                 if (*fr >= FLOAT_PARAM_REGS)
 965                                         args [quad] = ARG_CLASS_MEMORY;
 966                                 else {
 967                                         if (quadsize[quad] <= 4)
 968                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 969                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 970                                         ainfo->pair_regs [quad] = *fr;
 971                                         (*fr) ++;
 972                                 }
 973                                 break;
 974                         case ARG_CLASS_MEMORY:
 975                                 break;
 976                         default:
 977                                 g_assert_not_reached ();
 978                         }
 979                 }
 980
 981                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 982                         /* Revert possible register assignments */
 983                         *gr = orig_gr;
 984                         *fr = orig_fr;
 985
 986                         ainfo->offset = *stack_size;
 987                         if (sig->pinvoke)
 988                                 *stack_size += ALIGN_TO (info->native_size, 8);
 989                         else
 990                                 *stack_size += nquads * sizeof(mgreg_t);
 991                         ainfo->storage = ArgOnStack;
 992                 }
 993         }
 994 }
 995
 996 /*
 997  * get_call_info:
 998  *
 999  *  Obtain information about a call according to the calling convention.
1000  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1001  * Draft Version 0.23" document for more information.
1002  */
1003 static CallInfo*
1004 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1005 {
1006         guint32 i, gr, fr, pstart;
1007         MonoType *ret_type;
1008         int n = sig->hasthis + sig->param_count;
1009         guint32 stack_size = 0;
1010         CallInfo *cinfo;
1011         gboolean is_pinvoke = sig->pinvoke;
1012
1013         if (mp)
1014                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1015         else
1016                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1017
1018         cinfo->nargs = n;
1019
1020         gr = 0;
1021         fr = 0;
1022
1023 #ifdef TARGET_WIN32
1024         /* Reserve space where the callee can save the argument registers */
1025         stack_size = 4 * sizeof (mgreg_t);
1026 #endif
1027
1028         /* return value */
1029         ret_type = mini_get_underlying_type (sig->ret);
1030         switch (ret_type->type) {
1031         case MONO_TYPE_I1:
1032         case MONO_TYPE_U1:
1033         case MONO_TYPE_I2:
1034         case MONO_TYPE_U2:
1035         case MONO_TYPE_I4:
1036         case MONO_TYPE_U4:
1037         case MONO_TYPE_I:
1038         case MONO_TYPE_U:
1039         case MONO_TYPE_PTR:
1040         case MONO_TYPE_FNPTR:
1041         case MONO_TYPE_CLASS:
1042         case MONO_TYPE_OBJECT:
1043         case MONO_TYPE_SZARRAY:
1044         case MONO_TYPE_ARRAY:
1045         case MONO_TYPE_STRING:
1046                 cinfo->ret.storage = ArgInIReg;
1047                 cinfo->ret.reg = AMD64_RAX;
1048                 break;
1049         case MONO_TYPE_U8:
1050         case MONO_TYPE_I8:
1051                 cinfo->ret.storage = ArgInIReg;
1052                 cinfo->ret.reg = AMD64_RAX;
1053                 break;
1054         case MONO_TYPE_R4:
1055                 cinfo->ret.storage = ArgInFloatSSEReg;
1056                 cinfo->ret.reg = AMD64_XMM0;
1057                 break;
1058         case MONO_TYPE_R8:
1059                 cinfo->ret.storage = ArgInDoubleSSEReg;
1060                 cinfo->ret.reg = AMD64_XMM0;
1061                 break;
1062         case MONO_TYPE_GENERICINST:
1063                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1064                         cinfo->ret.storage = ArgInIReg;
1065                         cinfo->ret.reg = AMD64_RAX;
1066                         break;
1067                 }
1068                 /* fall through */
1069 #if defined( __native_client_codegen__ )
1070         case MONO_TYPE_TYPEDBYREF:
1071 #endif
1072         case MONO_TYPE_VALUETYPE: {
1073                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1074
1075                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1076                 if (cinfo->ret.storage == ArgOnStack) {
1077                         cinfo->vtype_retaddr = TRUE;
1078                         /* The caller passes the address where the value is stored */
1079                 }
1080                 break;
1081         }
1082 #if !defined( __native_client_codegen__ )
1083         case MONO_TYPE_TYPEDBYREF:
1084                 /* Same as a valuetype with size 24 */
1085                 cinfo->vtype_retaddr = TRUE;
1086                 break;
1087 #endif
1088         case MONO_TYPE_VOID:
1089                 break;
1090         default:
1091                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1092         }
1093
1094         pstart = 0;
1095         /*
1096          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1097          * the first argument, allowing 'this' to be always passed in the first arg reg.
1098          * Also do this if the first argument is a reference type, since virtual calls
1099          * are sometimes made using calli without sig->hasthis set, like in the delegate
1100          * invoke wrappers.
1101          */
1102         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1103                 if (sig->hasthis) {
1104                         add_general (&gr, &stack_size, cinfo->args + 0);
1105                 } else {
1106                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1107                         pstart = 1;
1108                 }
1109                 add_general (&gr, &stack_size, &cinfo->ret);
1110                 cinfo->vret_arg_index = 1;
1111         } else {
1112                 /* this */
1113                 if (sig->hasthis)
1114                         add_general (&gr, &stack_size, cinfo->args + 0);
1115
1116                 if (cinfo->vtype_retaddr)
1117                         add_general (&gr, &stack_size, &cinfo->ret);
1118         }
1119
1120         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1121                 gr = PARAM_REGS;
1122                 fr = FLOAT_PARAM_REGS;
1123
1124                 /* Emit the signature cookie just before the implicit arguments */
1125                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1126         }
1127
1128         for (i = pstart; i < sig->param_count; ++i) {
1129                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1130                 MonoType *ptype;
1131
1132 #ifdef TARGET_WIN32
1133                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1134                 if (gr > fr)
1135                         fr = gr;
1136                 else if (fr > gr)
1137                         gr = fr;
1138 #endif
1139
1140                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1141                         /* We allways pass the sig cookie on the stack for simplicity */
1142                         /*
1143                          * Prevent implicit arguments + the sig cookie from being passed
1144                          * in registers.
1145                          */
1146                         gr = PARAM_REGS;
1147                         fr = FLOAT_PARAM_REGS;
1148
1149                         /* Emit the signature cookie just before the implicit arguments */
1150                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1151                 }
1152
1153                 ptype = mini_get_underlying_type (sig->params [i]);
1154                 switch (ptype->type) {
1155                 case MONO_TYPE_I1:
1156                 case MONO_TYPE_U1:
1157                         add_general (&gr, &stack_size, ainfo);
1158                         break;
1159                 case MONO_TYPE_I2:
1160                 case MONO_TYPE_U2:
1161                         add_general (&gr, &stack_size, ainfo);
1162                         break;
1163                 case MONO_TYPE_I4:
1164                 case MONO_TYPE_U4:
1165                         add_general (&gr, &stack_size, ainfo);
1166                         break;
1167                 case MONO_TYPE_I:
1168                 case MONO_TYPE_U:
1169                 case MONO_TYPE_PTR:
1170                 case MONO_TYPE_FNPTR:
1171                 case MONO_TYPE_CLASS:
1172                 case MONO_TYPE_OBJECT:
1173                 case MONO_TYPE_STRING:
1174                 case MONO_TYPE_SZARRAY:
1175                 case MONO_TYPE_ARRAY:
1176                         add_general (&gr, &stack_size, ainfo);
1177                         break;
1178                 case MONO_TYPE_GENERICINST:
1179                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1180                                 add_general (&gr, &stack_size, ainfo);
1181                                 break;
1182                         }
1183                         /* fall through */
1184                 case MONO_TYPE_VALUETYPE:
1185                 case MONO_TYPE_TYPEDBYREF:
1186                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1187                         break;
1188                 case MONO_TYPE_U8:
1189
1190                 case MONO_TYPE_I8:
1191                         add_general (&gr, &stack_size, ainfo);
1192                         break;
1193                 case MONO_TYPE_R4:
1194                         add_float (&fr, &stack_size, ainfo, FALSE);
1195                         break;
1196                 case MONO_TYPE_R8:
1197                         add_float (&fr, &stack_size, ainfo, TRUE);
1198                         break;
1199                 default:
1200                         g_assert_not_reached ();
1201                 }
1202         }
1203
1204         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1205                 gr = PARAM_REGS;
1206                 fr = FLOAT_PARAM_REGS;
1207
1208                 /* Emit the signature cookie just before the implicit arguments */
1209                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1210         }
1211
1212         cinfo->stack_usage = stack_size;
1213         cinfo->reg_usage = gr;
1214         cinfo->freg_usage = fr;
1215         return cinfo;
1216 }
1217
1218 /*
1219  * mono_arch_get_argument_info:
1220  * @csig:  a method signature
1221  * @param_count: the number of parameters to consider
1222  * @arg_info: an array to store the result infos
1223  *
1224  * Gathers information on parameters such as size, alignment and
1225  * padding. arg_info should be large enought to hold param_count + 1 entries.
1226  *
1227  * Returns the size of the argument area on the stack.
1228  */
1229 int
1230 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1231 {
1232         int k;
1233         CallInfo *cinfo = get_call_info (NULL, csig);
1234         guint32 args_size = cinfo->stack_usage;
1235
1236         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1237         if (csig->hasthis) {
1238                 arg_info [0].offset = 0;
1239         }
1240
1241         for (k = 0; k < param_count; k++) {
1242                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1243                 /* FIXME: */
1244                 arg_info [k + 1].size = 0;
1245         }
1246
1247         g_free (cinfo);
1248
1249         return args_size;
1250 }
1251
1252 gboolean
1253 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1254 {
1255         CallInfo *c1, *c2;
1256         gboolean res;
1257         MonoType *callee_ret;
1258
1259         c1 = get_call_info (NULL, caller_sig);
1260         c2 = get_call_info (NULL, callee_sig);
1261         res = c1->stack_usage >= c2->stack_usage;
1262         callee_ret = mini_get_underlying_type (callee_sig->ret);
1263         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1264                 /* An address on the callee's stack is passed as the first argument */
1265                 res = FALSE;
1266
1267         g_free (c1);
1268         g_free (c2);
1269
1270         return res;
1271 }
1272
1273 /*
1274  * Initialize the cpu to execute managed code.
1275  */
1276 void
1277 mono_arch_cpu_init (void)
1278 {
1279 #ifndef _MSC_VER
1280         guint16 fpcw;
1281
1282         /* spec compliance requires running with double precision */
1283         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1284         fpcw &= ~X86_FPCW_PRECC_MASK;
1285         fpcw |= X86_FPCW_PREC_DOUBLE;
1286         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1287         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1288 #else
1289         /* TODO: This is crashing on Win64 right now.
1290         * _control87 (_PC_53, MCW_PC);
1291         */
1292 #endif
1293 }
1294
1295 /*
1296  * Initialize architecture specific code.
1297  */
1298 void
1299 mono_arch_init (void)
1300 {
1301         int flags;
1302
1303         mono_mutex_init_recursive (&mini_arch_mutex);
1304 #if defined(__native_client_codegen__)
1305         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1306         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1307         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1308         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1309 #endif
1310
1311 #ifdef MONO_ARCH_NOMAP32BIT
1312         flags = MONO_MMAP_READ;
1313         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1314         breakpoint_size = 13;
1315         breakpoint_fault_size = 3;
1316 #else
1317         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1318         /* amd64_mov_reg_mem () */
1319         breakpoint_size = 8;
1320         breakpoint_fault_size = 8;
1321 #endif
1322
1323         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1324         single_step_fault_size = 4;
1325
1326         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1327         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1328         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1329
1330         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1331         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1332         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1333         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1334 }
1335
1336 /*
1337  * Cleanup architecture specific code.
1338  */
1339 void
1340 mono_arch_cleanup (void)
1341 {
1342         mono_mutex_destroy (&mini_arch_mutex);
1343 #if defined(__native_client_codegen__)
1344         mono_native_tls_free (nacl_instruction_depth);
1345         mono_native_tls_free (nacl_rex_tag);
1346         mono_native_tls_free (nacl_legacy_prefix_tag);
1347 #endif
1348 }
1349
1350 /*
1351  * This function returns the optimizations supported on this cpu.
1352  */
1353 guint32
1354 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1355 {
1356         guint32 opts = 0;
1357
1358         *exclude_mask = 0;
1359
1360         if (mono_hwcap_x86_has_cmov) {
1361                 opts |= MONO_OPT_CMOV;
1362
1363                 if (mono_hwcap_x86_has_fcmov)
1364                         opts |= MONO_OPT_FCMOV;
1365                 else
1366                         *exclude_mask |= MONO_OPT_FCMOV;
1367         } else {
1368                 *exclude_mask |= MONO_OPT_CMOV;
1369         }
1370
1371         return opts;
1372 }
1373
1374 /*
1375  * This function test for all SSE functions supported.
1376  *
1377  * Returns a bitmask corresponding to all supported versions.
1378  *
1379  */
1380 guint32
1381 mono_arch_cpu_enumerate_simd_versions (void)
1382 {
1383         guint32 sse_opts = 0;
1384
1385         if (mono_hwcap_x86_has_sse1)
1386                 sse_opts |= SIMD_VERSION_SSE1;
1387
1388         if (mono_hwcap_x86_has_sse2)
1389                 sse_opts |= SIMD_VERSION_SSE2;
1390
1391         if (mono_hwcap_x86_has_sse3)
1392                 sse_opts |= SIMD_VERSION_SSE3;
1393
1394         if (mono_hwcap_x86_has_ssse3)
1395                 sse_opts |= SIMD_VERSION_SSSE3;
1396
1397         if (mono_hwcap_x86_has_sse41)
1398                 sse_opts |= SIMD_VERSION_SSE41;
1399
1400         if (mono_hwcap_x86_has_sse42)
1401                 sse_opts |= SIMD_VERSION_SSE42;
1402
1403         if (mono_hwcap_x86_has_sse4a)
1404                 sse_opts |= SIMD_VERSION_SSE4a;
1405
1406         return sse_opts;
1407 }
1408
1409 #ifndef DISABLE_JIT
1410
1411 GList *
1412 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1413 {
1414         GList *vars = NULL;
1415         int i;
1416
1417         for (i = 0; i < cfg->num_varinfo; i++) {
1418                 MonoInst *ins = cfg->varinfo [i];
1419                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1420
1421                 /* unused vars */
1422                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1423                         continue;
1424
1425                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1426                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1427                         continue;
1428
1429                 if (mono_is_regsize_var (ins->inst_vtype)) {
1430                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1431                         g_assert (i == vmv->idx);
1432                         vars = g_list_prepend (vars, vmv);
1433                 }
1434         }
1435
1436         vars = mono_varlist_sort (cfg, vars, 0);
1437
1438         return vars;
1439 }
1440
1441 /**
1442  * mono_arch_compute_omit_fp:
1443  *
1444  *   Determine whenever the frame pointer can be eliminated.
1445  */
1446 static void
1447 mono_arch_compute_omit_fp (MonoCompile *cfg)
1448 {
1449         MonoMethodSignature *sig;
1450         MonoMethodHeader *header;
1451         int i, locals_size;
1452         CallInfo *cinfo;
1453
1454         if (cfg->arch.omit_fp_computed)
1455                 return;
1456
1457         header = cfg->header;
1458
1459         sig = mono_method_signature (cfg->method);
1460
1461         if (!cfg->arch.cinfo)
1462                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1463         cinfo = cfg->arch.cinfo;
1464
1465         /*
1466          * FIXME: Remove some of the restrictions.
1467          */
1468         cfg->arch.omit_fp = TRUE;
1469         cfg->arch.omit_fp_computed = TRUE;
1470
1471 #ifdef __native_client_codegen__
1472         /* NaCl modules may not change the value of RBP, so it cannot be */
1473         /* used as a normal register, but it can be used as a frame pointer*/
1474         cfg->disable_omit_fp = TRUE;
1475         cfg->arch.omit_fp = FALSE;
1476 #endif
1477
1478         if (cfg->disable_omit_fp)
1479                 cfg->arch.omit_fp = FALSE;
1480
1481         if (!debug_omit_fp ())
1482                 cfg->arch.omit_fp = FALSE;
1483         /*
1484         if (cfg->method->save_lmf)
1485                 cfg->arch.omit_fp = FALSE;
1486         */
1487         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1488                 cfg->arch.omit_fp = FALSE;
1489         if (header->num_clauses)
1490                 cfg->arch.omit_fp = FALSE;
1491         if (cfg->param_area)
1492                 cfg->arch.omit_fp = FALSE;
1493         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1494                 cfg->arch.omit_fp = FALSE;
1495         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1496                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1497                 cfg->arch.omit_fp = FALSE;
1498         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1499                 ArgInfo *ainfo = &cinfo->args [i];
1500
1501                 if (ainfo->storage == ArgOnStack) {
1502                         /*
1503                          * The stack offset can only be determined when the frame
1504                          * size is known.
1505                          */
1506                         cfg->arch.omit_fp = FALSE;
1507                 }
1508         }
1509
1510         locals_size = 0;
1511         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1512                 MonoInst *ins = cfg->varinfo [i];
1513                 int ialign;
1514
1515                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1516         }
1517 }
1518
1519 GList *
1520 mono_arch_get_global_int_regs (MonoCompile *cfg)
1521 {
1522         GList *regs = NULL;
1523
1524         mono_arch_compute_omit_fp (cfg);
1525
1526         if (cfg->arch.omit_fp)
1527                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1528
1529         /* We use the callee saved registers for global allocation */
1530         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1531         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1532         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1533         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1534 #ifndef __native_client_codegen__
1535         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1536 #endif
1537 #ifdef TARGET_WIN32
1538         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1539         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1540 #endif
1541
1542         return regs;
1543 }
1544
1545 GList*
1546 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1547 {
1548         GList *regs = NULL;
1549         int i;
1550
1551         /* All XMM registers */
1552         for (i = 0; i < 16; ++i)
1553                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1554
1555         return regs;
1556 }
1557
1558 GList*
1559 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1560 {
1561         static GList *r = NULL;
1562
1563         if (r == NULL) {
1564                 GList *regs = NULL;
1565
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1568                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1569                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1570                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1571 #ifndef __native_client_codegen__
1572                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1573 #endif
1574
1575                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1576                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1577                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1583
1584                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1585         }
1586
1587         return r;
1588 }
1589
1590 GList*
1591 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1592 {
1593         int i;
1594         static GList *r = NULL;
1595
1596         if (r == NULL) {
1597                 GList *regs = NULL;
1598
1599                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1600                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1601
1602                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1603         }
1604
1605         return r;
1606 }
1607
1608 /*
1609  * mono_arch_regalloc_cost:
1610  *
1611  *  Return the cost, in number of memory references, of the action of
1612  * allocating the variable VMV into a register during global register
1613  * allocation.
1614  */
1615 guint32
1616 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1617 {
1618         MonoInst *ins = cfg->varinfo [vmv->idx];
1619
1620         if (cfg->method->save_lmf)
1621                 /* The register is already saved */
1622                 /* substract 1 for the invisible store in the prolog */
1623                 return (ins->opcode == OP_ARG) ? 0 : 1;
1624         else
1625                 /* push+pop */
1626                 return (ins->opcode == OP_ARG) ? 1 : 2;
1627 }
1628
1629 /*
1630  * mono_arch_fill_argument_info:
1631  *
1632  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1633  * of the method.
1634  */
1635 void
1636 mono_arch_fill_argument_info (MonoCompile *cfg)
1637 {
1638         MonoType *sig_ret;
1639         MonoMethodSignature *sig;
1640         MonoInst *ins;
1641         int i;
1642         CallInfo *cinfo;
1643
1644         sig = mono_method_signature (cfg->method);
1645
1646         cinfo = cfg->arch.cinfo;
1647         sig_ret = mini_get_underlying_type (sig->ret);
1648
1649         /*
1650          * Contrary to mono_arch_allocate_vars (), the information should describe
1651          * where the arguments are at the beginning of the method, not where they can be
1652          * accessed during the execution of the method. The later makes no sense for the
1653          * global register allocator, since a variable can be in more than one location.
1654          */
1655         if (sig_ret->type != MONO_TYPE_VOID) {
1656                 switch (cinfo->ret.storage) {
1657                 case ArgInIReg:
1658                 case ArgInFloatSSEReg:
1659                 case ArgInDoubleSSEReg:
1660                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1661                                 cfg->vret_addr->opcode = OP_REGVAR;
1662                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1663                         }
1664                         else {
1665                                 cfg->ret->opcode = OP_REGVAR;
1666                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1667                         }
1668                         break;
1669                 case ArgValuetypeInReg:
1670                         cfg->ret->opcode = OP_REGOFFSET;
1671                         cfg->ret->inst_basereg = -1;
1672                         cfg->ret->inst_offset = -1;
1673                         break;
1674                 default:
1675                         g_assert_not_reached ();
1676                 }
1677         }
1678
1679         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1680                 ArgInfo *ainfo = &cinfo->args [i];
1681
1682                 ins = cfg->args [i];
1683
1684                 switch (ainfo->storage) {
1685                 case ArgInIReg:
1686                 case ArgInFloatSSEReg:
1687                 case ArgInDoubleSSEReg:
1688                         ins->opcode = OP_REGVAR;
1689                         ins->inst_c0 = ainfo->reg;
1690                         break;
1691                 case ArgOnStack:
1692                         ins->opcode = OP_REGOFFSET;
1693                         ins->inst_basereg = -1;
1694                         ins->inst_offset = -1;
1695                         break;
1696                 case ArgValuetypeInReg:
1697                         /* Dummy */
1698                         ins->opcode = OP_NOP;
1699                         break;
1700                 default:
1701                         g_assert_not_reached ();
1702                 }
1703         }
1704 }
1705
1706 void
1707 mono_arch_allocate_vars (MonoCompile *cfg)
1708 {
1709         MonoType *sig_ret;
1710         MonoMethodSignature *sig;
1711         MonoInst *ins;
1712         int i, offset;
1713         guint32 locals_stack_size, locals_stack_align;
1714         gint32 *offsets;
1715         CallInfo *cinfo;
1716
1717         sig = mono_method_signature (cfg->method);
1718
1719         cinfo = cfg->arch.cinfo;
1720         sig_ret = mini_get_underlying_type (sig->ret);
1721
1722         mono_arch_compute_omit_fp (cfg);
1723
1724         /*
1725          * We use the ABI calling conventions for managed code as well.
1726          * Exception: valuetypes are only sometimes passed or returned in registers.
1727          */
1728
1729         /*
1730          * The stack looks like this:
1731          * <incoming arguments passed on the stack>
1732          * <return value>
1733          * <lmf/caller saved registers>
1734          * <locals>
1735          * <spill area>
1736          * <localloc area>  -> grows dynamically
1737          * <params area>
1738          */
1739
1740         if (cfg->arch.omit_fp) {
1741                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1742                 cfg->frame_reg = AMD64_RSP;
1743                 offset = 0;
1744         } else {
1745                 /* Locals are allocated backwards from %fp */
1746                 cfg->frame_reg = AMD64_RBP;
1747                 offset = 0;
1748         }
1749
1750         cfg->arch.saved_iregs = cfg->used_int_regs;
1751         if (cfg->method->save_lmf)
1752                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1753                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1754
1755         if (cfg->arch.omit_fp)
1756                 cfg->arch.reg_save_area_offset = offset;
1757         /* Reserve space for callee saved registers */
1758         for (i = 0; i < AMD64_NREG; ++i)
1759                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1760                         offset += sizeof(mgreg_t);
1761                 }
1762         if (!cfg->arch.omit_fp)
1763                 cfg->arch.reg_save_area_offset = -offset;
1764
1765         if (sig_ret->type != MONO_TYPE_VOID) {
1766                 switch (cinfo->ret.storage) {
1767                 case ArgInIReg:
1768                 case ArgInFloatSSEReg:
1769                 case ArgInDoubleSSEReg:
1770                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1771                                 /* The register is volatile */
1772                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1773                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1774                                 if (cfg->arch.omit_fp) {
1775                                         cfg->vret_addr->inst_offset = offset;
1776                                         offset += 8;
1777                                 } else {
1778                                         offset += 8;
1779                                         cfg->vret_addr->inst_offset = -offset;
1780                                 }
1781                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1782                                         printf ("vret_addr =");
1783                                         mono_print_ins (cfg->vret_addr);
1784                                 }
1785                         }
1786                         else {
1787                                 cfg->ret->opcode = OP_REGVAR;
1788                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1789                         }
1790                         break;
1791                 case ArgValuetypeInReg:
1792                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1793                         cfg->ret->opcode = OP_REGOFFSET;
1794                         cfg->ret->inst_basereg = cfg->frame_reg;
1795                         if (cfg->arch.omit_fp) {
1796                                 cfg->ret->inst_offset = offset;
1797                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1798                         } else {
1799                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1800                                 cfg->ret->inst_offset = - offset;
1801                         }
1802                         break;
1803                 default:
1804                         g_assert_not_reached ();
1805                 }
1806                 cfg->ret->dreg = cfg->ret->inst_c0;
1807         }
1808
1809         /* Allocate locals */
1810         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1811         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1812                 char *mname = mono_method_full_name (cfg->method, TRUE);
1813                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1814                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1815                 g_free (mname);
1816                 return;
1817         }
1818
1819         if (locals_stack_align) {
1820                 offset += (locals_stack_align - 1);
1821                 offset &= ~(locals_stack_align - 1);
1822         }
1823         if (cfg->arch.omit_fp) {
1824                 cfg->locals_min_stack_offset = offset;
1825                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1826         } else {
1827                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1828                 cfg->locals_max_stack_offset = - offset;
1829         }
1830
1831         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1832                 if (offsets [i] != -1) {
1833                         MonoInst *ins = cfg->varinfo [i];
1834                         ins->opcode = OP_REGOFFSET;
1835                         ins->inst_basereg = cfg->frame_reg;
1836                         if (cfg->arch.omit_fp)
1837                                 ins->inst_offset = (offset + offsets [i]);
1838                         else
1839                                 ins->inst_offset = - (offset + offsets [i]);
1840                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1841                 }
1842         }
1843         offset += locals_stack_size;
1844
1845         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1846                 g_assert (!cfg->arch.omit_fp);
1847                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1848                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1849         }
1850
1851         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1852                 ins = cfg->args [i];
1853                 if (ins->opcode != OP_REGVAR) {
1854                         ArgInfo *ainfo = &cinfo->args [i];
1855                         gboolean inreg = TRUE;
1856
1857                         /* FIXME: Allocate volatile arguments to registers */
1858                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1859                                 inreg = FALSE;
1860
1861                         /*
1862                          * Under AMD64, all registers used to pass arguments to functions
1863                          * are volatile across calls.
1864                          * FIXME: Optimize this.
1865                          */
1866                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1867                                 inreg = FALSE;
1868
1869                         ins->opcode = OP_REGOFFSET;
1870
1871                         switch (ainfo->storage) {
1872                         case ArgInIReg:
1873                         case ArgInFloatSSEReg:
1874                         case ArgInDoubleSSEReg:
1875                                 if (inreg) {
1876                                         ins->opcode = OP_REGVAR;
1877                                         ins->dreg = ainfo->reg;
1878                                 }
1879                                 break;
1880                         case ArgOnStack:
1881                                 g_assert (!cfg->arch.omit_fp);
1882                                 ins->opcode = OP_REGOFFSET;
1883                                 ins->inst_basereg = cfg->frame_reg;
1884                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1885                                 break;
1886                         case ArgValuetypeInReg:
1887                                 break;
1888                         case ArgValuetypeAddrInIReg: {
1889                                 MonoInst *indir;
1890                                 g_assert (!cfg->arch.omit_fp);
1891
1892                                 MONO_INST_NEW (cfg, indir, 0);
1893                                 indir->opcode = OP_REGOFFSET;
1894                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1895                                         indir->inst_basereg = cfg->frame_reg;
1896                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1897                                         offset += (sizeof (gpointer));
1898                                         indir->inst_offset = - offset;
1899                                 }
1900                                 else {
1901                                         indir->inst_basereg = cfg->frame_reg;
1902                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1903                                 }
1904
1905                                 ins->opcode = OP_VTARG_ADDR;
1906                                 ins->inst_left = indir;
1907
1908                                 break;
1909                         }
1910                         default:
1911                                 NOT_IMPLEMENTED;
1912                         }
1913
1914                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1915                                 ins->opcode = OP_REGOFFSET;
1916                                 ins->inst_basereg = cfg->frame_reg;
1917                                 /* These arguments are saved to the stack in the prolog */
1918                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1919                                 if (cfg->arch.omit_fp) {
1920                                         ins->inst_offset = offset;
1921                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1922                                         // Arguments are yet supported by the stack map creation code
1923                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1924                                 } else {
1925                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1926                                         ins->inst_offset = - offset;
1927                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1928                                 }
1929                         }
1930                 }
1931         }
1932
1933         cfg->stack_offset = offset;
1934 }
1935
1936 void
1937 mono_arch_create_vars (MonoCompile *cfg)
1938 {
1939         MonoMethodSignature *sig;
1940         CallInfo *cinfo;
1941         MonoType *sig_ret;
1942
1943         sig = mono_method_signature (cfg->method);
1944
1945         if (!cfg->arch.cinfo)
1946                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1947         cinfo = cfg->arch.cinfo;
1948
1949         if (cinfo->ret.storage == ArgValuetypeInReg)
1950                 cfg->ret_var_is_local = TRUE;
1951
1952         sig_ret = mini_get_underlying_type (sig->ret);
1953         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1954                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1955                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1956                         printf ("vret_addr = ");
1957                         mono_print_ins (cfg->vret_addr);
1958                 }
1959         }
1960
1961         if (cfg->gen_sdb_seq_points) {
1962                 MonoInst *ins;
1963
1964                 if (cfg->compile_aot) {
1965                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1966                         ins->flags |= MONO_INST_VOLATILE;
1967                         cfg->arch.seq_point_info_var = ins;
1968
1969                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1970                         ins->flags |= MONO_INST_VOLATILE;
1971                         cfg->arch.ss_tramp_var = ins;
1972                 }
1973
1974             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1975                 ins->flags |= MONO_INST_VOLATILE;
1976                 cfg->arch.ss_trigger_page_var = ins;
1977         }
1978
1979         if (cfg->method->save_lmf)
1980                 cfg->create_lmf_var = TRUE;
1981
1982         if (cfg->method->save_lmf) {
1983                 cfg->lmf_ir = TRUE;
1984 #if !defined(TARGET_WIN32)
1985                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1986                         cfg->lmf_ir_mono_lmf = TRUE;
1987 #endif
1988         }
1989 }
1990
1991 static void
1992 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1993 {
1994         MonoInst *ins;
1995
1996         switch (storage) {
1997         case ArgInIReg:
1998                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1999                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2000                 ins->sreg1 = tree->dreg;
2001                 MONO_ADD_INS (cfg->cbb, ins);
2002                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2003                 break;
2004         case ArgInFloatSSEReg:
2005                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2006                 ins->dreg = mono_alloc_freg (cfg);
2007                 ins->sreg1 = tree->dreg;
2008                 MONO_ADD_INS (cfg->cbb, ins);
2009
2010                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2011                 break;
2012         case ArgInDoubleSSEReg:
2013                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2014                 ins->dreg = mono_alloc_freg (cfg);
2015                 ins->sreg1 = tree->dreg;
2016                 MONO_ADD_INS (cfg->cbb, ins);
2017
2018                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2019
2020                 break;
2021         default:
2022                 g_assert_not_reached ();
2023         }
2024 }
2025
2026 static int
2027 arg_storage_to_load_membase (ArgStorage storage)
2028 {
2029         switch (storage) {
2030         case ArgInIReg:
2031 #if defined(__mono_ilp32__)
2032                 return OP_LOADI8_MEMBASE;
2033 #else
2034                 return OP_LOAD_MEMBASE;
2035 #endif
2036         case ArgInDoubleSSEReg:
2037                 return OP_LOADR8_MEMBASE;
2038         case ArgInFloatSSEReg:
2039                 return OP_LOADR4_MEMBASE;
2040         default:
2041                 g_assert_not_reached ();
2042         }
2043
2044         return -1;
2045 }
2046
2047 static void
2048 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2049 {
2050         MonoMethodSignature *tmp_sig;
2051         int sig_reg;
2052
2053         if (call->tail_call)
2054                 NOT_IMPLEMENTED;
2055
2056         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2057
2058         /*
2059          * mono_ArgIterator_Setup assumes the signature cookie is
2060          * passed first and all the arguments which were before it are
2061          * passed on the stack after the signature. So compensate by
2062          * passing a different signature.
2063          */
2064         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2065         tmp_sig->param_count -= call->signature->sentinelpos;
2066         tmp_sig->sentinelpos = 0;
2067         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2068
2069         sig_reg = mono_alloc_ireg (cfg);
2070         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2071
2072         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2073 }
2074
2075 #ifdef ENABLE_LLVM
2076 static inline LLVMArgStorage
2077 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2078 {
2079         switch (storage) {
2080         case ArgInIReg:
2081                 return LLVMArgInIReg;
2082         case ArgNone:
2083                 return LLVMArgNone;
2084         default:
2085                 g_assert_not_reached ();
2086                 return LLVMArgNone;
2087         }
2088 }
2089
2090 LLVMCallInfo*
2091 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2092 {
2093         int i, n;
2094         CallInfo *cinfo;
2095         ArgInfo *ainfo;
2096         int j;
2097         LLVMCallInfo *linfo;
2098         MonoType *t, *sig_ret;
2099
2100         n = sig->param_count + sig->hasthis;
2101         sig_ret = mini_get_underlying_type (sig->ret);
2102
2103         cinfo = get_call_info (cfg->mempool, sig);
2104
2105         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2106
2107         /*
2108          * LLVM always uses the native ABI while we use our own ABI, the
2109          * only difference is the handling of vtypes:
2110          * - we only pass/receive them in registers in some cases, and only
2111          *   in 1 or 2 integer registers.
2112          */
2113         if (cinfo->ret.storage == ArgValuetypeInReg) {
2114                 if (sig->pinvoke) {
2115                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2116                         cfg->disable_llvm = TRUE;
2117                         return linfo;
2118                 }
2119
2120                 linfo->ret.storage = LLVMArgVtypeInReg;
2121                 for (j = 0; j < 2; ++j)
2122                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2123         }
2124
2125         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2126                 /* Vtype returned using a hidden argument */
2127                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2128                 linfo->vret_arg_index = cinfo->vret_arg_index;
2129         }
2130
2131         for (i = 0; i < n; ++i) {
2132                 ainfo = cinfo->args + i;
2133
2134                 if (i >= sig->hasthis)
2135                         t = sig->params [i - sig->hasthis];
2136                 else
2137                         t = &mono_defaults.int_class->byval_arg;
2138
2139                 linfo->args [i].storage = LLVMArgNone;
2140
2141                 switch (ainfo->storage) {
2142                 case ArgInIReg:
2143                         linfo->args [i].storage = LLVMArgInIReg;
2144                         break;
2145                 case ArgInDoubleSSEReg:
2146                 case ArgInFloatSSEReg:
2147                         linfo->args [i].storage = LLVMArgInFPReg;
2148                         break;
2149                 case ArgOnStack:
2150                         if (MONO_TYPE_ISSTRUCT (t)) {
2151                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2152                         } else {
2153                                 linfo->args [i].storage = LLVMArgInIReg;
2154                                 if (!t->byref) {
2155                                         if (t->type == MONO_TYPE_R4)
2156                                                 linfo->args [i].storage = LLVMArgInFPReg;
2157                                         else if (t->type == MONO_TYPE_R8)
2158                                                 linfo->args [i].storage = LLVMArgInFPReg;
2159                                 }
2160                         }
2161                         break;
2162                 case ArgValuetypeInReg:
2163                         if (sig->pinvoke) {
2164                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2165                                 cfg->disable_llvm = TRUE;
2166                                 return linfo;
2167                         }
2168
2169                         linfo->args [i].storage = LLVMArgVtypeInReg;
2170                         for (j = 0; j < 2; ++j)
2171                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2172                         break;
2173                 default:
2174                         cfg->exception_message = g_strdup ("ainfo->storage");
2175                         cfg->disable_llvm = TRUE;
2176                         break;
2177                 }
2178         }
2179
2180         return linfo;
2181 }
2182 #endif
2183
2184 void
2185 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2186 {
2187         MonoInst *arg, *in;
2188         MonoMethodSignature *sig;
2189         MonoType *sig_ret;
2190         int i, n;
2191         CallInfo *cinfo;
2192         ArgInfo *ainfo;
2193
2194         sig = call->signature;
2195         n = sig->param_count + sig->hasthis;
2196
2197         cinfo = get_call_info (cfg->mempool, sig);
2198
2199         sig_ret = sig->ret;
2200
2201         if (COMPILE_LLVM (cfg)) {
2202                 /* We shouldn't be called in the llvm case */
2203                 cfg->disable_llvm = TRUE;
2204                 return;
2205         }
2206
2207         /*
2208          * Emit all arguments which are passed on the stack to prevent register
2209          * allocation problems.
2210          */
2211         for (i = 0; i < n; ++i) {
2212                 MonoType *t;
2213                 ainfo = cinfo->args + i;
2214
2215                 in = call->args [i];
2216
2217                 if (sig->hasthis && i == 0)
2218                         t = &mono_defaults.object_class->byval_arg;
2219                 else
2220                         t = sig->params [i - sig->hasthis];
2221
2222                 t = mini_get_underlying_type (t);
2223                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2224                         if (!t->byref) {
2225                                 if (t->type == MONO_TYPE_R4)
2226                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2227                                 else if (t->type == MONO_TYPE_R8)
2228                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2229                                 else
2230                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2231                         } else {
2232                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2233                         }
2234                         if (cfg->compute_gc_maps) {
2235                                 MonoInst *def;
2236
2237                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2238                         }
2239                 }
2240         }
2241
2242         /*
2243          * Emit all parameters passed in registers in non-reverse order for better readability
2244          * and to help the optimization in emit_prolog ().
2245          */
2246         for (i = 0; i < n; ++i) {
2247                 ainfo = cinfo->args + i;
2248
2249                 in = call->args [i];
2250
2251                 if (ainfo->storage == ArgInIReg)
2252                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2253         }
2254
2255         for (i = n - 1; i >= 0; --i) {
2256                 MonoType *t;
2257
2258                 ainfo = cinfo->args + i;
2259
2260                 in = call->args [i];
2261
2262                 if (sig->hasthis && i == 0)
2263                         t = &mono_defaults.object_class->byval_arg;
2264                 else
2265                         t = sig->params [i - sig->hasthis];
2266                 t = mini_get_underlying_type (t);
2267
2268                 switch (ainfo->storage) {
2269                 case ArgInIReg:
2270                         /* Already done */
2271                         break;
2272                 case ArgInFloatSSEReg:
2273                 case ArgInDoubleSSEReg:
2274                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2275                         break;
2276                 case ArgOnStack:
2277                 case ArgValuetypeInReg:
2278                 case ArgValuetypeAddrInIReg:
2279                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2280                                 MonoInst *call_inst = (MonoInst*)call;
2281                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2282                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2283                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
2284                                 guint32 align;
2285                                 guint32 size;
2286
2287                                 if (t->type == MONO_TYPE_TYPEDBYREF) {
2288                                         size = sizeof (MonoTypedRef);
2289                                         align = sizeof (gpointer);
2290                                 }
2291                                 else {
2292                                         if (sig->pinvoke)
2293                                                 size = mono_type_native_stack_size (t, &align);
2294                                         else {
2295                                                 /*
2296                                                  * Other backends use mono_type_stack_size (), but that
2297                                                  * aligns the size to 8, which is larger than the size of
2298                                                  * the source, leading to reads of invalid memory if the
2299                                                  * source is at the end of address space.
2300                                                  */
2301                                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2302                                         }
2303                                 }
2304                                 g_assert (in->klass);
2305
2306                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2307                                         /* Avoid asserts in emit_memcpy () */
2308                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2309                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2310                                         /* Continue normally */
2311                                 }
2312
2313                                 if (size > 0) {
2314                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2315                                         arg->sreg1 = in->dreg;
2316                                         arg->klass = mono_class_from_mono_type (t);
2317                                         arg->backend.size = size;
2318                                         arg->inst_p0 = call;
2319                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2320                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2321
2322                                         MONO_ADD_INS (cfg->cbb, arg);
2323                                 }
2324                         }
2325                         break;
2326                 default:
2327                         g_assert_not_reached ();
2328                 }
2329
2330                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2331                         /* Emit the signature cookie just before the implicit arguments */
2332                         emit_sig_cookie (cfg, call, cinfo);
2333         }
2334
2335         /* Handle the case where there are no implicit arguments */
2336         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2337                 emit_sig_cookie (cfg, call, cinfo);
2338
2339         sig_ret = mini_get_underlying_type (sig->ret);
2340         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2341                 MonoInst *vtarg;
2342
2343                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2344                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2345                                 /*
2346                                  * Tell the JIT to use a more efficient calling convention: call using
2347                                  * OP_CALL, compute the result location after the call, and save the
2348                                  * result there.
2349                                  */
2350                                 call->vret_in_reg = TRUE;
2351                                 /*
2352                                  * Nullify the instruction computing the vret addr to enable
2353                                  * future optimizations.
2354                                  */
2355                                 if (call->vret_var)
2356                                         NULLIFY_INS (call->vret_var);
2357                         } else {
2358                                 if (call->tail_call)
2359                                         NOT_IMPLEMENTED;
2360                                 /*
2361                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2362                                  * the stack. Push the address here, so the call instruction can
2363                                  * access it.
2364                                  */
2365                                 if (!cfg->arch.vret_addr_loc) {
2366                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2367                                         /* Prevent it from being register allocated or optimized away */
2368                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2369                                 }
2370
2371                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2372                         }
2373                 }
2374                 else {
2375                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2376                         vtarg->sreg1 = call->vret_var->dreg;
2377                         vtarg->dreg = mono_alloc_preg (cfg);
2378                         MONO_ADD_INS (cfg->cbb, vtarg);
2379
2380                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2381                 }
2382         }
2383
2384         if (cfg->method->save_lmf) {
2385                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2386                 MONO_ADD_INS (cfg->cbb, arg);
2387         }
2388
2389         call->stack_usage = cinfo->stack_usage;
2390 }
2391
2392 void
2393 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2394 {
2395         MonoInst *arg;
2396         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2397         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2398         int size = ins->backend.size;
2399
2400         if (ainfo->storage == ArgValuetypeInReg) {
2401                 MonoInst *load;
2402                 int part;
2403
2404                 for (part = 0; part < 2; ++part) {
2405                         if (ainfo->pair_storage [part] == ArgNone)
2406                                 continue;
2407
2408                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2409                         load->inst_basereg = src->dreg;
2410                         load->inst_offset = part * sizeof(mgreg_t);
2411
2412                         switch (ainfo->pair_storage [part]) {
2413                         case ArgInIReg:
2414                                 load->dreg = mono_alloc_ireg (cfg);
2415                                 break;
2416                         case ArgInDoubleSSEReg:
2417                         case ArgInFloatSSEReg:
2418                                 load->dreg = mono_alloc_freg (cfg);
2419                                 break;
2420                         default:
2421                                 g_assert_not_reached ();
2422                         }
2423                         MONO_ADD_INS (cfg->cbb, load);
2424
2425                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2426                 }
2427         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2428                 MonoInst *vtaddr, *load;
2429                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2430
2431                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2432                 cfg->has_indirection = TRUE;
2433                 load->inst_p0 = vtaddr;
2434                 vtaddr->flags |= MONO_INST_INDIRECT;
2435                 load->type = STACK_MP;
2436                 load->klass = vtaddr->klass;
2437                 load->dreg = mono_alloc_ireg (cfg);
2438                 MONO_ADD_INS (cfg->cbb, load);
2439                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2440
2441                 if (ainfo->pair_storage [0] == ArgInIReg) {
2442                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2443                         arg->dreg = mono_alloc_ireg (cfg);
2444                         arg->sreg1 = load->dreg;
2445                         arg->inst_imm = 0;
2446                         MONO_ADD_INS (cfg->cbb, arg);
2447                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2448                 } else {
2449                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2450                 }
2451         } else {
2452                 if (size == 8) {
2453                         int dreg = mono_alloc_ireg (cfg);
2454
2455                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2456                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2457                 } else if (size <= 40) {
2458                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2459                 } else {
2460                         // FIXME: Code growth
2461                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2462                 }
2463
2464                 if (cfg->compute_gc_maps) {
2465                         MonoInst *def;
2466                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2467                 }
2468         }
2469 }
2470
2471 void
2472 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2473 {
2474         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2475
2476         if (ret->type == MONO_TYPE_R4) {
2477                 if (COMPILE_LLVM (cfg))
2478                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2479                 else
2480                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2481                 return;
2482         } else if (ret->type == MONO_TYPE_R8) {
2483                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2484                 return;
2485         }
2486
2487         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2488 }
2489
2490 #endif /* DISABLE_JIT */
2491
2492 #define EMIT_COND_BRANCH(ins,cond,sign) \
2493         if (ins->inst_true_bb->native_offset) { \
2494                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2495         } else { \
2496                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2497                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2498             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2499                         x86_branch8 (code, cond, 0, sign); \
2500                 else \
2501                         x86_branch32 (code, cond, 0, sign); \
2502 }
2503
2504 typedef struct {
2505         MonoMethodSignature *sig;
2506         CallInfo *cinfo;
2507 } ArchDynCallInfo;
2508
2509 static gboolean
2510 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2511 {
2512         int i;
2513
2514 #ifdef HOST_WIN32
2515         return FALSE;
2516 #endif
2517
2518         switch (cinfo->ret.storage) {
2519         case ArgNone:
2520         case ArgInIReg:
2521                 break;
2522         case ArgValuetypeInReg: {
2523                 ArgInfo *ainfo = &cinfo->ret;
2524
2525                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2526                         return FALSE;
2527                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2528                         return FALSE;
2529                 break;
2530         }
2531         default:
2532                 return FALSE;
2533         }
2534
2535         for (i = 0; i < cinfo->nargs; ++i) {
2536                 ArgInfo *ainfo = &cinfo->args [i];
2537                 switch (ainfo->storage) {
2538                 case ArgInIReg:
2539                         break;
2540                 case ArgValuetypeInReg:
2541                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2542                                 return FALSE;
2543                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2544                                 return FALSE;
2545                         break;
2546                 default:
2547                         return FALSE;
2548                 }
2549         }
2550
2551         return TRUE;
2552 }
2553
2554 /*
2555  * mono_arch_dyn_call_prepare:
2556  *
2557  *   Return a pointer to an arch-specific structure which contains information
2558  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2559  * supported for SIG.
2560  * This function is equivalent to ffi_prep_cif in libffi.
2561  */
2562 MonoDynCallInfo*
2563 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2564 {
2565         ArchDynCallInfo *info;
2566         CallInfo *cinfo;
2567
2568         cinfo = get_call_info (NULL, sig);
2569
2570         if (!dyn_call_supported (sig, cinfo)) {
2571                 g_free (cinfo);
2572                 return NULL;
2573         }
2574
2575         info = g_new0 (ArchDynCallInfo, 1);
2576         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2577         info->sig = sig;
2578         info->cinfo = cinfo;
2579
2580         return (MonoDynCallInfo*)info;
2581 }
2582
2583 /*
2584  * mono_arch_dyn_call_free:
2585  *
2586  *   Free a MonoDynCallInfo structure.
2587  */
2588 void
2589 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2590 {
2591         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2592
2593         g_free (ainfo->cinfo);
2594         g_free (ainfo);
2595 }
2596
2597 #if !defined(__native_client__)
2598 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2599 #define GREG_TO_PTR(greg) (gpointer)(greg)
2600 #else
2601 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2602 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2603 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2604 #endif
2605
2606 /*
2607  * mono_arch_get_start_dyn_call:
2608  *
2609  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2610  * store the result into BUF.
2611  * ARGS should be an array of pointers pointing to the arguments.
2612  * RET should point to a memory buffer large enought to hold the result of the
2613  * call.
2614  * This function should be as fast as possible, any work which does not depend
2615  * on the actual values of the arguments should be done in
2616  * mono_arch_dyn_call_prepare ().
2617  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2618  * libffi.
2619  */
2620 void
2621 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2622 {
2623         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2624         DynCallArgs *p = (DynCallArgs*)buf;
2625         int arg_index, greg, i, pindex;
2626         MonoMethodSignature *sig = dinfo->sig;
2627
2628         g_assert (buf_len >= sizeof (DynCallArgs));
2629
2630         p->res = 0;
2631         p->ret = ret;
2632
2633         arg_index = 0;
2634         greg = 0;
2635         pindex = 0;
2636
2637         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2638                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2639                 if (!sig->hasthis)
2640                         pindex = 1;
2641         }
2642
2643         if (dinfo->cinfo->vtype_retaddr)
2644                 p->regs [greg ++] = PTR_TO_GREG(ret);
2645
2646         for (i = pindex; i < sig->param_count; i++) {
2647                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2648                 gpointer *arg = args [arg_index ++];
2649
2650                 if (t->byref) {
2651                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2652                         continue;
2653                 }
2654
2655                 switch (t->type) {
2656                 case MONO_TYPE_STRING:
2657                 case MONO_TYPE_CLASS:
2658                 case MONO_TYPE_ARRAY:
2659                 case MONO_TYPE_SZARRAY:
2660                 case MONO_TYPE_OBJECT:
2661                 case MONO_TYPE_PTR:
2662                 case MONO_TYPE_I:
2663                 case MONO_TYPE_U:
2664 #if !defined(__mono_ilp32__)
2665                 case MONO_TYPE_I8:
2666                 case MONO_TYPE_U8:
2667 #endif
2668                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2669                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2670                         break;
2671 #if defined(__mono_ilp32__)
2672                 case MONO_TYPE_I8:
2673                 case MONO_TYPE_U8:
2674                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2675                         p->regs [greg ++] = *(guint64*)(arg);
2676                         break;
2677 #endif
2678                 case MONO_TYPE_U1:
2679                         p->regs [greg ++] = *(guint8*)(arg);
2680                         break;
2681                 case MONO_TYPE_I1:
2682                         p->regs [greg ++] = *(gint8*)(arg);
2683                         break;
2684                 case MONO_TYPE_I2:
2685                         p->regs [greg ++] = *(gint16*)(arg);
2686                         break;
2687                 case MONO_TYPE_U2:
2688                         p->regs [greg ++] = *(guint16*)(arg);
2689                         break;
2690                 case MONO_TYPE_I4:
2691                         p->regs [greg ++] = *(gint32*)(arg);
2692                         break;
2693                 case MONO_TYPE_U4:
2694                         p->regs [greg ++] = *(guint32*)(arg);
2695                         break;
2696                 case MONO_TYPE_GENERICINST:
2697                     if (MONO_TYPE_IS_REFERENCE (t)) {
2698                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2699                                 break;
2700                         } else {
2701                                 /* Fall through */
2702                         }
2703                 case MONO_TYPE_VALUETYPE: {
2704                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2705
2706                         g_assert (ainfo->storage == ArgValuetypeInReg);
2707                         if (ainfo->pair_storage [0] != ArgNone) {
2708                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2709                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2710                         }
2711                         if (ainfo->pair_storage [1] != ArgNone) {
2712                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2713                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2714                         }
2715                         break;
2716                 }
2717                 default:
2718                         g_assert_not_reached ();
2719                 }
2720         }
2721
2722         g_assert (greg <= PARAM_REGS);
2723 }
2724
2725 /*
2726  * mono_arch_finish_dyn_call:
2727  *
2728  *   Store the result of a dyn call into the return value buffer passed to
2729  * start_dyn_call ().
2730  * This function should be as fast as possible, any work which does not depend
2731  * on the actual values of the arguments should be done in
2732  * mono_arch_dyn_call_prepare ().
2733  */
2734 void
2735 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2736 {
2737         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2738         MonoMethodSignature *sig = dinfo->sig;
2739         guint8 *ret = ((DynCallArgs*)buf)->ret;
2740         mgreg_t res = ((DynCallArgs*)buf)->res;
2741         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2742
2743         switch (sig_ret->type) {
2744         case MONO_TYPE_VOID:
2745                 *(gpointer*)ret = NULL;
2746                 break;
2747         case MONO_TYPE_STRING:
2748         case MONO_TYPE_CLASS:
2749         case MONO_TYPE_ARRAY:
2750         case MONO_TYPE_SZARRAY:
2751         case MONO_TYPE_OBJECT:
2752         case MONO_TYPE_I:
2753         case MONO_TYPE_U:
2754         case MONO_TYPE_PTR:
2755                 *(gpointer*)ret = GREG_TO_PTR(res);
2756                 break;
2757         case MONO_TYPE_I1:
2758                 *(gint8*)ret = res;
2759                 break;
2760         case MONO_TYPE_U1:
2761                 *(guint8*)ret = res;
2762                 break;
2763         case MONO_TYPE_I2:
2764                 *(gint16*)ret = res;
2765                 break;
2766         case MONO_TYPE_U2:
2767                 *(guint16*)ret = res;
2768                 break;
2769         case MONO_TYPE_I4:
2770                 *(gint32*)ret = res;
2771                 break;
2772         case MONO_TYPE_U4:
2773                 *(guint32*)ret = res;
2774                 break;
2775         case MONO_TYPE_I8:
2776                 *(gint64*)ret = res;
2777                 break;
2778         case MONO_TYPE_U8:
2779                 *(guint64*)ret = res;
2780                 break;
2781         case MONO_TYPE_GENERICINST:
2782                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2783                         *(gpointer*)ret = GREG_TO_PTR(res);
2784                         break;
2785                 } else {
2786                         /* Fall through */
2787                 }
2788         case MONO_TYPE_VALUETYPE:
2789                 if (dinfo->cinfo->vtype_retaddr) {
2790                         /* Nothing to do */
2791                 } else {
2792                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2793
2794                         g_assert (ainfo->storage == ArgValuetypeInReg);
2795
2796                         if (ainfo->pair_storage [0] != ArgNone) {
2797                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2798                                 ((mgreg_t*)ret)[0] = res;
2799                         }
2800
2801                         g_assert (ainfo->pair_storage [1] == ArgNone);
2802                 }
2803                 break;
2804         default:
2805                 g_assert_not_reached ();
2806         }
2807 }
2808
2809 /* emit an exception if condition is fail */
2810 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2811         do {                                                        \
2812                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2813                 if (tins == NULL) {                                                                             \
2814                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2815                                         MONO_PATCH_INFO_EXC, exc_name);  \
2816                         x86_branch32 (code, cond, 0, signed);               \
2817                 } else {        \
2818                         EMIT_COND_BRANCH (tins, cond, signed);  \
2819                 }                       \
2820         } while (0);
2821
2822 #define EMIT_FPCOMPARE(code) do { \
2823         amd64_fcompp (code); \
2824         amd64_fnstsw (code); \
2825 } while (0);
2826
2827 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2828     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2829         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2830         amd64_ ##op (code); \
2831         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2832         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2833 } while (0);
2834
2835 static guint8*
2836 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2837 {
2838         gboolean no_patch = FALSE;
2839
2840         /*
2841          * FIXME: Add support for thunks
2842          */
2843         {
2844                 gboolean near_call = FALSE;
2845
2846                 /*
2847                  * Indirect calls are expensive so try to make a near call if possible.
2848                  * The caller memory is allocated by the code manager so it is
2849                  * guaranteed to be at a 32 bit offset.
2850                  */
2851
2852                 if (patch_type != MONO_PATCH_INFO_ABS) {
2853                         /* The target is in memory allocated using the code manager */
2854                         near_call = TRUE;
2855
2856                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2857                                 if (((MonoMethod*)data)->klass->image->aot_module)
2858                                         /* The callee might be an AOT method */
2859                                         near_call = FALSE;
2860                                 if (((MonoMethod*)data)->dynamic)
2861                                         /* The target is in malloc-ed memory */
2862                                         near_call = FALSE;
2863                         }
2864
2865                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2866                                 /*
2867                                  * The call might go directly to a native function without
2868                                  * the wrapper.
2869                                  */
2870                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2871                                 if (mi) {
2872                                         gconstpointer target = mono_icall_get_wrapper (mi);
2873                                         if ((((guint64)target) >> 32) != 0)
2874                                                 near_call = FALSE;
2875                                 }
2876                         }
2877                 }
2878                 else {
2879                         MonoJumpInfo *jinfo = NULL;
2880
2881                         if (cfg->abs_patches)
2882                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2883                         if (jinfo) {
2884                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2885                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2886                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2887                                                 near_call = TRUE;
2888                                         no_patch = TRUE;
2889                                 } else {
2890                                         /*
2891                                          * This is not really an optimization, but required because the
2892                                          * generic class init trampolines use R11 to pass the vtable.
2893                                          */
2894                                         near_call = TRUE;
2895                                 }
2896                         } else {
2897                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2898                                 if (info) {
2899                                         if (info->func == info->wrapper) {
2900                                                 /* No wrapper */
2901                                                 if ((((guint64)info->func) >> 32) == 0)
2902                                                         near_call = TRUE;
2903                                         }
2904                                         else {
2905                                                 /* See the comment in mono_codegen () */
2906                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2907                                                         near_call = TRUE;
2908                                         }
2909                                 }
2910                                 else if ((((guint64)data) >> 32) == 0) {
2911                                         near_call = TRUE;
2912                                         no_patch = TRUE;
2913                                 }
2914                         }
2915                 }
2916
2917                 if (cfg->method->dynamic)
2918                         /* These methods are allocated using malloc */
2919                         near_call = FALSE;
2920
2921 #ifdef MONO_ARCH_NOMAP32BIT
2922                 near_call = FALSE;
2923 #endif
2924 #if defined(__native_client__)
2925                 /* Always use near_call == TRUE for Native Client */
2926                 near_call = TRUE;
2927 #endif
2928                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2929                 if (optimize_for_xen)
2930                         near_call = FALSE;
2931
2932                 if (cfg->compile_aot) {
2933                         near_call = TRUE;
2934                         no_patch = TRUE;
2935                 }
2936
2937                 if (near_call) {
2938                         /*
2939                          * Align the call displacement to an address divisible by 4 so it does
2940                          * not span cache lines. This is required for code patching to work on SMP
2941                          * systems.
2942                          */
2943                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2944                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2945                                 amd64_padding (code, pad_size);
2946                         }
2947                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2948                         amd64_call_code (code, 0);
2949                 }
2950                 else {
2951                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2952                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2953                         amd64_call_reg (code, GP_SCRATCH_REG);
2954                 }
2955         }
2956
2957         return code;
2958 }
2959
2960 static inline guint8*
2961 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2962 {
2963 #ifdef TARGET_WIN32
2964         if (win64_adjust_stack)
2965                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2966 #endif
2967         code = emit_call_body (cfg, code, patch_type, data);
2968 #ifdef TARGET_WIN32
2969         if (win64_adjust_stack)
2970                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2971 #endif
2972
2973         return code;
2974 }
2975
2976 static inline int
2977 store_membase_imm_to_store_membase_reg (int opcode)
2978 {
2979         switch (opcode) {
2980         case OP_STORE_MEMBASE_IMM:
2981                 return OP_STORE_MEMBASE_REG;
2982         case OP_STOREI4_MEMBASE_IMM:
2983                 return OP_STOREI4_MEMBASE_REG;
2984         case OP_STOREI8_MEMBASE_IMM:
2985                 return OP_STOREI8_MEMBASE_REG;
2986         }
2987
2988         return -1;
2989 }
2990
2991 #ifndef DISABLE_JIT
2992
2993 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2994
2995 /*
2996  * mono_arch_peephole_pass_1:
2997  *
2998  *   Perform peephole opts which should/can be performed before local regalloc
2999  */
3000 void
3001 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3002 {
3003         MonoInst *ins, *n;
3004
3005         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3006                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3007
3008                 switch (ins->opcode) {
3009                 case OP_ADD_IMM:
3010                 case OP_IADD_IMM:
3011                 case OP_LADD_IMM:
3012                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3013                                 /*
3014                                  * X86_LEA is like ADD, but doesn't have the
3015                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3016                                  * its operand to 64 bit.
3017                                  */
3018                                 ins->opcode = OP_X86_LEA_MEMBASE;
3019                                 ins->inst_basereg = ins->sreg1;
3020                         }
3021                         break;
3022                 case OP_LXOR:
3023                 case OP_IXOR:
3024                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3025                                 MonoInst *ins2;
3026
3027                                 /*
3028                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3029                                  * the latter has length 2-3 instead of 6 (reverse constant
3030                                  * propagation). These instruction sequences are very common
3031                                  * in the initlocals bblock.
3032                                  */
3033                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3034                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3035                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3036                                                 ins2->sreg1 = ins->dreg;
3037                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3038                                                 /* Continue */
3039                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3040                                                 NULLIFY_INS (ins2);
3041                                                 /* Continue */
3042                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3043                                                 /* Continue */
3044                                         } else {
3045                                                 break;
3046                                         }
3047                                 }
3048                         }
3049                         break;
3050                 case OP_COMPARE_IMM:
3051                 case OP_LCOMPARE_IMM:
3052                         /* OP_COMPARE_IMM (reg, 0)
3053                          * -->
3054                          * OP_AMD64_TEST_NULL (reg)
3055                          */
3056                         if (!ins->inst_imm)
3057                                 ins->opcode = OP_AMD64_TEST_NULL;
3058                         break;
3059                 case OP_ICOMPARE_IMM:
3060                         if (!ins->inst_imm)
3061                                 ins->opcode = OP_X86_TEST_NULL;
3062                         break;
3063                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3064                         /*
3065                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3066                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3067                          * -->
3068                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3069                          * OP_COMPARE_IMM reg, imm
3070                          *
3071                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3072                          */
3073                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3074                             ins->inst_basereg == last_ins->inst_destbasereg &&
3075                             ins->inst_offset == last_ins->inst_offset) {
3076                                         ins->opcode = OP_ICOMPARE_IMM;
3077                                         ins->sreg1 = last_ins->sreg1;
3078
3079                                         /* check if we can remove cmp reg,0 with test null */
3080                                         if (!ins->inst_imm)
3081                                                 ins->opcode = OP_X86_TEST_NULL;
3082                                 }
3083
3084                         break;
3085                 }
3086
3087                 mono_peephole_ins (bb, ins);
3088         }
3089 }
3090
3091 void
3092 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3093 {
3094         MonoInst *ins, *n;
3095
3096         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3097                 switch (ins->opcode) {
3098                 case OP_ICONST:
3099                 case OP_I8CONST: {
3100                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3101                         /* reg = 0 -> XOR (reg, reg) */
3102                         /* XOR sets cflags on x86, so we cant do it always */
3103                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3104                                 ins->opcode = OP_LXOR;
3105                                 ins->sreg1 = ins->dreg;
3106                                 ins->sreg2 = ins->dreg;
3107                                 /* Fall through */
3108                         } else {
3109                                 break;
3110                         }
3111                 }
3112                 case OP_LXOR:
3113                         /*
3114                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3115                          * 0 result into 64 bits.
3116                          */
3117                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3118                                 ins->opcode = OP_IXOR;
3119                         }
3120                         /* Fall through */
3121                 case OP_IXOR:
3122                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3123                                 MonoInst *ins2;
3124
3125                                 /*
3126                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3127                                  * the latter has length 2-3 instead of 6 (reverse constant
3128                                  * propagation). These instruction sequences are very common
3129                                  * in the initlocals bblock.
3130                                  */
3131                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3132                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3133                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3134                                                 ins2->sreg1 = ins->dreg;
3135                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3136                                                 /* Continue */
3137                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3138                                                 NULLIFY_INS (ins2);
3139                                                 /* Continue */
3140                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3141                                                 /* Continue */
3142                                         } else {
3143                                                 break;
3144                                         }
3145                                 }
3146                         }
3147                         break;
3148                 case OP_IADD_IMM:
3149                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3150                                 ins->opcode = OP_X86_INC_REG;
3151                         break;
3152                 case OP_ISUB_IMM:
3153                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3154                                 ins->opcode = OP_X86_DEC_REG;
3155                         break;
3156                 }
3157
3158                 mono_peephole_ins (bb, ins);
3159         }
3160 }
3161
3162 #define NEW_INS(cfg,ins,dest,op) do {   \
3163                 MONO_INST_NEW ((cfg), (dest), (op)); \
3164         (dest)->cil_code = (ins)->cil_code; \
3165         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3166         } while (0)
3167
3168 /*
3169  * mono_arch_lowering_pass:
3170  *
3171  *  Converts complex opcodes into simpler ones so that each IR instruction
3172  * corresponds to one machine instruction.
3173  */
3174 void
3175 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3176 {
3177         MonoInst *ins, *n, *temp;
3178
3179         /*
3180          * FIXME: Need to add more instructions, but the current machine
3181          * description can't model some parts of the composite instructions like
3182          * cdq.
3183          */
3184         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3185                 switch (ins->opcode) {
3186                 case OP_DIV_IMM:
3187                 case OP_REM_IMM:
3188                 case OP_IDIV_IMM:
3189                 case OP_IDIV_UN_IMM:
3190                 case OP_IREM_UN_IMM:
3191                 case OP_LREM_IMM:
3192                 case OP_IREM_IMM:
3193                         mono_decompose_op_imm (cfg, bb, ins);
3194                         break;
3195                 case OP_COMPARE_IMM:
3196                 case OP_LCOMPARE_IMM:
3197                         if (!amd64_use_imm32 (ins->inst_imm)) {
3198                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3199                                 temp->inst_c0 = ins->inst_imm;
3200                                 temp->dreg = mono_alloc_ireg (cfg);
3201                                 ins->opcode = OP_COMPARE;
3202                                 ins->sreg2 = temp->dreg;
3203                         }
3204                         break;
3205 #ifndef __mono_ilp32__
3206                 case OP_LOAD_MEMBASE:
3207 #endif
3208                 case OP_LOADI8_MEMBASE:
3209 #ifndef __native_client_codegen__
3210                 /*  Don't generate memindex opcodes (to simplify */
3211                 /*  read sandboxing) */
3212                         if (!amd64_use_imm32 (ins->inst_offset)) {
3213                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3214                                 temp->inst_c0 = ins->inst_offset;
3215                                 temp->dreg = mono_alloc_ireg (cfg);
3216                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3217                                 ins->inst_indexreg = temp->dreg;
3218                         }
3219 #endif
3220                         break;
3221 #ifndef __mono_ilp32__
3222                 case OP_STORE_MEMBASE_IMM:
3223 #endif
3224                 case OP_STOREI8_MEMBASE_IMM:
3225                         if (!amd64_use_imm32 (ins->inst_imm)) {
3226                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3227                                 temp->inst_c0 = ins->inst_imm;
3228                                 temp->dreg = mono_alloc_ireg (cfg);
3229                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3230                                 ins->sreg1 = temp->dreg;
3231                         }
3232                         break;
3233 #ifdef MONO_ARCH_SIMD_INTRINSICS
3234                 case OP_EXPAND_I1: {
3235                                 int temp_reg1 = mono_alloc_ireg (cfg);
3236                                 int temp_reg2 = mono_alloc_ireg (cfg);
3237                                 int original_reg = ins->sreg1;
3238
3239                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3240                                 temp->sreg1 = original_reg;
3241                                 temp->dreg = temp_reg1;
3242
3243                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3244                                 temp->sreg1 = temp_reg1;
3245                                 temp->dreg = temp_reg2;
3246                                 temp->inst_imm = 8;
3247
3248                                 NEW_INS (cfg, ins, temp, OP_LOR);
3249                                 temp->sreg1 = temp->dreg = temp_reg2;
3250                                 temp->sreg2 = temp_reg1;
3251
3252                                 ins->opcode = OP_EXPAND_I2;
3253                                 ins->sreg1 = temp_reg2;
3254                         }
3255                         break;
3256 #endif
3257                 default:
3258                         break;
3259                 }
3260         }
3261
3262         bb->max_vreg = cfg->next_vreg;
3263 }
3264
3265 static const int
3266 branch_cc_table [] = {
3267         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3268         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3269         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3270 };
3271
3272 /* Maps CMP_... constants to X86_CC_... constants */
3273 static const int
3274 cc_table [] = {
3275         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3276         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3277 };
3278
3279 static const int
3280 cc_signed_table [] = {
3281         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3282         FALSE, FALSE, FALSE, FALSE
3283 };
3284
3285 /*#include "cprop.c"*/
3286
3287 static unsigned char*
3288 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3289 {
3290         if (size == 8)
3291                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3292         else
3293                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3294
3295         if (size == 1)
3296                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3297         else if (size == 2)
3298                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3299         return code;
3300 }
3301
3302 static unsigned char*
3303 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3304 {
3305         int sreg = tree->sreg1;
3306         int need_touch = FALSE;
3307
3308 #if defined(TARGET_WIN32)
3309         need_touch = TRUE;
3310 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3311         if (!tree->flags & MONO_INST_INIT)
3312                 need_touch = TRUE;
3313 #endif
3314
3315         if (need_touch) {
3316                 guint8* br[5];
3317
3318                 /*
3319                  * Under Windows:
3320                  * If requested stack size is larger than one page,
3321                  * perform stack-touch operation
3322                  */
3323                 /*
3324                  * Generate stack probe code.
3325                  * Under Windows, it is necessary to allocate one page at a time,
3326                  * "touching" stack after each successful sub-allocation. This is
3327                  * because of the way stack growth is implemented - there is a
3328                  * guard page before the lowest stack page that is currently commited.
3329                  * Stack normally grows sequentially so OS traps access to the
3330                  * guard page and commits more pages when needed.
3331                  */
3332                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3333                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3334
3335                 br[2] = code; /* loop */
3336                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3337                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3338                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3339                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3340                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3341                 amd64_patch (br[3], br[2]);
3342                 amd64_test_reg_reg (code, sreg, sreg);
3343                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3344                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3345
3346                 br[1] = code; x86_jump8 (code, 0);
3347
3348                 amd64_patch (br[0], code);
3349                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3350                 amd64_patch (br[1], code);
3351                 amd64_patch (br[4], code);
3352         }
3353         else
3354                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3355
3356         if (tree->flags & MONO_INST_INIT) {
3357                 int offset = 0;
3358                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3359                         amd64_push_reg (code, AMD64_RAX);
3360                         offset += 8;
3361                 }
3362                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3363                         amd64_push_reg (code, AMD64_RCX);
3364                         offset += 8;
3365                 }
3366                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3367                         amd64_push_reg (code, AMD64_RDI);
3368                         offset += 8;
3369                 }
3370
3371                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3372                 if (sreg != AMD64_RCX)
3373                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3374                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3375
3376                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3377                 if (cfg->param_area)
3378                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3379                 amd64_cld (code);
3380 #if defined(__default_codegen__)
3381                 amd64_prefix (code, X86_REP_PREFIX);
3382                 amd64_stosl (code);
3383 #elif defined(__native_client_codegen__)
3384                 /* NaCl stos pseudo-instruction */
3385                 amd64_codegen_pre(code);
3386                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3387                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3388                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3389                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3390                 amd64_prefix (code, X86_REP_PREFIX);
3391                 amd64_stosl (code);
3392                 amd64_codegen_post(code);
3393 #endif /* __native_client_codegen__ */
3394
3395                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3396                         amd64_pop_reg (code, AMD64_RDI);
3397                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3398                         amd64_pop_reg (code, AMD64_RCX);
3399                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3400                         amd64_pop_reg (code, AMD64_RAX);
3401         }
3402         return code;
3403 }
3404
3405 static guint8*
3406 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3407 {
3408         CallInfo *cinfo;
3409         guint32 quad;
3410
3411         /* Move return value to the target register */
3412         /* FIXME: do this in the local reg allocator */
3413         switch (ins->opcode) {
3414         case OP_CALL:
3415         case OP_CALL_REG:
3416         case OP_CALL_MEMBASE:
3417         case OP_LCALL:
3418         case OP_LCALL_REG:
3419         case OP_LCALL_MEMBASE:
3420                 g_assert (ins->dreg == AMD64_RAX);
3421                 break;
3422         case OP_FCALL:
3423         case OP_FCALL_REG:
3424         case OP_FCALL_MEMBASE: {
3425                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3426                 if (rtype->type == MONO_TYPE_R4) {
3427                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3428                 }
3429                 else {
3430                         if (ins->dreg != AMD64_XMM0)
3431                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3432                 }
3433                 break;
3434         }
3435         case OP_RCALL:
3436         case OP_RCALL_REG:
3437         case OP_RCALL_MEMBASE:
3438                 if (ins->dreg != AMD64_XMM0)
3439                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3440                 break;
3441         case OP_VCALL:
3442         case OP_VCALL_REG:
3443         case OP_VCALL_MEMBASE:
3444         case OP_VCALL2:
3445         case OP_VCALL2_REG:
3446         case OP_VCALL2_MEMBASE:
3447                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3448                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3449                         MonoInst *loc = cfg->arch.vret_addr_loc;
3450
3451                         /* Load the destination address */
3452                         g_assert (loc->opcode == OP_REGOFFSET);
3453                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3454
3455                         for (quad = 0; quad < 2; quad ++) {
3456                                 switch (cinfo->ret.pair_storage [quad]) {
3457                                 case ArgInIReg:
3458                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3459                                         break;
3460                                 case ArgInFloatSSEReg:
3461                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3462                                         break;
3463                                 case ArgInDoubleSSEReg:
3464                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3465                                         break;
3466                                 case ArgNone:
3467                                         break;
3468                                 default:
3469                                         NOT_IMPLEMENTED;
3470                                 }
3471                         }
3472                 }
3473                 break;
3474         }
3475
3476         return code;
3477 }
3478
3479 #endif /* DISABLE_JIT */
3480
3481 #ifdef __APPLE__
3482 static int tls_gs_offset;
3483 #endif
3484
3485 gboolean
3486 mono_amd64_have_tls_get (void)
3487 {
3488 #ifdef TARGET_MACH
3489         static gboolean have_tls_get = FALSE;
3490         static gboolean inited = FALSE;
3491
3492         if (inited)
3493                 return have_tls_get;
3494
3495 #if MONO_HAVE_FAST_TLS
3496         guint8 *ins = (guint8*)pthread_getspecific;
3497
3498         /*
3499          * We're looking for these two instructions:
3500          *
3501          * mov    %gs:[offset](,%rdi,8),%rax
3502          * retq
3503          */
3504         have_tls_get = ins [0] == 0x65 &&
3505                        ins [1] == 0x48 &&
3506                        ins [2] == 0x8b &&
3507                        ins [3] == 0x04 &&
3508                        ins [4] == 0xfd &&
3509                        ins [6] == 0x00 &&
3510                        ins [7] == 0x00 &&
3511                        ins [8] == 0x00 &&
3512                        ins [9] == 0xc3;
3513
3514         tls_gs_offset = ins[5];
3515 #endif
3516
3517         inited = TRUE;
3518
3519         return have_tls_get;
3520 #elif defined(TARGET_ANDROID)
3521         return FALSE;
3522 #else
3523         return TRUE;
3524 #endif
3525 }
3526
3527 int
3528 mono_amd64_get_tls_gs_offset (void)
3529 {
3530 #ifdef TARGET_OSX
3531         return tls_gs_offset;
3532 #else
3533         g_assert_not_reached ();
3534         return -1;
3535 #endif
3536 }
3537
3538 /*
3539  * mono_amd64_emit_tls_get:
3540  * @code: buffer to store code to
3541  * @dreg: hard register where to place the result
3542  * @tls_offset: offset info
3543  *
3544  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3545  * the dreg register the item in the thread local storage identified
3546  * by tls_offset.
3547  *
3548  * Returns: a pointer to the end of the stored code
3549  */
3550 guint8*
3551 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3552 {
3553 #ifdef TARGET_WIN32
3554         if (tls_offset < 64) {
3555                 x86_prefix (code, X86_GS_PREFIX);
3556                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3557         } else {
3558                 guint8 *buf [16];
3559
3560                 g_assert (tls_offset < 0x440);
3561                 /* Load TEB->TlsExpansionSlots */
3562                 x86_prefix (code, X86_GS_PREFIX);
3563                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3564                 amd64_test_reg_reg (code, dreg, dreg);
3565                 buf [0] = code;
3566                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3567                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3568                 amd64_patch (buf [0], code);
3569         }
3570 #elif defined(__APPLE__)
3571         x86_prefix (code, X86_GS_PREFIX);
3572         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3573 #else
3574         if (optimize_for_xen) {
3575                 x86_prefix (code, X86_FS_PREFIX);
3576                 amd64_mov_reg_mem (code, dreg, 0, 8);
3577                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3578         } else {
3579                 x86_prefix (code, X86_FS_PREFIX);
3580                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3581         }
3582 #endif
3583         return code;
3584 }
3585
3586 static guint8*
3587 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3588 {
3589         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3590 #ifdef TARGET_OSX
3591         if (dreg != offset_reg)
3592                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3593         amd64_prefix (code, X86_GS_PREFIX);
3594         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3595 #elif defined(__linux__)
3596         int tmpreg = -1;
3597
3598         if (dreg == offset_reg) {
3599                 /* Use a temporary reg by saving it to the redzone */
3600                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3601                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3602                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3603                 offset_reg = tmpreg;
3604         }
3605         x86_prefix (code, X86_FS_PREFIX);
3606         amd64_mov_reg_mem (code, dreg, 0, 8);
3607         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3608         if (tmpreg != -1)
3609                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3610 #else
3611         g_assert_not_reached ();
3612 #endif
3613         return code;
3614 }
3615
3616 static guint8*
3617 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3618 {
3619 #ifdef TARGET_WIN32
3620         g_assert_not_reached ();
3621 #elif defined(__APPLE__)
3622         x86_prefix (code, X86_GS_PREFIX);
3623         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3624 #else
3625         g_assert (!optimize_for_xen);
3626         x86_prefix (code, X86_FS_PREFIX);
3627         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3628 #endif
3629         return code;
3630 }
3631
3632 static guint8*
3633 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3634 {
3635         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3636 #ifdef TARGET_WIN32
3637         g_assert_not_reached ();
3638 #elif defined(__APPLE__)
3639         x86_prefix (code, X86_GS_PREFIX);
3640         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3641 #else
3642         x86_prefix (code, X86_FS_PREFIX);
3643         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3644 #endif
3645         return code;
3646 }
3647
3648  /*
3649  * mono_arch_translate_tls_offset:
3650  *
3651  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3652  */
3653 int
3654 mono_arch_translate_tls_offset (int offset)
3655 {
3656 #ifdef __APPLE__
3657         return tls_gs_offset + (offset * 8);
3658 #else
3659         return offset;
3660 #endif
3661 }
3662
3663 /*
3664  * emit_setup_lmf:
3665  *
3666  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3667  */
3668 static guint8*
3669 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3670 {
3671         /*
3672          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3673          */
3674         /*
3675          * sp is saved right before calls but we need to save it here too so
3676          * async stack walks would work.
3677          */
3678         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3679         /* Save rbp */
3680         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3681         if (cfg->arch.omit_fp && cfa_offset != -1)
3682                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3683
3684         /* These can't contain refs */
3685         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3686         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3687         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3688         /* These are handled automatically by the stack marking code */
3689         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3690
3691         return code;
3692 }
3693
3694 #define REAL_PRINT_REG(text,reg) \
3695 mono_assert (reg >= 0); \
3696 amd64_push_reg (code, AMD64_RAX); \
3697 amd64_push_reg (code, AMD64_RDX); \
3698 amd64_push_reg (code, AMD64_RCX); \
3699 amd64_push_reg (code, reg); \
3700 amd64_push_imm (code, reg); \
3701 amd64_push_imm (code, text " %d %p\n"); \
3702 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3703 amd64_call_reg (code, AMD64_RAX); \
3704 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3705 amd64_pop_reg (code, AMD64_RCX); \
3706 amd64_pop_reg (code, AMD64_RDX); \
3707 amd64_pop_reg (code, AMD64_RAX);
3708
3709 /* benchmark and set based on cpu */
3710 #define LOOP_ALIGNMENT 8
3711 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3712
3713 #ifndef DISABLE_JIT
3714 void
3715 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3716 {
3717         MonoInst *ins;
3718         MonoCallInst *call;
3719         guint offset;
3720         guint8 *code = cfg->native_code + cfg->code_len;
3721         int max_len;
3722
3723         /* Fix max_offset estimate for each successor bb */
3724         if (cfg->opt & MONO_OPT_BRANCH) {
3725                 int current_offset = cfg->code_len;
3726                 MonoBasicBlock *current_bb;
3727                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3728                         current_bb->max_offset = current_offset;
3729                         current_offset += current_bb->max_length;
3730                 }
3731         }
3732
3733         if (cfg->opt & MONO_OPT_LOOP) {
3734                 int pad, align = LOOP_ALIGNMENT;
3735                 /* set alignment depending on cpu */
3736                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3737                         pad = align - pad;
3738                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3739                         amd64_padding (code, pad);
3740                         cfg->code_len += pad;
3741                         bb->native_offset = cfg->code_len;
3742                 }
3743         }
3744
3745 #if defined(__native_client_codegen__)
3746         /* For Native Client, all indirect call/jump targets must be */
3747         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3748         /* indirectly as well.                                       */
3749         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3750                                       (bb->flags & BB_EXCEPTION_HANDLER);
3751
3752         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3753                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3754                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3755                 cfg->code_len += pad;
3756                 bb->native_offset = cfg->code_len;
3757         }
3758 #endif  /*__native_client_codegen__*/
3759
3760         if (cfg->verbose_level > 2)
3761                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3762
3763         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3764                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3765                 g_assert (!cfg->compile_aot);
3766
3767                 cov->data [bb->dfn].cil_code = bb->cil_code;
3768                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3769                 /* this is not thread save, but good enough */
3770                 amd64_inc_membase (code, AMD64_R11, 0);
3771         }
3772
3773         offset = code - cfg->native_code;
3774
3775         mono_debug_open_block (cfg, bb, offset);
3776
3777     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3778                 x86_breakpoint (code);
3779
3780         MONO_BB_FOR_EACH_INS (bb, ins) {
3781                 offset = code - cfg->native_code;
3782
3783                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3784
3785 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3786
3787                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3788                         cfg->code_size *= 2;
3789                         cfg->native_code = mono_realloc_native_code(cfg);
3790                         code = cfg->native_code + offset;
3791                         cfg->stat_code_reallocs++;
3792                 }
3793
3794                 if (cfg->debug_info)
3795                         mono_debug_record_line_number (cfg, ins, offset);
3796
3797                 switch (ins->opcode) {
3798                 case OP_BIGMUL:
3799                         amd64_mul_reg (code, ins->sreg2, TRUE);
3800                         break;
3801                 case OP_BIGMUL_UN:
3802                         amd64_mul_reg (code, ins->sreg2, FALSE);
3803                         break;
3804                 case OP_X86_SETEQ_MEMBASE:
3805                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3806                         break;
3807                 case OP_STOREI1_MEMBASE_IMM:
3808                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3809                         break;
3810                 case OP_STOREI2_MEMBASE_IMM:
3811                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3812                         break;
3813                 case OP_STOREI4_MEMBASE_IMM:
3814                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3815                         break;
3816                 case OP_STOREI1_MEMBASE_REG:
3817                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3818                         break;
3819                 case OP_STOREI2_MEMBASE_REG:
3820                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3821                         break;
3822                 /* In AMD64 NaCl, pointers are 4 bytes, */
3823                 /*  so STORE_* != STOREI8_*. Likewise below. */
3824                 case OP_STORE_MEMBASE_REG:
3825                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3826                         break;
3827                 case OP_STOREI8_MEMBASE_REG:
3828                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3829                         break;
3830                 case OP_STOREI4_MEMBASE_REG:
3831                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3832                         break;
3833                 case OP_STORE_MEMBASE_IMM:
3834 #ifndef __native_client_codegen__
3835                         /* In NaCl, this could be a PCONST type, which could */
3836                         /* mean a pointer type was copied directly into the  */
3837                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3838                         /* the value would be 0x00000000FFFFFFFF which is    */
3839                         /* not proper for an imm32 unless you cast it.       */
3840                         g_assert (amd64_is_imm32 (ins->inst_imm));
3841 #endif
3842                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3843                         break;
3844                 case OP_STOREI8_MEMBASE_IMM:
3845                         g_assert (amd64_is_imm32 (ins->inst_imm));
3846                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3847                         break;
3848                 case OP_LOAD_MEM:
3849 #ifdef __mono_ilp32__
3850                         /* In ILP32, pointers are 4 bytes, so separate these */
3851                         /* cases, use literal 8 below where we really want 8 */
3852                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3853                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3854                         break;
3855 #endif
3856                 case OP_LOADI8_MEM:
3857                         // FIXME: Decompose this earlier
3858                         if (amd64_use_imm32 (ins->inst_imm))
3859                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3860                         else {
3861                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3862                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3863                         }
3864                         break;
3865                 case OP_LOADI4_MEM:
3866                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3867                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3868                         break;
3869                 case OP_LOADU4_MEM:
3870                         // FIXME: Decompose this earlier
3871                         if (amd64_use_imm32 (ins->inst_imm))
3872                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3873                         else {
3874                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3875                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3876                         }
3877                         break;
3878                 case OP_LOADU1_MEM:
3879                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3880                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3881                         break;
3882                 case OP_LOADU2_MEM:
3883                         /* For NaCl, pointers are 4 bytes, so separate these */
3884                         /* cases, use literal 8 below where we really want 8 */
3885                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3886                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3887                         break;
3888                 case OP_LOAD_MEMBASE:
3889                         g_assert (amd64_is_imm32 (ins->inst_offset));
3890                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3891                         break;
3892                 case OP_LOADI8_MEMBASE:
3893                         /* Use literal 8 instead of sizeof pointer or */
3894                         /* register, we really want 8 for this opcode */
3895                         g_assert (amd64_is_imm32 (ins->inst_offset));
3896                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3897                         break;
3898                 case OP_LOADI4_MEMBASE:
3899                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3900                         break;
3901                 case OP_LOADU4_MEMBASE:
3902                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3903                         break;
3904                 case OP_LOADU1_MEMBASE:
3905                         /* The cpu zero extends the result into 64 bits */
3906                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3907                         break;
3908                 case OP_LOADI1_MEMBASE:
3909                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3910                         break;
3911                 case OP_LOADU2_MEMBASE:
3912                         /* The cpu zero extends the result into 64 bits */
3913                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3914                         break;
3915                 case OP_LOADI2_MEMBASE:
3916                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3917                         break;
3918                 case OP_AMD64_LOADI8_MEMINDEX:
3919                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3920                         break;
3921                 case OP_LCONV_TO_I1:
3922                 case OP_ICONV_TO_I1:
3923                 case OP_SEXT_I1:
3924                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3925                         break;
3926                 case OP_LCONV_TO_I2:
3927                 case OP_ICONV_TO_I2:
3928                 case OP_SEXT_I2:
3929                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3930                         break;
3931                 case OP_LCONV_TO_U1:
3932                 case OP_ICONV_TO_U1:
3933                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3934                         break;
3935                 case OP_LCONV_TO_U2:
3936                 case OP_ICONV_TO_U2:
3937                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3938                         break;
3939                 case OP_ZEXT_I4:
3940                         /* Clean out the upper word */
3941                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3942                         break;
3943                 case OP_SEXT_I4:
3944                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3945                         break;
3946                 case OP_COMPARE:
3947                 case OP_LCOMPARE:
3948                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3949                         break;
3950                 case OP_COMPARE_IMM:
3951 #if defined(__mono_ilp32__)
3952                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3953                         g_assert (amd64_is_imm32 (ins->inst_imm));
3954                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3955                         break;
3956 #endif
3957                 case OP_LCOMPARE_IMM:
3958                         g_assert (amd64_is_imm32 (ins->inst_imm));
3959                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3960                         break;
3961                 case OP_X86_COMPARE_REG_MEMBASE:
3962                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3963                         break;
3964                 case OP_X86_TEST_NULL:
3965                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3966                         break;
3967                 case OP_AMD64_TEST_NULL:
3968                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3969                         break;
3970
3971                 case OP_X86_ADD_REG_MEMBASE:
3972                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3973                         break;
3974                 case OP_X86_SUB_REG_MEMBASE:
3975                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3976                         break;
3977                 case OP_X86_AND_REG_MEMBASE:
3978                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3979                         break;
3980                 case OP_X86_OR_REG_MEMBASE:
3981                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3982                         break;
3983                 case OP_X86_XOR_REG_MEMBASE:
3984                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3985                         break;
3986
3987                 case OP_X86_ADD_MEMBASE_IMM:
3988                         /* FIXME: Make a 64 version too */
3989                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3990                         break;
3991                 case OP_X86_SUB_MEMBASE_IMM:
3992                         g_assert (amd64_is_imm32 (ins->inst_imm));
3993                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3994                         break;
3995                 case OP_X86_AND_MEMBASE_IMM:
3996                         g_assert (amd64_is_imm32 (ins->inst_imm));
3997                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3998                         break;
3999                 case OP_X86_OR_MEMBASE_IMM:
4000                         g_assert (amd64_is_imm32 (ins->inst_imm));
4001                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4002                         break;
4003                 case OP_X86_XOR_MEMBASE_IMM:
4004                         g_assert (amd64_is_imm32 (ins->inst_imm));
4005                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4006                         break;
4007                 case OP_X86_ADD_MEMBASE_REG:
4008                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4009                         break;
4010                 case OP_X86_SUB_MEMBASE_REG:
4011                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4012                         break;
4013                 case OP_X86_AND_MEMBASE_REG:
4014                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4015                         break;
4016                 case OP_X86_OR_MEMBASE_REG:
4017                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4018                         break;
4019                 case OP_X86_XOR_MEMBASE_REG:
4020                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4021                         break;
4022                 case OP_X86_INC_MEMBASE:
4023                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4024                         break;
4025                 case OP_X86_INC_REG:
4026                         amd64_inc_reg_size (code, ins->dreg, 4);
4027                         break;
4028                 case OP_X86_DEC_MEMBASE:
4029                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4030                         break;
4031                 case OP_X86_DEC_REG:
4032                         amd64_dec_reg_size (code, ins->dreg, 4);
4033                         break;
4034                 case OP_X86_MUL_REG_MEMBASE:
4035                 case OP_X86_MUL_MEMBASE_REG:
4036                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4037                         break;
4038                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4039                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4040                         break;
4041                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4042                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4043                         break;
4044                 case OP_AMD64_COMPARE_MEMBASE_REG:
4045                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4046                         break;
4047                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4048                         g_assert (amd64_is_imm32 (ins->inst_imm));
4049                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4050                         break;
4051                 case OP_X86_COMPARE_MEMBASE8_IMM:
4052                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4053                         break;
4054                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4055                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4056                         break;
4057                 case OP_AMD64_COMPARE_REG_MEMBASE:
4058                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4059                         break;
4060
4061                 case OP_AMD64_ADD_REG_MEMBASE:
4062                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4063                         break;
4064                 case OP_AMD64_SUB_REG_MEMBASE:
4065                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4066                         break;
4067                 case OP_AMD64_AND_REG_MEMBASE:
4068                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4069                         break;
4070                 case OP_AMD64_OR_REG_MEMBASE:
4071                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4072                         break;
4073                 case OP_AMD64_XOR_REG_MEMBASE:
4074                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4075                         break;
4076
4077                 case OP_AMD64_ADD_MEMBASE_REG:
4078                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4079                         break;
4080                 case OP_AMD64_SUB_MEMBASE_REG:
4081                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4082                         break;
4083                 case OP_AMD64_AND_MEMBASE_REG:
4084                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4085                         break;
4086                 case OP_AMD64_OR_MEMBASE_REG:
4087                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4088                         break;
4089                 case OP_AMD64_XOR_MEMBASE_REG:
4090                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4091                         break;
4092
4093                 case OP_AMD64_ADD_MEMBASE_IMM:
4094                         g_assert (amd64_is_imm32 (ins->inst_imm));
4095                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4096                         break;
4097                 case OP_AMD64_SUB_MEMBASE_IMM:
4098                         g_assert (amd64_is_imm32 (ins->inst_imm));
4099                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4100                         break;
4101                 case OP_AMD64_AND_MEMBASE_IMM:
4102                         g_assert (amd64_is_imm32 (ins->inst_imm));
4103                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4104                         break;
4105                 case OP_AMD64_OR_MEMBASE_IMM:
4106                         g_assert (amd64_is_imm32 (ins->inst_imm));
4107                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4108                         break;
4109                 case OP_AMD64_XOR_MEMBASE_IMM:
4110                         g_assert (amd64_is_imm32 (ins->inst_imm));
4111                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4112                         break;
4113
4114                 case OP_BREAK:
4115                         amd64_breakpoint (code);
4116                         break;
4117                 case OP_RELAXED_NOP:
4118                         x86_prefix (code, X86_REP_PREFIX);
4119                         x86_nop (code);
4120                         break;
4121                 case OP_HARD_NOP:
4122                         x86_nop (code);
4123                         break;
4124                 case OP_NOP:
4125                 case OP_DUMMY_USE:
4126                 case OP_DUMMY_STORE:
4127                 case OP_DUMMY_ICONST:
4128                 case OP_DUMMY_R8CONST:
4129                 case OP_NOT_REACHED:
4130                 case OP_NOT_NULL:
4131                         break;
4132                 case OP_IL_SEQ_POINT:
4133                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4134                         break;
4135                 case OP_SEQ_POINT: {
4136                         int i;
4137
4138                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4139                                 if (cfg->compile_aot) {
4140                                         MonoInst *var = cfg->arch.ss_tramp_var;
4141                                         guint8 *label;
4142
4143                                         /* Load ss_tramp_var */
4144                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4145                                         /* Load the trampoline address */
4146                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4147                                         /* Call it if it is non-null */
4148                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4149                                         label = code;
4150                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4151                                         amd64_call_reg (code, AMD64_R11);
4152                                         amd64_patch (label, code);
4153                                 } else {
4154                                         /*
4155                                          * Read from the single stepping trigger page. This will cause a
4156                                          * SIGSEGV when single stepping is enabled.
4157                                          * We do this _before_ the breakpoint, so single stepping after
4158                                          * a breakpoint is hit will step to the next IL offset.
4159                                          */
4160                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4161
4162                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4163                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4164                                 }
4165                         }
4166
4167                         /*
4168                          * This is the address which is saved in seq points,
4169                          */
4170                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4171
4172                         if (cfg->compile_aot) {
4173                                 guint32 offset = code - cfg->native_code;
4174                                 guint32 val;
4175                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4176                                 guint8 *label;
4177
4178                                 /* Load info var */
4179                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4180                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4181                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4182                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4183                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4184                                 label = code;
4185                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4186                                 /* Call the trampoline */
4187                                 amd64_call_reg (code, AMD64_R11);
4188                                 amd64_patch (label, code);
4189                         } else {
4190                                 /*
4191                                  * A placeholder for a possible breakpoint inserted by
4192                                  * mono_arch_set_breakpoint ().
4193                                  */
4194                                 for (i = 0; i < breakpoint_size; ++i)
4195                                         x86_nop (code);
4196                         }
4197                         /*
4198                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4199                          * to another IL offset.
4200                          */
4201                         x86_nop (code);
4202                         break;
4203                 }
4204                 case OP_ADDCC:
4205                 case OP_LADDCC:
4206                 case OP_LADD:
4207                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4208                         break;
4209                 case OP_ADC:
4210                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4211                         break;
4212                 case OP_ADD_IMM:
4213                 case OP_LADD_IMM:
4214                         g_assert (amd64_is_imm32 (ins->inst_imm));
4215                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4216                         break;
4217                 case OP_ADC_IMM:
4218                         g_assert (amd64_is_imm32 (ins->inst_imm));
4219                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4220                         break;
4221                 case OP_SUBCC:
4222                 case OP_LSUBCC:
4223                 case OP_LSUB:
4224                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4225                         break;
4226                 case OP_SBB:
4227                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4228                         break;
4229                 case OP_SUB_IMM:
4230                 case OP_LSUB_IMM:
4231                         g_assert (amd64_is_imm32 (ins->inst_imm));
4232                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4233                         break;
4234                 case OP_SBB_IMM:
4235                         g_assert (amd64_is_imm32 (ins->inst_imm));
4236                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4237                         break;
4238                 case OP_LAND:
4239                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4240                         break;
4241                 case OP_AND_IMM:
4242                 case OP_LAND_IMM:
4243                         g_assert (amd64_is_imm32 (ins->inst_imm));
4244                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4245                         break;
4246                 case OP_LMUL:
4247                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4248                         break;
4249                 case OP_MUL_IMM:
4250                 case OP_LMUL_IMM:
4251                 case OP_IMUL_IMM: {
4252                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4253
4254                         switch (ins->inst_imm) {
4255                         case 2:
4256                                 /* MOV r1, r2 */
4257                                 /* ADD r1, r1 */
4258                                 if (ins->dreg != ins->sreg1)
4259                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4260                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4261                                 break;
4262                         case 3:
4263                                 /* LEA r1, [r2 + r2*2] */
4264                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4265                                 break;
4266                         case 5:
4267                                 /* LEA r1, [r2 + r2*4] */
4268                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4269                                 break;
4270                         case 6:
4271                                 /* LEA r1, [r2 + r2*2] */
4272                                 /* ADD r1, r1          */
4273                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4274                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4275                                 break;
4276                         case 9:
4277                                 /* LEA r1, [r2 + r2*8] */
4278                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4279                                 break;
4280                         case 10:
4281                                 /* LEA r1, [r2 + r2*4] */
4282                                 /* ADD r1, r1          */
4283                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4284                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4285                                 break;
4286                         case 12:
4287                                 /* LEA r1, [r2 + r2*2] */
4288                                 /* SHL r1, 2           */
4289                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4290                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4291                                 break;
4292                         case 25:
4293                                 /* LEA r1, [r2 + r2*4] */
4294                                 /* LEA r1, [r1 + r1*4] */
4295                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4296                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4297                                 break;
4298                         case 100:
4299                                 /* LEA r1, [r2 + r2*4] */
4300                                 /* SHL r1, 2           */
4301                                 /* LEA r1, [r1 + r1*4] */
4302                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4303                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4304                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4305                                 break;
4306                         default:
4307                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4308                                 break;
4309                         }
4310                         break;
4311                 }
4312                 case OP_LDIV:
4313                 case OP_LREM:
4314 #if defined( __native_client_codegen__ )
4315                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4316                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4317 #endif
4318                         /* Regalloc magic makes the div/rem cases the same */
4319                         if (ins->sreg2 == AMD64_RDX) {
4320                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4321                                 amd64_cdq (code);
4322                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4323                         } else {
4324                                 amd64_cdq (code);
4325                                 amd64_div_reg (code, ins->sreg2, TRUE);
4326                         }
4327                         break;
4328                 case OP_LDIV_UN:
4329                 case OP_LREM_UN:
4330 #if defined( __native_client_codegen__ )
4331                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4332                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4333 #endif
4334                         if (ins->sreg2 == AMD64_RDX) {
4335                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4336                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4337                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4338                         } else {
4339                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4340                                 amd64_div_reg (code, ins->sreg2, FALSE);
4341                         }
4342                         break;
4343                 case OP_IDIV:
4344                 case OP_IREM:
4345 #if defined( __native_client_codegen__ )
4346                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4347                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4348 #endif
4349                         if (ins->sreg2 == AMD64_RDX) {
4350                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4351                                 amd64_cdq_size (code, 4);
4352                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4353                         } else {
4354                                 amd64_cdq_size (code, 4);
4355                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4356                         }
4357                         break;
4358                 case OP_IDIV_UN:
4359                 case OP_IREM_UN:
4360 #if defined( __native_client_codegen__ )
4361                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4362                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4363 #endif
4364                         if (ins->sreg2 == AMD64_RDX) {
4365                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4366                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4367                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4368                         } else {
4369                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4370                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4371                         }
4372                         break;
4373                 case OP_LMUL_OVF:
4374                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4375                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4376                         break;
4377                 case OP_LOR:
4378                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4379                         break;
4380                 case OP_OR_IMM:
4381                 case OP_LOR_IMM:
4382                         g_assert (amd64_is_imm32 (ins->inst_imm));
4383                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4384                         break;
4385                 case OP_LXOR:
4386                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4387                         break;
4388                 case OP_XOR_IMM:
4389                 case OP_LXOR_IMM:
4390                         g_assert (amd64_is_imm32 (ins->inst_imm));
4391                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4392                         break;
4393                 case OP_LSHL:
4394                         g_assert (ins->sreg2 == AMD64_RCX);
4395                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4396                         break;
4397                 case OP_LSHR:
4398                         g_assert (ins->sreg2 == AMD64_RCX);
4399                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4400                         break;
4401                 case OP_SHR_IMM:
4402                 case OP_LSHR_IMM:
4403                         g_assert (amd64_is_imm32 (ins->inst_imm));
4404                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4405                         break;
4406                 case OP_SHR_UN_IMM:
4407                         g_assert (amd64_is_imm32 (ins->inst_imm));
4408                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4409                         break;
4410                 case OP_LSHR_UN_IMM:
4411                         g_assert (amd64_is_imm32 (ins->inst_imm));
4412                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4413                         break;
4414                 case OP_LSHR_UN:
4415                         g_assert (ins->sreg2 == AMD64_RCX);
4416                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4417                         break;
4418                 case OP_SHL_IMM:
4419                 case OP_LSHL_IMM:
4420                         g_assert (amd64_is_imm32 (ins->inst_imm));
4421                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4422                         break;
4423
4424                 case OP_IADDCC:
4425                 case OP_IADD:
4426                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4427                         break;
4428                 case OP_IADC:
4429                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4430                         break;
4431                 case OP_IADD_IMM:
4432                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4433                         break;
4434                 case OP_IADC_IMM:
4435                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4436                         break;
4437                 case OP_ISUBCC:
4438                 case OP_ISUB:
4439                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4440                         break;
4441                 case OP_ISBB:
4442                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4443                         break;
4444                 case OP_ISUB_IMM:
4445                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4446                         break;
4447                 case OP_ISBB_IMM:
4448                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4449                         break;
4450                 case OP_IAND:
4451                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4452                         break;
4453                 case OP_IAND_IMM:
4454                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4455                         break;
4456                 case OP_IOR:
4457                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4458                         break;
4459                 case OP_IOR_IMM:
4460                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4461                         break;
4462                 case OP_IXOR:
4463                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4464                         break;
4465                 case OP_IXOR_IMM:
4466                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4467                         break;
4468                 case OP_INEG:
4469                         amd64_neg_reg_size (code, ins->sreg1, 4);
4470                         break;
4471                 case OP_INOT:
4472                         amd64_not_reg_size (code, ins->sreg1, 4);
4473                         break;
4474                 case OP_ISHL:
4475                         g_assert (ins->sreg2 == AMD64_RCX);
4476                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4477                         break;
4478                 case OP_ISHR:
4479                         g_assert (ins->sreg2 == AMD64_RCX);
4480                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4481                         break;
4482                 case OP_ISHR_IMM:
4483                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4484                         break;
4485                 case OP_ISHR_UN_IMM:
4486                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4487                         break;
4488                 case OP_ISHR_UN:
4489                         g_assert (ins->sreg2 == AMD64_RCX);
4490                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4491                         break;
4492                 case OP_ISHL_IMM:
4493                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4494                         break;
4495                 case OP_IMUL:
4496                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4497                         break;
4498                 case OP_IMUL_OVF:
4499                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4500                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4501                         break;
4502                 case OP_IMUL_OVF_UN:
4503                 case OP_LMUL_OVF_UN: {
4504                         /* the mul operation and the exception check should most likely be split */
4505                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4506                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4507                         /*g_assert (ins->sreg2 == X86_EAX);
4508                         g_assert (ins->dreg == X86_EAX);*/
4509                         if (ins->sreg2 == X86_EAX) {
4510                                 non_eax_reg = ins->sreg1;
4511                         } else if (ins->sreg1 == X86_EAX) {
4512                                 non_eax_reg = ins->sreg2;
4513                         } else {
4514                                 /* no need to save since we're going to store to it anyway */
4515                                 if (ins->dreg != X86_EAX) {
4516                                         saved_eax = TRUE;
4517                                         amd64_push_reg (code, X86_EAX);
4518                                 }
4519                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4520                                 non_eax_reg = ins->sreg2;
4521                         }
4522                         if (ins->dreg == X86_EDX) {
4523                                 if (!saved_eax) {
4524                                         saved_eax = TRUE;
4525                                         amd64_push_reg (code, X86_EAX);
4526                                 }
4527                         } else {
4528                                 saved_edx = TRUE;
4529                                 amd64_push_reg (code, X86_EDX);
4530                         }
4531                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4532                         /* save before the check since pop and mov don't change the flags */
4533                         if (ins->dreg != X86_EAX)
4534                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4535                         if (saved_edx)
4536                                 amd64_pop_reg (code, X86_EDX);
4537                         if (saved_eax)
4538                                 amd64_pop_reg (code, X86_EAX);
4539                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4540                         break;
4541                 }
4542                 case OP_ICOMPARE:
4543                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4544                         break;
4545                 case OP_ICOMPARE_IMM:
4546                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4547                         break;
4548                 case OP_IBEQ:
4549                 case OP_IBLT:
4550                 case OP_IBGT:
4551                 case OP_IBGE:
4552                 case OP_IBLE:
4553                 case OP_LBEQ:
4554                 case OP_LBLT:
4555                 case OP_LBGT:
4556                 case OP_LBGE:
4557                 case OP_LBLE:
4558                 case OP_IBNE_UN:
4559                 case OP_IBLT_UN:
4560                 case OP_IBGT_UN:
4561                 case OP_IBGE_UN:
4562                 case OP_IBLE_UN:
4563                 case OP_LBNE_UN:
4564                 case OP_LBLT_UN:
4565                 case OP_LBGT_UN:
4566                 case OP_LBGE_UN:
4567                 case OP_LBLE_UN:
4568                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4569                         break;
4570
4571                 case OP_CMOV_IEQ:
4572                 case OP_CMOV_IGE:
4573                 case OP_CMOV_IGT:
4574                 case OP_CMOV_ILE:
4575                 case OP_CMOV_ILT:
4576                 case OP_CMOV_INE_UN:
4577                 case OP_CMOV_IGE_UN:
4578                 case OP_CMOV_IGT_UN:
4579                 case OP_CMOV_ILE_UN:
4580                 case OP_CMOV_ILT_UN:
4581                 case OP_CMOV_LEQ:
4582                 case OP_CMOV_LGE:
4583                 case OP_CMOV_LGT:
4584                 case OP_CMOV_LLE:
4585                 case OP_CMOV_LLT:
4586                 case OP_CMOV_LNE_UN:
4587                 case OP_CMOV_LGE_UN:
4588                 case OP_CMOV_LGT_UN:
4589                 case OP_CMOV_LLE_UN:
4590                 case OP_CMOV_LLT_UN:
4591                         g_assert (ins->dreg == ins->sreg1);
4592                         /* This needs to operate on 64 bit values */
4593                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4594                         break;
4595
4596                 case OP_LNOT:
4597                         amd64_not_reg (code, ins->sreg1);
4598                         break;
4599                 case OP_LNEG:
4600                         amd64_neg_reg (code, ins->sreg1);
4601                         break;
4602
4603                 case OP_ICONST:
4604                 case OP_I8CONST:
4605                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4606                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4607                         else
4608                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4609                         break;
4610                 case OP_AOTCONST:
4611                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4612                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4613                         break;
4614                 case OP_JUMP_TABLE:
4615                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4616                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4617                         break;
4618                 case OP_MOVE:
4619                         if (ins->dreg != ins->sreg1)
4620                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4621                         break;
4622                 case OP_AMD64_SET_XMMREG_R4: {
4623                         if (cfg->r4fp) {
4624                                 if (ins->dreg != ins->sreg1)
4625                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4626                         } else {
4627                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4628                         }
4629                         break;
4630                 }
4631                 case OP_AMD64_SET_XMMREG_R8: {
4632                         if (ins->dreg != ins->sreg1)
4633                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4634                         break;
4635                 }
4636                 case OP_TAILCALL: {
4637                         MonoCallInst *call = (MonoCallInst*)ins;
4638                         int i, save_area_offset;
4639
4640                         g_assert (!cfg->method->save_lmf);
4641
4642                         /* Restore callee saved registers */
4643                         save_area_offset = cfg->arch.reg_save_area_offset;
4644                         for (i = 0; i < AMD64_NREG; ++i)
4645                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4646                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4647                                         save_area_offset += 8;
4648                                 }
4649
4650                         if (cfg->arch.omit_fp) {
4651                                 if (cfg->arch.stack_alloc_size)
4652                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4653                                 // FIXME:
4654                                 if (call->stack_usage)
4655                                         NOT_IMPLEMENTED;
4656                         } else {
4657                                 /* Copy arguments on the stack to our argument area */
4658                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4659                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4660                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4661                                 }
4662
4663                                 amd64_leave (code);
4664                         }
4665
4666                         offset = code - cfg->native_code;
4667                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4668                         if (cfg->compile_aot)
4669                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4670                         else
4671                                 amd64_set_reg_template (code, AMD64_R11);
4672                         amd64_jump_reg (code, AMD64_R11);
4673                         ins->flags |= MONO_INST_GC_CALLSITE;
4674                         ins->backend.pc_offset = code - cfg->native_code;
4675                         break;
4676                 }
4677                 case OP_CHECK_THIS:
4678                         /* ensure ins->sreg1 is not NULL */
4679                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4680                         break;
4681                 case OP_ARGLIST: {
4682                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4683                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4684                         break;
4685                 }
4686                 case OP_CALL:
4687                 case OP_FCALL:
4688                 case OP_RCALL:
4689                 case OP_LCALL:
4690                 case OP_VCALL:
4691                 case OP_VCALL2:
4692                 case OP_VOIDCALL:
4693                         call = (MonoCallInst*)ins;
4694                         /*
4695                          * The AMD64 ABI forces callers to know about varargs.
4696                          */
4697                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4698                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4699                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4700                                 /*
4701                                  * Since the unmanaged calling convention doesn't contain a
4702                                  * 'vararg' entry, we have to treat every pinvoke call as a
4703                                  * potential vararg call.
4704                                  */
4705                                 guint32 nregs, i;
4706                                 nregs = 0;
4707                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4708                                         if (call->used_fregs & (1 << i))
4709                                                 nregs ++;
4710                                 if (!nregs)
4711                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4712                                 else
4713                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4714                         }
4715
4716                         if (ins->flags & MONO_INST_HAS_METHOD)
4717                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4718                         else
4719                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4720                         ins->flags |= MONO_INST_GC_CALLSITE;
4721                         ins->backend.pc_offset = code - cfg->native_code;
4722                         code = emit_move_return_value (cfg, ins, code);
4723                         break;
4724                 case OP_FCALL_REG:
4725                 case OP_RCALL_REG:
4726                 case OP_LCALL_REG:
4727                 case OP_VCALL_REG:
4728                 case OP_VCALL2_REG:
4729                 case OP_VOIDCALL_REG:
4730                 case OP_CALL_REG:
4731                         call = (MonoCallInst*)ins;
4732
4733                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4734                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4735                                 ins->sreg1 = AMD64_R11;
4736                         }
4737
4738                         /*
4739                          * The AMD64 ABI forces callers to know about varargs.
4740                          */
4741                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4742                                 if (ins->sreg1 == AMD64_RAX) {
4743                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4744                                         ins->sreg1 = AMD64_R11;
4745                                 }
4746                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4747                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4748                                 /*
4749                                  * Since the unmanaged calling convention doesn't contain a
4750                                  * 'vararg' entry, we have to treat every pinvoke call as a
4751                                  * potential vararg call.
4752                                  */
4753                                 guint32 nregs, i;
4754                                 nregs = 0;
4755                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4756                                         if (call->used_fregs & (1 << i))
4757                                                 nregs ++;
4758                                 if (ins->sreg1 == AMD64_RAX) {
4759                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4760                                         ins->sreg1 = AMD64_R11;
4761                                 }
4762                                 if (!nregs)
4763                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4764                                 else
4765                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4766                         }
4767
4768                         amd64_call_reg (code, ins->sreg1);
4769                         ins->flags |= MONO_INST_GC_CALLSITE;
4770                         ins->backend.pc_offset = code - cfg->native_code;
4771                         code = emit_move_return_value (cfg, ins, code);
4772                         break;
4773                 case OP_FCALL_MEMBASE:
4774                 case OP_RCALL_MEMBASE:
4775                 case OP_LCALL_MEMBASE:
4776                 case OP_VCALL_MEMBASE:
4777                 case OP_VCALL2_MEMBASE:
4778                 case OP_VOIDCALL_MEMBASE:
4779                 case OP_CALL_MEMBASE:
4780                         call = (MonoCallInst*)ins;
4781
4782                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4783                         ins->flags |= MONO_INST_GC_CALLSITE;
4784                         ins->backend.pc_offset = code - cfg->native_code;
4785                         code = emit_move_return_value (cfg, ins, code);
4786                         break;
4787                 case OP_DYN_CALL: {
4788                         int i;
4789                         MonoInst *var = cfg->dyn_call_var;
4790
4791                         g_assert (var->opcode == OP_REGOFFSET);
4792
4793                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4794                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4795                         /* r10 = ftn */
4796                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4797
4798                         /* Save args buffer */
4799                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4800
4801                         /* Set argument registers */
4802                         for (i = 0; i < PARAM_REGS; ++i)
4803                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4804
4805                         /* Make the call */
4806                         amd64_call_reg (code, AMD64_R10);
4807
4808                         ins->flags |= MONO_INST_GC_CALLSITE;
4809                         ins->backend.pc_offset = code - cfg->native_code;
4810
4811                         /* Save result */
4812                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4813                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4814                         break;
4815                 }
4816                 case OP_AMD64_SAVE_SP_TO_LMF: {
4817                         MonoInst *lmf_var = cfg->lmf_var;
4818                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4819                         break;
4820                 }
4821                 case OP_X86_PUSH:
4822                         g_assert_not_reached ();
4823                         amd64_push_reg (code, ins->sreg1);
4824                         break;
4825                 case OP_X86_PUSH_IMM:
4826                         g_assert_not_reached ();
4827                         g_assert (amd64_is_imm32 (ins->inst_imm));
4828                         amd64_push_imm (code, ins->inst_imm);
4829                         break;
4830                 case OP_X86_PUSH_MEMBASE:
4831                         g_assert_not_reached ();
4832                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4833                         break;
4834                 case OP_X86_PUSH_OBJ: {
4835                         int size = ALIGN_TO (ins->inst_imm, 8);
4836
4837                         g_assert_not_reached ();
4838
4839                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4840                         amd64_push_reg (code, AMD64_RDI);
4841                         amd64_push_reg (code, AMD64_RSI);
4842                         amd64_push_reg (code, AMD64_RCX);
4843                         if (ins->inst_offset)
4844                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4845                         else
4846                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4847                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4848                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4849                         amd64_cld (code);
4850                         amd64_prefix (code, X86_REP_PREFIX);
4851                         amd64_movsd (code);
4852                         amd64_pop_reg (code, AMD64_RCX);
4853                         amd64_pop_reg (code, AMD64_RSI);
4854                         amd64_pop_reg (code, AMD64_RDI);
4855                         break;
4856                 }
4857                 case OP_GENERIC_CLASS_INIT: {
4858                         static int byte_offset = -1;
4859                         static guint8 bitmask;
4860                         guint8 *jump;
4861
4862                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4863
4864                         if (byte_offset < 0)
4865                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4866
4867                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4868                         jump = code;
4869                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4870
4871                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4872                         ins->flags |= MONO_INST_GC_CALLSITE;
4873                         ins->backend.pc_offset = code - cfg->native_code;
4874
4875                         x86_patch (jump, code);
4876                         break;
4877                 }
4878
4879                 case OP_X86_LEA:
4880                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4881                         break;
4882                 case OP_X86_LEA_MEMBASE:
4883                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4884                         break;
4885                 case OP_X86_XCHG:
4886                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4887                         break;
4888                 case OP_LOCALLOC:
4889                         /* keep alignment */
4890                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4891                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4892                         code = mono_emit_stack_alloc (cfg, code, ins);
4893                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4894                         if (cfg->param_area)
4895                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4896                         break;
4897                 case OP_LOCALLOC_IMM: {
4898                         guint32 size = ins->inst_imm;
4899                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4900
4901                         if (ins->flags & MONO_INST_INIT) {
4902                                 if (size < 64) {
4903                                         int i;
4904
4905                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4906                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4907
4908                                         for (i = 0; i < size; i += 8)
4909                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4910                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4911                                 } else {
4912                                         amd64_mov_reg_imm (code, ins->dreg, size);
4913                                         ins->sreg1 = ins->dreg;
4914
4915                                         code = mono_emit_stack_alloc (cfg, code, ins);
4916                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4917                                 }
4918                         } else {
4919                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4920                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4921                         }
4922                         if (cfg->param_area)
4923                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4924                         break;
4925                 }
4926                 case OP_THROW: {
4927                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4928                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4929                                              (gpointer)"mono_arch_throw_exception", FALSE);
4930                         ins->flags |= MONO_INST_GC_CALLSITE;
4931                         ins->backend.pc_offset = code - cfg->native_code;
4932                         break;
4933                 }
4934                 case OP_RETHROW: {
4935                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4936                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4937                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4938                         ins->flags |= MONO_INST_GC_CALLSITE;
4939                         ins->backend.pc_offset = code - cfg->native_code;
4940                         break;
4941                 }
4942                 case OP_CALL_HANDLER:
4943                         /* Align stack */
4944                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4945                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4946                         amd64_call_imm (code, 0);
4947                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4948                         /* Restore stack alignment */
4949                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4950                         break;
4951                 case OP_START_HANDLER: {
4952                         /* Even though we're saving RSP, use sizeof */
4953                         /* gpointer because spvar is of type IntPtr */
4954                         /* see: mono_create_spvar_for_region */
4955                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4956                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4957
4958                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4959                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4960                                 cfg->param_area) {
4961                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4962                         }
4963                         break;
4964                 }
4965                 case OP_ENDFINALLY: {
4966                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4967                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4968                         amd64_ret (code);
4969                         break;
4970                 }
4971                 case OP_ENDFILTER: {
4972                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4973                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4974                         /* The local allocator will put the result into RAX */
4975                         amd64_ret (code);
4976                         break;
4977                 }
4978                 case OP_GET_EX_OBJ:
4979                         if (ins->dreg != AMD64_RAX)
4980                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4981                         break;
4982                 case OP_LABEL:
4983                         ins->inst_c0 = code - cfg->native_code;
4984                         break;
4985                 case OP_BR:
4986                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4987                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4988                         //break;
4989                                 if (ins->inst_target_bb->native_offset) {
4990                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4991                                 } else {
4992                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4993                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4994                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4995                                                 x86_jump8 (code, 0);
4996                                         else
4997                                                 x86_jump32 (code, 0);
4998                         }
4999                         break;
5000                 case OP_BR_REG:
5001                         amd64_jump_reg (code, ins->sreg1);
5002                         break;
5003                 case OP_ICNEQ:
5004                 case OP_ICGE:
5005                 case OP_ICLE:
5006                 case OP_ICGE_UN:
5007                 case OP_ICLE_UN:
5008
5009                 case OP_CEQ:
5010                 case OP_LCEQ:
5011                 case OP_ICEQ:
5012                 case OP_CLT:
5013                 case OP_LCLT:
5014                 case OP_ICLT:
5015                 case OP_CGT:
5016                 case OP_ICGT:
5017                 case OP_LCGT:
5018                 case OP_CLT_UN:
5019                 case OP_LCLT_UN:
5020                 case OP_ICLT_UN:
5021                 case OP_CGT_UN:
5022                 case OP_LCGT_UN:
5023                 case OP_ICGT_UN:
5024                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5025                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5026                         break;
5027                 case OP_COND_EXC_EQ:
5028                 case OP_COND_EXC_NE_UN:
5029                 case OP_COND_EXC_LT:
5030                 case OP_COND_EXC_LT_UN:
5031                 case OP_COND_EXC_GT:
5032                 case OP_COND_EXC_GT_UN:
5033                 case OP_COND_EXC_GE:
5034                 case OP_COND_EXC_GE_UN:
5035                 case OP_COND_EXC_LE:
5036                 case OP_COND_EXC_LE_UN:
5037                 case OP_COND_EXC_IEQ:
5038                 case OP_COND_EXC_INE_UN:
5039                 case OP_COND_EXC_ILT:
5040                 case OP_COND_EXC_ILT_UN:
5041                 case OP_COND_EXC_IGT:
5042                 case OP_COND_EXC_IGT_UN:
5043                 case OP_COND_EXC_IGE:
5044                 case OP_COND_EXC_IGE_UN:
5045                 case OP_COND_EXC_ILE:
5046                 case OP_COND_EXC_ILE_UN:
5047                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5048                         break;
5049                 case OP_COND_EXC_OV:
5050                 case OP_COND_EXC_NO:
5051                 case OP_COND_EXC_C:
5052                 case OP_COND_EXC_NC:
5053                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5054                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5055                         break;
5056                 case OP_COND_EXC_IOV:
5057                 case OP_COND_EXC_INO:
5058                 case OP_COND_EXC_IC:
5059                 case OP_COND_EXC_INC:
5060                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5061                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5062                         break;
5063
5064                 /* floating point opcodes */
5065                 case OP_R8CONST: {
5066                         double d = *(double *)ins->inst_p0;
5067
5068                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5069                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5070                         }
5071                         else {
5072                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5073                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5074                         }
5075                         break;
5076                 }
5077                 case OP_R4CONST: {
5078                         float f = *(float *)ins->inst_p0;
5079
5080                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5081                                 if (cfg->r4fp)
5082                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5083                                 else
5084                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5085                         }
5086                         else {
5087                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5088                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5089                                 if (!cfg->r4fp)
5090                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5091                         }
5092                         break;
5093                 }
5094                 case OP_STORER8_MEMBASE_REG:
5095                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5096                         break;
5097                 case OP_LOADR8_MEMBASE:
5098                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5099                         break;
5100                 case OP_STORER4_MEMBASE_REG:
5101                         if (cfg->r4fp) {
5102                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5103                         } else {
5104                                 /* This requires a double->single conversion */
5105                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5106                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5107                         }
5108                         break;
5109                 case OP_LOADR4_MEMBASE:
5110                         if (cfg->r4fp) {
5111                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5112                         } else {
5113                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5114                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5115                         }
5116                         break;
5117                 case OP_ICONV_TO_R4:
5118                         if (cfg->r4fp) {
5119                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5120                         } else {
5121                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5122                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5123                         }
5124                         break;
5125                 case OP_ICONV_TO_R8:
5126                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5127                         break;
5128                 case OP_LCONV_TO_R4:
5129                         if (cfg->r4fp) {
5130                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5131                         } else {
5132                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5133                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5134                         }
5135                         break;
5136                 case OP_LCONV_TO_R8:
5137                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5138                         break;
5139                 case OP_FCONV_TO_R4:
5140                         if (cfg->r4fp) {
5141                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5142                         } else {
5143                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5144                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5145                         }
5146                         break;
5147                 case OP_FCONV_TO_I1:
5148                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5149                         break;
5150                 case OP_FCONV_TO_U1:
5151                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5152                         break;
5153                 case OP_FCONV_TO_I2:
5154                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5155                         break;
5156                 case OP_FCONV_TO_U2:
5157                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5158                         break;
5159                 case OP_FCONV_TO_U4:
5160                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5161                         break;
5162                 case OP_FCONV_TO_I4:
5163                 case OP_FCONV_TO_I:
5164                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5165                         break;
5166                 case OP_FCONV_TO_I8:
5167                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5168                         break;
5169
5170                 case OP_RCONV_TO_I1:
5171                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5172                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5173                         break;
5174                 case OP_RCONV_TO_U1:
5175                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5176                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5177                         break;
5178                 case OP_RCONV_TO_I2:
5179                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5180                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5181                         break;
5182                 case OP_RCONV_TO_U2:
5183                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5184                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5185                         break;
5186                 case OP_RCONV_TO_I4:
5187                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5188                         break;
5189                 case OP_RCONV_TO_U4:
5190                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5191                         break;
5192                 case OP_RCONV_TO_I8:
5193                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5194                         break;
5195                 case OP_RCONV_TO_R8:
5196                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5197                         break;
5198                 case OP_RCONV_TO_R4:
5199                         if (ins->dreg != ins->sreg1)
5200                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5201                         break;
5202
5203                 case OP_LCONV_TO_R_UN: {
5204                         guint8 *br [2];
5205
5206                         /* Based on gcc code */
5207                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5208                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5209
5210                         /* Positive case */
5211                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5212                         br [1] = code; x86_jump8 (code, 0);
5213                         amd64_patch (br [0], code);
5214
5215                         /* Negative case */
5216                         /* Save to the red zone */
5217                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5218                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5219                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5220                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5221                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5222                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5223                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5224                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5225                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5226                         /* Restore */
5227                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5228                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5229                         amd64_patch (br [1], code);
5230                         break;
5231                 }
5232                 case OP_LCONV_TO_OVF_U4:
5233                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5234                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5235                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5236                         break;
5237                 case OP_LCONV_TO_OVF_I4_UN:
5238                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5239                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5240                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5241                         break;
5242                 case OP_FMOVE:
5243                         if (ins->dreg != ins->sreg1)
5244                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5245                         break;
5246                 case OP_RMOVE:
5247                         if (ins->dreg != ins->sreg1)
5248                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5249                         break;
5250                 case OP_MOVE_F_TO_I4:
5251                         if (cfg->r4fp) {
5252                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5253                         } else {
5254                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5255                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5256                         }
5257                         break;
5258                 case OP_MOVE_I4_TO_F:
5259                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5260                         if (!cfg->r4fp)
5261                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5262                         break;
5263                 case OP_MOVE_F_TO_I8:
5264                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5265                         break;
5266                 case OP_MOVE_I8_TO_F:
5267                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5268                         break;
5269                 case OP_FADD:
5270                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5271                         break;
5272                 case OP_FSUB:
5273                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5274                         break;
5275                 case OP_FMUL:
5276                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5277                         break;
5278                 case OP_FDIV:
5279                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5280                         break;
5281                 case OP_FNEG: {
5282                         static double r8_0 = -0.0;
5283
5284                         g_assert (ins->sreg1 == ins->dreg);
5285
5286                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5287                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5288                         break;
5289                 }
5290                 case OP_SIN:
5291                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5292                         break;
5293                 case OP_COS:
5294                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5295                         break;
5296                 case OP_ABS: {
5297                         static guint64 d = 0x7fffffffffffffffUL;
5298
5299                         g_assert (ins->sreg1 == ins->dreg);
5300
5301                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5302                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5303                         break;
5304                 }
5305                 case OP_SQRT:
5306                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5307                         break;
5308
5309                 case OP_RADD:
5310                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5311                         break;
5312                 case OP_RSUB:
5313                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5314                         break;
5315                 case OP_RMUL:
5316                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5317                         break;
5318                 case OP_RDIV:
5319                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5320                         break;
5321                 case OP_RNEG: {
5322                         static float r4_0 = -0.0;
5323
5324                         g_assert (ins->sreg1 == ins->dreg);
5325
5326                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5327                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5328                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5329                         break;
5330                 }
5331
5332                 case OP_IMIN:
5333                         g_assert (cfg->opt & MONO_OPT_CMOV);
5334                         g_assert (ins->dreg == ins->sreg1);
5335                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5336                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5337                         break;
5338                 case OP_IMIN_UN:
5339                         g_assert (cfg->opt & MONO_OPT_CMOV);
5340                         g_assert (ins->dreg == ins->sreg1);
5341                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5342                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5343                         break;
5344                 case OP_IMAX:
5345                         g_assert (cfg->opt & MONO_OPT_CMOV);
5346                         g_assert (ins->dreg == ins->sreg1);
5347                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5348                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5349                         break;
5350                 case OP_IMAX_UN:
5351                         g_assert (cfg->opt & MONO_OPT_CMOV);
5352                         g_assert (ins->dreg == ins->sreg1);
5353                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5354                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5355                         break;
5356                 case OP_LMIN:
5357                         g_assert (cfg->opt & MONO_OPT_CMOV);
5358                         g_assert (ins->dreg == ins->sreg1);
5359                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5360                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5361                         break;
5362                 case OP_LMIN_UN:
5363                         g_assert (cfg->opt & MONO_OPT_CMOV);
5364                         g_assert (ins->dreg == ins->sreg1);
5365                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5366                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5367                         break;
5368                 case OP_LMAX:
5369                         g_assert (cfg->opt & MONO_OPT_CMOV);
5370                         g_assert (ins->dreg == ins->sreg1);
5371                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5372                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5373                         break;
5374                 case OP_LMAX_UN:
5375                         g_assert (cfg->opt & MONO_OPT_CMOV);
5376                         g_assert (ins->dreg == ins->sreg1);
5377                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5378                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5379                         break;
5380                 case OP_X86_FPOP:
5381                         break;
5382                 case OP_FCOMPARE:
5383                         /*
5384                          * The two arguments are swapped because the fbranch instructions
5385                          * depend on this for the non-sse case to work.
5386                          */
5387                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5388                         break;
5389                 case OP_RCOMPARE:
5390                         /*
5391                          * FIXME: Get rid of this.
5392                          * The two arguments are swapped because the fbranch instructions
5393                          * depend on this for the non-sse case to work.
5394                          */
5395                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5396                         break;
5397                 case OP_FCNEQ:
5398                 case OP_FCEQ: {
5399                         /* zeroing the register at the start results in
5400                          * shorter and faster code (we can also remove the widening op)
5401                          */
5402                         guchar *unordered_check;
5403
5404                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5405                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5406                         unordered_check = code;
5407                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5408
5409                         if (ins->opcode == OP_FCEQ) {
5410                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5411                                 amd64_patch (unordered_check, code);
5412                         } else {
5413                                 guchar *jump_to_end;
5414                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5415                                 jump_to_end = code;
5416                                 x86_jump8 (code, 0);
5417                                 amd64_patch (unordered_check, code);
5418                                 amd64_inc_reg (code, ins->dreg);
5419                                 amd64_patch (jump_to_end, code);
5420                         }
5421                         break;
5422                 }
5423                 case OP_FCLT:
5424                 case OP_FCLT_UN: {
5425                         /* zeroing the register at the start results in
5426                          * shorter and faster code (we can also remove the widening op)
5427                          */
5428                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5429                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5430                         if (ins->opcode == OP_FCLT_UN) {
5431                                 guchar *unordered_check = code;
5432                                 guchar *jump_to_end;
5433                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5434                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5435                                 jump_to_end = code;
5436                                 x86_jump8 (code, 0);
5437                                 amd64_patch (unordered_check, code);
5438                                 amd64_inc_reg (code, ins->dreg);
5439                                 amd64_patch (jump_to_end, code);
5440                         } else {
5441                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5442                         }
5443                         break;
5444                 }
5445                 case OP_FCLE: {
5446                         guchar *unordered_check;
5447                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5448                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5449                         unordered_check = code;
5450                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5451                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5452                         amd64_patch (unordered_check, code);
5453                         break;
5454                 }
5455                 case OP_FCGT:
5456                 case OP_FCGT_UN: {
5457                         /* zeroing the register at the start results in
5458                          * shorter and faster code (we can also remove the widening op)
5459                          */
5460                         guchar *unordered_check;
5461
5462                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5463                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5464                         if (ins->opcode == OP_FCGT) {
5465                                 unordered_check = code;
5466                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5467                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5468                                 amd64_patch (unordered_check, code);
5469                         } else {
5470                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5471                         }
5472                         break;
5473                 }
5474                 case OP_FCGE: {
5475                         guchar *unordered_check;
5476                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5477                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5478                         unordered_check = code;
5479                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5480                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5481                         amd64_patch (unordered_check, code);
5482                         break;
5483                 }
5484
5485                 case OP_RCEQ:
5486                 case OP_RCGT:
5487                 case OP_RCLT:
5488                 case OP_RCLT_UN:
5489                 case OP_RCGT_UN: {
5490                         int x86_cond;
5491                         gboolean unordered = FALSE;
5492
5493                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5494                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5495
5496                         switch (ins->opcode) {
5497                         case OP_RCEQ:
5498                                 x86_cond = X86_CC_EQ;
5499                                 break;
5500                         case OP_RCGT:
5501                                 x86_cond = X86_CC_LT;
5502                                 break;
5503                         case OP_RCLT:
5504                                 x86_cond = X86_CC_GT;
5505                                 break;
5506                         case OP_RCLT_UN:
5507                                 x86_cond = X86_CC_GT;
5508                                 unordered = TRUE;
5509                                 break;
5510                         case OP_RCGT_UN:
5511                                 x86_cond = X86_CC_LT;
5512                                 unordered = TRUE;
5513                                 break;
5514                         default:
5515                                 g_assert_not_reached ();
5516                                 break;
5517                         }
5518
5519                         if (unordered) {
5520                                 guchar *unordered_check;
5521                                 guchar *jump_to_end;
5522
5523                                 unordered_check = code;
5524                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5525                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5526                                 jump_to_end = code;
5527                                 x86_jump8 (code, 0);
5528                                 amd64_patch (unordered_check, code);
5529                                 amd64_inc_reg (code, ins->dreg);
5530                                 amd64_patch (jump_to_end, code);
5531                         } else {
5532                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5533                         }
5534                         break;
5535                 }
5536                 case OP_FCLT_MEMBASE:
5537                 case OP_FCGT_MEMBASE:
5538                 case OP_FCLT_UN_MEMBASE:
5539                 case OP_FCGT_UN_MEMBASE:
5540                 case OP_FCEQ_MEMBASE: {
5541                         guchar *unordered_check, *jump_to_end;
5542                         int x86_cond;
5543
5544                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5545                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5546
5547                         switch (ins->opcode) {
5548                         case OP_FCEQ_MEMBASE:
5549                                 x86_cond = X86_CC_EQ;
5550                                 break;
5551                         case OP_FCLT_MEMBASE:
5552                         case OP_FCLT_UN_MEMBASE:
5553                                 x86_cond = X86_CC_LT;
5554                                 break;
5555                         case OP_FCGT_MEMBASE:
5556                         case OP_FCGT_UN_MEMBASE:
5557                                 x86_cond = X86_CC_GT;
5558                                 break;
5559                         default:
5560                                 g_assert_not_reached ();
5561                         }
5562
5563                         unordered_check = code;
5564                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5565                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5566
5567                         switch (ins->opcode) {
5568                         case OP_FCEQ_MEMBASE:
5569                         case OP_FCLT_MEMBASE:
5570                         case OP_FCGT_MEMBASE:
5571                                 amd64_patch (unordered_check, code);
5572                                 break;
5573                         case OP_FCLT_UN_MEMBASE:
5574                         case OP_FCGT_UN_MEMBASE:
5575                                 jump_to_end = code;
5576                                 x86_jump8 (code, 0);
5577                                 amd64_patch (unordered_check, code);
5578                                 amd64_inc_reg (code, ins->dreg);
5579                                 amd64_patch (jump_to_end, code);
5580                                 break;
5581                         default:
5582                                 break;
5583                         }
5584                         break;
5585                 }
5586                 case OP_FBEQ: {
5587                         guchar *jump = code;
5588                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5589                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5590                         amd64_patch (jump, code);
5591                         break;
5592                 }
5593                 case OP_FBNE_UN:
5594                         /* Branch if C013 != 100 */
5595                         /* branch if !ZF or (PF|CF) */
5596                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5597                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5598                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5599                         break;
5600                 case OP_FBLT:
5601                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5602                         break;
5603                 case OP_FBLT_UN:
5604                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5605                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5606                         break;
5607                 case OP_FBGT:
5608                 case OP_FBGT_UN:
5609                         if (ins->opcode == OP_FBGT) {
5610                                 guchar *br1;
5611
5612                                 /* skip branch if C1=1 */
5613                                 br1 = code;
5614                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5615                                 /* branch if (C0 | C3) = 1 */
5616                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5617                                 amd64_patch (br1, code);
5618                                 break;
5619                         } else {
5620                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5621                         }
5622                         break;
5623                 case OP_FBGE: {
5624                         /* Branch if C013 == 100 or 001 */
5625                         guchar *br1;
5626
5627                         /* skip branch if C1=1 */
5628                         br1 = code;
5629                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5630                         /* branch if (C0 | C3) = 1 */
5631                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5632                         amd64_patch (br1, code);
5633                         break;
5634                 }
5635                 case OP_FBGE_UN:
5636                         /* Branch if C013 == 000 */
5637                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5638                         break;
5639                 case OP_FBLE: {
5640                         /* Branch if C013=000 or 100 */
5641                         guchar *br1;
5642
5643                         /* skip branch if C1=1 */
5644                         br1 = code;
5645                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5646                         /* branch if C0=0 */
5647                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5648                         amd64_patch (br1, code);
5649                         break;
5650                 }
5651                 case OP_FBLE_UN:
5652                         /* Branch if C013 != 001 */
5653                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5654                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5655                         break;
5656                 case OP_CKFINITE:
5657                         /* Transfer value to the fp stack */
5658                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5659                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5660                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5661
5662                         amd64_push_reg (code, AMD64_RAX);
5663                         amd64_fxam (code);
5664                         amd64_fnstsw (code);
5665                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5666                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5667                         amd64_pop_reg (code, AMD64_RAX);
5668                         amd64_fstp (code, 0);
5669                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5670                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5671                         break;
5672                 case OP_TLS_GET: {
5673                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5674                         break;
5675                 }
5676                 case OP_TLS_GET_REG:
5677                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5678                         break;
5679                 case OP_TLS_SET: {
5680                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5681                         break;
5682                 }
5683                 case OP_TLS_SET_REG: {
5684                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5685                         break;
5686                 }
5687                 case OP_MEMORY_BARRIER: {
5688                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5689                                 x86_mfence (code);
5690                         break;
5691                 }
5692                 case OP_ATOMIC_ADD_I4:
5693                 case OP_ATOMIC_ADD_I8: {
5694                         int dreg = ins->dreg;
5695                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5696
5697                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5698                                 dreg = AMD64_R11;
5699
5700                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5701                         amd64_prefix (code, X86_LOCK_PREFIX);
5702                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5703                         /* dreg contains the old value, add with sreg2 value */
5704                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5705
5706                         if (ins->dreg != dreg)
5707                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5708
5709                         break;
5710                 }
5711                 case OP_ATOMIC_EXCHANGE_I4:
5712                 case OP_ATOMIC_EXCHANGE_I8: {
5713                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5714
5715                         /* LOCK prefix is implied. */
5716                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5717                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5718                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5719                         break;
5720                 }
5721                 case OP_ATOMIC_CAS_I4:
5722                 case OP_ATOMIC_CAS_I8: {
5723                         guint32 size;
5724
5725                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5726                                 size = 8;
5727                         else
5728                                 size = 4;
5729
5730                         /*
5731                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5732                          * an explanation of how this works.
5733                          */
5734                         g_assert (ins->sreg3 == AMD64_RAX);
5735                         g_assert (ins->sreg1 != AMD64_RAX);
5736                         g_assert (ins->sreg1 != ins->sreg2);
5737
5738                         amd64_prefix (code, X86_LOCK_PREFIX);
5739                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5740
5741                         if (ins->dreg != AMD64_RAX)
5742                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5743                         break;
5744                 }
5745                 case OP_ATOMIC_LOAD_I1: {
5746                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5747                         break;
5748                 }
5749                 case OP_ATOMIC_LOAD_U1: {
5750                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5751                         break;
5752                 }
5753                 case OP_ATOMIC_LOAD_I2: {
5754                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5755                         break;
5756                 }
5757                 case OP_ATOMIC_LOAD_U2: {
5758                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5759                         break;
5760                 }
5761                 case OP_ATOMIC_LOAD_I4: {
5762                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5763                         break;
5764                 }
5765                 case OP_ATOMIC_LOAD_U4:
5766                 case OP_ATOMIC_LOAD_I8:
5767                 case OP_ATOMIC_LOAD_U8: {
5768                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5769                         break;
5770                 }
5771                 case OP_ATOMIC_LOAD_R4: {
5772                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5773                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5774                         break;
5775                 }
5776                 case OP_ATOMIC_LOAD_R8: {
5777                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5778                         break;
5779                 }
5780                 case OP_ATOMIC_STORE_I1:
5781                 case OP_ATOMIC_STORE_U1:
5782                 case OP_ATOMIC_STORE_I2:
5783                 case OP_ATOMIC_STORE_U2:
5784                 case OP_ATOMIC_STORE_I4:
5785                 case OP_ATOMIC_STORE_U4:
5786                 case OP_ATOMIC_STORE_I8:
5787                 case OP_ATOMIC_STORE_U8: {
5788                         int size;
5789
5790                         switch (ins->opcode) {
5791                         case OP_ATOMIC_STORE_I1:
5792                         case OP_ATOMIC_STORE_U1:
5793                                 size = 1;
5794                                 break;
5795                         case OP_ATOMIC_STORE_I2:
5796                         case OP_ATOMIC_STORE_U2:
5797                                 size = 2;
5798                                 break;
5799                         case OP_ATOMIC_STORE_I4:
5800                         case OP_ATOMIC_STORE_U4:
5801                                 size = 4;
5802                                 break;
5803                         case OP_ATOMIC_STORE_I8:
5804                         case OP_ATOMIC_STORE_U8:
5805                                 size = 8;
5806                                 break;
5807                         }
5808
5809                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5810
5811                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5812                                 x86_mfence (code);
5813                         break;
5814                 }
5815                 case OP_ATOMIC_STORE_R4: {
5816                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5817                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5818
5819                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5820                                 x86_mfence (code);
5821                         break;
5822                 }
5823                 case OP_ATOMIC_STORE_R8: {
5824                         x86_nop (code);
5825                         x86_nop (code);
5826                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5827                         x86_nop (code);
5828                         x86_nop (code);
5829
5830                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5831                                 x86_mfence (code);
5832                         break;
5833                 }
5834                 case OP_CARD_TABLE_WBARRIER: {
5835                         int ptr = ins->sreg1;
5836                         int value = ins->sreg2;
5837                         guchar *br = 0;
5838                         int nursery_shift, card_table_shift;
5839                         gpointer card_table_mask;
5840                         size_t nursery_size;
5841
5842                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5843                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5844                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5845
5846                         /*If either point to the stack we can simply avoid the WB. This happens due to
5847                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5848                          */
5849                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5850                                 continue;
5851
5852                         /*
5853                          * We need one register we can clobber, we choose EDX and make sreg1
5854                          * fixed EAX to work around limitations in the local register allocator.
5855                          * sreg2 might get allocated to EDX, but that is not a problem since
5856                          * we use it before clobbering EDX.
5857                          */
5858                         g_assert (ins->sreg1 == AMD64_RAX);
5859
5860                         /*
5861                          * This is the code we produce:
5862                          *
5863                          *   edx = value
5864                          *   edx >>= nursery_shift
5865                          *   cmp edx, (nursery_start >> nursery_shift)
5866                          *   jne done
5867                          *   edx = ptr
5868                          *   edx >>= card_table_shift
5869                          *   edx += cardtable
5870                          *   [edx] = 1
5871                          * done:
5872                          */
5873
5874                         if (mono_gc_card_table_nursery_check ()) {
5875                                 if (value != AMD64_RDX)
5876                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5877                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5878                                 if (shifted_nursery_start >> 31) {
5879                                         /*
5880                                          * The value we need to compare against is 64 bits, so we need
5881                                          * another spare register.  We use RBX, which we save and
5882                                          * restore.
5883                                          */
5884                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5885                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5886                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5887                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5888                                 } else {
5889                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5890                                 }
5891                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5892                         }
5893                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5894                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5895                         if (card_table_mask)
5896                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5897
5898                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5899                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5900
5901                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5902
5903                         if (mono_gc_card_table_nursery_check ())
5904                                 x86_patch (br, code);
5905                         break;
5906                 }
5907 #ifdef MONO_ARCH_SIMD_INTRINSICS
5908                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5909                 case OP_ADDPS:
5910                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_DIVPS:
5913                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_MULPS:
5916                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5917                         break;
5918                 case OP_SUBPS:
5919                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5920                         break;
5921                 case OP_MAXPS:
5922                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5923                         break;
5924                 case OP_MINPS:
5925                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5926                         break;
5927                 case OP_COMPPS:
5928                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5929                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5930                         break;
5931                 case OP_ANDPS:
5932                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5933                         break;
5934                 case OP_ANDNPS:
5935                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5936                         break;
5937                 case OP_ORPS:
5938                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5939                         break;
5940                 case OP_XORPS:
5941                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5942                         break;
5943                 case OP_SQRTPS:
5944                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5945                         break;
5946                 case OP_RSQRTPS:
5947                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5948                         break;
5949                 case OP_RCPPS:
5950                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5951                         break;
5952                 case OP_ADDSUBPS:
5953                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955                 case OP_HADDPS:
5956                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958                 case OP_HSUBPS:
5959                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5960                         break;
5961                 case OP_DUPPS_HIGH:
5962                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5963                         break;
5964                 case OP_DUPPS_LOW:
5965                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5966                         break;
5967
5968                 case OP_PSHUFLEW_HIGH:
5969                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5970                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5971                         break;
5972                 case OP_PSHUFLEW_LOW:
5973                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5974                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5975                         break;
5976                 case OP_PSHUFLED:
5977                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5978                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5979                         break;
5980                 case OP_SHUFPS:
5981                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5982                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5983                         break;
5984                 case OP_SHUFPD:
5985                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5986                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5987                         break;
5988
5989                 case OP_ADDPD:
5990                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_DIVPD:
5993                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_MULPD:
5996                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_SUBPD:
5999                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_MAXPD:
6002                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004                 case OP_MINPD:
6005                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007                 case OP_COMPPD:
6008                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6009                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6010                         break;
6011                 case OP_ANDPD:
6012                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_ANDNPD:
6015                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017                 case OP_ORPD:
6018                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020                 case OP_XORPD:
6021                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6022                         break;
6023                 case OP_SQRTPD:
6024                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6025                         break;
6026                 case OP_ADDSUBPD:
6027                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6028                         break;
6029                 case OP_HADDPD:
6030                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_HSUBPD:
6033                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_DUPPD:
6036                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6037                         break;
6038
6039                 case OP_EXTRACT_MASK:
6040                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6041                         break;
6042
6043                 case OP_PAND:
6044                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6045                         break;
6046                 case OP_POR:
6047                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_PXOR:
6050                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052
6053                 case OP_PADDB:
6054                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056                 case OP_PADDW:
6057                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6058                         break;
6059                 case OP_PADDD:
6060                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062                 case OP_PADDQ:
6063                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6064                         break;
6065
6066                 case OP_PSUBB:
6067                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6068                         break;
6069                 case OP_PSUBW:
6070                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072                 case OP_PSUBD:
6073                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075                 case OP_PSUBQ:
6076                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6077                         break;
6078
6079                 case OP_PMAXB_UN:
6080                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_PMAXW_UN:
6083                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085                 case OP_PMAXD_UN:
6086                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088
6089                 case OP_PMAXB:
6090                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PMAXW:
6093                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095                 case OP_PMAXD:
6096                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6097                         break;
6098
6099                 case OP_PAVGB_UN:
6100                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102                 case OP_PAVGW_UN:
6103                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6104                         break;
6105
6106                 case OP_PMINB_UN:
6107                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_PMINW_UN:
6110                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PMIND_UN:
6113                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115
6116                 case OP_PMINB:
6117                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6118                         break;
6119                 case OP_PMINW:
6120                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122                 case OP_PMIND:
6123                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6124                         break;
6125
6126                 case OP_PCMPEQB:
6127                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129                 case OP_PCMPEQW:
6130                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6131                         break;
6132                 case OP_PCMPEQD:
6133                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135                 case OP_PCMPEQQ:
6136                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6137                         break;
6138
6139                 case OP_PCMPGTB:
6140                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6141                         break;
6142                 case OP_PCMPGTW:
6143                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_PCMPGTD:
6146                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148                 case OP_PCMPGTQ:
6149                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6150                         break;
6151
6152                 case OP_PSUM_ABS_DIFF:
6153                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6154                         break;
6155
6156                 case OP_UNPACK_LOWB:
6157                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6158                         break;
6159                 case OP_UNPACK_LOWW:
6160                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6161                         break;
6162                 case OP_UNPACK_LOWD:
6163                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6164                         break;
6165                 case OP_UNPACK_LOWQ:
6166                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6167                         break;
6168                 case OP_UNPACK_LOWPS:
6169                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6170                         break;
6171                 case OP_UNPACK_LOWPD:
6172                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6173                         break;
6174
6175                 case OP_UNPACK_HIGHB:
6176                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6177                         break;
6178                 case OP_UNPACK_HIGHW:
6179                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6180                         break;
6181                 case OP_UNPACK_HIGHD:
6182                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6183                         break;
6184                 case OP_UNPACK_HIGHQ:
6185                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6186                         break;
6187                 case OP_UNPACK_HIGHPS:
6188                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6189                         break;
6190                 case OP_UNPACK_HIGHPD:
6191                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6192                         break;
6193
6194                 case OP_PACKW:
6195                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6196                         break;
6197                 case OP_PACKD:
6198                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6199                         break;
6200                 case OP_PACKW_UN:
6201                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6202                         break;
6203                 case OP_PACKD_UN:
6204                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6205                         break;
6206
6207                 case OP_PADDB_SAT_UN:
6208                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6209                         break;
6210                 case OP_PSUBB_SAT_UN:
6211                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6212                         break;
6213                 case OP_PADDW_SAT_UN:
6214                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6215                         break;
6216                 case OP_PSUBW_SAT_UN:
6217                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6218                         break;
6219
6220                 case OP_PADDB_SAT:
6221                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6222                         break;
6223                 case OP_PSUBB_SAT:
6224                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6225                         break;
6226                 case OP_PADDW_SAT:
6227                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6228                         break;
6229                 case OP_PSUBW_SAT:
6230                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6231                         break;
6232
6233                 case OP_PMULW:
6234                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236                 case OP_PMULD:
6237                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239                 case OP_PMULQ:
6240                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6241                         break;
6242                 case OP_PMULW_HIGH_UN:
6243                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6244                         break;
6245                 case OP_PMULW_HIGH:
6246                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6247                         break;
6248
6249                 case OP_PSHRW:
6250                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6251                         break;
6252                 case OP_PSHRW_REG:
6253                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6254                         break;
6255
6256                 case OP_PSARW:
6257                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6258                         break;
6259                 case OP_PSARW_REG:
6260                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6261                         break;
6262
6263                 case OP_PSHLW:
6264                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6265                         break;
6266                 case OP_PSHLW_REG:
6267                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6268                         break;
6269
6270                 case OP_PSHRD:
6271                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6272                         break;
6273                 case OP_PSHRD_REG:
6274                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6275                         break;
6276
6277                 case OP_PSARD:
6278                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6279                         break;
6280                 case OP_PSARD_REG:
6281                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6282                         break;
6283
6284                 case OP_PSHLD:
6285                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6286                         break;
6287                 case OP_PSHLD_REG:
6288                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6289                         break;
6290
6291                 case OP_PSHRQ:
6292                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6293                         break;
6294                 case OP_PSHRQ_REG:
6295                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6296                         break;
6297
6298                 /*TODO: This is appart of the sse spec but not added
6299                 case OP_PSARQ:
6300                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6301                         break;
6302                 case OP_PSARQ_REG:
6303                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6304                         break;
6305                 */
6306
6307                 case OP_PSHLQ:
6308                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6309                         break;
6310                 case OP_PSHLQ_REG:
6311                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6312                         break;
6313                 case OP_CVTDQ2PD:
6314                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6315                         break;
6316                 case OP_CVTDQ2PS:
6317                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6318                         break;
6319                 case OP_CVTPD2DQ:
6320                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6321                         break;
6322                 case OP_CVTPD2PS:
6323                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6324                         break;
6325                 case OP_CVTPS2DQ:
6326                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6327                         break;
6328                 case OP_CVTPS2PD:
6329                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6330                         break;
6331                 case OP_CVTTPD2DQ:
6332                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6333                         break;
6334                 case OP_CVTTPS2DQ:
6335                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6336                         break;
6337
6338                 case OP_ICONV_TO_X:
6339                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6340                         break;
6341                 case OP_EXTRACT_I4:
6342                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6343                         break;
6344                 case OP_EXTRACT_I8:
6345                         if (ins->inst_c0) {
6346                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6347                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6348                         } else {
6349                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6350                         }
6351                         break;
6352                 case OP_EXTRACT_I1:
6353                 case OP_EXTRACT_U1:
6354                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6355                         if (ins->inst_c0)
6356                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6357                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6358                         break;
6359                 case OP_EXTRACT_I2:
6360                 case OP_EXTRACT_U2:
6361                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6362                         if (ins->inst_c0)
6363                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6364                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6365                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6366                         break;
6367                 case OP_EXTRACT_R8:
6368                         if (ins->inst_c0)
6369                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6370                         else
6371                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6372                         break;
6373                 case OP_INSERT_I2:
6374                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6375                         break;
6376                 case OP_EXTRACTX_U2:
6377                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6378                         break;
6379                 case OP_INSERTX_U1_SLOW:
6380                         /*sreg1 is the extracted ireg (scratch)
6381                         /sreg2 is the to be inserted ireg (scratch)
6382                         /dreg is the xreg to receive the value*/
6383
6384                         /*clear the bits from the extracted word*/
6385                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6386                         /*shift the value to insert if needed*/
6387                         if (ins->inst_c0 & 1)
6388                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6389                         /*join them together*/
6390                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6391                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6392                         break;
6393                 case OP_INSERTX_I4_SLOW:
6394                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6395                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6396                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6397                         break;
6398                 case OP_INSERTX_I8_SLOW:
6399                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6400                         if (ins->inst_c0)
6401                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6402                         else
6403                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6404                         break;
6405
6406                 case OP_INSERTX_R4_SLOW:
6407                         switch (ins->inst_c0) {
6408                         case 0:
6409                                 if (cfg->r4fp)
6410                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6411                                 else
6412                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6413                                 break;
6414                         case 1:
6415                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6416                                 if (cfg->r4fp)
6417                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6418                                 else
6419                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6420                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6421                                 break;
6422                         case 2:
6423                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6424                                 if (cfg->r4fp)
6425                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6426                                 else
6427                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6428                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6429                                 break;
6430                         case 3:
6431                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6432                                 if (cfg->r4fp)
6433                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6434                                 else
6435                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6436                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6437                                 break;
6438                         }
6439                         break;
6440                 case OP_INSERTX_R8_SLOW:
6441                         if (ins->inst_c0)
6442                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6443                         else
6444                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6445                         break;
6446                 case OP_STOREX_MEMBASE_REG:
6447                 case OP_STOREX_MEMBASE:
6448                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6449                         break;
6450                 case OP_LOADX_MEMBASE:
6451                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6452                         break;
6453                 case OP_LOADX_ALIGNED_MEMBASE:
6454                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6455                         break;
6456                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6457                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6458                         break;
6459                 case OP_STOREX_NTA_MEMBASE_REG:
6460                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6461                         break;
6462                 case OP_PREFETCH_MEMBASE:
6463                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6464                         break;
6465
6466                 case OP_XMOVE:
6467                         /*FIXME the peephole pass should have killed this*/
6468                         if (ins->dreg != ins->sreg1)
6469                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6470                         break;
6471                 case OP_XZERO:
6472                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6473                         break;
6474                 case OP_ICONV_TO_R4_RAW:
6475                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6476                         break;
6477
6478                 case OP_FCONV_TO_R8_X:
6479                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6480                         break;
6481
6482                 case OP_XCONV_R8_TO_I4:
6483                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6484                         switch (ins->backend.source_opcode) {
6485                         case OP_FCONV_TO_I1:
6486                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6487                                 break;
6488                         case OP_FCONV_TO_U1:
6489                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6490                                 break;
6491                         case OP_FCONV_TO_I2:
6492                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6493                                 break;
6494                         case OP_FCONV_TO_U2:
6495                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6496                                 break;
6497                         }
6498                         break;
6499
6500                 case OP_EXPAND_I2:
6501                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6502                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6503                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6504                         break;
6505                 case OP_EXPAND_I4:
6506                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6507                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6508                         break;
6509                 case OP_EXPAND_I8:
6510                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6511                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6512                         break;
6513                 case OP_EXPAND_R4:
6514                         if (cfg->r4fp) {
6515                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6516                         } else {
6517                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6518                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6519                         }
6520                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6521                         break;
6522                 case OP_EXPAND_R8:
6523                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6524                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6525                         break;
6526 #endif
6527                 case OP_LIVERANGE_START: {
6528                         if (cfg->verbose_level > 1)
6529                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6530                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6531                         break;
6532                 }
6533                 case OP_LIVERANGE_END: {
6534                         if (cfg->verbose_level > 1)
6535                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6536                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6537                         break;
6538                 }
6539                 case OP_GC_SAFE_POINT: {
6540                         const char *polling_func = NULL;
6541                         int compare_val = 0;
6542                         guint8 *br [1];
6543
6544 #if defined (USE_COOP_GC)
6545                         polling_func = "mono_threads_state_poll";
6546                         compare_val = 1;
6547 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6548                         polling_func = "mono_nacl_gc";
6549                         compare_val = 0xFFFFFFFF;
6550 #endif
6551                         if (!polling_func)
6552                                 break;
6553
6554                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6555                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6556                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6557                         amd64_patch (br[0], code);
6558                         break;
6559                 }
6560
6561                 case OP_GC_LIVENESS_DEF:
6562                 case OP_GC_LIVENESS_USE:
6563                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6564                         ins->backend.pc_offset = code - cfg->native_code;
6565                         break;
6566                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6567                         ins->backend.pc_offset = code - cfg->native_code;
6568                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6569                         break;
6570                 default:
6571                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6572                         g_assert_not_reached ();
6573                 }
6574
6575                 if ((code - cfg->native_code - offset) > max_len) {
6576 #if !defined(__native_client_codegen__)
6577                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6578                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6579                         g_assert_not_reached ();
6580 #endif
6581                 }
6582         }
6583
6584         cfg->code_len = code - cfg->native_code;
6585 }
6586
6587 #endif /* DISABLE_JIT */
6588
6589 void
6590 mono_arch_register_lowlevel_calls (void)
6591 {
6592         /* The signature doesn't matter */
6593         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6594 }
6595
6596 void
6597 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6598 {
6599         unsigned char *ip = ji->ip.i + code;
6600
6601         /*
6602          * Debug code to help track down problems where the target of a near call is
6603          * is not valid.
6604          */
6605         if (amd64_is_near_call (ip)) {
6606                 gint64 disp = (guint8*)target - (guint8*)ip;
6607
6608                 if (!amd64_is_imm32 (disp)) {
6609                         printf ("TYPE: %d\n", ji->type);
6610                         switch (ji->type) {
6611                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6612                                 printf ("V: %s\n", ji->data.name);
6613                                 break;
6614                         case MONO_PATCH_INFO_METHOD_JUMP:
6615                         case MONO_PATCH_INFO_METHOD:
6616                                 printf ("V: %s\n", ji->data.method->name);
6617                                 break;
6618                         default:
6619                                 break;
6620                         }
6621                 }
6622         }
6623
6624         amd64_patch (ip, (gpointer)target);
6625 }
6626
6627 #ifndef DISABLE_JIT
6628
6629 static int
6630 get_max_epilog_size (MonoCompile *cfg)
6631 {
6632         int max_epilog_size = 16;
6633
6634         if (cfg->method->save_lmf)
6635                 max_epilog_size += 256;
6636
6637         if (mono_jit_trace_calls != NULL)
6638                 max_epilog_size += 50;
6639
6640         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6641                 max_epilog_size += 50;
6642
6643         max_epilog_size += (AMD64_NREG * 2);
6644
6645         return max_epilog_size;
6646 }
6647
6648 /*
6649  * This macro is used for testing whenever the unwinder works correctly at every point
6650  * where an async exception can happen.
6651  */
6652 /* This will generate a SIGSEGV at the given point in the code */
6653 #define async_exc_point(code) do { \
6654     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6655          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6656              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6657          cfg->arch.async_point_count ++; \
6658     } \
6659 } while (0)
6660
6661 guint8 *
6662 mono_arch_emit_prolog (MonoCompile *cfg)
6663 {
6664         MonoMethod *method = cfg->method;
6665         MonoBasicBlock *bb;
6666         MonoMethodSignature *sig;
6667         MonoInst *ins;
6668         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6669         guint8 *code;
6670         CallInfo *cinfo;
6671         MonoInst *lmf_var = cfg->lmf_var;
6672         gboolean args_clobbered = FALSE;
6673         gboolean trace = FALSE;
6674 #ifdef __native_client_codegen__
6675         guint alignment_check;
6676 #endif
6677
6678         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6679
6680 #if defined(__default_codegen__)
6681         code = cfg->native_code = g_malloc (cfg->code_size);
6682 #elif defined(__native_client_codegen__)
6683         /* native_code_alloc is not 32-byte aligned, native_code is. */
6684         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6685
6686         /* Align native_code to next nearest kNaclAlignment byte. */
6687         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6688         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6689
6690         code = cfg->native_code;
6691
6692         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6693         g_assert (alignment_check == 0);
6694 #endif
6695
6696         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6697                 trace = TRUE;
6698
6699         /* Amount of stack space allocated by register saving code */
6700         pos = 0;
6701
6702         /* Offset between RSP and the CFA */
6703         cfa_offset = 0;
6704
6705         /*
6706          * The prolog consists of the following parts:
6707          * FP present:
6708          * - push rbp, mov rbp, rsp
6709          * - save callee saved regs using pushes
6710          * - allocate frame
6711          * - save rgctx if needed
6712          * - save lmf if needed
6713          * FP not present:
6714          * - allocate frame
6715          * - save rgctx if needed
6716          * - save lmf if needed
6717          * - save callee saved regs using moves
6718          */
6719
6720         // CFA = sp + 8
6721         cfa_offset = 8;
6722         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6723         // IP saved at CFA - 8
6724         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6725         async_exc_point (code);
6726         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6727
6728         if (!cfg->arch.omit_fp) {
6729                 amd64_push_reg (code, AMD64_RBP);
6730                 cfa_offset += 8;
6731                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6732                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6733                 async_exc_point (code);
6734 #ifdef TARGET_WIN32
6735                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6736 #endif
6737                 /* These are handled automatically by the stack marking code */
6738                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6739
6740                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6741                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6742                 async_exc_point (code);
6743 #ifdef TARGET_WIN32
6744                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6745 #endif
6746         }
6747
6748         /* The param area is always at offset 0 from sp */
6749         /* This needs to be allocated here, since it has to come after the spill area */
6750         if (cfg->param_area) {
6751                 if (cfg->arch.omit_fp)
6752                         // FIXME:
6753                         g_assert_not_reached ();
6754                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6755         }
6756
6757         if (cfg->arch.omit_fp) {
6758                 /*
6759                  * On enter, the stack is misaligned by the pushing of the return
6760                  * address. It is either made aligned by the pushing of %rbp, or by
6761                  * this.
6762                  */
6763                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6764                 if ((alloc_size % 16) == 0) {
6765                         alloc_size += 8;
6766                         /* Mark the padding slot as NOREF */
6767                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6768                 }
6769         } else {
6770                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6771                 if (cfg->stack_offset != alloc_size) {
6772                         /* Mark the padding slot as NOREF */
6773                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6774                 }
6775                 cfg->arch.sp_fp_offset = alloc_size;
6776                 alloc_size -= pos;
6777         }
6778
6779         cfg->arch.stack_alloc_size = alloc_size;
6780
6781         /* Allocate stack frame */
6782         if (alloc_size) {
6783                 /* See mono_emit_stack_alloc */
6784 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6785                 guint32 remaining_size = alloc_size;
6786                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6787                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6788                 guint32 offset = code - cfg->native_code;
6789                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6790                         while (required_code_size >= (cfg->code_size - offset))
6791                                 cfg->code_size *= 2;
6792                         cfg->native_code = mono_realloc_native_code (cfg);
6793                         code = cfg->native_code + offset;
6794                         cfg->stat_code_reallocs++;
6795                 }
6796
6797                 while (remaining_size >= 0x1000) {
6798                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6799                         if (cfg->arch.omit_fp) {
6800                                 cfa_offset += 0x1000;
6801                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6802                         }
6803                         async_exc_point (code);
6804 #ifdef TARGET_WIN32
6805                         if (cfg->arch.omit_fp)
6806                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6807 #endif
6808
6809                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6810                         remaining_size -= 0x1000;
6811                 }
6812                 if (remaining_size) {
6813                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6814                         if (cfg->arch.omit_fp) {
6815                                 cfa_offset += remaining_size;
6816                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6817                                 async_exc_point (code);
6818                         }
6819 #ifdef TARGET_WIN32
6820                         if (cfg->arch.omit_fp)
6821                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6822 #endif
6823                 }
6824 #else
6825                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6826                 if (cfg->arch.omit_fp) {
6827                         cfa_offset += alloc_size;
6828                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6829                         async_exc_point (code);
6830                 }
6831 #endif
6832         }
6833
6834         /* Stack alignment check */
6835 #if 0
6836         {
6837                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6838                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6839                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6840                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6841                 amd64_breakpoint (code);
6842         }
6843 #endif
6844
6845         if (mini_get_debug_options ()->init_stacks) {
6846                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6847
6848                 /* Save registers to the red zone */
6849                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6850                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6851
6852                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6853                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6854                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6855
6856                 amd64_cld (code);
6857 #if defined(__default_codegen__)
6858                 amd64_prefix (code, X86_REP_PREFIX);
6859                 amd64_stosl (code);
6860 #elif defined(__native_client_codegen__)
6861                 /* NaCl stos pseudo-instruction */
6862                 amd64_codegen_pre (code);
6863                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6864                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6865                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6866                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6867                 amd64_prefix (code, X86_REP_PREFIX);
6868                 amd64_stosl (code);
6869                 amd64_codegen_post (code);
6870 #endif /* __native_client_codegen__ */
6871
6872                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6873                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6874         }
6875
6876         /* Save LMF */
6877         if (method->save_lmf)
6878                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6879
6880         /* Save callee saved registers */
6881         if (cfg->arch.omit_fp) {
6882                 save_area_offset = cfg->arch.reg_save_area_offset;
6883                 /* Save caller saved registers after sp is adjusted */
6884                 /* The registers are saved at the bottom of the frame */
6885                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6886         } else {
6887                 /* The registers are saved just below the saved rbp */
6888                 save_area_offset = cfg->arch.reg_save_area_offset;
6889         }
6890
6891         for (i = 0; i < AMD64_NREG; ++i) {
6892                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6893                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6894
6895                         if (cfg->arch.omit_fp) {
6896                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6897                                 /* These are handled automatically by the stack marking code */
6898                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6899                         } else {
6900                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6901                                 // FIXME: GC
6902                         }
6903
6904                         save_area_offset += 8;
6905                         async_exc_point (code);
6906                 }
6907         }
6908
6909         /* store runtime generic context */
6910         if (cfg->rgctx_var) {
6911                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6912                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6913
6914                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6915
6916                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6917                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6918         }
6919
6920         /* compute max_length in order to use short forward jumps */
6921         max_epilog_size = get_max_epilog_size (cfg);
6922         if (cfg->opt & MONO_OPT_BRANCH) {
6923                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6924                         MonoInst *ins;
6925                         int max_length = 0;
6926
6927                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6928                                 max_length += 6;
6929                         /* max alignment for loops */
6930                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6931                                 max_length += LOOP_ALIGNMENT;
6932 #ifdef __native_client_codegen__
6933                         /* max alignment for native client */
6934                         max_length += kNaClAlignment;
6935 #endif
6936
6937                         MONO_BB_FOR_EACH_INS (bb, ins) {
6938 #ifdef __native_client_codegen__
6939                                 {
6940                                         int space_in_block = kNaClAlignment -
6941                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6942                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6943                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6944                                                 max_length += space_in_block;
6945                                         }
6946                                 }
6947 #endif  /*__native_client_codegen__*/
6948                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6949                         }
6950
6951                         /* Take prolog and epilog instrumentation into account */
6952                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6953                                 max_length += max_epilog_size;
6954
6955                         bb->max_length = max_length;
6956                 }
6957         }
6958
6959         sig = mono_method_signature (method);
6960         pos = 0;
6961
6962         cinfo = cfg->arch.cinfo;
6963
6964         if (sig->ret->type != MONO_TYPE_VOID) {
6965                 /* Save volatile arguments to the stack */
6966                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6967                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6968         }
6969
6970         /* Keep this in sync with emit_load_volatile_arguments */
6971         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6972                 ArgInfo *ainfo = cinfo->args + i;
6973
6974                 ins = cfg->args [i];
6975
6976                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6977                         /* Unused arguments */
6978                         continue;
6979
6980                 /* Save volatile arguments to the stack */
6981                 if (ins->opcode != OP_REGVAR) {
6982                         switch (ainfo->storage) {
6983                         case ArgInIReg: {
6984                                 guint32 size = 8;
6985
6986                                 /* FIXME: I1 etc */
6987                                 /*
6988                                 if (stack_offset & 0x1)
6989                                         size = 1;
6990                                 else if (stack_offset & 0x2)
6991                                         size = 2;
6992                                 else if (stack_offset & 0x4)
6993                                         size = 4;
6994                                 else
6995                                         size = 8;
6996                                 */
6997                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6998
6999                                 /*
7000                                  * Save the original location of 'this',
7001                                  * get_generic_info_from_stack_frame () needs this to properly look up
7002                                  * the argument value during the handling of async exceptions.
7003                                  */
7004                                 if (ins == cfg->args [0]) {
7005                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7006                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7007                                 }
7008                                 break;
7009                         }
7010                         case ArgInFloatSSEReg:
7011                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7012                                 break;
7013                         case ArgInDoubleSSEReg:
7014                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7015                                 break;
7016                         case ArgValuetypeInReg:
7017                                 for (quad = 0; quad < 2; quad ++) {
7018                                         switch (ainfo->pair_storage [quad]) {
7019                                         case ArgInIReg:
7020                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7021                                                 break;
7022                                         case ArgInFloatSSEReg:
7023                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7024                                                 break;
7025                                         case ArgInDoubleSSEReg:
7026                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7027                                                 break;
7028                                         case ArgNone:
7029                                                 break;
7030                                         default:
7031                                                 g_assert_not_reached ();
7032                                         }
7033                                 }
7034                                 break;
7035                         case ArgValuetypeAddrInIReg:
7036                                 if (ainfo->pair_storage [0] == ArgInIReg)
7037                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7038                                 break;
7039                         default:
7040                                 break;
7041                         }
7042                 } else {
7043                         /* Argument allocated to (non-volatile) register */
7044                         switch (ainfo->storage) {
7045                         case ArgInIReg:
7046                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7047                                 break;
7048                         case ArgOnStack:
7049                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7050                                 break;
7051                         default:
7052                                 g_assert_not_reached ();
7053                         }
7054
7055                         if (ins == cfg->args [0]) {
7056                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7057                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7058                         }
7059                 }
7060         }
7061
7062         if (cfg->method->save_lmf)
7063                 args_clobbered = TRUE;
7064
7065         if (trace) {
7066                 args_clobbered = TRUE;
7067                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7068         }
7069
7070         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7071                 args_clobbered = TRUE;
7072
7073         /*
7074          * Optimize the common case of the first bblock making a call with the same
7075          * arguments as the method. This works because the arguments are still in their
7076          * original argument registers.
7077          * FIXME: Generalize this
7078          */
7079         if (!args_clobbered) {
7080                 MonoBasicBlock *first_bb = cfg->bb_entry;
7081                 MonoInst *next;
7082                 int filter = FILTER_IL_SEQ_POINT;
7083
7084                 next = mono_bb_first_inst (first_bb, filter);
7085                 if (!next && first_bb->next_bb) {
7086                         first_bb = first_bb->next_bb;
7087                         next = mono_bb_first_inst (first_bb, filter);
7088                 }
7089
7090                 if (first_bb->in_count > 1)
7091                         next = NULL;
7092
7093                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7094                         ArgInfo *ainfo = cinfo->args + i;
7095                         gboolean match = FALSE;
7096
7097                         ins = cfg->args [i];
7098                         if (ins->opcode != OP_REGVAR) {
7099                                 switch (ainfo->storage) {
7100                                 case ArgInIReg: {
7101                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7102                                                 if (next->dreg == ainfo->reg) {
7103                                                         NULLIFY_INS (next);
7104                                                         match = TRUE;
7105                                                 } else {
7106                                                         next->opcode = OP_MOVE;
7107                                                         next->sreg1 = ainfo->reg;
7108                                                         /* Only continue if the instruction doesn't change argument regs */
7109                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7110                                                                 match = TRUE;
7111                                                 }
7112                                         }
7113                                         break;
7114                                 }
7115                                 default:
7116                                         break;
7117                                 }
7118                         } else {
7119                                 /* Argument allocated to (non-volatile) register */
7120                                 switch (ainfo->storage) {
7121                                 case ArgInIReg:
7122                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7123                                                 NULLIFY_INS (next);
7124                                                 match = TRUE;
7125                                         }
7126                                         break;
7127                                 default:
7128                                         break;
7129                                 }
7130                         }
7131
7132                         if (match) {
7133                                 next = mono_inst_next (next, filter);
7134                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7135                                 if (!next)
7136                                         break;
7137                         }
7138                 }
7139         }
7140
7141         if (cfg->gen_sdb_seq_points) {
7142                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7143
7144                 /* Initialize seq_point_info_var */
7145                 if (cfg->compile_aot) {
7146                         /* Initialize the variable from a GOT slot */
7147                         /* Same as OP_AOTCONST */
7148                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7149                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7150                         g_assert (info_var->opcode == OP_REGOFFSET);
7151                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7152                 }
7153
7154                 if (cfg->compile_aot) {
7155                         /* Initialize ss_tramp_var */
7156                         ins = cfg->arch.ss_tramp_var;
7157                         g_assert (ins->opcode == OP_REGOFFSET);
7158
7159                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7160                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7161                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7162                 } else {
7163                         /* Initialize ss_trigger_page_var */
7164                         ins = cfg->arch.ss_trigger_page_var;
7165
7166                         g_assert (ins->opcode == OP_REGOFFSET);
7167
7168                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7169                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7170                 }
7171         }
7172
7173         cfg->code_len = code - cfg->native_code;
7174
7175         g_assert (cfg->code_len < cfg->code_size);
7176
7177         return code;
7178 }
7179
7180 void
7181 mono_arch_emit_epilog (MonoCompile *cfg)
7182 {
7183         MonoMethod *method = cfg->method;
7184         int quad, i;
7185         guint8 *code;
7186         int max_epilog_size;
7187         CallInfo *cinfo;
7188         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7189         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7190
7191         max_epilog_size = get_max_epilog_size (cfg);
7192
7193         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7194                 cfg->code_size *= 2;
7195                 cfg->native_code = mono_realloc_native_code (cfg);
7196                 cfg->stat_code_reallocs++;
7197         }
7198         code = cfg->native_code + cfg->code_len;
7199
7200         cfg->has_unwind_info_for_epilog = TRUE;
7201
7202         /* Mark the start of the epilog */
7203         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7204
7205         /* Save the uwind state which is needed by the out-of-line code */
7206         mono_emit_unwind_op_remember_state (cfg, code);
7207
7208         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7209                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7210
7211         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7212
7213         if (method->save_lmf) {
7214                 /* check if we need to restore protection of the stack after a stack overflow */
7215                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7216                         guint8 *patch;
7217                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7218                         /* we load the value in a separate instruction: this mechanism may be
7219                          * used later as a safer way to do thread interruption
7220                          */
7221                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7222                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7223                         patch = code;
7224                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7225                         /* note that the call trampoline will preserve eax/edx */
7226                         x86_call_reg (code, X86_ECX);
7227                         x86_patch (patch, code);
7228                 } else {
7229                         /* FIXME: maybe save the jit tls in the prolog */
7230                 }
7231                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7232                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7233                 }
7234         }
7235
7236         /* Restore callee saved regs */
7237         for (i = 0; i < AMD64_NREG; ++i) {
7238                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7239                         /* Restore only used_int_regs, not arch.saved_iregs */
7240                         if (cfg->used_int_regs & (1 << i)) {
7241                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7242                                 mono_emit_unwind_op_same_value (cfg, code, i);
7243                                 async_exc_point (code);
7244                         }
7245                         save_area_offset += 8;
7246                 }
7247         }
7248
7249         /* Load returned vtypes into registers if needed */
7250         cinfo = cfg->arch.cinfo;
7251         if (cinfo->ret.storage == ArgValuetypeInReg) {
7252                 ArgInfo *ainfo = &cinfo->ret;
7253                 MonoInst *inst = cfg->ret;
7254
7255                 for (quad = 0; quad < 2; quad ++) {
7256                         switch (ainfo->pair_storage [quad]) {
7257                         case ArgInIReg:
7258                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7259                                 break;
7260                         case ArgInFloatSSEReg:
7261                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7262                                 break;
7263                         case ArgInDoubleSSEReg:
7264                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7265                                 break;
7266                         case ArgNone:
7267                                 break;
7268                         default:
7269                                 g_assert_not_reached ();
7270                         }
7271                 }
7272         }
7273
7274         if (cfg->arch.omit_fp) {
7275                 if (cfg->arch.stack_alloc_size) {
7276                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7277                 }
7278         } else {
7279                 amd64_leave (code);
7280                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7281         }
7282         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7283         async_exc_point (code);
7284         amd64_ret (code);
7285
7286         /* Restore the unwind state to be the same as before the epilog */
7287         mono_emit_unwind_op_restore_state (cfg, code);
7288
7289         cfg->code_len = code - cfg->native_code;
7290
7291         g_assert (cfg->code_len < cfg->code_size);
7292 }
7293
7294 void
7295 mono_arch_emit_exceptions (MonoCompile *cfg)
7296 {
7297         MonoJumpInfo *patch_info;
7298         int nthrows, i;
7299         guint8 *code;
7300         MonoClass *exc_classes [16];
7301         guint8 *exc_throw_start [16], *exc_throw_end [16];
7302         guint32 code_size = 0;
7303
7304         /* Compute needed space */
7305         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7306                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7307                         code_size += 40;
7308                 if (patch_info->type == MONO_PATCH_INFO_R8)
7309                         code_size += 8 + 15; /* sizeof (double) + alignment */
7310                 if (patch_info->type == MONO_PATCH_INFO_R4)
7311                         code_size += 4 + 15; /* sizeof (float) + alignment */
7312                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7313                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7314         }
7315
7316 #ifdef __native_client_codegen__
7317         /* Give us extra room on Native Client.  This could be   */
7318         /* more carefully calculated, but bundle alignment makes */
7319         /* it much trickier, so *2 like other places is good.    */
7320         code_size *= 2;
7321 #endif
7322
7323         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7324                 cfg->code_size *= 2;
7325                 cfg->native_code = mono_realloc_native_code (cfg);
7326                 cfg->stat_code_reallocs++;
7327         }
7328
7329         code = cfg->native_code + cfg->code_len;
7330
7331         /* add code to raise exceptions */
7332         nthrows = 0;
7333         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7334                 switch (patch_info->type) {
7335                 case MONO_PATCH_INFO_EXC: {
7336                         MonoClass *exc_class;
7337                         guint8 *buf, *buf2;
7338                         guint32 throw_ip;
7339
7340                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7341
7342                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7343                         g_assert (exc_class);
7344                         throw_ip = patch_info->ip.i;
7345
7346                         //x86_breakpoint (code);
7347                         /* Find a throw sequence for the same exception class */
7348                         for (i = 0; i < nthrows; ++i)
7349                                 if (exc_classes [i] == exc_class)
7350                                         break;
7351                         if (i < nthrows) {
7352                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7353                                 x86_jump_code (code, exc_throw_start [i]);
7354                                 patch_info->type = MONO_PATCH_INFO_NONE;
7355                         }
7356                         else {
7357                                 buf = code;
7358                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7359                                 buf2 = code;
7360
7361                                 if (nthrows < 16) {
7362                                         exc_classes [nthrows] = exc_class;
7363                                         exc_throw_start [nthrows] = code;
7364                                 }
7365                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7366
7367                                 patch_info->type = MONO_PATCH_INFO_NONE;
7368
7369                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7370
7371                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7372                                 while (buf < buf2)
7373                                         x86_nop (buf);
7374
7375                                 if (nthrows < 16) {
7376                                         exc_throw_end [nthrows] = code;
7377                                         nthrows ++;
7378                                 }
7379                         }
7380                         break;
7381                 }
7382                 default:
7383                         /* do nothing */
7384                         break;
7385                 }
7386                 g_assert(code < cfg->native_code + cfg->code_size);
7387         }
7388
7389         /* Handle relocations with RIP relative addressing */
7390         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7391                 gboolean remove = FALSE;
7392                 guint8 *orig_code = code;
7393
7394                 switch (patch_info->type) {
7395                 case MONO_PATCH_INFO_R8:
7396                 case MONO_PATCH_INFO_R4: {
7397                         guint8 *pos, *patch_pos;
7398                         guint32 target_pos;
7399
7400                         /* The SSE opcodes require a 16 byte alignment */
7401 #if defined(__default_codegen__)
7402                         code = (guint8*)ALIGN_TO (code, 16);
7403 #elif defined(__native_client_codegen__)
7404                         {
7405                                 /* Pad this out with HLT instructions  */
7406                                 /* or we can get garbage bytes emitted */
7407                                 /* which will fail validation          */
7408                                 guint8 *aligned_code;
7409                                 /* extra align to make room for  */
7410                                 /* mov/push below                      */
7411                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7412                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7413                                 /* The technique of hiding data in an  */
7414                                 /* instruction has a problem here: we  */
7415                                 /* need the data aligned to a 16-byte  */
7416                                 /* boundary but the instruction cannot */
7417                                 /* cross the bundle boundary. so only  */
7418                                 /* odd multiples of 16 can be used     */
7419                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7420                                         aligned_code += 16;
7421                                 }
7422                                 while (code < aligned_code) {
7423                                         *(code++) = 0xf4; /* hlt */
7424                                 }
7425                         }
7426 #endif
7427
7428                         pos = cfg->native_code + patch_info->ip.i;
7429                         if (IS_REX (pos [1])) {
7430                                 patch_pos = pos + 5;
7431                                 target_pos = code - pos - 9;
7432                         }
7433                         else {
7434                                 patch_pos = pos + 4;
7435                                 target_pos = code - pos - 8;
7436                         }
7437
7438                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7439 #ifdef __native_client_codegen__
7440                                 /* Hide 64-bit data in a         */
7441                                 /* "mov imm64, r11" instruction. */
7442                                 /* write it before the start of  */
7443                                 /* the data*/
7444                                 *(code-2) = 0x49; /* prefix      */
7445                                 *(code-1) = 0xbb; /* mov X, %r11 */
7446 #endif
7447                                 *(double*)code = *(double*)patch_info->data.target;
7448                                 code += sizeof (double);
7449                         } else {
7450 #ifdef __native_client_codegen__
7451                                 /* Hide 32-bit data in a        */
7452                                 /* "push imm32" instruction.    */
7453                                 *(code-1) = 0x68; /* push */
7454 #endif
7455                                 *(float*)code = *(float*)patch_info->data.target;
7456                                 code += sizeof (float);
7457                         }
7458
7459                         *(guint32*)(patch_pos) = target_pos;
7460
7461                         remove = TRUE;
7462                         break;
7463                 }
7464                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7465                         guint8 *pos;
7466
7467                         if (cfg->compile_aot)
7468                                 continue;
7469
7470                         /*loading is faster against aligned addresses.*/
7471                         code = (guint8*)ALIGN_TO (code, 8);
7472                         memset (orig_code, 0, code - orig_code);
7473
7474                         pos = cfg->native_code + patch_info->ip.i;
7475
7476                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7477                         if (IS_REX (pos [1]))
7478                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7479                         else
7480                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7481
7482                         *(gpointer*)code = (gpointer)patch_info->data.target;
7483                         code += sizeof (gpointer);
7484
7485                         remove = TRUE;
7486                         break;
7487                 }
7488                 default:
7489                         break;
7490                 }
7491
7492                 if (remove) {
7493                         if (patch_info == cfg->patch_info)
7494                                 cfg->patch_info = patch_info->next;
7495                         else {
7496                                 MonoJumpInfo *tmp;
7497
7498                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7499                                         ;
7500                                 tmp->next = patch_info->next;
7501                         }
7502                 }
7503                 g_assert (code < cfg->native_code + cfg->code_size);
7504         }
7505
7506         cfg->code_len = code - cfg->native_code;
7507
7508         g_assert (cfg->code_len < cfg->code_size);
7509
7510 }
7511
7512 #endif /* DISABLE_JIT */
7513
7514 void*
7515 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7516 {
7517         guchar *code = p;
7518         MonoMethodSignature *sig;
7519         MonoInst *inst;
7520         int i, n, stack_area = 0;
7521
7522         /* Keep this in sync with mono_arch_get_argument_info */
7523
7524         if (enable_arguments) {
7525                 /* Allocate a new area on the stack and save arguments there */
7526                 sig = mono_method_signature (cfg->method);
7527
7528                 n = sig->param_count + sig->hasthis;
7529
7530                 stack_area = ALIGN_TO (n * 8, 16);
7531
7532                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7533
7534                 for (i = 0; i < n; ++i) {
7535                         inst = cfg->args [i];
7536
7537                         if (inst->opcode == OP_REGVAR)
7538                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7539                         else {
7540                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7541                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7542                         }
7543                 }
7544         }
7545
7546         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7547         amd64_set_reg_template (code, AMD64_ARG_REG1);
7548         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7549         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7550
7551         if (enable_arguments)
7552                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7553
7554         return code;
7555 }
7556
7557 enum {
7558         SAVE_NONE,
7559         SAVE_STRUCT,
7560         SAVE_EAX,
7561         SAVE_EAX_EDX,
7562         SAVE_XMM
7563 };
7564
7565 void*
7566 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7567 {
7568         guchar *code = p;
7569         int save_mode = SAVE_NONE;
7570         MonoMethod *method = cfg->method;
7571         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7572         int i;
7573
7574         switch (ret_type->type) {
7575         case MONO_TYPE_VOID:
7576                 /* special case string .ctor icall */
7577                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7578                         save_mode = SAVE_EAX;
7579                 else
7580                         save_mode = SAVE_NONE;
7581                 break;
7582         case MONO_TYPE_I8:
7583         case MONO_TYPE_U8:
7584                 save_mode = SAVE_EAX;
7585                 break;
7586         case MONO_TYPE_R4:
7587         case MONO_TYPE_R8:
7588                 save_mode = SAVE_XMM;
7589                 break;
7590         case MONO_TYPE_GENERICINST:
7591                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7592                         save_mode = SAVE_EAX;
7593                         break;
7594                 }
7595                 /* Fall through */
7596         case MONO_TYPE_VALUETYPE:
7597                 save_mode = SAVE_STRUCT;
7598                 break;
7599         default:
7600                 save_mode = SAVE_EAX;
7601                 break;
7602         }
7603
7604         /* Save the result and copy it into the proper argument register */
7605         switch (save_mode) {
7606         case SAVE_EAX:
7607                 amd64_push_reg (code, AMD64_RAX);
7608                 /* Align stack */
7609                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7610                 if (enable_arguments)
7611                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7612                 break;
7613         case SAVE_STRUCT:
7614                 /* FIXME: */
7615                 if (enable_arguments)
7616                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7617                 break;
7618         case SAVE_XMM:
7619                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7620                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7621                 /* Align stack */
7622                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7623                 /*
7624                  * The result is already in the proper argument register so no copying
7625                  * needed.
7626                  */
7627                 break;
7628         case SAVE_NONE:
7629                 break;
7630         default:
7631                 g_assert_not_reached ();
7632         }
7633
7634         /* Set %al since this is a varargs call */
7635         if (save_mode == SAVE_XMM)
7636                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7637         else
7638                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7639
7640         if (preserve_argument_registers) {
7641                 for (i = 0; i < PARAM_REGS; ++i)
7642                         amd64_push_reg (code, param_regs [i]);
7643         }
7644
7645         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7646         amd64_set_reg_template (code, AMD64_ARG_REG1);
7647         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7648
7649         if (preserve_argument_registers) {
7650                 for (i = PARAM_REGS - 1; i >= 0; --i)
7651                         amd64_pop_reg (code, param_regs [i]);
7652         }
7653
7654         /* Restore result */
7655         switch (save_mode) {
7656         case SAVE_EAX:
7657                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7658                 amd64_pop_reg (code, AMD64_RAX);
7659                 break;
7660         case SAVE_STRUCT:
7661                 /* FIXME: */
7662                 break;
7663         case SAVE_XMM:
7664                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7665                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7666                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7667                 break;
7668         case SAVE_NONE:
7669                 break;
7670         default:
7671                 g_assert_not_reached ();
7672         }
7673
7674         return code;
7675 }
7676
7677 void
7678 mono_arch_flush_icache (guint8 *code, gint size)
7679 {
7680         /* Not needed */
7681 }
7682
7683 void
7684 mono_arch_flush_register_windows (void)
7685 {
7686 }
7687
7688 gboolean
7689 mono_arch_is_inst_imm (gint64 imm)
7690 {
7691         return amd64_use_imm32 (imm);
7692 }
7693
7694 /*
7695  * Determine whenever the trap whose info is in SIGINFO is caused by
7696  * integer overflow.
7697  */
7698 gboolean
7699 mono_arch_is_int_overflow (void *sigctx, void *info)
7700 {
7701         MonoContext ctx;
7702         guint8* rip;
7703         int reg;
7704         gint64 value;
7705
7706         mono_sigctx_to_monoctx (sigctx, &ctx);
7707
7708         rip = (guint8*)ctx.gregs [AMD64_RIP];
7709
7710         if (IS_REX (rip [0])) {
7711                 reg = amd64_rex_b (rip [0]);
7712                 rip ++;
7713         }
7714         else
7715                 reg = 0;
7716
7717         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7718                 /* idiv REG */
7719                 reg += x86_modrm_rm (rip [1]);
7720
7721                 value = ctx.gregs [reg];
7722
7723                 if (value == -1)
7724                         return TRUE;
7725         }
7726
7727         return FALSE;
7728 }
7729
7730 guint32
7731 mono_arch_get_patch_offset (guint8 *code)
7732 {
7733         return 3;
7734 }
7735
7736 /**
7737  * mono_breakpoint_clean_code:
7738  *
7739  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7740  * breakpoints in the original code, they are removed in the copy.
7741  *
7742  * Returns TRUE if no sw breakpoint was present.
7743  */
7744 gboolean
7745 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7746 {
7747         /*
7748          * If method_start is non-NULL we need to perform bound checks, since we access memory
7749          * at code - offset we could go before the start of the method and end up in a different
7750          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7751          * instead.
7752          */
7753         if (!method_start || code - offset >= method_start) {
7754                 memcpy (buf, code - offset, size);
7755         } else {
7756                 int diff = code - method_start;
7757                 memset (buf, 0, size);
7758                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7759         }
7760         return TRUE;
7761 }
7762
7763 #if defined(__native_client_codegen__)
7764 /* For membase calls, we want the base register. for Native Client,  */
7765 /* all indirect calls have the following sequence with the given sizes: */
7766 /* mov %eXX,%eXX                                [2-3]   */
7767 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7768 /* and $0xffffffffffffffe0,%r11d                [4]     */
7769 /* add %r15,%r11                                [3]     */
7770 /* callq *%r11                                  [3]     */
7771
7772
7773 /* Determine if code points to a NaCl call-through-register sequence, */
7774 /* (i.e., the last 3 instructions listed above) */
7775 int
7776 is_nacl_call_reg_sequence(guint8* code)
7777 {
7778         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7779                                "\x4d\x03\xdf"     /* add */
7780                                "\x41\xff\xd3";   /* call */
7781         return memcmp(code, sequence, 10) == 0;
7782 }
7783
7784 /* Determine if code points to the first opcode of the mov membase component */
7785 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7786 /* (there could be a REX prefix before the opcode but it is ignored) */
7787 static int
7788 is_nacl_indirect_call_membase_sequence(guint8* code)
7789 {
7790                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7791         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7792                /* and that src reg = dest reg */
7793                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7794                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7795                IS_REX(code[2]) &&
7796                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7797                /* and has dst of r11 and base of r15 */
7798                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7799                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7800 }
7801 #endif /* __native_client_codegen__ */
7802
7803 int
7804 mono_arch_get_this_arg_reg (guint8 *code)
7805 {
7806         return AMD64_ARG_REG1;
7807 }
7808
7809 gpointer
7810 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7811 {
7812         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7813 }
7814
7815 #define MAX_ARCH_DELEGATE_PARAMS 10
7816
7817 static gpointer
7818 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7819 {
7820         guint8 *code, *start;
7821         int i;
7822
7823         if (has_target) {
7824                 start = code = mono_global_codeman_reserve (64);
7825
7826                 /* Replace the this argument with the target */
7827                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7828                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7829                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7830
7831                 g_assert ((code - start) < 64);
7832         } else {
7833                 start = code = mono_global_codeman_reserve (64);
7834
7835                 if (param_count == 0) {
7836                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7837                 } else {
7838                         /* We have to shift the arguments left */
7839                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7840                         for (i = 0; i < param_count; ++i) {
7841 #ifdef TARGET_WIN32
7842                                 if (i < 3)
7843                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7844                                 else
7845                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7846 #else
7847                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7848 #endif
7849                         }
7850
7851                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7852                 }
7853                 g_assert ((code - start) < 64);
7854         }
7855
7856         nacl_global_codeman_validate (&start, 64, &code);
7857         mono_arch_flush_icache (start, code - start);
7858
7859         if (code_len)
7860                 *code_len = code - start;
7861
7862         if (mono_jit_map_is_enabled ()) {
7863                 char *buff;
7864                 if (has_target)
7865                         buff = (char*)"delegate_invoke_has_target";
7866                 else
7867                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7868                 mono_emit_jit_tramp (start, code - start, buff);
7869                 if (!has_target)
7870                         g_free (buff);
7871         }
7872         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7873
7874         return start;
7875 }
7876
7877 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7878
7879 static gpointer
7880 get_delegate_virtual_invoke_impl (gboolean load_imt_reg, int offset, guint32 *code_len)
7881 {
7882         guint8 *code, *start;
7883         int size = 20;
7884
7885         if (offset / sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7886                 return NULL;
7887
7888         start = code = mono_global_codeman_reserve (size);
7889
7890         /* Replace the this argument with the target */
7891         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7892         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7893
7894         if (load_imt_reg) {
7895                 /* Load the IMT reg */
7896                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7897         }
7898
7899         /* Load the vtable */
7900         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7901         amd64_jump_membase (code, AMD64_RAX, offset);
7902         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7903
7904         if (code_len)
7905                 *code_len = code - start;
7906
7907         return start;
7908 }
7909
7910 /*
7911  * mono_arch_get_delegate_invoke_impls:
7912  *
7913  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7914  * trampolines.
7915  */
7916 GSList*
7917 mono_arch_get_delegate_invoke_impls (void)
7918 {
7919         GSList *res = NULL;
7920         guint8 *code;
7921         guint32 code_len;
7922         int i;
7923         char *tramp_name;
7924
7925         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7926         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7927
7928         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7929                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7930                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7931                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7932                 g_free (tramp_name);
7933         }
7934
7935         for (i = 0; i < MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7936                 code = get_delegate_virtual_invoke_impl (TRUE, i * SIZEOF_VOID_P, &code_len);
7937                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", i);
7938                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7939                 g_free (tramp_name);
7940
7941                 code = get_delegate_virtual_invoke_impl (FALSE, i * SIZEOF_VOID_P, &code_len);
7942                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", i);
7943                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7944                 g_free (tramp_name);
7945         }
7946
7947         return res;
7948 }
7949
7950 gpointer
7951 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7952 {
7953         guint8 *code, *start;
7954         int i;
7955
7956         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7957                 return NULL;
7958
7959         /* FIXME: Support more cases */
7960         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7961                 return NULL;
7962
7963         if (has_target) {
7964                 static guint8* cached = NULL;
7965
7966                 if (cached)
7967                         return cached;
7968
7969                 if (mono_aot_only)
7970                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7971                 else
7972                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7973
7974                 mono_memory_barrier ();
7975
7976                 cached = start;
7977         } else {
7978                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7979                 for (i = 0; i < sig->param_count; ++i)
7980                         if (!mono_is_regsize_var (sig->params [i]))
7981                                 return NULL;
7982                 if (sig->param_count > 4)
7983                         return NULL;
7984
7985                 code = cache [sig->param_count];
7986                 if (code)
7987                         return code;
7988
7989                 if (mono_aot_only) {
7990                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7991                         start = mono_aot_get_trampoline (name);
7992                         g_free (name);
7993                 } else {
7994                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7995                 }
7996
7997                 mono_memory_barrier ();
7998
7999                 cache [sig->param_count] = start;
8000         }
8001
8002         return start;
8003 }
8004
8005 gpointer
8006 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8007 {
8008         return get_delegate_virtual_invoke_impl (load_imt_reg, offset, NULL);
8009 }
8010
8011 void
8012 mono_arch_finish_init (void)
8013 {
8014 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8015         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8016 #endif
8017 }
8018
8019 void
8020 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8021 {
8022 }
8023
8024 #if defined(__default_codegen__)
8025 #define CMP_SIZE (6 + 1)
8026 #define CMP_REG_REG_SIZE (4 + 1)
8027 #define BR_SMALL_SIZE 2
8028 #define BR_LARGE_SIZE 6
8029 #define MOV_REG_IMM_SIZE 10
8030 #define MOV_REG_IMM_32BIT_SIZE 6
8031 #define JUMP_REG_SIZE (2 + 1)
8032 #elif defined(__native_client_codegen__)
8033 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8034 #define CMP_SIZE ((6 + 1) * 2 - 1)
8035 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8036 #define BR_SMALL_SIZE (2 * 2 - 1)
8037 #define BR_LARGE_SIZE (6 * 2 - 1)
8038 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8039 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8040 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8041 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8042 /* Jump membase's size is large and unpredictable    */
8043 /* in native client, just pad it out a whole bundle. */
8044 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8045 #endif
8046
8047 static int
8048 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8049 {
8050         int i, distance = 0;
8051         for (i = start; i < target; ++i)
8052                 distance += imt_entries [i]->chunk_size;
8053         return distance;
8054 }
8055
8056 /*
8057  * LOCKING: called with the domain lock held
8058  */
8059 gpointer
8060 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8061         gpointer fail_tramp)
8062 {
8063         int i;
8064         int size = 0;
8065         guint8 *code, *start;
8066         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8067
8068         for (i = 0; i < count; ++i) {
8069                 MonoIMTCheckItem *item = imt_entries [i];
8070                 if (item->is_equals) {
8071                         if (item->check_target_idx) {
8072                                 if (!item->compare_done) {
8073                                         if (amd64_use_imm32 ((gint64)item->key))
8074                                                 item->chunk_size += CMP_SIZE;
8075                                         else
8076                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8077                                 }
8078                                 if (item->has_target_code) {
8079                                         item->chunk_size += MOV_REG_IMM_SIZE;
8080                                 } else {
8081                                         if (vtable_is_32bit)
8082                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8083                                         else
8084                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8085 #ifdef __native_client_codegen__
8086                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8087 #endif
8088                                 }
8089                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8090                         } else {
8091                                 if (fail_tramp) {
8092                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8093                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8094                                 } else {
8095                                         if (vtable_is_32bit)
8096                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8097                                         else
8098                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8099                                         item->chunk_size += JUMP_REG_SIZE;
8100                                         /* with assert below:
8101                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8102                                          */
8103 #ifdef __native_client_codegen__
8104                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8105 #endif
8106                                 }
8107                         }
8108                 } else {
8109                         if (amd64_use_imm32 ((gint64)item->key))
8110                                 item->chunk_size += CMP_SIZE;
8111                         else
8112                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8113                         item->chunk_size += BR_LARGE_SIZE;
8114                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8115                 }
8116                 size += item->chunk_size;
8117         }
8118 #if defined(__native_client__) && defined(__native_client_codegen__)
8119         /* In Native Client, we don't re-use thunks, allocate from the */
8120         /* normal code manager paths. */
8121         code = mono_domain_code_reserve (domain, size);
8122 #else
8123         if (fail_tramp)
8124                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8125         else
8126                 code = mono_domain_code_reserve (domain, size);
8127 #endif
8128         start = code;
8129         for (i = 0; i < count; ++i) {
8130                 MonoIMTCheckItem *item = imt_entries [i];
8131                 item->code_target = code;
8132                 if (item->is_equals) {
8133                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8134
8135                         if (item->check_target_idx || fail_case) {
8136                                 if (!item->compare_done || fail_case) {
8137                                         if (amd64_use_imm32 ((gint64)item->key))
8138                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8139                                         else {
8140                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8141                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8142                                         }
8143                                 }
8144                                 item->jmp_code = code;
8145                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8146                                 if (item->has_target_code) {
8147                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8148                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8149                                 } else {
8150                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8151                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8152                                 }
8153
8154                                 if (fail_case) {
8155                                         amd64_patch (item->jmp_code, code);
8156                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8157                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8158                                         item->jmp_code = NULL;
8159                                 }
8160                         } else {
8161                                 /* enable the commented code to assert on wrong method */
8162 #if 0
8163                                 if (amd64_is_imm32 (item->key))
8164                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8165                                 else {
8166                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8167                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8168                                 }
8169                                 item->jmp_code = code;
8170                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8171                                 /* See the comment below about R10 */
8172                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8173                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8174                                 amd64_patch (item->jmp_code, code);
8175                                 amd64_breakpoint (code);
8176                                 item->jmp_code = NULL;
8177 #else
8178                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8179                                    needs to be preserved.  R10 needs
8180                                    to be preserved for calls which
8181                                    require a runtime generic context,
8182                                    but interface calls don't. */
8183                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8184                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8185 #endif
8186                         }
8187                 } else {
8188                         if (amd64_use_imm32 ((gint64)item->key))
8189                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8190                         else {
8191                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8192                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8193                         }
8194                         item->jmp_code = code;
8195                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8196                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8197                         else
8198                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8199                 }
8200                 g_assert (code - item->code_target <= item->chunk_size);
8201         }
8202         /* patch the branches to get to the target items */
8203         for (i = 0; i < count; ++i) {
8204                 MonoIMTCheckItem *item = imt_entries [i];
8205                 if (item->jmp_code) {
8206                         if (item->check_target_idx) {
8207                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8208                         }
8209                 }
8210         }
8211
8212         if (!fail_tramp)
8213                 mono_stats.imt_thunks_size += code - start;
8214         g_assert (code - start <= size);
8215
8216         nacl_domain_code_validate(domain, &start, size, &code);
8217         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8218
8219         return start;
8220 }
8221
8222 MonoMethod*
8223 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8224 {
8225         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8226 }
8227
8228 MonoVTable*
8229 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8230 {
8231         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8232 }
8233
8234 GSList*
8235 mono_arch_get_cie_program (void)
8236 {
8237         GSList *l = NULL;
8238
8239         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8240         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8241
8242         return l;
8243 }
8244
8245 #ifndef DISABLE_JIT
8246
8247 MonoInst*
8248 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8249 {
8250         MonoInst *ins = NULL;
8251         int opcode = 0;
8252
8253         if (cmethod->klass == mono_defaults.math_class) {
8254                 if (strcmp (cmethod->name, "Sin") == 0) {
8255                         opcode = OP_SIN;
8256                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8257                         opcode = OP_COS;
8258                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8259                         opcode = OP_SQRT;
8260                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8261                         opcode = OP_ABS;
8262                 }
8263
8264                 if (opcode && fsig->param_count == 1) {
8265                         MONO_INST_NEW (cfg, ins, opcode);
8266                         ins->type = STACK_R8;
8267                         ins->dreg = mono_alloc_freg (cfg);
8268                         ins->sreg1 = args [0]->dreg;
8269                         MONO_ADD_INS (cfg->cbb, ins);
8270                 }
8271
8272                 opcode = 0;
8273                 if (cfg->opt & MONO_OPT_CMOV) {
8274                         if (strcmp (cmethod->name, "Min") == 0) {
8275                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8276                                         opcode = OP_IMIN;
8277                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8278                                         opcode = OP_IMIN_UN;
8279                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8280                                         opcode = OP_LMIN;
8281                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8282                                         opcode = OP_LMIN_UN;
8283                         } else if (strcmp (cmethod->name, "Max") == 0) {
8284                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8285                                         opcode = OP_IMAX;
8286                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8287                                         opcode = OP_IMAX_UN;
8288                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8289                                         opcode = OP_LMAX;
8290                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8291                                         opcode = OP_LMAX_UN;
8292                         }
8293                 }
8294
8295                 if (opcode && fsig->param_count == 2) {
8296                         MONO_INST_NEW (cfg, ins, opcode);
8297                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8298                         ins->dreg = mono_alloc_ireg (cfg);
8299                         ins->sreg1 = args [0]->dreg;
8300                         ins->sreg2 = args [1]->dreg;
8301                         MONO_ADD_INS (cfg->cbb, ins);
8302                 }
8303
8304 #if 0
8305                 /* OP_FREM is not IEEE compatible */
8306                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8307                         MONO_INST_NEW (cfg, ins, OP_FREM);
8308                         ins->inst_i0 = args [0];
8309                         ins->inst_i1 = args [1];
8310                 }
8311 #endif
8312         }
8313
8314         return ins;
8315 }
8316 #endif
8317
8318 gboolean
8319 mono_arch_print_tree (MonoInst *tree, int arity)
8320 {
8321         return 0;
8322 }
8323
8324 mgreg_t
8325 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8326 {
8327         return ctx->gregs [reg];
8328 }
8329
8330 void
8331 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8332 {
8333         ctx->gregs [reg] = val;
8334 }
8335
8336 gpointer
8337 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8338 {
8339         gpointer *sp, old_value;
8340         char *bp;
8341
8342         /*Load the spvar*/
8343         bp = MONO_CONTEXT_GET_BP (ctx);
8344         sp = *(gpointer*)(bp + clause->exvar_offset);
8345
8346         old_value = *sp;
8347         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8348                 return old_value;
8349
8350         *sp = new_value;
8351
8352         return old_value;
8353 }
8354
8355 /*
8356  * mono_arch_emit_load_aotconst:
8357  *
8358  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8359  * TARGET from the mscorlib GOT in full-aot code.
8360  * On AMD64, the result is placed into R11.
8361  */
8362 guint8*
8363 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8364 {
8365         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8366         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8367
8368         return code;
8369 }
8370
8371 /*
8372  * mono_arch_get_trampolines:
8373  *
8374  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8375  * for AOT.
8376  */
8377 GSList *
8378 mono_arch_get_trampolines (gboolean aot)
8379 {
8380         return mono_amd64_get_exception_trampolines (aot);
8381 }
8382
8383 /* Soft Debug support */
8384 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8385
8386 /*
8387  * mono_arch_set_breakpoint:
8388  *
8389  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8390  * The location should contain code emitted by OP_SEQ_POINT.
8391  */
8392 void
8393 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8394 {
8395         guint8 *code = ip;
8396         guint8 *orig_code = code;
8397
8398         if (ji->from_aot) {
8399                 guint32 native_offset = ip - (guint8*)ji->code_start;
8400                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8401
8402                 g_assert (info->bp_addrs [native_offset] == 0);
8403                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8404         } else {
8405                 /*
8406                  * In production, we will use int3 (has to fix the size in the md
8407                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8408                  * instead.
8409                  */
8410                 g_assert (code [0] == 0x90);
8411                 if (breakpoint_size == 8) {
8412                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8413                 } else {
8414                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8415                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8416                 }
8417
8418                 g_assert (code - orig_code == breakpoint_size);
8419         }
8420 }
8421
8422 /*
8423  * mono_arch_clear_breakpoint:
8424  *
8425  *   Clear the breakpoint at IP.
8426  */
8427 void
8428 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8429 {
8430         guint8 *code = ip;
8431         int i;
8432
8433         if (ji->from_aot) {
8434                 guint32 native_offset = ip - (guint8*)ji->code_start;
8435                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8436
8437                 info->bp_addrs [native_offset] = NULL;
8438         } else {
8439                 for (i = 0; i < breakpoint_size; ++i)
8440                         x86_nop (code);
8441         }
8442 }
8443
8444 gboolean
8445 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8446 {
8447 #ifdef HOST_WIN32
8448         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8449         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8450                 return TRUE;
8451         else
8452                 return FALSE;
8453 #else
8454         siginfo_t* sinfo = (siginfo_t*) info;
8455         /* Sometimes the address is off by 4 */
8456         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8457                 return TRUE;
8458         else
8459                 return FALSE;
8460 #endif
8461 }
8462
8463 /*
8464  * mono_arch_skip_breakpoint:
8465  *
8466  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8467  * we resume, the instruction is not executed again.
8468  */
8469 void
8470 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8471 {
8472         if (ji->from_aot) {
8473                 /* The breakpoint instruction is a call */
8474         } else {
8475                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8476         }
8477 }
8478
8479 /*
8480  * mono_arch_start_single_stepping:
8481  *
8482  *   Start single stepping.
8483  */
8484 void
8485 mono_arch_start_single_stepping (void)
8486 {
8487         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8488         ss_trampoline = mini_get_single_step_trampoline ();
8489 }
8490
8491 /*
8492  * mono_arch_stop_single_stepping:
8493  *
8494  *   Stop single stepping.
8495  */
8496 void
8497 mono_arch_stop_single_stepping (void)
8498 {
8499         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8500         ss_trampoline = NULL;
8501 }
8502
8503 /*
8504  * mono_arch_is_single_step_event:
8505  *
8506  *   Return whenever the machine state in SIGCTX corresponds to a single
8507  * step event.
8508  */
8509 gboolean
8510 mono_arch_is_single_step_event (void *info, void *sigctx)
8511 {
8512 #ifdef HOST_WIN32
8513         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8514         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8515                 return TRUE;
8516         else
8517                 return FALSE;
8518 #else
8519         siginfo_t* sinfo = (siginfo_t*) info;
8520         /* Sometimes the address is off by 4 */
8521         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8522                 return TRUE;
8523         else
8524                 return FALSE;
8525 #endif
8526 }
8527
8528 /*
8529  * mono_arch_skip_single_step:
8530  *
8531  *   Modify CTX so the ip is placed after the single step trigger instruction,
8532  * we resume, the instruction is not executed again.
8533  */
8534 void
8535 mono_arch_skip_single_step (MonoContext *ctx)
8536 {
8537         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8538 }
8539
8540 /*
8541  * mono_arch_create_seq_point_info:
8542  *
8543  *   Return a pointer to a data structure which is used by the sequence
8544  * point implementation in AOTed code.
8545  */
8546 gpointer
8547 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8548 {
8549         SeqPointInfo *info;
8550         MonoJitInfo *ji;
8551
8552         // FIXME: Add a free function
8553
8554         mono_domain_lock (domain);
8555         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8556                                                                 code);
8557         mono_domain_unlock (domain);
8558
8559         if (!info) {
8560                 ji = mono_jit_info_table_find (domain, (char*)code);
8561                 g_assert (ji);
8562
8563                 // FIXME: Optimize the size
8564                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8565
8566                 info->ss_tramp_addr = &ss_trampoline;
8567
8568                 mono_domain_lock (domain);
8569                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8570                                                          code, info);
8571                 mono_domain_unlock (domain);
8572         }
8573
8574         return info;
8575 }
8576
8577 void
8578 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8579 {
8580         ext->lmf.previous_lmf = prev_lmf;
8581         /* Mark that this is a MonoLMFExt */
8582         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8583         ext->lmf.rsp = (gssize)ext;
8584 }
8585
8586 #endif
8587
8588 gboolean
8589 mono_arch_opcode_supported (int opcode)
8590 {
8591         switch (opcode) {
8592         case OP_ATOMIC_ADD_I4:
8593         case OP_ATOMIC_ADD_I8:
8594         case OP_ATOMIC_EXCHANGE_I4:
8595         case OP_ATOMIC_EXCHANGE_I8:
8596         case OP_ATOMIC_CAS_I4:
8597         case OP_ATOMIC_CAS_I8:
8598         case OP_ATOMIC_LOAD_I1:
8599         case OP_ATOMIC_LOAD_I2:
8600         case OP_ATOMIC_LOAD_I4:
8601         case OP_ATOMIC_LOAD_I8:
8602         case OP_ATOMIC_LOAD_U1:
8603         case OP_ATOMIC_LOAD_U2:
8604         case OP_ATOMIC_LOAD_U4:
8605         case OP_ATOMIC_LOAD_U8:
8606         case OP_ATOMIC_LOAD_R4:
8607         case OP_ATOMIC_LOAD_R8:
8608         case OP_ATOMIC_STORE_I1:
8609         case OP_ATOMIC_STORE_I2:
8610         case OP_ATOMIC_STORE_I4:
8611         case OP_ATOMIC_STORE_I8:
8612         case OP_ATOMIC_STORE_U1:
8613         case OP_ATOMIC_STORE_U2:
8614         case OP_ATOMIC_STORE_U4:
8615         case OP_ATOMIC_STORE_U8:
8616         case OP_ATOMIC_STORE_R4:
8617         case OP_ATOMIC_STORE_R8:
8618                 return TRUE;
8619         default:
8620                 return FALSE;
8621         }
8622 }