mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         /* The size of each pair */
 506         int pair_size [2];
 507         int nregs;
 508 } ArgInfo;
 509
 510 typedef struct {
 511         int nargs;
 512         guint32 stack_usage;
 513         guint32 reg_usage;
 514         guint32 freg_usage;
 515         gboolean need_stack_align;
 516         gboolean vtype_retaddr;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 #ifdef HOST_WIN32
 527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 528
 529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 530 #else
 531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 532
 533  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #endif
 535
 536 static void inline
 537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 538 {
 539     ainfo->offset = *stack_size;
 540
 541     if (*gr >= PARAM_REGS) {
 542                 ainfo->storage = ArgOnStack;
 543                 /* Since the same stack slot size is used for all arg */
 544                 /*  types, it needs to be big enough to hold them all */
 545                 (*stack_size) += sizeof(mgreg_t);
 546     }
 547     else {
 548                 ainfo->storage = ArgInIReg;
 549                 ainfo->reg = param_regs [*gr];
 550                 (*gr) ++;
 551     }
 552 }
 553
 554 #ifdef HOST_WIN32
 555 #define FLOAT_PARAM_REGS 4
 556 #else
 557 #define FLOAT_PARAM_REGS 8
 558 #endif
 559
 560 static void inline
 561 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 562 {
 563     ainfo->offset = *stack_size;
 564
 565     if (*gr >= FLOAT_PARAM_REGS) {
 566                 ainfo->storage = ArgOnStack;
 567                 /* Since the same stack slot size is used for both float */
 568                 /*  types, it needs to be big enough to hold them both */
 569                 (*stack_size) += sizeof(mgreg_t);
 570     }
 571     else {
 572                 /* A double register */
 573                 if (is_double)
 574                         ainfo->storage = ArgInDoubleSSEReg;
 575                 else
 576                         ainfo->storage = ArgInFloatSSEReg;
 577                 ainfo->reg = *gr;
 578                 (*gr) += 1;
 579     }
 580 }
 581
 582 typedef enum ArgumentClass {
 583         ARG_CLASS_NO_CLASS,
 584         ARG_CLASS_MEMORY,
 585         ARG_CLASS_INTEGER,
 586         ARG_CLASS_SSE
 587 } ArgumentClass;
 588
 589 static ArgumentClass
 590 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 591 {
 592         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 593         MonoType *ptype;
 594
 595         ptype = mini_type_get_underlying_type (gsctx, type);
 596         switch (ptype->type) {
 597         case MONO_TYPE_BOOLEAN:
 598         case MONO_TYPE_CHAR:
 599         case MONO_TYPE_I1:
 600         case MONO_TYPE_U1:
 601         case MONO_TYPE_I2:
 602         case MONO_TYPE_U2:
 603         case MONO_TYPE_I4:
 604         case MONO_TYPE_U4:
 605         case MONO_TYPE_I:
 606         case MONO_TYPE_U:
 607         case MONO_TYPE_STRING:
 608         case MONO_TYPE_OBJECT:
 609         case MONO_TYPE_CLASS:
 610         case MONO_TYPE_SZARRAY:
 611         case MONO_TYPE_PTR:
 612         case MONO_TYPE_FNPTR:
 613         case MONO_TYPE_ARRAY:
 614         case MONO_TYPE_I8:
 615         case MONO_TYPE_U8:
 616                 class2 = ARG_CLASS_INTEGER;
 617                 break;
 618         case MONO_TYPE_R4:
 619         case MONO_TYPE_R8:
 620 #ifdef HOST_WIN32
 621                 class2 = ARG_CLASS_INTEGER;
 622 #else
 623                 class2 = ARG_CLASS_SSE;
 624 #endif
 625                 break;
 626
 627         case MONO_TYPE_TYPEDBYREF:
 628                 g_assert_not_reached ();
 629
 630         case MONO_TYPE_GENERICINST:
 631                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 632                         class2 = ARG_CLASS_INTEGER;
 633                         break;
 634                 }
 635                 /* fall through */
 636         case MONO_TYPE_VALUETYPE: {
 637                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 638                 int i;
 639
 640                 for (i = 0; i < info->num_fields; ++i) {
 641                         class2 = class1;
 642                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 643                 }
 644                 break;
 645         }
 646         default:
 647                 g_assert_not_reached ();
 648         }
 649
 650         /* Merge */
 651         if (class1 == class2)
 652                 ;
 653         else if (class1 == ARG_CLASS_NO_CLASS)
 654                 class1 = class2;
 655         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 656                 class1 = ARG_CLASS_MEMORY;
 657         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 658                 class1 = ARG_CLASS_INTEGER;
 659         else
 660                 class1 = ARG_CLASS_SSE;
 661
 662         return class1;
 663 }
 664 #ifdef __native_client_codegen__
 665
 666 /* Default alignment for Native Client is 32-byte. */
 667 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 668
 669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 670 /* Check that alignment doesn't cross an alignment boundary.             */
 671 guint8*
 672 mono_arch_nacl_pad(guint8 *code, int pad)
 673 {
 674         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 675
 676         if (pad == 0) return code;
 677         /* assertion: alignment cannot cross a block boundary */
 678         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 679                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 680         while (pad >= kMaxPadding) {
 681                 amd64_padding (code, kMaxPadding);
 682                 pad -= kMaxPadding;
 683         }
 684         if (pad != 0) amd64_padding (code, pad);
 685         return code;
 686 }
 687 #endif
 688
 689 static int
 690 count_fields_nested (MonoClass *klass)
 691 {
 692         MonoMarshalType *info;
 693         int i, count;
 694
 695         info = mono_marshal_load_type_info (klass);
 696         g_assert(info);
 697         count = 0;
 698         for (i = 0; i < info->num_fields; ++i) {
 699                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 700                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 701                 else
 702                         count ++;
 703         }
 704         return count;
 705 }
 706
 707 static int
 708 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 709 {
 710         MonoMarshalType *info;
 711         int i;
 712
 713         info = mono_marshal_load_type_info (klass);
 714         g_assert(info);
 715         for (i = 0; i < info->num_fields; ++i) {
 716                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 717                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 718                 } else {
 719                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 720                         fields [index].offset += offset;
 721                         index ++;
 722                 }
 723         }
 724         return index;
 725 }
 726
 727 static void
 728 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 729                            gboolean is_return,
 730                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 731 {
 732         guint32 size, quad, nquads, i, nfields;
 733         /* Keep track of the size used in each quad so we can */
 734         /* use the right size when copying args/return vars.  */
 735         guint32 quadsize [2] = {8, 8};
 736         ArgumentClass args [2];
 737         MonoMarshalType *info = NULL;
 738         MonoMarshalField *fields = NULL;
 739         MonoClass *klass;
 740         MonoGenericSharingContext tmp_gsctx;
 741         gboolean pass_on_stack = FALSE;
 742
 743         /*
 744          * The gsctx currently contains no data, it is only used for checking whenever
 745          * open types are allowed, some callers like mono_arch_get_argument_info ()
 746          * don't pass it to us, so work around that.
 747          */
 748         if (!gsctx)
 749                 gsctx = &tmp_gsctx;
 750
 751         klass = mono_class_from_mono_type (type);
 752         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 753 #ifndef HOST_WIN32
 754         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 755                 /* We pass and return vtypes of size 8 in a register */
 756         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 757                 pass_on_stack = TRUE;
 758         }
 759 #else
 760         if (!sig->pinvoke) {
 761                 pass_on_stack = TRUE;
 762         }
 763 #endif
 764
 765         /* If this struct can't be split up naturally into 8-byte */
 766         /* chunks (registers), pass it on the stack.              */
 767         if (sig->pinvoke && !pass_on_stack) {
 768                 guint32 align;
 769                 guint32 field_size;
 770
 771                 info = mono_marshal_load_type_info (klass);
 772                 g_assert (info);
 773
 774                 /*
 775                  * Collect field information recursively to be able to
 776                  * handle nested structures.
 777                  */
 778                 nfields = count_fields_nested (klass);
 779                 fields = g_new0 (MonoMarshalField, nfields);
 780                 collect_field_info_nested (klass, fields, 0, 0);
 781
 782                 for (i = 0; i < nfields; ++i) {
 783                         field_size = mono_marshal_type_size (fields [i].field->type,
 784                                                            fields [i].mspec,
 785                                                            &align, TRUE, klass->unicode);
 786                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 787                                 pass_on_stack = TRUE;
 788                                 break;
 789                         }
 790                 }
 791         }
 792
 793         if (pass_on_stack) {
 794                 /* Allways pass in memory */
 795                 ainfo->offset = *stack_size;
 796                 *stack_size += ALIGN_TO (size, 8);
 797                 ainfo->storage = ArgOnStack;
 798
 799                 g_free (fields);
 800                 return;
 801         }
 802
 803         /* FIXME: Handle structs smaller than 8 bytes */
 804         //if ((size % 8) != 0)
 805         //      NOT_IMPLEMENTED;
 806
 807         if (size > 8)
 808                 nquads = 2;
 809         else
 810                 nquads = 1;
 811
 812         if (!sig->pinvoke) {
 813                 int n = mono_class_value_size (klass, NULL);
 814
 815                 quadsize [0] = n >= 8 ? 8 : n;
 816                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 817
 818                 /* Always pass in 1 or 2 integer registers */
 819                 args [0] = ARG_CLASS_INTEGER;
 820                 args [1] = ARG_CLASS_INTEGER;
 821                 /* Only the simplest cases are supported */
 822                 if (is_return && nquads != 1) {
 823                         args [0] = ARG_CLASS_MEMORY;
 824                         args [1] = ARG_CLASS_MEMORY;
 825                 }
 826         } else {
 827                 /*
 828                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 829                  * The X87 and SSEUP stuff is left out since there are no such types in
 830                  * the CLR.
 831                  */
 832                 g_assert (info);
 833                 g_assert (fields);
 834
 835 #ifndef HOST_WIN32
 836                 if (info->native_size > 16) {
 837                         ainfo->offset = *stack_size;
 838                         *stack_size += ALIGN_TO (info->native_size, 8);
 839                         ainfo->storage = ArgOnStack;
 840
 841                         g_free (fields);
 842                         return;
 843                 }
 844 #else
 845                 switch (info->native_size) {
 846                 case 1: case 2: case 4: case 8:
 847                         break;
 848                 default:
 849                         if (is_return) {
 850                                 ainfo->storage = ArgOnStack;
 851                                 ainfo->offset = *stack_size;
 852                                 *stack_size += ALIGN_TO (info->native_size, 8);
 853                         }
 854                         else {
 855                                 ainfo->storage = ArgValuetypeAddrInIReg;
 856
 857                                 if (*gr < PARAM_REGS) {
 858                                         ainfo->pair_storage [0] = ArgInIReg;
 859                                         ainfo->pair_regs [0] = param_regs [*gr];
 860                                         (*gr) ++;
 861                                 }
 862                                 else {
 863                                         ainfo->pair_storage [0] = ArgOnStack;
 864                                         ainfo->offset = *stack_size;
 865                                         *stack_size += 8;
 866                                 }
 867                         }
 868
 869                         g_free (fields);
 870                         return;
 871                 }
 872 #endif
 873
 874                 args [0] = ARG_CLASS_NO_CLASS;
 875                 args [1] = ARG_CLASS_NO_CLASS;
 876                 for (quad = 0; quad < nquads; ++quad) {
 877                         int size;
 878                         guint32 align;
 879                         ArgumentClass class1;
 880
 881                         if (nfields == 0)
 882                                 class1 = ARG_CLASS_MEMORY;
 883                         else
 884                                 class1 = ARG_CLASS_NO_CLASS;
 885                         for (i = 0; i < nfields; ++i) {
 886                                 size = mono_marshal_type_size (fields [i].field->type,
 887                                                                                            fields [i].mspec,
 888                                                                                            &align, TRUE, klass->unicode);
 889                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 890                                         /* Unaligned field */
 891                                         NOT_IMPLEMENTED;
 892                                 }
 893
 894                                 /* Skip fields in other quad */
 895                                 if ((quad == 0) && (fields [i].offset >= 8))
 896                                         continue;
 897                                 if ((quad == 1) && (fields [i].offset < 8))
 898                                         continue;
 899
 900                                 /* How far into this quad this data extends.*/
 901                                 /* (8 is size of quad) */
 902                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 903
 904                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 905                         }
 906                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 907                         args [quad] = class1;
 908                 }
 909         }
 910
 911         g_free (fields);
 912
 913         /* Post merger cleanup */
 914         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 915                 args [0] = args [1] = ARG_CLASS_MEMORY;
 916
 917         /* Allocate registers */
 918         {
 919                 int orig_gr = *gr;
 920                 int orig_fr = *fr;
 921
 922                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 923                         quadsize [0] ++;
 924                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 925                         quadsize [1] ++;
 926
 927                 ainfo->storage = ArgValuetypeInReg;
 928                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 929                 g_assert (quadsize [0] <= 8);
 930                 g_assert (quadsize [1] <= 8);
 931                 ainfo->pair_size [0] = quadsize [0];
 932                 ainfo->pair_size [1] = quadsize [1];
 933                 ainfo->nregs = nquads;
 934                 for (quad = 0; quad < nquads; ++quad) {
 935                         switch (args [quad]) {
 936                         case ARG_CLASS_INTEGER:
 937                                 if (*gr >= PARAM_REGS)
 938                                         args [quad] = ARG_CLASS_MEMORY;
 939                                 else {
 940                                         ainfo->pair_storage [quad] = ArgInIReg;
 941                                         if (is_return)
 942                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 943                                         else
 944                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 945                                         (*gr) ++;
 946                                 }
 947                                 break;
 948                         case ARG_CLASS_SSE:
 949                                 if (*fr >= FLOAT_PARAM_REGS)
 950                                         args [quad] = ARG_CLASS_MEMORY;
 951                                 else {
 952                                         if (quadsize[quad] <= 4)
 953                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 954                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 955                                         ainfo->pair_regs [quad] = *fr;
 956                                         (*fr) ++;
 957                                 }
 958                                 break;
 959                         case ARG_CLASS_MEMORY:
 960                                 break;
 961                         default:
 962                                 g_assert_not_reached ();
 963                         }
 964                 }
 965
 966                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 967                         /* Revert possible register assignments */
 968                         *gr = orig_gr;
 969                         *fr = orig_fr;
 970
 971                         ainfo->offset = *stack_size;
 972                         if (sig->pinvoke)
 973                                 *stack_size += ALIGN_TO (info->native_size, 8);
 974                         else
 975                                 *stack_size += nquads * sizeof(mgreg_t);
 976                         ainfo->storage = ArgOnStack;
 977                 }
 978         }
 979 }
 980
 981 /*
 982  * get_call_info:
 983  *
 984  *  Obtain information about a call according to the calling convention.
 985  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 986  * Draft Version 0.23" document for more information.
 987  */
 988 static CallInfo*
 989 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 990 {
 991         guint32 i, gr, fr, pstart;
 992         MonoType *ret_type;
 993         int n = sig->hasthis + sig->param_count;
 994         guint32 stack_size = 0;
 995         CallInfo *cinfo;
 996         gboolean is_pinvoke = sig->pinvoke;
 997
 998         if (mp)
 999                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1000         else
1001                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002
1003         cinfo->nargs = n;
1004
1005         gr = 0;
1006         fr = 0;
1007
1008 #ifdef HOST_WIN32
1009         /* Reserve space where the callee can save the argument registers */
1010         stack_size = 4 * sizeof (mgreg_t);
1011 #endif
1012
1013         /* return value */
1014         {
1015                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1016                 switch (ret_type->type) {
1017                 case MONO_TYPE_BOOLEAN:
1018                 case MONO_TYPE_I1:
1019                 case MONO_TYPE_U1:
1020                 case MONO_TYPE_I2:
1021                 case MONO_TYPE_U2:
1022                 case MONO_TYPE_CHAR:
1023                 case MONO_TYPE_I4:
1024                 case MONO_TYPE_U4:
1025                 case MONO_TYPE_I:
1026                 case MONO_TYPE_U:
1027                 case MONO_TYPE_PTR:
1028                 case MONO_TYPE_FNPTR:
1029                 case MONO_TYPE_CLASS:
1030                 case MONO_TYPE_OBJECT:
1031                 case MONO_TYPE_SZARRAY:
1032                 case MONO_TYPE_ARRAY:
1033                 case MONO_TYPE_STRING:
1034                         cinfo->ret.storage = ArgInIReg;
1035                         cinfo->ret.reg = AMD64_RAX;
1036                         break;
1037                 case MONO_TYPE_U8:
1038                 case MONO_TYPE_I8:
1039                         cinfo->ret.storage = ArgInIReg;
1040                         cinfo->ret.reg = AMD64_RAX;
1041                         break;
1042                 case MONO_TYPE_R4:
1043                         cinfo->ret.storage = ArgInFloatSSEReg;
1044                         cinfo->ret.reg = AMD64_XMM0;
1045                         break;
1046                 case MONO_TYPE_R8:
1047                         cinfo->ret.storage = ArgInDoubleSSEReg;
1048                         cinfo->ret.reg = AMD64_XMM0;
1049                         break;
1050                 case MONO_TYPE_GENERICINST:
1051                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1052                                 cinfo->ret.storage = ArgInIReg;
1053                                 cinfo->ret.reg = AMD64_RAX;
1054                                 break;
1055                         }
1056                         /* fall through */
1057 #if defined( __native_client_codegen__ )
1058                 case MONO_TYPE_TYPEDBYREF:
1059 #endif
1060                 case MONO_TYPE_VALUETYPE: {
1061                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062
1063                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1064                         if (cinfo->ret.storage == ArgOnStack) {
1065                                 cinfo->vtype_retaddr = TRUE;
1066                                 /* The caller passes the address where the value is stored */
1067                         }
1068                         break;
1069                 }
1070 #if !defined( __native_client_codegen__ )
1071                 case MONO_TYPE_TYPEDBYREF:
1072                         /* Same as a valuetype with size 24 */
1073                         cinfo->vtype_retaddr = TRUE;
1074                         break;
1075 #endif
1076                 case MONO_TYPE_VOID:
1077                         break;
1078                 default:
1079                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1080                 }
1081         }
1082
1083         pstart = 0;
1084         /*
1085          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1086          * the first argument, allowing 'this' to be always passed in the first arg reg.
1087          * Also do this if the first argument is a reference type, since virtual calls
1088          * are sometimes made using calli without sig->hasthis set, like in the delegate
1089          * invoke wrappers.
1090          */
1091         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1092                 if (sig->hasthis) {
1093                         add_general (&gr, &stack_size, cinfo->args + 0);
1094                 } else {
1095                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1096                         pstart = 1;
1097                 }
1098                 add_general (&gr, &stack_size, &cinfo->ret);
1099                 cinfo->vret_arg_index = 1;
1100         } else {
1101                 /* this */
1102                 if (sig->hasthis)
1103                         add_general (&gr, &stack_size, cinfo->args + 0);
1104
1105                 if (cinfo->vtype_retaddr)
1106                         add_general (&gr, &stack_size, &cinfo->ret);
1107         }
1108
1109         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1110                 gr = PARAM_REGS;
1111                 fr = FLOAT_PARAM_REGS;
1112
1113                 /* Emit the signature cookie just before the implicit arguments */
1114                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1115         }
1116
1117         for (i = pstart; i < sig->param_count; ++i) {
1118                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1119                 MonoType *ptype;
1120
1121 #ifdef HOST_WIN32
1122                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1123                 if (gr > fr)
1124                         fr = gr;
1125                 else if (fr > gr)
1126                         gr = fr;
1127 #endif
1128
1129                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1130                         /* We allways pass the sig cookie on the stack for simplicity */
1131                         /*
1132                          * Prevent implicit arguments + the sig cookie from being passed
1133                          * in registers.
1134                          */
1135                         gr = PARAM_REGS;
1136                         fr = FLOAT_PARAM_REGS;
1137
1138                         /* Emit the signature cookie just before the implicit arguments */
1139                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1140                 }
1141
1142                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1143                 switch (ptype->type) {
1144                 case MONO_TYPE_BOOLEAN:
1145                 case MONO_TYPE_I1:
1146                 case MONO_TYPE_U1:
1147                         add_general (&gr, &stack_size, ainfo);
1148                         break;
1149                 case MONO_TYPE_I2:
1150                 case MONO_TYPE_U2:
1151                 case MONO_TYPE_CHAR:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I4:
1155                 case MONO_TYPE_U4:
1156                         add_general (&gr, &stack_size, ainfo);
1157                         break;
1158                 case MONO_TYPE_I:
1159                 case MONO_TYPE_U:
1160                 case MONO_TYPE_PTR:
1161                 case MONO_TYPE_FNPTR:
1162                 case MONO_TYPE_CLASS:
1163                 case MONO_TYPE_OBJECT:
1164                 case MONO_TYPE_STRING:
1165                 case MONO_TYPE_SZARRAY:
1166                 case MONO_TYPE_ARRAY:
1167                         add_general (&gr, &stack_size, ainfo);
1168                         break;
1169                 case MONO_TYPE_GENERICINST:
1170                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1171                                 add_general (&gr, &stack_size, ainfo);
1172                                 break;
1173                         }
1174                         /* fall through */
1175                 case MONO_TYPE_VALUETYPE:
1176                 case MONO_TYPE_TYPEDBYREF:
1177                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178                         break;
1179                 case MONO_TYPE_U8:
1180
1181                 case MONO_TYPE_I8:
1182                         add_general (&gr, &stack_size, ainfo);
1183                         break;
1184                 case MONO_TYPE_R4:
1185                         add_float (&fr, &stack_size, ainfo, FALSE);
1186                         break;
1187                 case MONO_TYPE_R8:
1188                         add_float (&fr, &stack_size, ainfo, TRUE);
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1196                 gr = PARAM_REGS;
1197                 fr = FLOAT_PARAM_REGS;
1198
1199                 /* Emit the signature cookie just before the implicit arguments */
1200                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1201         }
1202
1203         cinfo->stack_usage = stack_size;
1204         cinfo->reg_usage = gr;
1205         cinfo->freg_usage = fr;
1206         return cinfo;
1207 }
1208
1209 /*
1210  * mono_arch_get_argument_info:
1211  * @csig:  a method signature
1212  * @param_count: the number of parameters to consider
1213  * @arg_info: an array to store the result infos
1214  *
1215  * Gathers information on parameters such as size, alignment and
1216  * padding. arg_info should be large enought to hold param_count + 1 entries.
1217  *
1218  * Returns the size of the argument area on the stack.
1219  */
1220 int
1221 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1222 {
1223         int k;
1224         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1225         guint32 args_size = cinfo->stack_usage;
1226
1227         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1228         if (csig->hasthis) {
1229                 arg_info [0].offset = 0;
1230         }
1231
1232         for (k = 0; k < param_count; k++) {
1233                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1234                 /* FIXME: */
1235                 arg_info [k + 1].size = 0;
1236         }
1237
1238         g_free (cinfo);
1239
1240         return args_size;
1241 }
1242
1243 gboolean
1244 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1245 {
1246         CallInfo *c1, *c2;
1247         gboolean res;
1248         MonoType *callee_ret;
1249
1250         c1 = get_call_info (NULL, NULL, caller_sig);
1251         c2 = get_call_info (NULL, NULL, callee_sig);
1252         res = c1->stack_usage >= c2->stack_usage;
1253         callee_ret = mini_replace_type (callee_sig->ret);
1254         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1255                 /* An address on the callee's stack is passed as the first argument */
1256                 res = FALSE;
1257
1258         g_free (c1);
1259         g_free (c2);
1260
1261         return res;
1262 }
1263
1264 /*
1265  * Initialize the cpu to execute managed code.
1266  */
1267 void
1268 mono_arch_cpu_init (void)
1269 {
1270 #ifndef _MSC_VER
1271         guint16 fpcw;
1272
1273         /* spec compliance requires running with double precision */
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275         fpcw &= ~X86_FPCW_PRECC_MASK;
1276         fpcw |= X86_FPCW_PREC_DOUBLE;
1277         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1278         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 #else
1280         /* TODO: This is crashing on Win64 right now.
1281         * _control87 (_PC_53, MCW_PC);
1282         */
1283 #endif
1284 }
1285
1286 /*
1287  * Initialize architecture specific code.
1288  */
1289 void
1290 mono_arch_init (void)
1291 {
1292         int flags;
1293
1294         mono_mutex_init_recursive (&mini_arch_mutex);
1295 #if defined(__native_client_codegen__)
1296         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1297         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1298         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1299         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1300 #endif
1301
1302 #ifdef MONO_ARCH_NOMAP32BIT
1303         flags = MONO_MMAP_READ;
1304         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1305         breakpoint_size = 13;
1306         breakpoint_fault_size = 3;
1307 #else
1308         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1309         /* amd64_mov_reg_mem () */
1310         breakpoint_size = 8;
1311         breakpoint_fault_size = 8;
1312 #endif
1313
1314         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1315         single_step_fault_size = 4;
1316
1317         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1318         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1319         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1320
1321         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1322         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1323         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1324 }
1325
1326 /*
1327  * Cleanup architecture specific code.
1328  */
1329 void
1330 mono_arch_cleanup (void)
1331 {
1332         mono_mutex_destroy (&mini_arch_mutex);
1333 #if defined(__native_client_codegen__)
1334         mono_native_tls_free (nacl_instruction_depth);
1335         mono_native_tls_free (nacl_rex_tag);
1336         mono_native_tls_free (nacl_legacy_prefix_tag);
1337 #endif
1338 }
1339
1340 /*
1341  * This function returns the optimizations supported on this cpu.
1342  */
1343 guint32
1344 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1345 {
1346         guint32 opts = 0;
1347
1348         *exclude_mask = 0;
1349
1350         if (mono_hwcap_x86_has_cmov) {
1351                 opts |= MONO_OPT_CMOV;
1352
1353                 if (mono_hwcap_x86_has_fcmov)
1354                         opts |= MONO_OPT_FCMOV;
1355                 else
1356                         *exclude_mask |= MONO_OPT_FCMOV;
1357         } else {
1358                 *exclude_mask |= MONO_OPT_CMOV;
1359         }
1360
1361         return opts;
1362 }
1363
1364 /*
1365  * This function test for all SSE functions supported.
1366  *
1367  * Returns a bitmask corresponding to all supported versions.
1368  *
1369  */
1370 guint32
1371 mono_arch_cpu_enumerate_simd_versions (void)
1372 {
1373         guint32 sse_opts = 0;
1374
1375         if (mono_hwcap_x86_has_sse1)
1376                 sse_opts |= SIMD_VERSION_SSE1;
1377
1378         if (mono_hwcap_x86_has_sse2)
1379                 sse_opts |= SIMD_VERSION_SSE2;
1380
1381         if (mono_hwcap_x86_has_sse3)
1382                 sse_opts |= SIMD_VERSION_SSE3;
1383
1384         if (mono_hwcap_x86_has_ssse3)
1385                 sse_opts |= SIMD_VERSION_SSSE3;
1386
1387         if (mono_hwcap_x86_has_sse41)
1388                 sse_opts |= SIMD_VERSION_SSE41;
1389
1390         if (mono_hwcap_x86_has_sse42)
1391                 sse_opts |= SIMD_VERSION_SSE42;
1392
1393         if (mono_hwcap_x86_has_sse4a)
1394                 sse_opts |= SIMD_VERSION_SSE4a;
1395
1396         return sse_opts;
1397 }
1398
1399 #ifndef DISABLE_JIT
1400
1401 GList *
1402 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1403 {
1404         GList *vars = NULL;
1405         int i;
1406
1407         for (i = 0; i < cfg->num_varinfo; i++) {
1408                 MonoInst *ins = cfg->varinfo [i];
1409                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1410
1411                 /* unused vars */
1412                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1413                         continue;
1414
1415                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1416                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1417                         continue;
1418
1419                 if (mono_is_regsize_var (ins->inst_vtype)) {
1420                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1421                         g_assert (i == vmv->idx);
1422                         vars = g_list_prepend (vars, vmv);
1423                 }
1424         }
1425
1426         vars = mono_varlist_sort (cfg, vars, 0);
1427
1428         return vars;
1429 }
1430
1431 /**
1432  * mono_arch_compute_omit_fp:
1433  *
1434  *   Determine whenever the frame pointer can be eliminated.
1435  */
1436 static void
1437 mono_arch_compute_omit_fp (MonoCompile *cfg)
1438 {
1439         MonoMethodSignature *sig;
1440         MonoMethodHeader *header;
1441         int i, locals_size;
1442         CallInfo *cinfo;
1443
1444         if (cfg->arch.omit_fp_computed)
1445                 return;
1446
1447         header = cfg->header;
1448
1449         sig = mono_method_signature (cfg->method);
1450
1451         if (!cfg->arch.cinfo)
1452                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1453         cinfo = cfg->arch.cinfo;
1454
1455         /*
1456          * FIXME: Remove some of the restrictions.
1457          */
1458         cfg->arch.omit_fp = TRUE;
1459         cfg->arch.omit_fp_computed = TRUE;
1460
1461 #ifdef __native_client_codegen__
1462         /* NaCl modules may not change the value of RBP, so it cannot be */
1463         /* used as a normal register, but it can be used as a frame pointer*/
1464         cfg->disable_omit_fp = TRUE;
1465         cfg->arch.omit_fp = FALSE;
1466 #endif
1467
1468         if (cfg->disable_omit_fp)
1469                 cfg->arch.omit_fp = FALSE;
1470
1471         if (!debug_omit_fp ())
1472                 cfg->arch.omit_fp = FALSE;
1473         /*
1474         if (cfg->method->save_lmf)
1475                 cfg->arch.omit_fp = FALSE;
1476         */
1477         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (header->num_clauses)
1480                 cfg->arch.omit_fp = FALSE;
1481         if (cfg->param_area)
1482                 cfg->arch.omit_fp = FALSE;
1483         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1484                 cfg->arch.omit_fp = FALSE;
1485         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1486                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1487                 cfg->arch.omit_fp = FALSE;
1488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489                 ArgInfo *ainfo = &cinfo->args [i];
1490
1491                 if (ainfo->storage == ArgOnStack) {
1492                         /*
1493                          * The stack offset can only be determined when the frame
1494                          * size is known.
1495                          */
1496                         cfg->arch.omit_fp = FALSE;
1497                 }
1498         }
1499
1500         locals_size = 0;
1501         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1502                 MonoInst *ins = cfg->varinfo [i];
1503                 int ialign;
1504
1505                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1506         }
1507 }
1508
1509 GList *
1510 mono_arch_get_global_int_regs (MonoCompile *cfg)
1511 {
1512         GList *regs = NULL;
1513
1514         mono_arch_compute_omit_fp (cfg);
1515
1516         if (cfg->globalra) {
1517                 if (cfg->arch.omit_fp)
1518                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1519
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1524 #ifndef __native_client_codegen__
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1526 #endif
1527
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1531                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1532                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1534                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1536         } else {
1537                 if (cfg->arch.omit_fp)
1538                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1539
1540                 /* We use the callee saved registers for global allocation */
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1543                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1545 #ifndef __native_client_codegen__
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1547 #endif
1548 #ifdef HOST_WIN32
1549                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1551 #endif
1552         }
1553
1554         return regs;
1555 }
1556
1557 GList*
1558 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1559 {
1560         GList *regs = NULL;
1561         int i;
1562
1563         /* All XMM registers */
1564         for (i = 0; i < 16; ++i)
1565                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1566
1567         return regs;
1568 }
1569
1570 GList*
1571 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1572 {
1573         static GList *r = NULL;
1574
1575         if (r == NULL) {
1576                 GList *regs = NULL;
1577
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1583 #ifndef __native_client_codegen__
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1585 #endif
1586
1587                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1588                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1589                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1590                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1591                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1592                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1593                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1594                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1595
1596                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1597         }
1598
1599         return r;
1600 }
1601
1602 GList*
1603 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1604 {
1605         int i;
1606         static GList *r = NULL;
1607
1608         if (r == NULL) {
1609                 GList *regs = NULL;
1610
1611                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1612                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1613
1614                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1615         }
1616
1617         return r;
1618 }
1619
1620 /*
1621  * mono_arch_regalloc_cost:
1622  *
1623  *  Return the cost, in number of memory references, of the action of
1624  * allocating the variable VMV into a register during global register
1625  * allocation.
1626  */
1627 guint32
1628 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1629 {
1630         MonoInst *ins = cfg->varinfo [vmv->idx];
1631
1632         if (cfg->method->save_lmf)
1633                 /* The register is already saved */
1634                 /* substract 1 for the invisible store in the prolog */
1635                 return (ins->opcode == OP_ARG) ? 0 : 1;
1636         else
1637                 /* push+pop */
1638                 return (ins->opcode == OP_ARG) ? 1 : 2;
1639 }
1640
1641 /*
1642  * mono_arch_fill_argument_info:
1643  *
1644  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1645  * of the method.
1646  */
1647 void
1648 mono_arch_fill_argument_info (MonoCompile *cfg)
1649 {
1650         MonoType *sig_ret;
1651         MonoMethodSignature *sig;
1652         MonoMethodHeader *header;
1653         MonoInst *ins;
1654         int i;
1655         CallInfo *cinfo;
1656
1657         header = cfg->header;
1658
1659         sig = mono_method_signature (cfg->method);
1660
1661         cinfo = cfg->arch.cinfo;
1662         sig_ret = mini_replace_type (sig->ret);
1663
1664         /*
1665          * Contrary to mono_arch_allocate_vars (), the information should describe
1666          * where the arguments are at the beginning of the method, not where they can be
1667          * accessed during the execution of the method. The later makes no sense for the
1668          * global register allocator, since a variable can be in more than one location.
1669          */
1670         if (sig_ret->type != MONO_TYPE_VOID) {
1671                 switch (cinfo->ret.storage) {
1672                 case ArgInIReg:
1673                 case ArgInFloatSSEReg:
1674                 case ArgInDoubleSSEReg:
1675                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1676                                 cfg->vret_addr->opcode = OP_REGVAR;
1677                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1678                         }
1679                         else {
1680                                 cfg->ret->opcode = OP_REGVAR;
1681                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1682                         }
1683                         break;
1684                 case ArgValuetypeInReg:
1685                         cfg->ret->opcode = OP_REGOFFSET;
1686                         cfg->ret->inst_basereg = -1;
1687                         cfg->ret->inst_offset = -1;
1688                         break;
1689                 default:
1690                         g_assert_not_reached ();
1691                 }
1692         }
1693
1694         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1695                 ArgInfo *ainfo = &cinfo->args [i];
1696                 MonoType *arg_type;
1697
1698                 ins = cfg->args [i];
1699
1700                 if (sig->hasthis && (i == 0))
1701                         arg_type = &mono_defaults.object_class->byval_arg;
1702                 else
1703                         arg_type = sig->params [i - sig->hasthis];
1704
1705                 switch (ainfo->storage) {
1706                 case ArgInIReg:
1707                 case ArgInFloatSSEReg:
1708                 case ArgInDoubleSSEReg:
1709                         ins->opcode = OP_REGVAR;
1710                         ins->inst_c0 = ainfo->reg;
1711                         break;
1712                 case ArgOnStack:
1713                         ins->opcode = OP_REGOFFSET;
1714                         ins->inst_basereg = -1;
1715                         ins->inst_offset = -1;
1716                         break;
1717                 case ArgValuetypeInReg:
1718                         /* Dummy */
1719                         ins->opcode = OP_NOP;
1720                         break;
1721                 default:
1722                         g_assert_not_reached ();
1723                 }
1724         }
1725 }
1726
1727 void
1728 mono_arch_allocate_vars (MonoCompile *cfg)
1729 {
1730         MonoType *sig_ret;
1731         MonoMethodSignature *sig;
1732         MonoMethodHeader *header;
1733         MonoInst *ins;
1734         int i, offset;
1735         guint32 locals_stack_size, locals_stack_align;
1736         gint32 *offsets;
1737         CallInfo *cinfo;
1738
1739         header = cfg->header;
1740
1741         sig = mono_method_signature (cfg->method);
1742
1743         cinfo = cfg->arch.cinfo;
1744         sig_ret = mini_replace_type (sig->ret);
1745
1746         mono_arch_compute_omit_fp (cfg);
1747
1748         /*
1749          * We use the ABI calling conventions for managed code as well.
1750          * Exception: valuetypes are only sometimes passed or returned in registers.
1751          */
1752
1753         /*
1754          * The stack looks like this:
1755          * <incoming arguments passed on the stack>
1756          * <return value>
1757          * <lmf/caller saved registers>
1758          * <locals>
1759          * <spill area>
1760          * <localloc area>  -> grows dynamically
1761          * <params area>
1762          */
1763
1764         if (cfg->arch.omit_fp) {
1765                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1766                 cfg->frame_reg = AMD64_RSP;
1767                 offset = 0;
1768         } else {
1769                 /* Locals are allocated backwards from %fp */
1770                 cfg->frame_reg = AMD64_RBP;
1771                 offset = 0;
1772         }
1773
1774         cfg->arch.saved_iregs = cfg->used_int_regs;
1775         if (cfg->method->save_lmf)
1776                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1777                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1778
1779         if (cfg->arch.omit_fp)
1780                 cfg->arch.reg_save_area_offset = offset;
1781         /* Reserve space for callee saved registers */
1782         for (i = 0; i < AMD64_NREG; ++i)
1783                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1784                         offset += sizeof(mgreg_t);
1785                 }
1786         if (!cfg->arch.omit_fp)
1787                 cfg->arch.reg_save_area_offset = -offset;
1788
1789         if (sig_ret->type != MONO_TYPE_VOID) {
1790                 switch (cinfo->ret.storage) {
1791                 case ArgInIReg:
1792                 case ArgInFloatSSEReg:
1793                 case ArgInDoubleSSEReg:
1794                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1795                                 if (cfg->globalra) {
1796                                         cfg->vret_addr->opcode = OP_REGVAR;
1797                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1798                                 } else {
1799                                         /* The register is volatile */
1800                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1801                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1802                                         if (cfg->arch.omit_fp) {
1803                                                 cfg->vret_addr->inst_offset = offset;
1804                                                 offset += 8;
1805                                         } else {
1806                                                 offset += 8;
1807                                                 cfg->vret_addr->inst_offset = -offset;
1808                                         }
1809                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1810                                                 printf ("vret_addr =");
1811                                                 mono_print_ins (cfg->vret_addr);
1812                                         }
1813                                 }
1814                         }
1815                         else {
1816                                 cfg->ret->opcode = OP_REGVAR;
1817                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1818                         }
1819                         break;
1820                 case ArgValuetypeInReg:
1821                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1822                         cfg->ret->opcode = OP_REGOFFSET;
1823                         cfg->ret->inst_basereg = cfg->frame_reg;
1824                         if (cfg->arch.omit_fp) {
1825                                 cfg->ret->inst_offset = offset;
1826                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1827                         } else {
1828                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1829                                 cfg->ret->inst_offset = - offset;
1830                         }
1831                         break;
1832                 default:
1833                         g_assert_not_reached ();
1834                 }
1835                 if (!cfg->globalra)
1836                         cfg->ret->dreg = cfg->ret->inst_c0;
1837         }
1838
1839         /* Allocate locals */
1840         if (!cfg->globalra) {
1841                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1842                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1843                         char *mname = mono_method_full_name (cfg->method, TRUE);
1844                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1845                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1846                         g_free (mname);
1847                         return;
1848                 }
1849
1850                 if (locals_stack_align) {
1851                         offset += (locals_stack_align - 1);
1852                         offset &= ~(locals_stack_align - 1);
1853                 }
1854                 if (cfg->arch.omit_fp) {
1855                         cfg->locals_min_stack_offset = offset;
1856                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1857                 } else {
1858                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1859                         cfg->locals_max_stack_offset = - offset;
1860                 }
1861
1862                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1863                         if (offsets [i] != -1) {
1864                                 MonoInst *ins = cfg->varinfo [i];
1865                                 ins->opcode = OP_REGOFFSET;
1866                                 ins->inst_basereg = cfg->frame_reg;
1867                                 if (cfg->arch.omit_fp)
1868                                         ins->inst_offset = (offset + offsets [i]);
1869                                 else
1870                                         ins->inst_offset = - (offset + offsets [i]);
1871                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1872                         }
1873                 }
1874                 offset += locals_stack_size;
1875         }
1876
1877         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1878                 g_assert (!cfg->arch.omit_fp);
1879                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1880                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1881         }
1882
1883         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1884                 ins = cfg->args [i];
1885                 if (ins->opcode != OP_REGVAR) {
1886                         ArgInfo *ainfo = &cinfo->args [i];
1887                         gboolean inreg = TRUE;
1888                         MonoType *arg_type;
1889
1890                         if (sig->hasthis && (i == 0))
1891                                 arg_type = &mono_defaults.object_class->byval_arg;
1892                         else
1893                                 arg_type = sig->params [i - sig->hasthis];
1894
1895                         if (cfg->globalra) {
1896                                 /* The new allocator needs info about the original locations of the arguments */
1897                                 switch (ainfo->storage) {
1898                                 case ArgInIReg:
1899                                 case ArgInFloatSSEReg:
1900                                 case ArgInDoubleSSEReg:
1901                                         ins->opcode = OP_REGVAR;
1902                                         ins->inst_c0 = ainfo->reg;
1903                                         break;
1904                                 case ArgOnStack:
1905                                         g_assert (!cfg->arch.omit_fp);
1906                                         ins->opcode = OP_REGOFFSET;
1907                                         ins->inst_basereg = cfg->frame_reg;
1908                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1909                                         break;
1910                                 case ArgValuetypeInReg:
1911                                         ins->opcode = OP_REGOFFSET;
1912                                         ins->inst_basereg = cfg->frame_reg;
1913                                         /* These arguments are saved to the stack in the prolog */
1914                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1915                                         if (cfg->arch.omit_fp) {
1916                                                 ins->inst_offset = offset;
1917                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1918                                         } else {
1919                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1920                                                 ins->inst_offset = - offset;
1921                                         }
1922                                         break;
1923                                 default:
1924                                         g_assert_not_reached ();
1925                                 }
1926
1927                                 continue;
1928                         }
1929
1930                         /* FIXME: Allocate volatile arguments to registers */
1931                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1932                                 inreg = FALSE;
1933
1934                         /*
1935                          * Under AMD64, all registers used to pass arguments to functions
1936                          * are volatile across calls.
1937                          * FIXME: Optimize this.
1938                          */
1939                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1940                                 inreg = FALSE;
1941
1942                         ins->opcode = OP_REGOFFSET;
1943
1944                         switch (ainfo->storage) {
1945                         case ArgInIReg:
1946                         case ArgInFloatSSEReg:
1947                         case ArgInDoubleSSEReg:
1948                                 if (inreg) {
1949                                         ins->opcode = OP_REGVAR;
1950                                         ins->dreg = ainfo->reg;
1951                                 }
1952                                 break;
1953                         case ArgOnStack:
1954                                 g_assert (!cfg->arch.omit_fp);
1955                                 ins->opcode = OP_REGOFFSET;
1956                                 ins->inst_basereg = cfg->frame_reg;
1957                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1958                                 break;
1959                         case ArgValuetypeInReg:
1960                                 break;
1961                         case ArgValuetypeAddrInIReg: {
1962                                 MonoInst *indir;
1963                                 g_assert (!cfg->arch.omit_fp);
1964
1965                                 MONO_INST_NEW (cfg, indir, 0);
1966                                 indir->opcode = OP_REGOFFSET;
1967                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1968                                         indir->inst_basereg = cfg->frame_reg;
1969                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1970                                         offset += (sizeof (gpointer));
1971                                         indir->inst_offset = - offset;
1972                                 }
1973                                 else {
1974                                         indir->inst_basereg = cfg->frame_reg;
1975                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1976                                 }
1977
1978                                 ins->opcode = OP_VTARG_ADDR;
1979                                 ins->inst_left = indir;
1980
1981                                 break;
1982                         }
1983                         default:
1984                                 NOT_IMPLEMENTED;
1985                         }
1986
1987                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1988                                 ins->opcode = OP_REGOFFSET;
1989                                 ins->inst_basereg = cfg->frame_reg;
1990                                 /* These arguments are saved to the stack in the prolog */
1991                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1992                                 if (cfg->arch.omit_fp) {
1993                                         ins->inst_offset = offset;
1994                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1995                                         // Arguments are yet supported by the stack map creation code
1996                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1997                                 } else {
1998                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1999                                         ins->inst_offset = - offset;
2000                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2001                                 }
2002                         }
2003                 }
2004         }
2005
2006         cfg->stack_offset = offset;
2007 }
2008
2009 void
2010 mono_arch_create_vars (MonoCompile *cfg)
2011 {
2012         MonoMethodSignature *sig;
2013         CallInfo *cinfo;
2014         MonoType *sig_ret;
2015
2016         sig = mono_method_signature (cfg->method);
2017
2018         if (!cfg->arch.cinfo)
2019                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2020         cinfo = cfg->arch.cinfo;
2021
2022         if (cinfo->ret.storage == ArgValuetypeInReg)
2023                 cfg->ret_var_is_local = TRUE;
2024
2025         sig_ret = mini_replace_type (sig->ret);
2026         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2027                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2028                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2029                         printf ("vret_addr = ");
2030                         mono_print_ins (cfg->vret_addr);
2031                 }
2032         }
2033
2034         if (cfg->gen_seq_points_debug_data) {
2035                 MonoInst *ins;
2036
2037                 if (cfg->compile_aot) {
2038                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2039                         ins->flags |= MONO_INST_VOLATILE;
2040                         cfg->arch.seq_point_info_var = ins;
2041                 }
2042
2043             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2044                 ins->flags |= MONO_INST_VOLATILE;
2045                 cfg->arch.ss_trigger_page_var = ins;
2046         }
2047
2048         if (cfg->method->save_lmf)
2049                 cfg->create_lmf_var = TRUE;
2050
2051         if (cfg->method->save_lmf) {
2052                 cfg->lmf_ir = TRUE;
2053 #if !defined(HOST_WIN32)
2054                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2055                         cfg->lmf_ir_mono_lmf = TRUE;
2056 #endif
2057         }
2058 }
2059
2060 static void
2061 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2062 {
2063         MonoInst *ins;
2064
2065         switch (storage) {
2066         case ArgInIReg:
2067                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2068                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2069                 ins->sreg1 = tree->dreg;
2070                 MONO_ADD_INS (cfg->cbb, ins);
2071                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2072                 break;
2073         case ArgInFloatSSEReg:
2074                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2075                 ins->dreg = mono_alloc_freg (cfg);
2076                 ins->sreg1 = tree->dreg;
2077                 MONO_ADD_INS (cfg->cbb, ins);
2078
2079                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2080                 break;
2081         case ArgInDoubleSSEReg:
2082                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2083                 ins->dreg = mono_alloc_freg (cfg);
2084                 ins->sreg1 = tree->dreg;
2085                 MONO_ADD_INS (cfg->cbb, ins);
2086
2087                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2088
2089                 break;
2090         default:
2091                 g_assert_not_reached ();
2092         }
2093 }
2094
2095 static int
2096 arg_storage_to_load_membase (ArgStorage storage)
2097 {
2098         switch (storage) {
2099         case ArgInIReg:
2100 #if defined(__mono_ilp32__)
2101                 return OP_LOADI8_MEMBASE;
2102 #else
2103                 return OP_LOAD_MEMBASE;
2104 #endif
2105         case ArgInDoubleSSEReg:
2106                 return OP_LOADR8_MEMBASE;
2107         case ArgInFloatSSEReg:
2108                 return OP_LOADR4_MEMBASE;
2109         default:
2110                 g_assert_not_reached ();
2111         }
2112
2113         return -1;
2114 }
2115
2116 static void
2117 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2118 {
2119         MonoMethodSignature *tmp_sig;
2120         int sig_reg;
2121
2122         if (call->tail_call)
2123                 NOT_IMPLEMENTED;
2124
2125         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2126
2127         /*
2128          * mono_ArgIterator_Setup assumes the signature cookie is
2129          * passed first and all the arguments which were before it are
2130          * passed on the stack after the signature. So compensate by
2131          * passing a different signature.
2132          */
2133         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2134         tmp_sig->param_count -= call->signature->sentinelpos;
2135         tmp_sig->sentinelpos = 0;
2136         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2137
2138         sig_reg = mono_alloc_ireg (cfg);
2139         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2140
2141         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2142 }
2143
2144 static inline LLVMArgStorage
2145 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2146 {
2147         switch (storage) {
2148         case ArgInIReg:
2149                 return LLVMArgInIReg;
2150         case ArgNone:
2151                 return LLVMArgNone;
2152         default:
2153                 g_assert_not_reached ();
2154                 return LLVMArgNone;
2155         }
2156 }
2157
2158 #ifdef ENABLE_LLVM
2159 LLVMCallInfo*
2160 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2161 {
2162         int i, n;
2163         CallInfo *cinfo;
2164         ArgInfo *ainfo;
2165         int j;
2166         LLVMCallInfo *linfo;
2167         MonoType *t, *sig_ret;
2168
2169         n = sig->param_count + sig->hasthis;
2170         sig_ret = mini_replace_type (sig->ret);
2171
2172         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2173
2174         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2175
2176         /*
2177          * LLVM always uses the native ABI while we use our own ABI, the
2178          * only difference is the handling of vtypes:
2179          * - we only pass/receive them in registers in some cases, and only
2180          *   in 1 or 2 integer registers.
2181          */
2182         if (cinfo->ret.storage == ArgValuetypeInReg) {
2183                 if (sig->pinvoke) {
2184                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2185                         cfg->disable_llvm = TRUE;
2186                         return linfo;
2187                 }
2188
2189                 linfo->ret.storage = LLVMArgVtypeInReg;
2190                 for (j = 0; j < 2; ++j)
2191                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2192         }
2193
2194         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2195                 /* Vtype returned using a hidden argument */
2196                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2197                 linfo->vret_arg_index = cinfo->vret_arg_index;
2198         }
2199
2200         for (i = 0; i < n; ++i) {
2201                 ainfo = cinfo->args + i;
2202
2203                 if (i >= sig->hasthis)
2204                         t = sig->params [i - sig->hasthis];
2205                 else
2206                         t = &mono_defaults.int_class->byval_arg;
2207
2208                 linfo->args [i].storage = LLVMArgNone;
2209
2210                 switch (ainfo->storage) {
2211                 case ArgInIReg:
2212                         linfo->args [i].storage = LLVMArgInIReg;
2213                         break;
2214                 case ArgInDoubleSSEReg:
2215                 case ArgInFloatSSEReg:
2216                         linfo->args [i].storage = LLVMArgInFPReg;
2217                         break;
2218                 case ArgOnStack:
2219                         if (MONO_TYPE_ISSTRUCT (t)) {
2220                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2221                         } else {
2222                                 linfo->args [i].storage = LLVMArgInIReg;
2223                                 if (!t->byref) {
2224                                         if (t->type == MONO_TYPE_R4)
2225                                                 linfo->args [i].storage = LLVMArgInFPReg;
2226                                         else if (t->type == MONO_TYPE_R8)
2227                                                 linfo->args [i].storage = LLVMArgInFPReg;
2228                                 }
2229                         }
2230                         break;
2231                 case ArgValuetypeInReg:
2232                         if (sig->pinvoke) {
2233                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2234                                 cfg->disable_llvm = TRUE;
2235                                 return linfo;
2236                         }
2237
2238                         linfo->args [i].storage = LLVMArgVtypeInReg;
2239                         for (j = 0; j < 2; ++j)
2240                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2241                         break;
2242                 default:
2243                         cfg->exception_message = g_strdup ("ainfo->storage");
2244                         cfg->disable_llvm = TRUE;
2245                         break;
2246                 }
2247         }
2248
2249         return linfo;
2250 }
2251 #endif
2252
2253 void
2254 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2255 {
2256         MonoInst *arg, *in;
2257         MonoMethodSignature *sig;
2258         MonoType *sig_ret;
2259         int i, n, stack_size;
2260         CallInfo *cinfo;
2261         ArgInfo *ainfo;
2262
2263         stack_size = 0;
2264
2265         sig = call->signature;
2266         n = sig->param_count + sig->hasthis;
2267
2268         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2269
2270         sig_ret = sig->ret;
2271
2272         if (COMPILE_LLVM (cfg)) {
2273                 /* We shouldn't be called in the llvm case */
2274                 cfg->disable_llvm = TRUE;
2275                 return;
2276         }
2277
2278         /*
2279          * Emit all arguments which are passed on the stack to prevent register
2280          * allocation problems.
2281          */
2282         for (i = 0; i < n; ++i) {
2283                 MonoType *t;
2284                 ainfo = cinfo->args + i;
2285
2286                 in = call->args [i];
2287
2288                 if (sig->hasthis && i == 0)
2289                         t = &mono_defaults.object_class->byval_arg;
2290                 else
2291                         t = sig->params [i - sig->hasthis];
2292
2293                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2294                         if (!t->byref) {
2295                                 if (t->type == MONO_TYPE_R4)
2296                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2297                                 else if (t->type == MONO_TYPE_R8)
2298                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2299                                 else
2300                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2301                         } else {
2302                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2303                         }
2304                         if (cfg->compute_gc_maps) {
2305                                 MonoInst *def;
2306
2307                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2308                         }
2309                 }
2310         }
2311
2312         /*
2313          * Emit all parameters passed in registers in non-reverse order for better readability
2314          * and to help the optimization in emit_prolog ().
2315          */
2316         for (i = 0; i < n; ++i) {
2317                 ainfo = cinfo->args + i;
2318
2319                 in = call->args [i];
2320
2321                 if (ainfo->storage == ArgInIReg)
2322                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2323         }
2324
2325         for (i = n - 1; i >= 0; --i) {
2326                 ainfo = cinfo->args + i;
2327
2328                 in = call->args [i];
2329
2330                 switch (ainfo->storage) {
2331                 case ArgInIReg:
2332                         /* Already done */
2333                         break;
2334                 case ArgInFloatSSEReg:
2335                 case ArgInDoubleSSEReg:
2336                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2337                         break;
2338                 case ArgOnStack:
2339                 case ArgValuetypeInReg:
2340                 case ArgValuetypeAddrInIReg:
2341                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2342                                 MonoInst *call_inst = (MonoInst*)call;
2343                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2344                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2345                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2346                                 guint32 align;
2347                                 guint32 size;
2348
2349                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2350                                         size = sizeof (MonoTypedRef);
2351                                         align = sizeof (gpointer);
2352                                 }
2353                                 else {
2354                                         if (sig->pinvoke)
2355                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2356                                         else {
2357                                                 /*
2358                                                  * Other backends use mono_type_stack_size (), but that
2359                                                  * aligns the size to 8, which is larger than the size of
2360                                                  * the source, leading to reads of invalid memory if the
2361                                                  * source is at the end of address space.
2362                                                  */
2363                                                 size = mono_class_value_size (in->klass, &align);
2364                                         }
2365                                 }
2366                                 g_assert (in->klass);
2367
2368                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2369                                         /* Avoid asserts in emit_memcpy () */
2370                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2371                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2372                                         /* Continue normally */
2373                                 }
2374
2375                                 if (size > 0) {
2376                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2377                                         arg->sreg1 = in->dreg;
2378                                         arg->klass = in->klass;
2379                                         arg->backend.size = size;
2380                                         arg->inst_p0 = call;
2381                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2382                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2383
2384                                         MONO_ADD_INS (cfg->cbb, arg);
2385                                 }
2386                         }
2387                         break;
2388                 default:
2389                         g_assert_not_reached ();
2390                 }
2391
2392                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2393                         /* Emit the signature cookie just before the implicit arguments */
2394                         emit_sig_cookie (cfg, call, cinfo);
2395         }
2396
2397         /* Handle the case where there are no implicit arguments */
2398         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2399                 emit_sig_cookie (cfg, call, cinfo);
2400
2401         sig_ret = mini_replace_type (sig->ret);
2402         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2403                 MonoInst *vtarg;
2404
2405                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2406                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2407                                 /*
2408                                  * Tell the JIT to use a more efficient calling convention: call using
2409                                  * OP_CALL, compute the result location after the call, and save the
2410                                  * result there.
2411                                  */
2412                                 call->vret_in_reg = TRUE;
2413                                 /*
2414                                  * Nullify the instruction computing the vret addr to enable
2415                                  * future optimizations.
2416                                  */
2417                                 if (call->vret_var)
2418                                         NULLIFY_INS (call->vret_var);
2419                         } else {
2420                                 if (call->tail_call)
2421                                         NOT_IMPLEMENTED;
2422                                 /*
2423                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2424                                  * the stack. Push the address here, so the call instruction can
2425                                  * access it.
2426                                  */
2427                                 if (!cfg->arch.vret_addr_loc) {
2428                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2429                                         /* Prevent it from being register allocated or optimized away */
2430                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2431                                 }
2432
2433                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2434                         }
2435                 }
2436                 else {
2437                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2438                         vtarg->sreg1 = call->vret_var->dreg;
2439                         vtarg->dreg = mono_alloc_preg (cfg);
2440                         MONO_ADD_INS (cfg->cbb, vtarg);
2441
2442                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2443                 }
2444         }
2445
2446         if (cfg->method->save_lmf) {
2447                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2448                 MONO_ADD_INS (cfg->cbb, arg);
2449         }
2450
2451         call->stack_usage = cinfo->stack_usage;
2452 }
2453
2454 void
2455 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2456 {
2457         MonoInst *arg;
2458         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2459         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2460         int size = ins->backend.size;
2461
2462         if (ainfo->storage == ArgValuetypeInReg) {
2463                 MonoInst *load;
2464                 int part;
2465
2466                 for (part = 0; part < 2; ++part) {
2467                         if (ainfo->pair_storage [part] == ArgNone)
2468                                 continue;
2469
2470                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2471                         load->inst_basereg = src->dreg;
2472                         load->inst_offset = part * sizeof(mgreg_t);
2473
2474                         switch (ainfo->pair_storage [part]) {
2475                         case ArgInIReg:
2476                                 load->dreg = mono_alloc_ireg (cfg);
2477                                 break;
2478                         case ArgInDoubleSSEReg:
2479                         case ArgInFloatSSEReg:
2480                                 load->dreg = mono_alloc_freg (cfg);
2481                                 break;
2482                         default:
2483                                 g_assert_not_reached ();
2484                         }
2485                         MONO_ADD_INS (cfg->cbb, load);
2486
2487                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2488                 }
2489         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2490                 MonoInst *vtaddr, *load;
2491                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2492
2493                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2494                 cfg->has_indirection = TRUE;
2495                 load->inst_p0 = vtaddr;
2496                 vtaddr->flags |= MONO_INST_INDIRECT;
2497                 load->type = STACK_MP;
2498                 load->klass = vtaddr->klass;
2499                 load->dreg = mono_alloc_ireg (cfg);
2500                 MONO_ADD_INS (cfg->cbb, load);
2501                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2502
2503                 if (ainfo->pair_storage [0] == ArgInIReg) {
2504                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2505                         arg->dreg = mono_alloc_ireg (cfg);
2506                         arg->sreg1 = load->dreg;
2507                         arg->inst_imm = 0;
2508                         MONO_ADD_INS (cfg->cbb, arg);
2509                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2510                 } else {
2511                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2512                 }
2513         } else {
2514                 if (size == 8) {
2515                         int dreg = mono_alloc_ireg (cfg);
2516
2517                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2518                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2519                 } else if (size <= 40) {
2520                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2521                 } else {
2522                         // FIXME: Code growth
2523                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2524                 }
2525
2526                 if (cfg->compute_gc_maps) {
2527                         MonoInst *def;
2528                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2529                 }
2530         }
2531 }
2532
2533 void
2534 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2535 {
2536         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2537
2538         if (ret->type == MONO_TYPE_R4) {
2539                 if (COMPILE_LLVM (cfg))
2540                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2541                 else
2542                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2543                 return;
2544         } else if (ret->type == MONO_TYPE_R8) {
2545                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2546                 return;
2547         }
2548
2549         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2550 }
2551
2552 #endif /* DISABLE_JIT */
2553
2554 #define EMIT_COND_BRANCH(ins,cond,sign) \
2555         if (ins->inst_true_bb->native_offset) { \
2556                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2557         } else { \
2558                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2559                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2560             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2561                         x86_branch8 (code, cond, 0, sign); \
2562                 else \
2563                         x86_branch32 (code, cond, 0, sign); \
2564 }
2565
2566 typedef struct {
2567         MonoMethodSignature *sig;
2568         CallInfo *cinfo;
2569 } ArchDynCallInfo;
2570
2571 static gboolean
2572 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2573 {
2574         int i;
2575
2576 #ifdef HOST_WIN32
2577         return FALSE;
2578 #endif
2579
2580         switch (cinfo->ret.storage) {
2581         case ArgNone:
2582         case ArgInIReg:
2583                 break;
2584         case ArgValuetypeInReg: {
2585                 ArgInfo *ainfo = &cinfo->ret;
2586
2587                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2588                         return FALSE;
2589                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2590                         return FALSE;
2591                 break;
2592         }
2593         default:
2594                 return FALSE;
2595         }
2596
2597         for (i = 0; i < cinfo->nargs; ++i) {
2598                 ArgInfo *ainfo = &cinfo->args [i];
2599                 switch (ainfo->storage) {
2600                 case ArgInIReg:
2601                         break;
2602                 case ArgValuetypeInReg:
2603                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2604                                 return FALSE;
2605                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2606                                 return FALSE;
2607                         break;
2608                 default:
2609                         return FALSE;
2610                 }
2611         }
2612
2613         return TRUE;
2614 }
2615
2616 /*
2617  * mono_arch_dyn_call_prepare:
2618  *
2619  *   Return a pointer to an arch-specific structure which contains information
2620  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2621  * supported for SIG.
2622  * This function is equivalent to ffi_prep_cif in libffi.
2623  */
2624 MonoDynCallInfo*
2625 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2626 {
2627         ArchDynCallInfo *info;
2628         CallInfo *cinfo;
2629
2630         cinfo = get_call_info (NULL, NULL, sig);
2631
2632         if (!dyn_call_supported (sig, cinfo)) {
2633                 g_free (cinfo);
2634                 return NULL;
2635         }
2636
2637         info = g_new0 (ArchDynCallInfo, 1);
2638         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2639         info->sig = sig;
2640         info->cinfo = cinfo;
2641
2642         return (MonoDynCallInfo*)info;
2643 }
2644
2645 /*
2646  * mono_arch_dyn_call_free:
2647  *
2648  *   Free a MonoDynCallInfo structure.
2649  */
2650 void
2651 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2652 {
2653         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2654
2655         g_free (ainfo->cinfo);
2656         g_free (ainfo);
2657 }
2658
2659 #if !defined(__native_client__)
2660 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2661 #define GREG_TO_PTR(greg) (gpointer)(greg)
2662 #else
2663 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2664 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2665 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2666 #endif
2667
2668 /*
2669  * mono_arch_get_start_dyn_call:
2670  *
2671  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2672  * store the result into BUF.
2673  * ARGS should be an array of pointers pointing to the arguments.
2674  * RET should point to a memory buffer large enought to hold the result of the
2675  * call.
2676  * This function should be as fast as possible, any work which does not depend
2677  * on the actual values of the arguments should be done in
2678  * mono_arch_dyn_call_prepare ().
2679  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2680  * libffi.
2681  */
2682 void
2683 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2684 {
2685         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2686         DynCallArgs *p = (DynCallArgs*)buf;
2687         int arg_index, greg, i, pindex;
2688         MonoMethodSignature *sig = dinfo->sig;
2689
2690         g_assert (buf_len >= sizeof (DynCallArgs));
2691
2692         p->res = 0;
2693         p->ret = ret;
2694
2695         arg_index = 0;
2696         greg = 0;
2697         pindex = 0;
2698
2699         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2700                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2701                 if (!sig->hasthis)
2702                         pindex = 1;
2703         }
2704
2705         if (dinfo->cinfo->vtype_retaddr)
2706                 p->regs [greg ++] = PTR_TO_GREG(ret);
2707
2708         for (i = pindex; i < sig->param_count; i++) {
2709                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2710                 gpointer *arg = args [arg_index ++];
2711
2712                 if (t->byref) {
2713                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2714                         continue;
2715                 }
2716
2717                 switch (t->type) {
2718                 case MONO_TYPE_STRING:
2719                 case MONO_TYPE_CLASS:
2720                 case MONO_TYPE_ARRAY:
2721                 case MONO_TYPE_SZARRAY:
2722                 case MONO_TYPE_OBJECT:
2723                 case MONO_TYPE_PTR:
2724                 case MONO_TYPE_I:
2725                 case MONO_TYPE_U:
2726 #if !defined(__mono_ilp32__)
2727                 case MONO_TYPE_I8:
2728                 case MONO_TYPE_U8:
2729 #endif
2730                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2731                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2732                         break;
2733 #if defined(__mono_ilp32__)
2734                 case MONO_TYPE_I8:
2735                 case MONO_TYPE_U8:
2736                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2737                         p->regs [greg ++] = *(guint64*)(arg);
2738                         break;
2739 #endif
2740                 case MONO_TYPE_BOOLEAN:
2741                 case MONO_TYPE_U1:
2742                         p->regs [greg ++] = *(guint8*)(arg);
2743                         break;
2744                 case MONO_TYPE_I1:
2745                         p->regs [greg ++] = *(gint8*)(arg);
2746                         break;
2747                 case MONO_TYPE_I2:
2748                         p->regs [greg ++] = *(gint16*)(arg);
2749                         break;
2750                 case MONO_TYPE_U2:
2751                 case MONO_TYPE_CHAR:
2752                         p->regs [greg ++] = *(guint16*)(arg);
2753                         break;
2754                 case MONO_TYPE_I4:
2755                         p->regs [greg ++] = *(gint32*)(arg);
2756                         break;
2757                 case MONO_TYPE_U4:
2758                         p->regs [greg ++] = *(guint32*)(arg);
2759                         break;
2760                 case MONO_TYPE_GENERICINST:
2761                     if (MONO_TYPE_IS_REFERENCE (t)) {
2762                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2763                                 break;
2764                         } else {
2765                                 /* Fall through */
2766                         }
2767                 case MONO_TYPE_VALUETYPE: {
2768                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2769
2770                         g_assert (ainfo->storage == ArgValuetypeInReg);
2771                         if (ainfo->pair_storage [0] != ArgNone) {
2772                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2773                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2774                         }
2775                         if (ainfo->pair_storage [1] != ArgNone) {
2776                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2777                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2778                         }
2779                         break;
2780                 }
2781                 default:
2782                         g_assert_not_reached ();
2783                 }
2784         }
2785
2786         g_assert (greg <= PARAM_REGS);
2787 }
2788
2789 /*
2790  * mono_arch_finish_dyn_call:
2791  *
2792  *   Store the result of a dyn call into the return value buffer passed to
2793  * start_dyn_call ().
2794  * This function should be as fast as possible, any work which does not depend
2795  * on the actual values of the arguments should be done in
2796  * mono_arch_dyn_call_prepare ().
2797  */
2798 void
2799 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2800 {
2801         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2802         MonoMethodSignature *sig = dinfo->sig;
2803         guint8 *ret = ((DynCallArgs*)buf)->ret;
2804         mgreg_t res = ((DynCallArgs*)buf)->res;
2805         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2806
2807         switch (sig_ret->type) {
2808         case MONO_TYPE_VOID:
2809                 *(gpointer*)ret = NULL;
2810                 break;
2811         case MONO_TYPE_STRING:
2812         case MONO_TYPE_CLASS:
2813         case MONO_TYPE_ARRAY:
2814         case MONO_TYPE_SZARRAY:
2815         case MONO_TYPE_OBJECT:
2816         case MONO_TYPE_I:
2817         case MONO_TYPE_U:
2818         case MONO_TYPE_PTR:
2819                 *(gpointer*)ret = GREG_TO_PTR(res);
2820                 break;
2821         case MONO_TYPE_I1:
2822                 *(gint8*)ret = res;
2823                 break;
2824         case MONO_TYPE_U1:
2825         case MONO_TYPE_BOOLEAN:
2826                 *(guint8*)ret = res;
2827                 break;
2828         case MONO_TYPE_I2:
2829                 *(gint16*)ret = res;
2830                 break;
2831         case MONO_TYPE_U2:
2832         case MONO_TYPE_CHAR:
2833                 *(guint16*)ret = res;
2834                 break;
2835         case MONO_TYPE_I4:
2836                 *(gint32*)ret = res;
2837                 break;
2838         case MONO_TYPE_U4:
2839                 *(guint32*)ret = res;
2840                 break;
2841         case MONO_TYPE_I8:
2842                 *(gint64*)ret = res;
2843                 break;
2844         case MONO_TYPE_U8:
2845                 *(guint64*)ret = res;
2846                 break;
2847         case MONO_TYPE_GENERICINST:
2848                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2849                         *(gpointer*)ret = GREG_TO_PTR(res);
2850                         break;
2851                 } else {
2852                         /* Fall through */
2853                 }
2854         case MONO_TYPE_VALUETYPE:
2855                 if (dinfo->cinfo->vtype_retaddr) {
2856                         /* Nothing to do */
2857                 } else {
2858                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2859
2860                         g_assert (ainfo->storage == ArgValuetypeInReg);
2861
2862                         if (ainfo->pair_storage [0] != ArgNone) {
2863                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2864                                 ((mgreg_t*)ret)[0] = res;
2865                         }
2866
2867                         g_assert (ainfo->pair_storage [1] == ArgNone);
2868                 }
2869                 break;
2870         default:
2871                 g_assert_not_reached ();
2872         }
2873 }
2874
2875 /* emit an exception if condition is fail */
2876 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2877         do {                                                        \
2878                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2879                 if (tins == NULL) {                                                                             \
2880                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2881                                         MONO_PATCH_INFO_EXC, exc_name);  \
2882                         x86_branch32 (code, cond, 0, signed);               \
2883                 } else {        \
2884                         EMIT_COND_BRANCH (tins, cond, signed);  \
2885                 }                       \
2886         } while (0);
2887
2888 #define EMIT_FPCOMPARE(code) do { \
2889         amd64_fcompp (code); \
2890         amd64_fnstsw (code); \
2891 } while (0);
2892
2893 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2894     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2895         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2896         amd64_ ##op (code); \
2897         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2898         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2899 } while (0);
2900
2901 static guint8*
2902 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2903 {
2904         gboolean no_patch = FALSE;
2905
2906         /*
2907          * FIXME: Add support for thunks
2908          */
2909         {
2910                 gboolean near_call = FALSE;
2911
2912                 /*
2913                  * Indirect calls are expensive so try to make a near call if possible.
2914                  * The caller memory is allocated by the code manager so it is
2915                  * guaranteed to be at a 32 bit offset.
2916                  */
2917
2918                 if (patch_type != MONO_PATCH_INFO_ABS) {
2919                         /* The target is in memory allocated using the code manager */
2920                         near_call = TRUE;
2921
2922                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2923                                 if (((MonoMethod*)data)->klass->image->aot_module)
2924                                         /* The callee might be an AOT method */
2925                                         near_call = FALSE;
2926                                 if (((MonoMethod*)data)->dynamic)
2927                                         /* The target is in malloc-ed memory */
2928                                         near_call = FALSE;
2929                         }
2930
2931                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2932                                 /*
2933                                  * The call might go directly to a native function without
2934                                  * the wrapper.
2935                                  */
2936                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2937                                 if (mi) {
2938                                         gconstpointer target = mono_icall_get_wrapper (mi);
2939                                         if ((((guint64)target) >> 32) != 0)
2940                                                 near_call = FALSE;
2941                                 }
2942                         }
2943                 }
2944                 else {
2945                         MonoJumpInfo *jinfo = NULL;
2946
2947                         if (cfg->abs_patches)
2948                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2949                         if (jinfo) {
2950                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2951                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2952                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2953                                                 near_call = TRUE;
2954                                         no_patch = TRUE;
2955                                 } else {
2956                                         /*
2957                                          * This is not really an optimization, but required because the
2958                                          * generic class init trampolines use R11 to pass the vtable.
2959                                          */
2960                                         near_call = TRUE;
2961                                 }
2962                         } else {
2963                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2964                                 if (info) {
2965                                         if (info->func == info->wrapper) {
2966                                                 /* No wrapper */
2967                                                 if ((((guint64)info->func) >> 32) == 0)
2968                                                         near_call = TRUE;
2969                                         }
2970                                         else {
2971                                                 /* See the comment in mono_codegen () */
2972                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2973                                                         near_call = TRUE;
2974                                         }
2975                                 }
2976                                 else if ((((guint64)data) >> 32) == 0) {
2977                                         near_call = TRUE;
2978                                         no_patch = TRUE;
2979                                 }
2980                         }
2981                 }
2982
2983                 if (cfg->method->dynamic)
2984                         /* These methods are allocated using malloc */
2985                         near_call = FALSE;
2986
2987 #ifdef MONO_ARCH_NOMAP32BIT
2988                 near_call = FALSE;
2989 #endif
2990 #if defined(__native_client__)
2991                 /* Always use near_call == TRUE for Native Client */
2992                 near_call = TRUE;
2993 #endif
2994                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2995                 if (optimize_for_xen)
2996                         near_call = FALSE;
2997
2998                 if (cfg->compile_aot) {
2999                         near_call = TRUE;
3000                         no_patch = TRUE;
3001                 }
3002
3003                 if (near_call) {
3004                         /*
3005                          * Align the call displacement to an address divisible by 4 so it does
3006                          * not span cache lines. This is required for code patching to work on SMP
3007                          * systems.
3008                          */
3009                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3010                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3011                                 amd64_padding (code, pad_size);
3012                         }
3013                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3014                         amd64_call_code (code, 0);
3015                 }
3016                 else {
3017                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3018                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3019                         amd64_call_reg (code, GP_SCRATCH_REG);
3020                 }
3021         }
3022
3023         return code;
3024 }
3025
3026 static inline guint8*
3027 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3028 {
3029 #ifdef HOST_WIN32
3030         if (win64_adjust_stack)
3031                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3032 #endif
3033         code = emit_call_body (cfg, code, patch_type, data);
3034 #ifdef HOST_WIN32
3035         if (win64_adjust_stack)
3036                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3037 #endif
3038
3039         return code;
3040 }
3041
3042 static inline int
3043 store_membase_imm_to_store_membase_reg (int opcode)
3044 {
3045         switch (opcode) {
3046         case OP_STORE_MEMBASE_IMM:
3047                 return OP_STORE_MEMBASE_REG;
3048         case OP_STOREI4_MEMBASE_IMM:
3049                 return OP_STOREI4_MEMBASE_REG;
3050         case OP_STOREI8_MEMBASE_IMM:
3051                 return OP_STOREI8_MEMBASE_REG;
3052         }
3053
3054         return -1;
3055 }
3056
3057 #ifndef DISABLE_JIT
3058
3059 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3060
3061 /*
3062  * mono_arch_peephole_pass_1:
3063  *
3064  *   Perform peephole opts which should/can be performed before local regalloc
3065  */
3066 void
3067 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3068 {
3069         MonoInst *ins, *n;
3070
3071         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3072                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3073
3074                 switch (ins->opcode) {
3075                 case OP_ADD_IMM:
3076                 case OP_IADD_IMM:
3077                 case OP_LADD_IMM:
3078                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3079                                 /*
3080                                  * X86_LEA is like ADD, but doesn't have the
3081                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3082                                  * its operand to 64 bit.
3083                                  */
3084                                 ins->opcode = OP_X86_LEA_MEMBASE;
3085                                 ins->inst_basereg = ins->sreg1;
3086                         }
3087                         break;
3088                 case OP_LXOR:
3089                 case OP_IXOR:
3090                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3091                                 MonoInst *ins2;
3092
3093                                 /*
3094                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3095                                  * the latter has length 2-3 instead of 6 (reverse constant
3096                                  * propagation). These instruction sequences are very common
3097                                  * in the initlocals bblock.
3098                                  */
3099                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3100                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3101                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3102                                                 ins2->sreg1 = ins->dreg;
3103                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3104                                                 /* Continue */
3105                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3106                                                 NULLIFY_INS (ins2);
3107                                                 /* Continue */
3108                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3109                                                 /* Continue */
3110                                         } else {
3111                                                 break;
3112                                         }
3113                                 }
3114                         }
3115                         break;
3116                 case OP_COMPARE_IMM:
3117                 case OP_LCOMPARE_IMM:
3118                         /* OP_COMPARE_IMM (reg, 0)
3119                          * -->
3120                          * OP_AMD64_TEST_NULL (reg)
3121                          */
3122                         if (!ins->inst_imm)
3123                                 ins->opcode = OP_AMD64_TEST_NULL;
3124                         break;
3125                 case OP_ICOMPARE_IMM:
3126                         if (!ins->inst_imm)
3127                                 ins->opcode = OP_X86_TEST_NULL;
3128                         break;
3129                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3130                         /*
3131                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3132                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3133                          * -->
3134                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3135                          * OP_COMPARE_IMM reg, imm
3136                          *
3137                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3138                          */
3139                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3140                             ins->inst_basereg == last_ins->inst_destbasereg &&
3141                             ins->inst_offset == last_ins->inst_offset) {
3142                                         ins->opcode = OP_ICOMPARE_IMM;
3143                                         ins->sreg1 = last_ins->sreg1;
3144
3145                                         /* check if we can remove cmp reg,0 with test null */
3146                                         if (!ins->inst_imm)
3147                                                 ins->opcode = OP_X86_TEST_NULL;
3148                                 }
3149
3150                         break;
3151                 }
3152
3153                 mono_peephole_ins (bb, ins);
3154         }
3155 }
3156
3157 void
3158 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3159 {
3160         MonoInst *ins, *n;
3161
3162         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3163                 switch (ins->opcode) {
3164                 case OP_ICONST:
3165                 case OP_I8CONST: {
3166                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3167                         /* reg = 0 -> XOR (reg, reg) */
3168                         /* XOR sets cflags on x86, so we cant do it always */
3169                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3170                                 ins->opcode = OP_LXOR;
3171                                 ins->sreg1 = ins->dreg;
3172                                 ins->sreg2 = ins->dreg;
3173                                 /* Fall through */
3174                         } else {
3175                                 break;
3176                         }
3177                 }
3178                 case OP_LXOR:
3179                         /*
3180                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3181                          * 0 result into 64 bits.
3182                          */
3183                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3184                                 ins->opcode = OP_IXOR;
3185                         }
3186                         /* Fall through */
3187                 case OP_IXOR:
3188                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3189                                 MonoInst *ins2;
3190
3191                                 /*
3192                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3193                                  * the latter has length 2-3 instead of 6 (reverse constant
3194                                  * propagation). These instruction sequences are very common
3195                                  * in the initlocals bblock.
3196                                  */
3197                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3198                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3199                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3200                                                 ins2->sreg1 = ins->dreg;
3201                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3202                                                 /* Continue */
3203                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3204                                                 NULLIFY_INS (ins2);
3205                                                 /* Continue */
3206                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3207                                                 /* Continue */
3208                                         } else {
3209                                                 break;
3210                                         }
3211                                 }
3212                         }
3213                         break;
3214                 case OP_IADD_IMM:
3215                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3216                                 ins->opcode = OP_X86_INC_REG;
3217                         break;
3218                 case OP_ISUB_IMM:
3219                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3220                                 ins->opcode = OP_X86_DEC_REG;
3221                         break;
3222                 }
3223
3224                 mono_peephole_ins (bb, ins);
3225         }
3226 }
3227
3228 #define NEW_INS(cfg,ins,dest,op) do {   \
3229                 MONO_INST_NEW ((cfg), (dest), (op)); \
3230         (dest)->cil_code = (ins)->cil_code; \
3231         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3232         } while (0)
3233
3234 /*
3235  * mono_arch_lowering_pass:
3236  *
3237  *  Converts complex opcodes into simpler ones so that each IR instruction
3238  * corresponds to one machine instruction.
3239  */
3240 void
3241 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3242 {
3243         MonoInst *ins, *n, *temp;
3244
3245         /*
3246          * FIXME: Need to add more instructions, but the current machine
3247          * description can't model some parts of the composite instructions like
3248          * cdq.
3249          */
3250         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3251                 switch (ins->opcode) {
3252                 case OP_DIV_IMM:
3253                 case OP_REM_IMM:
3254                 case OP_IDIV_IMM:
3255                 case OP_IDIV_UN_IMM:
3256                 case OP_IREM_UN_IMM:
3257                 case OP_LREM_IMM:
3258                 case OP_IREM_IMM:
3259                         mono_decompose_op_imm (cfg, bb, ins);
3260                         break;
3261                 case OP_COMPARE_IMM:
3262                 case OP_LCOMPARE_IMM:
3263                         if (!amd64_is_imm32 (ins->inst_imm)) {
3264                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3265                                 temp->inst_c0 = ins->inst_imm;
3266                                 temp->dreg = mono_alloc_ireg (cfg);
3267                                 ins->opcode = OP_COMPARE;
3268                                 ins->sreg2 = temp->dreg;
3269                         }
3270                         break;
3271 #ifndef __mono_ilp32__
3272                 case OP_LOAD_MEMBASE:
3273 #endif
3274                 case OP_LOADI8_MEMBASE:
3275 #ifndef __native_client_codegen__
3276                 /*  Don't generate memindex opcodes (to simplify */
3277                 /*  read sandboxing) */
3278                         if (!amd64_is_imm32 (ins->inst_offset)) {
3279                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3280                                 temp->inst_c0 = ins->inst_offset;
3281                                 temp->dreg = mono_alloc_ireg (cfg);
3282                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3283                                 ins->inst_indexreg = temp->dreg;
3284                         }
3285 #endif
3286                         break;
3287 #ifndef __mono_ilp32__
3288                 case OP_STORE_MEMBASE_IMM:
3289 #endif
3290                 case OP_STOREI8_MEMBASE_IMM:
3291                         if (!amd64_is_imm32 (ins->inst_imm)) {
3292                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3293                                 temp->inst_c0 = ins->inst_imm;
3294                                 temp->dreg = mono_alloc_ireg (cfg);
3295                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3296                                 ins->sreg1 = temp->dreg;
3297                         }
3298                         break;
3299 #ifdef MONO_ARCH_SIMD_INTRINSICS
3300                 case OP_EXPAND_I1: {
3301                                 int temp_reg1 = mono_alloc_ireg (cfg);
3302                                 int temp_reg2 = mono_alloc_ireg (cfg);
3303                                 int original_reg = ins->sreg1;
3304
3305                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3306                                 temp->sreg1 = original_reg;
3307                                 temp->dreg = temp_reg1;
3308
3309                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3310                                 temp->sreg1 = temp_reg1;
3311                                 temp->dreg = temp_reg2;
3312                                 temp->inst_imm = 8;
3313
3314                                 NEW_INS (cfg, ins, temp, OP_LOR);
3315                                 temp->sreg1 = temp->dreg = temp_reg2;
3316                                 temp->sreg2 = temp_reg1;
3317
3318                                 ins->opcode = OP_EXPAND_I2;
3319                                 ins->sreg1 = temp_reg2;
3320                         }
3321                         break;
3322 #endif
3323                 default:
3324                         break;
3325                 }
3326         }
3327
3328         bb->max_vreg = cfg->next_vreg;
3329 }
3330
3331 static const int
3332 branch_cc_table [] = {
3333         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3334         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3335         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3336 };
3337
3338 /* Maps CMP_... constants to X86_CC_... constants */
3339 static const int
3340 cc_table [] = {
3341         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3342         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3343 };
3344
3345 static const int
3346 cc_signed_table [] = {
3347         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3348         FALSE, FALSE, FALSE, FALSE
3349 };
3350
3351 /*#include "cprop.c"*/
3352
3353 static unsigned char*
3354 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3355 {
3356         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3357
3358         if (size == 1)
3359                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3360         else if (size == 2)
3361                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3362         return code;
3363 }
3364
3365 static unsigned char*
3366 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3367 {
3368         int sreg = tree->sreg1;
3369         int need_touch = FALSE;
3370
3371 #if defined(HOST_WIN32)
3372         need_touch = TRUE;
3373 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3374         if (!tree->flags & MONO_INST_INIT)
3375                 need_touch = TRUE;
3376 #endif
3377
3378         if (need_touch) {
3379                 guint8* br[5];
3380
3381                 /*
3382                  * Under Windows:
3383                  * If requested stack size is larger than one page,
3384                  * perform stack-touch operation
3385                  */
3386                 /*
3387                  * Generate stack probe code.
3388                  * Under Windows, it is necessary to allocate one page at a time,
3389                  * "touching" stack after each successful sub-allocation. This is
3390                  * because of the way stack growth is implemented - there is a
3391                  * guard page before the lowest stack page that is currently commited.
3392                  * Stack normally grows sequentially so OS traps access to the
3393                  * guard page and commits more pages when needed.
3394                  */
3395                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3396                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3397
3398                 br[2] = code; /* loop */
3399                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3400                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3401                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3402                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3403                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3404                 amd64_patch (br[3], br[2]);
3405                 amd64_test_reg_reg (code, sreg, sreg);
3406                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3407                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3408
3409                 br[1] = code; x86_jump8 (code, 0);
3410
3411                 amd64_patch (br[0], code);
3412                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3413                 amd64_patch (br[1], code);
3414                 amd64_patch (br[4], code);
3415         }
3416         else
3417                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3418
3419         if (tree->flags & MONO_INST_INIT) {
3420                 int offset = 0;
3421                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3422                         amd64_push_reg (code, AMD64_RAX);
3423                         offset += 8;
3424                 }
3425                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3426                         amd64_push_reg (code, AMD64_RCX);
3427                         offset += 8;
3428                 }
3429                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3430                         amd64_push_reg (code, AMD64_RDI);
3431                         offset += 8;
3432                 }
3433
3434                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3435                 if (sreg != AMD64_RCX)
3436                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3437                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3438
3439                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3440                 if (cfg->param_area)
3441                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3442                 amd64_cld (code);
3443 #if defined(__default_codegen__)
3444                 amd64_prefix (code, X86_REP_PREFIX);
3445                 amd64_stosl (code);
3446 #elif defined(__native_client_codegen__)
3447                 /* NaCl stos pseudo-instruction */
3448                 amd64_codegen_pre(code);
3449                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3450                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3451                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3452                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3453                 amd64_prefix (code, X86_REP_PREFIX);
3454                 amd64_stosl (code);
3455                 amd64_codegen_post(code);
3456 #endif /* __native_client_codegen__ */
3457
3458                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3459                         amd64_pop_reg (code, AMD64_RDI);
3460                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3461                         amd64_pop_reg (code, AMD64_RCX);
3462                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3463                         amd64_pop_reg (code, AMD64_RAX);
3464         }
3465         return code;
3466 }
3467
3468 static guint8*
3469 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3470 {
3471         CallInfo *cinfo;
3472         guint32 quad;
3473
3474         /* Move return value to the target register */
3475         /* FIXME: do this in the local reg allocator */
3476         switch (ins->opcode) {
3477         case OP_CALL:
3478         case OP_CALL_REG:
3479         case OP_CALL_MEMBASE:
3480         case OP_LCALL:
3481         case OP_LCALL_REG:
3482         case OP_LCALL_MEMBASE:
3483                 g_assert (ins->dreg == AMD64_RAX);
3484                 break;
3485         case OP_FCALL:
3486         case OP_FCALL_REG:
3487         case OP_FCALL_MEMBASE:
3488                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3489                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3490                 }
3491                 else {
3492                         if (ins->dreg != AMD64_XMM0)
3493                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3494                 }
3495                 break;
3496         case OP_VCALL:
3497         case OP_VCALL_REG:
3498         case OP_VCALL_MEMBASE:
3499         case OP_VCALL2:
3500         case OP_VCALL2_REG:
3501         case OP_VCALL2_MEMBASE:
3502                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3503                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3504                         MonoInst *loc = cfg->arch.vret_addr_loc;
3505
3506                         /* Load the destination address */
3507                         g_assert (loc->opcode == OP_REGOFFSET);
3508                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3509
3510                         for (quad = 0; quad < 2; quad ++) {
3511                                 switch (cinfo->ret.pair_storage [quad]) {
3512                                 case ArgInIReg:
3513                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3514                                         break;
3515                                 case ArgInFloatSSEReg:
3516                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3517                                         break;
3518                                 case ArgInDoubleSSEReg:
3519                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3520                                         break;
3521                                 case ArgNone:
3522                                         break;
3523                                 default:
3524                                         NOT_IMPLEMENTED;
3525                                 }
3526                         }
3527                 }
3528                 break;
3529         }
3530
3531         return code;
3532 }
3533
3534 #endif /* DISABLE_JIT */
3535
3536 #ifdef __APPLE__
3537 static int tls_gs_offset;
3538 #endif
3539
3540 gboolean
3541 mono_amd64_have_tls_get (void)
3542 {
3543 #ifdef __APPLE__
3544         static gboolean have_tls_get = FALSE;
3545         static gboolean inited = FALSE;
3546         guint8 *ins;
3547
3548         if (inited)
3549                 return have_tls_get;
3550
3551         ins = (guint8*)pthread_getspecific;
3552
3553         /*
3554          * We're looking for these two instructions:
3555          *
3556          * mov    %gs:[offset](,%rdi,8),%rax
3557          * retq
3558          */
3559         have_tls_get = ins [0] == 0x65 &&
3560                        ins [1] == 0x48 &&
3561                        ins [2] == 0x8b &&
3562                        ins [3] == 0x04 &&
3563                        ins [4] == 0xfd &&
3564                        ins [6] == 0x00 &&
3565                        ins [7] == 0x00 &&
3566                        ins [8] == 0x00 &&
3567                        ins [9] == 0xc3;
3568
3569         inited = TRUE;
3570
3571         tls_gs_offset = ins[5];
3572
3573         return have_tls_get;
3574 #else
3575         return TRUE;
3576 #endif
3577 }
3578
3579 int
3580 mono_amd64_get_tls_gs_offset (void)
3581 {
3582 #ifdef TARGET_OSX
3583         return tls_gs_offset;
3584 #else
3585         g_assert_not_reached ();
3586         return -1;
3587 #endif
3588 }
3589
3590 /*
3591  * mono_amd64_emit_tls_get:
3592  * @code: buffer to store code to
3593  * @dreg: hard register where to place the result
3594  * @tls_offset: offset info
3595  *
3596  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3597  * the dreg register the item in the thread local storage identified
3598  * by tls_offset.
3599  *
3600  * Returns: a pointer to the end of the stored code
3601  */
3602 guint8*
3603 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3604 {
3605 #ifdef HOST_WIN32
3606         if (tls_offset < 64) {
3607                 x86_prefix (code, X86_GS_PREFIX);
3608                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3609         } else {
3610                 guint8 *buf [16];
3611
3612                 g_assert (tls_offset < 0x440);
3613                 /* Load TEB->TlsExpansionSlots */
3614                 x86_prefix (code, X86_GS_PREFIX);
3615                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3616                 amd64_test_reg_reg (code, dreg, dreg);
3617                 buf [0] = code;
3618                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3619                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3620                 amd64_patch (buf [0], code);
3621         }
3622 #elif defined(__APPLE__)
3623         x86_prefix (code, X86_GS_PREFIX);
3624         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3625 #else
3626         if (optimize_for_xen) {
3627                 x86_prefix (code, X86_FS_PREFIX);
3628                 amd64_mov_reg_mem (code, dreg, 0, 8);
3629                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3630         } else {
3631                 x86_prefix (code, X86_FS_PREFIX);
3632                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3633         }
3634 #endif
3635         return code;
3636 }
3637
3638 static guint8*
3639 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3640 {
3641         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3642 #ifdef TARGET_OSX
3643         if (dreg != offset_reg)
3644                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3645         amd64_prefix (code, X86_GS_PREFIX);
3646         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3647 #elif defined(__linux__)
3648         int tmpreg = -1;
3649
3650         if (dreg == offset_reg) {
3651                 /* Use a temporary reg by saving it to the redzone */
3652                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3653                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3654                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3655                 offset_reg = tmpreg;
3656         }
3657         x86_prefix (code, X86_FS_PREFIX);
3658         amd64_mov_reg_mem (code, dreg, 0, 8);
3659         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3660         if (tmpreg != -1)
3661                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3662 #else
3663         g_assert_not_reached ();
3664 #endif
3665         return code;
3666 }
3667
3668 static guint8*
3669 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3670 {
3671 #ifdef HOST_WIN32
3672         g_assert_not_reached ();
3673 #elif defined(__APPLE__)
3674         x86_prefix (code, X86_GS_PREFIX);
3675         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3676 #else
3677         g_assert (!optimize_for_xen);
3678         x86_prefix (code, X86_FS_PREFIX);
3679         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3680 #endif
3681         return code;
3682 }
3683
3684 static guint8*
3685 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3686 {
3687         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3688 #ifdef HOST_WIN32
3689         g_assert_not_reached ();
3690 #elif defined(__APPLE__)
3691         x86_prefix (code, X86_GS_PREFIX);
3692         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3693 #else
3694         x86_prefix (code, X86_FS_PREFIX);
3695         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3696 #endif
3697         return code;
3698 }
3699
3700  /*
3701  * mono_arch_translate_tls_offset:
3702  *
3703  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3704  */
3705 int
3706 mono_arch_translate_tls_offset (int offset)
3707 {
3708 #ifdef __APPLE__
3709         return tls_gs_offset + (offset * 8);
3710 #else
3711         return offset;
3712 #endif
3713 }
3714
3715 /*
3716  * emit_setup_lmf:
3717  *
3718  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3719  */
3720 static guint8*
3721 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3722 {
3723         /*
3724          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3725          */
3726         /*
3727          * sp is saved right before calls but we need to save it here too so
3728          * async stack walks would work.
3729          */
3730         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3731         /* Save rbp */
3732         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3733         if (cfg->arch.omit_fp && cfa_offset != -1)
3734                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3735
3736         /* These can't contain refs */
3737         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3738         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3739         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3740         /* These are handled automatically by the stack marking code */
3741         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3742
3743         return code;
3744 }
3745
3746 #define REAL_PRINT_REG(text,reg) \
3747 mono_assert (reg >= 0); \
3748 amd64_push_reg (code, AMD64_RAX); \
3749 amd64_push_reg (code, AMD64_RDX); \
3750 amd64_push_reg (code, AMD64_RCX); \
3751 amd64_push_reg (code, reg); \
3752 amd64_push_imm (code, reg); \
3753 amd64_push_imm (code, text " %d %p\n"); \
3754 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3755 amd64_call_reg (code, AMD64_RAX); \
3756 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3757 amd64_pop_reg (code, AMD64_RCX); \
3758 amd64_pop_reg (code, AMD64_RDX); \
3759 amd64_pop_reg (code, AMD64_RAX);
3760
3761 /* benchmark and set based on cpu */
3762 #define LOOP_ALIGNMENT 8
3763 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3764
3765 #ifndef DISABLE_JIT
3766 void
3767 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3768 {
3769         MonoInst *ins;
3770         MonoCallInst *call;
3771         guint offset;
3772         guint8 *code = cfg->native_code + cfg->code_len;
3773         MonoInst *last_ins = NULL;
3774         guint last_offset = 0;
3775         int max_len;
3776
3777         /* Fix max_offset estimate for each successor bb */
3778         if (cfg->opt & MONO_OPT_BRANCH) {
3779                 int current_offset = cfg->code_len;
3780                 MonoBasicBlock *current_bb;
3781                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3782                         current_bb->max_offset = current_offset;
3783                         current_offset += current_bb->max_length;
3784                 }
3785         }
3786
3787         if (cfg->opt & MONO_OPT_LOOP) {
3788                 int pad, align = LOOP_ALIGNMENT;
3789                 /* set alignment depending on cpu */
3790                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3791                         pad = align - pad;
3792                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3793                         amd64_padding (code, pad);
3794                         cfg->code_len += pad;
3795                         bb->native_offset = cfg->code_len;
3796                 }
3797         }
3798
3799 #if defined(__native_client_codegen__)
3800         /* For Native Client, all indirect call/jump targets must be */
3801         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3802         /* indirectly as well.                                       */
3803         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3804                                       (bb->flags & BB_EXCEPTION_HANDLER);
3805
3806         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3807                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3808                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3809                 cfg->code_len += pad;
3810                 bb->native_offset = cfg->code_len;
3811         }
3812 #endif  /*__native_client_codegen__*/
3813
3814         if (cfg->verbose_level > 2)
3815                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3816
3817         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3818                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3819                 g_assert (!cfg->compile_aot);
3820
3821                 cov->data [bb->dfn].cil_code = bb->cil_code;
3822                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3823                 /* this is not thread save, but good enough */
3824                 amd64_inc_membase (code, AMD64_R11, 0);
3825         }
3826
3827         offset = code - cfg->native_code;
3828
3829         mono_debug_open_block (cfg, bb, offset);
3830
3831     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3832                 x86_breakpoint (code);
3833
3834         MONO_BB_FOR_EACH_INS (bb, ins) {
3835                 offset = code - cfg->native_code;
3836
3837                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3838
3839 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3840
3841                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3842                         cfg->code_size *= 2;
3843                         cfg->native_code = mono_realloc_native_code(cfg);
3844                         code = cfg->native_code + offset;
3845                         cfg->stat_code_reallocs++;
3846                 }
3847
3848                 if (cfg->debug_info)
3849                         mono_debug_record_line_number (cfg, ins, offset);
3850
3851                 switch (ins->opcode) {
3852                 case OP_BIGMUL:
3853                         amd64_mul_reg (code, ins->sreg2, TRUE);
3854                         break;
3855                 case OP_BIGMUL_UN:
3856                         amd64_mul_reg (code, ins->sreg2, FALSE);
3857                         break;
3858                 case OP_X86_SETEQ_MEMBASE:
3859                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3860                         break;
3861                 case OP_STOREI1_MEMBASE_IMM:
3862                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3863                         break;
3864                 case OP_STOREI2_MEMBASE_IMM:
3865                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3866                         break;
3867                 case OP_STOREI4_MEMBASE_IMM:
3868                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3869                         break;
3870                 case OP_STOREI1_MEMBASE_REG:
3871                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3872                         break;
3873                 case OP_STOREI2_MEMBASE_REG:
3874                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3875                         break;
3876                 /* In AMD64 NaCl, pointers are 4 bytes, */
3877                 /*  so STORE_* != STOREI8_*. Likewise below. */
3878                 case OP_STORE_MEMBASE_REG:
3879                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3880                         break;
3881                 case OP_STOREI8_MEMBASE_REG:
3882                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3883                         break;
3884                 case OP_STOREI4_MEMBASE_REG:
3885                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3886                         break;
3887                 case OP_STORE_MEMBASE_IMM:
3888 #ifndef __native_client_codegen__
3889                         /* In NaCl, this could be a PCONST type, which could */
3890                         /* mean a pointer type was copied directly into the  */
3891                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3892                         /* the value would be 0x00000000FFFFFFFF which is    */
3893                         /* not proper for an imm32 unless you cast it.       */
3894                         g_assert (amd64_is_imm32 (ins->inst_imm));
3895 #endif
3896                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3897                         break;
3898                 case OP_STOREI8_MEMBASE_IMM:
3899                         g_assert (amd64_is_imm32 (ins->inst_imm));
3900                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3901                         break;
3902                 case OP_LOAD_MEM:
3903 #ifdef __mono_ilp32__
3904                         /* In ILP32, pointers are 4 bytes, so separate these */
3905                         /* cases, use literal 8 below where we really want 8 */
3906                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3907                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3908                         break;
3909 #endif
3910                 case OP_LOADI8_MEM:
3911                         // FIXME: Decompose this earlier
3912                         if (amd64_is_imm32 (ins->inst_imm))
3913                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3914                         else {
3915                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3916                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3917                         }
3918                         break;
3919                 case OP_LOADI4_MEM:
3920                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3921                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3922                         break;
3923                 case OP_LOADU4_MEM:
3924                         // FIXME: Decompose this earlier
3925                         if (amd64_is_imm32 (ins->inst_imm))
3926                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3927                         else {
3928                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3929                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3930                         }
3931                         break;
3932                 case OP_LOADU1_MEM:
3933                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3934                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3935                         break;
3936                 case OP_LOADU2_MEM:
3937                         /* For NaCl, pointers are 4 bytes, so separate these */
3938                         /* cases, use literal 8 below where we really want 8 */
3939                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3940                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3941                         break;
3942                 case OP_LOAD_MEMBASE:
3943                         g_assert (amd64_is_imm32 (ins->inst_offset));
3944                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3945                         break;
3946                 case OP_LOADI8_MEMBASE:
3947                         /* Use literal 8 instead of sizeof pointer or */
3948                         /* register, we really want 8 for this opcode */
3949                         g_assert (amd64_is_imm32 (ins->inst_offset));
3950                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3951                         break;
3952                 case OP_LOADI4_MEMBASE:
3953                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3954                         break;
3955                 case OP_LOADU4_MEMBASE:
3956                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3957                         break;
3958                 case OP_LOADU1_MEMBASE:
3959                         /* The cpu zero extends the result into 64 bits */
3960                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3961                         break;
3962                 case OP_LOADI1_MEMBASE:
3963                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3964                         break;
3965                 case OP_LOADU2_MEMBASE:
3966                         /* The cpu zero extends the result into 64 bits */
3967                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3968                         break;
3969                 case OP_LOADI2_MEMBASE:
3970                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3971                         break;
3972                 case OP_AMD64_LOADI8_MEMINDEX:
3973                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3974                         break;
3975                 case OP_LCONV_TO_I1:
3976                 case OP_ICONV_TO_I1:
3977                 case OP_SEXT_I1:
3978                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3979                         break;
3980                 case OP_LCONV_TO_I2:
3981                 case OP_ICONV_TO_I2:
3982                 case OP_SEXT_I2:
3983                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3984                         break;
3985                 case OP_LCONV_TO_U1:
3986                 case OP_ICONV_TO_U1:
3987                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3988                         break;
3989                 case OP_LCONV_TO_U2:
3990                 case OP_ICONV_TO_U2:
3991                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3992                         break;
3993                 case OP_ZEXT_I4:
3994                         /* Clean out the upper word */
3995                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3996                         break;
3997                 case OP_SEXT_I4:
3998                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3999                         break;
4000                 case OP_COMPARE:
4001                 case OP_LCOMPARE:
4002                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4003                         break;
4004                 case OP_COMPARE_IMM:
4005 #if defined(__mono_ilp32__)
4006                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4007                         g_assert (amd64_is_imm32 (ins->inst_imm));
4008                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4009                         break;
4010 #endif
4011                 case OP_LCOMPARE_IMM:
4012                         g_assert (amd64_is_imm32 (ins->inst_imm));
4013                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4014                         break;
4015                 case OP_X86_COMPARE_REG_MEMBASE:
4016                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4017                         break;
4018                 case OP_X86_TEST_NULL:
4019                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4020                         break;
4021                 case OP_AMD64_TEST_NULL:
4022                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4023                         break;
4024
4025                 case OP_X86_ADD_REG_MEMBASE:
4026                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4027                         break;
4028                 case OP_X86_SUB_REG_MEMBASE:
4029                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4030                         break;
4031                 case OP_X86_AND_REG_MEMBASE:
4032                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4033                         break;
4034                 case OP_X86_OR_REG_MEMBASE:
4035                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4036                         break;
4037                 case OP_X86_XOR_REG_MEMBASE:
4038                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4039                         break;
4040
4041                 case OP_X86_ADD_MEMBASE_IMM:
4042                         /* FIXME: Make a 64 version too */
4043                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4044                         break;
4045                 case OP_X86_SUB_MEMBASE_IMM:
4046                         g_assert (amd64_is_imm32 (ins->inst_imm));
4047                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4048                         break;
4049                 case OP_X86_AND_MEMBASE_IMM:
4050                         g_assert (amd64_is_imm32 (ins->inst_imm));
4051                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4052                         break;
4053                 case OP_X86_OR_MEMBASE_IMM:
4054                         g_assert (amd64_is_imm32 (ins->inst_imm));
4055                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4056                         break;
4057                 case OP_X86_XOR_MEMBASE_IMM:
4058                         g_assert (amd64_is_imm32 (ins->inst_imm));
4059                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4060                         break;
4061                 case OP_X86_ADD_MEMBASE_REG:
4062                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4063                         break;
4064                 case OP_X86_SUB_MEMBASE_REG:
4065                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4066                         break;
4067                 case OP_X86_AND_MEMBASE_REG:
4068                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4069                         break;
4070                 case OP_X86_OR_MEMBASE_REG:
4071                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4072                         break;
4073                 case OP_X86_XOR_MEMBASE_REG:
4074                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4075                         break;
4076                 case OP_X86_INC_MEMBASE:
4077                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4078                         break;
4079                 case OP_X86_INC_REG:
4080                         amd64_inc_reg_size (code, ins->dreg, 4);
4081                         break;
4082                 case OP_X86_DEC_MEMBASE:
4083                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4084                         break;
4085                 case OP_X86_DEC_REG:
4086                         amd64_dec_reg_size (code, ins->dreg, 4);
4087                         break;
4088                 case OP_X86_MUL_REG_MEMBASE:
4089                 case OP_X86_MUL_MEMBASE_REG:
4090                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4091                         break;
4092                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4093                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4094                         break;
4095                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4096                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4097                         break;
4098                 case OP_AMD64_COMPARE_MEMBASE_REG:
4099                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4100                         break;
4101                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4102                         g_assert (amd64_is_imm32 (ins->inst_imm));
4103                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4104                         break;
4105                 case OP_X86_COMPARE_MEMBASE8_IMM:
4106                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4107                         break;
4108                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4109                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4110                         break;
4111                 case OP_AMD64_COMPARE_REG_MEMBASE:
4112                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4113                         break;
4114
4115                 case OP_AMD64_ADD_REG_MEMBASE:
4116                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4117                         break;
4118                 case OP_AMD64_SUB_REG_MEMBASE:
4119                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4120                         break;
4121                 case OP_AMD64_AND_REG_MEMBASE:
4122                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4123                         break;
4124                 case OP_AMD64_OR_REG_MEMBASE:
4125                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4126                         break;
4127                 case OP_AMD64_XOR_REG_MEMBASE:
4128                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4129                         break;
4130
4131                 case OP_AMD64_ADD_MEMBASE_REG:
4132                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4133                         break;
4134                 case OP_AMD64_SUB_MEMBASE_REG:
4135                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4136                         break;
4137                 case OP_AMD64_AND_MEMBASE_REG:
4138                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4139                         break;
4140                 case OP_AMD64_OR_MEMBASE_REG:
4141                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4142                         break;
4143                 case OP_AMD64_XOR_MEMBASE_REG:
4144                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4145                         break;
4146
4147                 case OP_AMD64_ADD_MEMBASE_IMM:
4148                         g_assert (amd64_is_imm32 (ins->inst_imm));
4149                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4150                         break;
4151                 case OP_AMD64_SUB_MEMBASE_IMM:
4152                         g_assert (amd64_is_imm32 (ins->inst_imm));
4153                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4154                         break;
4155                 case OP_AMD64_AND_MEMBASE_IMM:
4156                         g_assert (amd64_is_imm32 (ins->inst_imm));
4157                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4158                         break;
4159                 case OP_AMD64_OR_MEMBASE_IMM:
4160                         g_assert (amd64_is_imm32 (ins->inst_imm));
4161                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4162                         break;
4163                 case OP_AMD64_XOR_MEMBASE_IMM:
4164                         g_assert (amd64_is_imm32 (ins->inst_imm));
4165                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4166                         break;
4167
4168                 case OP_BREAK:
4169                         amd64_breakpoint (code);
4170                         break;
4171                 case OP_RELAXED_NOP:
4172                         x86_prefix (code, X86_REP_PREFIX);
4173                         x86_nop (code);
4174                         break;
4175                 case OP_HARD_NOP:
4176                         x86_nop (code);
4177                         break;
4178                 case OP_NOP:
4179                 case OP_DUMMY_USE:
4180                 case OP_DUMMY_STORE:
4181                 case OP_DUMMY_ICONST:
4182                 case OP_DUMMY_R8CONST:
4183                 case OP_NOT_REACHED:
4184                 case OP_NOT_NULL:
4185                         break;
4186                 case OP_IL_SEQ_POINT:
4187                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4188                         break;
4189                 case OP_SEQ_POINT: {
4190                         int i;
4191
4192                         /*
4193                          * Read from the single stepping trigger page. This will cause a
4194                          * SIGSEGV when single stepping is enabled.
4195                          * We do this _before_ the breakpoint, so single stepping after
4196                          * a breakpoint is hit will step to the next IL offset.
4197                          */
4198                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4199                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4200
4201                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4202                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4203                         }
4204
4205                         /*
4206                          * This is the address which is saved in seq points,
4207                          */
4208                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4209
4210                         if (cfg->compile_aot) {
4211                                 guint32 offset = code - cfg->native_code;
4212                                 guint32 val;
4213                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4214
4215                                 /* Load info var */
4216                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4217                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4218                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4219                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4220                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4221                         } else {
4222                                 /*
4223                                  * A placeholder for a possible breakpoint inserted by
4224                                  * mono_arch_set_breakpoint ().
4225                                  */
4226                                 for (i = 0; i < breakpoint_size; ++i)
4227                                         x86_nop (code);
4228                         }
4229                         /*
4230                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4231                          * to another IL offset.
4232                          */
4233                         x86_nop (code);
4234                         break;
4235                 }
4236                 case OP_ADDCC:
4237                 case OP_LADDCC:
4238                 case OP_LADD:
4239                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4240                         break;
4241                 case OP_ADC:
4242                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4243                         break;
4244                 case OP_ADD_IMM:
4245                 case OP_LADD_IMM:
4246                         g_assert (amd64_is_imm32 (ins->inst_imm));
4247                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4248                         break;
4249                 case OP_ADC_IMM:
4250                         g_assert (amd64_is_imm32 (ins->inst_imm));
4251                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4252                         break;
4253                 case OP_SUBCC:
4254                 case OP_LSUBCC:
4255                 case OP_LSUB:
4256                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4257                         break;
4258                 case OP_SBB:
4259                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4260                         break;
4261                 case OP_SUB_IMM:
4262                 case OP_LSUB_IMM:
4263                         g_assert (amd64_is_imm32 (ins->inst_imm));
4264                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4265                         break;
4266                 case OP_SBB_IMM:
4267                         g_assert (amd64_is_imm32 (ins->inst_imm));
4268                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4269                         break;
4270                 case OP_LAND:
4271                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4272                         break;
4273                 case OP_AND_IMM:
4274                 case OP_LAND_IMM:
4275                         g_assert (amd64_is_imm32 (ins->inst_imm));
4276                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4277                         break;
4278                 case OP_LMUL:
4279                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4280                         break;
4281                 case OP_MUL_IMM:
4282                 case OP_LMUL_IMM:
4283                 case OP_IMUL_IMM: {
4284                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4285
4286                         switch (ins->inst_imm) {
4287                         case 2:
4288                                 /* MOV r1, r2 */
4289                                 /* ADD r1, r1 */
4290                                 if (ins->dreg != ins->sreg1)
4291                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4292                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4293                                 break;
4294                         case 3:
4295                                 /* LEA r1, [r2 + r2*2] */
4296                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4297                                 break;
4298                         case 5:
4299                                 /* LEA r1, [r2 + r2*4] */
4300                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4301                                 break;
4302                         case 6:
4303                                 /* LEA r1, [r2 + r2*2] */
4304                                 /* ADD r1, r1          */
4305                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4306                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4307                                 break;
4308                         case 9:
4309                                 /* LEA r1, [r2 + r2*8] */
4310                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4311                                 break;
4312                         case 10:
4313                                 /* LEA r1, [r2 + r2*4] */
4314                                 /* ADD r1, r1          */
4315                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4316                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4317                                 break;
4318                         case 12:
4319                                 /* LEA r1, [r2 + r2*2] */
4320                                 /* SHL r1, 2           */
4321                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4322                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4323                                 break;
4324                         case 25:
4325                                 /* LEA r1, [r2 + r2*4] */
4326                                 /* LEA r1, [r1 + r1*4] */
4327                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4328                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4329                                 break;
4330                         case 100:
4331                                 /* LEA r1, [r2 + r2*4] */
4332                                 /* SHL r1, 2           */
4333                                 /* LEA r1, [r1 + r1*4] */
4334                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4335                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4336                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4337                                 break;
4338                         default:
4339                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4340                                 break;
4341                         }
4342                         break;
4343                 }
4344                 case OP_LDIV:
4345                 case OP_LREM:
4346 #if defined( __native_client_codegen__ )
4347                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4348                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4349 #endif
4350                         /* Regalloc magic makes the div/rem cases the same */
4351                         if (ins->sreg2 == AMD64_RDX) {
4352                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4353                                 amd64_cdq (code);
4354                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4355                         } else {
4356                                 amd64_cdq (code);
4357                                 amd64_div_reg (code, ins->sreg2, TRUE);
4358                         }
4359                         break;
4360                 case OP_LDIV_UN:
4361                 case OP_LREM_UN:
4362 #if defined( __native_client_codegen__ )
4363                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4364                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4365 #endif
4366                         if (ins->sreg2 == AMD64_RDX) {
4367                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4368                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4369                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4370                         } else {
4371                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4372                                 amd64_div_reg (code, ins->sreg2, FALSE);
4373                         }
4374                         break;
4375                 case OP_IDIV:
4376                 case OP_IREM:
4377 #if defined( __native_client_codegen__ )
4378                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4379                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4380 #endif
4381                         if (ins->sreg2 == AMD64_RDX) {
4382                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4383                                 amd64_cdq_size (code, 4);
4384                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4385                         } else {
4386                                 amd64_cdq_size (code, 4);
4387                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4388                         }
4389                         break;
4390                 case OP_IDIV_UN:
4391                 case OP_IREM_UN:
4392 #if defined( __native_client_codegen__ )
4393                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4394                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4395 #endif
4396                         if (ins->sreg2 == AMD64_RDX) {
4397                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4398                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4399                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4400                         } else {
4401                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4402                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4403                         }
4404                         break;
4405                 case OP_LMUL_OVF:
4406                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4407                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4408                         break;
4409                 case OP_LOR:
4410                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4411                         break;
4412                 case OP_OR_IMM:
4413                 case OP_LOR_IMM:
4414                         g_assert (amd64_is_imm32 (ins->inst_imm));
4415                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4416                         break;
4417                 case OP_LXOR:
4418                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4419                         break;
4420                 case OP_XOR_IMM:
4421                 case OP_LXOR_IMM:
4422                         g_assert (amd64_is_imm32 (ins->inst_imm));
4423                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4424                         break;
4425                 case OP_LSHL:
4426                         g_assert (ins->sreg2 == AMD64_RCX);
4427                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4428                         break;
4429                 case OP_LSHR:
4430                         g_assert (ins->sreg2 == AMD64_RCX);
4431                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4432                         break;
4433                 case OP_SHR_IMM:
4434                         g_assert (amd64_is_imm32 (ins->inst_imm));
4435                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4436                         break;
4437                 case OP_LSHR_IMM:
4438                         g_assert (amd64_is_imm32 (ins->inst_imm));
4439                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4440                         break;
4441                 case OP_SHR_UN_IMM:
4442                         g_assert (amd64_is_imm32 (ins->inst_imm));
4443                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4444                         break;
4445                 case OP_LSHR_UN_IMM:
4446                         g_assert (amd64_is_imm32 (ins->inst_imm));
4447                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4448                         break;
4449                 case OP_LSHR_UN:
4450                         g_assert (ins->sreg2 == AMD64_RCX);
4451                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4452                         break;
4453                 case OP_SHL_IMM:
4454                         g_assert (amd64_is_imm32 (ins->inst_imm));
4455                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4456                         break;
4457                 case OP_LSHL_IMM:
4458                         g_assert (amd64_is_imm32 (ins->inst_imm));
4459                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4460                         break;
4461
4462                 case OP_IADDCC:
4463                 case OP_IADD:
4464                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4465                         break;
4466                 case OP_IADC:
4467                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4468                         break;
4469                 case OP_IADD_IMM:
4470                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4471                         break;
4472                 case OP_IADC_IMM:
4473                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4474                         break;
4475                 case OP_ISUBCC:
4476                 case OP_ISUB:
4477                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4478                         break;
4479                 case OP_ISBB:
4480                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4481                         break;
4482                 case OP_ISUB_IMM:
4483                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4484                         break;
4485                 case OP_ISBB_IMM:
4486                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4487                         break;
4488                 case OP_IAND:
4489                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4490                         break;
4491                 case OP_IAND_IMM:
4492                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4493                         break;
4494                 case OP_IOR:
4495                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4496                         break;
4497                 case OP_IOR_IMM:
4498                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4499                         break;
4500                 case OP_IXOR:
4501                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4502                         break;
4503                 case OP_IXOR_IMM:
4504                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4505                         break;
4506                 case OP_INEG:
4507                         amd64_neg_reg_size (code, ins->sreg1, 4);
4508                         break;
4509                 case OP_INOT:
4510                         amd64_not_reg_size (code, ins->sreg1, 4);
4511                         break;
4512                 case OP_ISHL:
4513                         g_assert (ins->sreg2 == AMD64_RCX);
4514                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4515                         break;
4516                 case OP_ISHR:
4517                         g_assert (ins->sreg2 == AMD64_RCX);
4518                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4519                         break;
4520                 case OP_ISHR_IMM:
4521                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4522                         break;
4523                 case OP_ISHR_UN_IMM:
4524                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4525                         break;
4526                 case OP_ISHR_UN:
4527                         g_assert (ins->sreg2 == AMD64_RCX);
4528                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4529                         break;
4530                 case OP_ISHL_IMM:
4531                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4532                         break;
4533                 case OP_IMUL:
4534                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4535                         break;
4536                 case OP_IMUL_OVF:
4537                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4538                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4539                         break;
4540                 case OP_IMUL_OVF_UN:
4541                 case OP_LMUL_OVF_UN: {
4542                         /* the mul operation and the exception check should most likely be split */
4543                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4544                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4545                         /*g_assert (ins->sreg2 == X86_EAX);
4546                         g_assert (ins->dreg == X86_EAX);*/
4547                         if (ins->sreg2 == X86_EAX) {
4548                                 non_eax_reg = ins->sreg1;
4549                         } else if (ins->sreg1 == X86_EAX) {
4550                                 non_eax_reg = ins->sreg2;
4551                         } else {
4552                                 /* no need to save since we're going to store to it anyway */
4553                                 if (ins->dreg != X86_EAX) {
4554                                         saved_eax = TRUE;
4555                                         amd64_push_reg (code, X86_EAX);
4556                                 }
4557                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4558                                 non_eax_reg = ins->sreg2;
4559                         }
4560                         if (ins->dreg == X86_EDX) {
4561                                 if (!saved_eax) {
4562                                         saved_eax = TRUE;
4563                                         amd64_push_reg (code, X86_EAX);
4564                                 }
4565                         } else {
4566                                 saved_edx = TRUE;
4567                                 amd64_push_reg (code, X86_EDX);
4568                         }
4569                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4570                         /* save before the check since pop and mov don't change the flags */
4571                         if (ins->dreg != X86_EAX)
4572                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4573                         if (saved_edx)
4574                                 amd64_pop_reg (code, X86_EDX);
4575                         if (saved_eax)
4576                                 amd64_pop_reg (code, X86_EAX);
4577                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4578                         break;
4579                 }
4580                 case OP_ICOMPARE:
4581                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4582                         break;
4583                 case OP_ICOMPARE_IMM:
4584                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4585                         break;
4586                 case OP_IBEQ:
4587                 case OP_IBLT:
4588                 case OP_IBGT:
4589                 case OP_IBGE:
4590                 case OP_IBLE:
4591                 case OP_LBEQ:
4592                 case OP_LBLT:
4593                 case OP_LBGT:
4594                 case OP_LBGE:
4595                 case OP_LBLE:
4596                 case OP_IBNE_UN:
4597                 case OP_IBLT_UN:
4598                 case OP_IBGT_UN:
4599                 case OP_IBGE_UN:
4600                 case OP_IBLE_UN:
4601                 case OP_LBNE_UN:
4602                 case OP_LBLT_UN:
4603                 case OP_LBGT_UN:
4604                 case OP_LBGE_UN:
4605                 case OP_LBLE_UN:
4606                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4607                         break;
4608
4609                 case OP_CMOV_IEQ:
4610                 case OP_CMOV_IGE:
4611                 case OP_CMOV_IGT:
4612                 case OP_CMOV_ILE:
4613                 case OP_CMOV_ILT:
4614                 case OP_CMOV_INE_UN:
4615                 case OP_CMOV_IGE_UN:
4616                 case OP_CMOV_IGT_UN:
4617                 case OP_CMOV_ILE_UN:
4618                 case OP_CMOV_ILT_UN:
4619                 case OP_CMOV_LEQ:
4620                 case OP_CMOV_LGE:
4621                 case OP_CMOV_LGT:
4622                 case OP_CMOV_LLE:
4623                 case OP_CMOV_LLT:
4624                 case OP_CMOV_LNE_UN:
4625                 case OP_CMOV_LGE_UN:
4626                 case OP_CMOV_LGT_UN:
4627                 case OP_CMOV_LLE_UN:
4628                 case OP_CMOV_LLT_UN:
4629                         g_assert (ins->dreg == ins->sreg1);
4630                         /* This needs to operate on 64 bit values */
4631                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4632                         break;
4633
4634                 case OP_LNOT:
4635                         amd64_not_reg (code, ins->sreg1);
4636                         break;
4637                 case OP_LNEG:
4638                         amd64_neg_reg (code, ins->sreg1);
4639                         break;
4640
4641                 case OP_ICONST:
4642                 case OP_I8CONST:
4643                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4644                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4645                         else
4646                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4647                         break;
4648                 case OP_AOTCONST:
4649                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4650                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4651                         break;
4652                 case OP_JUMP_TABLE:
4653                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4654                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4655                         break;
4656                 case OP_MOVE:
4657                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4658                         break;
4659                 case OP_AMD64_SET_XMMREG_R4: {
4660                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4661                         break;
4662                 }
4663                 case OP_AMD64_SET_XMMREG_R8: {
4664                         if (ins->dreg != ins->sreg1)
4665                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4666                         break;
4667                 }
4668                 case OP_TAILCALL: {
4669                         MonoCallInst *call = (MonoCallInst*)ins;
4670                         int i, save_area_offset;
4671
4672                         g_assert (!cfg->method->save_lmf);
4673
4674                         /* Restore callee saved registers */
4675                         save_area_offset = cfg->arch.reg_save_area_offset;
4676                         for (i = 0; i < AMD64_NREG; ++i)
4677                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4678                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4679                                         save_area_offset += 8;
4680                                 }
4681
4682                         if (cfg->arch.omit_fp) {
4683                                 if (cfg->arch.stack_alloc_size)
4684                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4685                                 // FIXME:
4686                                 if (call->stack_usage)
4687                                         NOT_IMPLEMENTED;
4688                         } else {
4689                                 /* Copy arguments on the stack to our argument area */
4690                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4691                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4692                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4693                                 }
4694
4695                                 amd64_leave (code);
4696                         }
4697
4698                         offset = code - cfg->native_code;
4699                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4700                         if (cfg->compile_aot)
4701                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4702                         else
4703                                 amd64_set_reg_template (code, AMD64_R11);
4704                         amd64_jump_reg (code, AMD64_R11);
4705                         ins->flags |= MONO_INST_GC_CALLSITE;
4706                         ins->backend.pc_offset = code - cfg->native_code;
4707                         break;
4708                 }
4709                 case OP_CHECK_THIS:
4710                         /* ensure ins->sreg1 is not NULL */
4711                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4712                         break;
4713                 case OP_ARGLIST: {
4714                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4715                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4716                         break;
4717                 }
4718                 case OP_CALL:
4719                 case OP_FCALL:
4720                 case OP_LCALL:
4721                 case OP_VCALL:
4722                 case OP_VCALL2:
4723                 case OP_VOIDCALL:
4724                         call = (MonoCallInst*)ins;
4725                         /*
4726                          * The AMD64 ABI forces callers to know about varargs.
4727                          */
4728                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4729                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4730                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4731                                 /*
4732                                  * Since the unmanaged calling convention doesn't contain a
4733                                  * 'vararg' entry, we have to treat every pinvoke call as a
4734                                  * potential vararg call.
4735                                  */
4736                                 guint32 nregs, i;
4737                                 nregs = 0;
4738                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4739                                         if (call->used_fregs & (1 << i))
4740                                                 nregs ++;
4741                                 if (!nregs)
4742                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4743                                 else
4744                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4745                         }
4746
4747                         if (ins->flags & MONO_INST_HAS_METHOD)
4748                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4749                         else
4750                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4751                         ins->flags |= MONO_INST_GC_CALLSITE;
4752                         ins->backend.pc_offset = code - cfg->native_code;
4753                         code = emit_move_return_value (cfg, ins, code);
4754                         break;
4755                 case OP_FCALL_REG:
4756                 case OP_LCALL_REG:
4757                 case OP_VCALL_REG:
4758                 case OP_VCALL2_REG:
4759                 case OP_VOIDCALL_REG:
4760                 case OP_CALL_REG:
4761                         call = (MonoCallInst*)ins;
4762
4763                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4764                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4765                                 ins->sreg1 = AMD64_R11;
4766                         }
4767
4768                         /*
4769                          * The AMD64 ABI forces callers to know about varargs.
4770                          */
4771                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4772                                 if (ins->sreg1 == AMD64_RAX) {
4773                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4774                                         ins->sreg1 = AMD64_R11;
4775                                 }
4776                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4777                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4778                                 /*
4779                                  * Since the unmanaged calling convention doesn't contain a
4780                                  * 'vararg' entry, we have to treat every pinvoke call as a
4781                                  * potential vararg call.
4782                                  */
4783                                 guint32 nregs, i;
4784                                 nregs = 0;
4785                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4786                                         if (call->used_fregs & (1 << i))
4787                                                 nregs ++;
4788                                 if (ins->sreg1 == AMD64_RAX) {
4789                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4790                                         ins->sreg1 = AMD64_R11;
4791                                 }
4792                                 if (!nregs)
4793                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4794                                 else
4795                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4796                         }
4797
4798                         amd64_call_reg (code, ins->sreg1);
4799                         ins->flags |= MONO_INST_GC_CALLSITE;
4800                         ins->backend.pc_offset = code - cfg->native_code;
4801                         code = emit_move_return_value (cfg, ins, code);
4802                         break;
4803                 case OP_FCALL_MEMBASE:
4804                 case OP_LCALL_MEMBASE:
4805                 case OP_VCALL_MEMBASE:
4806                 case OP_VCALL2_MEMBASE:
4807                 case OP_VOIDCALL_MEMBASE:
4808                 case OP_CALL_MEMBASE:
4809                         call = (MonoCallInst*)ins;
4810
4811                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4812                         ins->flags |= MONO_INST_GC_CALLSITE;
4813                         ins->backend.pc_offset = code - cfg->native_code;
4814                         code = emit_move_return_value (cfg, ins, code);
4815                         break;
4816                 case OP_DYN_CALL: {
4817                         int i;
4818                         MonoInst *var = cfg->dyn_call_var;
4819
4820                         g_assert (var->opcode == OP_REGOFFSET);
4821
4822                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4823                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4824                         /* r10 = ftn */
4825                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4826
4827                         /* Save args buffer */
4828                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4829
4830                         /* Set argument registers */
4831                         for (i = 0; i < PARAM_REGS; ++i)
4832                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4833
4834                         /* Make the call */
4835                         amd64_call_reg (code, AMD64_R10);
4836
4837                         ins->flags |= MONO_INST_GC_CALLSITE;
4838                         ins->backend.pc_offset = code - cfg->native_code;
4839
4840                         /* Save result */
4841                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4842                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4843                         break;
4844                 }
4845                 case OP_AMD64_SAVE_SP_TO_LMF: {
4846                         MonoInst *lmf_var = cfg->lmf_var;
4847                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4848                         break;
4849                 }
4850                 case OP_X86_PUSH:
4851                         g_assert_not_reached ();
4852                         amd64_push_reg (code, ins->sreg1);
4853                         break;
4854                 case OP_X86_PUSH_IMM:
4855                         g_assert_not_reached ();
4856                         g_assert (amd64_is_imm32 (ins->inst_imm));
4857                         amd64_push_imm (code, ins->inst_imm);
4858                         break;
4859                 case OP_X86_PUSH_MEMBASE:
4860                         g_assert_not_reached ();
4861                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4862                         break;
4863                 case OP_X86_PUSH_OBJ: {
4864                         int size = ALIGN_TO (ins->inst_imm, 8);
4865
4866                         g_assert_not_reached ();
4867
4868                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4869                         amd64_push_reg (code, AMD64_RDI);
4870                         amd64_push_reg (code, AMD64_RSI);
4871                         amd64_push_reg (code, AMD64_RCX);
4872                         if (ins->inst_offset)
4873                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4874                         else
4875                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4876                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4877                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4878                         amd64_cld (code);
4879                         amd64_prefix (code, X86_REP_PREFIX);
4880                         amd64_movsd (code);
4881                         amd64_pop_reg (code, AMD64_RCX);
4882                         amd64_pop_reg (code, AMD64_RSI);
4883                         amd64_pop_reg (code, AMD64_RDI);
4884                         break;
4885                 }
4886                 case OP_X86_LEA:
4887                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4888                         break;
4889                 case OP_X86_LEA_MEMBASE:
4890                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4891                         break;
4892                 case OP_X86_XCHG:
4893                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4894                         break;
4895                 case OP_LOCALLOC:
4896                         /* keep alignment */
4897                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4898                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4899                         code = mono_emit_stack_alloc (cfg, code, ins);
4900                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4901                         if (cfg->param_area)
4902                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4903                         break;
4904                 case OP_LOCALLOC_IMM: {
4905                         guint32 size = ins->inst_imm;
4906                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4907
4908                         if (ins->flags & MONO_INST_INIT) {
4909                                 if (size < 64) {
4910                                         int i;
4911
4912                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4913                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4914
4915                                         for (i = 0; i < size; i += 8)
4916                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4917                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4918                                 } else {
4919                                         amd64_mov_reg_imm (code, ins->dreg, size);
4920                                         ins->sreg1 = ins->dreg;
4921
4922                                         code = mono_emit_stack_alloc (cfg, code, ins);
4923                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4924                                 }
4925                         } else {
4926                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4927                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4928                         }
4929                         if (cfg->param_area)
4930                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4931                         break;
4932                 }
4933                 case OP_THROW: {
4934                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4935                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4936                                              (gpointer)"mono_arch_throw_exception", FALSE);
4937                         ins->flags |= MONO_INST_GC_CALLSITE;
4938                         ins->backend.pc_offset = code - cfg->native_code;
4939                         break;
4940                 }
4941                 case OP_RETHROW: {
4942                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4943                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4944                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4945                         ins->flags |= MONO_INST_GC_CALLSITE;
4946                         ins->backend.pc_offset = code - cfg->native_code;
4947                         break;
4948                 }
4949                 case OP_CALL_HANDLER:
4950                         /* Align stack */
4951                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4952                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4953                         amd64_call_imm (code, 0);
4954                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4955                         /* Restore stack alignment */
4956                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4957                         break;
4958                 case OP_START_HANDLER: {
4959                         /* Even though we're saving RSP, use sizeof */
4960                         /* gpointer because spvar is of type IntPtr */
4961                         /* see: mono_create_spvar_for_region */
4962                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4963                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4964
4965                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4966                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4967                                 cfg->param_area) {
4968                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4969                         }
4970                         break;
4971                 }
4972                 case OP_ENDFINALLY: {
4973                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4974                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4975                         amd64_ret (code);
4976                         break;
4977                 }
4978                 case OP_ENDFILTER: {
4979                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4980                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4981                         /* The local allocator will put the result into RAX */
4982                         amd64_ret (code);
4983                         break;
4984                 }
4985
4986                 case OP_LABEL:
4987                         ins->inst_c0 = code - cfg->native_code;
4988                         break;
4989                 case OP_BR:
4990                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4991                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4992                         //break;
4993                                 if (ins->inst_target_bb->native_offset) {
4994                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4995                                 } else {
4996                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4997                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4998                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4999                                                 x86_jump8 (code, 0);
5000                                         else
5001                                                 x86_jump32 (code, 0);
5002                         }
5003                         break;
5004                 case OP_BR_REG:
5005                         amd64_jump_reg (code, ins->sreg1);
5006                         break;
5007                 case OP_ICNEQ:
5008                 case OP_ICGE:
5009                 case OP_ICLE:
5010                 case OP_ICGE_UN:
5011                 case OP_ICLE_UN:
5012
5013                 case OP_CEQ:
5014                 case OP_LCEQ:
5015                 case OP_ICEQ:
5016                 case OP_CLT:
5017                 case OP_LCLT:
5018                 case OP_ICLT:
5019                 case OP_CGT:
5020                 case OP_ICGT:
5021                 case OP_LCGT:
5022                 case OP_CLT_UN:
5023                 case OP_LCLT_UN:
5024                 case OP_ICLT_UN:
5025                 case OP_CGT_UN:
5026                 case OP_LCGT_UN:
5027                 case OP_ICGT_UN:
5028                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5029                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5030                         break;
5031                 case OP_COND_EXC_EQ:
5032                 case OP_COND_EXC_NE_UN:
5033                 case OP_COND_EXC_LT:
5034                 case OP_COND_EXC_LT_UN:
5035                 case OP_COND_EXC_GT:
5036                 case OP_COND_EXC_GT_UN:
5037                 case OP_COND_EXC_GE:
5038                 case OP_COND_EXC_GE_UN:
5039                 case OP_COND_EXC_LE:
5040                 case OP_COND_EXC_LE_UN:
5041                 case OP_COND_EXC_IEQ:
5042                 case OP_COND_EXC_INE_UN:
5043                 case OP_COND_EXC_ILT:
5044                 case OP_COND_EXC_ILT_UN:
5045                 case OP_COND_EXC_IGT:
5046                 case OP_COND_EXC_IGT_UN:
5047                 case OP_COND_EXC_IGE:
5048                 case OP_COND_EXC_IGE_UN:
5049                 case OP_COND_EXC_ILE:
5050                 case OP_COND_EXC_ILE_UN:
5051                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5052                         break;
5053                 case OP_COND_EXC_OV:
5054                 case OP_COND_EXC_NO:
5055                 case OP_COND_EXC_C:
5056                 case OP_COND_EXC_NC:
5057                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5058                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5059                         break;
5060                 case OP_COND_EXC_IOV:
5061                 case OP_COND_EXC_INO:
5062                 case OP_COND_EXC_IC:
5063                 case OP_COND_EXC_INC:
5064                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5065                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5066                         break;
5067
5068                 /* floating point opcodes */
5069                 case OP_R8CONST: {
5070                         double d = *(double *)ins->inst_p0;
5071
5072                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5073                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5074                         }
5075                         else {
5076                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5077                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5078                         }
5079                         break;
5080                 }
5081                 case OP_R4CONST: {
5082                         float f = *(float *)ins->inst_p0;
5083
5084                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5085                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5086                         }
5087                         else {
5088                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5089                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5090                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5091                         }
5092                         break;
5093                 }
5094                 case OP_STORER8_MEMBASE_REG:
5095                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5096                         break;
5097                 case OP_LOADR8_MEMBASE:
5098                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5099                         break;
5100                 case OP_STORER4_MEMBASE_REG:
5101                         /* This requires a double->single conversion */
5102                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5103                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5104                         break;
5105                 case OP_LOADR4_MEMBASE:
5106                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5107                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5108                         break;
5109                 case OP_ICONV_TO_R4:
5110                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5111                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5112                         break;
5113                 case OP_ICONV_TO_R8:
5114                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5115                         break;
5116                 case OP_LCONV_TO_R4:
5117                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5118                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5119                         break;
5120                 case OP_LCONV_TO_R8:
5121                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5122                         break;
5123                 case OP_FCONV_TO_R4:
5124                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5125                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5126                         break;
5127                 case OP_FCONV_TO_I1:
5128                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5129                         break;
5130                 case OP_FCONV_TO_U1:
5131                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5132                         break;
5133                 case OP_FCONV_TO_I2:
5134                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5135                         break;
5136                 case OP_FCONV_TO_U2:
5137                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5138                         break;
5139                 case OP_FCONV_TO_U4:
5140                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5141                         break;
5142                 case OP_FCONV_TO_I4:
5143                 case OP_FCONV_TO_I:
5144                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5145                         break;
5146                 case OP_FCONV_TO_I8:
5147                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5148                         break;
5149                 case OP_LCONV_TO_R_UN: {
5150                         guint8 *br [2];
5151
5152                         /* Based on gcc code */
5153                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5154                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5155
5156                         /* Positive case */
5157                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5158                         br [1] = code; x86_jump8 (code, 0);
5159                         amd64_patch (br [0], code);
5160
5161                         /* Negative case */
5162                         /* Save to the red zone */
5163                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5164                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5165                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5166                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5167                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5168                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5169                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5170                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5171                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5172                         /* Restore */
5173                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5174                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5175                         amd64_patch (br [1], code);
5176                         break;
5177                 }
5178                 case OP_LCONV_TO_OVF_U4:
5179                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5180                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5181                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5182                         break;
5183                 case OP_LCONV_TO_OVF_I4_UN:
5184                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5185                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5186                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5187                         break;
5188                 case OP_FMOVE:
5189                         if (ins->dreg != ins->sreg1)
5190                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5191                         break;
5192                 case OP_FADD:
5193                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5194                         break;
5195                 case OP_FSUB:
5196                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5197                         break;
5198                 case OP_FMUL:
5199                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5200                         break;
5201                 case OP_FDIV:
5202                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5203                         break;
5204                 case OP_FNEG: {
5205                         static double r8_0 = -0.0;
5206
5207                         g_assert (ins->sreg1 == ins->dreg);
5208
5209                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5210                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5211                         break;
5212                 }
5213                 case OP_SIN:
5214                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5215                         break;
5216                 case OP_COS:
5217                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5218                         break;
5219                 case OP_ABS: {
5220                         static guint64 d = 0x7fffffffffffffffUL;
5221
5222                         g_assert (ins->sreg1 == ins->dreg);
5223
5224                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5225                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5226                         break;
5227                 }
5228                 case OP_SQRT:
5229                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5230                         break;
5231                 case OP_IMIN:
5232                         g_assert (cfg->opt & MONO_OPT_CMOV);
5233                         g_assert (ins->dreg == ins->sreg1);
5234                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5235                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5236                         break;
5237                 case OP_IMIN_UN:
5238                         g_assert (cfg->opt & MONO_OPT_CMOV);
5239                         g_assert (ins->dreg == ins->sreg1);
5240                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5241                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5242                         break;
5243                 case OP_IMAX:
5244                         g_assert (cfg->opt & MONO_OPT_CMOV);
5245                         g_assert (ins->dreg == ins->sreg1);
5246                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5247                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5248                         break;
5249                 case OP_IMAX_UN:
5250                         g_assert (cfg->opt & MONO_OPT_CMOV);
5251                         g_assert (ins->dreg == ins->sreg1);
5252                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5253                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5254                         break;
5255                 case OP_LMIN:
5256                         g_assert (cfg->opt & MONO_OPT_CMOV);
5257                         g_assert (ins->dreg == ins->sreg1);
5258                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5259                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5260                         break;
5261                 case OP_LMIN_UN:
5262                         g_assert (cfg->opt & MONO_OPT_CMOV);
5263                         g_assert (ins->dreg == ins->sreg1);
5264                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5265                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5266                         break;
5267                 case OP_LMAX:
5268                         g_assert (cfg->opt & MONO_OPT_CMOV);
5269                         g_assert (ins->dreg == ins->sreg1);
5270                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5271                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5272                         break;
5273                 case OP_LMAX_UN:
5274                         g_assert (cfg->opt & MONO_OPT_CMOV);
5275                         g_assert (ins->dreg == ins->sreg1);
5276                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5277                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5278                         break;
5279                 case OP_X86_FPOP:
5280                         break;
5281                 case OP_FCOMPARE:
5282                         /*
5283                          * The two arguments are swapped because the fbranch instructions
5284                          * depend on this for the non-sse case to work.
5285                          */
5286                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5287                         break;
5288                 case OP_FCNEQ:
5289                 case OP_FCEQ: {
5290                         /* zeroing the register at the start results in
5291                          * shorter and faster code (we can also remove the widening op)
5292                          */
5293                         guchar *unordered_check;
5294                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5295                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5296                         unordered_check = code;
5297                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5298
5299                         if (ins->opcode == OP_FCEQ) {
5300                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5301                                 amd64_patch (unordered_check, code);
5302                         } else {
5303                                 guchar *jump_to_end;
5304                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5305                                 jump_to_end = code;
5306                                 x86_jump8 (code, 0);
5307                                 amd64_patch (unordered_check, code);
5308                                 amd64_inc_reg (code, ins->dreg);
5309                                 amd64_patch (jump_to_end, code);
5310                         }
5311                         break;
5312                 }
5313                 case OP_FCLT:
5314                 case OP_FCLT_UN:
5315                         /* zeroing the register at the start results in
5316                          * shorter and faster code (we can also remove the widening op)
5317                          */
5318                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5319                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5320                         if (ins->opcode == OP_FCLT_UN) {
5321                                 guchar *unordered_check = code;
5322                                 guchar *jump_to_end;
5323                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5324                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5325                                 jump_to_end = code;
5326                                 x86_jump8 (code, 0);
5327                                 amd64_patch (unordered_check, code);
5328                                 amd64_inc_reg (code, ins->dreg);
5329                                 amd64_patch (jump_to_end, code);
5330                         } else {
5331                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5332                         }
5333                         break;
5334                 case OP_FCLE: {
5335                         guchar *unordered_check;
5336                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5337                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5338                         unordered_check = code;
5339                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5340                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5341                         amd64_patch (unordered_check, code);
5342                         break;
5343                 }
5344                 case OP_FCGT:
5345                 case OP_FCGT_UN: {
5346                         /* zeroing the register at the start results in
5347                          * shorter and faster code (we can also remove the widening op)
5348                          */
5349                         guchar *unordered_check;
5350                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5351                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5352                         if (ins->opcode == OP_FCGT) {
5353                                 unordered_check = code;
5354                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5355                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5356                                 amd64_patch (unordered_check, code);
5357                         } else {
5358                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5359                         }
5360                         break;
5361                 }
5362                 case OP_FCGE: {
5363                         guchar *unordered_check;
5364                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5365                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5366                         unordered_check = code;
5367                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5368                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5369                         amd64_patch (unordered_check, code);
5370                         break;
5371                 }
5372
5373                 case OP_FCLT_MEMBASE:
5374                 case OP_FCGT_MEMBASE:
5375                 case OP_FCLT_UN_MEMBASE:
5376                 case OP_FCGT_UN_MEMBASE:
5377                 case OP_FCEQ_MEMBASE: {
5378                         guchar *unordered_check, *jump_to_end;
5379                         int x86_cond;
5380
5381                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5382                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5383
5384                         switch (ins->opcode) {
5385                         case OP_FCEQ_MEMBASE:
5386                                 x86_cond = X86_CC_EQ;
5387                                 break;
5388                         case OP_FCLT_MEMBASE:
5389                         case OP_FCLT_UN_MEMBASE:
5390                                 x86_cond = X86_CC_LT;
5391                                 break;
5392                         case OP_FCGT_MEMBASE:
5393                         case OP_FCGT_UN_MEMBASE:
5394                                 x86_cond = X86_CC_GT;
5395                                 break;
5396                         default:
5397                                 g_assert_not_reached ();
5398                         }
5399
5400                         unordered_check = code;
5401                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5402                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5403
5404                         switch (ins->opcode) {
5405                         case OP_FCEQ_MEMBASE:
5406                         case OP_FCLT_MEMBASE:
5407                         case OP_FCGT_MEMBASE:
5408                                 amd64_patch (unordered_check, code);
5409                                 break;
5410                         case OP_FCLT_UN_MEMBASE:
5411                         case OP_FCGT_UN_MEMBASE:
5412                                 jump_to_end = code;
5413                                 x86_jump8 (code, 0);
5414                                 amd64_patch (unordered_check, code);
5415                                 amd64_inc_reg (code, ins->dreg);
5416                                 amd64_patch (jump_to_end, code);
5417                                 break;
5418                         default:
5419                                 break;
5420                         }
5421                         break;
5422                 }
5423                 case OP_FBEQ: {
5424                         guchar *jump = code;
5425                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5426                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5427                         amd64_patch (jump, code);
5428                         break;
5429                 }
5430                 case OP_FBNE_UN:
5431                         /* Branch if C013 != 100 */
5432                         /* branch if !ZF or (PF|CF) */
5433                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5434                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5435                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5436                         break;
5437                 case OP_FBLT:
5438                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5439                         break;
5440                 case OP_FBLT_UN:
5441                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5442                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5443                         break;
5444                 case OP_FBGT:
5445                 case OP_FBGT_UN:
5446                         if (ins->opcode == OP_FBGT) {
5447                                 guchar *br1;
5448
5449                                 /* skip branch if C1=1 */
5450                                 br1 = code;
5451                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5452                                 /* branch if (C0 | C3) = 1 */
5453                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5454                                 amd64_patch (br1, code);
5455                                 break;
5456                         } else {
5457                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5458                         }
5459                         break;
5460                 case OP_FBGE: {
5461                         /* Branch if C013 == 100 or 001 */
5462                         guchar *br1;
5463
5464                         /* skip branch if C1=1 */
5465                         br1 = code;
5466                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5467                         /* branch if (C0 | C3) = 1 */
5468                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5469                         amd64_patch (br1, code);
5470                         break;
5471                 }
5472                 case OP_FBGE_UN:
5473                         /* Branch if C013 == 000 */
5474                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5475                         break;
5476                 case OP_FBLE: {
5477                         /* Branch if C013=000 or 100 */
5478                         guchar *br1;
5479
5480                         /* skip branch if C1=1 */
5481                         br1 = code;
5482                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5483                         /* branch if C0=0 */
5484                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5485                         amd64_patch (br1, code);
5486                         break;
5487                 }
5488                 case OP_FBLE_UN:
5489                         /* Branch if C013 != 001 */
5490                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5491                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5492                         break;
5493                 case OP_CKFINITE:
5494                         /* Transfer value to the fp stack */
5495                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5496                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5497                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5498
5499                         amd64_push_reg (code, AMD64_RAX);
5500                         amd64_fxam (code);
5501                         amd64_fnstsw (code);
5502                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5503                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5504                         amd64_pop_reg (code, AMD64_RAX);
5505                         amd64_fstp (code, 0);
5506                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5507                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5508                         break;
5509                 case OP_TLS_GET: {
5510                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5511                         break;
5512                 }
5513                 case OP_TLS_GET_REG:
5514                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5515                         break;
5516                 case OP_TLS_SET: {
5517                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5518                         break;
5519                 }
5520                 case OP_TLS_SET_REG: {
5521                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5522                         break;
5523                 }
5524                 case OP_MEMORY_BARRIER: {
5525                         switch (ins->backend.memory_barrier_kind) {
5526                         case StoreLoadBarrier:
5527                         case FullBarrier:
5528                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5529                                 x86_prefix (code, X86_LOCK_PREFIX);
5530                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5531                                 break;
5532                         }
5533                         break;
5534                 }
5535                 case OP_ATOMIC_ADD_I4:
5536                 case OP_ATOMIC_ADD_I8: {
5537                         int dreg = ins->dreg;
5538                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5539
5540                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5541                                 dreg = AMD64_R11;
5542
5543                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5544                         amd64_prefix (code, X86_LOCK_PREFIX);
5545                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5546                         /* dreg contains the old value, add with sreg2 value */
5547                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5548
5549                         if (ins->dreg != dreg)
5550                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5551
5552                         break;
5553                 }
5554                 case OP_ATOMIC_EXCHANGE_I4:
5555                 case OP_ATOMIC_EXCHANGE_I8: {
5556                         guchar *br[2];
5557                         int sreg2 = ins->sreg2;
5558                         int breg = ins->inst_basereg;
5559                         guint32 size;
5560                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5561
5562                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5563                                 size = 8;
5564                         else
5565                                 size = 4;
5566
5567                         /*
5568                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5569                          * an explanation of how this works.
5570                          */
5571
5572                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5573                          * hack to overcome limits in x86 reg allocator
5574                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5575                          */
5576                         g_assert (ins->dreg == AMD64_RAX);
5577
5578                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5579                                 /* Highly unlikely, but possible */
5580                                 need_push = TRUE;
5581
5582                         /* The pushes invalidate rsp */
5583                         if ((breg == AMD64_RAX) || need_push) {
5584                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5585                                 breg = AMD64_R11;
5586                         }
5587
5588                         /* We need the EAX reg for the comparand */
5589                         if (ins->sreg2 == AMD64_RAX) {
5590                                 if (breg != AMD64_R11) {
5591                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5592                                         sreg2 = AMD64_R11;
5593                                 } else {
5594                                         g_assert (need_push);
5595                                         amd64_push_reg (code, AMD64_RDX);
5596                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5597                                         sreg2 = AMD64_RDX;
5598                                         rdx_pushed = TRUE;
5599                                 }
5600                         }
5601
5602                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5603
5604                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5605                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5606                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5607                         amd64_patch (br [1], br [0]);
5608
5609                         if (rdx_pushed)
5610                                 amd64_pop_reg (code, AMD64_RDX);
5611
5612                         break;
5613                 }
5614                 case OP_ATOMIC_CAS_I4:
5615                 case OP_ATOMIC_CAS_I8: {
5616                         guint32 size;
5617
5618                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5619                                 size = 8;
5620                         else
5621                                 size = 4;
5622
5623                         /*
5624                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5625                          * an explanation of how this works.
5626                          */
5627                         g_assert (ins->sreg3 == AMD64_RAX);
5628                         g_assert (ins->sreg1 != AMD64_RAX);
5629                         g_assert (ins->sreg1 != ins->sreg2);
5630
5631                         amd64_prefix (code, X86_LOCK_PREFIX);
5632                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5633
5634                         if (ins->dreg != AMD64_RAX)
5635                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5636                         break;
5637                 }
5638                 case OP_CARD_TABLE_WBARRIER: {
5639                         int ptr = ins->sreg1;
5640                         int value = ins->sreg2;
5641                         guchar *br = 0;
5642                         int nursery_shift, card_table_shift;
5643                         gpointer card_table_mask;
5644                         size_t nursery_size;
5645
5646                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5647                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5648                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5649
5650                         /*If either point to the stack we can simply avoid the WB. This happens due to
5651                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5652                          */
5653                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5654                                 continue;
5655
5656                         /*
5657                          * We need one register we can clobber, we choose EDX and make sreg1
5658                          * fixed EAX to work around limitations in the local register allocator.
5659                          * sreg2 might get allocated to EDX, but that is not a problem since
5660                          * we use it before clobbering EDX.
5661                          */
5662                         g_assert (ins->sreg1 == AMD64_RAX);
5663
5664                         /*
5665                          * This is the code we produce:
5666                          *
5667                          *   edx = value
5668                          *   edx >>= nursery_shift
5669                          *   cmp edx, (nursery_start >> nursery_shift)
5670                          *   jne done
5671                          *   edx = ptr
5672                          *   edx >>= card_table_shift
5673                          *   edx += cardtable
5674                          *   [edx] = 1
5675                          * done:
5676                          */
5677
5678                         if (mono_gc_card_table_nursery_check ()) {
5679                                 if (value != AMD64_RDX)
5680                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5681                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5682                                 if (shifted_nursery_start >> 31) {
5683                                         /*
5684                                          * The value we need to compare against is 64 bits, so we need
5685                                          * another spare register.  We use RBX, which we save and
5686                                          * restore.
5687                                          */
5688                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5689                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5690                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5691                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5692                                 } else {
5693                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5694                                 }
5695                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5696                         }
5697                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5698                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5699                         if (card_table_mask)
5700                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5701
5702                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5703                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5704
5705                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5706
5707                         if (mono_gc_card_table_nursery_check ())
5708                                 x86_patch (br, code);
5709                         break;
5710                 }
5711 #ifdef MONO_ARCH_SIMD_INTRINSICS
5712                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5713                 case OP_ADDPS:
5714                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5715                         break;
5716                 case OP_DIVPS:
5717                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5718                         break;
5719                 case OP_MULPS:
5720                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5721                         break;
5722                 case OP_SUBPS:
5723                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5724                         break;
5725                 case OP_MAXPS:
5726                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5727                         break;
5728                 case OP_MINPS:
5729                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5730                         break;
5731                 case OP_COMPPS:
5732                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5733                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5734                         break;
5735                 case OP_ANDPS:
5736                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5737                         break;
5738                 case OP_ANDNPS:
5739                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5740                         break;
5741                 case OP_ORPS:
5742                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5743                         break;
5744                 case OP_XORPS:
5745                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5746                         break;
5747                 case OP_SQRTPS:
5748                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5749                         break;
5750                 case OP_RSQRTPS:
5751                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5752                         break;
5753                 case OP_RCPPS:
5754                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5755                         break;
5756                 case OP_ADDSUBPS:
5757                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5758                         break;
5759                 case OP_HADDPS:
5760                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5761                         break;
5762                 case OP_HSUBPS:
5763                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5764                         break;
5765                 case OP_DUPPS_HIGH:
5766                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5767                         break;
5768                 case OP_DUPPS_LOW:
5769                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5770                         break;
5771
5772                 case OP_PSHUFLEW_HIGH:
5773                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5774                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5775                         break;
5776                 case OP_PSHUFLEW_LOW:
5777                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5778                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5779                         break;
5780                 case OP_PSHUFLED:
5781                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5782                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5783                         break;
5784                 case OP_SHUFPS:
5785                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5786                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5787                         break;
5788                 case OP_SHUFPD:
5789                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5790                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5791                         break;
5792
5793                 case OP_ADDPD:
5794                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5795                         break;
5796                 case OP_DIVPD:
5797                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5798                         break;
5799                 case OP_MULPD:
5800                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5801                         break;
5802                 case OP_SUBPD:
5803                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5804                         break;
5805                 case OP_MAXPD:
5806                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5807                         break;
5808                 case OP_MINPD:
5809                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5810                         break;
5811                 case OP_COMPPD:
5812                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5813                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5814                         break;
5815                 case OP_ANDPD:
5816                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5817                         break;
5818                 case OP_ANDNPD:
5819                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5820                         break;
5821                 case OP_ORPD:
5822                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5823                         break;
5824                 case OP_XORPD:
5825                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5826                         break;
5827                 case OP_SQRTPD:
5828                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5829                         break;
5830                 case OP_ADDSUBPD:
5831                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5832                         break;
5833                 case OP_HADDPD:
5834                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5835                         break;
5836                 case OP_HSUBPD:
5837                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5838                         break;
5839                 case OP_DUPPD:
5840                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5841                         break;
5842
5843                 case OP_EXTRACT_MASK:
5844                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5845                         break;
5846
5847                 case OP_PAND:
5848                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5849                         break;
5850                 case OP_POR:
5851                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5852                         break;
5853                 case OP_PXOR:
5854                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5855                         break;
5856
5857                 case OP_PADDB:
5858                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5859                         break;
5860                 case OP_PADDW:
5861                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5862                         break;
5863                 case OP_PADDD:
5864                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5865                         break;
5866                 case OP_PADDQ:
5867                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5868                         break;
5869
5870                 case OP_PSUBB:
5871                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5872                         break;
5873                 case OP_PSUBW:
5874                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5875                         break;
5876                 case OP_PSUBD:
5877                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5878                         break;
5879                 case OP_PSUBQ:
5880                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5881                         break;
5882
5883                 case OP_PMAXB_UN:
5884                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5885                         break;
5886                 case OP_PMAXW_UN:
5887                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5888                         break;
5889                 case OP_PMAXD_UN:
5890                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5891                         break;
5892
5893                 case OP_PMAXB:
5894                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5895                         break;
5896                 case OP_PMAXW:
5897                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5898                         break;
5899                 case OP_PMAXD:
5900                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5901                         break;
5902
5903                 case OP_PAVGB_UN:
5904                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5905                         break;
5906                 case OP_PAVGW_UN:
5907                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5908                         break;
5909
5910                 case OP_PMINB_UN:
5911                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_PMINW_UN:
5914                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5915                         break;
5916                 case OP_PMIND_UN:
5917                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919
5920                 case OP_PMINB:
5921                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_PMINW:
5924                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_PMIND:
5927                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929
5930                 case OP_PCMPEQB:
5931                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5932                         break;
5933                 case OP_PCMPEQW:
5934                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936                 case OP_PCMPEQD:
5937                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_PCMPEQQ:
5940                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942
5943                 case OP_PCMPGTB:
5944                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946                 case OP_PCMPGTW:
5947                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949                 case OP_PCMPGTD:
5950                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_PCMPGTQ:
5953                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955
5956                 case OP_PSUM_ABS_DIFF:
5957                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5958                         break;
5959
5960                 case OP_UNPACK_LOWB:
5961                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963                 case OP_UNPACK_LOWW:
5964                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5965                         break;
5966                 case OP_UNPACK_LOWD:
5967                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5968                         break;
5969                 case OP_UNPACK_LOWQ:
5970                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_UNPACK_LOWPS:
5973                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975                 case OP_UNPACK_LOWPD:
5976                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5977                         break;
5978
5979                 case OP_UNPACK_HIGHB:
5980                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_UNPACK_HIGHW:
5983                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985                 case OP_UNPACK_HIGHD:
5986                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5987                         break;
5988                 case OP_UNPACK_HIGHQ:
5989                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5990                         break;
5991                 case OP_UNPACK_HIGHPS:
5992                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994                 case OP_UNPACK_HIGHPD:
5995                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997
5998                 case OP_PACKW:
5999                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_PACKD:
6002                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004                 case OP_PACKW_UN:
6005                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007                 case OP_PACKD_UN:
6008                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6009                         break;
6010
6011                 case OP_PADDB_SAT_UN:
6012                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_PSUBB_SAT_UN:
6015                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017                 case OP_PADDW_SAT_UN:
6018                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020                 case OP_PSUBW_SAT_UN:
6021                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6022                         break;
6023
6024                 case OP_PADDB_SAT:
6025                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_PSUBB_SAT:
6028                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030                 case OP_PADDW_SAT:
6031                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6032                         break;
6033                 case OP_PSUBW_SAT:
6034                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6035                         break;
6036
6037                 case OP_PMULW:
6038                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_PMULD:
6041                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043                 case OP_PMULQ:
6044                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6045                         break;
6046                 case OP_PMULW_HIGH_UN:
6047                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_PMULW_HIGH:
6050                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052
6053                 case OP_PSHRW:
6054                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6055                         break;
6056                 case OP_PSHRW_REG:
6057                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6058                         break;
6059
6060                 case OP_PSARW:
6061                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6062                         break;
6063                 case OP_PSARW_REG:
6064                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6065                         break;
6066
6067                 case OP_PSHLW:
6068                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6069                         break;
6070                 case OP_PSHLW_REG:
6071                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6072                         break;
6073
6074                 case OP_PSHRD:
6075                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6076                         break;
6077                 case OP_PSHRD_REG:
6078                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6079                         break;
6080
6081                 case OP_PSARD:
6082                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6083                         break;
6084                 case OP_PSARD_REG:
6085                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6086                         break;
6087
6088                 case OP_PSHLD:
6089                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6090                         break;
6091                 case OP_PSHLD_REG:
6092                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6093                         break;
6094
6095                 case OP_PSHRQ:
6096                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6097                         break;
6098                 case OP_PSHRQ_REG:
6099                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6100                         break;
6101
6102                 /*TODO: This is appart of the sse spec but not added
6103                 case OP_PSARQ:
6104                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6105                         break;
6106                 case OP_PSARQ_REG:
6107                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6108                         break;
6109                 */
6110
6111                 case OP_PSHLQ:
6112                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6113                         break;
6114                 case OP_PSHLQ_REG:
6115                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6116                         break;
6117                 case OP_CVTDQ2PD:
6118                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6119                         break;
6120                 case OP_CVTDQ2PS:
6121                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6122                         break;
6123                 case OP_CVTPD2DQ:
6124                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6125                         break;
6126                 case OP_CVTPD2PS:
6127                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6128                         break;
6129                 case OP_CVTPS2DQ:
6130                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6131                         break;
6132                 case OP_CVTPS2PD:
6133                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6134                         break;
6135                 case OP_CVTTPD2DQ:
6136                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6137                         break;
6138                 case OP_CVTTPS2DQ:
6139                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6140                         break;
6141
6142                 case OP_ICONV_TO_X:
6143                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6144                         break;
6145                 case OP_EXTRACT_I4:
6146                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6147                         break;
6148                 case OP_EXTRACT_I8:
6149                         if (ins->inst_c0) {
6150                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6151                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6152                         } else {
6153                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6154                         }
6155                         break;
6156                 case OP_EXTRACT_I1:
6157                 case OP_EXTRACT_U1:
6158                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6159                         if (ins->inst_c0)
6160                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6161                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6162                         break;
6163                 case OP_EXTRACT_I2:
6164                 case OP_EXTRACT_U2:
6165                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6166                         if (ins->inst_c0)
6167                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6168                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6169                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6170                         break;
6171                 case OP_EXTRACT_R8:
6172                         if (ins->inst_c0)
6173                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6174                         else
6175                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6176                         break;
6177                 case OP_INSERT_I2:
6178                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6179                         break;
6180                 case OP_EXTRACTX_U2:
6181                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6182                         break;
6183                 case OP_INSERTX_U1_SLOW:
6184                         /*sreg1 is the extracted ireg (scratch)
6185                         /sreg2 is the to be inserted ireg (scratch)
6186                         /dreg is the xreg to receive the value*/
6187
6188                         /*clear the bits from the extracted word*/
6189                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6190                         /*shift the value to insert if needed*/
6191                         if (ins->inst_c0 & 1)
6192                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6193                         /*join them together*/
6194                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6195                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6196                         break;
6197                 case OP_INSERTX_I4_SLOW:
6198                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6199                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6200                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6201                         break;
6202                 case OP_INSERTX_I8_SLOW:
6203                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6204                         if (ins->inst_c0)
6205                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6206                         else
6207                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6208                         break;
6209
6210                 case OP_INSERTX_R4_SLOW:
6211                         switch (ins->inst_c0) {
6212                         case 0:
6213                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6214                                 break;
6215                         case 1:
6216                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6217                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6218                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6219                                 break;
6220                         case 2:
6221                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6222                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6223                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6224                                 break;
6225                         case 3:
6226                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6227                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6228                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6229                                 break;
6230                         }
6231                         break;
6232                 case OP_INSERTX_R8_SLOW:
6233                         if (ins->inst_c0)
6234                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6235                         else
6236                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6237                         break;
6238                 case OP_STOREX_MEMBASE_REG:
6239                 case OP_STOREX_MEMBASE:
6240                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6241                         break;
6242                 case OP_LOADX_MEMBASE:
6243                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6244                         break;
6245                 case OP_LOADX_ALIGNED_MEMBASE:
6246                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6247                         break;
6248                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6249                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6250                         break;
6251                 case OP_STOREX_NTA_MEMBASE_REG:
6252                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6253                         break;
6254                 case OP_PREFETCH_MEMBASE:
6255                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6256                         break;
6257
6258                 case OP_XMOVE:
6259                         /*FIXME the peephole pass should have killed this*/
6260                         if (ins->dreg != ins->sreg1)
6261                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6262                         break;
6263                 case OP_XZERO:
6264                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6265                         break;
6266                 case OP_ICONV_TO_R8_RAW:
6267                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6268                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6269                         break;
6270
6271                 case OP_FCONV_TO_R8_X:
6272                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6273                         break;
6274
6275                 case OP_XCONV_R8_TO_I4:
6276                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6277                         switch (ins->backend.source_opcode) {
6278                         case OP_FCONV_TO_I1:
6279                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6280                                 break;
6281                         case OP_FCONV_TO_U1:
6282                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6283                                 break;
6284                         case OP_FCONV_TO_I2:
6285                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6286                                 break;
6287                         case OP_FCONV_TO_U2:
6288                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6289                                 break;
6290                         }
6291                         break;
6292
6293                 case OP_EXPAND_I2:
6294                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6295                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6296                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6297                         break;
6298                 case OP_EXPAND_I4:
6299                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6300                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6301                         break;
6302                 case OP_EXPAND_I8:
6303                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6304                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6305                         break;
6306                 case OP_EXPAND_R4:
6307                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6308                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6309                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6310                         break;
6311                 case OP_EXPAND_R8:
6312                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6313                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6314                         break;
6315 #endif
6316                 case OP_LIVERANGE_START: {
6317                         if (cfg->verbose_level > 1)
6318                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6319                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6320                         break;
6321                 }
6322                 case OP_LIVERANGE_END: {
6323                         if (cfg->verbose_level > 1)
6324                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6325                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6326                         break;
6327                 }
6328                 case OP_NACL_GC_SAFE_POINT: {
6329 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6330                         if (cfg->compile_aot)
6331                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6332                         else {
6333                                 guint8 *br [1];
6334
6335                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6336                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6337                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6338                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6339                                 amd64_patch (br[0], code);
6340                         }
6341 #endif
6342                         break;
6343                 }
6344                 case OP_GC_LIVENESS_DEF:
6345                 case OP_GC_LIVENESS_USE:
6346                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6347                         ins->backend.pc_offset = code - cfg->native_code;
6348                         break;
6349                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6350                         ins->backend.pc_offset = code - cfg->native_code;
6351                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6352                         break;
6353                 default:
6354                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6355                         g_assert_not_reached ();
6356                 }
6357
6358                 if ((code - cfg->native_code - offset) > max_len) {
6359 #if !defined(__native_client_codegen__)
6360                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6361                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6362                         g_assert_not_reached ();
6363 #endif
6364                 }
6365
6366                 last_ins = ins;
6367                 last_offset = offset;
6368         }
6369
6370         cfg->code_len = code - cfg->native_code;
6371 }
6372
6373 #endif /* DISABLE_JIT */
6374
6375 void
6376 mono_arch_register_lowlevel_calls (void)
6377 {
6378         /* The signature doesn't matter */
6379         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6380 }
6381
6382 void
6383 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6384 {
6385         MonoJumpInfo *patch_info;
6386         gboolean compile_aot = !run_cctors;
6387
6388         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6389                 unsigned char *ip = patch_info->ip.i + code;
6390                 unsigned char *target;
6391
6392                 if (compile_aot) {
6393                         switch (patch_info->type) {
6394                         case MONO_PATCH_INFO_BB:
6395                         case MONO_PATCH_INFO_LABEL:
6396                                 break;
6397                         default:
6398                                 /* No need to patch these */
6399                                 continue;
6400                         }
6401                 }
6402
6403                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6404
6405                 switch (patch_info->type) {
6406                 case MONO_PATCH_INFO_NONE:
6407                         continue;
6408                 case MONO_PATCH_INFO_METHOD_REL:
6409                 case MONO_PATCH_INFO_R8:
6410                 case MONO_PATCH_INFO_R4:
6411                         g_assert_not_reached ();
6412                         continue;
6413                 case MONO_PATCH_INFO_BB:
6414                         break;
6415                 default:
6416                         break;
6417                 }
6418
6419                 /*
6420                  * Debug code to help track down problems where the target of a near call is
6421                  * is not valid.
6422                  */
6423                 if (amd64_is_near_call (ip)) {
6424                         gint64 disp = (guint8*)target - (guint8*)ip;
6425
6426                         if (!amd64_is_imm32 (disp)) {
6427                                 printf ("TYPE: %d\n", patch_info->type);
6428                                 switch (patch_info->type) {
6429                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6430                                         printf ("V: %s\n", patch_info->data.name);
6431                                         break;
6432                                 case MONO_PATCH_INFO_METHOD_JUMP:
6433                                 case MONO_PATCH_INFO_METHOD:
6434                                         printf ("V: %s\n", patch_info->data.method->name);
6435                                         break;
6436                                 default:
6437                                         break;
6438                                 }
6439                         }
6440                 }
6441
6442                 amd64_patch (ip, (gpointer)target);
6443         }
6444 }
6445
6446 #ifndef DISABLE_JIT
6447
6448 static int
6449 get_max_epilog_size (MonoCompile *cfg)
6450 {
6451         int max_epilog_size = 16;
6452
6453         if (cfg->method->save_lmf)
6454                 max_epilog_size += 256;
6455
6456         if (mono_jit_trace_calls != NULL)
6457                 max_epilog_size += 50;
6458
6459         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6460                 max_epilog_size += 50;
6461
6462         max_epilog_size += (AMD64_NREG * 2);
6463
6464         return max_epilog_size;
6465 }
6466
6467 /*
6468  * This macro is used for testing whenever the unwinder works correctly at every point
6469  * where an async exception can happen.
6470  */
6471 /* This will generate a SIGSEGV at the given point in the code */
6472 #define async_exc_point(code) do { \
6473     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6474          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6475              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6476          cfg->arch.async_point_count ++; \
6477     } \
6478 } while (0)
6479
6480 guint8 *
6481 mono_arch_emit_prolog (MonoCompile *cfg)
6482 {
6483         MonoMethod *method = cfg->method;
6484         MonoBasicBlock *bb;
6485         MonoMethodSignature *sig;
6486         MonoInst *ins;
6487         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6488         guint8 *code;
6489         CallInfo *cinfo;
6490         MonoInst *lmf_var = cfg->lmf_var;
6491         gboolean args_clobbered = FALSE;
6492         gboolean trace = FALSE;
6493 #ifdef __native_client_codegen__
6494         guint alignment_check;
6495 #endif
6496
6497         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6498
6499 #if defined(__default_codegen__)
6500         code = cfg->native_code = g_malloc (cfg->code_size);
6501 #elif defined(__native_client_codegen__)
6502         /* native_code_alloc is not 32-byte aligned, native_code is. */
6503         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6504
6505         /* Align native_code to next nearest kNaclAlignment byte. */
6506         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6507         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6508
6509         code = cfg->native_code;
6510
6511         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6512         g_assert (alignment_check == 0);
6513 #endif
6514
6515         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6516                 trace = TRUE;
6517
6518         /* Amount of stack space allocated by register saving code */
6519         pos = 0;
6520
6521         /* Offset between RSP and the CFA */
6522         cfa_offset = 0;
6523
6524         /*
6525          * The prolog consists of the following parts:
6526          * FP present:
6527          * - push rbp, mov rbp, rsp
6528          * - save callee saved regs using pushes
6529          * - allocate frame
6530          * - save rgctx if needed
6531          * - save lmf if needed
6532          * FP not present:
6533          * - allocate frame
6534          * - save rgctx if needed
6535          * - save lmf if needed
6536          * - save callee saved regs using moves
6537          */
6538
6539         // CFA = sp + 8
6540         cfa_offset = 8;
6541         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6542         // IP saved at CFA - 8
6543         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6544         async_exc_point (code);
6545         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6546
6547         if (!cfg->arch.omit_fp) {
6548                 amd64_push_reg (code, AMD64_RBP);
6549                 cfa_offset += 8;
6550                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6551                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6552                 async_exc_point (code);
6553 #ifdef HOST_WIN32
6554                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6555 #endif
6556                 /* These are handled automatically by the stack marking code */
6557                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6558
6559                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6560                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6561                 async_exc_point (code);
6562 #ifdef HOST_WIN32
6563                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6564 #endif
6565         }
6566
6567         /* The param area is always at offset 0 from sp */
6568         /* This needs to be allocated here, since it has to come after the spill area */
6569         if (cfg->param_area) {
6570                 if (cfg->arch.omit_fp)
6571                         // FIXME:
6572                         g_assert_not_reached ();
6573                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6574         }
6575
6576         if (cfg->arch.omit_fp) {
6577                 /*
6578                  * On enter, the stack is misaligned by the pushing of the return
6579                  * address. It is either made aligned by the pushing of %rbp, or by
6580                  * this.
6581                  */
6582                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6583                 if ((alloc_size % 16) == 0) {
6584                         alloc_size += 8;
6585                         /* Mark the padding slot as NOREF */
6586                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6587                 }
6588         } else {
6589                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6590                 if (cfg->stack_offset != alloc_size) {
6591                         /* Mark the padding slot as NOREF */
6592                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6593                 }
6594                 cfg->arch.sp_fp_offset = alloc_size;
6595                 alloc_size -= pos;
6596         }
6597
6598         cfg->arch.stack_alloc_size = alloc_size;
6599
6600         /* Allocate stack frame */
6601         if (alloc_size) {
6602                 /* See mono_emit_stack_alloc */
6603 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6604                 guint32 remaining_size = alloc_size;
6605                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6606                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6607                 guint32 offset = code - cfg->native_code;
6608                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6609                         while (required_code_size >= (cfg->code_size - offset))
6610                                 cfg->code_size *= 2;
6611                         cfg->native_code = mono_realloc_native_code (cfg);
6612                         code = cfg->native_code + offset;
6613                         cfg->stat_code_reallocs++;
6614                 }
6615
6616                 while (remaining_size >= 0x1000) {
6617                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6618                         if (cfg->arch.omit_fp) {
6619                                 cfa_offset += 0x1000;
6620                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6621                         }
6622                         async_exc_point (code);
6623 #ifdef HOST_WIN32
6624                         if (cfg->arch.omit_fp)
6625                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6626 #endif
6627
6628                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6629                         remaining_size -= 0x1000;
6630                 }
6631                 if (remaining_size) {
6632                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6633                         if (cfg->arch.omit_fp) {
6634                                 cfa_offset += remaining_size;
6635                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6636                                 async_exc_point (code);
6637                         }
6638 #ifdef HOST_WIN32
6639                         if (cfg->arch.omit_fp)
6640                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6641 #endif
6642                 }
6643 #else
6644                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6645                 if (cfg->arch.omit_fp) {
6646                         cfa_offset += alloc_size;
6647                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6648                         async_exc_point (code);
6649                 }
6650 #endif
6651         }
6652
6653         /* Stack alignment check */
6654 #if 0
6655         {
6656                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6657                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6658                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6659                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6660                 amd64_breakpoint (code);
6661         }
6662 #endif
6663
6664         if (mini_get_debug_options ()->init_stacks) {
6665                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6666
6667                 /* Save registers to the red zone */
6668                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6669                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6670
6671                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6672                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6673                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6674
6675                 amd64_cld (code);
6676 #if defined(__default_codegen__)
6677                 amd64_prefix (code, X86_REP_PREFIX);
6678                 amd64_stosl (code);
6679 #elif defined(__native_client_codegen__)
6680                 /* NaCl stos pseudo-instruction */
6681                 amd64_codegen_pre (code);
6682                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6683                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6684                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6685                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6686                 amd64_prefix (code, X86_REP_PREFIX);
6687                 amd64_stosl (code);
6688                 amd64_codegen_post (code);
6689 #endif /* __native_client_codegen__ */
6690
6691                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6692                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6693         }
6694
6695         /* Save LMF */
6696         if (method->save_lmf)
6697                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6698
6699         /* Save callee saved registers */
6700         if (cfg->arch.omit_fp) {
6701                 save_area_offset = cfg->arch.reg_save_area_offset;
6702                 /* Save caller saved registers after sp is adjusted */
6703                 /* The registers are saved at the bottom of the frame */
6704                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6705         } else {
6706                 /* The registers are saved just below the saved rbp */
6707                 save_area_offset = cfg->arch.reg_save_area_offset;
6708         }
6709
6710         for (i = 0; i < AMD64_NREG; ++i) {
6711                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6712                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6713
6714                         if (cfg->arch.omit_fp) {
6715                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6716                                 /* These are handled automatically by the stack marking code */
6717                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6718                         } else {
6719                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6720                                 // FIXME: GC
6721                         }
6722
6723                         save_area_offset += 8;
6724                         async_exc_point (code);
6725                 }
6726         }
6727
6728         /* store runtime generic context */
6729         if (cfg->rgctx_var) {
6730                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6731                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6732
6733                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6734
6735                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6736                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6737         }
6738
6739         /* compute max_length in order to use short forward jumps */
6740         max_epilog_size = get_max_epilog_size (cfg);
6741         if (cfg->opt & MONO_OPT_BRANCH) {
6742                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6743                         MonoInst *ins;
6744                         int max_length = 0;
6745
6746                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6747                                 max_length += 6;
6748                         /* max alignment for loops */
6749                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6750                                 max_length += LOOP_ALIGNMENT;
6751 #ifdef __native_client_codegen__
6752                         /* max alignment for native client */
6753                         max_length += kNaClAlignment;
6754 #endif
6755
6756                         MONO_BB_FOR_EACH_INS (bb, ins) {
6757 #ifdef __native_client_codegen__
6758                                 {
6759                                         int space_in_block = kNaClAlignment -
6760                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6761                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6762                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6763                                                 max_length += space_in_block;
6764                                         }
6765                                 }
6766 #endif  /*__native_client_codegen__*/
6767                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6768                         }
6769
6770                         /* Take prolog and epilog instrumentation into account */
6771                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6772                                 max_length += max_epilog_size;
6773
6774                         bb->max_length = max_length;
6775                 }
6776         }
6777
6778         sig = mono_method_signature (method);
6779         pos = 0;
6780
6781         cinfo = cfg->arch.cinfo;
6782
6783         if (sig->ret->type != MONO_TYPE_VOID) {
6784                 /* Save volatile arguments to the stack */
6785                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6786                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6787         }
6788
6789         /* Keep this in sync with emit_load_volatile_arguments */
6790         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6791                 ArgInfo *ainfo = cinfo->args + i;
6792                 gint32 stack_offset;
6793                 MonoType *arg_type;
6794
6795                 ins = cfg->args [i];
6796
6797                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6798                         /* Unused arguments */
6799                         continue;
6800
6801                 if (sig->hasthis && (i == 0))
6802                         arg_type = &mono_defaults.object_class->byval_arg;
6803                 else
6804                         arg_type = sig->params [i - sig->hasthis];
6805
6806                 stack_offset = ainfo->offset + ARGS_OFFSET;
6807
6808                 if (cfg->globalra) {
6809                         /* All the other moves are done by the register allocator */
6810                         switch (ainfo->storage) {
6811                         case ArgInFloatSSEReg:
6812                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6813                                 break;
6814                         case ArgValuetypeInReg:
6815                                 for (quad = 0; quad < 2; quad ++) {
6816                                         switch (ainfo->pair_storage [quad]) {
6817                                         case ArgInIReg:
6818                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6819                                                 break;
6820                                         case ArgInFloatSSEReg:
6821                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6822                                                 break;
6823                                         case ArgInDoubleSSEReg:
6824                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6825                                                 break;
6826                                         case ArgNone:
6827                                                 break;
6828                                         default:
6829                                                 g_assert_not_reached ();
6830                                         }
6831                                 }
6832                                 break;
6833                         default:
6834                                 break;
6835                         }
6836
6837                         continue;
6838                 }
6839
6840                 /* Save volatile arguments to the stack */
6841                 if (ins->opcode != OP_REGVAR) {
6842                         switch (ainfo->storage) {
6843                         case ArgInIReg: {
6844                                 guint32 size = 8;
6845
6846                                 /* FIXME: I1 etc */
6847                                 /*
6848                                 if (stack_offset & 0x1)
6849                                         size = 1;
6850                                 else if (stack_offset & 0x2)
6851                                         size = 2;
6852                                 else if (stack_offset & 0x4)
6853                                         size = 4;
6854                                 else
6855                                         size = 8;
6856                                 */
6857                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6858
6859                                 /*
6860                                  * Save the original location of 'this',
6861                                  * get_generic_info_from_stack_frame () needs this to properly look up
6862                                  * the argument value during the handling of async exceptions.
6863                                  */
6864                                 if (ins == cfg->args [0]) {
6865                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6866                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6867                                 }
6868                                 break;
6869                         }
6870                         case ArgInFloatSSEReg:
6871                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6872                                 break;
6873                         case ArgInDoubleSSEReg:
6874                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6875                                 break;
6876                         case ArgValuetypeInReg:
6877                                 for (quad = 0; quad < 2; quad ++) {
6878                                         switch (ainfo->pair_storage [quad]) {
6879                                         case ArgInIReg:
6880                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6881                                                 break;
6882                                         case ArgInFloatSSEReg:
6883                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6884                                                 break;
6885                                         case ArgInDoubleSSEReg:
6886                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6887                                                 break;
6888                                         case ArgNone:
6889                                                 break;
6890                                         default:
6891                                                 g_assert_not_reached ();
6892                                         }
6893                                 }
6894                                 break;
6895                         case ArgValuetypeAddrInIReg:
6896                                 if (ainfo->pair_storage [0] == ArgInIReg)
6897                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6898                                 break;
6899                         default:
6900                                 break;
6901                         }
6902                 } else {
6903                         /* Argument allocated to (non-volatile) register */
6904                         switch (ainfo->storage) {
6905                         case ArgInIReg:
6906                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6907                                 break;
6908                         case ArgOnStack:
6909                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6910                                 break;
6911                         default:
6912                                 g_assert_not_reached ();
6913                         }
6914
6915                         if (ins == cfg->args [0]) {
6916                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6917                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6918                         }
6919                 }
6920         }
6921
6922         if (cfg->method->save_lmf)
6923                 args_clobbered = TRUE;
6924
6925         if (trace) {
6926                 args_clobbered = TRUE;
6927                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6928         }
6929
6930         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6931                 args_clobbered = TRUE;
6932
6933         /*
6934          * Optimize the common case of the first bblock making a call with the same
6935          * arguments as the method. This works because the arguments are still in their
6936          * original argument registers.
6937          * FIXME: Generalize this
6938          */
6939         if (!args_clobbered) {
6940                 MonoBasicBlock *first_bb = cfg->bb_entry;
6941                 MonoInst *next;
6942                 int filter = FILTER_IL_SEQ_POINT;
6943
6944                 next = mono_bb_first_inst (first_bb, filter);
6945                 if (!next && first_bb->next_bb) {
6946                         first_bb = first_bb->next_bb;
6947                         next = mono_bb_first_inst (first_bb, filter);
6948                 }
6949
6950                 if (first_bb->in_count > 1)
6951                         next = NULL;
6952
6953                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6954                         ArgInfo *ainfo = cinfo->args + i;
6955                         gboolean match = FALSE;
6956
6957                         ins = cfg->args [i];
6958                         if (ins->opcode != OP_REGVAR) {
6959                                 switch (ainfo->storage) {
6960                                 case ArgInIReg: {
6961                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6962                                                 if (next->dreg == ainfo->reg) {
6963                                                         NULLIFY_INS (next);
6964                                                         match = TRUE;
6965                                                 } else {
6966                                                         next->opcode = OP_MOVE;
6967                                                         next->sreg1 = ainfo->reg;
6968                                                         /* Only continue if the instruction doesn't change argument regs */
6969                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6970                                                                 match = TRUE;
6971                                                 }
6972                                         }
6973                                         break;
6974                                 }
6975                                 default:
6976                                         break;
6977                                 }
6978                         } else {
6979                                 /* Argument allocated to (non-volatile) register */
6980                                 switch (ainfo->storage) {
6981                                 case ArgInIReg:
6982                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6983                                                 NULLIFY_INS (next);
6984                                                 match = TRUE;
6985                                         }
6986                                         break;
6987                                 default:
6988                                         break;
6989                                 }
6990                         }
6991
6992                         if (match) {
6993                                 next = mono_inst_next (next, filter);
6994                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6995                                 if (!next)
6996                                         break;
6997                         }
6998                 }
6999         }
7000
7001         if (cfg->gen_seq_points_debug_data) {
7002                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7003
7004                 /* Initialize seq_point_info_var */
7005                 if (cfg->compile_aot) {
7006                         /* Initialize the variable from a GOT slot */
7007                         /* Same as OP_AOTCONST */
7008                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7009                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7010                         g_assert (info_var->opcode == OP_REGOFFSET);
7011                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7012                 }
7013
7014                 /* Initialize ss_trigger_page_var */
7015                 ins = cfg->arch.ss_trigger_page_var;
7016
7017                 g_assert (ins->opcode == OP_REGOFFSET);
7018
7019                 if (cfg->compile_aot) {
7020                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7021                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7022                 } else {
7023                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7024                 }
7025                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7026         }
7027
7028         cfg->code_len = code - cfg->native_code;
7029
7030         g_assert (cfg->code_len < cfg->code_size);
7031
7032         return code;
7033 }
7034
7035 void
7036 mono_arch_emit_epilog (MonoCompile *cfg)
7037 {
7038         MonoMethod *method = cfg->method;
7039         int quad, pos, i;
7040         guint8 *code;
7041         int max_epilog_size;
7042         CallInfo *cinfo;
7043         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7044         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7045
7046         max_epilog_size = get_max_epilog_size (cfg);
7047
7048         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7049                 cfg->code_size *= 2;
7050                 cfg->native_code = mono_realloc_native_code (cfg);
7051                 cfg->stat_code_reallocs++;
7052         }
7053         code = cfg->native_code + cfg->code_len;
7054
7055         cfg->has_unwind_info_for_epilog = TRUE;
7056
7057         /* Mark the start of the epilog */
7058         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7059
7060         /* Save the uwind state which is needed by the out-of-line code */
7061         mono_emit_unwind_op_remember_state (cfg, code);
7062
7063         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7064                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7065
7066         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7067         pos = 0;
7068
7069         if (method->save_lmf) {
7070                 /* check if we need to restore protection of the stack after a stack overflow */
7071                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7072                         guint8 *patch;
7073                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7074                         /* we load the value in a separate instruction: this mechanism may be
7075                          * used later as a safer way to do thread interruption
7076                          */
7077                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7078                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7079                         patch = code;
7080                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7081                         /* note that the call trampoline will preserve eax/edx */
7082                         x86_call_reg (code, X86_ECX);
7083                         x86_patch (patch, code);
7084                 } else {
7085                         /* FIXME: maybe save the jit tls in the prolog */
7086                 }
7087                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7088                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7089                 }
7090         }
7091
7092         /* Restore callee saved regs */
7093         for (i = 0; i < AMD64_NREG; ++i) {
7094                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7095                         /* Restore only used_int_regs, not arch.saved_iregs */
7096                         if (cfg->used_int_regs & (1 << i)) {
7097                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7098                                 mono_emit_unwind_op_same_value (cfg, code, i);
7099                                 async_exc_point (code);
7100                         }
7101                         save_area_offset += 8;
7102                 }
7103         }
7104
7105         /* Load returned vtypes into registers if needed */
7106         cinfo = cfg->arch.cinfo;
7107         if (cinfo->ret.storage == ArgValuetypeInReg) {
7108                 ArgInfo *ainfo = &cinfo->ret;
7109                 MonoInst *inst = cfg->ret;
7110
7111                 for (quad = 0; quad < 2; quad ++) {
7112                         switch (ainfo->pair_storage [quad]) {
7113                         case ArgInIReg:
7114                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7115                                 break;
7116                         case ArgInFloatSSEReg:
7117                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7118                                 break;
7119                         case ArgInDoubleSSEReg:
7120                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7121                                 break;
7122                         case ArgNone:
7123                                 break;
7124                         default:
7125                                 g_assert_not_reached ();
7126                         }
7127                 }
7128         }
7129
7130         if (cfg->arch.omit_fp) {
7131                 if (cfg->arch.stack_alloc_size) {
7132                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7133                 }
7134         } else {
7135                 amd64_leave (code);
7136                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7137         }
7138         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7139         async_exc_point (code);
7140         amd64_ret (code);
7141
7142         /* Restore the unwind state to be the same as before the epilog */
7143         mono_emit_unwind_op_restore_state (cfg, code);
7144
7145         cfg->code_len = code - cfg->native_code;
7146
7147         g_assert (cfg->code_len < cfg->code_size);
7148 }
7149
7150 void
7151 mono_arch_emit_exceptions (MonoCompile *cfg)
7152 {
7153         MonoJumpInfo *patch_info;
7154         int nthrows, i;
7155         guint8 *code;
7156         MonoClass *exc_classes [16];
7157         guint8 *exc_throw_start [16], *exc_throw_end [16];
7158         guint32 code_size = 0;
7159
7160         /* Compute needed space */
7161         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7162                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7163                         code_size += 40;
7164                 if (patch_info->type == MONO_PATCH_INFO_R8)
7165                         code_size += 8 + 15; /* sizeof (double) + alignment */
7166                 if (patch_info->type == MONO_PATCH_INFO_R4)
7167                         code_size += 4 + 15; /* sizeof (float) + alignment */
7168                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7169                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7170         }
7171
7172 #ifdef __native_client_codegen__
7173         /* Give us extra room on Native Client.  This could be   */
7174         /* more carefully calculated, but bundle alignment makes */
7175         /* it much trickier, so *2 like other places is good.    */
7176         code_size *= 2;
7177 #endif
7178
7179         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7180                 cfg->code_size *= 2;
7181                 cfg->native_code = mono_realloc_native_code (cfg);
7182                 cfg->stat_code_reallocs++;
7183         }
7184
7185         code = cfg->native_code + cfg->code_len;
7186
7187         /* add code to raise exceptions */
7188         nthrows = 0;
7189         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7190                 switch (patch_info->type) {
7191                 case MONO_PATCH_INFO_EXC: {
7192                         MonoClass *exc_class;
7193                         guint8 *buf, *buf2;
7194                         guint32 throw_ip;
7195
7196                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7197
7198                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7199                         g_assert (exc_class);
7200                         throw_ip = patch_info->ip.i;
7201
7202                         //x86_breakpoint (code);
7203                         /* Find a throw sequence for the same exception class */
7204                         for (i = 0; i < nthrows; ++i)
7205                                 if (exc_classes [i] == exc_class)
7206                                         break;
7207                         if (i < nthrows) {
7208                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7209                                 x86_jump_code (code, exc_throw_start [i]);
7210                                 patch_info->type = MONO_PATCH_INFO_NONE;
7211                         }
7212                         else {
7213                                 buf = code;
7214                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7215                                 buf2 = code;
7216
7217                                 if (nthrows < 16) {
7218                                         exc_classes [nthrows] = exc_class;
7219                                         exc_throw_start [nthrows] = code;
7220                                 }
7221                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7222
7223                                 patch_info->type = MONO_PATCH_INFO_NONE;
7224
7225                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7226
7227                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7228                                 while (buf < buf2)
7229                                         x86_nop (buf);
7230
7231                                 if (nthrows < 16) {
7232                                         exc_throw_end [nthrows] = code;
7233                                         nthrows ++;
7234                                 }
7235                         }
7236                         break;
7237                 }
7238                 default:
7239                         /* do nothing */
7240                         break;
7241                 }
7242                 g_assert(code < cfg->native_code + cfg->code_size);
7243         }
7244
7245         /* Handle relocations with RIP relative addressing */
7246         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7247                 gboolean remove = FALSE;
7248                 guint8 *orig_code = code;
7249
7250                 switch (patch_info->type) {
7251                 case MONO_PATCH_INFO_R8:
7252                 case MONO_PATCH_INFO_R4: {
7253                         guint8 *pos, *patch_pos;
7254                         guint32 target_pos;
7255
7256                         /* The SSE opcodes require a 16 byte alignment */
7257 #if defined(__default_codegen__)
7258                         code = (guint8*)ALIGN_TO (code, 16);
7259 #elif defined(__native_client_codegen__)
7260                         {
7261                                 /* Pad this out with HLT instructions  */
7262                                 /* or we can get garbage bytes emitted */
7263                                 /* which will fail validation          */
7264                                 guint8 *aligned_code;
7265                                 /* extra align to make room for  */
7266                                 /* mov/push below                      */
7267                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7268                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7269                                 /* The technique of hiding data in an  */
7270                                 /* instruction has a problem here: we  */
7271                                 /* need the data aligned to a 16-byte  */
7272                                 /* boundary but the instruction cannot */
7273                                 /* cross the bundle boundary. so only  */
7274                                 /* odd multiples of 16 can be used     */
7275                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7276                                         aligned_code += 16;
7277                                 }
7278                                 while (code < aligned_code) {
7279                                         *(code++) = 0xf4; /* hlt */
7280                                 }
7281                         }
7282 #endif
7283
7284                         pos = cfg->native_code + patch_info->ip.i;
7285                         if (IS_REX (pos [1])) {
7286                                 patch_pos = pos + 5;
7287                                 target_pos = code - pos - 9;
7288                         }
7289                         else {
7290                                 patch_pos = pos + 4;
7291                                 target_pos = code - pos - 8;
7292                         }
7293
7294                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7295 #ifdef __native_client_codegen__
7296                                 /* Hide 64-bit data in a         */
7297                                 /* "mov imm64, r11" instruction. */
7298                                 /* write it before the start of  */
7299                                 /* the data*/
7300                                 *(code-2) = 0x49; /* prefix      */
7301                                 *(code-1) = 0xbb; /* mov X, %r11 */
7302 #endif
7303                                 *(double*)code = *(double*)patch_info->data.target;
7304                                 code += sizeof (double);
7305                         } else {
7306 #ifdef __native_client_codegen__
7307                                 /* Hide 32-bit data in a        */
7308                                 /* "push imm32" instruction.    */
7309                                 *(code-1) = 0x68; /* push */
7310 #endif
7311                                 *(float*)code = *(float*)patch_info->data.target;
7312                                 code += sizeof (float);
7313                         }
7314
7315                         *(guint32*)(patch_pos) = target_pos;
7316
7317                         remove = TRUE;
7318                         break;
7319                 }
7320                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7321                         guint8 *pos;
7322
7323                         if (cfg->compile_aot)
7324                                 continue;
7325
7326                         /*loading is faster against aligned addresses.*/
7327                         code = (guint8*)ALIGN_TO (code, 8);
7328                         memset (orig_code, 0, code - orig_code);
7329
7330                         pos = cfg->native_code + patch_info->ip.i;
7331
7332                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7333                         if (IS_REX (pos [1]))
7334                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7335                         else
7336                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7337
7338                         *(gpointer*)code = (gpointer)patch_info->data.target;
7339                         code += sizeof (gpointer);
7340
7341                         remove = TRUE;
7342                         break;
7343                 }
7344                 default:
7345                         break;
7346                 }
7347
7348                 if (remove) {
7349                         if (patch_info == cfg->patch_info)
7350                                 cfg->patch_info = patch_info->next;
7351                         else {
7352                                 MonoJumpInfo *tmp;
7353
7354                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7355                                         ;
7356                                 tmp->next = patch_info->next;
7357                         }
7358                 }
7359                 g_assert (code < cfg->native_code + cfg->code_size);
7360         }
7361
7362         cfg->code_len = code - cfg->native_code;
7363
7364         g_assert (cfg->code_len < cfg->code_size);
7365
7366 }
7367
7368 #endif /* DISABLE_JIT */
7369
7370 void*
7371 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7372 {
7373         guchar *code = p;
7374         CallInfo *cinfo = NULL;
7375         MonoMethodSignature *sig;
7376         MonoInst *inst;
7377         int i, n, stack_area = 0;
7378
7379         /* Keep this in sync with mono_arch_get_argument_info */
7380
7381         if (enable_arguments) {
7382                 /* Allocate a new area on the stack and save arguments there */
7383                 sig = mono_method_signature (cfg->method);
7384
7385                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7386
7387                 n = sig->param_count + sig->hasthis;
7388
7389                 stack_area = ALIGN_TO (n * 8, 16);
7390
7391                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7392
7393                 for (i = 0; i < n; ++i) {
7394                         inst = cfg->args [i];
7395
7396                         if (inst->opcode == OP_REGVAR)
7397                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7398                         else {
7399                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7400                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7401                         }
7402                 }
7403         }
7404
7405         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7406         amd64_set_reg_template (code, AMD64_ARG_REG1);
7407         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7408         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7409
7410         if (enable_arguments)
7411                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7412
7413         return code;
7414 }
7415
7416 enum {
7417         SAVE_NONE,
7418         SAVE_STRUCT,
7419         SAVE_EAX,
7420         SAVE_EAX_EDX,
7421         SAVE_XMM
7422 };
7423
7424 void*
7425 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7426 {
7427         guchar *code = p;
7428         int save_mode = SAVE_NONE;
7429         MonoMethod *method = cfg->method;
7430         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7431         int i;
7432
7433         switch (ret_type->type) {
7434         case MONO_TYPE_VOID:
7435                 /* special case string .ctor icall */
7436                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7437                         save_mode = SAVE_EAX;
7438                 else
7439                         save_mode = SAVE_NONE;
7440                 break;
7441         case MONO_TYPE_I8:
7442         case MONO_TYPE_U8:
7443                 save_mode = SAVE_EAX;
7444                 break;
7445         case MONO_TYPE_R4:
7446         case MONO_TYPE_R8:
7447                 save_mode = SAVE_XMM;
7448                 break;
7449         case MONO_TYPE_GENERICINST:
7450                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7451                         save_mode = SAVE_EAX;
7452                         break;
7453                 }
7454                 /* Fall through */
7455         case MONO_TYPE_VALUETYPE:
7456                 save_mode = SAVE_STRUCT;
7457                 break;
7458         default:
7459                 save_mode = SAVE_EAX;
7460                 break;
7461         }
7462
7463         /* Save the result and copy it into the proper argument register */
7464         switch (save_mode) {
7465         case SAVE_EAX:
7466                 amd64_push_reg (code, AMD64_RAX);
7467                 /* Align stack */
7468                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7469                 if (enable_arguments)
7470                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7471                 break;
7472         case SAVE_STRUCT:
7473                 /* FIXME: */
7474                 if (enable_arguments)
7475                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7476                 break;
7477         case SAVE_XMM:
7478                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7479                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7480                 /* Align stack */
7481                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7482                 /*
7483                  * The result is already in the proper argument register so no copying
7484                  * needed.
7485                  */
7486                 break;
7487         case SAVE_NONE:
7488                 break;
7489         default:
7490                 g_assert_not_reached ();
7491         }
7492
7493         /* Set %al since this is a varargs call */
7494         if (save_mode == SAVE_XMM)
7495                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7496         else
7497                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7498
7499         if (preserve_argument_registers) {
7500                 for (i = 0; i < PARAM_REGS; ++i)
7501                         amd64_push_reg (code, param_regs [i]);
7502         }
7503
7504         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7505         amd64_set_reg_template (code, AMD64_ARG_REG1);
7506         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7507
7508         if (preserve_argument_registers) {
7509                 for (i = PARAM_REGS - 1; i >= 0; --i)
7510                         amd64_pop_reg (code, param_regs [i]);
7511         }
7512
7513         /* Restore result */
7514         switch (save_mode) {
7515         case SAVE_EAX:
7516                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7517                 amd64_pop_reg (code, AMD64_RAX);
7518                 break;
7519         case SAVE_STRUCT:
7520                 /* FIXME: */
7521                 break;
7522         case SAVE_XMM:
7523                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7524                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7525                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7526                 break;
7527         case SAVE_NONE:
7528                 break;
7529         default:
7530                 g_assert_not_reached ();
7531         }
7532
7533         return code;
7534 }
7535
7536 void
7537 mono_arch_flush_icache (guint8 *code, gint size)
7538 {
7539         /* Not needed */
7540 }
7541
7542 void
7543 mono_arch_flush_register_windows (void)
7544 {
7545 }
7546
7547 gboolean
7548 mono_arch_is_inst_imm (gint64 imm)
7549 {
7550         return amd64_is_imm32 (imm);
7551 }
7552
7553 /*
7554  * Determine whenever the trap whose info is in SIGINFO is caused by
7555  * integer overflow.
7556  */
7557 gboolean
7558 mono_arch_is_int_overflow (void *sigctx, void *info)
7559 {
7560         MonoContext ctx;
7561         guint8* rip;
7562         int reg;
7563         gint64 value;
7564
7565         mono_sigctx_to_monoctx (sigctx, &ctx);
7566
7567         rip = (guint8*)ctx.rip;
7568
7569         if (IS_REX (rip [0])) {
7570                 reg = amd64_rex_b (rip [0]);
7571                 rip ++;
7572         }
7573         else
7574                 reg = 0;
7575
7576         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7577                 /* idiv REG */
7578                 reg += x86_modrm_rm (rip [1]);
7579
7580                 switch (reg) {
7581                 case AMD64_RAX:
7582                         value = ctx.rax;
7583                         break;
7584                 case AMD64_RBX:
7585                         value = ctx.rbx;
7586                         break;
7587                 case AMD64_RCX:
7588                         value = ctx.rcx;
7589                         break;
7590                 case AMD64_RDX:
7591                         value = ctx.rdx;
7592                         break;
7593                 case AMD64_RBP:
7594                         value = ctx.rbp;
7595                         break;
7596                 case AMD64_RSP:
7597                         value = ctx.rsp;
7598                         break;
7599                 case AMD64_RSI:
7600                         value = ctx.rsi;
7601                         break;
7602                 case AMD64_RDI:
7603                         value = ctx.rdi;
7604                         break;
7605                 case AMD64_R12:
7606                         value = ctx.r12;
7607                         break;
7608                 case AMD64_R13:
7609                         value = ctx.r13;
7610                         break;
7611                 case AMD64_R14:
7612                         value = ctx.r14;
7613                         break;
7614                 case AMD64_R15:
7615                         value = ctx.r15;
7616                         break;
7617                 default:
7618                         g_assert_not_reached ();
7619                         reg = -1;
7620                 }
7621
7622                 if (value == -1)
7623                         return TRUE;
7624         }
7625
7626         return FALSE;
7627 }
7628
7629 guint32
7630 mono_arch_get_patch_offset (guint8 *code)
7631 {
7632         return 3;
7633 }
7634
7635 /**
7636  * mono_breakpoint_clean_code:
7637  *
7638  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7639  * breakpoints in the original code, they are removed in the copy.
7640  *
7641  * Returns TRUE if no sw breakpoint was present.
7642  */
7643 gboolean
7644 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7645 {
7646         int i;
7647         gboolean can_write = TRUE;
7648         /*
7649          * If method_start is non-NULL we need to perform bound checks, since we access memory
7650          * at code - offset we could go before the start of the method and end up in a different
7651          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7652          * instead.
7653          */
7654         if (!method_start || code - offset >= method_start) {
7655                 memcpy (buf, code - offset, size);
7656         } else {
7657                 int diff = code - method_start;
7658                 memset (buf, 0, size);
7659                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7660         }
7661         code -= offset;
7662         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7663                 int idx = mono_breakpoint_info_index [i];
7664                 guint8 *ptr;
7665                 if (idx < 1)
7666                         continue;
7667                 ptr = mono_breakpoint_info [idx].address;
7668                 if (ptr >= code && ptr < code + size) {
7669                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7670                         can_write = FALSE;
7671                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7672                         buf [ptr - code] = saved_byte;
7673                 }
7674         }
7675         return can_write;
7676 }
7677
7678 #if defined(__native_client_codegen__)
7679 /* For membase calls, we want the base register. for Native Client,  */
7680 /* all indirect calls have the following sequence with the given sizes: */
7681 /* mov %eXX,%eXX                                [2-3]   */
7682 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7683 /* and $0xffffffffffffffe0,%r11d                [4]     */
7684 /* add %r15,%r11                                [3]     */
7685 /* callq *%r11                                  [3]     */
7686
7687
7688 /* Determine if code points to a NaCl call-through-register sequence, */
7689 /* (i.e., the last 3 instructions listed above) */
7690 int
7691 is_nacl_call_reg_sequence(guint8* code)
7692 {
7693         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7694                                "\x4d\x03\xdf"     /* add */
7695                                "\x41\xff\xd3";   /* call */
7696         return memcmp(code, sequence, 10) == 0;
7697 }
7698
7699 /* Determine if code points to the first opcode of the mov membase component */
7700 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7701 /* (there could be a REX prefix before the opcode but it is ignored) */
7702 static int
7703 is_nacl_indirect_call_membase_sequence(guint8* code)
7704 {
7705                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7706         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7707                /* and that src reg = dest reg */
7708                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7709                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7710                IS_REX(code[2]) &&
7711                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7712                /* and has dst of r11 and base of r15 */
7713                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7714                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7715 }
7716 #endif /* __native_client_codegen__ */
7717
7718 int
7719 mono_arch_get_this_arg_reg (guint8 *code)
7720 {
7721         return AMD64_ARG_REG1;
7722 }
7723
7724 gpointer
7725 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7726 {
7727         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7728 }
7729
7730 #define MAX_ARCH_DELEGATE_PARAMS 10
7731
7732 static gpointer
7733 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7734 {
7735         guint8 *code, *start;
7736         int i;
7737
7738         if (has_target) {
7739                 start = code = mono_global_codeman_reserve (64);
7740
7741                 /* Replace the this argument with the target */
7742                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7743                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7744                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7745
7746                 g_assert ((code - start) < 64);
7747         } else {
7748                 start = code = mono_global_codeman_reserve (64);
7749
7750                 if (param_count == 0) {
7751                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7752                 } else {
7753                         /* We have to shift the arguments left */
7754                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7755                         for (i = 0; i < param_count; ++i) {
7756 #ifdef HOST_WIN32
7757                                 if (i < 3)
7758                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7759                                 else
7760                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7761 #else
7762                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7763 #endif
7764                         }
7765
7766                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7767                 }
7768                 g_assert ((code - start) < 64);
7769         }
7770
7771         nacl_global_codeman_validate (&start, 64, &code);
7772
7773         if (code_len)
7774                 *code_len = code - start;
7775
7776         if (mono_jit_map_is_enabled ()) {
7777                 char *buff;
7778                 if (has_target)
7779                         buff = (char*)"delegate_invoke_has_target";
7780                 else
7781                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7782                 mono_emit_jit_tramp (start, code - start, buff);
7783                 if (!has_target)
7784                         g_free (buff);
7785         }
7786         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7787
7788         return start;
7789 }
7790
7791 /*
7792  * mono_arch_get_delegate_invoke_impls:
7793  *
7794  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7795  * trampolines.
7796  */
7797 GSList*
7798 mono_arch_get_delegate_invoke_impls (void)
7799 {
7800         GSList *res = NULL;
7801         guint8 *code;
7802         guint32 code_len;
7803         int i;
7804         char *tramp_name;
7805
7806         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7807         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7808
7809         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7810                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7811                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7812                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7813                 g_free (tramp_name);
7814         }
7815
7816         return res;
7817 }
7818
7819 gpointer
7820 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7821 {
7822         guint8 *code, *start;
7823         int i;
7824
7825         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7826                 return NULL;
7827
7828         /* FIXME: Support more cases */
7829         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7830                 return NULL;
7831
7832         if (has_target) {
7833                 static guint8* cached = NULL;
7834
7835                 if (cached)
7836                         return cached;
7837
7838                 if (mono_aot_only)
7839                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7840                 else
7841                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7842
7843                 mono_memory_barrier ();
7844
7845                 cached = start;
7846         } else {
7847                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7848                 for (i = 0; i < sig->param_count; ++i)
7849                         if (!mono_is_regsize_var (sig->params [i]))
7850                                 return NULL;
7851                 if (sig->param_count > 4)
7852                         return NULL;
7853
7854                 code = cache [sig->param_count];
7855                 if (code)
7856                         return code;
7857
7858                 if (mono_aot_only) {
7859                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7860                         start = mono_aot_get_trampoline (name);
7861                         g_free (name);
7862                 } else {
7863                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7864                 }
7865
7866                 mono_memory_barrier ();
7867
7868                 cache [sig->param_count] = start;
7869         }
7870
7871         return start;
7872 }
7873
7874 gpointer
7875 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7876 {
7877         guint8 *code, *start;
7878         int size = 20;
7879
7880         start = code = mono_global_codeman_reserve (size);
7881
7882         /* Replace the this argument with the target */
7883         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7884         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7885
7886         if (load_imt_reg) {
7887                 /* Load the IMT reg */
7888                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7889         }
7890
7891         /* Load the vtable */
7892         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7893         amd64_jump_membase (code, AMD64_RAX, offset);
7894         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7895
7896         return start;
7897 }
7898
7899 void
7900 mono_arch_finish_init (void)
7901 {
7902 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7903         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7904 #endif
7905 }
7906
7907 void
7908 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7909 {
7910 }
7911
7912 #if defined(__default_codegen__)
7913 #define CMP_SIZE (6 + 1)
7914 #define CMP_REG_REG_SIZE (4 + 1)
7915 #define BR_SMALL_SIZE 2
7916 #define BR_LARGE_SIZE 6
7917 #define MOV_REG_IMM_SIZE 10
7918 #define MOV_REG_IMM_32BIT_SIZE 6
7919 #define JUMP_REG_SIZE (2 + 1)
7920 #elif defined(__native_client_codegen__)
7921 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7922 #define CMP_SIZE ((6 + 1) * 2 - 1)
7923 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7924 #define BR_SMALL_SIZE (2 * 2 - 1)
7925 #define BR_LARGE_SIZE (6 * 2 - 1)
7926 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7927 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7928 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7929 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7930 /* Jump membase's size is large and unpredictable    */
7931 /* in native client, just pad it out a whole bundle. */
7932 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7933 #endif
7934
7935 static int
7936 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7937 {
7938         int i, distance = 0;
7939         for (i = start; i < target; ++i)
7940                 distance += imt_entries [i]->chunk_size;
7941         return distance;
7942 }
7943
7944 /*
7945  * LOCKING: called with the domain lock held
7946  */
7947 gpointer
7948 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7949         gpointer fail_tramp)
7950 {
7951         int i;
7952         int size = 0;
7953         guint8 *code, *start;
7954         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7955
7956         for (i = 0; i < count; ++i) {
7957                 MonoIMTCheckItem *item = imt_entries [i];
7958                 if (item->is_equals) {
7959                         if (item->check_target_idx) {
7960                                 if (!item->compare_done) {
7961                                         if (amd64_is_imm32 (item->key))
7962                                                 item->chunk_size += CMP_SIZE;
7963                                         else
7964                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7965                                 }
7966                                 if (item->has_target_code) {
7967                                         item->chunk_size += MOV_REG_IMM_SIZE;
7968                                 } else {
7969                                         if (vtable_is_32bit)
7970                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7971                                         else
7972                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7973 #ifdef __native_client_codegen__
7974                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7975 #endif
7976                                 }
7977                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7978                         } else {
7979                                 if (fail_tramp) {
7980                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7981                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7982                                 } else {
7983                                         if (vtable_is_32bit)
7984                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7985                                         else
7986                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7987                                         item->chunk_size += JUMP_REG_SIZE;
7988                                         /* with assert below:
7989                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7990                                          */
7991 #ifdef __native_client_codegen__
7992                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7993 #endif
7994                                 }
7995                         }
7996                 } else {
7997                         if (amd64_is_imm32 (item->key))
7998                                 item->chunk_size += CMP_SIZE;
7999                         else
8000                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8001                         item->chunk_size += BR_LARGE_SIZE;
8002                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8003                 }
8004                 size += item->chunk_size;
8005         }
8006 #if defined(__native_client__) && defined(__native_client_codegen__)
8007         /* In Native Client, we don't re-use thunks, allocate from the */
8008         /* normal code manager paths. */
8009         code = mono_domain_code_reserve (domain, size);
8010 #else
8011         if (fail_tramp)
8012                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8013         else
8014                 code = mono_domain_code_reserve (domain, size);
8015 #endif
8016         start = code;
8017         for (i = 0; i < count; ++i) {
8018                 MonoIMTCheckItem *item = imt_entries [i];
8019                 item->code_target = code;
8020                 if (item->is_equals) {
8021                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8022
8023                         if (item->check_target_idx || fail_case) {
8024                                 if (!item->compare_done || fail_case) {
8025                                         if (amd64_is_imm32 (item->key))
8026                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8027                                         else {
8028                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8029                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8030                                         }
8031                                 }
8032                                 item->jmp_code = code;
8033                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8034                                 if (item->has_target_code) {
8035                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8036                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8037                                 } else {
8038                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8039                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8040                                 }
8041
8042                                 if (fail_case) {
8043                                         amd64_patch (item->jmp_code, code);
8044                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8045                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8046                                         item->jmp_code = NULL;
8047                                 }
8048                         } else {
8049                                 /* enable the commented code to assert on wrong method */
8050 #if 0
8051                                 if (amd64_is_imm32 (item->key))
8052                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8053                                 else {
8054                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8055                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8056                                 }
8057                                 item->jmp_code = code;
8058                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8059                                 /* See the comment below about R10 */
8060                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8061                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8062                                 amd64_patch (item->jmp_code, code);
8063                                 amd64_breakpoint (code);
8064                                 item->jmp_code = NULL;
8065 #else
8066                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8067                                    needs to be preserved.  R10 needs
8068                                    to be preserved for calls which
8069                                    require a runtime generic context,
8070                                    but interface calls don't. */
8071                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8072                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8073 #endif
8074                         }
8075                 } else {
8076                         if (amd64_is_imm32 (item->key))
8077                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8078                         else {
8079                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8080                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8081                         }
8082                         item->jmp_code = code;
8083                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8084                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8085                         else
8086                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8087                 }
8088                 g_assert (code - item->code_target <= item->chunk_size);
8089         }
8090         /* patch the branches to get to the target items */
8091         for (i = 0; i < count; ++i) {
8092                 MonoIMTCheckItem *item = imt_entries [i];
8093                 if (item->jmp_code) {
8094                         if (item->check_target_idx) {
8095                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8096                         }
8097                 }
8098         }
8099
8100         if (!fail_tramp)
8101                 mono_stats.imt_thunks_size += code - start;
8102         g_assert (code - start <= size);
8103
8104         nacl_domain_code_validate(domain, &start, size, &code);
8105         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8106
8107         return start;
8108 }
8109
8110 MonoMethod*
8111 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8112 {
8113         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8114 }
8115
8116 MonoVTable*
8117 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8118 {
8119         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8120 }
8121
8122 GSList*
8123 mono_arch_get_cie_program (void)
8124 {
8125         GSList *l = NULL;
8126
8127         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8128         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8129
8130         return l;
8131 }
8132
8133 MonoInst*
8134 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8135 {
8136         MonoInst *ins = NULL;
8137         int opcode = 0;
8138
8139         if (cmethod->klass == mono_defaults.math_class) {
8140                 if (strcmp (cmethod->name, "Sin") == 0) {
8141                         opcode = OP_SIN;
8142                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8143                         opcode = OP_COS;
8144                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8145                         opcode = OP_SQRT;
8146                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8147                         opcode = OP_ABS;
8148                 }
8149
8150                 if (opcode) {
8151                         MONO_INST_NEW (cfg, ins, opcode);
8152                         ins->type = STACK_R8;
8153                         ins->dreg = mono_alloc_freg (cfg);
8154                         ins->sreg1 = args [0]->dreg;
8155                         MONO_ADD_INS (cfg->cbb, ins);
8156                 }
8157
8158                 opcode = 0;
8159                 if (cfg->opt & MONO_OPT_CMOV) {
8160                         if (strcmp (cmethod->name, "Min") == 0) {
8161                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8162                                         opcode = OP_IMIN;
8163                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8164                                         opcode = OP_IMIN_UN;
8165                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8166                                         opcode = OP_LMIN;
8167                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8168                                         opcode = OP_LMIN_UN;
8169                         } else if (strcmp (cmethod->name, "Max") == 0) {
8170                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8171                                         opcode = OP_IMAX;
8172                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8173                                         opcode = OP_IMAX_UN;
8174                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8175                                         opcode = OP_LMAX;
8176                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8177                                         opcode = OP_LMAX_UN;
8178                         }
8179                 }
8180
8181                 if (opcode) {
8182                         MONO_INST_NEW (cfg, ins, opcode);
8183                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8184                         ins->dreg = mono_alloc_ireg (cfg);
8185                         ins->sreg1 = args [0]->dreg;
8186                         ins->sreg2 = args [1]->dreg;
8187                         MONO_ADD_INS (cfg->cbb, ins);
8188                 }
8189
8190 #if 0
8191                 /* OP_FREM is not IEEE compatible */
8192                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8193                         MONO_INST_NEW (cfg, ins, OP_FREM);
8194                         ins->inst_i0 = args [0];
8195                         ins->inst_i1 = args [1];
8196                 }
8197 #endif
8198         }
8199
8200         /*
8201          * Can't implement CompareExchange methods this way since they have
8202          * three arguments.
8203          */
8204
8205         return ins;
8206 }
8207
8208 gboolean
8209 mono_arch_print_tree (MonoInst *tree, int arity)
8210 {
8211         return 0;
8212 }
8213
8214 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8215
8216 mgreg_t
8217 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8218 {
8219         switch (reg) {
8220         case AMD64_RCX: return ctx->rcx;
8221         case AMD64_RDX: return ctx->rdx;
8222         case AMD64_RBX: return ctx->rbx;
8223         case AMD64_RBP: return ctx->rbp;
8224         case AMD64_RSP: return ctx->rsp;
8225         default:
8226                 return _CTX_REG (ctx, rax, reg);
8227         }
8228 }
8229
8230 void
8231 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8232 {
8233         switch (reg) {
8234         case AMD64_RCX:
8235                 ctx->rcx = val;
8236                 break;
8237         case AMD64_RDX:
8238                 ctx->rdx = val;
8239                 break;
8240         case AMD64_RBX:
8241                 ctx->rbx = val;
8242                 break;
8243         case AMD64_RBP:
8244                 ctx->rbp = val;
8245                 break;
8246         case AMD64_RSP:
8247                 ctx->rsp = val;
8248                 break;
8249         default:
8250                 _CTX_REG (ctx, rax, reg) = val;
8251         }
8252 }
8253
8254 gpointer
8255 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8256 {
8257         gpointer *sp, old_value;
8258         char *bp;
8259
8260         /*Load the spvar*/
8261         bp = MONO_CONTEXT_GET_BP (ctx);
8262         sp = *(gpointer*)(bp + clause->exvar_offset);
8263
8264         old_value = *sp;
8265         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8266                 return old_value;
8267
8268         *sp = new_value;
8269
8270         return old_value;
8271 }
8272
8273 /*
8274  * mono_arch_emit_load_aotconst:
8275  *
8276  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8277  * TARGET from the mscorlib GOT in full-aot code.
8278  * On AMD64, the result is placed into R11.
8279  */
8280 guint8*
8281 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8282 {
8283         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8284         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8285
8286         return code;
8287 }
8288
8289 /*
8290  * mono_arch_get_trampolines:
8291  *
8292  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8293  * for AOT.
8294  */
8295 GSList *
8296 mono_arch_get_trampolines (gboolean aot)
8297 {
8298         return mono_amd64_get_exception_trampolines (aot);
8299 }
8300
8301 /* Soft Debug support */
8302 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8303
8304 /*
8305  * mono_arch_set_breakpoint:
8306  *
8307  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8308  * The location should contain code emitted by OP_SEQ_POINT.
8309  */
8310 void
8311 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8312 {
8313         guint8 *code = ip;
8314         guint8 *orig_code = code;
8315
8316         if (ji->from_aot) {
8317                 guint32 native_offset = ip - (guint8*)ji->code_start;
8318                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8319
8320                 g_assert (info->bp_addrs [native_offset] == 0);
8321                 info->bp_addrs [native_offset] = bp_trigger_page;
8322         } else {
8323                 /*
8324                  * In production, we will use int3 (has to fix the size in the md
8325                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8326                  * instead.
8327                  */
8328                 g_assert (code [0] == 0x90);
8329                 if (breakpoint_size == 8) {
8330                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8331                 } else {
8332                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8333                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8334                 }
8335
8336                 g_assert (code - orig_code == breakpoint_size);
8337         }
8338 }
8339
8340 /*
8341  * mono_arch_clear_breakpoint:
8342  *
8343  *   Clear the breakpoint at IP.
8344  */
8345 void
8346 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8347 {
8348         guint8 *code = ip;
8349         int i;
8350
8351         if (ji->from_aot) {
8352                 guint32 native_offset = ip - (guint8*)ji->code_start;
8353                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8354
8355                 g_assert (info->bp_addrs [native_offset] == 0);
8356                 info->bp_addrs [native_offset] = info;
8357         } else {
8358                 for (i = 0; i < breakpoint_size; ++i)
8359                         x86_nop (code);
8360         }
8361 }
8362
8363 gboolean
8364 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8365 {
8366 #ifdef HOST_WIN32
8367         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8368         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8369                 return TRUE;
8370         else
8371                 return FALSE;
8372 #else
8373         siginfo_t* sinfo = (siginfo_t*) info;
8374         /* Sometimes the address is off by 4 */
8375         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8376                 return TRUE;
8377         else
8378                 return FALSE;
8379 #endif
8380 }
8381
8382 /*
8383  * mono_arch_skip_breakpoint:
8384  *
8385  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8386  * we resume, the instruction is not executed again.
8387  */
8388 void
8389 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8390 {
8391         if (ji->from_aot) {
8392                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8393                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8394         } else {
8395                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8396         }
8397 }
8398
8399 /*
8400  * mono_arch_start_single_stepping:
8401  *
8402  *   Start single stepping.
8403  */
8404 void
8405 mono_arch_start_single_stepping (void)
8406 {
8407         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8408 }
8409
8410 /*
8411  * mono_arch_stop_single_stepping:
8412  *
8413  *   Stop single stepping.
8414  */
8415 void
8416 mono_arch_stop_single_stepping (void)
8417 {
8418         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8419 }
8420
8421 /*
8422  * mono_arch_is_single_step_event:
8423  *
8424  *   Return whenever the machine state in SIGCTX corresponds to a single
8425  * step event.
8426  */
8427 gboolean
8428 mono_arch_is_single_step_event (void *info, void *sigctx)
8429 {
8430 #ifdef HOST_WIN32
8431         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8432         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8433                 return TRUE;
8434         else
8435                 return FALSE;
8436 #else
8437         siginfo_t* sinfo = (siginfo_t*) info;
8438         /* Sometimes the address is off by 4 */
8439         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8440                 return TRUE;
8441         else
8442                 return FALSE;
8443 #endif
8444 }
8445
8446 /*
8447  * mono_arch_skip_single_step:
8448  *
8449  *   Modify CTX so the ip is placed after the single step trigger instruction,
8450  * we resume, the instruction is not executed again.
8451  */
8452 void
8453 mono_arch_skip_single_step (MonoContext *ctx)
8454 {
8455         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8456 }
8457
8458 /*
8459  * mono_arch_create_seq_point_info:
8460  *
8461  *   Return a pointer to a data structure which is used by the sequence
8462  * point implementation in AOTed code.
8463  */
8464 gpointer
8465 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8466 {
8467         SeqPointInfo *info;
8468         MonoJitInfo *ji;
8469         int i;
8470
8471         // FIXME: Add a free function
8472
8473         mono_domain_lock (domain);
8474         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8475                                                                 code);
8476         mono_domain_unlock (domain);
8477
8478         if (!info) {
8479                 ji = mono_jit_info_table_find (domain, (char*)code);
8480                 g_assert (ji);
8481
8482                 // FIXME: Optimize the size
8483                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8484
8485                 info->ss_trigger_page = ss_trigger_page;
8486                 info->bp_trigger_page = bp_trigger_page;
8487                 /* Initialize to a valid address */
8488                 for (i = 0; i < ji->code_size; ++i)
8489                         info->bp_addrs [i] = info;
8490
8491                 mono_domain_lock (domain);
8492                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8493                                                          code, info);
8494                 mono_domain_unlock (domain);
8495         }
8496
8497         return info;
8498 }
8499
8500 void
8501 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8502 {
8503         ext->lmf.previous_lmf = prev_lmf;
8504         /* Mark that this is a MonoLMFExt */
8505         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8506         ext->lmf.rsp = (gssize)ext;
8507 }
8508
8509 #endif
8510
8511 gboolean
8512 mono_arch_opcode_supported (int opcode)
8513 {
8514         switch (opcode) {
8515         case OP_ATOMIC_ADD_I4:
8516         case OP_ATOMIC_ADD_I8:
8517         case OP_ATOMIC_EXCHANGE_I4:
8518         case OP_ATOMIC_EXCHANGE_I8:
8519         case OP_ATOMIC_CAS_I4:
8520         case OP_ATOMIC_CAS_I8:
8521                 return TRUE;
8522         default:
8523                 return FALSE;
8524         }
8525 }