mono/mini/mini-amd64.c

   1 /**
   2  * \file
   3  * AMD64 backend for the Mono code generator
   4  *
   5  * Based on mini-x86.c.
   6  *
   7  * Authors:
   8  *   Paolo Molaro (lupus@ximian.com)
   9  *   Dietmar Maurer (dietmar@ximian.com)
  10  *   Patrik Torstensson
  11  *   Zoltan Varga (vargaz@gmail.com)
  12  *   Johan Lorensson (lateralusx.github@gmail.com)
  13  *
  14  * (C) 2003 Ximian, Inc.
  15  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  16  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  17  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  18  */
  19 #include "mini.h"
  20 #include <string.h>
  21 #include <math.h>
  22 #include <assert.h>
  23 #ifdef HAVE_UNISTD_H
  24 #include <unistd.h>
  25 #endif
  26
  27 #include <mono/metadata/abi-details.h>
  28 #include <mono/metadata/appdomain.h>
  29 #include <mono/metadata/debug-helpers.h>
  30 #include <mono/metadata/threads.h>
  31 #include <mono/metadata/profiler-private.h>
  32 #include <mono/metadata/mono-debug.h>
  33 #include <mono/metadata/gc-internals.h>
  34 #include <mono/utils/mono-math.h>
  35 #include <mono/utils/mono-mmap.h>
  36 #include <mono/utils/mono-memory-model.h>
  37 #include <mono/utils/mono-tls.h>
  38 #include <mono/utils/mono-hwcap.h>
  39 #include <mono/utils/mono-threads.h>
  40
  41 #include "trace.h"
  42 #include "ir-emit.h"
  43 #include "mini-amd64.h"
  44 #include "cpu-amd64.h"
  45 #include "debugger-agent.h"
  46 #include "mini-gc.h"
  47
  48 #ifdef MONO_XEN_OPT
  49 static gboolean optimize_for_xen = TRUE;
  50 #else
  51 #define optimize_for_xen 0
  52 #endif
  53
  54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  55
  56 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  57
  58 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  59
  60 #ifdef TARGET_WIN32
  61 /* Under windows, the calling convention is never stdcall */
  62 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  63 #else
  64 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  65 #endif
  66
  67 /* This mutex protects architecture specific caches */
  68 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  69 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  70 static mono_mutex_t mini_arch_mutex;
  71
  72 /* The single step trampoline */
  73 static gpointer ss_trampoline;
  74
  75 /* The breakpoint trampoline */
  76 static gpointer bp_trampoline;
  77
  78 /* Offset between fp and the first argument in the callee */
  79 #define ARGS_OFFSET 16
  80 #define GP_SCRATCH_REG AMD64_R11
  81
  82 /*
  83  * AMD64 register usage:
  84  * - callee saved registers are used for global register allocation
  85  * - %r11 is used for materializing 64 bit constants in opcodes
  86  * - the rest is used for local allocation
  87  */
  88
  89 /*
  90  * Floating point comparison results:
  91  *                  ZF PF CF
  92  * A > B            0  0  0
  93  * A < B            0  0  1
  94  * A = B            1  0  0
  95  * A > B            0  0  0
  96  * UNORDERED        1  1  1
  97  */
  98
  99 const char*
 100 mono_arch_regname (int reg)
 101 {
 102         switch (reg) {
 103         case AMD64_RAX: return "%rax";
 104         case AMD64_RBX: return "%rbx";
 105         case AMD64_RCX: return "%rcx";
 106         case AMD64_RDX: return "%rdx";
 107         case AMD64_RSP: return "%rsp";
 108         case AMD64_RBP: return "%rbp";
 109         case AMD64_RDI: return "%rdi";
 110         case AMD64_RSI: return "%rsi";
 111         case AMD64_R8: return "%r8";
 112         case AMD64_R9: return "%r9";
 113         case AMD64_R10: return "%r10";
 114         case AMD64_R11: return "%r11";
 115         case AMD64_R12: return "%r12";
 116         case AMD64_R13: return "%r13";
 117         case AMD64_R14: return "%r14";
 118         case AMD64_R15: return "%r15";
 119         }
 120         return "unknown";
 121 }
 122
 123 static const char * packed_xmmregs [] = {
 124         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 125         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 126 };
 127
 128 static const char * single_xmmregs [] = {
 129         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 130         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 131 };
 132
 133 const char*
 134 mono_arch_fregname (int reg)
 135 {
 136         if (reg < AMD64_XMM_NREG)
 137                 return single_xmmregs [reg];
 138         else
 139                 return "unknown";
 140 }
 141
 142 const char *
 143 mono_arch_xregname (int reg)
 144 {
 145         if (reg < AMD64_XMM_NREG)
 146                 return packed_xmmregs [reg];
 147         else
 148                 return "unknown";
 149 }
 150
 151 static gboolean
 152 debug_omit_fp (void)
 153 {
 154 #if 0
 155         return mono_debug_count ();
 156 #else
 157         return TRUE;
 158 #endif
 159 }
 160
 161 static inline gboolean
 162 amd64_is_near_call (guint8 *code)
 163 {
 164         /* Skip REX */
 165         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 166                 code += 1;
 167
 168         return code [0] == 0xe8;
 169 }
 170
 171 static inline gboolean
 172 amd64_use_imm32 (gint64 val)
 173 {
 174         if (mini_get_debug_options()->single_imm_size)
 175                 return FALSE;
 176
 177         return amd64_is_imm32 (val);
 178 }
 179
 180 static void
 181 amd64_patch (unsigned char* code, gpointer target)
 182 {
 183         guint8 rex = 0;
 184
 185         /* Skip REX */
 186         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 187                 rex = code [0];
 188                 code += 1;
 189         }
 190
 191         if ((code [0] & 0xf8) == 0xb8) {
 192                 /* amd64_set_reg_template */
 193                 *(guint64*)(code + 1) = (guint64)target;
 194         }
 195         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 196                 /* mov 0(%rip), %dreg */
 197                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 198         }
 199         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 200                 /* call *<OFFSET>(%rip) */
 201                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 202         }
 203         else if (code [0] == 0xe8) {
 204                 /* call <DISP> */
 205                 gint64 disp = (guint8*)target - (guint8*)code;
 206                 g_assert (amd64_is_imm32 (disp));
 207                 x86_patch (code, (unsigned char*)target);
 208         }
 209         else
 210                 x86_patch (code, (unsigned char*)target);
 211 }
 212
 213 void
 214 mono_amd64_patch (unsigned char* code, gpointer target)
 215 {
 216         amd64_patch (code, target);
 217 }
 218
 219 #define DEBUG(a) if (cfg->verbose_level > 1) a
 220
 221 static void inline
 222 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 223 {
 224     ainfo->offset = *stack_size;
 225
 226     if (*gr >= PARAM_REGS) {
 227                 ainfo->storage = ArgOnStack;
 228                 ainfo->arg_size = sizeof (mgreg_t);
 229                 /* Since the same stack slot size is used for all arg */
 230                 /*  types, it needs to be big enough to hold them all */
 231                 (*stack_size) += sizeof(mgreg_t);
 232     }
 233     else {
 234                 ainfo->storage = ArgInIReg;
 235                 ainfo->reg = param_regs [*gr];
 236                 (*gr) ++;
 237     }
 238 }
 239
 240 static void inline
 241 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 242 {
 243     ainfo->offset = *stack_size;
 244
 245     if (*gr >= FLOAT_PARAM_REGS) {
 246                 ainfo->storage = ArgOnStack;
 247                 ainfo->arg_size = sizeof (mgreg_t);
 248                 /* Since the same stack slot size is used for both float */
 249                 /*  types, it needs to be big enough to hold them both */
 250                 (*stack_size) += sizeof(mgreg_t);
 251     }
 252     else {
 253                 /* A double register */
 254                 if (is_double)
 255                         ainfo->storage = ArgInDoubleSSEReg;
 256                 else
 257                         ainfo->storage = ArgInFloatSSEReg;
 258                 ainfo->reg = *gr;
 259                 (*gr) += 1;
 260     }
 261 }
 262
 263 typedef enum ArgumentClass {
 264         ARG_CLASS_NO_CLASS,
 265         ARG_CLASS_MEMORY,
 266         ARG_CLASS_INTEGER,
 267         ARG_CLASS_SSE
 268 } ArgumentClass;
 269
 270 static ArgumentClass
 271 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 272 {
 273         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 274         MonoType *ptype;
 275
 276         ptype = mini_get_underlying_type (type);
 277         switch (ptype->type) {
 278         case MONO_TYPE_I1:
 279         case MONO_TYPE_U1:
 280         case MONO_TYPE_I2:
 281         case MONO_TYPE_U2:
 282         case MONO_TYPE_I4:
 283         case MONO_TYPE_U4:
 284         case MONO_TYPE_I:
 285         case MONO_TYPE_U:
 286         case MONO_TYPE_OBJECT:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_I8:
 290         case MONO_TYPE_U8:
 291                 class2 = ARG_CLASS_INTEGER;
 292                 break;
 293         case MONO_TYPE_R4:
 294         case MONO_TYPE_R8:
 295 #ifdef TARGET_WIN32
 296                 class2 = ARG_CLASS_INTEGER;
 297 #else
 298                 class2 = ARG_CLASS_SSE;
 299 #endif
 300                 break;
 301
 302         case MONO_TYPE_TYPEDBYREF:
 303                 g_assert_not_reached ();
 304
 305         case MONO_TYPE_GENERICINST:
 306                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 307                         class2 = ARG_CLASS_INTEGER;
 308                         break;
 309                 }
 310                 /* fall through */
 311         case MONO_TYPE_VALUETYPE: {
 312                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 313                 int i;
 314
 315                 for (i = 0; i < info->num_fields; ++i) {
 316                         class2 = class1;
 317                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 318                 }
 319                 break;
 320         }
 321         default:
 322                 g_assert_not_reached ();
 323         }
 324
 325         /* Merge */
 326         if (class1 == class2)
 327                 ;
 328         else if (class1 == ARG_CLASS_NO_CLASS)
 329                 class1 = class2;
 330         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 331                 class1 = ARG_CLASS_MEMORY;
 332         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 333                 class1 = ARG_CLASS_INTEGER;
 334         else
 335                 class1 = ARG_CLASS_SSE;
 336
 337         return class1;
 338 }
 339
 340 typedef struct {
 341         MonoType *type;
 342         int size, offset;
 343 } StructFieldInfo;
 344
 345 /*
 346  * collect_field_info_nested:
 347  *
 348  *   Collect field info from KLASS recursively into FIELDS.
 349  */
 350 static void
 351 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
 352 {
 353         MonoMarshalType *info;
 354         int i;
 355
 356         if (pinvoke) {
 357                 info = mono_marshal_load_type_info (klass);
 358                 g_assert(info);
 359                 for (i = 0; i < info->num_fields; ++i) {
 360                         if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 361                                 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
 362                         } else {
 363                                 guint32 align;
 364                                 StructFieldInfo f;
 365
 366                                 f.type = info->fields [i].field->type;
 367                                 f.size = mono_marshal_type_size (info->fields [i].field->type,
 368                                                                                                                            info->fields [i].mspec,
 369                                                                                                                            &align, TRUE, unicode);
 370                                 f.offset = offset + info->fields [i].offset;
 371                                 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
 372                                         /* This can happen with .pack directives eg. 'fixed' arrays */
 373                                         if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
 374                                                 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
 375                                                 g_array_append_val (fields_array, f);
 376                                                 while (f.size + f.offset < info->native_size) {
 377                                                         f.offset += f.size;
 378                                                         g_array_append_val (fields_array, f);
 379                                                 }
 380                                         } else {
 381                                                 f.size = info->native_size - f.offset;
 382                                                 g_array_append_val (fields_array, f);
 383                                         }
 384                                 } else {
 385                                         g_array_append_val (fields_array, f);
 386                                 }
 387                         }
 388                 }
 389         } else {
 390                 gpointer iter;
 391                 MonoClassField *field;
 392
 393                 iter = NULL;
 394                 while ((field = mono_class_get_fields (klass, &iter))) {
 395                         if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
 396                                 continue;
 397                         if (MONO_TYPE_ISSTRUCT (field->type)) {
 398                                 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
 399                         } else {
 400                                 int align;
 401                                 StructFieldInfo f;
 402
 403                                 f.type = field->type;
 404                                 f.size = mono_type_size (field->type, &align);
 405                                 f.offset = field->offset - sizeof (MonoObject) + offset;
 406
 407                                 g_array_append_val (fields_array, f);
 408                         }
 409                 }
 410         }
 411 }
 412
 413 #ifdef TARGET_WIN32
 414
 415 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
 416 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
 417
 418 static gboolean
 419 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
 420 {
 421         gboolean result = FALSE;
 422
 423         assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
 424         assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
 425
 426         arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 427         arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
 428         arg_info->pair_size [0] = 0;
 429         arg_info->pair_size [1] = 0;
 430         arg_info->nregs = 0;
 431
 432         if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
 433                 /* Pass parameter in integer register. */
 434                 arg_info->pair_storage [0] = ArgInIReg;
 435                 arg_info->pair_regs [0] = int_regs [*current_int_reg];
 436                 (*current_int_reg) ++;
 437                 result = TRUE;
 438         } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
 439                 /* Pass parameter in float register. */
 440                 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
 441                 arg_info->pair_regs [0] = float_regs [*current_float_reg];
 442                 (*current_float_reg) ++;
 443                 result = TRUE;
 444         }
 445
 446         if (result == TRUE) {
 447                 arg_info->pair_size [0] = arg_size;
 448                 arg_info->nregs = 1;
 449         }
 450
 451         return result;
 452 }
 453
 454 static inline gboolean
 455 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 456 {
 457         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
 458 }
 459
 460 static inline gboolean
 461 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 462 {
 463         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
 464 }
 465
 466 static void
 467 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
 468                                                                           guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 469 {
 470         /* Windows x64 value type ABI.
 471         *
 472         * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
 473         *
 474         * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
 475         *    Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
 476         * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 477         *    Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
 478         *
 479         * Return values:  https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
 480         *
 481         * Integers/Float types smaller than or equal to 8 bytes
 482         *    Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
 483         * Properly sized struct/unions (1,2,4,8)
 484         *    Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
 485         * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 486         *    Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
 487         */
 488
 489         assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 490
 491         if (!is_return) {
 492
 493                 /* Parameter cases. */
 494                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 495                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 496
 497                         /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
 498                         arg_info->storage = ArgValuetypeInReg;
 499                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 500                                 /* No more registers, fallback passing parameter on stack as value. */
 501                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 502
 503                                 /* Passing value directly on stack, so use size of value. */
 504                                 arg_info->storage = ArgOnStack;
 505                                 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 506                                 arg_info->offset = *stack_size;
 507                                 arg_info->arg_size = arg_size;
 508                                 *stack_size += arg_size;
 509                         }
 510                 } else {
 511                         /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
 512                         arg_info->storage = ArgValuetypeAddrInIReg;
 513                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 514                                 /* No more registers, fallback passing address to parameter on stack. */
 515                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 516
 517                                 /* Passing an address to value on stack, so use size of register as argument size. */
 518                                 arg_info->storage = ArgValuetypeAddrOnStack;
 519                                 arg_size = sizeof (mgreg_t);
 520                                 arg_info->offset = *stack_size;
 521                                 arg_info->arg_size = arg_size;
 522                                 *stack_size += arg_size;
 523                         }
 524                 }
 525         } else {
 526                 /* Return value cases. */
 527                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 528                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 529
 530                         /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
 531                         arg_info->storage = ArgValuetypeInReg;
 532                         allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 533
 534                         /* Only RAX/XMM0 should be used to return valuetype. */
 535                         assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
 536                 } else {
 537                         /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
 538                         arg_info->storage = ArgValuetypeAddrInIReg;
 539                         allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 540
 541                         /* Only RAX should be used to return valuetype address. */
 542                         assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
 543
 544                         arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 545                         arg_info->offset = *stack_size;
 546                         *stack_size += arg_size;
 547                 }
 548         }
 549 }
 550
 551 static void
 552 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
 553 {
 554         *arg_size = 0;
 555         *arg_class = ARG_CLASS_NO_CLASS;
 556
 557         assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
 558
 559         if (pinvoke) {
 560                 /* Calculate argument class type and size of marshalled type. */
 561                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 562                 *arg_size = info->native_size;
 563         } else {
 564                 /* Calculate argument class type and size of managed type. */
 565                 *arg_size = mono_class_value_size (klass, NULL);
 566         }
 567
 568         /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
 569         *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
 570
 571         if (*arg_class == ARG_CLASS_MEMORY) {
 572                 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
 573                 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
 574         }
 575
 576         /*
 577         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 578         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 579         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 580         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 581         * it must be represented in call and cannot be dropped.
 582         */
 583         if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
 584                 arg_info->pass_empty_struct = TRUE;
 585                 *arg_size = SIZEOF_REGISTER;
 586                 *arg_class = ARG_CLASS_INTEGER;
 587         }
 588
 589         assert (*arg_class != ARG_CLASS_NO_CLASS);
 590 }
 591
 592 static void
 593 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
 594                                                 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 595 {
 596         guint32 arg_size = SIZEOF_REGISTER;
 597         MonoClass *klass = NULL;
 598         ArgumentClass arg_class;
 599
 600         assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 601
 602         klass = mono_class_from_mono_type (type);
 603         get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
 604
 605         /* Only drop value type if its not an empty struct as input that must be represented in call */
 606         if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
 607                 arg_info->storage = ArgValuetypeInReg;
 608                 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 609         } else {
 610                 /* Alocate storage for value type. */
 611                 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
 612         }
 613 }
 614
 615 #endif /* TARGET_WIN32 */
 616
 617 static void
 618 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 619                            gboolean is_return,
 620                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 621 {
 622 #ifdef TARGET_WIN32
 623         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 624 #else
 625         guint32 size, quad, nquads, i, nfields;
 626         /* Keep track of the size used in each quad so we can */
 627         /* use the right size when copying args/return vars.  */
 628         guint32 quadsize [2] = {8, 8};
 629         ArgumentClass args [2];
 630         StructFieldInfo *fields = NULL;
 631         GArray *fields_array;
 632         MonoClass *klass;
 633         gboolean pass_on_stack = FALSE;
 634         int struct_size;
 635
 636         klass = mono_class_from_mono_type (type);
 637         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 638
 639         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 640                 /* We pass and return vtypes of size 8 in a register */
 641         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 642                 pass_on_stack = TRUE;
 643         }
 644
 645         /* If this struct can't be split up naturally into 8-byte */
 646         /* chunks (registers), pass it on the stack.              */
 647         if (sig->pinvoke) {
 648                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 649                 g_assert (info);
 650                 struct_size = info->native_size;
 651         } else {
 652                 struct_size = mono_class_value_size (klass, NULL);
 653         }
 654         /*
 655          * Collect field information recursively to be able to
 656          * handle nested structures.
 657          */
 658         fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
 659         collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
 660         fields = (StructFieldInfo*)fields_array->data;
 661         nfields = fields_array->len;
 662
 663         for (i = 0; i < nfields; ++i) {
 664                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 665                         pass_on_stack = TRUE;
 666                         break;
 667                 }
 668         }
 669
 670         if (size == 0) {
 671                 ainfo->storage = ArgValuetypeInReg;
 672                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 673                 return;
 674         }
 675
 676         if (pass_on_stack) {
 677                 /* Allways pass in memory */
 678                 ainfo->offset = *stack_size;
 679                 *stack_size += ALIGN_TO (size, 8);
 680                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 681                 if (!is_return)
 682                         ainfo->arg_size = ALIGN_TO (size, 8);
 683
 684                 g_array_free (fields_array, TRUE);
 685                 return;
 686         }
 687
 688         if (size > 8)
 689                 nquads = 2;
 690         else
 691                 nquads = 1;
 692
 693         if (!sig->pinvoke) {
 694                 int n = mono_class_value_size (klass, NULL);
 695
 696                 quadsize [0] = n >= 8 ? 8 : n;
 697                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 698
 699                 /* Always pass in 1 or 2 integer registers */
 700                 args [0] = ARG_CLASS_INTEGER;
 701                 args [1] = ARG_CLASS_INTEGER;
 702                 /* Only the simplest cases are supported */
 703                 if (is_return && nquads != 1) {
 704                         args [0] = ARG_CLASS_MEMORY;
 705                         args [1] = ARG_CLASS_MEMORY;
 706                 }
 707         } else {
 708                 /*
 709                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 710                  * The X87 and SSEUP stuff is left out since there are no such types in
 711                  * the CLR.
 712                  */
 713                 if (!nfields) {
 714                         ainfo->storage = ArgValuetypeInReg;
 715                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 716                         return;
 717                 }
 718
 719                 if (struct_size > 16) {
 720                         ainfo->offset = *stack_size;
 721                         *stack_size += ALIGN_TO (struct_size, 8);
 722                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 723                         if (!is_return)
 724                                 ainfo->arg_size = ALIGN_TO (struct_size, 8);
 725
 726                         g_array_free (fields_array, TRUE);
 727                         return;
 728                 }
 729
 730                 args [0] = ARG_CLASS_NO_CLASS;
 731                 args [1] = ARG_CLASS_NO_CLASS;
 732                 for (quad = 0; quad < nquads; ++quad) {
 733                         ArgumentClass class1;
 734
 735                         if (nfields == 0)
 736                                 class1 = ARG_CLASS_MEMORY;
 737                         else
 738                                 class1 = ARG_CLASS_NO_CLASS;
 739                         for (i = 0; i < nfields; ++i) {
 740                                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 741                                         /* Unaligned field */
 742                                         NOT_IMPLEMENTED;
 743                                 }
 744
 745                                 /* Skip fields in other quad */
 746                                 if ((quad == 0) && (fields [i].offset >= 8))
 747                                         continue;
 748                                 if ((quad == 1) && (fields [i].offset < 8))
 749                                         continue;
 750
 751                                 /* How far into this quad this data extends.*/
 752                                 /* (8 is size of quad) */
 753                                 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
 754
 755                                 class1 = merge_argument_class_from_type (fields [i].type, class1);
 756                         }
 757                         /* Empty structs have a nonzero size, causing this assert to be hit */
 758                         if (sig->pinvoke)
 759                                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 760                         args [quad] = class1;
 761                 }
 762         }
 763
 764         g_array_free (fields_array, TRUE);
 765
 766         /* Post merger cleanup */
 767         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 768                 args [0] = args [1] = ARG_CLASS_MEMORY;
 769
 770         /* Allocate registers */
 771         {
 772                 int orig_gr = *gr;
 773                 int orig_fr = *fr;
 774
 775                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 776                         quadsize [0] ++;
 777                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 778                         quadsize [1] ++;
 779
 780                 ainfo->storage = ArgValuetypeInReg;
 781                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 782                 g_assert (quadsize [0] <= 8);
 783                 g_assert (quadsize [1] <= 8);
 784                 ainfo->pair_size [0] = quadsize [0];
 785                 ainfo->pair_size [1] = quadsize [1];
 786                 ainfo->nregs = nquads;
 787                 for (quad = 0; quad < nquads; ++quad) {
 788                         switch (args [quad]) {
 789                         case ARG_CLASS_INTEGER:
 790                                 if (*gr >= PARAM_REGS)
 791                                         args [quad] = ARG_CLASS_MEMORY;
 792                                 else {
 793                                         ainfo->pair_storage [quad] = ArgInIReg;
 794                                         if (is_return)
 795                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 796                                         else
 797                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 798                                         (*gr) ++;
 799                                 }
 800                                 break;
 801                         case ARG_CLASS_SSE:
 802                                 if (*fr >= FLOAT_PARAM_REGS)
 803                                         args [quad] = ARG_CLASS_MEMORY;
 804                                 else {
 805                                         if (quadsize[quad] <= 4)
 806                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 807                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 808                                         ainfo->pair_regs [quad] = *fr;
 809                                         (*fr) ++;
 810                                 }
 811                                 break;
 812                         case ARG_CLASS_MEMORY:
 813                                 break;
 814                         case ARG_CLASS_NO_CLASS:
 815                                 break;
 816                         default:
 817                                 g_assert_not_reached ();
 818                         }
 819                 }
 820
 821                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 822                         int arg_size;
 823                         /* Revert possible register assignments */
 824                         *gr = orig_gr;
 825                         *fr = orig_fr;
 826
 827                         ainfo->offset = *stack_size;
 828                         if (sig->pinvoke)
 829                                 arg_size = ALIGN_TO (struct_size, 8);
 830                         else
 831                                 arg_size = nquads * sizeof(mgreg_t);
 832                         *stack_size += arg_size;
 833                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 834                         if (!is_return)
 835                                 ainfo->arg_size = arg_size;
 836                 }
 837         }
 838 #endif /* !TARGET_WIN32 */
 839 }
 840
 841 /*
 842  * get_call_info:
 843  *
 844  * Obtain information about a call according to the calling convention.
 845  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 846  * Draft Version 0.23" document for more information.
 847  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 848  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 849  */
 850 static CallInfo*
 851 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 852 {
 853         guint32 i, gr, fr, pstart;
 854         MonoType *ret_type;
 855         int n = sig->hasthis + sig->param_count;
 856         guint32 stack_size = 0;
 857         CallInfo *cinfo;
 858         gboolean is_pinvoke = sig->pinvoke;
 859
 860         if (mp)
 861                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 862         else
 863                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 864
 865         cinfo->nargs = n;
 866         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 867
 868         gr = 0;
 869         fr = 0;
 870
 871 #ifdef TARGET_WIN32
 872         /* Reserve space where the callee can save the argument registers */
 873         stack_size = 4 * sizeof (mgreg_t);
 874 #endif
 875
 876         /* return value */
 877         ret_type = mini_get_underlying_type (sig->ret);
 878         switch (ret_type->type) {
 879         case MONO_TYPE_I1:
 880         case MONO_TYPE_U1:
 881         case MONO_TYPE_I2:
 882         case MONO_TYPE_U2:
 883         case MONO_TYPE_I4:
 884         case MONO_TYPE_U4:
 885         case MONO_TYPE_I:
 886         case MONO_TYPE_U:
 887         case MONO_TYPE_PTR:
 888         case MONO_TYPE_FNPTR:
 889         case MONO_TYPE_OBJECT:
 890                 cinfo->ret.storage = ArgInIReg;
 891                 cinfo->ret.reg = AMD64_RAX;
 892                 break;
 893         case MONO_TYPE_U8:
 894         case MONO_TYPE_I8:
 895                 cinfo->ret.storage = ArgInIReg;
 896                 cinfo->ret.reg = AMD64_RAX;
 897                 break;
 898         case MONO_TYPE_R4:
 899                 cinfo->ret.storage = ArgInFloatSSEReg;
 900                 cinfo->ret.reg = AMD64_XMM0;
 901                 break;
 902         case MONO_TYPE_R8:
 903                 cinfo->ret.storage = ArgInDoubleSSEReg;
 904                 cinfo->ret.reg = AMD64_XMM0;
 905                 break;
 906         case MONO_TYPE_GENERICINST:
 907                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 908                         cinfo->ret.storage = ArgInIReg;
 909                         cinfo->ret.reg = AMD64_RAX;
 910                         break;
 911                 }
 912                 if (mini_is_gsharedvt_type (ret_type)) {
 913                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 914                         break;
 915                 }
 916                 /* fall through */
 917         case MONO_TYPE_VALUETYPE:
 918         case MONO_TYPE_TYPEDBYREF: {
 919                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 920
 921                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 922                 g_assert (cinfo->ret.storage != ArgInIReg);
 923                 break;
 924         }
 925         case MONO_TYPE_VAR:
 926         case MONO_TYPE_MVAR:
 927                 g_assert (mini_is_gsharedvt_type (ret_type));
 928                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 929                 break;
 930         case MONO_TYPE_VOID:
 931                 break;
 932         default:
 933                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 934         }
 935
 936         pstart = 0;
 937         /*
 938          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 939          * the first argument, allowing 'this' to be always passed in the first arg reg.
 940          * Also do this if the first argument is a reference type, since virtual calls
 941          * are sometimes made using calli without sig->hasthis set, like in the delegate
 942          * invoke wrappers.
 943          */
 944         ArgStorage ret_storage = cinfo->ret.storage;
 945         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 946                 if (sig->hasthis) {
 947                         add_general (&gr, &stack_size, cinfo->args + 0);
 948                 } else {
 949                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 950                         pstart = 1;
 951                 }
 952                 add_general (&gr, &stack_size, &cinfo->ret);
 953                 cinfo->ret.storage = ret_storage;
 954                 cinfo->vret_arg_index = 1;
 955         } else {
 956                 /* this */
 957                 if (sig->hasthis)
 958                         add_general (&gr, &stack_size, cinfo->args + 0);
 959
 960                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 961                         add_general (&gr, &stack_size, &cinfo->ret);
 962                         cinfo->ret.storage = ret_storage;
 963                 }
 964         }
 965
 966         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 967                 gr = PARAM_REGS;
 968                 fr = FLOAT_PARAM_REGS;
 969
 970                 /* Emit the signature cookie just before the implicit arguments */
 971                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 972         }
 973
 974         for (i = pstart; i < sig->param_count; ++i) {
 975                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 976                 MonoType *ptype;
 977
 978 #ifdef TARGET_WIN32
 979                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 980                 if (gr > fr)
 981                         fr = gr;
 982                 else if (fr > gr)
 983                         gr = fr;
 984 #endif
 985
 986                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 987                         /* We allways pass the sig cookie on the stack for simplicity */
 988                         /*
 989                          * Prevent implicit arguments + the sig cookie from being passed
 990                          * in registers.
 991                          */
 992                         gr = PARAM_REGS;
 993                         fr = FLOAT_PARAM_REGS;
 994
 995                         /* Emit the signature cookie just before the implicit arguments */
 996                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 997                 }
 998
 999                 ptype = mini_get_underlying_type (sig->params [i]);
1000                 switch (ptype->type) {
1001                 case MONO_TYPE_I1:
1002                 case MONO_TYPE_U1:
1003                         add_general (&gr, &stack_size, ainfo);
1004                         break;
1005                 case MONO_TYPE_I2:
1006                 case MONO_TYPE_U2:
1007                         add_general (&gr, &stack_size, ainfo);
1008                         break;
1009                 case MONO_TYPE_I4:
1010                 case MONO_TYPE_U4:
1011                         add_general (&gr, &stack_size, ainfo);
1012                         break;
1013                 case MONO_TYPE_I:
1014                 case MONO_TYPE_U:
1015                 case MONO_TYPE_PTR:
1016                 case MONO_TYPE_FNPTR:
1017                 case MONO_TYPE_OBJECT:
1018                         add_general (&gr, &stack_size, ainfo);
1019                         break;
1020                 case MONO_TYPE_GENERICINST:
1021                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1022                                 add_general (&gr, &stack_size, ainfo);
1023                                 break;
1024                         }
1025                         if (mini_is_gsharedvt_variable_type (ptype)) {
1026                                 /* gsharedvt arguments are passed by ref */
1027                                 add_general (&gr, &stack_size, ainfo);
1028                                 if (ainfo->storage == ArgInIReg)
1029                                         ainfo->storage = ArgGSharedVtInReg;
1030                                 else
1031                                         ainfo->storage = ArgGSharedVtOnStack;
1032                                 break;
1033                         }
1034                         /* fall through */
1035                 case MONO_TYPE_VALUETYPE:
1036                 case MONO_TYPE_TYPEDBYREF:
1037                         add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1038                         break;
1039                 case MONO_TYPE_U8:
1040
1041                 case MONO_TYPE_I8:
1042                         add_general (&gr, &stack_size, ainfo);
1043                         break;
1044                 case MONO_TYPE_R4:
1045                         add_float (&fr, &stack_size, ainfo, FALSE);
1046                         break;
1047                 case MONO_TYPE_R8:
1048                         add_float (&fr, &stack_size, ainfo, TRUE);
1049                         break;
1050                 case MONO_TYPE_VAR:
1051                 case MONO_TYPE_MVAR:
1052                         /* gsharedvt arguments are passed by ref */
1053                         g_assert (mini_is_gsharedvt_type (ptype));
1054                         add_general (&gr, &stack_size, ainfo);
1055                         if (ainfo->storage == ArgInIReg)
1056                                 ainfo->storage = ArgGSharedVtInReg;
1057                         else
1058                                 ainfo->storage = ArgGSharedVtOnStack;
1059                         break;
1060                 default:
1061                         g_assert_not_reached ();
1062                 }
1063         }
1064
1065         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1066                 gr = PARAM_REGS;
1067                 fr = FLOAT_PARAM_REGS;
1068
1069                 /* Emit the signature cookie just before the implicit arguments */
1070                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1071         }
1072
1073         cinfo->stack_usage = stack_size;
1074         cinfo->reg_usage = gr;
1075         cinfo->freg_usage = fr;
1076         return cinfo;
1077 }
1078
1079 /*
1080  * mono_arch_get_argument_info:
1081  * @csig:  a method signature
1082  * @param_count: the number of parameters to consider
1083  * @arg_info: an array to store the result infos
1084  *
1085  * Gathers information on parameters such as size, alignment and
1086  * padding. arg_info should be large enought to hold param_count + 1 entries.
1087  *
1088  * Returns the size of the argument area on the stack.
1089  */
1090 int
1091 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1092 {
1093         int k;
1094         CallInfo *cinfo = get_call_info (NULL, csig);
1095         guint32 args_size = cinfo->stack_usage;
1096
1097         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1098         if (csig->hasthis) {
1099                 arg_info [0].offset = 0;
1100         }
1101
1102         for (k = 0; k < param_count; k++) {
1103                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1104                 /* FIXME: */
1105                 arg_info [k + 1].size = 0;
1106         }
1107
1108         g_free (cinfo);
1109
1110         return args_size;
1111 }
1112
1113 gboolean
1114 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1115 {
1116         CallInfo *c1, *c2;
1117         gboolean res;
1118         MonoType *callee_ret;
1119
1120         c1 = get_call_info (NULL, caller_sig);
1121         c2 = get_call_info (NULL, callee_sig);
1122         res = c1->stack_usage >= c2->stack_usage;
1123         callee_ret = mini_get_underlying_type (callee_sig->ret);
1124         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1125                 /* An address on the callee's stack is passed as the first argument */
1126                 res = FALSE;
1127
1128         g_free (c1);
1129         g_free (c2);
1130
1131         return res;
1132 }
1133
1134 /*
1135  * Initialize the cpu to execute managed code.
1136  */
1137 void
1138 mono_arch_cpu_init (void)
1139 {
1140 #ifndef _MSC_VER
1141         guint16 fpcw;
1142
1143         /* spec compliance requires running with double precision */
1144         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1145         fpcw &= ~X86_FPCW_PRECC_MASK;
1146         fpcw |= X86_FPCW_PREC_DOUBLE;
1147         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1148         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1149 #else
1150         /* TODO: This is crashing on Win64 right now.
1151         * _control87 (_PC_53, MCW_PC);
1152         */
1153 #endif
1154 }
1155
1156 /*
1157  * Initialize architecture specific code.
1158  */
1159 void
1160 mono_arch_init (void)
1161 {
1162         mono_os_mutex_init_recursive (&mini_arch_mutex);
1163
1164         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1165         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1166         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1167         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1168         mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1169
1170 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1171         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1172 #endif
1173
1174         if (!mono_aot_only)
1175                 bp_trampoline = mini_get_breakpoint_trampoline ();
1176 }
1177
1178 /*
1179  * Cleanup architecture specific code.
1180  */
1181 void
1182 mono_arch_cleanup (void)
1183 {
1184         mono_os_mutex_destroy (&mini_arch_mutex);
1185 }
1186
1187 /*
1188  * This function returns the optimizations supported on this cpu.
1189  */
1190 guint32
1191 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1192 {
1193         guint32 opts = 0;
1194
1195         *exclude_mask = 0;
1196
1197         if (mono_hwcap_x86_has_cmov) {
1198                 opts |= MONO_OPT_CMOV;
1199
1200                 if (mono_hwcap_x86_has_fcmov)
1201                         opts |= MONO_OPT_FCMOV;
1202                 else
1203                         *exclude_mask |= MONO_OPT_FCMOV;
1204         } else {
1205                 *exclude_mask |= MONO_OPT_CMOV;
1206         }
1207
1208 #ifdef TARGET_WIN32
1209         /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1210         /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1211         /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1212         /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1213         /* will now have a reference to an argument that won't be fully decomposed. */
1214         *exclude_mask |= MONO_OPT_SIMD;
1215 #endif
1216
1217         return opts;
1218 }
1219
1220 /*
1221  * This function test for all SSE functions supported.
1222  *
1223  * Returns a bitmask corresponding to all supported versions.
1224  *
1225  */
1226 guint32
1227 mono_arch_cpu_enumerate_simd_versions (void)
1228 {
1229         guint32 sse_opts = 0;
1230
1231         if (mono_hwcap_x86_has_sse1)
1232                 sse_opts |= SIMD_VERSION_SSE1;
1233
1234         if (mono_hwcap_x86_has_sse2)
1235                 sse_opts |= SIMD_VERSION_SSE2;
1236
1237         if (mono_hwcap_x86_has_sse3)
1238                 sse_opts |= SIMD_VERSION_SSE3;
1239
1240         if (mono_hwcap_x86_has_ssse3)
1241                 sse_opts |= SIMD_VERSION_SSSE3;
1242
1243         if (mono_hwcap_x86_has_sse41)
1244                 sse_opts |= SIMD_VERSION_SSE41;
1245
1246         if (mono_hwcap_x86_has_sse42)
1247                 sse_opts |= SIMD_VERSION_SSE42;
1248
1249         if (mono_hwcap_x86_has_sse4a)
1250                 sse_opts |= SIMD_VERSION_SSE4a;
1251
1252         return sse_opts;
1253 }
1254
1255 #ifndef DISABLE_JIT
1256
1257 GList *
1258 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1259 {
1260         GList *vars = NULL;
1261         int i;
1262
1263         for (i = 0; i < cfg->num_varinfo; i++) {
1264                 MonoInst *ins = cfg->varinfo [i];
1265                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1266
1267                 /* unused vars */
1268                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1269                         continue;
1270
1271                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1272                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1273                         continue;
1274
1275                 if (mono_is_regsize_var (ins->inst_vtype)) {
1276                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1277                         g_assert (i == vmv->idx);
1278                         vars = g_list_prepend (vars, vmv);
1279                 }
1280         }
1281
1282         vars = mono_varlist_sort (cfg, vars, 0);
1283
1284         return vars;
1285 }
1286
1287 /**
1288  * mono_arch_compute_omit_fp:
1289  * Determine whether the frame pointer can be eliminated.
1290  */
1291 static void
1292 mono_arch_compute_omit_fp (MonoCompile *cfg)
1293 {
1294         MonoMethodSignature *sig;
1295         MonoMethodHeader *header;
1296         int i, locals_size;
1297         CallInfo *cinfo;
1298
1299         if (cfg->arch.omit_fp_computed)
1300                 return;
1301
1302         header = cfg->header;
1303
1304         sig = mono_method_signature (cfg->method);
1305
1306         if (!cfg->arch.cinfo)
1307                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1308         cinfo = (CallInfo *)cfg->arch.cinfo;
1309
1310         /*
1311          * FIXME: Remove some of the restrictions.
1312          */
1313         cfg->arch.omit_fp = TRUE;
1314         cfg->arch.omit_fp_computed = TRUE;
1315
1316         if (cfg->disable_omit_fp)
1317                 cfg->arch.omit_fp = FALSE;
1318
1319         if (!debug_omit_fp ())
1320                 cfg->arch.omit_fp = FALSE;
1321         /*
1322         if (cfg->method->save_lmf)
1323                 cfg->arch.omit_fp = FALSE;
1324         */
1325         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1326                 cfg->arch.omit_fp = FALSE;
1327         if (header->num_clauses)
1328                 cfg->arch.omit_fp = FALSE;
1329         if (cfg->param_area)
1330                 cfg->arch.omit_fp = FALSE;
1331         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1332                 cfg->arch.omit_fp = FALSE;
1333         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1334                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1335                 cfg->arch.omit_fp = FALSE;
1336         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1337                 ArgInfo *ainfo = &cinfo->args [i];
1338
1339                 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1340                         /*
1341                          * The stack offset can only be determined when the frame
1342                          * size is known.
1343                          */
1344                         cfg->arch.omit_fp = FALSE;
1345                 }
1346         }
1347
1348         locals_size = 0;
1349         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1350                 MonoInst *ins = cfg->varinfo [i];
1351                 int ialign;
1352
1353                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1354         }
1355 }
1356
1357 GList *
1358 mono_arch_get_global_int_regs (MonoCompile *cfg)
1359 {
1360         GList *regs = NULL;
1361
1362         mono_arch_compute_omit_fp (cfg);
1363
1364         if (cfg->arch.omit_fp)
1365                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1366
1367         /* We use the callee saved registers for global allocation */
1368         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1369         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1370         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1371         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1372         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1373 #ifdef TARGET_WIN32
1374         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1375         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1376 #endif
1377
1378         return regs;
1379 }
1380
1381 GList*
1382 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1383 {
1384         GList *regs = NULL;
1385         int i;
1386
1387         /* All XMM registers */
1388         for (i = 0; i < 16; ++i)
1389                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1390
1391         return regs;
1392 }
1393
1394 GList*
1395 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1396 {
1397         static GList *r = NULL;
1398
1399         if (r == NULL) {
1400                 GList *regs = NULL;
1401
1402                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1403                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1404                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1405                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1406                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1407                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1408
1409                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1410                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1411                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1412                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1413                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1414                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1415                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1416                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1417
1418                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1419         }
1420
1421         return r;
1422 }
1423
1424 GList*
1425 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1426 {
1427         int i;
1428         static GList *r = NULL;
1429
1430         if (r == NULL) {
1431                 GList *regs = NULL;
1432
1433                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1434                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1435
1436                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1437         }
1438
1439         return r;
1440 }
1441
1442 /*
1443  * mono_arch_regalloc_cost:
1444  *
1445  *  Return the cost, in number of memory references, of the action of
1446  * allocating the variable VMV into a register during global register
1447  * allocation.
1448  */
1449 guint32
1450 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1451 {
1452         MonoInst *ins = cfg->varinfo [vmv->idx];
1453
1454         if (cfg->method->save_lmf)
1455                 /* The register is already saved */
1456                 /* substract 1 for the invisible store in the prolog */
1457                 return (ins->opcode == OP_ARG) ? 0 : 1;
1458         else
1459                 /* push+pop */
1460                 return (ins->opcode == OP_ARG) ? 1 : 2;
1461 }
1462
1463 /*
1464  * mono_arch_fill_argument_info:
1465  *
1466  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1467  * of the method.
1468  */
1469 void
1470 mono_arch_fill_argument_info (MonoCompile *cfg)
1471 {
1472         MonoType *sig_ret;
1473         MonoMethodSignature *sig;
1474         MonoInst *ins;
1475         int i;
1476         CallInfo *cinfo;
1477
1478         sig = mono_method_signature (cfg->method);
1479
1480         cinfo = (CallInfo *)cfg->arch.cinfo;
1481         sig_ret = mini_get_underlying_type (sig->ret);
1482
1483         /*
1484          * Contrary to mono_arch_allocate_vars (), the information should describe
1485          * where the arguments are at the beginning of the method, not where they can be
1486          * accessed during the execution of the method. The later makes no sense for the
1487          * global register allocator, since a variable can be in more than one location.
1488          */
1489         switch (cinfo->ret.storage) {
1490         case ArgInIReg:
1491         case ArgInFloatSSEReg:
1492         case ArgInDoubleSSEReg:
1493                 cfg->ret->opcode = OP_REGVAR;
1494                 cfg->ret->inst_c0 = cinfo->ret.reg;
1495                 break;
1496         case ArgValuetypeInReg:
1497                 cfg->ret->opcode = OP_REGOFFSET;
1498                 cfg->ret->inst_basereg = -1;
1499                 cfg->ret->inst_offset = -1;
1500                 break;
1501         case ArgNone:
1502                 break;
1503         default:
1504                 g_assert_not_reached ();
1505         }
1506
1507         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1508                 ArgInfo *ainfo = &cinfo->args [i];
1509
1510                 ins = cfg->args [i];
1511
1512                 switch (ainfo->storage) {
1513                 case ArgInIReg:
1514                 case ArgInFloatSSEReg:
1515                 case ArgInDoubleSSEReg:
1516                         ins->opcode = OP_REGVAR;
1517                         ins->inst_c0 = ainfo->reg;
1518                         break;
1519                 case ArgOnStack:
1520                         ins->opcode = OP_REGOFFSET;
1521                         ins->inst_basereg = -1;
1522                         ins->inst_offset = -1;
1523                         break;
1524                 case ArgValuetypeInReg:
1525                         /* Dummy */
1526                         ins->opcode = OP_NOP;
1527                         break;
1528                 default:
1529                         g_assert_not_reached ();
1530                 }
1531         }
1532 }
1533
1534 void
1535 mono_arch_allocate_vars (MonoCompile *cfg)
1536 {
1537         MonoType *sig_ret;
1538         MonoMethodSignature *sig;
1539         MonoInst *ins;
1540         int i, offset;
1541         guint32 locals_stack_size, locals_stack_align;
1542         gint32 *offsets;
1543         CallInfo *cinfo;
1544
1545         sig = mono_method_signature (cfg->method);
1546
1547         cinfo = (CallInfo *)cfg->arch.cinfo;
1548         sig_ret = mini_get_underlying_type (sig->ret);
1549
1550         mono_arch_compute_omit_fp (cfg);
1551
1552         /*
1553          * We use the ABI calling conventions for managed code as well.
1554          * Exception: valuetypes are only sometimes passed or returned in registers.
1555          */
1556
1557         /*
1558          * The stack looks like this:
1559          * <incoming arguments passed on the stack>
1560          * <return value>
1561          * <lmf/caller saved registers>
1562          * <locals>
1563          * <spill area>
1564          * <localloc area>  -> grows dynamically
1565          * <params area>
1566          */
1567
1568         if (cfg->arch.omit_fp) {
1569                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1570                 cfg->frame_reg = AMD64_RSP;
1571                 offset = 0;
1572         } else {
1573                 /* Locals are allocated backwards from %fp */
1574                 cfg->frame_reg = AMD64_RBP;
1575                 offset = 0;
1576         }
1577
1578         cfg->arch.saved_iregs = cfg->used_int_regs;
1579         if (cfg->method->save_lmf) {
1580                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1581                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1582                 cfg->arch.saved_iregs |= iregs_to_save;
1583         }
1584
1585         if (cfg->arch.omit_fp)
1586                 cfg->arch.reg_save_area_offset = offset;
1587         /* Reserve space for callee saved registers */
1588         for (i = 0; i < AMD64_NREG; ++i)
1589                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1590                         offset += sizeof(mgreg_t);
1591                 }
1592         if (!cfg->arch.omit_fp)
1593                 cfg->arch.reg_save_area_offset = -offset;
1594
1595         if (sig_ret->type != MONO_TYPE_VOID) {
1596                 switch (cinfo->ret.storage) {
1597                 case ArgInIReg:
1598                 case ArgInFloatSSEReg:
1599                 case ArgInDoubleSSEReg:
1600                         cfg->ret->opcode = OP_REGVAR;
1601                         cfg->ret->inst_c0 = cinfo->ret.reg;
1602                         cfg->ret->dreg = cinfo->ret.reg;
1603                         break;
1604                 case ArgValuetypeAddrInIReg:
1605                 case ArgGsharedvtVariableInReg:
1606                         /* The register is volatile */
1607                         cfg->vret_addr->opcode = OP_REGOFFSET;
1608                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1609                         if (cfg->arch.omit_fp) {
1610                                 cfg->vret_addr->inst_offset = offset;
1611                                 offset += 8;
1612                         } else {
1613                                 offset += 8;
1614                                 cfg->vret_addr->inst_offset = -offset;
1615                         }
1616                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1617                                 printf ("vret_addr =");
1618                                 mono_print_ins (cfg->vret_addr);
1619                         }
1620                         break;
1621                 case ArgValuetypeInReg:
1622                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1623                         cfg->ret->opcode = OP_REGOFFSET;
1624                         cfg->ret->inst_basereg = cfg->frame_reg;
1625                         if (cfg->arch.omit_fp) {
1626                                 cfg->ret->inst_offset = offset;
1627                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1628                         } else {
1629                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1630                                 cfg->ret->inst_offset = - offset;
1631                         }
1632                         break;
1633                 default:
1634                         g_assert_not_reached ();
1635                 }
1636         }
1637
1638         /* Allocate locals */
1639         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1640         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1641                 char *mname = mono_method_full_name (cfg->method, TRUE);
1642                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1643                 g_free (mname);
1644                 return;
1645         }
1646
1647         if (locals_stack_align) {
1648                 offset += (locals_stack_align - 1);
1649                 offset &= ~(locals_stack_align - 1);
1650         }
1651         if (cfg->arch.omit_fp) {
1652                 cfg->locals_min_stack_offset = offset;
1653                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1654         } else {
1655                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1656                 cfg->locals_max_stack_offset = - offset;
1657         }
1658
1659         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1660                 if (offsets [i] != -1) {
1661                         MonoInst *ins = cfg->varinfo [i];
1662                         ins->opcode = OP_REGOFFSET;
1663                         ins->inst_basereg = cfg->frame_reg;
1664                         if (cfg->arch.omit_fp)
1665                                 ins->inst_offset = (offset + offsets [i]);
1666                         else
1667                                 ins->inst_offset = - (offset + offsets [i]);
1668                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1669                 }
1670         }
1671         offset += locals_stack_size;
1672
1673         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1674                 g_assert (!cfg->arch.omit_fp);
1675                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1676                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1677         }
1678
1679         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1680                 ins = cfg->args [i];
1681                 if (ins->opcode != OP_REGVAR) {
1682                         ArgInfo *ainfo = &cinfo->args [i];
1683                         gboolean inreg = TRUE;
1684
1685                         /* FIXME: Allocate volatile arguments to registers */
1686                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1687                                 inreg = FALSE;
1688
1689                         /*
1690                          * Under AMD64, all registers used to pass arguments to functions
1691                          * are volatile across calls.
1692                          * FIXME: Optimize this.
1693                          */
1694                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1695                                 inreg = FALSE;
1696
1697                         ins->opcode = OP_REGOFFSET;
1698
1699                         switch (ainfo->storage) {
1700                         case ArgInIReg:
1701                         case ArgInFloatSSEReg:
1702                         case ArgInDoubleSSEReg:
1703                         case ArgGSharedVtInReg:
1704                                 if (inreg) {
1705                                         ins->opcode = OP_REGVAR;
1706                                         ins->dreg = ainfo->reg;
1707                                 }
1708                                 break;
1709                         case ArgOnStack:
1710                         case ArgGSharedVtOnStack:
1711                                 g_assert (!cfg->arch.omit_fp);
1712                                 ins->opcode = OP_REGOFFSET;
1713                                 ins->inst_basereg = cfg->frame_reg;
1714                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1715                                 break;
1716                         case ArgValuetypeInReg:
1717                                 break;
1718                         case ArgValuetypeAddrInIReg:
1719                         case ArgValuetypeAddrOnStack: {
1720                                 MonoInst *indir;
1721                                 g_assert (!cfg->arch.omit_fp);
1722                                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1723                                 MONO_INST_NEW (cfg, indir, 0);
1724
1725                                 indir->opcode = OP_REGOFFSET;
1726                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1727                                         indir->inst_basereg = cfg->frame_reg;
1728                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1729                                         offset += (sizeof (gpointer));
1730                                         indir->inst_offset = - offset;
1731                                 }
1732                                 else {
1733                                         indir->inst_basereg = cfg->frame_reg;
1734                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1735                                 }
1736
1737                                 ins->opcode = OP_VTARG_ADDR;
1738                                 ins->inst_left = indir;
1739
1740                                 break;
1741                         }
1742                         default:
1743                                 NOT_IMPLEMENTED;
1744                         }
1745
1746                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1747                                 ins->opcode = OP_REGOFFSET;
1748                                 ins->inst_basereg = cfg->frame_reg;
1749                                 /* These arguments are saved to the stack in the prolog */
1750                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1751                                 if (cfg->arch.omit_fp) {
1752                                         ins->inst_offset = offset;
1753                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1754                                         // Arguments are yet supported by the stack map creation code
1755                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1756                                 } else {
1757                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1758                                         ins->inst_offset = - offset;
1759                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1760                                 }
1761                         }
1762                 }
1763         }
1764
1765         cfg->stack_offset = offset;
1766 }
1767
1768 void
1769 mono_arch_create_vars (MonoCompile *cfg)
1770 {
1771         MonoMethodSignature *sig;
1772         CallInfo *cinfo;
1773         MonoType *sig_ret;
1774
1775         sig = mono_method_signature (cfg->method);
1776
1777         if (!cfg->arch.cinfo)
1778                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1779         cinfo = (CallInfo *)cfg->arch.cinfo;
1780
1781         if (cinfo->ret.storage == ArgValuetypeInReg)
1782                 cfg->ret_var_is_local = TRUE;
1783
1784         sig_ret = mini_get_underlying_type (sig->ret);
1785         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1786                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1787                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1788                         printf ("vret_addr = ");
1789                         mono_print_ins (cfg->vret_addr);
1790                 }
1791         }
1792
1793         if (cfg->gen_sdb_seq_points) {
1794                 MonoInst *ins;
1795
1796                 if (cfg->compile_aot) {
1797                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1798                         ins->flags |= MONO_INST_VOLATILE;
1799                         cfg->arch.seq_point_info_var = ins;
1800                 }
1801                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1802                 ins->flags |= MONO_INST_VOLATILE;
1803                 cfg->arch.ss_tramp_var = ins;
1804
1805                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1806                 ins->flags |= MONO_INST_VOLATILE;
1807                 cfg->arch.bp_tramp_var = ins;
1808         }
1809
1810         if (cfg->method->save_lmf)
1811                 cfg->create_lmf_var = TRUE;
1812
1813         if (cfg->method->save_lmf) {
1814                 cfg->lmf_ir = TRUE;
1815         }
1816 }
1817
1818 static void
1819 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1820 {
1821         MonoInst *ins;
1822
1823         switch (storage) {
1824         case ArgInIReg:
1825                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1826                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1827                 ins->sreg1 = tree->dreg;
1828                 MONO_ADD_INS (cfg->cbb, ins);
1829                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1830                 break;
1831         case ArgInFloatSSEReg:
1832                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1833                 ins->dreg = mono_alloc_freg (cfg);
1834                 ins->sreg1 = tree->dreg;
1835                 MONO_ADD_INS (cfg->cbb, ins);
1836
1837                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1838                 break;
1839         case ArgInDoubleSSEReg:
1840                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1841                 ins->dreg = mono_alloc_freg (cfg);
1842                 ins->sreg1 = tree->dreg;
1843                 MONO_ADD_INS (cfg->cbb, ins);
1844
1845                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1846
1847                 break;
1848         default:
1849                 g_assert_not_reached ();
1850         }
1851 }
1852
1853 static int
1854 arg_storage_to_load_membase (ArgStorage storage)
1855 {
1856         switch (storage) {
1857         case ArgInIReg:
1858 #if defined(__mono_ilp32__)
1859                 return OP_LOADI8_MEMBASE;
1860 #else
1861                 return OP_LOAD_MEMBASE;
1862 #endif
1863         case ArgInDoubleSSEReg:
1864                 return OP_LOADR8_MEMBASE;
1865         case ArgInFloatSSEReg:
1866                 return OP_LOADR4_MEMBASE;
1867         default:
1868                 g_assert_not_reached ();
1869         }
1870
1871         return -1;
1872 }
1873
1874 static void
1875 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1876 {
1877         MonoMethodSignature *tmp_sig;
1878         int sig_reg;
1879
1880         if (call->tail_call)
1881                 NOT_IMPLEMENTED;
1882
1883         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1884
1885         /*
1886          * mono_ArgIterator_Setup assumes the signature cookie is
1887          * passed first and all the arguments which were before it are
1888          * passed on the stack after the signature. So compensate by
1889          * passing a different signature.
1890          */
1891         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1892         tmp_sig->param_count -= call->signature->sentinelpos;
1893         tmp_sig->sentinelpos = 0;
1894         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1895
1896         sig_reg = mono_alloc_ireg (cfg);
1897         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1898
1899         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1900 }
1901
1902 #ifdef ENABLE_LLVM
1903 static inline LLVMArgStorage
1904 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1905 {
1906         switch (storage) {
1907         case ArgInIReg:
1908                 return LLVMArgInIReg;
1909         case ArgNone:
1910                 return LLVMArgNone;
1911         case ArgGSharedVtInReg:
1912         case ArgGSharedVtOnStack:
1913                 return LLVMArgGSharedVt;
1914         default:
1915                 g_assert_not_reached ();
1916                 return LLVMArgNone;
1917         }
1918 }
1919
1920 LLVMCallInfo*
1921 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1922 {
1923         int i, n;
1924         CallInfo *cinfo;
1925         ArgInfo *ainfo;
1926         int j;
1927         LLVMCallInfo *linfo;
1928         MonoType *t, *sig_ret;
1929
1930         n = sig->param_count + sig->hasthis;
1931         sig_ret = mini_get_underlying_type (sig->ret);
1932
1933         cinfo = get_call_info (cfg->mempool, sig);
1934
1935         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1936
1937         /*
1938          * LLVM always uses the native ABI while we use our own ABI, the
1939          * only difference is the handling of vtypes:
1940          * - we only pass/receive them in registers in some cases, and only
1941          *   in 1 or 2 integer registers.
1942          */
1943         switch (cinfo->ret.storage) {
1944         case ArgNone:
1945                 linfo->ret.storage = LLVMArgNone;
1946                 break;
1947         case ArgInIReg:
1948         case ArgInFloatSSEReg:
1949         case ArgInDoubleSSEReg:
1950                 linfo->ret.storage = LLVMArgNormal;
1951                 break;
1952         case ArgValuetypeInReg: {
1953                 ainfo = &cinfo->ret;
1954
1955                 if (sig->pinvoke &&
1956                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1957                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1958                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1959                         cfg->disable_llvm = TRUE;
1960                         return linfo;
1961                 }
1962
1963                 linfo->ret.storage = LLVMArgVtypeInReg;
1964                 for (j = 0; j < 2; ++j)
1965                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1966                 break;
1967         }
1968         case ArgValuetypeAddrInIReg:
1969         case ArgGsharedvtVariableInReg:
1970                 /* Vtype returned using a hidden argument */
1971                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1972                 linfo->vret_arg_index = cinfo->vret_arg_index;
1973                 break;
1974         default:
1975                 g_assert_not_reached ();
1976                 break;
1977         }
1978
1979         for (i = 0; i < n; ++i) {
1980                 ainfo = cinfo->args + i;
1981
1982                 if (i >= sig->hasthis)
1983                         t = sig->params [i - sig->hasthis];
1984                 else
1985                         t = &mono_defaults.int_class->byval_arg;
1986                 t = mini_type_get_underlying_type (t);
1987
1988                 linfo->args [i].storage = LLVMArgNone;
1989
1990                 switch (ainfo->storage) {
1991                 case ArgInIReg:
1992                         linfo->args [i].storage = LLVMArgNormal;
1993                         break;
1994                 case ArgInDoubleSSEReg:
1995                 case ArgInFloatSSEReg:
1996                         linfo->args [i].storage = LLVMArgNormal;
1997                         break;
1998                 case ArgOnStack:
1999                         if (MONO_TYPE_ISSTRUCT (t))
2000                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2001                         else
2002                                 linfo->args [i].storage = LLVMArgNormal;
2003                         break;
2004                 case ArgValuetypeInReg:
2005                         if (sig->pinvoke &&
2006                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2007                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2008                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2009                                 cfg->disable_llvm = TRUE;
2010                                 return linfo;
2011                         }
2012
2013                         linfo->args [i].storage = LLVMArgVtypeInReg;
2014                         for (j = 0; j < 2; ++j)
2015                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2016                         break;
2017                 case ArgGSharedVtInReg:
2018                 case ArgGSharedVtOnStack:
2019                         linfo->args [i].storage = LLVMArgGSharedVt;
2020                         break;
2021                 default:
2022                         cfg->exception_message = g_strdup ("ainfo->storage");
2023                         cfg->disable_llvm = TRUE;
2024                         break;
2025                 }
2026         }
2027
2028         return linfo;
2029 }
2030 #endif
2031
2032 void
2033 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2034 {
2035         MonoInst *arg, *in;
2036         MonoMethodSignature *sig;
2037         MonoType *sig_ret;
2038         int i, n;
2039         CallInfo *cinfo;
2040         ArgInfo *ainfo;
2041
2042         sig = call->signature;
2043         n = sig->param_count + sig->hasthis;
2044
2045         cinfo = get_call_info (cfg->mempool, sig);
2046
2047         sig_ret = sig->ret;
2048
2049         if (COMPILE_LLVM (cfg)) {
2050                 /* We shouldn't be called in the llvm case */
2051                 cfg->disable_llvm = TRUE;
2052                 return;
2053         }
2054
2055         /*
2056          * Emit all arguments which are passed on the stack to prevent register
2057          * allocation problems.
2058          */
2059         for (i = 0; i < n; ++i) {
2060                 MonoType *t;
2061                 ainfo = cinfo->args + i;
2062
2063                 in = call->args [i];
2064
2065                 if (sig->hasthis && i == 0)
2066                         t = &mono_defaults.object_class->byval_arg;
2067                 else
2068                         t = sig->params [i - sig->hasthis];
2069
2070                 t = mini_get_underlying_type (t);
2071                 //XXX what about ArgGSharedVtOnStack here?
2072                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2073                         if (!t->byref) {
2074                                 if (t->type == MONO_TYPE_R4)
2075                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2076                                 else if (t->type == MONO_TYPE_R8)
2077                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2078                                 else
2079                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2080                         } else {
2081                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2082                         }
2083                         if (cfg->compute_gc_maps) {
2084                                 MonoInst *def;
2085
2086                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2087                         }
2088                 }
2089         }
2090
2091         /*
2092          * Emit all parameters passed in registers in non-reverse order for better readability
2093          * and to help the optimization in emit_prolog ().
2094          */
2095         for (i = 0; i < n; ++i) {
2096                 ainfo = cinfo->args + i;
2097
2098                 in = call->args [i];
2099
2100                 if (ainfo->storage == ArgInIReg)
2101                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2102         }
2103
2104         for (i = n - 1; i >= 0; --i) {
2105                 MonoType *t;
2106
2107                 ainfo = cinfo->args + i;
2108
2109                 in = call->args [i];
2110
2111                 if (sig->hasthis && i == 0)
2112                         t = &mono_defaults.object_class->byval_arg;
2113                 else
2114                         t = sig->params [i - sig->hasthis];
2115                 t = mini_get_underlying_type (t);
2116
2117                 switch (ainfo->storage) {
2118                 case ArgInIReg:
2119                         /* Already done */
2120                         break;
2121                 case ArgInFloatSSEReg:
2122                 case ArgInDoubleSSEReg:
2123                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2124                         break;
2125                 case ArgOnStack:
2126                 case ArgValuetypeInReg:
2127                 case ArgValuetypeAddrInIReg:
2128                 case ArgValuetypeAddrOnStack:
2129                 case ArgGSharedVtInReg:
2130                 case ArgGSharedVtOnStack: {
2131                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2132                                 /* Already emitted above */
2133                                 break;
2134                         //FIXME what about ArgGSharedVtOnStack ?
2135                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2136                                 MonoInst *call_inst = (MonoInst*)call;
2137                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2138                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2139                                 break;
2140                         }
2141
2142                         guint32 align;
2143                         guint32 size;
2144
2145                         if (sig->pinvoke)
2146                                 size = mono_type_native_stack_size (t, &align);
2147                         else {
2148                                 /*
2149                                  * Other backends use mono_type_stack_size (), but that
2150                                  * aligns the size to 8, which is larger than the size of
2151                                  * the source, leading to reads of invalid memory if the
2152                                  * source is at the end of address space.
2153                                  */
2154                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2155                         }
2156
2157                         if (size >= 10000) {
2158                                 /* Avoid asserts in emit_memcpy () */
2159                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2160                                 /* Continue normally */
2161                         }
2162
2163                         if (size > 0 || ainfo->pass_empty_struct) {
2164                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2165                                 arg->sreg1 = in->dreg;
2166                                 arg->klass = mono_class_from_mono_type (t);
2167                                 arg->backend.size = size;
2168                                 arg->inst_p0 = call;
2169                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2170                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2171
2172                                 MONO_ADD_INS (cfg->cbb, arg);
2173                         }
2174                         break;
2175                 }
2176                 default:
2177                         g_assert_not_reached ();
2178                 }
2179
2180                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2181                         /* Emit the signature cookie just before the implicit arguments */
2182                         emit_sig_cookie (cfg, call, cinfo);
2183         }
2184
2185         /* Handle the case where there are no implicit arguments */
2186         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2187                 emit_sig_cookie (cfg, call, cinfo);
2188
2189         switch (cinfo->ret.storage) {
2190         case ArgValuetypeInReg:
2191                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2192                         /*
2193                          * Tell the JIT to use a more efficient calling convention: call using
2194                          * OP_CALL, compute the result location after the call, and save the
2195                          * result there.
2196                          */
2197                         call->vret_in_reg = TRUE;
2198                         /*
2199                          * Nullify the instruction computing the vret addr to enable
2200                          * future optimizations.
2201                          */
2202                         if (call->vret_var)
2203                                 NULLIFY_INS (call->vret_var);
2204                 } else {
2205                         if (call->tail_call)
2206                                 NOT_IMPLEMENTED;
2207                         /*
2208                          * The valuetype is in RAX:RDX after the call, need to be copied to
2209                          * the stack. Push the address here, so the call instruction can
2210                          * access it.
2211                          */
2212                         if (!cfg->arch.vret_addr_loc) {
2213                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2214                                 /* Prevent it from being register allocated or optimized away */
2215                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2216                         }
2217
2218                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2219                 }
2220                 break;
2221         case ArgValuetypeAddrInIReg:
2222         case ArgGsharedvtVariableInReg: {
2223                 MonoInst *vtarg;
2224                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2225                 vtarg->sreg1 = call->vret_var->dreg;
2226                 vtarg->dreg = mono_alloc_preg (cfg);
2227                 MONO_ADD_INS (cfg->cbb, vtarg);
2228
2229                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2230                 break;
2231         }
2232         default:
2233                 break;
2234         }
2235
2236         if (cfg->method->save_lmf) {
2237                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2238                 MONO_ADD_INS (cfg->cbb, arg);
2239         }
2240
2241         call->stack_usage = cinfo->stack_usage;
2242 }
2243
2244 void
2245 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2246 {
2247         MonoInst *arg;
2248         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2249         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2250         int size = ins->backend.size;
2251
2252         switch (ainfo->storage) {
2253         case ArgValuetypeInReg: {
2254                 MonoInst *load;
2255                 int part;
2256
2257                 for (part = 0; part < 2; ++part) {
2258                         if (ainfo->pair_storage [part] == ArgNone)
2259                                 continue;
2260
2261                         if (ainfo->pass_empty_struct) {
2262                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2263                                 NEW_ICONST (cfg, load, 0);
2264                         }
2265                         else {
2266                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2267                                 load->inst_basereg = src->dreg;
2268                                 load->inst_offset = part * sizeof(mgreg_t);
2269
2270                                 switch (ainfo->pair_storage [part]) {
2271                                 case ArgInIReg:
2272                                         load->dreg = mono_alloc_ireg (cfg);
2273                                         break;
2274                                 case ArgInDoubleSSEReg:
2275                                 case ArgInFloatSSEReg:
2276                                         load->dreg = mono_alloc_freg (cfg);
2277                                         break;
2278                                 default:
2279                                         g_assert_not_reached ();
2280                                 }
2281                         }
2282
2283                         MONO_ADD_INS (cfg->cbb, load);
2284
2285                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2286                 }
2287                 break;
2288         }
2289         case ArgValuetypeAddrInIReg:
2290         case ArgValuetypeAddrOnStack: {
2291                 MonoInst *vtaddr, *load;
2292
2293                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2294
2295                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2296
2297                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2298                 cfg->has_indirection = TRUE;
2299                 load->inst_p0 = vtaddr;
2300                 vtaddr->flags |= MONO_INST_INDIRECT;
2301                 load->type = STACK_MP;
2302                 load->klass = vtaddr->klass;
2303                 load->dreg = mono_alloc_ireg (cfg);
2304                 MONO_ADD_INS (cfg->cbb, load);
2305                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2306
2307                 if (ainfo->pair_storage [0] == ArgInIReg) {
2308                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2309                         arg->dreg = mono_alloc_ireg (cfg);
2310                         arg->sreg1 = load->dreg;
2311                         arg->inst_imm = 0;
2312                         MONO_ADD_INS (cfg->cbb, arg);
2313                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2314                 } else {
2315                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2316                 }
2317                 break;
2318         }
2319         case ArgGSharedVtInReg:
2320                 /* Pass by addr */
2321                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2322                 break;
2323         case ArgGSharedVtOnStack:
2324                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2325                 break;
2326         default:
2327                 if (size == 8) {
2328                         int dreg = mono_alloc_ireg (cfg);
2329
2330                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2331                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2332                 } else if (size <= 40) {
2333                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2334                 } else {
2335                         // FIXME: Code growth
2336                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2337                 }
2338
2339                 if (cfg->compute_gc_maps) {
2340                         MonoInst *def;
2341                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2342                 }
2343         }
2344 }
2345
2346 void
2347 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2348 {
2349         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2350
2351         if (ret->type == MONO_TYPE_R4) {
2352                 if (COMPILE_LLVM (cfg))
2353                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2354                 else
2355                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2356                 return;
2357         } else if (ret->type == MONO_TYPE_R8) {
2358                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2359                 return;
2360         }
2361
2362         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2363 }
2364
2365 #endif /* DISABLE_JIT */
2366
2367 #define EMIT_COND_BRANCH(ins,cond,sign) \
2368         if (ins->inst_true_bb->native_offset) { \
2369                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2370         } else { \
2371                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2372                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2373             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2374                         x86_branch8 (code, cond, 0, sign); \
2375                 else \
2376                         x86_branch32 (code, cond, 0, sign); \
2377 }
2378
2379 typedef struct {
2380         MonoMethodSignature *sig;
2381         CallInfo *cinfo;
2382 } ArchDynCallInfo;
2383
2384 static gboolean
2385 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2386 {
2387         int i;
2388
2389         switch (cinfo->ret.storage) {
2390         case ArgNone:
2391         case ArgInIReg:
2392         case ArgInFloatSSEReg:
2393         case ArgInDoubleSSEReg:
2394         case ArgValuetypeAddrInIReg:
2395         case ArgValuetypeInReg:
2396                 break;
2397         default:
2398                 return FALSE;
2399         }
2400
2401         for (i = 0; i < cinfo->nargs; ++i) {
2402                 ArgInfo *ainfo = &cinfo->args [i];
2403                 switch (ainfo->storage) {
2404                 case ArgInIReg:
2405                 case ArgInFloatSSEReg:
2406                 case ArgInDoubleSSEReg:
2407                 case ArgValuetypeInReg:
2408                         break;
2409                 case ArgOnStack:
2410                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2411                                 return FALSE;
2412                         break;
2413                 default:
2414                         return FALSE;
2415                 }
2416         }
2417
2418         return TRUE;
2419 }
2420
2421 /*
2422  * mono_arch_dyn_call_prepare:
2423  *
2424  *   Return a pointer to an arch-specific structure which contains information
2425  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2426  * supported for SIG.
2427  * This function is equivalent to ffi_prep_cif in libffi.
2428  */
2429 MonoDynCallInfo*
2430 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2431 {
2432         ArchDynCallInfo *info;
2433         CallInfo *cinfo;
2434
2435         cinfo = get_call_info (NULL, sig);
2436
2437         if (!dyn_call_supported (sig, cinfo)) {
2438                 g_free (cinfo);
2439                 return NULL;
2440         }
2441
2442         info = g_new0 (ArchDynCallInfo, 1);
2443         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2444         info->sig = sig;
2445         info->cinfo = cinfo;
2446
2447         return (MonoDynCallInfo*)info;
2448 }
2449
2450 /*
2451  * mono_arch_dyn_call_free:
2452  *
2453  *   Free a MonoDynCallInfo structure.
2454  */
2455 void
2456 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2457 {
2458         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2459
2460         g_free (ainfo->cinfo);
2461         g_free (ainfo);
2462 }
2463
2464 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2465 #define GREG_TO_PTR(greg) (gpointer)(greg)
2466
2467 /*
2468  * mono_arch_get_start_dyn_call:
2469  *
2470  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2471  * store the result into BUF.
2472  * ARGS should be an array of pointers pointing to the arguments.
2473  * RET should point to a memory buffer large enought to hold the result of the
2474  * call.
2475  * This function should be as fast as possible, any work which does not depend
2476  * on the actual values of the arguments should be done in
2477  * mono_arch_dyn_call_prepare ().
2478  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2479  * libffi.
2480  */
2481 void
2482 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2483 {
2484         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2485         DynCallArgs *p = (DynCallArgs*)buf;
2486         int arg_index, greg, freg, i, pindex;
2487         MonoMethodSignature *sig = dinfo->sig;
2488         int buffer_offset = 0;
2489         static int param_reg_to_index [16];
2490         static gboolean param_reg_to_index_inited;
2491
2492         if (!param_reg_to_index_inited) {
2493                 for (i = 0; i < PARAM_REGS; ++i)
2494                         param_reg_to_index [param_regs [i]] = i;
2495                 mono_memory_barrier ();
2496                 param_reg_to_index_inited = 1;
2497         }
2498
2499         g_assert (buf_len >= sizeof (DynCallArgs));
2500
2501         p->res = 0;
2502         p->ret = ret;
2503
2504         arg_index = 0;
2505         greg = 0;
2506         freg = 0;
2507         pindex = 0;
2508
2509         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2510                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2511                 if (!sig->hasthis)
2512                         pindex = 1;
2513         }
2514
2515         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2516                 p->regs [greg ++] = PTR_TO_GREG(ret);
2517
2518         for (; pindex < sig->param_count; pindex++) {
2519                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2520                 gpointer *arg = args [arg_index ++];
2521                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2522                 int slot;
2523
2524                 if (ainfo->storage == ArgOnStack) {
2525                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2526                 } else {
2527                         slot = param_reg_to_index [ainfo->reg];
2528                 }
2529
2530                 if (t->byref) {
2531                         p->regs [slot] = PTR_TO_GREG(*(arg));
2532                         greg ++;
2533                         continue;
2534                 }
2535
2536                 switch (t->type) {
2537                 case MONO_TYPE_OBJECT:
2538                 case MONO_TYPE_PTR:
2539                 case MONO_TYPE_I:
2540                 case MONO_TYPE_U:
2541 #if !defined(__mono_ilp32__)
2542                 case MONO_TYPE_I8:
2543                 case MONO_TYPE_U8:
2544 #endif
2545                         p->regs [slot] = PTR_TO_GREG(*(arg));
2546                         break;
2547 #if defined(__mono_ilp32__)
2548                 case MONO_TYPE_I8:
2549                 case MONO_TYPE_U8:
2550                         p->regs [slot] = *(guint64*)(arg);
2551                         break;
2552 #endif
2553                 case MONO_TYPE_U1:
2554                         p->regs [slot] = *(guint8*)(arg);
2555                         break;
2556                 case MONO_TYPE_I1:
2557                         p->regs [slot] = *(gint8*)(arg);
2558                         break;
2559                 case MONO_TYPE_I2:
2560                         p->regs [slot] = *(gint16*)(arg);
2561                         break;
2562                 case MONO_TYPE_U2:
2563                         p->regs [slot] = *(guint16*)(arg);
2564                         break;
2565                 case MONO_TYPE_I4:
2566                         p->regs [slot] = *(gint32*)(arg);
2567                         break;
2568                 case MONO_TYPE_U4:
2569                         p->regs [slot] = *(guint32*)(arg);
2570                         break;
2571                 case MONO_TYPE_R4: {
2572                         double d;
2573
2574                         *(float*)&d = *(float*)(arg);
2575                         p->has_fp = 1;
2576                         p->fregs [freg ++] = d;
2577                         break;
2578                 }
2579                 case MONO_TYPE_R8:
2580                         p->has_fp = 1;
2581                         p->fregs [freg ++] = *(double*)(arg);
2582                         break;
2583                 case MONO_TYPE_GENERICINST:
2584                     if (MONO_TYPE_IS_REFERENCE (t)) {
2585                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2586                                 break;
2587                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2588                                         MonoClass *klass = mono_class_from_mono_type (t);
2589                                         guint8 *nullable_buf;
2590                                         int size;
2591
2592                                         size = mono_class_value_size (klass, NULL);
2593                                         nullable_buf = p->buffer + buffer_offset;
2594                                         buffer_offset += size;
2595                                         g_assert (buffer_offset <= 256);
2596
2597                                         /* The argument pointed to by arg is either a boxed vtype or null */
2598                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2599
2600                                         arg = (gpointer*)nullable_buf;
2601                                         /* Fall though */
2602
2603                         } else {
2604                                 /* Fall through */
2605                         }
2606                 case MONO_TYPE_VALUETYPE: {
2607                         switch (ainfo->storage) {
2608                         case ArgValuetypeInReg:
2609                                 for (i = 0; i < 2; ++i) {
2610                                         switch (ainfo->pair_storage [i]) {
2611                                         case ArgNone:
2612                                                 break;
2613                                         case ArgInIReg:
2614                                                 slot = param_reg_to_index [ainfo->pair_regs [i]];
2615                                                 p->regs [slot] = ((mgreg_t*)(arg))[i];
2616                                                 break;
2617                                         case ArgInDoubleSSEReg:
2618                                                 p->has_fp = 1;
2619                                                 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2620                                                 break;
2621                                         default:
2622                                                 g_assert_not_reached ();
2623                                                 break;
2624                                         }
2625                                 }
2626                                 break;
2627                         case ArgOnStack:
2628                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2629                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2630                                 break;
2631                         default:
2632                                 g_assert_not_reached ();
2633                                 break;
2634                         }
2635                         break;
2636                 }
2637                 default:
2638                         g_assert_not_reached ();
2639                 }
2640         }
2641 }
2642
2643 /*
2644  * mono_arch_finish_dyn_call:
2645  *
2646  *   Store the result of a dyn call into the return value buffer passed to
2647  * start_dyn_call ().
2648  * This function should be as fast as possible, any work which does not depend
2649  * on the actual values of the arguments should be done in
2650  * mono_arch_dyn_call_prepare ().
2651  */
2652 void
2653 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2654 {
2655         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2656         MonoMethodSignature *sig = dinfo->sig;
2657         DynCallArgs *dargs = (DynCallArgs*)buf;
2658         guint8 *ret = dargs->ret;
2659         mgreg_t res = dargs->res;
2660         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2661         int i;
2662
2663         switch (sig_ret->type) {
2664         case MONO_TYPE_VOID:
2665                 *(gpointer*)ret = NULL;
2666                 break;
2667         case MONO_TYPE_OBJECT:
2668         case MONO_TYPE_I:
2669         case MONO_TYPE_U:
2670         case MONO_TYPE_PTR:
2671                 *(gpointer*)ret = GREG_TO_PTR(res);
2672                 break;
2673         case MONO_TYPE_I1:
2674                 *(gint8*)ret = res;
2675                 break;
2676         case MONO_TYPE_U1:
2677                 *(guint8*)ret = res;
2678                 break;
2679         case MONO_TYPE_I2:
2680                 *(gint16*)ret = res;
2681                 break;
2682         case MONO_TYPE_U2:
2683                 *(guint16*)ret = res;
2684                 break;
2685         case MONO_TYPE_I4:
2686                 *(gint32*)ret = res;
2687                 break;
2688         case MONO_TYPE_U4:
2689                 *(guint32*)ret = res;
2690                 break;
2691         case MONO_TYPE_I8:
2692                 *(gint64*)ret = res;
2693                 break;
2694         case MONO_TYPE_U8:
2695                 *(guint64*)ret = res;
2696                 break;
2697         case MONO_TYPE_R4:
2698                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2699                 break;
2700         case MONO_TYPE_R8:
2701                 *(double*)ret = dargs->fregs [0];
2702                 break;
2703         case MONO_TYPE_GENERICINST:
2704                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2705                         *(gpointer*)ret = GREG_TO_PTR(res);
2706                         break;
2707                 } else {
2708                         /* Fall through */
2709                 }
2710         case MONO_TYPE_VALUETYPE:
2711                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2712                         /* Nothing to do */
2713                 } else {
2714                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2715
2716                         g_assert (ainfo->storage == ArgValuetypeInReg);
2717
2718                         for (i = 0; i < 2; ++i) {
2719                                 switch (ainfo->pair_storage [0]) {
2720                                 case ArgInIReg:
2721                                         ((mgreg_t*)ret)[i] = res;
2722                                         break;
2723                                 case ArgInDoubleSSEReg:
2724                                         ((double*)ret)[i] = dargs->fregs [i];
2725                                         break;
2726                                 case ArgNone:
2727                                         break;
2728                                 default:
2729                                         g_assert_not_reached ();
2730                                         break;
2731                                 }
2732                         }
2733                 }
2734                 break;
2735         default:
2736                 g_assert_not_reached ();
2737         }
2738 }
2739
2740 /* emit an exception if condition is fail */
2741 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2742         do {                                                        \
2743                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2744                 if (tins == NULL) {                                                                             \
2745                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2746                                         MONO_PATCH_INFO_EXC, exc_name);  \
2747                         x86_branch32 (code, cond, 0, signed);               \
2748                 } else {        \
2749                         EMIT_COND_BRANCH (tins, cond, signed);  \
2750                 }                       \
2751         } while (0);
2752
2753 #define EMIT_FPCOMPARE(code) do { \
2754         amd64_fcompp (code); \
2755         amd64_fnstsw (code); \
2756 } while (0);
2757
2758 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2759     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2760         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2761         amd64_ ##op (code); \
2762         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2763         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2764 } while (0);
2765
2766 static guint8*
2767 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2768 {
2769         gboolean no_patch = FALSE;
2770
2771         /*
2772          * FIXME: Add support for thunks
2773          */
2774         {
2775                 gboolean near_call = FALSE;
2776
2777                 /*
2778                  * Indirect calls are expensive so try to make a near call if possible.
2779                  * The caller memory is allocated by the code manager so it is
2780                  * guaranteed to be at a 32 bit offset.
2781                  */
2782
2783                 if (patch_type != MONO_PATCH_INFO_ABS) {
2784                         /* The target is in memory allocated using the code manager */
2785                         near_call = TRUE;
2786
2787                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2788                                 if (((MonoMethod*)data)->klass->image->aot_module)
2789                                         /* The callee might be an AOT method */
2790                                         near_call = FALSE;
2791                                 if (((MonoMethod*)data)->dynamic)
2792                                         /* The target is in malloc-ed memory */
2793                                         near_call = FALSE;
2794                         }
2795
2796                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2797                                 /*
2798                                  * The call might go directly to a native function without
2799                                  * the wrapper.
2800                                  */
2801                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2802                                 if (mi) {
2803                                         gconstpointer target = mono_icall_get_wrapper (mi);
2804                                         if ((((guint64)target) >> 32) != 0)
2805                                                 near_call = FALSE;
2806                                 }
2807                         }
2808                 }
2809                 else {
2810                         MonoJumpInfo *jinfo = NULL;
2811
2812                         if (cfg->abs_patches)
2813                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2814                         if (jinfo) {
2815                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2816                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2817                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2818                                                 near_call = TRUE;
2819                                         no_patch = TRUE;
2820                                 } else {
2821                                         /*
2822                                          * This is not really an optimization, but required because the
2823                                          * generic class init trampolines use R11 to pass the vtable.
2824                                          */
2825                                         near_call = TRUE;
2826                                 }
2827                         } else {
2828                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2829                                 if (info) {
2830                                         if (info->func == info->wrapper) {
2831                                                 /* No wrapper */
2832                                                 if ((((guint64)info->func) >> 32) == 0)
2833                                                         near_call = TRUE;
2834                                         }
2835                                         else {
2836                                                 /* See the comment in mono_codegen () */
2837                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2838                                                         near_call = TRUE;
2839                                         }
2840                                 }
2841                                 else if ((((guint64)data) >> 32) == 0) {
2842                                         near_call = TRUE;
2843                                         no_patch = TRUE;
2844                                 }
2845                         }
2846                 }
2847
2848                 if (cfg->method->dynamic)
2849                         /* These methods are allocated using malloc */
2850                         near_call = FALSE;
2851
2852 #ifdef MONO_ARCH_NOMAP32BIT
2853                 near_call = FALSE;
2854 #endif
2855                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2856                 if (optimize_for_xen)
2857                         near_call = FALSE;
2858
2859                 if (cfg->compile_aot) {
2860                         near_call = TRUE;
2861                         no_patch = TRUE;
2862                 }
2863
2864                 if (near_call) {
2865                         /*
2866                          * Align the call displacement to an address divisible by 4 so it does
2867                          * not span cache lines. This is required for code patching to work on SMP
2868                          * systems.
2869                          */
2870                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2871                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2872                                 amd64_padding (code, pad_size);
2873                         }
2874                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2875                         amd64_call_code (code, 0);
2876                 }
2877                 else {
2878                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2879                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2880                         amd64_call_reg (code, GP_SCRATCH_REG);
2881                 }
2882         }
2883
2884         return code;
2885 }
2886
2887 static inline guint8*
2888 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2889 {
2890 #ifdef TARGET_WIN32
2891         if (win64_adjust_stack)
2892                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2893 #endif
2894         code = emit_call_body (cfg, code, patch_type, data);
2895 #ifdef TARGET_WIN32
2896         if (win64_adjust_stack)
2897                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2898 #endif
2899
2900         return code;
2901 }
2902
2903 static inline int
2904 store_membase_imm_to_store_membase_reg (int opcode)
2905 {
2906         switch (opcode) {
2907         case OP_STORE_MEMBASE_IMM:
2908                 return OP_STORE_MEMBASE_REG;
2909         case OP_STOREI4_MEMBASE_IMM:
2910                 return OP_STOREI4_MEMBASE_REG;
2911         case OP_STOREI8_MEMBASE_IMM:
2912                 return OP_STOREI8_MEMBASE_REG;
2913         }
2914
2915         return -1;
2916 }
2917
2918 #ifndef DISABLE_JIT
2919
2920 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2921
2922 /*
2923  * mono_arch_peephole_pass_1:
2924  *
2925  *   Perform peephole opts which should/can be performed before local regalloc
2926  */
2927 void
2928 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2929 {
2930         MonoInst *ins, *n;
2931
2932         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2933                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2934
2935                 switch (ins->opcode) {
2936                 case OP_ADD_IMM:
2937                 case OP_IADD_IMM:
2938                 case OP_LADD_IMM:
2939                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2940                                 /*
2941                                  * X86_LEA is like ADD, but doesn't have the
2942                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2943                                  * its operand to 64 bit.
2944                                  */
2945                                 ins->opcode = OP_X86_LEA_MEMBASE;
2946                                 ins->inst_basereg = ins->sreg1;
2947                         }
2948                         break;
2949                 case OP_LXOR:
2950                 case OP_IXOR:
2951                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2952                                 MonoInst *ins2;
2953
2954                                 /*
2955                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2956                                  * the latter has length 2-3 instead of 6 (reverse constant
2957                                  * propagation). These instruction sequences are very common
2958                                  * in the initlocals bblock.
2959                                  */
2960                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2961                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2962                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2963                                                 ins2->sreg1 = ins->dreg;
2964                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2965                                                 /* Continue */
2966                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2967                                                 NULLIFY_INS (ins2);
2968                                                 /* Continue */
2969                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2970                                                 /* Continue */
2971                                         } else {
2972                                                 break;
2973                                         }
2974                                 }
2975                         }
2976                         break;
2977                 case OP_COMPARE_IMM:
2978                 case OP_LCOMPARE_IMM:
2979                         /* OP_COMPARE_IMM (reg, 0)
2980                          * -->
2981                          * OP_AMD64_TEST_NULL (reg)
2982                          */
2983                         if (!ins->inst_imm)
2984                                 ins->opcode = OP_AMD64_TEST_NULL;
2985                         break;
2986                 case OP_ICOMPARE_IMM:
2987                         if (!ins->inst_imm)
2988                                 ins->opcode = OP_X86_TEST_NULL;
2989                         break;
2990                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2991                         /*
2992                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2993                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2994                          * -->
2995                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2996                          * OP_COMPARE_IMM reg, imm
2997                          *
2998                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2999                          */
3000                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3001                             ins->inst_basereg == last_ins->inst_destbasereg &&
3002                             ins->inst_offset == last_ins->inst_offset) {
3003                                         ins->opcode = OP_ICOMPARE_IMM;
3004                                         ins->sreg1 = last_ins->sreg1;
3005
3006                                         /* check if we can remove cmp reg,0 with test null */
3007                                         if (!ins->inst_imm)
3008                                                 ins->opcode = OP_X86_TEST_NULL;
3009                                 }
3010
3011                         break;
3012                 }
3013
3014                 mono_peephole_ins (bb, ins);
3015         }
3016 }
3017
3018 void
3019 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3020 {
3021         MonoInst *ins, *n;
3022
3023         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3024                 switch (ins->opcode) {
3025                 case OP_ICONST:
3026                 case OP_I8CONST: {
3027                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3028                         /* reg = 0 -> XOR (reg, reg) */
3029                         /* XOR sets cflags on x86, so we cant do it always */
3030                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3031                                 ins->opcode = OP_LXOR;
3032                                 ins->sreg1 = ins->dreg;
3033                                 ins->sreg2 = ins->dreg;
3034                                 /* Fall through */
3035                         } else {
3036                                 break;
3037                         }
3038                 }
3039                 case OP_LXOR:
3040                         /*
3041                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3042                          * 0 result into 64 bits.
3043                          */
3044                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3045                                 ins->opcode = OP_IXOR;
3046                         }
3047                         /* Fall through */
3048                 case OP_IXOR:
3049                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3050                                 MonoInst *ins2;
3051
3052                                 /*
3053                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3054                                  * the latter has length 2-3 instead of 6 (reverse constant
3055                                  * propagation). These instruction sequences are very common
3056                                  * in the initlocals bblock.
3057                                  */
3058                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3059                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3060                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3061                                                 ins2->sreg1 = ins->dreg;
3062                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3063                                                 /* Continue */
3064                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3065                                                 NULLIFY_INS (ins2);
3066                                                 /* Continue */
3067                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3068                                                 /* Continue */
3069                                         } else {
3070                                                 break;
3071                                         }
3072                                 }
3073                         }
3074                         break;
3075                 case OP_IADD_IMM:
3076                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3077                                 ins->opcode = OP_X86_INC_REG;
3078                         break;
3079                 case OP_ISUB_IMM:
3080                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3081                                 ins->opcode = OP_X86_DEC_REG;
3082                         break;
3083                 }
3084
3085                 mono_peephole_ins (bb, ins);
3086         }
3087 }
3088
3089 #define NEW_INS(cfg,ins,dest,op) do {   \
3090                 MONO_INST_NEW ((cfg), (dest), (op)); \
3091         (dest)->cil_code = (ins)->cil_code; \
3092         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3093         } while (0)
3094
3095 /*
3096  * mono_arch_lowering_pass:
3097  *
3098  *  Converts complex opcodes into simpler ones so that each IR instruction
3099  * corresponds to one machine instruction.
3100  */
3101 void
3102 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3103 {
3104         MonoInst *ins, *n, *temp;
3105
3106         /*
3107          * FIXME: Need to add more instructions, but the current machine
3108          * description can't model some parts of the composite instructions like
3109          * cdq.
3110          */
3111         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3112                 switch (ins->opcode) {
3113                 case OP_DIV_IMM:
3114                 case OP_REM_IMM:
3115                 case OP_IDIV_IMM:
3116                 case OP_IDIV_UN_IMM:
3117                 case OP_IREM_UN_IMM:
3118                 case OP_LREM_IMM:
3119                 case OP_IREM_IMM:
3120                         mono_decompose_op_imm (cfg, bb, ins);
3121                         break;
3122                 case OP_COMPARE_IMM:
3123                 case OP_LCOMPARE_IMM:
3124                         if (!amd64_use_imm32 (ins->inst_imm)) {
3125                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3126                                 temp->inst_c0 = ins->inst_imm;
3127                                 temp->dreg = mono_alloc_ireg (cfg);
3128                                 ins->opcode = OP_COMPARE;
3129                                 ins->sreg2 = temp->dreg;
3130                         }
3131                         break;
3132 #ifndef __mono_ilp32__
3133                 case OP_LOAD_MEMBASE:
3134 #endif
3135                 case OP_LOADI8_MEMBASE:
3136                 /*  Don't generate memindex opcodes (to simplify */
3137                 /*  read sandboxing) */
3138                         if (!amd64_use_imm32 (ins->inst_offset)) {
3139                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3140                                 temp->inst_c0 = ins->inst_offset;
3141                                 temp->dreg = mono_alloc_ireg (cfg);
3142                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3143                                 ins->inst_indexreg = temp->dreg;
3144                         }
3145                         break;
3146 #ifndef __mono_ilp32__
3147                 case OP_STORE_MEMBASE_IMM:
3148 #endif
3149                 case OP_STOREI8_MEMBASE_IMM:
3150                         if (!amd64_use_imm32 (ins->inst_imm)) {
3151                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3152                                 temp->inst_c0 = ins->inst_imm;
3153                                 temp->dreg = mono_alloc_ireg (cfg);
3154                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3155                                 ins->sreg1 = temp->dreg;
3156                         }
3157                         break;
3158 #ifdef MONO_ARCH_SIMD_INTRINSICS
3159                 case OP_EXPAND_I1: {
3160                                 int temp_reg1 = mono_alloc_ireg (cfg);
3161                                 int temp_reg2 = mono_alloc_ireg (cfg);
3162                                 int original_reg = ins->sreg1;
3163
3164                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3165                                 temp->sreg1 = original_reg;
3166                                 temp->dreg = temp_reg1;
3167
3168                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3169                                 temp->sreg1 = temp_reg1;
3170                                 temp->dreg = temp_reg2;
3171                                 temp->inst_imm = 8;
3172
3173                                 NEW_INS (cfg, ins, temp, OP_LOR);
3174                                 temp->sreg1 = temp->dreg = temp_reg2;
3175                                 temp->sreg2 = temp_reg1;
3176
3177                                 ins->opcode = OP_EXPAND_I2;
3178                                 ins->sreg1 = temp_reg2;
3179                         }
3180                         break;
3181 #endif
3182                 default:
3183                         break;
3184                 }
3185         }
3186
3187         bb->max_vreg = cfg->next_vreg;
3188 }
3189
3190 static const int
3191 branch_cc_table [] = {
3192         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3193         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3194         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3195 };
3196
3197 /* Maps CMP_... constants to X86_CC_... constants */
3198 static const int
3199 cc_table [] = {
3200         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3201         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3202 };
3203
3204 static const int
3205 cc_signed_table [] = {
3206         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3207         FALSE, FALSE, FALSE, FALSE
3208 };
3209
3210 /*#include "cprop.c"*/
3211
3212 static unsigned char*
3213 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3214 {
3215         if (size == 8)
3216                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3217         else
3218                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3219
3220         if (size == 1)
3221                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3222         else if (size == 2)
3223                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3224         return code;
3225 }
3226
3227 static unsigned char*
3228 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3229 {
3230         int sreg = tree->sreg1;
3231         int need_touch = FALSE;
3232
3233 #if defined(TARGET_WIN32)
3234         need_touch = TRUE;
3235 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3236         if (!tree->flags & MONO_INST_INIT)
3237                 need_touch = TRUE;
3238 #endif
3239
3240         if (need_touch) {
3241                 guint8* br[5];
3242
3243                 /*
3244                  * Under Windows:
3245                  * If requested stack size is larger than one page,
3246                  * perform stack-touch operation
3247                  */
3248                 /*
3249                  * Generate stack probe code.
3250                  * Under Windows, it is necessary to allocate one page at a time,
3251                  * "touching" stack after each successful sub-allocation. This is
3252                  * because of the way stack growth is implemented - there is a
3253                  * guard page before the lowest stack page that is currently commited.
3254                  * Stack normally grows sequentially so OS traps access to the
3255                  * guard page and commits more pages when needed.
3256                  */
3257                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3258                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3259
3260                 br[2] = code; /* loop */
3261                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3262                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3263                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3264                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3265                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3266                 amd64_patch (br[3], br[2]);
3267                 amd64_test_reg_reg (code, sreg, sreg);
3268                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3269                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3270
3271                 br[1] = code; x86_jump8 (code, 0);
3272
3273                 amd64_patch (br[0], code);
3274                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3275                 amd64_patch (br[1], code);
3276                 amd64_patch (br[4], code);
3277         }
3278         else
3279                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3280
3281         if (tree->flags & MONO_INST_INIT) {
3282                 int offset = 0;
3283                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3284                         amd64_push_reg (code, AMD64_RAX);
3285                         offset += 8;
3286                 }
3287                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3288                         amd64_push_reg (code, AMD64_RCX);
3289                         offset += 8;
3290                 }
3291                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3292                         amd64_push_reg (code, AMD64_RDI);
3293                         offset += 8;
3294                 }
3295
3296                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3297                 if (sreg != AMD64_RCX)
3298                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3299                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3300
3301                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3302                 if (cfg->param_area)
3303                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3304                 amd64_cld (code);
3305                 amd64_prefix (code, X86_REP_PREFIX);
3306                 amd64_stosl (code);
3307
3308                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3309                         amd64_pop_reg (code, AMD64_RDI);
3310                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3311                         amd64_pop_reg (code, AMD64_RCX);
3312                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3313                         amd64_pop_reg (code, AMD64_RAX);
3314         }
3315         return code;
3316 }
3317
3318 static guint8*
3319 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3320 {
3321         CallInfo *cinfo;
3322         guint32 quad;
3323
3324         /* Move return value to the target register */
3325         /* FIXME: do this in the local reg allocator */
3326         switch (ins->opcode) {
3327         case OP_CALL:
3328         case OP_CALL_REG:
3329         case OP_CALL_MEMBASE:
3330         case OP_LCALL:
3331         case OP_LCALL_REG:
3332         case OP_LCALL_MEMBASE:
3333                 g_assert (ins->dreg == AMD64_RAX);
3334                 break;
3335         case OP_FCALL:
3336         case OP_FCALL_REG:
3337         case OP_FCALL_MEMBASE: {
3338                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3339                 if (rtype->type == MONO_TYPE_R4) {
3340                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3341                 }
3342                 else {
3343                         if (ins->dreg != AMD64_XMM0)
3344                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3345                 }
3346                 break;
3347         }
3348         case OP_RCALL:
3349         case OP_RCALL_REG:
3350         case OP_RCALL_MEMBASE:
3351                 if (ins->dreg != AMD64_XMM0)
3352                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3353                 break;
3354         case OP_VCALL:
3355         case OP_VCALL_REG:
3356         case OP_VCALL_MEMBASE:
3357         case OP_VCALL2:
3358         case OP_VCALL2_REG:
3359         case OP_VCALL2_MEMBASE:
3360                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3361                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3362                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3363
3364                         /* Load the destination address */
3365                         g_assert (loc->opcode == OP_REGOFFSET);
3366                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3367
3368                         for (quad = 0; quad < 2; quad ++) {
3369                                 switch (cinfo->ret.pair_storage [quad]) {
3370                                 case ArgInIReg:
3371                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3372                                         break;
3373                                 case ArgInFloatSSEReg:
3374                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3375                                         break;
3376                                 case ArgInDoubleSSEReg:
3377                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3378                                         break;
3379                                 case ArgNone:
3380                                         break;
3381                                 default:
3382                                         NOT_IMPLEMENTED;
3383                                 }
3384                         }
3385                 }
3386                 break;
3387         }
3388
3389         return code;
3390 }
3391
3392 #endif /* DISABLE_JIT */
3393
3394 #ifdef TARGET_MACH
3395 static int tls_gs_offset;
3396 #endif
3397
3398 gboolean
3399 mono_arch_have_fast_tls (void)
3400 {
3401 #ifdef TARGET_MACH
3402         static gboolean have_fast_tls = FALSE;
3403         static gboolean inited = FALSE;
3404         guint8 *ins;
3405
3406         if (mini_get_debug_options ()->use_fallback_tls)
3407                 return FALSE;
3408
3409         if (inited)
3410                 return have_fast_tls;
3411
3412         ins = (guint8*)pthread_getspecific;
3413
3414         /*
3415          * We're looking for these two instructions:
3416          *
3417          * mov    %gs:[offset](,%rdi,8),%rax
3418          * retq
3419          */
3420         have_fast_tls = ins [0] == 0x65 &&
3421                        ins [1] == 0x48 &&
3422                        ins [2] == 0x8b &&
3423                        ins [3] == 0x04 &&
3424                        ins [4] == 0xfd &&
3425                        ins [6] == 0x00 &&
3426                        ins [7] == 0x00 &&
3427                        ins [8] == 0x00 &&
3428                        ins [9] == 0xc3;
3429
3430         tls_gs_offset = ins[5];
3431
3432         /*
3433          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3434          * For that version we're looking for these instructions:
3435          *
3436          * pushq  %rbp
3437          * movq   %rsp, %rbp
3438          * mov    %gs:[offset](,%rdi,8),%rax
3439          * popq   %rbp
3440          * retq
3441          */
3442         if (!have_fast_tls) {
3443                 have_fast_tls = ins [0] == 0x55 &&
3444                                ins [1] == 0x48 &&
3445                                ins [2] == 0x89 &&
3446                                ins [3] == 0xe5 &&
3447                                ins [4] == 0x65 &&
3448                                ins [5] == 0x48 &&
3449                                ins [6] == 0x8b &&
3450                                ins [7] == 0x04 &&
3451                                ins [8] == 0xfd &&
3452                                ins [10] == 0x00 &&
3453                                ins [11] == 0x00 &&
3454                                ins [12] == 0x00 &&
3455                                ins [13] == 0x5d &&
3456                                ins [14] == 0xc3;
3457
3458                 tls_gs_offset = ins[9];
3459         }
3460         inited = TRUE;
3461
3462         return have_fast_tls;
3463 #elif defined(TARGET_ANDROID)
3464         return FALSE;
3465 #else
3466         if (mini_get_debug_options ()->use_fallback_tls)
3467                 return FALSE;
3468         return TRUE;
3469 #endif
3470 }
3471
3472 int
3473 mono_amd64_get_tls_gs_offset (void)
3474 {
3475 #ifdef TARGET_OSX
3476         return tls_gs_offset;
3477 #else
3478         g_assert_not_reached ();
3479         return -1;
3480 #endif
3481 }
3482
3483 /*
3484  * \param code buffer to store code to
3485  * \param dreg hard register where to place the result
3486  * \param tls_offset offset info
3487  * \return a pointer to the end of the stored code
3488  *
3489  * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3490  * the dreg register the item in the thread local storage identified
3491  * by tls_offset.
3492  */
3493 static guint8*
3494 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3495 {
3496 #ifdef TARGET_WIN32
3497         if (tls_offset < 64) {
3498                 x86_prefix (code, X86_GS_PREFIX);
3499                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3500         } else {
3501                 guint8 *buf [16];
3502
3503                 g_assert (tls_offset < 0x440);
3504                 /* Load TEB->TlsExpansionSlots */
3505                 x86_prefix (code, X86_GS_PREFIX);
3506                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3507                 amd64_test_reg_reg (code, dreg, dreg);
3508                 buf [0] = code;
3509                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3510                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3511                 amd64_patch (buf [0], code);
3512         }
3513 #elif defined(TARGET_MACH)
3514         x86_prefix (code, X86_GS_PREFIX);
3515         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3516 #else
3517         if (optimize_for_xen) {
3518                 x86_prefix (code, X86_FS_PREFIX);
3519                 amd64_mov_reg_mem (code, dreg, 0, 8);
3520                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3521         } else {
3522                 x86_prefix (code, X86_FS_PREFIX);
3523                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3524         }
3525 #endif
3526         return code;
3527 }
3528
3529 static guint8*
3530 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3531 {
3532 #ifdef TARGET_WIN32
3533         g_assert_not_reached ();
3534 #elif defined(TARGET_MACH)
3535         x86_prefix (code, X86_GS_PREFIX);
3536         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3537 #else
3538         g_assert (!optimize_for_xen);
3539         x86_prefix (code, X86_FS_PREFIX);
3540         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3541 #endif
3542         return code;
3543 }
3544
3545 /*
3546  * emit_setup_lmf:
3547  *
3548  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3549  */
3550 static guint8*
3551 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3552 {
3553         /*
3554          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3555          */
3556         /*
3557          * sp is saved right before calls but we need to save it here too so
3558          * async stack walks would work.
3559          */
3560         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3561         /* Save rbp */
3562         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3563         if (cfg->arch.omit_fp && cfa_offset != -1)
3564                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3565
3566         /* These can't contain refs */
3567         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3568         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3569         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3570         /* These are handled automatically by the stack marking code */
3571         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3572
3573         return code;
3574 }
3575
3576 #ifdef TARGET_WIN32
3577
3578 #define TEB_LAST_ERROR_OFFSET 0x068
3579
3580 static guint8*
3581 emit_get_last_error (guint8* code, int dreg)
3582 {
3583         /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3584         x86_prefix (code, X86_GS_PREFIX);
3585         amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3586
3587         return code;
3588 }
3589
3590 #else
3591
3592 static guint8*
3593 emit_get_last_error (guint8* code, int dreg)
3594 {
3595         g_assert_not_reached ();
3596 }
3597
3598 #endif
3599
3600 /* benchmark and set based on cpu */
3601 #define LOOP_ALIGNMENT 8
3602 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3603
3604 #ifndef DISABLE_JIT
3605 void
3606 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3607 {
3608         MonoInst *ins;
3609         MonoCallInst *call;
3610         guint offset;
3611         guint8 *code = cfg->native_code + cfg->code_len;
3612         int max_len;
3613
3614         /* Fix max_offset estimate for each successor bb */
3615         if (cfg->opt & MONO_OPT_BRANCH) {
3616                 int current_offset = cfg->code_len;
3617                 MonoBasicBlock *current_bb;
3618                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3619                         current_bb->max_offset = current_offset;
3620                         current_offset += current_bb->max_length;
3621                 }
3622         }
3623
3624         if (cfg->opt & MONO_OPT_LOOP) {
3625                 int pad, align = LOOP_ALIGNMENT;
3626                 /* set alignment depending on cpu */
3627                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3628                         pad = align - pad;
3629                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3630                         amd64_padding (code, pad);
3631                         cfg->code_len += pad;
3632                         bb->native_offset = cfg->code_len;
3633                 }
3634         }
3635
3636         if (cfg->verbose_level > 2)
3637                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3638
3639         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3640                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3641                 g_assert (!cfg->compile_aot);
3642
3643                 cov->data [bb->dfn].cil_code = bb->cil_code;
3644                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3645                 /* this is not thread save, but good enough */
3646                 amd64_inc_membase (code, AMD64_R11, 0);
3647         }
3648
3649         offset = code - cfg->native_code;
3650
3651         mono_debug_open_block (cfg, bb, offset);
3652
3653     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3654                 x86_breakpoint (code);
3655
3656         MONO_BB_FOR_EACH_INS (bb, ins) {
3657                 offset = code - cfg->native_code;
3658
3659                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3660
3661 #define EXTRA_CODE_SPACE (16)
3662
3663                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3664                         cfg->code_size *= 2;
3665                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3666                         code = cfg->native_code + offset;
3667                         cfg->stat_code_reallocs++;
3668                 }
3669
3670                 if (cfg->debug_info)
3671                         mono_debug_record_line_number (cfg, ins, offset);
3672
3673                 switch (ins->opcode) {
3674                 case OP_BIGMUL:
3675                         amd64_mul_reg (code, ins->sreg2, TRUE);
3676                         break;
3677                 case OP_BIGMUL_UN:
3678                         amd64_mul_reg (code, ins->sreg2, FALSE);
3679                         break;
3680                 case OP_X86_SETEQ_MEMBASE:
3681                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3682                         break;
3683                 case OP_STOREI1_MEMBASE_IMM:
3684                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3685                         break;
3686                 case OP_STOREI2_MEMBASE_IMM:
3687                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3688                         break;
3689                 case OP_STOREI4_MEMBASE_IMM:
3690                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3691                         break;
3692                 case OP_STOREI1_MEMBASE_REG:
3693                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3694                         break;
3695                 case OP_STOREI2_MEMBASE_REG:
3696                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3697                         break;
3698                 /* In AMD64 NaCl, pointers are 4 bytes, */
3699                 /*  so STORE_* != STOREI8_*. Likewise below. */
3700                 case OP_STORE_MEMBASE_REG:
3701                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3702                         break;
3703                 case OP_STOREI8_MEMBASE_REG:
3704                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3705                         break;
3706                 case OP_STOREI4_MEMBASE_REG:
3707                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3708                         break;
3709                 case OP_STORE_MEMBASE_IMM:
3710                         /* In NaCl, this could be a PCONST type, which could */
3711                         /* mean a pointer type was copied directly into the  */
3712                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3713                         /* the value would be 0x00000000FFFFFFFF which is    */
3714                         /* not proper for an imm32 unless you cast it.       */
3715                         g_assert (amd64_is_imm32 (ins->inst_imm));
3716                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3717                         break;
3718                 case OP_STOREI8_MEMBASE_IMM:
3719                         g_assert (amd64_is_imm32 (ins->inst_imm));
3720                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3721                         break;
3722                 case OP_LOAD_MEM:
3723 #ifdef __mono_ilp32__
3724                         /* In ILP32, pointers are 4 bytes, so separate these */
3725                         /* cases, use literal 8 below where we really want 8 */
3726                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3727                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3728                         break;
3729 #endif
3730                 case OP_LOADI8_MEM:
3731                         // FIXME: Decompose this earlier
3732                         if (amd64_use_imm32 (ins->inst_imm))
3733                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3734                         else {
3735                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3736                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3737                         }
3738                         break;
3739                 case OP_LOADI4_MEM:
3740                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3741                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3742                         break;
3743                 case OP_LOADU4_MEM:
3744                         // FIXME: Decompose this earlier
3745                         if (amd64_use_imm32 (ins->inst_imm))
3746                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3747                         else {
3748                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3749                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3750                         }
3751                         break;
3752                 case OP_LOADU1_MEM:
3753                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3754                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3755                         break;
3756                 case OP_LOADU2_MEM:
3757                         /* For NaCl, pointers are 4 bytes, so separate these */
3758                         /* cases, use literal 8 below where we really want 8 */
3759                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3760                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3761                         break;
3762                 case OP_LOAD_MEMBASE:
3763                         g_assert (amd64_is_imm32 (ins->inst_offset));
3764                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3765                         break;
3766                 case OP_LOADI8_MEMBASE:
3767                         /* Use literal 8 instead of sizeof pointer or */
3768                         /* register, we really want 8 for this opcode */
3769                         g_assert (amd64_is_imm32 (ins->inst_offset));
3770                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3771                         break;
3772                 case OP_LOADI4_MEMBASE:
3773                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3774                         break;
3775                 case OP_LOADU4_MEMBASE:
3776                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3777                         break;
3778                 case OP_LOADU1_MEMBASE:
3779                         /* The cpu zero extends the result into 64 bits */
3780                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3781                         break;
3782                 case OP_LOADI1_MEMBASE:
3783                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3784                         break;
3785                 case OP_LOADU2_MEMBASE:
3786                         /* The cpu zero extends the result into 64 bits */
3787                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3788                         break;
3789                 case OP_LOADI2_MEMBASE:
3790                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3791                         break;
3792                 case OP_AMD64_LOADI8_MEMINDEX:
3793                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3794                         break;
3795                 case OP_LCONV_TO_I1:
3796                 case OP_ICONV_TO_I1:
3797                 case OP_SEXT_I1:
3798                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3799                         break;
3800                 case OP_LCONV_TO_I2:
3801                 case OP_ICONV_TO_I2:
3802                 case OP_SEXT_I2:
3803                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3804                         break;
3805                 case OP_LCONV_TO_U1:
3806                 case OP_ICONV_TO_U1:
3807                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3808                         break;
3809                 case OP_LCONV_TO_U2:
3810                 case OP_ICONV_TO_U2:
3811                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3812                         break;
3813                 case OP_ZEXT_I4:
3814                         /* Clean out the upper word */
3815                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3816                         break;
3817                 case OP_SEXT_I4:
3818                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3819                         break;
3820                 case OP_COMPARE:
3821                 case OP_LCOMPARE:
3822                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3823                         break;
3824                 case OP_COMPARE_IMM:
3825 #if defined(__mono_ilp32__)
3826                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3827                         g_assert (amd64_is_imm32 (ins->inst_imm));
3828                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3829                         break;
3830 #endif
3831                 case OP_LCOMPARE_IMM:
3832                         g_assert (amd64_is_imm32 (ins->inst_imm));
3833                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3834                         break;
3835                 case OP_X86_COMPARE_REG_MEMBASE:
3836                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3837                         break;
3838                 case OP_X86_TEST_NULL:
3839                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3840                         break;
3841                 case OP_AMD64_TEST_NULL:
3842                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3843                         break;
3844
3845                 case OP_X86_ADD_REG_MEMBASE:
3846                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3847                         break;
3848                 case OP_X86_SUB_REG_MEMBASE:
3849                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3850                         break;
3851                 case OP_X86_AND_REG_MEMBASE:
3852                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3853                         break;
3854                 case OP_X86_OR_REG_MEMBASE:
3855                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3856                         break;
3857                 case OP_X86_XOR_REG_MEMBASE:
3858                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3859                         break;
3860
3861                 case OP_X86_ADD_MEMBASE_IMM:
3862                         /* FIXME: Make a 64 version too */
3863                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3864                         break;
3865                 case OP_X86_SUB_MEMBASE_IMM:
3866                         g_assert (amd64_is_imm32 (ins->inst_imm));
3867                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3868                         break;
3869                 case OP_X86_AND_MEMBASE_IMM:
3870                         g_assert (amd64_is_imm32 (ins->inst_imm));
3871                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3872                         break;
3873                 case OP_X86_OR_MEMBASE_IMM:
3874                         g_assert (amd64_is_imm32 (ins->inst_imm));
3875                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3876                         break;
3877                 case OP_X86_XOR_MEMBASE_IMM:
3878                         g_assert (amd64_is_imm32 (ins->inst_imm));
3879                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3880                         break;
3881                 case OP_X86_ADD_MEMBASE_REG:
3882                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3883                         break;
3884                 case OP_X86_SUB_MEMBASE_REG:
3885                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3886                         break;
3887                 case OP_X86_AND_MEMBASE_REG:
3888                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3889                         break;
3890                 case OP_X86_OR_MEMBASE_REG:
3891                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3892                         break;
3893                 case OP_X86_XOR_MEMBASE_REG:
3894                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3895                         break;
3896                 case OP_X86_INC_MEMBASE:
3897                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3898                         break;
3899                 case OP_X86_INC_REG:
3900                         amd64_inc_reg_size (code, ins->dreg, 4);
3901                         break;
3902                 case OP_X86_DEC_MEMBASE:
3903                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3904                         break;
3905                 case OP_X86_DEC_REG:
3906                         amd64_dec_reg_size (code, ins->dreg, 4);
3907                         break;
3908                 case OP_X86_MUL_REG_MEMBASE:
3909                 case OP_X86_MUL_MEMBASE_REG:
3910                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3911                         break;
3912                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3913                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3914                         break;
3915                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3916                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3917                         break;
3918                 case OP_AMD64_COMPARE_MEMBASE_REG:
3919                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3920                         break;
3921                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3922                         g_assert (amd64_is_imm32 (ins->inst_imm));
3923                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3924                         break;
3925                 case OP_X86_COMPARE_MEMBASE8_IMM:
3926                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3927                         break;
3928                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3929                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3930                         break;
3931                 case OP_AMD64_COMPARE_REG_MEMBASE:
3932                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3933                         break;
3934
3935                 case OP_AMD64_ADD_REG_MEMBASE:
3936                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3937                         break;
3938                 case OP_AMD64_SUB_REG_MEMBASE:
3939                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3940                         break;
3941                 case OP_AMD64_AND_REG_MEMBASE:
3942                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3943                         break;
3944                 case OP_AMD64_OR_REG_MEMBASE:
3945                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3946                         break;
3947                 case OP_AMD64_XOR_REG_MEMBASE:
3948                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3949                         break;
3950
3951                 case OP_AMD64_ADD_MEMBASE_REG:
3952                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3953                         break;
3954                 case OP_AMD64_SUB_MEMBASE_REG:
3955                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3956                         break;
3957                 case OP_AMD64_AND_MEMBASE_REG:
3958                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3959                         break;
3960                 case OP_AMD64_OR_MEMBASE_REG:
3961                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3962                         break;
3963                 case OP_AMD64_XOR_MEMBASE_REG:
3964                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3965                         break;
3966
3967                 case OP_AMD64_ADD_MEMBASE_IMM:
3968                         g_assert (amd64_is_imm32 (ins->inst_imm));
3969                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3970                         break;
3971                 case OP_AMD64_SUB_MEMBASE_IMM:
3972                         g_assert (amd64_is_imm32 (ins->inst_imm));
3973                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3974                         break;
3975                 case OP_AMD64_AND_MEMBASE_IMM:
3976                         g_assert (amd64_is_imm32 (ins->inst_imm));
3977                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3978                         break;
3979                 case OP_AMD64_OR_MEMBASE_IMM:
3980                         g_assert (amd64_is_imm32 (ins->inst_imm));
3981                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3982                         break;
3983                 case OP_AMD64_XOR_MEMBASE_IMM:
3984                         g_assert (amd64_is_imm32 (ins->inst_imm));
3985                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3986                         break;
3987
3988                 case OP_BREAK:
3989                         amd64_breakpoint (code);
3990                         break;
3991                 case OP_RELAXED_NOP:
3992                         x86_prefix (code, X86_REP_PREFIX);
3993                         x86_nop (code);
3994                         break;
3995                 case OP_HARD_NOP:
3996                         x86_nop (code);
3997                         break;
3998                 case OP_NOP:
3999                 case OP_DUMMY_USE:
4000                 case OP_DUMMY_STORE:
4001                 case OP_DUMMY_ICONST:
4002                 case OP_DUMMY_R8CONST:
4003                 case OP_NOT_REACHED:
4004                 case OP_NOT_NULL:
4005                         break;
4006                 case OP_IL_SEQ_POINT:
4007                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4008                         break;
4009                 case OP_SEQ_POINT: {
4010                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4011                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4012                                 guint8 *label;
4013
4014                                 /* Load ss_tramp_var */
4015                                 /* This is equal to &ss_trampoline */
4016                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4017                                 /* Load the trampoline address */
4018                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4019                                 /* Call it if it is non-null */
4020                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4021                                 label = code;
4022                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4023                                 amd64_call_reg (code, AMD64_R11);
4024                                 amd64_patch (label, code);
4025                         }
4026
4027                         /*
4028                          * This is the address which is saved in seq points,
4029                          */
4030                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4031
4032                         if (cfg->compile_aot) {
4033                                 guint32 offset = code - cfg->native_code;
4034                                 guint32 val;
4035                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4036                                 guint8 *label;
4037
4038                                 /* Load info var */
4039                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4040                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4041                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4042                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4043                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4044                                 label = code;
4045                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4046                                 /* Call the trampoline */
4047                                 amd64_call_reg (code, AMD64_R11);
4048                                 amd64_patch (label, code);
4049                         } else {
4050                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4051                                 guint8 *label;
4052
4053                                 /*
4054                                  * Emit a test+branch against a constant, the constant will be overwritten
4055                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4056                                  */
4057                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4058                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4059                                 label = code;
4060                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4061
4062                                 g_assert (var);
4063                                 g_assert (var->opcode == OP_REGOFFSET);
4064                                 /* Load bp_tramp_var */
4065                                 /* This is equal to &bp_trampoline */
4066                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4067                                 /* Call the trampoline */
4068                                 amd64_call_membase (code, AMD64_R11, 0);
4069                                 amd64_patch (label, code);
4070                         }
4071                         /*
4072                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4073                          * to another IL offset.
4074                          */
4075                         x86_nop (code);
4076                         break;
4077                 }
4078                 case OP_ADDCC:
4079                 case OP_LADDCC:
4080                 case OP_LADD:
4081                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4082                         break;
4083                 case OP_ADC:
4084                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4085                         break;
4086                 case OP_ADD_IMM:
4087                 case OP_LADD_IMM:
4088                         g_assert (amd64_is_imm32 (ins->inst_imm));
4089                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4090                         break;
4091                 case OP_ADC_IMM:
4092                         g_assert (amd64_is_imm32 (ins->inst_imm));
4093                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4094                         break;
4095                 case OP_SUBCC:
4096                 case OP_LSUBCC:
4097                 case OP_LSUB:
4098                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4099                         break;
4100                 case OP_SBB:
4101                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4102                         break;
4103                 case OP_SUB_IMM:
4104                 case OP_LSUB_IMM:
4105                         g_assert (amd64_is_imm32 (ins->inst_imm));
4106                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4107                         break;
4108                 case OP_SBB_IMM:
4109                         g_assert (amd64_is_imm32 (ins->inst_imm));
4110                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4111                         break;
4112                 case OP_LAND:
4113                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4114                         break;
4115                 case OP_AND_IMM:
4116                 case OP_LAND_IMM:
4117                         g_assert (amd64_is_imm32 (ins->inst_imm));
4118                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4119                         break;
4120                 case OP_LMUL:
4121                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4122                         break;
4123                 case OP_MUL_IMM:
4124                 case OP_LMUL_IMM:
4125                 case OP_IMUL_IMM: {
4126                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4127
4128                         switch (ins->inst_imm) {
4129                         case 2:
4130                                 /* MOV r1, r2 */
4131                                 /* ADD r1, r1 */
4132                                 if (ins->dreg != ins->sreg1)
4133                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4134                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4135                                 break;
4136                         case 3:
4137                                 /* LEA r1, [r2 + r2*2] */
4138                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4139                                 break;
4140                         case 5:
4141                                 /* LEA r1, [r2 + r2*4] */
4142                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4143                                 break;
4144                         case 6:
4145                                 /* LEA r1, [r2 + r2*2] */
4146                                 /* ADD r1, r1          */
4147                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4148                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4149                                 break;
4150                         case 9:
4151                                 /* LEA r1, [r2 + r2*8] */
4152                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4153                                 break;
4154                         case 10:
4155                                 /* LEA r1, [r2 + r2*4] */
4156                                 /* ADD r1, r1          */
4157                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4158                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4159                                 break;
4160                         case 12:
4161                                 /* LEA r1, [r2 + r2*2] */
4162                                 /* SHL r1, 2           */
4163                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4164                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4165                                 break;
4166                         case 25:
4167                                 /* LEA r1, [r2 + r2*4] */
4168                                 /* LEA r1, [r1 + r1*4] */
4169                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4170                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4171                                 break;
4172                         case 100:
4173                                 /* LEA r1, [r2 + r2*4] */
4174                                 /* SHL r1, 2           */
4175                                 /* LEA r1, [r1 + r1*4] */
4176                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4177                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4178                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4179                                 break;
4180                         default:
4181                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4182                                 break;
4183                         }
4184                         break;
4185                 }
4186                 case OP_LDIV:
4187                 case OP_LREM:
4188                         /* Regalloc magic makes the div/rem cases the same */
4189                         if (ins->sreg2 == AMD64_RDX) {
4190                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4191                                 amd64_cdq (code);
4192                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4193                         } else {
4194                                 amd64_cdq (code);
4195                                 amd64_div_reg (code, ins->sreg2, TRUE);
4196                         }
4197                         break;
4198                 case OP_LDIV_UN:
4199                 case OP_LREM_UN:
4200                         if (ins->sreg2 == AMD64_RDX) {
4201                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4202                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4203                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4204                         } else {
4205                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4206                                 amd64_div_reg (code, ins->sreg2, FALSE);
4207                         }
4208                         break;
4209                 case OP_IDIV:
4210                 case OP_IREM:
4211                         if (ins->sreg2 == AMD64_RDX) {
4212                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4213                                 amd64_cdq_size (code, 4);
4214                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4215                         } else {
4216                                 amd64_cdq_size (code, 4);
4217                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4218                         }
4219                         break;
4220                 case OP_IDIV_UN:
4221                 case OP_IREM_UN:
4222                         if (ins->sreg2 == AMD64_RDX) {
4223                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4224                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4225                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4226                         } else {
4227                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4228                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4229                         }
4230                         break;
4231                 case OP_LMUL_OVF:
4232                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4233                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4234                         break;
4235                 case OP_LOR:
4236                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4237                         break;
4238                 case OP_OR_IMM:
4239                 case OP_LOR_IMM:
4240                         g_assert (amd64_is_imm32 (ins->inst_imm));
4241                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4242                         break;
4243                 case OP_LXOR:
4244                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4245                         break;
4246                 case OP_XOR_IMM:
4247                 case OP_LXOR_IMM:
4248                         g_assert (amd64_is_imm32 (ins->inst_imm));
4249                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4250                         break;
4251                 case OP_LSHL:
4252                         g_assert (ins->sreg2 == AMD64_RCX);
4253                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4254                         break;
4255                 case OP_LSHR:
4256                         g_assert (ins->sreg2 == AMD64_RCX);
4257                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4258                         break;
4259                 case OP_SHR_IMM:
4260                 case OP_LSHR_IMM:
4261                         g_assert (amd64_is_imm32 (ins->inst_imm));
4262                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4263                         break;
4264                 case OP_SHR_UN_IMM:
4265                         g_assert (amd64_is_imm32 (ins->inst_imm));
4266                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4267                         break;
4268                 case OP_LSHR_UN_IMM:
4269                         g_assert (amd64_is_imm32 (ins->inst_imm));
4270                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4271                         break;
4272                 case OP_LSHR_UN:
4273                         g_assert (ins->sreg2 == AMD64_RCX);
4274                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4275                         break;
4276                 case OP_SHL_IMM:
4277                 case OP_LSHL_IMM:
4278                         g_assert (amd64_is_imm32 (ins->inst_imm));
4279                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4280                         break;
4281
4282                 case OP_IADDCC:
4283                 case OP_IADD:
4284                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4285                         break;
4286                 case OP_IADC:
4287                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4288                         break;
4289                 case OP_IADD_IMM:
4290                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4291                         break;
4292                 case OP_IADC_IMM:
4293                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4294                         break;
4295                 case OP_ISUBCC:
4296                 case OP_ISUB:
4297                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4298                         break;
4299                 case OP_ISBB:
4300                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4301                         break;
4302                 case OP_ISUB_IMM:
4303                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4304                         break;
4305                 case OP_ISBB_IMM:
4306                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4307                         break;
4308                 case OP_IAND:
4309                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4310                         break;
4311                 case OP_IAND_IMM:
4312                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4313                         break;
4314                 case OP_IOR:
4315                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4316                         break;
4317                 case OP_IOR_IMM:
4318                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4319                         break;
4320                 case OP_IXOR:
4321                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4322                         break;
4323                 case OP_IXOR_IMM:
4324                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4325                         break;
4326                 case OP_INEG:
4327                         amd64_neg_reg_size (code, ins->sreg1, 4);
4328                         break;
4329                 case OP_INOT:
4330                         amd64_not_reg_size (code, ins->sreg1, 4);
4331                         break;
4332                 case OP_ISHL:
4333                         g_assert (ins->sreg2 == AMD64_RCX);
4334                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4335                         break;
4336                 case OP_ISHR:
4337                         g_assert (ins->sreg2 == AMD64_RCX);
4338                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4339                         break;
4340                 case OP_ISHR_IMM:
4341                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4342                         break;
4343                 case OP_ISHR_UN_IMM:
4344                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4345                         break;
4346                 case OP_ISHR_UN:
4347                         g_assert (ins->sreg2 == AMD64_RCX);
4348                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4349                         break;
4350                 case OP_ISHL_IMM:
4351                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4352                         break;
4353                 case OP_IMUL:
4354                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4355                         break;
4356                 case OP_IMUL_OVF:
4357                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4358                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4359                         break;
4360                 case OP_IMUL_OVF_UN:
4361                 case OP_LMUL_OVF_UN: {
4362                         /* the mul operation and the exception check should most likely be split */
4363                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4364                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4365                         /*g_assert (ins->sreg2 == X86_EAX);
4366                         g_assert (ins->dreg == X86_EAX);*/
4367                         if (ins->sreg2 == X86_EAX) {
4368                                 non_eax_reg = ins->sreg1;
4369                         } else if (ins->sreg1 == X86_EAX) {
4370                                 non_eax_reg = ins->sreg2;
4371                         } else {
4372                                 /* no need to save since we're going to store to it anyway */
4373                                 if (ins->dreg != X86_EAX) {
4374                                         saved_eax = TRUE;
4375                                         amd64_push_reg (code, X86_EAX);
4376                                 }
4377                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4378                                 non_eax_reg = ins->sreg2;
4379                         }
4380                         if (ins->dreg == X86_EDX) {
4381                                 if (!saved_eax) {
4382                                         saved_eax = TRUE;
4383                                         amd64_push_reg (code, X86_EAX);
4384                                 }
4385                         } else {
4386                                 saved_edx = TRUE;
4387                                 amd64_push_reg (code, X86_EDX);
4388                         }
4389                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4390                         /* save before the check since pop and mov don't change the flags */
4391                         if (ins->dreg != X86_EAX)
4392                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4393                         if (saved_edx)
4394                                 amd64_pop_reg (code, X86_EDX);
4395                         if (saved_eax)
4396                                 amd64_pop_reg (code, X86_EAX);
4397                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4398                         break;
4399                 }
4400                 case OP_ICOMPARE:
4401                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4402                         break;
4403                 case OP_ICOMPARE_IMM:
4404                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4405                         break;
4406                 case OP_IBEQ:
4407                 case OP_IBLT:
4408                 case OP_IBGT:
4409                 case OP_IBGE:
4410                 case OP_IBLE:
4411                 case OP_LBEQ:
4412                 case OP_LBLT:
4413                 case OP_LBGT:
4414                 case OP_LBGE:
4415                 case OP_LBLE:
4416                 case OP_IBNE_UN:
4417                 case OP_IBLT_UN:
4418                 case OP_IBGT_UN:
4419                 case OP_IBGE_UN:
4420                 case OP_IBLE_UN:
4421                 case OP_LBNE_UN:
4422                 case OP_LBLT_UN:
4423                 case OP_LBGT_UN:
4424                 case OP_LBGE_UN:
4425                 case OP_LBLE_UN:
4426                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4427                         break;
4428
4429                 case OP_CMOV_IEQ:
4430                 case OP_CMOV_IGE:
4431                 case OP_CMOV_IGT:
4432                 case OP_CMOV_ILE:
4433                 case OP_CMOV_ILT:
4434                 case OP_CMOV_INE_UN:
4435                 case OP_CMOV_IGE_UN:
4436                 case OP_CMOV_IGT_UN:
4437                 case OP_CMOV_ILE_UN:
4438                 case OP_CMOV_ILT_UN:
4439                 case OP_CMOV_LEQ:
4440                 case OP_CMOV_LGE:
4441                 case OP_CMOV_LGT:
4442                 case OP_CMOV_LLE:
4443                 case OP_CMOV_LLT:
4444                 case OP_CMOV_LNE_UN:
4445                 case OP_CMOV_LGE_UN:
4446                 case OP_CMOV_LGT_UN:
4447                 case OP_CMOV_LLE_UN:
4448                 case OP_CMOV_LLT_UN:
4449                         g_assert (ins->dreg == ins->sreg1);
4450                         /* This needs to operate on 64 bit values */
4451                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4452                         break;
4453
4454                 case OP_LNOT:
4455                         amd64_not_reg (code, ins->sreg1);
4456                         break;
4457                 case OP_LNEG:
4458                         amd64_neg_reg (code, ins->sreg1);
4459                         break;
4460
4461                 case OP_ICONST:
4462                 case OP_I8CONST:
4463                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4464                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4465                         else
4466                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4467                         break;
4468                 case OP_AOTCONST:
4469                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4470                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4471                         break;
4472                 case OP_JUMP_TABLE:
4473                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4474                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4475                         break;
4476                 case OP_MOVE:
4477                         if (ins->dreg != ins->sreg1)
4478                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4479                         break;
4480                 case OP_AMD64_SET_XMMREG_R4: {
4481                         if (cfg->r4fp) {
4482                                 if (ins->dreg != ins->sreg1)
4483                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4484                         } else {
4485                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4486                         }
4487                         break;
4488                 }
4489                 case OP_AMD64_SET_XMMREG_R8: {
4490                         if (ins->dreg != ins->sreg1)
4491                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4492                         break;
4493                 }
4494                 case OP_TAILCALL: {
4495                         MonoCallInst *call = (MonoCallInst*)ins;
4496                         int i, save_area_offset;
4497
4498                         g_assert (!cfg->method->save_lmf);
4499
4500                         /* Restore callee saved registers */
4501                         save_area_offset = cfg->arch.reg_save_area_offset;
4502                         for (i = 0; i < AMD64_NREG; ++i)
4503                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4504                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4505                                         save_area_offset += 8;
4506                                 }
4507
4508                         if (cfg->arch.omit_fp) {
4509                                 if (cfg->arch.stack_alloc_size)
4510                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4511                                 // FIXME:
4512                                 if (call->stack_usage)
4513                                         NOT_IMPLEMENTED;
4514                         } else {
4515                                 /* Copy arguments on the stack to our argument area */
4516                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4517                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4518                                         amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4519                                 }
4520
4521 #ifdef TARGET_WIN32
4522                                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4523                                 amd64_pop_reg (code, AMD64_RBP);
4524                                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4525 #else
4526                                 amd64_leave (code);
4527 #endif
4528                         }
4529
4530                         offset = code - cfg->native_code;
4531                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4532                         if (cfg->compile_aot)
4533                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4534                         else
4535                                 amd64_set_reg_template (code, AMD64_R11);
4536                         amd64_jump_reg (code, AMD64_R11);
4537                         ins->flags |= MONO_INST_GC_CALLSITE;
4538                         ins->backend.pc_offset = code - cfg->native_code;
4539                         break;
4540                 }
4541                 case OP_CHECK_THIS:
4542                         /* ensure ins->sreg1 is not NULL */
4543                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4544                         break;
4545                 case OP_ARGLIST: {
4546                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4547                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4548                         break;
4549                 }
4550                 case OP_CALL:
4551                 case OP_FCALL:
4552                 case OP_RCALL:
4553                 case OP_LCALL:
4554                 case OP_VCALL:
4555                 case OP_VCALL2:
4556                 case OP_VOIDCALL:
4557                         call = (MonoCallInst*)ins;
4558                         /*
4559                          * The AMD64 ABI forces callers to know about varargs.
4560                          */
4561                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4562                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4563                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4564                                 /*
4565                                  * Since the unmanaged calling convention doesn't contain a
4566                                  * 'vararg' entry, we have to treat every pinvoke call as a
4567                                  * potential vararg call.
4568                                  */
4569                                 guint32 nregs, i;
4570                                 nregs = 0;
4571                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4572                                         if (call->used_fregs & (1 << i))
4573                                                 nregs ++;
4574                                 if (!nregs)
4575                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4576                                 else
4577                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4578                         }
4579
4580                         if (ins->flags & MONO_INST_HAS_METHOD)
4581                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4582                         else
4583                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4584                         ins->flags |= MONO_INST_GC_CALLSITE;
4585                         ins->backend.pc_offset = code - cfg->native_code;
4586                         code = emit_move_return_value (cfg, ins, code);
4587                         break;
4588                 case OP_FCALL_REG:
4589                 case OP_RCALL_REG:
4590                 case OP_LCALL_REG:
4591                 case OP_VCALL_REG:
4592                 case OP_VCALL2_REG:
4593                 case OP_VOIDCALL_REG:
4594                 case OP_CALL_REG:
4595                         call = (MonoCallInst*)ins;
4596
4597                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4598                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4599                                 ins->sreg1 = AMD64_R11;
4600                         }
4601
4602                         /*
4603                          * The AMD64 ABI forces callers to know about varargs.
4604                          */
4605                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4606                                 if (ins->sreg1 == AMD64_RAX) {
4607                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4608                                         ins->sreg1 = AMD64_R11;
4609                                 }
4610                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4611                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4612                                 /*
4613                                  * Since the unmanaged calling convention doesn't contain a
4614                                  * 'vararg' entry, we have to treat every pinvoke call as a
4615                                  * potential vararg call.
4616                                  */
4617                                 guint32 nregs, i;
4618                                 nregs = 0;
4619                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4620                                         if (call->used_fregs & (1 << i))
4621                                                 nregs ++;
4622                                 if (ins->sreg1 == AMD64_RAX) {
4623                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4624                                         ins->sreg1 = AMD64_R11;
4625                                 }
4626                                 if (!nregs)
4627                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4628                                 else
4629                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4630                         }
4631
4632                         amd64_call_reg (code, ins->sreg1);
4633                         ins->flags |= MONO_INST_GC_CALLSITE;
4634                         ins->backend.pc_offset = code - cfg->native_code;
4635                         code = emit_move_return_value (cfg, ins, code);
4636                         break;
4637                 case OP_FCALL_MEMBASE:
4638                 case OP_RCALL_MEMBASE:
4639                 case OP_LCALL_MEMBASE:
4640                 case OP_VCALL_MEMBASE:
4641                 case OP_VCALL2_MEMBASE:
4642                 case OP_VOIDCALL_MEMBASE:
4643                 case OP_CALL_MEMBASE:
4644                         call = (MonoCallInst*)ins;
4645
4646                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4647                         ins->flags |= MONO_INST_GC_CALLSITE;
4648                         ins->backend.pc_offset = code - cfg->native_code;
4649                         code = emit_move_return_value (cfg, ins, code);
4650                         break;
4651                 case OP_DYN_CALL: {
4652                         int i;
4653                         MonoInst *var = cfg->dyn_call_var;
4654                         guint8 *label;
4655
4656                         g_assert (var->opcode == OP_REGOFFSET);
4657
4658                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4659                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4660                         /* r10 = ftn */
4661                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4662
4663                         /* Save args buffer */
4664                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4665
4666                         /* Set fp arg regs */
4667                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4668                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4669                         label = code;
4670                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4671                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4672                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4673                         amd64_patch (label, code);
4674
4675                         /* Set stack args */
4676                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4677                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4678                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4679                         }
4680
4681                         /* Set argument registers */
4682                         for (i = 0; i < PARAM_REGS; ++i)
4683                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4684
4685                         /* Make the call */
4686                         amd64_call_reg (code, AMD64_R10);
4687
4688                         ins->flags |= MONO_INST_GC_CALLSITE;
4689                         ins->backend.pc_offset = code - cfg->native_code;
4690
4691                         /* Save result */
4692                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4693                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4694                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4695                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4696                         break;
4697                 }
4698                 case OP_AMD64_SAVE_SP_TO_LMF: {
4699                         MonoInst *lmf_var = cfg->lmf_var;
4700                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4701                         break;
4702                 }
4703                 case OP_X86_PUSH:
4704                         g_assert_not_reached ();
4705                         amd64_push_reg (code, ins->sreg1);
4706                         break;
4707                 case OP_X86_PUSH_IMM:
4708                         g_assert_not_reached ();
4709                         g_assert (amd64_is_imm32 (ins->inst_imm));
4710                         amd64_push_imm (code, ins->inst_imm);
4711                         break;
4712                 case OP_X86_PUSH_MEMBASE:
4713                         g_assert_not_reached ();
4714                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4715                         break;
4716                 case OP_X86_PUSH_OBJ: {
4717                         int size = ALIGN_TO (ins->inst_imm, 8);
4718
4719                         g_assert_not_reached ();
4720
4721                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4722                         amd64_push_reg (code, AMD64_RDI);
4723                         amd64_push_reg (code, AMD64_RSI);
4724                         amd64_push_reg (code, AMD64_RCX);
4725                         if (ins->inst_offset)
4726                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4727                         else
4728                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4729                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4730                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4731                         amd64_cld (code);
4732                         amd64_prefix (code, X86_REP_PREFIX);
4733                         amd64_movsd (code);
4734                         amd64_pop_reg (code, AMD64_RCX);
4735                         amd64_pop_reg (code, AMD64_RSI);
4736                         amd64_pop_reg (code, AMD64_RDI);
4737                         break;
4738                 }
4739                 case OP_GENERIC_CLASS_INIT: {
4740                         guint8 *jump;
4741
4742                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4743
4744                         amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4745                         jump = code;
4746                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4747
4748                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4749                         ins->flags |= MONO_INST_GC_CALLSITE;
4750                         ins->backend.pc_offset = code - cfg->native_code;
4751
4752                         x86_patch (jump, code);
4753                         break;
4754                 }
4755
4756                 case OP_X86_LEA:
4757                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4758                         break;
4759                 case OP_X86_LEA_MEMBASE:
4760                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4761                         break;
4762                 case OP_X86_XCHG:
4763                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4764                         break;
4765                 case OP_LOCALLOC:
4766                         /* keep alignment */
4767                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4768                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4769                         code = mono_emit_stack_alloc (cfg, code, ins);
4770                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4771                         if (cfg->param_area)
4772                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4773                         break;
4774                 case OP_LOCALLOC_IMM: {
4775                         guint32 size = ins->inst_imm;
4776                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4777
4778                         if (ins->flags & MONO_INST_INIT) {
4779                                 if (size < 64) {
4780                                         int i;
4781
4782                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4783                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4784
4785                                         for (i = 0; i < size; i += 8)
4786                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4787                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4788                                 } else {
4789                                         amd64_mov_reg_imm (code, ins->dreg, size);
4790                                         ins->sreg1 = ins->dreg;
4791
4792                                         code = mono_emit_stack_alloc (cfg, code, ins);
4793                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4794                                 }
4795                         } else {
4796                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4797                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4798                         }
4799                         if (cfg->param_area)
4800                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4801                         break;
4802                 }
4803                 case OP_THROW: {
4804                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4805                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4806                                              (gpointer)"mono_arch_throw_exception", FALSE);
4807                         ins->flags |= MONO_INST_GC_CALLSITE;
4808                         ins->backend.pc_offset = code - cfg->native_code;
4809                         break;
4810                 }
4811                 case OP_RETHROW: {
4812                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4813                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4814                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4815                         ins->flags |= MONO_INST_GC_CALLSITE;
4816                         ins->backend.pc_offset = code - cfg->native_code;
4817                         break;
4818                 }
4819                 case OP_CALL_HANDLER:
4820                         /* Align stack */
4821                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4822                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4823                         amd64_call_imm (code, 0);
4824                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4825                         /* Restore stack alignment */
4826                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4827                         break;
4828                 case OP_START_HANDLER: {
4829                         /* Even though we're saving RSP, use sizeof */
4830                         /* gpointer because spvar is of type IntPtr */
4831                         /* see: mono_create_spvar_for_region */
4832                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4833                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4834
4835                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4836                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4837                                 cfg->param_area) {
4838                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4839                         }
4840                         break;
4841                 }
4842                 case OP_ENDFINALLY: {
4843                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4844                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4845                         amd64_ret (code);
4846                         break;
4847                 }
4848                 case OP_ENDFILTER: {
4849                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4850                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4851                         /* The local allocator will put the result into RAX */
4852                         amd64_ret (code);
4853                         break;
4854                 }
4855                 case OP_GET_EX_OBJ:
4856                         if (ins->dreg != AMD64_RAX)
4857                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4858                         break;
4859                 case OP_LABEL:
4860                         ins->inst_c0 = code - cfg->native_code;
4861                         break;
4862                 case OP_BR:
4863                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4864                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4865                         //break;
4866                                 if (ins->inst_target_bb->native_offset) {
4867                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4868                                 } else {
4869                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4870                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4871                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4872                                                 x86_jump8 (code, 0);
4873                                         else
4874                                                 x86_jump32 (code, 0);
4875                         }
4876                         break;
4877                 case OP_BR_REG:
4878                         amd64_jump_reg (code, ins->sreg1);
4879                         break;
4880                 case OP_ICNEQ:
4881                 case OP_ICGE:
4882                 case OP_ICLE:
4883                 case OP_ICGE_UN:
4884                 case OP_ICLE_UN:
4885
4886                 case OP_CEQ:
4887                 case OP_LCEQ:
4888                 case OP_ICEQ:
4889                 case OP_CLT:
4890                 case OP_LCLT:
4891                 case OP_ICLT:
4892                 case OP_CGT:
4893                 case OP_ICGT:
4894                 case OP_LCGT:
4895                 case OP_CLT_UN:
4896                 case OP_LCLT_UN:
4897                 case OP_ICLT_UN:
4898                 case OP_CGT_UN:
4899                 case OP_LCGT_UN:
4900                 case OP_ICGT_UN:
4901                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4902                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4903                         break;
4904                 case OP_COND_EXC_EQ:
4905                 case OP_COND_EXC_NE_UN:
4906                 case OP_COND_EXC_LT:
4907                 case OP_COND_EXC_LT_UN:
4908                 case OP_COND_EXC_GT:
4909                 case OP_COND_EXC_GT_UN:
4910                 case OP_COND_EXC_GE:
4911                 case OP_COND_EXC_GE_UN:
4912                 case OP_COND_EXC_LE:
4913                 case OP_COND_EXC_LE_UN:
4914                 case OP_COND_EXC_IEQ:
4915                 case OP_COND_EXC_INE_UN:
4916                 case OP_COND_EXC_ILT:
4917                 case OP_COND_EXC_ILT_UN:
4918                 case OP_COND_EXC_IGT:
4919                 case OP_COND_EXC_IGT_UN:
4920                 case OP_COND_EXC_IGE:
4921                 case OP_COND_EXC_IGE_UN:
4922                 case OP_COND_EXC_ILE:
4923                 case OP_COND_EXC_ILE_UN:
4924                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4925                         break;
4926                 case OP_COND_EXC_OV:
4927                 case OP_COND_EXC_NO:
4928                 case OP_COND_EXC_C:
4929                 case OP_COND_EXC_NC:
4930                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4931                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4932                         break;
4933                 case OP_COND_EXC_IOV:
4934                 case OP_COND_EXC_INO:
4935                 case OP_COND_EXC_IC:
4936                 case OP_COND_EXC_INC:
4937                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4938                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4939                         break;
4940
4941                 /* floating point opcodes */
4942                 case OP_R8CONST: {
4943                         double d = *(double *)ins->inst_p0;
4944
4945                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4946                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4947                         }
4948                         else {
4949                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4950                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4951                         }
4952                         break;
4953                 }
4954                 case OP_R4CONST: {
4955                         float f = *(float *)ins->inst_p0;
4956
4957                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4958                                 if (cfg->r4fp)
4959                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4960                                 else
4961                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4962                         }
4963                         else {
4964                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4965                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4966                                 if (!cfg->r4fp)
4967                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4968                         }
4969                         break;
4970                 }
4971                 case OP_STORER8_MEMBASE_REG:
4972                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4973                         break;
4974                 case OP_LOADR8_MEMBASE:
4975                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4976                         break;
4977                 case OP_STORER4_MEMBASE_REG:
4978                         if (cfg->r4fp) {
4979                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4980                         } else {
4981                                 /* This requires a double->single conversion */
4982                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4983                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4984                         }
4985                         break;
4986                 case OP_LOADR4_MEMBASE:
4987                         if (cfg->r4fp) {
4988                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4989                         } else {
4990                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4991                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4992                         }
4993                         break;
4994                 case OP_ICONV_TO_R4:
4995                         if (cfg->r4fp) {
4996                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4997                         } else {
4998                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4999                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5000                         }
5001                         break;
5002                 case OP_ICONV_TO_R8:
5003                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5004                         break;
5005                 case OP_LCONV_TO_R4:
5006                         if (cfg->r4fp) {
5007                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5008                         } else {
5009                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5010                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5011                         }
5012                         break;
5013                 case OP_LCONV_TO_R8:
5014                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5015                         break;
5016                 case OP_FCONV_TO_R4:
5017                         if (cfg->r4fp) {
5018                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5019                         } else {
5020                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5021                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5022                         }
5023                         break;
5024                 case OP_FCONV_TO_I1:
5025                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5026                         break;
5027                 case OP_FCONV_TO_U1:
5028                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5029                         break;
5030                 case OP_FCONV_TO_I2:
5031                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5032                         break;
5033                 case OP_FCONV_TO_U2:
5034                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5035                         break;
5036                 case OP_FCONV_TO_U4:
5037                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5038                         break;
5039                 case OP_FCONV_TO_I4:
5040                 case OP_FCONV_TO_I:
5041                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5042                         break;
5043                 case OP_FCONV_TO_I8:
5044                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5045                         break;
5046
5047                 case OP_RCONV_TO_I1:
5048                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5049                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5050                         break;
5051                 case OP_RCONV_TO_U1:
5052                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5053                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5054                         break;
5055                 case OP_RCONV_TO_I2:
5056                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5057                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5058                         break;
5059                 case OP_RCONV_TO_U2:
5060                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5061                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5062                         break;
5063                 case OP_RCONV_TO_I4:
5064                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5065                         break;
5066                 case OP_RCONV_TO_U4:
5067                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5068                         break;
5069                 case OP_RCONV_TO_I8:
5070                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5071                         break;
5072                 case OP_RCONV_TO_R8:
5073                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5074                         break;
5075                 case OP_RCONV_TO_R4:
5076                         if (ins->dreg != ins->sreg1)
5077                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5078                         break;
5079
5080                 case OP_LCONV_TO_R_UN: {
5081                         guint8 *br [2];
5082
5083                         /* Based on gcc code */
5084                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5085                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5086
5087                         /* Positive case */
5088                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5089                         br [1] = code; x86_jump8 (code, 0);
5090                         amd64_patch (br [0], code);
5091
5092                         /* Negative case */
5093                         /* Save to the red zone */
5094                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5095                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5096                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5097                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5098                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5099                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5100                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5101                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5102                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5103                         /* Restore */
5104                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5105                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5106                         amd64_patch (br [1], code);
5107                         break;
5108                 }
5109                 case OP_LCONV_TO_OVF_U4:
5110                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5111                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5112                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5113                         break;
5114                 case OP_LCONV_TO_OVF_I4_UN:
5115                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5116                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5117                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5118                         break;
5119                 case OP_FMOVE:
5120                         if (ins->dreg != ins->sreg1)
5121                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5122                         break;
5123                 case OP_RMOVE:
5124                         if (ins->dreg != ins->sreg1)
5125                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5126                         break;
5127                 case OP_MOVE_F_TO_I4:
5128                         if (cfg->r4fp) {
5129                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5130                         } else {
5131                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5132                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5133                         }
5134                         break;
5135                 case OP_MOVE_I4_TO_F:
5136                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5137                         if (!cfg->r4fp)
5138                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5139                         break;
5140                 case OP_MOVE_F_TO_I8:
5141                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5142                         break;
5143                 case OP_MOVE_I8_TO_F:
5144                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5145                         break;
5146                 case OP_FADD:
5147                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5148                         break;
5149                 case OP_FSUB:
5150                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5151                         break;
5152                 case OP_FMUL:
5153                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5154                         break;
5155                 case OP_FDIV:
5156                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5157                         break;
5158                 case OP_FNEG: {
5159                         static double r8_0 = -0.0;
5160
5161                         g_assert (ins->sreg1 == ins->dreg);
5162
5163                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5164                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5165                         break;
5166                 }
5167                 case OP_SIN:
5168                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5169                         break;
5170                 case OP_COS:
5171                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5172                         break;
5173                 case OP_ABS: {
5174                         static guint64 d = 0x7fffffffffffffffUL;
5175
5176                         g_assert (ins->sreg1 == ins->dreg);
5177
5178                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5179                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5180                         break;
5181                 }
5182                 case OP_SQRT:
5183                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5184                         break;
5185
5186                 case OP_RADD:
5187                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5188                         break;
5189                 case OP_RSUB:
5190                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5191                         break;
5192                 case OP_RMUL:
5193                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5194                         break;
5195                 case OP_RDIV:
5196                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5197                         break;
5198                 case OP_RNEG: {
5199                         static float r4_0 = -0.0;
5200
5201                         g_assert (ins->sreg1 == ins->dreg);
5202
5203                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5204                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5205                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5206                         break;
5207                 }
5208
5209                 case OP_IMIN:
5210                         g_assert (cfg->opt & MONO_OPT_CMOV);
5211                         g_assert (ins->dreg == ins->sreg1);
5212                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5213                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5214                         break;
5215                 case OP_IMIN_UN:
5216                         g_assert (cfg->opt & MONO_OPT_CMOV);
5217                         g_assert (ins->dreg == ins->sreg1);
5218                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5219                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5220                         break;
5221                 case OP_IMAX:
5222                         g_assert (cfg->opt & MONO_OPT_CMOV);
5223                         g_assert (ins->dreg == ins->sreg1);
5224                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5225                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5226                         break;
5227                 case OP_IMAX_UN:
5228                         g_assert (cfg->opt & MONO_OPT_CMOV);
5229                         g_assert (ins->dreg == ins->sreg1);
5230                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5231                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5232                         break;
5233                 case OP_LMIN:
5234                         g_assert (cfg->opt & MONO_OPT_CMOV);
5235                         g_assert (ins->dreg == ins->sreg1);
5236                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5237                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5238                         break;
5239                 case OP_LMIN_UN:
5240                         g_assert (cfg->opt & MONO_OPT_CMOV);
5241                         g_assert (ins->dreg == ins->sreg1);
5242                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5243                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5244                         break;
5245                 case OP_LMAX:
5246                         g_assert (cfg->opt & MONO_OPT_CMOV);
5247                         g_assert (ins->dreg == ins->sreg1);
5248                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5249                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5250                         break;
5251                 case OP_LMAX_UN:
5252                         g_assert (cfg->opt & MONO_OPT_CMOV);
5253                         g_assert (ins->dreg == ins->sreg1);
5254                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5255                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5256                         break;
5257                 case OP_X86_FPOP:
5258                         break;
5259                 case OP_FCOMPARE:
5260                         /*
5261                          * The two arguments are swapped because the fbranch instructions
5262                          * depend on this for the non-sse case to work.
5263                          */
5264                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5265                         break;
5266                 case OP_RCOMPARE:
5267                         /*
5268                          * FIXME: Get rid of this.
5269                          * The two arguments are swapped because the fbranch instructions
5270                          * depend on this for the non-sse case to work.
5271                          */
5272                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5273                         break;
5274                 case OP_FCNEQ:
5275                 case OP_FCEQ: {
5276                         /* zeroing the register at the start results in
5277                          * shorter and faster code (we can also remove the widening op)
5278                          */
5279                         guchar *unordered_check;
5280
5281                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5282                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5283                         unordered_check = code;
5284                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5285
5286                         if (ins->opcode == OP_FCEQ) {
5287                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5288                                 amd64_patch (unordered_check, code);
5289                         } else {
5290                                 guchar *jump_to_end;
5291                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5292                                 jump_to_end = code;
5293                                 x86_jump8 (code, 0);
5294                                 amd64_patch (unordered_check, code);
5295                                 amd64_inc_reg (code, ins->dreg);
5296                                 amd64_patch (jump_to_end, code);
5297                         }
5298                         break;
5299                 }
5300                 case OP_FCLT:
5301                 case OP_FCLT_UN: {
5302                         /* zeroing the register at the start results in
5303                          * shorter and faster code (we can also remove the widening op)
5304                          */
5305                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5306                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5307                         if (ins->opcode == OP_FCLT_UN) {
5308                                 guchar *unordered_check = code;
5309                                 guchar *jump_to_end;
5310                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5311                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5312                                 jump_to_end = code;
5313                                 x86_jump8 (code, 0);
5314                                 amd64_patch (unordered_check, code);
5315                                 amd64_inc_reg (code, ins->dreg);
5316                                 amd64_patch (jump_to_end, code);
5317                         } else {
5318                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5319                         }
5320                         break;
5321                 }
5322                 case OP_FCLE: {
5323                         guchar *unordered_check;
5324                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5325                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5326                         unordered_check = code;
5327                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5328                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5329                         amd64_patch (unordered_check, code);
5330                         break;
5331                 }
5332                 case OP_FCGT:
5333                 case OP_FCGT_UN: {
5334                         /* zeroing the register at the start results in
5335                          * shorter and faster code (we can also remove the widening op)
5336                          */
5337                         guchar *unordered_check;
5338
5339                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5340                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5341                         if (ins->opcode == OP_FCGT) {
5342                                 unordered_check = code;
5343                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5344                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5345                                 amd64_patch (unordered_check, code);
5346                         } else {
5347                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5348                         }
5349                         break;
5350                 }
5351                 case OP_FCGE: {
5352                         guchar *unordered_check;
5353                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5354                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5355                         unordered_check = code;
5356                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5357                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5358                         amd64_patch (unordered_check, code);
5359                         break;
5360                 }
5361
5362                 case OP_RCEQ:
5363                 case OP_RCGT:
5364                 case OP_RCLT:
5365                 case OP_RCLT_UN:
5366                 case OP_RCGT_UN: {
5367                         int x86_cond;
5368                         gboolean unordered = FALSE;
5369
5370                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5371                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5372
5373                         switch (ins->opcode) {
5374                         case OP_RCEQ:
5375                                 x86_cond = X86_CC_EQ;
5376                                 break;
5377                         case OP_RCGT:
5378                                 x86_cond = X86_CC_LT;
5379                                 break;
5380                         case OP_RCLT:
5381                                 x86_cond = X86_CC_GT;
5382                                 break;
5383                         case OP_RCLT_UN:
5384                                 x86_cond = X86_CC_GT;
5385                                 unordered = TRUE;
5386                                 break;
5387                         case OP_RCGT_UN:
5388                                 x86_cond = X86_CC_LT;
5389                                 unordered = TRUE;
5390                                 break;
5391                         default:
5392                                 g_assert_not_reached ();
5393                                 break;
5394                         }
5395
5396                         if (unordered) {
5397                                 guchar *unordered_check;
5398                                 guchar *jump_to_end;
5399
5400                                 unordered_check = code;
5401                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5402                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5403                                 jump_to_end = code;
5404                                 x86_jump8 (code, 0);
5405                                 amd64_patch (unordered_check, code);
5406                                 amd64_inc_reg (code, ins->dreg);
5407                                 amd64_patch (jump_to_end, code);
5408                         } else {
5409                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5410                         }
5411                         break;
5412                 }
5413                 case OP_FCLT_MEMBASE:
5414                 case OP_FCGT_MEMBASE:
5415                 case OP_FCLT_UN_MEMBASE:
5416                 case OP_FCGT_UN_MEMBASE:
5417                 case OP_FCEQ_MEMBASE: {
5418                         guchar *unordered_check, *jump_to_end;
5419                         int x86_cond;
5420
5421                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5422                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5423
5424                         switch (ins->opcode) {
5425                         case OP_FCEQ_MEMBASE:
5426                                 x86_cond = X86_CC_EQ;
5427                                 break;
5428                         case OP_FCLT_MEMBASE:
5429                         case OP_FCLT_UN_MEMBASE:
5430                                 x86_cond = X86_CC_LT;
5431                                 break;
5432                         case OP_FCGT_MEMBASE:
5433                         case OP_FCGT_UN_MEMBASE:
5434                                 x86_cond = X86_CC_GT;
5435                                 break;
5436                         default:
5437                                 g_assert_not_reached ();
5438                         }
5439
5440                         unordered_check = code;
5441                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5442                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5443
5444                         switch (ins->opcode) {
5445                         case OP_FCEQ_MEMBASE:
5446                         case OP_FCLT_MEMBASE:
5447                         case OP_FCGT_MEMBASE:
5448                                 amd64_patch (unordered_check, code);
5449                                 break;
5450                         case OP_FCLT_UN_MEMBASE:
5451                         case OP_FCGT_UN_MEMBASE:
5452                                 jump_to_end = code;
5453                                 x86_jump8 (code, 0);
5454                                 amd64_patch (unordered_check, code);
5455                                 amd64_inc_reg (code, ins->dreg);
5456                                 amd64_patch (jump_to_end, code);
5457                                 break;
5458                         default:
5459                                 break;
5460                         }
5461                         break;
5462                 }
5463                 case OP_FBEQ: {
5464                         guchar *jump = code;
5465                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5466                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5467                         amd64_patch (jump, code);
5468                         break;
5469                 }
5470                 case OP_FBNE_UN:
5471                         /* Branch if C013 != 100 */
5472                         /* branch if !ZF or (PF|CF) */
5473                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5474                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5475                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5476                         break;
5477                 case OP_FBLT:
5478                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5479                         break;
5480                 case OP_FBLT_UN:
5481                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5482                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5483                         break;
5484                 case OP_FBGT:
5485                 case OP_FBGT_UN:
5486                         if (ins->opcode == OP_FBGT) {
5487                                 guchar *br1;
5488
5489                                 /* skip branch if C1=1 */
5490                                 br1 = code;
5491                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5492                                 /* branch if (C0 | C3) = 1 */
5493                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5494                                 amd64_patch (br1, code);
5495                                 break;
5496                         } else {
5497                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5498                         }
5499                         break;
5500                 case OP_FBGE: {
5501                         /* Branch if C013 == 100 or 001 */
5502                         guchar *br1;
5503
5504                         /* skip branch if C1=1 */
5505                         br1 = code;
5506                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5507                         /* branch if (C0 | C3) = 1 */
5508                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5509                         amd64_patch (br1, code);
5510                         break;
5511                 }
5512                 case OP_FBGE_UN:
5513                         /* Branch if C013 == 000 */
5514                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5515                         break;
5516                 case OP_FBLE: {
5517                         /* Branch if C013=000 or 100 */
5518                         guchar *br1;
5519
5520                         /* skip branch if C1=1 */
5521                         br1 = code;
5522                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5523                         /* branch if C0=0 */
5524                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5525                         amd64_patch (br1, code);
5526                         break;
5527                 }
5528                 case OP_FBLE_UN:
5529                         /* Branch if C013 != 001 */
5530                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5531                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5532                         break;
5533                 case OP_CKFINITE:
5534                         /* Transfer value to the fp stack */
5535                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5536                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5537                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5538
5539                         amd64_push_reg (code, AMD64_RAX);
5540                         amd64_fxam (code);
5541                         amd64_fnstsw (code);
5542                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5543                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5544                         amd64_pop_reg (code, AMD64_RAX);
5545                         amd64_fstp (code, 0);
5546                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5547                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5548                         break;
5549                 case OP_TLS_GET: {
5550                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5551                         break;
5552                 }
5553                 case OP_TLS_SET: {
5554                         code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5555                         break;
5556                 }
5557                 case OP_MEMORY_BARRIER: {
5558                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5559                                 x86_mfence (code);
5560                         break;
5561                 }
5562                 case OP_ATOMIC_ADD_I4:
5563                 case OP_ATOMIC_ADD_I8: {
5564                         int dreg = ins->dreg;
5565                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5566
5567                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5568                                 dreg = AMD64_R11;
5569
5570                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5571                         amd64_prefix (code, X86_LOCK_PREFIX);
5572                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5573                         /* dreg contains the old value, add with sreg2 value */
5574                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5575
5576                         if (ins->dreg != dreg)
5577                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5578
5579                         break;
5580                 }
5581                 case OP_ATOMIC_EXCHANGE_I4:
5582                 case OP_ATOMIC_EXCHANGE_I8: {
5583                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5584
5585                         /* LOCK prefix is implied. */
5586                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5587                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5588                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5589                         break;
5590                 }
5591                 case OP_ATOMIC_CAS_I4:
5592                 case OP_ATOMIC_CAS_I8: {
5593                         guint32 size;
5594
5595                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5596                                 size = 8;
5597                         else
5598                                 size = 4;
5599
5600                         /*
5601                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5602                          * an explanation of how this works.
5603                          */
5604                         g_assert (ins->sreg3 == AMD64_RAX);
5605                         g_assert (ins->sreg1 != AMD64_RAX);
5606                         g_assert (ins->sreg1 != ins->sreg2);
5607
5608                         amd64_prefix (code, X86_LOCK_PREFIX);
5609                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5610
5611                         if (ins->dreg != AMD64_RAX)
5612                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5613                         break;
5614                 }
5615                 case OP_ATOMIC_LOAD_I1: {
5616                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5617                         break;
5618                 }
5619                 case OP_ATOMIC_LOAD_U1: {
5620                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5621                         break;
5622                 }
5623                 case OP_ATOMIC_LOAD_I2: {
5624                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5625                         break;
5626                 }
5627                 case OP_ATOMIC_LOAD_U2: {
5628                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5629                         break;
5630                 }
5631                 case OP_ATOMIC_LOAD_I4: {
5632                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5633                         break;
5634                 }
5635                 case OP_ATOMIC_LOAD_U4:
5636                 case OP_ATOMIC_LOAD_I8:
5637                 case OP_ATOMIC_LOAD_U8: {
5638                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5639                         break;
5640                 }
5641                 case OP_ATOMIC_LOAD_R4: {
5642                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5643                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5644                         break;
5645                 }
5646                 case OP_ATOMIC_LOAD_R8: {
5647                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5648                         break;
5649                 }
5650                 case OP_ATOMIC_STORE_I1:
5651                 case OP_ATOMIC_STORE_U1:
5652                 case OP_ATOMIC_STORE_I2:
5653                 case OP_ATOMIC_STORE_U2:
5654                 case OP_ATOMIC_STORE_I4:
5655                 case OP_ATOMIC_STORE_U4:
5656                 case OP_ATOMIC_STORE_I8:
5657                 case OP_ATOMIC_STORE_U8: {
5658                         int size;
5659
5660                         switch (ins->opcode) {
5661                         case OP_ATOMIC_STORE_I1:
5662                         case OP_ATOMIC_STORE_U1:
5663                                 size = 1;
5664                                 break;
5665                         case OP_ATOMIC_STORE_I2:
5666                         case OP_ATOMIC_STORE_U2:
5667                                 size = 2;
5668                                 break;
5669                         case OP_ATOMIC_STORE_I4:
5670                         case OP_ATOMIC_STORE_U4:
5671                                 size = 4;
5672                                 break;
5673                         case OP_ATOMIC_STORE_I8:
5674                         case OP_ATOMIC_STORE_U8:
5675                                 size = 8;
5676                                 break;
5677                         }
5678
5679                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5680
5681                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5682                                 x86_mfence (code);
5683                         break;
5684                 }
5685                 case OP_ATOMIC_STORE_R4: {
5686                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5687                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5688
5689                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5690                                 x86_mfence (code);
5691                         break;
5692                 }
5693                 case OP_ATOMIC_STORE_R8: {
5694                         x86_nop (code);
5695                         x86_nop (code);
5696                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5697                         x86_nop (code);
5698                         x86_nop (code);
5699
5700                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5701                                 x86_mfence (code);
5702                         break;
5703                 }
5704                 case OP_CARD_TABLE_WBARRIER: {
5705                         int ptr = ins->sreg1;
5706                         int value = ins->sreg2;
5707                         guchar *br = 0;
5708                         int nursery_shift, card_table_shift;
5709                         gpointer card_table_mask;
5710                         size_t nursery_size;
5711
5712                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5713                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5714                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5715
5716                         /*If either point to the stack we can simply avoid the WB. This happens due to
5717                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5718                          */
5719                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5720                                 continue;
5721
5722                         /*
5723                          * We need one register we can clobber, we choose EDX and make sreg1
5724                          * fixed EAX to work around limitations in the local register allocator.
5725                          * sreg2 might get allocated to EDX, but that is not a problem since
5726                          * we use it before clobbering EDX.
5727                          */
5728                         g_assert (ins->sreg1 == AMD64_RAX);
5729
5730                         /*
5731                          * This is the code we produce:
5732                          *
5733                          *   edx = value
5734                          *   edx >>= nursery_shift
5735                          *   cmp edx, (nursery_start >> nursery_shift)
5736                          *   jne done
5737                          *   edx = ptr
5738                          *   edx >>= card_table_shift
5739                          *   edx += cardtable
5740                          *   [edx] = 1
5741                          * done:
5742                          */
5743
5744                         if (mono_gc_card_table_nursery_check ()) {
5745                                 if (value != AMD64_RDX)
5746                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5747                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5748                                 if (shifted_nursery_start >> 31) {
5749                                         /*
5750                                          * The value we need to compare against is 64 bits, so we need
5751                                          * another spare register.  We use RBX, which we save and
5752                                          * restore.
5753                                          */
5754                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5755                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5756                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5757                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5758                                 } else {
5759                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5760                                 }
5761                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5762                         }
5763                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5764                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5765                         if (card_table_mask)
5766                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5767
5768                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5769                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5770
5771                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5772
5773                         if (mono_gc_card_table_nursery_check ())
5774                                 x86_patch (br, code);
5775                         break;
5776                 }
5777 #ifdef MONO_ARCH_SIMD_INTRINSICS
5778                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5779                 case OP_ADDPS:
5780                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5781                         break;
5782                 case OP_DIVPS:
5783                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5784                         break;
5785                 case OP_MULPS:
5786                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5787                         break;
5788                 case OP_SUBPS:
5789                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5790                         break;
5791                 case OP_MAXPS:
5792                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5793                         break;
5794                 case OP_MINPS:
5795                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5796                         break;
5797                 case OP_COMPPS:
5798                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5799                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5800                         break;
5801                 case OP_ANDPS:
5802                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5803                         break;
5804                 case OP_ANDNPS:
5805                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5806                         break;
5807                 case OP_ORPS:
5808                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5809                         break;
5810                 case OP_XORPS:
5811                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5812                         break;
5813                 case OP_SQRTPS:
5814                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5815                         break;
5816                 case OP_RSQRTPS:
5817                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5818                         break;
5819                 case OP_RCPPS:
5820                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5821                         break;
5822                 case OP_ADDSUBPS:
5823                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5824                         break;
5825                 case OP_HADDPS:
5826                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5827                         break;
5828                 case OP_HSUBPS:
5829                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5830                         break;
5831                 case OP_DUPPS_HIGH:
5832                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5833                         break;
5834                 case OP_DUPPS_LOW:
5835                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5836                         break;
5837
5838                 case OP_PSHUFLEW_HIGH:
5839                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5840                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5841                         break;
5842                 case OP_PSHUFLEW_LOW:
5843                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5844                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5845                         break;
5846                 case OP_PSHUFLED:
5847                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5848                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5849                         break;
5850                 case OP_SHUFPS:
5851                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5852                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5853                         break;
5854                 case OP_SHUFPD:
5855                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5856                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5857                         break;
5858
5859                 case OP_ADDPD:
5860                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5861                         break;
5862                 case OP_DIVPD:
5863                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5864                         break;
5865                 case OP_MULPD:
5866                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5867                         break;
5868                 case OP_SUBPD:
5869                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5870                         break;
5871                 case OP_MAXPD:
5872                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5873                         break;
5874                 case OP_MINPD:
5875                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5876                         break;
5877                 case OP_COMPPD:
5878                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5879                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5880                         break;
5881                 case OP_ANDPD:
5882                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5883                         break;
5884                 case OP_ANDNPD:
5885                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887                 case OP_ORPD:
5888                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 case OP_XORPD:
5891                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5892                         break;
5893                 case OP_SQRTPD:
5894                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5895                         break;
5896                 case OP_ADDSUBPD:
5897                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5898                         break;
5899                 case OP_HADDPD:
5900                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5901                         break;
5902                 case OP_HSUBPD:
5903                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5904                         break;
5905                 case OP_DUPPD:
5906                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5907                         break;
5908
5909                 case OP_EXTRACT_MASK:
5910                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5911                         break;
5912
5913                 case OP_PAND:
5914                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5915                         break;
5916                 case OP_POR:
5917                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919                 case OP_PXOR:
5920                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5921                         break;
5922
5923                 case OP_PADDB:
5924                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_PADDW:
5927                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_PADDD:
5930                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 case OP_PADDQ:
5933                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5934                         break;
5935
5936                 case OP_PSUBB:
5937                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_PSUBW:
5940                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942                 case OP_PSUBD:
5943                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_PSUBQ:
5946                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948
5949                 case OP_PMAXB_UN:
5950                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_PMAXW_UN:
5953                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955                 case OP_PMAXD_UN:
5956                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958
5959                 case OP_PMAXB:
5960                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5961                         break;
5962                 case OP_PMAXW:
5963                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5964                         break;
5965                 case OP_PMAXD:
5966                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5967                         break;
5968
5969                 case OP_PAVGB_UN:
5970                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5971                         break;
5972                 case OP_PAVGW_UN:
5973                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5974                         break;
5975
5976                 case OP_PMINB_UN:
5977                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5978                         break;
5979                 case OP_PMINW_UN:
5980                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982                 case OP_PMIND_UN:
5983                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5984                         break;
5985
5986                 case OP_PMINB:
5987                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5988                         break;
5989                 case OP_PMINW:
5990                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_PMIND:
5993                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995
5996                 case OP_PCMPEQB:
5997                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_PCMPEQW:
6000                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_PCMPEQD:
6003                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005                 case OP_PCMPEQQ:
6006                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008
6009                 case OP_PCMPGTB:
6010                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_PCMPGTW:
6013                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_PCMPGTD:
6016                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_PCMPGTQ:
6019                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021
6022                 case OP_PSUM_ABS_DIFF:
6023                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025
6026                 case OP_UNPACK_LOWB:
6027                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6028                         break;
6029                 case OP_UNPACK_LOWW:
6030                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_UNPACK_LOWD:
6033                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6034                         break;
6035                 case OP_UNPACK_LOWQ:
6036                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6037                         break;
6038                 case OP_UNPACK_LOWPS:
6039                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041                 case OP_UNPACK_LOWPD:
6042                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044
6045                 case OP_UNPACK_HIGHB:
6046                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6047                         break;
6048                 case OP_UNPACK_HIGHW:
6049                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_UNPACK_HIGHD:
6052                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_UNPACK_HIGHQ:
6055                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_UNPACK_HIGHPS:
6058                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_UNPACK_HIGHPD:
6061                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063
6064                 case OP_PACKW:
6065                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_PACKD:
6068                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_PACKW_UN:
6071                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PACKD_UN:
6074                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076
6077                 case OP_PADDB_SAT_UN:
6078                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_PSUBB_SAT_UN:
6081                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083                 case OP_PADDW_SAT_UN:
6084                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086                 case OP_PSUBW_SAT_UN:
6087                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089
6090                 case OP_PADDB_SAT:
6091                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_PSUBB_SAT:
6094                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096                 case OP_PADDW_SAT:
6097                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PSUBW_SAT:
6100                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102
6103                 case OP_PMULW:
6104                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_PMULD:
6107                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_PMULQ:
6110                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_PMULW_HIGH_UN:
6113                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_PMULW_HIGH:
6116                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118
6119                 case OP_PSHRW:
6120                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6121                         break;
6122                 case OP_PSHRW_REG:
6123                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6124                         break;
6125
6126                 case OP_PSARW:
6127                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6128                         break;
6129                 case OP_PSARW_REG:
6130                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6131                         break;
6132
6133                 case OP_PSHLW:
6134                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6135                         break;
6136                 case OP_PSHLW_REG:
6137                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6138                         break;
6139
6140                 case OP_PSHRD:
6141                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6142                         break;
6143                 case OP_PSHRD_REG:
6144                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6145                         break;
6146
6147                 case OP_PSARD:
6148                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6149                         break;
6150                 case OP_PSARD_REG:
6151                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6152                         break;
6153
6154                 case OP_PSHLD:
6155                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6156                         break;
6157                 case OP_PSHLD_REG:
6158                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6159                         break;
6160
6161                 case OP_PSHRQ:
6162                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6163                         break;
6164                 case OP_PSHRQ_REG:
6165                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6166                         break;
6167
6168                 /*TODO: This is appart of the sse spec but not added
6169                 case OP_PSARQ:
6170                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6171                         break;
6172                 case OP_PSARQ_REG:
6173                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6174                         break;
6175                 */
6176
6177                 case OP_PSHLQ:
6178                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6179                         break;
6180                 case OP_PSHLQ_REG:
6181                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6182                         break;
6183                 case OP_CVTDQ2PD:
6184                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6185                         break;
6186                 case OP_CVTDQ2PS:
6187                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6188                         break;
6189                 case OP_CVTPD2DQ:
6190                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6191                         break;
6192                 case OP_CVTPD2PS:
6193                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6194                         break;
6195                 case OP_CVTPS2DQ:
6196                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6197                         break;
6198                 case OP_CVTPS2PD:
6199                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6200                         break;
6201                 case OP_CVTTPD2DQ:
6202                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6203                         break;
6204                 case OP_CVTTPS2DQ:
6205                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6206                         break;
6207
6208                 case OP_ICONV_TO_X:
6209                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6210                         break;
6211                 case OP_EXTRACT_I4:
6212                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6213                         break;
6214                 case OP_EXTRACT_I8:
6215                         if (ins->inst_c0) {
6216                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6217                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6218                         } else {
6219                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6220                         }
6221                         break;
6222                 case OP_EXTRACT_I1:
6223                 case OP_EXTRACT_U1:
6224                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6225                         if (ins->inst_c0)
6226                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6227                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6228                         break;
6229                 case OP_EXTRACT_I2:
6230                 case OP_EXTRACT_U2:
6231                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6232                         if (ins->inst_c0)
6233                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6234                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6235                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6236                         break;
6237                 case OP_EXTRACT_R8:
6238                         if (ins->inst_c0)
6239                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6240                         else
6241                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6242                         break;
6243                 case OP_INSERT_I2:
6244                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6245                         break;
6246                 case OP_EXTRACTX_U2:
6247                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6248                         break;
6249                 case OP_INSERTX_U1_SLOW:
6250                         /*sreg1 is the extracted ireg (scratch)
6251                         /sreg2 is the to be inserted ireg (scratch)
6252                         /dreg is the xreg to receive the value*/
6253
6254                         /*clear the bits from the extracted word*/
6255                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6256                         /*shift the value to insert if needed*/
6257                         if (ins->inst_c0 & 1)
6258                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6259                         /*join them together*/
6260                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6261                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6262                         break;
6263                 case OP_INSERTX_I4_SLOW:
6264                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6265                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6266                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6267                         break;
6268                 case OP_INSERTX_I8_SLOW:
6269                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6270                         if (ins->inst_c0)
6271                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6272                         else
6273                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6274                         break;
6275
6276                 case OP_INSERTX_R4_SLOW:
6277                         switch (ins->inst_c0) {
6278                         case 0:
6279                                 if (cfg->r4fp)
6280                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6281                                 else
6282                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6283                                 break;
6284                         case 1:
6285                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6286                                 if (cfg->r4fp)
6287                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6288                                 else
6289                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6290                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6291                                 break;
6292                         case 2:
6293                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6294                                 if (cfg->r4fp)
6295                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6296                                 else
6297                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6298                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6299                                 break;
6300                         case 3:
6301                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6302                                 if (cfg->r4fp)
6303                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6304                                 else
6305                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6306                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6307                                 break;
6308                         }
6309                         break;
6310                 case OP_INSERTX_R8_SLOW:
6311                         if (ins->inst_c0)
6312                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6313                         else
6314                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6315                         break;
6316                 case OP_STOREX_MEMBASE_REG:
6317                 case OP_STOREX_MEMBASE:
6318                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6319                         break;
6320                 case OP_LOADX_MEMBASE:
6321                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6322                         break;
6323                 case OP_LOADX_ALIGNED_MEMBASE:
6324                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6325                         break;
6326                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6327                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6328                         break;
6329                 case OP_STOREX_NTA_MEMBASE_REG:
6330                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6331                         break;
6332                 case OP_PREFETCH_MEMBASE:
6333                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6334                         break;
6335
6336                 case OP_XMOVE:
6337                         /*FIXME the peephole pass should have killed this*/
6338                         if (ins->dreg != ins->sreg1)
6339                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6340                         break;
6341                 case OP_XZERO:
6342                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6343                         break;
6344                 case OP_XONES:
6345                         amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6346                         break;
6347                 case OP_ICONV_TO_R4_RAW:
6348                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6349                         if (!cfg->r4fp)
6350                           amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6351                         break;
6352
6353                 case OP_FCONV_TO_R8_X:
6354                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6355                         break;
6356
6357                 case OP_XCONV_R8_TO_I4:
6358                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6359                         switch (ins->backend.source_opcode) {
6360                         case OP_FCONV_TO_I1:
6361                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6362                                 break;
6363                         case OP_FCONV_TO_U1:
6364                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6365                                 break;
6366                         case OP_FCONV_TO_I2:
6367                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6368                                 break;
6369                         case OP_FCONV_TO_U2:
6370                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6371                                 break;
6372                         }
6373                         break;
6374
6375                 case OP_EXPAND_I2:
6376                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6377                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6378                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6379                         break;
6380                 case OP_EXPAND_I4:
6381                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6382                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6383                         break;
6384                 case OP_EXPAND_I8:
6385                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6386                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6387                         break;
6388                 case OP_EXPAND_R4:
6389                         if (cfg->r4fp) {
6390                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6391                         } else {
6392                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6393                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6394                         }
6395                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6396                         break;
6397                 case OP_EXPAND_R8:
6398                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6399                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6400                         break;
6401 #endif
6402                 case OP_LIVERANGE_START: {
6403                         if (cfg->verbose_level > 1)
6404                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6405                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6406                         break;
6407                 }
6408                 case OP_LIVERANGE_END: {
6409                         if (cfg->verbose_level > 1)
6410                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6411                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6412                         break;
6413                 }
6414                 case OP_GC_SAFE_POINT: {
6415                         guint8 *br [1];
6416
6417                         g_assert (mono_threads_is_coop_enabled ());
6418
6419                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6420                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6421                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6422                         amd64_patch (br[0], code);
6423                         break;
6424                 }
6425
6426                 case OP_GC_LIVENESS_DEF:
6427                 case OP_GC_LIVENESS_USE:
6428                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6429                         ins->backend.pc_offset = code - cfg->native_code;
6430                         break;
6431                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6432                         ins->backend.pc_offset = code - cfg->native_code;
6433                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6434                         break;
6435                 case OP_GET_LAST_ERROR:
6436                         emit_get_last_error(code, ins->dreg);
6437                         break;
6438                 default:
6439                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6440                         g_assert_not_reached ();
6441                 }
6442
6443                 if ((code - cfg->native_code - offset) > max_len) {
6444                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6445                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6446                         g_assert_not_reached ();
6447                 }
6448         }
6449
6450         cfg->code_len = code - cfg->native_code;
6451 }
6452
6453 #endif /* DISABLE_JIT */
6454
6455 void
6456 mono_arch_register_lowlevel_calls (void)
6457 {
6458         /* The signature doesn't matter */
6459         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6460
6461 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6462 #if _MSC_VER
6463         extern void __chkstk (void);
6464         mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6465 #else
6466         extern void ___chkstk_ms (void);
6467         mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6468 #endif
6469 #endif
6470 }
6471
6472 void
6473 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6474 {
6475         unsigned char *ip = ji->ip.i + code;
6476
6477         /*
6478          * Debug code to help track down problems where the target of a near call is
6479          * is not valid.
6480          */
6481         if (amd64_is_near_call (ip)) {
6482                 gint64 disp = (guint8*)target - (guint8*)ip;
6483
6484                 if (!amd64_is_imm32 (disp)) {
6485                         printf ("TYPE: %d\n", ji->type);
6486                         switch (ji->type) {
6487                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6488                                 printf ("V: %s\n", ji->data.name);
6489                                 break;
6490                         case MONO_PATCH_INFO_METHOD_JUMP:
6491                         case MONO_PATCH_INFO_METHOD:
6492                                 printf ("V: %s\n", ji->data.method->name);
6493                                 break;
6494                         default:
6495                                 break;
6496                         }
6497                 }
6498         }
6499
6500         amd64_patch (ip, (gpointer)target);
6501 }
6502
6503 #ifndef DISABLE_JIT
6504
6505 static int
6506 get_max_epilog_size (MonoCompile *cfg)
6507 {
6508         int max_epilog_size = 16;
6509
6510         if (cfg->method->save_lmf)
6511                 max_epilog_size += 256;
6512
6513         if (mono_jit_trace_calls != NULL)
6514                 max_epilog_size += 50;
6515
6516         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6517                 max_epilog_size += 50;
6518
6519         max_epilog_size += (AMD64_NREG * 2);
6520
6521         return max_epilog_size;
6522 }
6523
6524 /*
6525  * This macro is used for testing whenever the unwinder works correctly at every point
6526  * where an async exception can happen.
6527  */
6528 /* This will generate a SIGSEGV at the given point in the code */
6529 #define async_exc_point(code) do { \
6530     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6531          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6532              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6533          cfg->arch.async_point_count ++; \
6534     } \
6535 } while (0)
6536
6537 #ifdef TARGET_WIN32
6538 static guint8 *
6539 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6540 {
6541         int cfa_offset = *cfa_offset_input;
6542
6543         /* Allocate windows stack frame using stack probing method */
6544         if (alloc_size) {
6545
6546                 if (alloc_size >= 0x1000) {
6547                         amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6548                         code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6549                 }
6550
6551                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6552                 if (cfg->arch.omit_fp) {
6553                         cfa_offset += alloc_size;
6554                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6555                         async_exc_point (code);
6556                 }
6557
6558                 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6559                 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6560                 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6561                 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6562                 // that will retrieve the expected results.
6563                 if (cfg->arch.omit_fp)
6564                         mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6565         }
6566
6567         *cfa_offset_input = cfa_offset;
6568         return code;
6569 }
6570 #endif /* TARGET_WIN32 */
6571
6572 guint8 *
6573 mono_arch_emit_prolog (MonoCompile *cfg)
6574 {
6575         MonoMethod *method = cfg->method;
6576         MonoBasicBlock *bb;
6577         MonoMethodSignature *sig;
6578         MonoInst *ins;
6579         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6580         guint8 *code;
6581         CallInfo *cinfo;
6582         MonoInst *lmf_var = cfg->lmf_var;
6583         gboolean args_clobbered = FALSE;
6584         gboolean trace = FALSE;
6585
6586         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6587
6588         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6589
6590         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6591                 trace = TRUE;
6592
6593         /* Amount of stack space allocated by register saving code */
6594         pos = 0;
6595
6596         /* Offset between RSP and the CFA */
6597         cfa_offset = 0;
6598
6599         /*
6600          * The prolog consists of the following parts:
6601          * FP present:
6602          * - push rbp
6603          * - mov rbp, rsp
6604          * - save callee saved regs using moves
6605          * - allocate frame
6606          * - save rgctx if needed
6607          * - save lmf if needed
6608          * FP not present:
6609          * - allocate frame
6610          * - save rgctx if needed
6611          * - save lmf if needed
6612          * - save callee saved regs using moves
6613          */
6614
6615         // CFA = sp + 8
6616         cfa_offset = 8;
6617         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6618         // IP saved at CFA - 8
6619         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6620         async_exc_point (code);
6621         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6622
6623         if (!cfg->arch.omit_fp) {
6624                 amd64_push_reg (code, AMD64_RBP);
6625                 cfa_offset += 8;
6626                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6627                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6628                 async_exc_point (code);
6629                 /* These are handled automatically by the stack marking code */
6630                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6631
6632                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6633                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6634                 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6635                 async_exc_point (code);
6636         }
6637
6638         /* The param area is always at offset 0 from sp */
6639         /* This needs to be allocated here, since it has to come after the spill area */
6640         if (cfg->param_area) {
6641                 if (cfg->arch.omit_fp)
6642                         // FIXME:
6643                         g_assert_not_reached ();
6644                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6645         }
6646
6647         if (cfg->arch.omit_fp) {
6648                 /*
6649                  * On enter, the stack is misaligned by the pushing of the return
6650                  * address. It is either made aligned by the pushing of %rbp, or by
6651                  * this.
6652                  */
6653                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6654                 if ((alloc_size % 16) == 0) {
6655                         alloc_size += 8;
6656                         /* Mark the padding slot as NOREF */
6657                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6658                 }
6659         } else {
6660                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6661                 if (cfg->stack_offset != alloc_size) {
6662                         /* Mark the padding slot as NOREF */
6663                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6664                 }
6665                 cfg->arch.sp_fp_offset = alloc_size;
6666                 alloc_size -= pos;
6667         }
6668
6669         cfg->arch.stack_alloc_size = alloc_size;
6670
6671         /* Allocate stack frame */
6672 #ifdef TARGET_WIN32
6673         code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6674 #else
6675         if (alloc_size) {
6676                 /* See mono_emit_stack_alloc */
6677 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6678                 guint32 remaining_size = alloc_size;
6679                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6680                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6681                 guint32 offset = code - cfg->native_code;
6682                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6683                         while (required_code_size >= (cfg->code_size - offset))
6684                                 cfg->code_size *= 2;
6685                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6686                         code = cfg->native_code + offset;
6687                         cfg->stat_code_reallocs++;
6688                 }
6689
6690                 while (remaining_size >= 0x1000) {
6691                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6692                         if (cfg->arch.omit_fp) {
6693                                 cfa_offset += 0x1000;
6694                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6695                         }
6696                         async_exc_point (code);
6697
6698                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6699                         remaining_size -= 0x1000;
6700                 }
6701                 if (remaining_size) {
6702                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6703                         if (cfg->arch.omit_fp) {
6704                                 cfa_offset += remaining_size;
6705                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6706                                 async_exc_point (code);
6707                         }
6708                 }
6709 #else
6710                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6711                 if (cfg->arch.omit_fp) {
6712                         cfa_offset += alloc_size;
6713                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6714                         async_exc_point (code);
6715                 }
6716 #endif
6717         }
6718 #endif
6719
6720         /* Stack alignment check */
6721 #if 0
6722         {
6723                 guint8 *buf;
6724
6725                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6726                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6727                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6728                 buf = code;
6729                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6730                 amd64_breakpoint (code);
6731                 amd64_patch (buf, code);
6732         }
6733 #endif
6734
6735         if (mini_get_debug_options ()->init_stacks) {
6736                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6737
6738                 /* Save registers to the red zone */
6739                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6740                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6741
6742                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6743                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6744                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6745
6746                 amd64_cld (code);
6747                 amd64_prefix (code, X86_REP_PREFIX);
6748                 amd64_stosl (code);
6749
6750                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6751                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6752         }
6753
6754         /* Save LMF */
6755         if (method->save_lmf)
6756                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6757
6758         /* Save callee saved registers */
6759         if (cfg->arch.omit_fp) {
6760                 save_area_offset = cfg->arch.reg_save_area_offset;
6761                 /* Save caller saved registers after sp is adjusted */
6762                 /* The registers are saved at the bottom of the frame */
6763                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6764         } else {
6765                 /* The registers are saved just below the saved rbp */
6766                 save_area_offset = cfg->arch.reg_save_area_offset;
6767         }
6768
6769         for (i = 0; i < AMD64_NREG; ++i) {
6770                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6771                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6772
6773                         if (cfg->arch.omit_fp) {
6774                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6775                                 /* These are handled automatically by the stack marking code */
6776                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6777                         } else {
6778                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6779                                 // FIXME: GC
6780                         }
6781
6782                         save_area_offset += 8;
6783                         async_exc_point (code);
6784                 }
6785         }
6786
6787         /* store runtime generic context */
6788         if (cfg->rgctx_var) {
6789                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6790                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6791
6792                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6793
6794                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6795                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6796         }
6797
6798         /* compute max_length in order to use short forward jumps */
6799         max_epilog_size = get_max_epilog_size (cfg);
6800         if (cfg->opt & MONO_OPT_BRANCH) {
6801                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6802                         MonoInst *ins;
6803                         int max_length = 0;
6804
6805                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6806                                 max_length += 6;
6807                         /* max alignment for loops */
6808                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6809                                 max_length += LOOP_ALIGNMENT;
6810
6811                         MONO_BB_FOR_EACH_INS (bb, ins) {
6812                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6813                         }
6814
6815                         /* Take prolog and epilog instrumentation into account */
6816                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6817                                 max_length += max_epilog_size;
6818
6819                         bb->max_length = max_length;
6820                 }
6821         }
6822
6823         sig = mono_method_signature (method);
6824         pos = 0;
6825
6826         cinfo = (CallInfo *)cfg->arch.cinfo;
6827
6828         if (sig->ret->type != MONO_TYPE_VOID) {
6829                 /* Save volatile arguments to the stack */
6830                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6831                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6832         }
6833
6834         /* Keep this in sync with emit_load_volatile_arguments */
6835         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6836                 ArgInfo *ainfo = cinfo->args + i;
6837
6838                 ins = cfg->args [i];
6839
6840                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6841                         /* Unused arguments */
6842                         continue;
6843
6844                 /* Save volatile arguments to the stack */
6845                 if (ins->opcode != OP_REGVAR) {
6846                         switch (ainfo->storage) {
6847                         case ArgInIReg: {
6848                                 guint32 size = 8;
6849
6850                                 /* FIXME: I1 etc */
6851                                 /*
6852                                 if (stack_offset & 0x1)
6853                                         size = 1;
6854                                 else if (stack_offset & 0x2)
6855                                         size = 2;
6856                                 else if (stack_offset & 0x4)
6857                                         size = 4;
6858                                 else
6859                                         size = 8;
6860                                 */
6861                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6862
6863                                 /*
6864                                  * Save the original location of 'this',
6865                                  * get_generic_info_from_stack_frame () needs this to properly look up
6866                                  * the argument value during the handling of async exceptions.
6867                                  */
6868                                 if (ins == cfg->args [0]) {
6869                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6870                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6871                                 }
6872                                 break;
6873                         }
6874                         case ArgInFloatSSEReg:
6875                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6876                                 break;
6877                         case ArgInDoubleSSEReg:
6878                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6879                                 break;
6880                         case ArgValuetypeInReg:
6881                                 for (quad = 0; quad < 2; quad ++) {
6882                                         switch (ainfo->pair_storage [quad]) {
6883                                         case ArgInIReg:
6884                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6885                                                 break;
6886                                         case ArgInFloatSSEReg:
6887                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6888                                                 break;
6889                                         case ArgInDoubleSSEReg:
6890                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6891                                                 break;
6892                                         case ArgNone:
6893                                                 break;
6894                                         default:
6895                                                 g_assert_not_reached ();
6896                                         }
6897                                 }
6898                                 break;
6899                         case ArgValuetypeAddrInIReg:
6900                                 if (ainfo->pair_storage [0] == ArgInIReg)
6901                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6902                                 break;
6903                         case ArgValuetypeAddrOnStack:
6904                                 break;
6905                         case ArgGSharedVtInReg:
6906                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6907                                 break;
6908                         default:
6909                                 break;
6910                         }
6911                 } else {
6912                         /* Argument allocated to (non-volatile) register */
6913                         switch (ainfo->storage) {
6914                         case ArgInIReg:
6915                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6916                                 break;
6917                         case ArgOnStack:
6918                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6919                                 break;
6920                         default:
6921                                 g_assert_not_reached ();
6922                         }
6923
6924                         if (ins == cfg->args [0]) {
6925                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6926                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6927                         }
6928                 }
6929         }
6930
6931         if (cfg->method->save_lmf)
6932                 args_clobbered = TRUE;
6933
6934         if (trace) {
6935                 args_clobbered = TRUE;
6936                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6937         }
6938
6939         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6940                 args_clobbered = TRUE;
6941
6942         /*
6943          * Optimize the common case of the first bblock making a call with the same
6944          * arguments as the method. This works because the arguments are still in their
6945          * original argument registers.
6946          * FIXME: Generalize this
6947          */
6948         if (!args_clobbered) {
6949                 MonoBasicBlock *first_bb = cfg->bb_entry;
6950                 MonoInst *next;
6951                 int filter = FILTER_IL_SEQ_POINT;
6952
6953                 next = mono_bb_first_inst (first_bb, filter);
6954                 if (!next && first_bb->next_bb) {
6955                         first_bb = first_bb->next_bb;
6956                         next = mono_bb_first_inst (first_bb, filter);
6957                 }
6958
6959                 if (first_bb->in_count > 1)
6960                         next = NULL;
6961
6962                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6963                         ArgInfo *ainfo = cinfo->args + i;
6964                         gboolean match = FALSE;
6965
6966                         ins = cfg->args [i];
6967                         if (ins->opcode != OP_REGVAR) {
6968                                 switch (ainfo->storage) {
6969                                 case ArgInIReg: {
6970                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6971                                                 if (next->dreg == ainfo->reg) {
6972                                                         NULLIFY_INS (next);
6973                                                         match = TRUE;
6974                                                 } else {
6975                                                         next->opcode = OP_MOVE;
6976                                                         next->sreg1 = ainfo->reg;
6977                                                         /* Only continue if the instruction doesn't change argument regs */
6978                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6979                                                                 match = TRUE;
6980                                                 }
6981                                         }
6982                                         break;
6983                                 }
6984                                 default:
6985                                         break;
6986                                 }
6987                         } else {
6988                                 /* Argument allocated to (non-volatile) register */
6989                                 switch (ainfo->storage) {
6990                                 case ArgInIReg:
6991                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6992                                                 NULLIFY_INS (next);
6993                                                 match = TRUE;
6994                                         }
6995                                         break;
6996                                 default:
6997                                         break;
6998                                 }
6999                         }
7000
7001                         if (match) {
7002                                 next = mono_inst_next (next, filter);
7003                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7004                                 if (!next)
7005                                         break;
7006                         }
7007                 }
7008         }
7009
7010         if (cfg->gen_sdb_seq_points) {
7011                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7012
7013                 /* Initialize seq_point_info_var */
7014                 if (cfg->compile_aot) {
7015                         /* Initialize the variable from a GOT slot */
7016                         /* Same as OP_AOTCONST */
7017                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7018                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7019                         g_assert (info_var->opcode == OP_REGOFFSET);
7020                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7021                 }
7022
7023                 if (cfg->compile_aot) {
7024                         /* Initialize ss_tramp_var */
7025                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7026                         g_assert (ins->opcode == OP_REGOFFSET);
7027
7028                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7029                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7030                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7031                 } else {
7032                         /* Initialize ss_tramp_var */
7033                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7034                         g_assert (ins->opcode == OP_REGOFFSET);
7035
7036                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7037                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7038
7039                         /* Initialize bp_tramp_var */
7040                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7041                         g_assert (ins->opcode == OP_REGOFFSET);
7042
7043                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7044                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7045                 }
7046         }
7047
7048         cfg->code_len = code - cfg->native_code;
7049
7050         g_assert (cfg->code_len < cfg->code_size);
7051
7052         return code;
7053 }
7054
7055 void
7056 mono_arch_emit_epilog (MonoCompile *cfg)
7057 {
7058         MonoMethod *method = cfg->method;
7059         int quad, i;
7060         guint8 *code;
7061         int max_epilog_size;
7062         CallInfo *cinfo;
7063         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7064         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7065
7066         max_epilog_size = get_max_epilog_size (cfg);
7067
7068         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7069                 cfg->code_size *= 2;
7070                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7071                 cfg->stat_code_reallocs++;
7072         }
7073         code = cfg->native_code + cfg->code_len;
7074
7075         cfg->has_unwind_info_for_epilog = TRUE;
7076
7077         /* Mark the start of the epilog */
7078         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7079
7080         /* Save the uwind state which is needed by the out-of-line code */
7081         mono_emit_unwind_op_remember_state (cfg, code);
7082
7083         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7084                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7085
7086         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7087
7088         if (method->save_lmf) {
7089                 /* check if we need to restore protection of the stack after a stack overflow */
7090                 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7091                         guint8 *patch;
7092                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7093                         /* we load the value in a separate instruction: this mechanism may be
7094                          * used later as a safer way to do thread interruption
7095                          */
7096                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7097                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7098                         patch = code;
7099                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7100                         /* note that the call trampoline will preserve eax/edx */
7101                         x86_call_reg (code, X86_ECX);
7102                         x86_patch (patch, code);
7103                 } else {
7104                         /* FIXME: maybe save the jit tls in the prolog */
7105                 }
7106                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7107                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7108                 }
7109         }
7110
7111         /* Restore callee saved regs */
7112         for (i = 0; i < AMD64_NREG; ++i) {
7113                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7114                         /* Restore only used_int_regs, not arch.saved_iregs */
7115 #if defined(MONO_SUPPORT_TASKLETS)
7116                         int restore_reg=1;
7117 #else
7118                         int restore_reg=(cfg->used_int_regs & (1 << i));
7119 #endif
7120                         if (restore_reg) {
7121                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7122                                 mono_emit_unwind_op_same_value (cfg, code, i);
7123                                 async_exc_point (code);
7124                         }
7125                         save_area_offset += 8;
7126                 }
7127         }
7128
7129         /* Load returned vtypes into registers if needed */
7130         cinfo = (CallInfo *)cfg->arch.cinfo;
7131         if (cinfo->ret.storage == ArgValuetypeInReg) {
7132                 ArgInfo *ainfo = &cinfo->ret;
7133                 MonoInst *inst = cfg->ret;
7134
7135                 for (quad = 0; quad < 2; quad ++) {
7136                         switch (ainfo->pair_storage [quad]) {
7137                         case ArgInIReg:
7138                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7139                                 break;
7140                         case ArgInFloatSSEReg:
7141                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7142                                 break;
7143                         case ArgInDoubleSSEReg:
7144                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7145                                 break;
7146                         case ArgNone:
7147                                 break;
7148                         default:
7149                                 g_assert_not_reached ();
7150                         }
7151                 }
7152         }
7153
7154         if (cfg->arch.omit_fp) {
7155                 if (cfg->arch.stack_alloc_size) {
7156                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7157                 }
7158         } else {
7159 #ifdef TARGET_WIN32
7160                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7161                 amd64_pop_reg (code, AMD64_RBP);
7162                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7163 #else
7164                 amd64_leave (code);
7165                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7166 #endif
7167         }
7168         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7169         async_exc_point (code);
7170         amd64_ret (code);
7171
7172         /* Restore the unwind state to be the same as before the epilog */
7173         mono_emit_unwind_op_restore_state (cfg, code);
7174
7175         cfg->code_len = code - cfg->native_code;
7176
7177         g_assert (cfg->code_len < cfg->code_size);
7178 }
7179
7180 void
7181 mono_arch_emit_exceptions (MonoCompile *cfg)
7182 {
7183         MonoJumpInfo *patch_info;
7184         int nthrows, i;
7185         guint8 *code;
7186         MonoClass *exc_classes [16];
7187         guint8 *exc_throw_start [16], *exc_throw_end [16];
7188         guint32 code_size = 0;
7189
7190         /* Compute needed space */
7191         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7192                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7193                         code_size += 40;
7194                 if (patch_info->type == MONO_PATCH_INFO_R8)
7195                         code_size += 8 + 15; /* sizeof (double) + alignment */
7196                 if (patch_info->type == MONO_PATCH_INFO_R4)
7197                         code_size += 4 + 15; /* sizeof (float) + alignment */
7198                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7199                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7200         }
7201
7202         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7203                 cfg->code_size *= 2;
7204                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7205                 cfg->stat_code_reallocs++;
7206         }
7207
7208         code = cfg->native_code + cfg->code_len;
7209
7210         /* add code to raise exceptions */
7211         nthrows = 0;
7212         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7213                 switch (patch_info->type) {
7214                 case MONO_PATCH_INFO_EXC: {
7215                         MonoClass *exc_class;
7216                         guint8 *buf, *buf2;
7217                         guint32 throw_ip;
7218
7219                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7220
7221                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7222                         throw_ip = patch_info->ip.i;
7223
7224                         //x86_breakpoint (code);
7225                         /* Find a throw sequence for the same exception class */
7226                         for (i = 0; i < nthrows; ++i)
7227                                 if (exc_classes [i] == exc_class)
7228                                         break;
7229                         if (i < nthrows) {
7230                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7231                                 x86_jump_code (code, exc_throw_start [i]);
7232                                 patch_info->type = MONO_PATCH_INFO_NONE;
7233                         }
7234                         else {
7235                                 buf = code;
7236                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7237                                 buf2 = code;
7238
7239                                 if (nthrows < 16) {
7240                                         exc_classes [nthrows] = exc_class;
7241                                         exc_throw_start [nthrows] = code;
7242                                 }
7243                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7244
7245                                 patch_info->type = MONO_PATCH_INFO_NONE;
7246
7247                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7248
7249                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7250                                 while (buf < buf2)
7251                                         x86_nop (buf);
7252
7253                                 if (nthrows < 16) {
7254                                         exc_throw_end [nthrows] = code;
7255                                         nthrows ++;
7256                                 }
7257                         }
7258                         break;
7259                 }
7260                 default:
7261                         /* do nothing */
7262                         break;
7263                 }
7264                 g_assert(code < cfg->native_code + cfg->code_size);
7265         }
7266
7267         /* Handle relocations with RIP relative addressing */
7268         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7269                 gboolean remove = FALSE;
7270                 guint8 *orig_code = code;
7271
7272                 switch (patch_info->type) {
7273                 case MONO_PATCH_INFO_R8:
7274                 case MONO_PATCH_INFO_R4: {
7275                         guint8 *pos, *patch_pos;
7276                         guint32 target_pos;
7277
7278                         /* The SSE opcodes require a 16 byte alignment */
7279                         code = (guint8*)ALIGN_TO (code, 16);
7280
7281                         pos = cfg->native_code + patch_info->ip.i;
7282                         if (IS_REX (pos [1])) {
7283                                 patch_pos = pos + 5;
7284                                 target_pos = code - pos - 9;
7285                         }
7286                         else {
7287                                 patch_pos = pos + 4;
7288                                 target_pos = code - pos - 8;
7289                         }
7290
7291                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7292                                 *(double*)code = *(double*)patch_info->data.target;
7293                                 code += sizeof (double);
7294                         } else {
7295                                 *(float*)code = *(float*)patch_info->data.target;
7296                                 code += sizeof (float);
7297                         }
7298
7299                         *(guint32*)(patch_pos) = target_pos;
7300
7301                         remove = TRUE;
7302                         break;
7303                 }
7304                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7305                         guint8 *pos;
7306
7307                         if (cfg->compile_aot)
7308                                 continue;
7309
7310                         /*loading is faster against aligned addresses.*/
7311                         code = (guint8*)ALIGN_TO (code, 8);
7312                         memset (orig_code, 0, code - orig_code);
7313
7314                         pos = cfg->native_code + patch_info->ip.i;
7315
7316                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7317                         if (IS_REX (pos [1]))
7318                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7319                         else
7320                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7321
7322                         *(gpointer*)code = (gpointer)patch_info->data.target;
7323                         code += sizeof (gpointer);
7324
7325                         remove = TRUE;
7326                         break;
7327                 }
7328                 default:
7329                         break;
7330                 }
7331
7332                 if (remove) {
7333                         if (patch_info == cfg->patch_info)
7334                                 cfg->patch_info = patch_info->next;
7335                         else {
7336                                 MonoJumpInfo *tmp;
7337
7338                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7339                                         ;
7340                                 tmp->next = patch_info->next;
7341                         }
7342                 }
7343                 g_assert (code < cfg->native_code + cfg->code_size);
7344         }
7345
7346         cfg->code_len = code - cfg->native_code;
7347
7348         g_assert (cfg->code_len < cfg->code_size);
7349
7350 }
7351
7352 #endif /* DISABLE_JIT */
7353
7354 void*
7355 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7356 {
7357         guchar *code = (guchar *)p;
7358         MonoMethodSignature *sig;
7359         MonoInst *inst;
7360         int i, n, stack_area = 0;
7361
7362         /* Keep this in sync with mono_arch_get_argument_info */
7363
7364         if (enable_arguments) {
7365                 /* Allocate a new area on the stack and save arguments there */
7366                 sig = mono_method_signature (cfg->method);
7367
7368                 n = sig->param_count + sig->hasthis;
7369
7370                 stack_area = ALIGN_TO (n * 8, 16);
7371
7372                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7373
7374                 for (i = 0; i < n; ++i) {
7375                         inst = cfg->args [i];
7376
7377                         if (inst->opcode == OP_REGVAR)
7378                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7379                         else {
7380                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7381                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7382                         }
7383                 }
7384         }
7385
7386         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7387         amd64_set_reg_template (code, AMD64_ARG_REG1);
7388         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7389         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7390
7391         if (enable_arguments)
7392                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7393
7394         return code;
7395 }
7396
7397 enum {
7398         SAVE_NONE,
7399         SAVE_STRUCT,
7400         SAVE_EAX,
7401         SAVE_EAX_EDX,
7402         SAVE_XMM
7403 };
7404
7405 void*
7406 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7407 {
7408         guchar *code = (guchar *)p;
7409         int save_mode = SAVE_NONE;
7410         MonoMethod *method = cfg->method;
7411         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7412         int i;
7413
7414         switch (ret_type->type) {
7415         case MONO_TYPE_VOID:
7416                 /* special case string .ctor icall */
7417                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7418                         save_mode = SAVE_EAX;
7419                 else
7420                         save_mode = SAVE_NONE;
7421                 break;
7422         case MONO_TYPE_I8:
7423         case MONO_TYPE_U8:
7424                 save_mode = SAVE_EAX;
7425                 break;
7426         case MONO_TYPE_R4:
7427         case MONO_TYPE_R8:
7428                 save_mode = SAVE_XMM;
7429                 break;
7430         case MONO_TYPE_GENERICINST:
7431                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7432                         save_mode = SAVE_EAX;
7433                         break;
7434                 }
7435                 /* Fall through */
7436         case MONO_TYPE_VALUETYPE:
7437                 save_mode = SAVE_STRUCT;
7438                 break;
7439         default:
7440                 save_mode = SAVE_EAX;
7441                 break;
7442         }
7443
7444         /* Save the result and copy it into the proper argument register */
7445         switch (save_mode) {
7446         case SAVE_EAX:
7447                 amd64_push_reg (code, AMD64_RAX);
7448                 /* Align stack */
7449                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7450                 if (enable_arguments)
7451                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7452                 break;
7453         case SAVE_STRUCT:
7454                 /* FIXME: */
7455                 if (enable_arguments)
7456                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7457                 break;
7458         case SAVE_XMM:
7459                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7460                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7461                 /* Align stack */
7462                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7463                 /*
7464                  * The result is already in the proper argument register so no copying
7465                  * needed.
7466                  */
7467                 break;
7468         case SAVE_NONE:
7469                 break;
7470         default:
7471                 g_assert_not_reached ();
7472         }
7473
7474         /* Set %al since this is a varargs call */
7475         if (save_mode == SAVE_XMM)
7476                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7477         else
7478                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7479
7480         if (preserve_argument_registers) {
7481                 for (i = 0; i < PARAM_REGS; ++i)
7482                         amd64_push_reg (code, param_regs [i]);
7483         }
7484
7485         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7486         amd64_set_reg_template (code, AMD64_ARG_REG1);
7487         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7488
7489         if (preserve_argument_registers) {
7490                 for (i = PARAM_REGS - 1; i >= 0; --i)
7491                         amd64_pop_reg (code, param_regs [i]);
7492         }
7493
7494         /* Restore result */
7495         switch (save_mode) {
7496         case SAVE_EAX:
7497                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7498                 amd64_pop_reg (code, AMD64_RAX);
7499                 break;
7500         case SAVE_STRUCT:
7501                 /* FIXME: */
7502                 break;
7503         case SAVE_XMM:
7504                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7505                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7506                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7507                 break;
7508         case SAVE_NONE:
7509                 break;
7510         default:
7511                 g_assert_not_reached ();
7512         }
7513
7514         return code;
7515 }
7516
7517 void
7518 mono_arch_flush_icache (guint8 *code, gint size)
7519 {
7520         /* Not needed */
7521 }
7522
7523 void
7524 mono_arch_flush_register_windows (void)
7525 {
7526 }
7527
7528 gboolean
7529 mono_arch_is_inst_imm (gint64 imm)
7530 {
7531         return amd64_use_imm32 (imm);
7532 }
7533
7534 /*
7535  * Determine whenever the trap whose info is in SIGINFO is caused by
7536  * integer overflow.
7537  */
7538 gboolean
7539 mono_arch_is_int_overflow (void *sigctx, void *info)
7540 {
7541         MonoContext ctx;
7542         guint8* rip;
7543         int reg;
7544         gint64 value;
7545
7546         mono_sigctx_to_monoctx (sigctx, &ctx);
7547
7548         rip = (guint8*)ctx.gregs [AMD64_RIP];
7549
7550         if (IS_REX (rip [0])) {
7551                 reg = amd64_rex_b (rip [0]);
7552                 rip ++;
7553         }
7554         else
7555                 reg = 0;
7556
7557         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7558                 /* idiv REG */
7559                 reg += x86_modrm_rm (rip [1]);
7560
7561                 value = ctx.gregs [reg];
7562
7563                 if (value == -1)
7564                         return TRUE;
7565         }
7566
7567         return FALSE;
7568 }
7569
7570 guint32
7571 mono_arch_get_patch_offset (guint8 *code)
7572 {
7573         return 3;
7574 }
7575
7576 /**
7577  * \return TRUE if no sw breakpoint was present.
7578  *
7579  * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7580  * breakpoints in the original code, they are removed in the copy.
7581  */
7582 gboolean
7583 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7584 {
7585         /*
7586          * If method_start is non-NULL we need to perform bound checks, since we access memory
7587          * at code - offset we could go before the start of the method and end up in a different
7588          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7589          * instead.
7590          */
7591         if (!method_start || code - offset >= method_start) {
7592                 memcpy (buf, code - offset, size);
7593         } else {
7594                 int diff = code - method_start;
7595                 memset (buf, 0, size);
7596                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7597         }
7598         return TRUE;
7599 }
7600
7601 int
7602 mono_arch_get_this_arg_reg (guint8 *code)
7603 {
7604         return AMD64_ARG_REG1;
7605 }
7606
7607 gpointer
7608 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7609 {
7610         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7611 }
7612
7613 #define MAX_ARCH_DELEGATE_PARAMS 10
7614
7615 static gpointer
7616 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7617 {
7618         guint8 *code, *start;
7619         GSList *unwind_ops = NULL;
7620         int i;
7621
7622         unwind_ops = mono_arch_get_cie_program ();
7623
7624         if (has_target) {
7625                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7626
7627                 /* Replace the this argument with the target */
7628                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7629                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7630                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7631
7632                 g_assert ((code - start) < 64);
7633                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7634         } else {
7635                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7636
7637                 if (param_count == 0) {
7638                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7639                 } else {
7640                         /* We have to shift the arguments left */
7641                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7642                         for (i = 0; i < param_count; ++i) {
7643 #ifdef TARGET_WIN32
7644                                 if (i < 3)
7645                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7646                                 else
7647                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7648 #else
7649                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7650 #endif
7651                         }
7652
7653                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7654                 }
7655                 g_assert ((code - start) < 64);
7656                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7657         }
7658
7659         mono_arch_flush_icache (start, code - start);
7660
7661         if (has_target) {
7662                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7663         } else {
7664                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7665                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7666                 g_free (name);
7667         }
7668
7669         if (mono_jit_map_is_enabled ()) {
7670                 char *buff;
7671                 if (has_target)
7672                         buff = (char*)"delegate_invoke_has_target";
7673                 else
7674                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7675                 mono_emit_jit_tramp (start, code - start, buff);
7676                 if (!has_target)
7677                         g_free (buff);
7678         }
7679         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7680
7681         return start;
7682 }
7683
7684 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7685
7686 static gpointer
7687 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7688 {
7689         guint8 *code, *start;
7690         int size = 20;
7691         char *tramp_name;
7692         GSList *unwind_ops;
7693
7694         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7695                 return NULL;
7696
7697         start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7698
7699         unwind_ops = mono_arch_get_cie_program ();
7700
7701         /* Replace the this argument with the target */
7702         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7703         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7704
7705         if (load_imt_reg) {
7706                 /* Load the IMT reg */
7707                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7708         }
7709
7710         /* Load the vtable */
7711         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7712         amd64_jump_membase (code, AMD64_RAX, offset);
7713         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7714
7715         tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7716         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7717         g_free (tramp_name);
7718
7719         return start;
7720 }
7721
7722 /*
7723  * mono_arch_get_delegate_invoke_impls:
7724  *
7725  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7726  * trampolines.
7727  */
7728 GSList*
7729 mono_arch_get_delegate_invoke_impls (void)
7730 {
7731         GSList *res = NULL;
7732         MonoTrampInfo *info;
7733         int i;
7734
7735         get_delegate_invoke_impl (&info, TRUE, 0);
7736         res = g_slist_prepend (res, info);
7737
7738         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7739                 get_delegate_invoke_impl (&info, FALSE, i);
7740                 res = g_slist_prepend (res, info);
7741         }
7742
7743         for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7744                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7745                 res = g_slist_prepend (res, info);
7746         }
7747
7748         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7749                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7750                 res = g_slist_prepend (res, info);
7751                 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7752                 res = g_slist_prepend (res, info);
7753         }
7754
7755         return res;
7756 }
7757
7758 gpointer
7759 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7760 {
7761         guint8 *code, *start;
7762         int i;
7763
7764         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7765                 return NULL;
7766
7767         /* FIXME: Support more cases */
7768         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7769                 return NULL;
7770
7771         if (has_target) {
7772                 static guint8* cached = NULL;
7773
7774                 if (cached)
7775                         return cached;
7776
7777                 if (mono_aot_only) {
7778                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7779                 } else {
7780                         MonoTrampInfo *info;
7781                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7782                         mono_tramp_info_register (info, NULL);
7783                 }
7784
7785                 mono_memory_barrier ();
7786
7787                 cached = start;
7788         } else {
7789                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7790                 for (i = 0; i < sig->param_count; ++i)
7791                         if (!mono_is_regsize_var (sig->params [i]))
7792                                 return NULL;
7793                 if (sig->param_count > 4)
7794                         return NULL;
7795
7796                 code = cache [sig->param_count];
7797                 if (code)
7798                         return code;
7799
7800                 if (mono_aot_only) {
7801                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7802                         start = (guint8 *)mono_aot_get_trampoline (name);
7803                         g_free (name);
7804                 } else {
7805                         MonoTrampInfo *info;
7806                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7807                         mono_tramp_info_register (info, NULL);
7808                 }
7809
7810                 mono_memory_barrier ();
7811
7812                 cache [sig->param_count] = start;
7813         }
7814
7815         return start;
7816 }
7817
7818 gpointer
7819 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7820 {
7821         MonoTrampInfo *info;
7822         gpointer code;
7823
7824         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7825         if (code)
7826                 mono_tramp_info_register (info, NULL);
7827         return code;
7828 }
7829
7830 void
7831 mono_arch_finish_init (void)
7832 {
7833 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7834         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7835 #endif
7836 }
7837
7838 void
7839 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7840 {
7841 }
7842
7843 #define CMP_SIZE (6 + 1)
7844 #define CMP_REG_REG_SIZE (4 + 1)
7845 #define BR_SMALL_SIZE 2
7846 #define BR_LARGE_SIZE 6
7847 #define MOV_REG_IMM_SIZE 10
7848 #define MOV_REG_IMM_32BIT_SIZE 6
7849 #define JUMP_REG_SIZE (2 + 1)
7850
7851 static int
7852 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7853 {
7854         int i, distance = 0;
7855         for (i = start; i < target; ++i)
7856                 distance += imt_entries [i]->chunk_size;
7857         return distance;
7858 }
7859
7860 /*
7861  * LOCKING: called with the domain lock held
7862  */
7863 gpointer
7864 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7865         gpointer fail_tramp)
7866 {
7867         int i;
7868         int size = 0;
7869         guint8 *code, *start;
7870         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7871         GSList *unwind_ops;
7872
7873         for (i = 0; i < count; ++i) {
7874                 MonoIMTCheckItem *item = imt_entries [i];
7875                 if (item->is_equals) {
7876                         if (item->check_target_idx) {
7877                                 if (!item->compare_done) {
7878                                         if (amd64_use_imm32 ((gint64)item->key))
7879                                                 item->chunk_size += CMP_SIZE;
7880                                         else
7881                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7882                                 }
7883                                 if (item->has_target_code) {
7884                                         item->chunk_size += MOV_REG_IMM_SIZE;
7885                                 } else {
7886                                         if (vtable_is_32bit)
7887                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7888                                         else
7889                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7890                                 }
7891                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7892                         } else {
7893                                 if (fail_tramp) {
7894                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7895                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7896                                 } else {
7897                                         if (vtable_is_32bit)
7898                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7899                                         else
7900                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7901                                         item->chunk_size += JUMP_REG_SIZE;
7902                                         /* with assert below:
7903                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7904                                          */
7905                                 }
7906                         }
7907                 } else {
7908                         if (amd64_use_imm32 ((gint64)item->key))
7909                                 item->chunk_size += CMP_SIZE;
7910                         else
7911                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7912                         item->chunk_size += BR_LARGE_SIZE;
7913                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7914                 }
7915                 size += item->chunk_size;
7916         }
7917         if (fail_tramp)
7918                 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7919         else
7920                 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7921         start = code;
7922
7923         unwind_ops = mono_arch_get_cie_program ();
7924
7925         for (i = 0; i < count; ++i) {
7926                 MonoIMTCheckItem *item = imt_entries [i];
7927                 item->code_target = code;
7928                 if (item->is_equals) {
7929                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7930
7931                         if (item->check_target_idx || fail_case) {
7932                                 if (!item->compare_done || fail_case) {
7933                                         if (amd64_use_imm32 ((gint64)item->key))
7934                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7935                                         else {
7936                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7937                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7938                                         }
7939                                 }
7940                                 item->jmp_code = code;
7941                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7942                                 if (item->has_target_code) {
7943                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7944                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7945                                 } else {
7946                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7947                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7948                                 }
7949
7950                                 if (fail_case) {
7951                                         amd64_patch (item->jmp_code, code);
7952                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7953                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7954                                         item->jmp_code = NULL;
7955                                 }
7956                         } else {
7957                                 /* enable the commented code to assert on wrong method */
7958 #if 0
7959                                 if (amd64_is_imm32 (item->key))
7960                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7961                                 else {
7962                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7963                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7964                                 }
7965                                 item->jmp_code = code;
7966                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7967                                 /* See the comment below about R10 */
7968                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7969                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7970                                 amd64_patch (item->jmp_code, code);
7971                                 amd64_breakpoint (code);
7972                                 item->jmp_code = NULL;
7973 #else
7974                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7975                                    needs to be preserved.  R10 needs
7976                                    to be preserved for calls which
7977                                    require a runtime generic context,
7978                                    but interface calls don't. */
7979                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7980                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7981 #endif
7982                         }
7983                 } else {
7984                         if (amd64_use_imm32 ((gint64)item->key))
7985                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7986                         else {
7987                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7988                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7989                         }
7990                         item->jmp_code = code;
7991                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7992                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7993                         else
7994                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7995                 }
7996                 g_assert (code - item->code_target <= item->chunk_size);
7997         }
7998         /* patch the branches to get to the target items */
7999         for (i = 0; i < count; ++i) {
8000                 MonoIMTCheckItem *item = imt_entries [i];
8001                 if (item->jmp_code) {
8002                         if (item->check_target_idx) {
8003                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8004                         }
8005                 }
8006         }
8007
8008         if (!fail_tramp)
8009                 mono_stats.imt_trampolines_size += code - start;
8010         g_assert (code - start <= size);
8011         g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8012
8013         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8014
8015         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8016
8017         return start;
8018 }
8019
8020 MonoMethod*
8021 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8022 {
8023         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8024 }
8025
8026 MonoVTable*
8027 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8028 {
8029         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8030 }
8031
8032 GSList*
8033 mono_arch_get_cie_program (void)
8034 {
8035         GSList *l = NULL;
8036
8037         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8038         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8039
8040         return l;
8041 }
8042
8043 #ifndef DISABLE_JIT
8044
8045 MonoInst*
8046 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8047 {
8048         MonoInst *ins = NULL;
8049         int opcode = 0;
8050
8051         if (cmethod->klass == mono_defaults.math_class) {
8052                 if (strcmp (cmethod->name, "Sin") == 0) {
8053                         opcode = OP_SIN;
8054                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8055                         opcode = OP_COS;
8056                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8057                         opcode = OP_SQRT;
8058                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8059                         opcode = OP_ABS;
8060                 }
8061
8062                 if (opcode && fsig->param_count == 1) {
8063                         MONO_INST_NEW (cfg, ins, opcode);
8064                         ins->type = STACK_R8;
8065                         ins->dreg = mono_alloc_freg (cfg);
8066                         ins->sreg1 = args [0]->dreg;
8067                         MONO_ADD_INS (cfg->cbb, ins);
8068                 }
8069
8070                 opcode = 0;
8071                 if (cfg->opt & MONO_OPT_CMOV) {
8072                         if (strcmp (cmethod->name, "Min") == 0) {
8073                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8074                                         opcode = OP_IMIN;
8075                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8076                                         opcode = OP_IMIN_UN;
8077                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8078                                         opcode = OP_LMIN;
8079                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8080                                         opcode = OP_LMIN_UN;
8081                         } else if (strcmp (cmethod->name, "Max") == 0) {
8082                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8083                                         opcode = OP_IMAX;
8084                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8085                                         opcode = OP_IMAX_UN;
8086                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8087                                         opcode = OP_LMAX;
8088                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8089                                         opcode = OP_LMAX_UN;
8090                         }
8091                 }
8092
8093                 if (opcode && fsig->param_count == 2) {
8094                         MONO_INST_NEW (cfg, ins, opcode);
8095                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8096                         ins->dreg = mono_alloc_ireg (cfg);
8097                         ins->sreg1 = args [0]->dreg;
8098                         ins->sreg2 = args [1]->dreg;
8099                         MONO_ADD_INS (cfg->cbb, ins);
8100                 }
8101
8102 #if 0
8103                 /* OP_FREM is not IEEE compatible */
8104                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8105                         MONO_INST_NEW (cfg, ins, OP_FREM);
8106                         ins->inst_i0 = args [0];
8107                         ins->inst_i1 = args [1];
8108                 }
8109 #endif
8110         }
8111
8112         return ins;
8113 }
8114 #endif
8115
8116 gboolean
8117 mono_arch_print_tree (MonoInst *tree, int arity)
8118 {
8119         return 0;
8120 }
8121
8122 mgreg_t
8123 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8124 {
8125         return ctx->gregs [reg];
8126 }
8127
8128 void
8129 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8130 {
8131         ctx->gregs [reg] = val;
8132 }
8133
8134 gpointer
8135 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8136 {
8137         gpointer *sp, old_value;
8138         char *bp;
8139
8140         /*Load the spvar*/
8141         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8142         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8143
8144         old_value = *sp;
8145         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8146                 return old_value;
8147
8148         *sp = new_value;
8149
8150         return old_value;
8151 }
8152
8153 /*
8154  * mono_arch_emit_load_aotconst:
8155  *
8156  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8157  * TARGET from the mscorlib GOT in full-aot code.
8158  * On AMD64, the result is placed into R11.
8159  */
8160 guint8*
8161 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8162 {
8163         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8164         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8165
8166         return code;
8167 }
8168
8169 /*
8170  * mono_arch_get_trampolines:
8171  *
8172  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8173  * for AOT.
8174  */
8175 GSList *
8176 mono_arch_get_trampolines (gboolean aot)
8177 {
8178         return mono_amd64_get_exception_trampolines (aot);
8179 }
8180
8181 /* Soft Debug support */
8182 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8183
8184 /*
8185  * mono_arch_set_breakpoint:
8186  *
8187  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8188  * The location should contain code emitted by OP_SEQ_POINT.
8189  */
8190 void
8191 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8192 {
8193         guint8 *code = ip;
8194
8195         if (ji->from_aot) {
8196                 guint32 native_offset = ip - (guint8*)ji->code_start;
8197                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8198
8199                 g_assert (info->bp_addrs [native_offset] == 0);
8200                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8201         } else {
8202                 /* ip points to a mov r11, 0 */
8203                 g_assert (code [0] == 0x41);
8204                 g_assert (code [1] == 0xbb);
8205                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8206         }
8207 }
8208
8209 /*
8210  * mono_arch_clear_breakpoint:
8211  *
8212  *   Clear the breakpoint at IP.
8213  */
8214 void
8215 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8216 {
8217         guint8 *code = ip;
8218
8219         if (ji->from_aot) {
8220                 guint32 native_offset = ip - (guint8*)ji->code_start;
8221                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8222
8223                 info->bp_addrs [native_offset] = NULL;
8224         } else {
8225                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8226         }
8227 }
8228
8229 gboolean
8230 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8231 {
8232         /* We use soft breakpoints on amd64 */
8233         return FALSE;
8234 }
8235
8236 /*
8237  * mono_arch_skip_breakpoint:
8238  *
8239  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8240  * we resume, the instruction is not executed again.
8241  */
8242 void
8243 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8244 {
8245         g_assert_not_reached ();
8246 }
8247
8248 /*
8249  * mono_arch_start_single_stepping:
8250  *
8251  *   Start single stepping.
8252  */
8253 void
8254 mono_arch_start_single_stepping (void)
8255 {
8256         ss_trampoline = mini_get_single_step_trampoline ();
8257 }
8258
8259 /*
8260  * mono_arch_stop_single_stepping:
8261  *
8262  *   Stop single stepping.
8263  */
8264 void
8265 mono_arch_stop_single_stepping (void)
8266 {
8267         ss_trampoline = NULL;
8268 }
8269
8270 /*
8271  * mono_arch_is_single_step_event:
8272  *
8273  *   Return whenever the machine state in SIGCTX corresponds to a single
8274  * step event.
8275  */
8276 gboolean
8277 mono_arch_is_single_step_event (void *info, void *sigctx)
8278 {
8279         /* We use soft breakpoints on amd64 */
8280         return FALSE;
8281 }
8282
8283 /*
8284  * mono_arch_skip_single_step:
8285  *
8286  *   Modify CTX so the ip is placed after the single step trigger instruction,
8287  * we resume, the instruction is not executed again.
8288  */
8289 void
8290 mono_arch_skip_single_step (MonoContext *ctx)
8291 {
8292         g_assert_not_reached ();
8293 }
8294
8295 /*
8296  * mono_arch_create_seq_point_info:
8297  *
8298  *   Return a pointer to a data structure which is used by the sequence
8299  * point implementation in AOTed code.
8300  */
8301 gpointer
8302 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8303 {
8304         SeqPointInfo *info;
8305         MonoJitInfo *ji;
8306
8307         // FIXME: Add a free function
8308
8309         mono_domain_lock (domain);
8310         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8311                                                                 code);
8312         mono_domain_unlock (domain);
8313
8314         if (!info) {
8315                 ji = mono_jit_info_table_find (domain, (char*)code);
8316                 g_assert (ji);
8317
8318                 // FIXME: Optimize the size
8319                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8320
8321                 info->ss_tramp_addr = &ss_trampoline;
8322
8323                 mono_domain_lock (domain);
8324                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8325                                                          code, info);
8326                 mono_domain_unlock (domain);
8327         }
8328
8329         return info;
8330 }
8331
8332 void
8333 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8334 {
8335         ext->lmf.previous_lmf = prev_lmf;
8336         /* Mark that this is a MonoLMFExt */
8337         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8338         ext->lmf.rsp = (gssize)ext;
8339 }
8340
8341 #endif
8342
8343 gboolean
8344 mono_arch_opcode_supported (int opcode)
8345 {
8346         switch (opcode) {
8347         case OP_ATOMIC_ADD_I4:
8348         case OP_ATOMIC_ADD_I8:
8349         case OP_ATOMIC_EXCHANGE_I4:
8350         case OP_ATOMIC_EXCHANGE_I8:
8351         case OP_ATOMIC_CAS_I4:
8352         case OP_ATOMIC_CAS_I8:
8353         case OP_ATOMIC_LOAD_I1:
8354         case OP_ATOMIC_LOAD_I2:
8355         case OP_ATOMIC_LOAD_I4:
8356         case OP_ATOMIC_LOAD_I8:
8357         case OP_ATOMIC_LOAD_U1:
8358         case OP_ATOMIC_LOAD_U2:
8359         case OP_ATOMIC_LOAD_U4:
8360         case OP_ATOMIC_LOAD_U8:
8361         case OP_ATOMIC_LOAD_R4:
8362         case OP_ATOMIC_LOAD_R8:
8363         case OP_ATOMIC_STORE_I1:
8364         case OP_ATOMIC_STORE_I2:
8365         case OP_ATOMIC_STORE_I4:
8366         case OP_ATOMIC_STORE_I8:
8367         case OP_ATOMIC_STORE_U1:
8368         case OP_ATOMIC_STORE_U2:
8369         case OP_ATOMIC_STORE_U4:
8370         case OP_ATOMIC_STORE_U8:
8371         case OP_ATOMIC_STORE_R4:
8372         case OP_ATOMIC_STORE_R8:
8373                 return TRUE;
8374         default:
8375                 return FALSE;
8376         }
8377 }
8378
8379 CallInfo*
8380 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8381 {
8382         return get_call_info (mp, sig);
8383 }