mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 #ifdef HOST_WIN32
  89 /* On Win64 always reserve first 32 bytes for first four arguments */
  90 #define ARGS_OFFSET 48
  91 #else
  92 #define ARGS_OFFSET 16
  93 #endif
  94 #define GP_SCRATCH_REG AMD64_R11
  95
  96 /*
  97  * AMD64 register usage:
  98  * - callee saved registers are used for global register allocation
  99  * - %r11 is used for materializing 64 bit constants in opcodes
 100  * - the rest is used for local allocation
 101  */
 102
 103 /*
 104  * Floating point comparison results:
 105  *                  ZF PF CF
 106  * A > B            0  0  0
 107  * A < B            0  0  1
 108  * A = B            1  0  0
 109  * A > B            0  0  0
 110  * UNORDERED        1  1  1
 111  */
 112
 113 const char*
 114 mono_arch_regname (int reg)
 115 {
 116         switch (reg) {
 117         case AMD64_RAX: return "%rax";
 118         case AMD64_RBX: return "%rbx";
 119         case AMD64_RCX: return "%rcx";
 120         case AMD64_RDX: return "%rdx";
 121         case AMD64_RSP: return "%rsp";
 122         case AMD64_RBP: return "%rbp";
 123         case AMD64_RDI: return "%rdi";
 124         case AMD64_RSI: return "%rsi";
 125         case AMD64_R8: return "%r8";
 126         case AMD64_R9: return "%r9";
 127         case AMD64_R10: return "%r10";
 128         case AMD64_R11: return "%r11";
 129         case AMD64_R12: return "%r12";
 130         case AMD64_R13: return "%r13";
 131         case AMD64_R14: return "%r14";
 132         case AMD64_R15: return "%r15";
 133         }
 134         return "unknown";
 135 }
 136
 137 static const char * packed_xmmregs [] = {
 138         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 139         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 140 };
 141
 142 static const char * single_xmmregs [] = {
 143         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 144         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 145 };
 146
 147 const char*
 148 mono_arch_fregname (int reg)
 149 {
 150         if (reg < AMD64_XMM_NREG)
 151                 return single_xmmregs [reg];
 152         else
 153                 return "unknown";
 154 }
 155
 156 const char *
 157 mono_arch_xregname (int reg)
 158 {
 159         if (reg < AMD64_XMM_NREG)
 160                 return packed_xmmregs [reg];
 161         else
 162                 return "unknown";
 163 }
 164
 165 static gboolean
 166 debug_omit_fp (void)
 167 {
 168 #if 0
 169         return mono_debug_count ();
 170 #else
 171         return TRUE;
 172 #endif
 173 }
 174
 175 static inline gboolean
 176 amd64_is_near_call (guint8 *code)
 177 {
 178         /* Skip REX */
 179         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 180                 code += 1;
 181
 182         return code [0] == 0xe8;
 183 }
 184
 185 #ifdef __native_client_codegen__
 186
 187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 188 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 190 /* We only want to force bundle alignment for the top level instruction,    */
 191 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 192 static MonoNativeTlsKey nacl_instruction_depth;
 193
 194 static MonoNativeTlsKey nacl_rex_tag;
 195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 196
 197 void
 198 amd64_nacl_clear_legacy_prefix_tag ()
 199 {
 200         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 201 }
 202
 203 void
 204 amd64_nacl_tag_legacy_prefix (guint8* code)
 205 {
 206         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 207                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 208 }
 209
 210 void
 211 amd64_nacl_tag_rex (guint8* code)
 212 {
 213         mono_native_tls_set_value (nacl_rex_tag, code);
 214 }
 215
 216 guint8*
 217 amd64_nacl_get_legacy_prefix_tag ()
 218 {
 219         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 220 }
 221
 222 guint8*
 223 amd64_nacl_get_rex_tag ()
 224 {
 225         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 226 }
 227
 228 /* Increment the instruction "depth" described above */
 229 void
 230 amd64_nacl_instruction_pre ()
 231 {
 232         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 233         depth++;
 234         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 235 }
 236
 237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 238 /* alignment if depth == 0 (top level instruction)                          */
 239 /* IN: start, end    pointers to instruction beginning and end              */
 240 /* OUT: start, end   pointers to beginning and end after possible alignment */
 241 /* GLOBALS: nacl_instruction_depth     defined above                        */
 242 void
 243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 244 {
 245         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 246         depth--;
 247         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 248
 249         g_assert ( depth >= 0 );
 250         if (depth == 0) {
 251                 uintptr_t space_in_block;
 252                 uintptr_t instlen;
 253                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 254                 /* if legacy prefix is present, and if it was emitted before */
 255                 /* the start of the instruction sequence, adjust the start   */
 256                 if (prefix != NULL && prefix < *start) {
 257                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 258                         *start = prefix;
 259                 }
 260                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 261                 instlen = (uintptr_t)(*end - *start);
 262                 /* Only check for instructions which are less than        */
 263                 /* kNaClAlignment. The only instructions that should ever */
 264                 /* be that long are call sequences, which are already     */
 265                 /* padded out to align the return to the next bundle.     */
 266                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 267                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 268                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 269                         const size_t length = (size_t)((*end)-(*start));
 270                         g_assert (length < MAX_NACL_INST_LENGTH);
 271
 272                         memcpy (copy_of_instruction, *start, length);
 273                         *start = mono_arch_nacl_pad (*start, space_in_block);
 274                         memcpy (*start, copy_of_instruction, length);
 275                         *end = *start + length;
 276                 }
 277                 amd64_nacl_clear_legacy_prefix_tag ();
 278                 amd64_nacl_tag_rex (NULL);
 279         }
 280 }
 281
 282 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 283 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 284 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 285 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 286 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 287 /* IN:      code                                                            */
 288 /*             pointer to current instruction stream (in the                */
 289 /*             middle of an instruction, after opcode is emitted)           */
 290 /*          basereg/offset/dreg                                             */
 291 /*             operands of normal membase address                           */
 292 /* OUT:     code                                                            */
 293 /*             pointer to the end of the membase/memindex emit              */
 294 /* GLOBALS: nacl_rex_tag                                                    */
 295 /*             position in instruction stream that rex prefix was emitted   */
 296 /*          nacl_legacy_prefix_tag                                          */
 297 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 298 void
 299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 300 {
 301         gint8 true_basereg = basereg;
 302
 303         /* Cache these values, they might change  */
 304         /* as new instructions are emitted below. */
 305         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 306         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 307
 308         /* 'basereg' is given masked to 0x7 at this point, so check */
 309         /* the rex prefix to see if this is an extended register.   */
 310         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 311                 true_basereg |= 0x8;
 312         }
 313
 314 #define X86_LEA_OPCODE (0x8D)
 315
 316         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 317                 guint8* old_instruction_start;
 318
 319                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 320                 /* 32-bits of the old base register (new index register)     */
 321                 guint8 buf[32];
 322                 guint8* buf_ptr = buf;
 323                 size_t insert_len;
 324
 325                 g_assert (rex_tag != NULL);
 326
 327                 if (IS_REX(*rex_tag)) {
 328                         /* The old rex.B should be the new rex.X */
 329                         if (*rex_tag & AMD64_REX_B) {
 330                                 *rex_tag |= AMD64_REX_X;
 331                         }
 332                         /* Since our new base is %r15 set rex.B */
 333                         *rex_tag |= AMD64_REX_B;
 334                 } else {
 335                         /* Shift the instruction by one byte  */
 336                         /* so we can insert a rex prefix      */
 337                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 338                         *code += 1;
 339                         /* New rex prefix only needs rex.B for %r15 base */
 340                         *rex_tag = AMD64_REX(AMD64_REX_B);
 341                 }
 342
 343                 if (legacy_prefix_tag) {
 344                         old_instruction_start = legacy_prefix_tag;
 345                 } else {
 346                         old_instruction_start = rex_tag;
 347                 }
 348
 349                 /* Clears the upper 32-bits of the previous base register */
 350                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 351                 insert_len = buf_ptr - buf;
 352
 353                 /* Move the old instruction forward to make */
 354                 /* room for 'mov' stored in 'buf_ptr'       */
 355                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 356                 *code += insert_len;
 357                 memcpy (old_instruction_start, buf, insert_len);
 358
 359                 /* Sandboxed replacement for the normal membase_emit */
 360                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 361
 362         } else {
 363                 /* Normal default behavior, emit membase memory location */
 364                 x86_membase_emit_body (*code, dreg, basereg, offset);
 365         }
 366 }
 367
 368
 369 static inline unsigned char*
 370 amd64_skip_nops (unsigned char* code)
 371 {
 372         guint8 in_nop;
 373         do {
 374                 in_nop = 0;
 375                 if (   code[0] == 0x90) {
 376                         in_nop = 1;
 377                         code += 1;
 378                 }
 379                 if (   code[0] == 0x66 && code[1] == 0x90) {
 380                         in_nop = 1;
 381                         code += 2;
 382                 }
 383                 if (code[0] == 0x0f && code[1] == 0x1f
 384                  && code[2] == 0x00) {
 385                         in_nop = 1;
 386                         code += 3;
 387                 }
 388                 if (code[0] == 0x0f && code[1] == 0x1f
 389                  && code[2] == 0x40 && code[3] == 0x00) {
 390                         in_nop = 1;
 391                         code += 4;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x44 && code[3] == 0x00
 395                  && code[4] == 0x00) {
 396                         in_nop = 1;
 397                         code += 5;
 398                 }
 399                 if (code[0] == 0x66 && code[1] == 0x0f
 400                  && code[2] == 0x1f && code[3] == 0x44
 401                  && code[4] == 0x00 && code[5] == 0x00) {
 402                         in_nop = 1;
 403                         code += 6;
 404                 }
 405                 if (code[0] == 0x0f && code[1] == 0x1f
 406                  && code[2] == 0x80 && code[3] == 0x00
 407                  && code[4] == 0x00 && code[5] == 0x00
 408                  && code[6] == 0x00) {
 409                         in_nop = 1;
 410                         code += 7;
 411                 }
 412                 if (code[0] == 0x0f && code[1] == 0x1f
 413                  && code[2] == 0x84 && code[3] == 0x00
 414                  && code[4] == 0x00 && code[5] == 0x00
 415                  && code[6] == 0x00 && code[7] == 0x00) {
 416                         in_nop = 1;
 417                         code += 8;
 418                 }
 419         } while ( in_nop );
 420         return code;
 421 }
 422
 423 guint8*
 424 mono_arch_nacl_skip_nops (guint8* code)
 425 {
 426   return amd64_skip_nops(code);
 427 }
 428
 429 #endif /*__native_client_codegen__*/
 430
 431 static inline void
 432 amd64_patch (unsigned char* code, gpointer target)
 433 {
 434         guint8 rex = 0;
 435
 436 #ifdef __native_client_codegen__
 437         code = amd64_skip_nops (code);
 438 #endif
 439 #if defined(__native_client_codegen__) && defined(__native_client__)
 440         if (nacl_is_code_address (code)) {
 441                 /* For tail calls, code is patched after being installed */
 442                 /* but not through the normal "patch callsite" method.   */
 443                 unsigned char buf[kNaClAlignment];
 444                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 445                 int ret;
 446                 memcpy (buf, aligned_code, kNaClAlignment);
 447                 /* Patch a temp buffer of bundle size, */
 448                 /* then install to actual location.    */
 449                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 450                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 451                 g_assert (ret == 0);
 452                 return;
 453         }
 454         target = nacl_modify_patch_target (target);
 455 #endif
 456
 457         /* Skip REX */
 458         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 459                 rex = code [0];
 460                 code += 1;
 461         }
 462
 463         if ((code [0] & 0xf8) == 0xb8) {
 464                 /* amd64_set_reg_template */
 465                 *(guint64*)(code + 1) = (guint64)target;
 466         }
 467         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 468                 /* mov 0(%rip), %dreg */
 469                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 470         }
 471         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 472                 /* call *<OFFSET>(%rip) */
 473                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 474         }
 475         else if (code [0] == 0xe8) {
 476                 /* call <DISP> */
 477                 gint64 disp = (guint8*)target - (guint8*)code;
 478                 g_assert (amd64_is_imm32 (disp));
 479                 x86_patch (code, (unsigned char*)target);
 480         }
 481         else
 482                 x86_patch (code, (unsigned char*)target);
 483 }
 484
 485 void
 486 mono_amd64_patch (unsigned char* code, gpointer target)
 487 {
 488         amd64_patch (code, target);
 489 }
 490
 491 typedef enum {
 492         ArgInIReg,
 493         ArgInFloatSSEReg,
 494         ArgInDoubleSSEReg,
 495         ArgOnStack,
 496         ArgValuetypeInReg,
 497         ArgValuetypeAddrInIReg,
 498         ArgNone /* only in pair_storage */
 499 } ArgStorage;
 500
 501 typedef struct {
 502         gint16 offset;
 503         gint8  reg;
 504         ArgStorage storage;
 505
 506         /* Only if storage == ArgValuetypeInReg */
 507         ArgStorage pair_storage [2];
 508         gint8 pair_regs [2];
 509         int nregs;
 510 } ArgInfo;
 511
 512 typedef struct {
 513         int nargs;
 514         guint32 stack_usage;
 515         guint32 reg_usage;
 516         guint32 freg_usage;
 517         gboolean need_stack_align;
 518         gboolean vtype_retaddr;
 519         /* The index of the vret arg in the argument list */
 520         int vret_arg_index;
 521         ArgInfo ret;
 522         ArgInfo sig_cookie;
 523         ArgInfo args [1];
 524 } CallInfo;
 525
 526 #define DEBUG(a) if (cfg->verbose_level > 1) a
 527
 528 #ifdef HOST_WIN32
 529 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 530
 531 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 532 #else
 533 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 534
 535  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 536 #endif
 537
 538 static void inline
 539 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 540 {
 541     ainfo->offset = *stack_size;
 542
 543     if (*gr >= PARAM_REGS) {
 544                 ainfo->storage = ArgOnStack;
 545                 /* Since the same stack slot size is used for all arg */
 546                 /*  types, it needs to be big enough to hold them all */
 547                 (*stack_size) += sizeof(mgreg_t);
 548     }
 549     else {
 550                 ainfo->storage = ArgInIReg;
 551                 ainfo->reg = param_regs [*gr];
 552                 (*gr) ++;
 553     }
 554 }
 555
 556 #ifdef HOST_WIN32
 557 #define FLOAT_PARAM_REGS 4
 558 #else
 559 #define FLOAT_PARAM_REGS 8
 560 #endif
 561
 562 static void inline
 563 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 564 {
 565     ainfo->offset = *stack_size;
 566
 567     if (*gr >= FLOAT_PARAM_REGS) {
 568                 ainfo->storage = ArgOnStack;
 569                 /* Since the same stack slot size is used for both float */
 570                 /*  types, it needs to be big enough to hold them both */
 571                 (*stack_size) += sizeof(mgreg_t);
 572     }
 573     else {
 574                 /* A double register */
 575                 if (is_double)
 576                         ainfo->storage = ArgInDoubleSSEReg;
 577                 else
 578                         ainfo->storage = ArgInFloatSSEReg;
 579                 ainfo->reg = *gr;
 580                 (*gr) += 1;
 581     }
 582 }
 583
 584 typedef enum ArgumentClass {
 585         ARG_CLASS_NO_CLASS,
 586         ARG_CLASS_MEMORY,
 587         ARG_CLASS_INTEGER,
 588         ARG_CLASS_SSE
 589 } ArgumentClass;
 590
 591 static ArgumentClass
 592 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 593 {
 594         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 595         MonoType *ptype;
 596
 597         ptype = mini_type_get_underlying_type (gsctx, type);
 598         switch (ptype->type) {
 599         case MONO_TYPE_BOOLEAN:
 600         case MONO_TYPE_CHAR:
 601         case MONO_TYPE_I1:
 602         case MONO_TYPE_U1:
 603         case MONO_TYPE_I2:
 604         case MONO_TYPE_U2:
 605         case MONO_TYPE_I4:
 606         case MONO_TYPE_U4:
 607         case MONO_TYPE_I:
 608         case MONO_TYPE_U:
 609         case MONO_TYPE_STRING:
 610         case MONO_TYPE_OBJECT:
 611         case MONO_TYPE_CLASS:
 612         case MONO_TYPE_SZARRAY:
 613         case MONO_TYPE_PTR:
 614         case MONO_TYPE_FNPTR:
 615         case MONO_TYPE_ARRAY:
 616         case MONO_TYPE_I8:
 617         case MONO_TYPE_U8:
 618                 class2 = ARG_CLASS_INTEGER;
 619                 break;
 620         case MONO_TYPE_R4:
 621         case MONO_TYPE_R8:
 622 #ifdef HOST_WIN32
 623                 class2 = ARG_CLASS_INTEGER;
 624 #else
 625                 class2 = ARG_CLASS_SSE;
 626 #endif
 627                 break;
 628
 629         case MONO_TYPE_TYPEDBYREF:
 630                 g_assert_not_reached ();
 631
 632         case MONO_TYPE_GENERICINST:
 633                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 634                         class2 = ARG_CLASS_INTEGER;
 635                         break;
 636                 }
 637                 /* fall through */
 638         case MONO_TYPE_VALUETYPE: {
 639                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 640                 int i;
 641
 642                 for (i = 0; i < info->num_fields; ++i) {
 643                         class2 = class1;
 644                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 645                 }
 646                 break;
 647         }
 648         default:
 649                 g_assert_not_reached ();
 650         }
 651
 652         /* Merge */
 653         if (class1 == class2)
 654                 ;
 655         else if (class1 == ARG_CLASS_NO_CLASS)
 656                 class1 = class2;
 657         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 658                 class1 = ARG_CLASS_MEMORY;
 659         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 660                 class1 = ARG_CLASS_INTEGER;
 661         else
 662                 class1 = ARG_CLASS_SSE;
 663
 664         return class1;
 665 }
 666 #ifdef __native_client_codegen__
 667
 668 /* Default alignment for Native Client is 32-byte. */
 669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 670
 671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 672 /* Check that alignment doesn't cross an alignment boundary.             */
 673 guint8*
 674 mono_arch_nacl_pad(guint8 *code, int pad)
 675 {
 676         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 677
 678         if (pad == 0) return code;
 679         /* assertion: alignment cannot cross a block boundary */
 680         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 681                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 682         while (pad >= kMaxPadding) {
 683                 amd64_padding (code, kMaxPadding);
 684                 pad -= kMaxPadding;
 685         }
 686         if (pad != 0) amd64_padding (code, pad);
 687         return code;
 688 }
 689 #endif
 690
 691 static void
 692 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 693                            gboolean is_return,
 694                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 695 {
 696         guint32 size, quad, nquads, i;
 697         /* Keep track of the size used in each quad so we can */
 698         /* use the right size when copying args/return vars.  */
 699         guint32 quadsize [2] = {8, 8};
 700         ArgumentClass args [2];
 701         MonoMarshalType *info = NULL;
 702         MonoClass *klass;
 703         MonoGenericSharingContext tmp_gsctx;
 704         gboolean pass_on_stack = FALSE;
 705
 706         /*
 707          * The gsctx currently contains no data, it is only used for checking whenever
 708          * open types are allowed, some callers like mono_arch_get_argument_info ()
 709          * don't pass it to us, so work around that.
 710          */
 711         if (!gsctx)
 712                 gsctx = &tmp_gsctx;
 713
 714         klass = mono_class_from_mono_type (type);
 715         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 716 #ifndef HOST_WIN32
 717         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 718                 /* We pass and return vtypes of size 8 in a register */
 719         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 720                 pass_on_stack = TRUE;
 721         }
 722 #else
 723         if (!sig->pinvoke) {
 724                 pass_on_stack = TRUE;
 725         }
 726 #endif
 727
 728         /* If this struct can't be split up naturally into 8-byte */
 729         /* chunks (registers), pass it on the stack.              */
 730         if (sig->pinvoke && !pass_on_stack) {
 731                 guint32 align;
 732                 guint32 field_size;
 733
 734                 info = mono_marshal_load_type_info (klass);
 735                 g_assert(info);
 736                 for (i = 0; i < info->num_fields; ++i) {
 737                         field_size = mono_marshal_type_size (info->fields [i].field->type,
 738                                                            info->fields [i].mspec,
 739                                                            &align, TRUE, klass->unicode);
 740                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + field_size) > 8) {
 741                                 pass_on_stack = TRUE;
 742                                 break;
 743                         }
 744                 }
 745         }
 746
 747         if (pass_on_stack) {
 748                 /* Allways pass in memory */
 749                 ainfo->offset = *stack_size;
 750                 *stack_size += ALIGN_TO (size, 8);
 751                 ainfo->storage = ArgOnStack;
 752
 753                 return;
 754         }
 755
 756         /* FIXME: Handle structs smaller than 8 bytes */
 757         //if ((size % 8) != 0)
 758         //      NOT_IMPLEMENTED;
 759
 760         if (size > 8)
 761                 nquads = 2;
 762         else
 763                 nquads = 1;
 764
 765         if (!sig->pinvoke) {
 766                 /* Always pass in 1 or 2 integer registers */
 767                 args [0] = ARG_CLASS_INTEGER;
 768                 args [1] = ARG_CLASS_INTEGER;
 769                 /* Only the simplest cases are supported */
 770                 if (is_return && nquads != 1) {
 771                         args [0] = ARG_CLASS_MEMORY;
 772                         args [1] = ARG_CLASS_MEMORY;
 773                 }
 774         } else {
 775                 /*
 776                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 777                  * The X87 and SSEUP stuff is left out since there are no such types in
 778                  * the CLR.
 779                  */
 780                 info = mono_marshal_load_type_info (klass);
 781                 g_assert (info);
 782
 783 #ifndef HOST_WIN32
 784                 if (info->native_size > 16) {
 785                         ainfo->offset = *stack_size;
 786                         *stack_size += ALIGN_TO (info->native_size, 8);
 787                         ainfo->storage = ArgOnStack;
 788
 789                         return;
 790                 }
 791 #else
 792                 switch (info->native_size) {
 793                 case 1: case 2: case 4: case 8:
 794                         break;
 795                 default:
 796                         if (is_return) {
 797                                 ainfo->storage = ArgOnStack;
 798                                 ainfo->offset = *stack_size;
 799                                 *stack_size += ALIGN_TO (info->native_size, 8);
 800                         }
 801                         else {
 802                                 ainfo->storage = ArgValuetypeAddrInIReg;
 803
 804                                 if (*gr < PARAM_REGS) {
 805                                         ainfo->pair_storage [0] = ArgInIReg;
 806                                         ainfo->pair_regs [0] = param_regs [*gr];
 807                                         (*gr) ++;
 808                                 }
 809                                 else {
 810                                         ainfo->pair_storage [0] = ArgOnStack;
 811                                         ainfo->offset = *stack_size;
 812                                         *stack_size += 8;
 813                                 }
 814                         }
 815
 816                         return;
 817                 }
 818 #endif
 819
 820                 args [0] = ARG_CLASS_NO_CLASS;
 821                 args [1] = ARG_CLASS_NO_CLASS;
 822                 for (quad = 0; quad < nquads; ++quad) {
 823                         int size;
 824                         guint32 align;
 825                         ArgumentClass class1;
 826
 827                         if (info->num_fields == 0)
 828                                 class1 = ARG_CLASS_MEMORY;
 829                         else
 830                                 class1 = ARG_CLASS_NO_CLASS;
 831                         for (i = 0; i < info->num_fields; ++i) {
 832                                 size = mono_marshal_type_size (info->fields [i].field->type,
 833                                                                                            info->fields [i].mspec,
 834                                                                                            &align, TRUE, klass->unicode);
 835                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 836                                         /* Unaligned field */
 837                                         NOT_IMPLEMENTED;
 838                                 }
 839
 840                                 /* Skip fields in other quad */
 841                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 842                                         continue;
 843                                 if ((quad == 1) && (info->fields [i].offset < 8))
 844                                         continue;
 845
 846                                 /* How far into this quad this data extends.*/
 847                                 /* (8 is size of quad) */
 848                                 quadsize [quad] = info->fields [i].offset + size - (quad * 8);
 849
 850                                 class1 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class1);
 851                         }
 852                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 853                         args [quad] = class1;
 854                 }
 855         }
 856
 857         /* Post merger cleanup */
 858         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 859                 args [0] = args [1] = ARG_CLASS_MEMORY;
 860
 861         /* Allocate registers */
 862         {
 863                 int orig_gr = *gr;
 864                 int orig_fr = *fr;
 865
 866                 ainfo->storage = ArgValuetypeInReg;
 867                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 868                 ainfo->nregs = nquads;
 869                 for (quad = 0; quad < nquads; ++quad) {
 870                         switch (args [quad]) {
 871                         case ARG_CLASS_INTEGER:
 872                                 if (*gr >= PARAM_REGS)
 873                                         args [quad] = ARG_CLASS_MEMORY;
 874                                 else {
 875                                         ainfo->pair_storage [quad] = ArgInIReg;
 876                                         if (is_return)
 877                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 878                                         else
 879                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 880                                         (*gr) ++;
 881                                 }
 882                                 break;
 883                         case ARG_CLASS_SSE:
 884                                 if (*fr >= FLOAT_PARAM_REGS)
 885                                         args [quad] = ARG_CLASS_MEMORY;
 886                                 else {
 887                                         if (quadsize[quad] <= 4)
 888                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 889                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 890                                         ainfo->pair_regs [quad] = *fr;
 891                                         (*fr) ++;
 892                                 }
 893                                 break;
 894                         case ARG_CLASS_MEMORY:
 895                                 break;
 896                         default:
 897                                 g_assert_not_reached ();
 898                         }
 899                 }
 900
 901                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 902                         /* Revert possible register assignments */
 903                         *gr = orig_gr;
 904                         *fr = orig_fr;
 905
 906                         ainfo->offset = *stack_size;
 907                         if (sig->pinvoke)
 908                                 *stack_size += ALIGN_TO (info->native_size, 8);
 909                         else
 910                                 *stack_size += nquads * sizeof(mgreg_t);
 911                         ainfo->storage = ArgOnStack;
 912                 }
 913         }
 914 }
 915
 916 /*
 917  * get_call_info:
 918  *
 919  *  Obtain information about a call according to the calling convention.
 920  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 921  * Draft Version 0.23" document for more information.
 922  */
 923 static CallInfo*
 924 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 925 {
 926         guint32 i, gr, fr, pstart;
 927         MonoType *ret_type;
 928         int n = sig->hasthis + sig->param_count;
 929         guint32 stack_size = 0;
 930         CallInfo *cinfo;
 931         gboolean is_pinvoke = sig->pinvoke;
 932
 933         if (mp)
 934                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 935         else
 936                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 937
 938         cinfo->nargs = n;
 939
 940         gr = 0;
 941         fr = 0;
 942
 943         /* return value */
 944         {
 945                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 946                 switch (ret_type->type) {
 947                 case MONO_TYPE_BOOLEAN:
 948                 case MONO_TYPE_I1:
 949                 case MONO_TYPE_U1:
 950                 case MONO_TYPE_I2:
 951                 case MONO_TYPE_U2:
 952                 case MONO_TYPE_CHAR:
 953                 case MONO_TYPE_I4:
 954                 case MONO_TYPE_U4:
 955                 case MONO_TYPE_I:
 956                 case MONO_TYPE_U:
 957                 case MONO_TYPE_PTR:
 958                 case MONO_TYPE_FNPTR:
 959                 case MONO_TYPE_CLASS:
 960                 case MONO_TYPE_OBJECT:
 961                 case MONO_TYPE_SZARRAY:
 962                 case MONO_TYPE_ARRAY:
 963                 case MONO_TYPE_STRING:
 964                         cinfo->ret.storage = ArgInIReg;
 965                         cinfo->ret.reg = AMD64_RAX;
 966                         break;
 967                 case MONO_TYPE_U8:
 968                 case MONO_TYPE_I8:
 969                         cinfo->ret.storage = ArgInIReg;
 970                         cinfo->ret.reg = AMD64_RAX;
 971                         break;
 972                 case MONO_TYPE_R4:
 973                         cinfo->ret.storage = ArgInFloatSSEReg;
 974                         cinfo->ret.reg = AMD64_XMM0;
 975                         break;
 976                 case MONO_TYPE_R8:
 977                         cinfo->ret.storage = ArgInDoubleSSEReg;
 978                         cinfo->ret.reg = AMD64_XMM0;
 979                         break;
 980                 case MONO_TYPE_GENERICINST:
 981                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 982                                 cinfo->ret.storage = ArgInIReg;
 983                                 cinfo->ret.reg = AMD64_RAX;
 984                                 break;
 985                         }
 986                         /* fall through */
 987 #if defined( __native_client_codegen__ )
 988                 case MONO_TYPE_TYPEDBYREF:
 989 #endif
 990                 case MONO_TYPE_VALUETYPE: {
 991                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 992
 993                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 994                         if (cinfo->ret.storage == ArgOnStack) {
 995                                 cinfo->vtype_retaddr = TRUE;
 996                                 /* The caller passes the address where the value is stored */
 997                         }
 998                         break;
 999                 }
1000 #if !defined( __native_client_codegen__ )
1001                 case MONO_TYPE_TYPEDBYREF:
1002                         /* Same as a valuetype with size 24 */
1003                         cinfo->vtype_retaddr = TRUE;
1004                         break;
1005 #endif
1006                 case MONO_TYPE_VOID:
1007                         break;
1008                 default:
1009                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1010                 }
1011         }
1012
1013         pstart = 0;
1014         /*
1015          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1016          * the first argument, allowing 'this' to be always passed in the first arg reg.
1017          * Also do this if the first argument is a reference type, since virtual calls
1018          * are sometimes made using calli without sig->hasthis set, like in the delegate
1019          * invoke wrappers.
1020          */
1021         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1022                 if (sig->hasthis) {
1023                         add_general (&gr, &stack_size, cinfo->args + 0);
1024                 } else {
1025                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1026                         pstart = 1;
1027                 }
1028                 add_general (&gr, &stack_size, &cinfo->ret);
1029                 cinfo->vret_arg_index = 1;
1030         } else {
1031                 /* this */
1032                 if (sig->hasthis)
1033                         add_general (&gr, &stack_size, cinfo->args + 0);
1034
1035                 if (cinfo->vtype_retaddr)
1036                         add_general (&gr, &stack_size, &cinfo->ret);
1037         }
1038
1039         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1040                 gr = PARAM_REGS;
1041                 fr = FLOAT_PARAM_REGS;
1042
1043                 /* Emit the signature cookie just before the implicit arguments */
1044                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1045         }
1046
1047         for (i = pstart; i < sig->param_count; ++i) {
1048                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1049                 MonoType *ptype;
1050
1051 #ifdef HOST_WIN32
1052                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1053                 if (gr > fr)
1054                         fr = gr;
1055                 else if (fr > gr)
1056                         gr = fr;
1057 #endif
1058
1059                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1060                         /* We allways pass the sig cookie on the stack for simplicity */
1061                         /*
1062                          * Prevent implicit arguments + the sig cookie from being passed
1063                          * in registers.
1064                          */
1065                         gr = PARAM_REGS;
1066                         fr = FLOAT_PARAM_REGS;
1067
1068                         /* Emit the signature cookie just before the implicit arguments */
1069                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1070                 }
1071
1072                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1073                 switch (ptype->type) {
1074                 case MONO_TYPE_BOOLEAN:
1075                 case MONO_TYPE_I1:
1076                 case MONO_TYPE_U1:
1077                         add_general (&gr, &stack_size, ainfo);
1078                         break;
1079                 case MONO_TYPE_I2:
1080                 case MONO_TYPE_U2:
1081                 case MONO_TYPE_CHAR:
1082                         add_general (&gr, &stack_size, ainfo);
1083                         break;
1084                 case MONO_TYPE_I4:
1085                 case MONO_TYPE_U4:
1086                         add_general (&gr, &stack_size, ainfo);
1087                         break;
1088                 case MONO_TYPE_I:
1089                 case MONO_TYPE_U:
1090                 case MONO_TYPE_PTR:
1091                 case MONO_TYPE_FNPTR:
1092                 case MONO_TYPE_CLASS:
1093                 case MONO_TYPE_OBJECT:
1094                 case MONO_TYPE_STRING:
1095                 case MONO_TYPE_SZARRAY:
1096                 case MONO_TYPE_ARRAY:
1097                         add_general (&gr, &stack_size, ainfo);
1098                         break;
1099                 case MONO_TYPE_GENERICINST:
1100                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1101                                 add_general (&gr, &stack_size, ainfo);
1102                                 break;
1103                         }
1104                         /* fall through */
1105                 case MONO_TYPE_VALUETYPE:
1106                 case MONO_TYPE_TYPEDBYREF:
1107                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1108                         break;
1109                 case MONO_TYPE_U8:
1110                 case MONO_TYPE_I8:
1111                         add_general (&gr, &stack_size, ainfo);
1112                         break;
1113                 case MONO_TYPE_R4:
1114                         add_float (&fr, &stack_size, ainfo, FALSE);
1115                         break;
1116                 case MONO_TYPE_R8:
1117                         add_float (&fr, &stack_size, ainfo, TRUE);
1118                         break;
1119                 default:
1120                         g_assert_not_reached ();
1121                 }
1122         }
1123
1124         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1125                 gr = PARAM_REGS;
1126                 fr = FLOAT_PARAM_REGS;
1127
1128                 /* Emit the signature cookie just before the implicit arguments */
1129                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1130         }
1131
1132 #ifdef HOST_WIN32
1133         // There always is 32 bytes reserved on the stack when calling on Winx64
1134         stack_size += 0x20;
1135 #endif
1136
1137 #ifndef MONO_AMD64_NO_PUSHES
1138         if (stack_size & 0x8) {
1139                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
1140                 cinfo->need_stack_align = TRUE;
1141                 stack_size += 8;
1142         }
1143 #endif
1144
1145         cinfo->stack_usage = stack_size;
1146         cinfo->reg_usage = gr;
1147         cinfo->freg_usage = fr;
1148         return cinfo;
1149 }
1150
1151 /*
1152  * mono_arch_get_argument_info:
1153  * @csig:  a method signature
1154  * @param_count: the number of parameters to consider
1155  * @arg_info: an array to store the result infos
1156  *
1157  * Gathers information on parameters such as size, alignment and
1158  * padding. arg_info should be large enought to hold param_count + 1 entries.
1159  *
1160  * Returns the size of the argument area on the stack.
1161  */
1162 int
1163 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1164 {
1165         int k;
1166         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1167         guint32 args_size = cinfo->stack_usage;
1168
1169         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1170         if (csig->hasthis) {
1171                 arg_info [0].offset = 0;
1172         }
1173
1174         for (k = 0; k < param_count; k++) {
1175                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1176                 /* FIXME: */
1177                 arg_info [k + 1].size = 0;
1178         }
1179
1180         g_free (cinfo);
1181
1182         return args_size;
1183 }
1184
1185 gboolean
1186 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1187 {
1188         CallInfo *c1, *c2;
1189         gboolean res;
1190         MonoType *callee_ret;
1191
1192         c1 = get_call_info (NULL, NULL, caller_sig);
1193         c2 = get_call_info (NULL, NULL, callee_sig);
1194         res = c1->stack_usage >= c2->stack_usage;
1195         callee_ret = mini_replace_type (callee_sig->ret);
1196         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1197                 /* An address on the callee's stack is passed as the first argument */
1198                 res = FALSE;
1199
1200         g_free (c1);
1201         g_free (c2);
1202
1203         return res;
1204 }
1205
1206 /*
1207  * Initialize the cpu to execute managed code.
1208  */
1209 void
1210 mono_arch_cpu_init (void)
1211 {
1212 #ifndef _MSC_VER
1213         guint16 fpcw;
1214
1215         /* spec compliance requires running with double precision */
1216         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1217         fpcw &= ~X86_FPCW_PRECC_MASK;
1218         fpcw |= X86_FPCW_PREC_DOUBLE;
1219         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1220         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1221 #else
1222         /* TODO: This is crashing on Win64 right now.
1223         * _control87 (_PC_53, MCW_PC);
1224         */
1225 #endif
1226 }
1227
1228 /*
1229  * Initialize architecture specific code.
1230  */
1231 void
1232 mono_arch_init (void)
1233 {
1234         int flags;
1235
1236         mono_mutex_init_recursive (&mini_arch_mutex);
1237 #if defined(__native_client_codegen__)
1238         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1239         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1240         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1241         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1242 #endif
1243
1244 #ifdef MONO_ARCH_NOMAP32BIT
1245         flags = MONO_MMAP_READ;
1246         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1247         breakpoint_size = 13;
1248         breakpoint_fault_size = 3;
1249 #else
1250         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1251         /* amd64_mov_reg_mem () */
1252         breakpoint_size = 8;
1253         breakpoint_fault_size = 8;
1254 #endif
1255
1256         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1257         single_step_fault_size = 4;
1258
1259         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1260         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1261         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1262
1263         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1264         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1265         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1266 }
1267
1268 /*
1269  * Cleanup architecture specific code.
1270  */
1271 void
1272 mono_arch_cleanup (void)
1273 {
1274         mono_mutex_destroy (&mini_arch_mutex);
1275 #if defined(__native_client_codegen__)
1276         mono_native_tls_free (nacl_instruction_depth);
1277         mono_native_tls_free (nacl_rex_tag);
1278         mono_native_tls_free (nacl_legacy_prefix_tag);
1279 #endif
1280 }
1281
1282 /*
1283  * This function returns the optimizations supported on this cpu.
1284  */
1285 guint32
1286 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1287 {
1288         guint32 opts = 0;
1289
1290         *exclude_mask = 0;
1291
1292         if (mono_hwcap_x86_has_cmov) {
1293                 opts |= MONO_OPT_CMOV;
1294
1295                 if (mono_hwcap_x86_has_fcmov)
1296                         opts |= MONO_OPT_FCMOV;
1297                 else
1298                         *exclude_mask |= MONO_OPT_FCMOV;
1299         } else {
1300                 *exclude_mask |= MONO_OPT_CMOV;
1301         }
1302
1303         return opts;
1304 }
1305
1306 /*
1307  * This function test for all SSE functions supported.
1308  *
1309  * Returns a bitmask corresponding to all supported versions.
1310  *
1311  */
1312 guint32
1313 mono_arch_cpu_enumerate_simd_versions (void)
1314 {
1315         guint32 sse_opts = 0;
1316
1317         if (mono_hwcap_x86_has_sse1)
1318                 sse_opts |= SIMD_VERSION_SSE1;
1319
1320         if (mono_hwcap_x86_has_sse2)
1321                 sse_opts |= SIMD_VERSION_SSE2;
1322
1323         if (mono_hwcap_x86_has_sse3)
1324                 sse_opts |= SIMD_VERSION_SSE3;
1325
1326         if (mono_hwcap_x86_has_ssse3)
1327                 sse_opts |= SIMD_VERSION_SSSE3;
1328
1329         if (mono_hwcap_x86_has_sse41)
1330                 sse_opts |= SIMD_VERSION_SSE41;
1331
1332         if (mono_hwcap_x86_has_sse42)
1333                 sse_opts |= SIMD_VERSION_SSE42;
1334
1335         if (mono_hwcap_x86_has_sse4a)
1336                 sse_opts |= SIMD_VERSION_SSE4a;
1337
1338         return sse_opts;
1339 }
1340
1341 #ifndef DISABLE_JIT
1342
1343 GList *
1344 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1345 {
1346         GList *vars = NULL;
1347         int i;
1348
1349         for (i = 0; i < cfg->num_varinfo; i++) {
1350                 MonoInst *ins = cfg->varinfo [i];
1351                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1352
1353                 /* unused vars */
1354                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1355                         continue;
1356
1357                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1358                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1359                         continue;
1360
1361                 if (mono_is_regsize_var (ins->inst_vtype)) {
1362                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1363                         g_assert (i == vmv->idx);
1364                         vars = g_list_prepend (vars, vmv);
1365                 }
1366         }
1367
1368         vars = mono_varlist_sort (cfg, vars, 0);
1369
1370         return vars;
1371 }
1372
1373 /**
1374  * mono_arch_compute_omit_fp:
1375  *
1376  *   Determine whenever the frame pointer can be eliminated.
1377  */
1378 static void
1379 mono_arch_compute_omit_fp (MonoCompile *cfg)
1380 {
1381         MonoMethodSignature *sig;
1382         MonoMethodHeader *header;
1383         int i, locals_size;
1384         CallInfo *cinfo;
1385
1386         if (cfg->arch.omit_fp_computed)
1387                 return;
1388
1389         header = cfg->header;
1390
1391         sig = mono_method_signature (cfg->method);
1392
1393         if (!cfg->arch.cinfo)
1394                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1395         cinfo = cfg->arch.cinfo;
1396
1397         /*
1398          * FIXME: Remove some of the restrictions.
1399          */
1400         cfg->arch.omit_fp = TRUE;
1401         cfg->arch.omit_fp_computed = TRUE;
1402
1403 #ifdef __native_client_codegen__
1404         /* NaCl modules may not change the value of RBP, so it cannot be */
1405         /* used as a normal register, but it can be used as a frame pointer*/
1406         cfg->disable_omit_fp = TRUE;
1407         cfg->arch.omit_fp = FALSE;
1408 #endif
1409
1410 #ifdef HOST_WIN32
1411         cfg->arch.omit_fp = FALSE;
1412 #endif
1413
1414         if (cfg->disable_omit_fp)
1415                 cfg->arch.omit_fp = FALSE;
1416
1417         if (!debug_omit_fp ())
1418                 cfg->arch.omit_fp = FALSE;
1419         /*
1420         if (cfg->method->save_lmf)
1421                 cfg->arch.omit_fp = FALSE;
1422         */
1423         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1424                 cfg->arch.omit_fp = FALSE;
1425         if (header->num_clauses)
1426                 cfg->arch.omit_fp = FALSE;
1427         if (cfg->param_area)
1428                 cfg->arch.omit_fp = FALSE;
1429         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1430                 cfg->arch.omit_fp = FALSE;
1431         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1432                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1433                 cfg->arch.omit_fp = FALSE;
1434         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1435                 ArgInfo *ainfo = &cinfo->args [i];
1436
1437                 if (ainfo->storage == ArgOnStack) {
1438                         /*
1439                          * The stack offset can only be determined when the frame
1440                          * size is known.
1441                          */
1442                         cfg->arch.omit_fp = FALSE;
1443                 }
1444         }
1445
1446         locals_size = 0;
1447         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1448                 MonoInst *ins = cfg->varinfo [i];
1449                 int ialign;
1450
1451                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1452         }
1453 }
1454
1455 GList *
1456 mono_arch_get_global_int_regs (MonoCompile *cfg)
1457 {
1458         GList *regs = NULL;
1459
1460         mono_arch_compute_omit_fp (cfg);
1461
1462         if (cfg->globalra) {
1463                 if (cfg->arch.omit_fp)
1464                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1465
1466                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1467                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1468                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1469                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1470 #ifndef __native_client_codegen__
1471                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1472 #endif
1473
1474                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1475                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1476                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1477                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1478                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1479                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1480                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1481                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1482         } else {
1483                 if (cfg->arch.omit_fp)
1484                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1485
1486                 /* We use the callee saved registers for global allocation */
1487                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1488                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1489                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1490                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1491 #ifndef __native_client_codegen__
1492                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1493 #endif
1494 #ifdef HOST_WIN32
1495                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1496                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1497 #endif
1498         }
1499
1500         return regs;
1501 }
1502
1503 GList*
1504 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1505 {
1506         GList *regs = NULL;
1507         int i;
1508
1509         /* All XMM registers */
1510         for (i = 0; i < 16; ++i)
1511                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1512
1513         return regs;
1514 }
1515
1516 GList*
1517 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1518 {
1519         static GList *r = NULL;
1520
1521         if (r == NULL) {
1522                 GList *regs = NULL;
1523
1524                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1526                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1527                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1529 #ifndef __native_client_codegen__
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1531 #endif
1532
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1534                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1536                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1537                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1538                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1539                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1540                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1541
1542                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1543         }
1544
1545         return r;
1546 }
1547
1548 GList*
1549 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1550 {
1551         int i;
1552         static GList *r = NULL;
1553
1554         if (r == NULL) {
1555                 GList *regs = NULL;
1556
1557                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1558                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1559
1560                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1561         }
1562
1563         return r;
1564 }
1565
1566 /*
1567  * mono_arch_regalloc_cost:
1568  *
1569  *  Return the cost, in number of memory references, of the action of
1570  * allocating the variable VMV into a register during global register
1571  * allocation.
1572  */
1573 guint32
1574 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1575 {
1576         MonoInst *ins = cfg->varinfo [vmv->idx];
1577
1578         if (cfg->method->save_lmf)
1579                 /* The register is already saved */
1580                 /* substract 1 for the invisible store in the prolog */
1581                 return (ins->opcode == OP_ARG) ? 0 : 1;
1582         else
1583                 /* push+pop */
1584                 return (ins->opcode == OP_ARG) ? 1 : 2;
1585 }
1586
1587 /*
1588  * mono_arch_fill_argument_info:
1589  *
1590  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1591  * of the method.
1592  */
1593 void
1594 mono_arch_fill_argument_info (MonoCompile *cfg)
1595 {
1596         MonoType *sig_ret;
1597         MonoMethodSignature *sig;
1598         MonoMethodHeader *header;
1599         MonoInst *ins;
1600         int i;
1601         CallInfo *cinfo;
1602
1603         header = cfg->header;
1604
1605         sig = mono_method_signature (cfg->method);
1606
1607         cinfo = cfg->arch.cinfo;
1608         sig_ret = mini_replace_type (sig->ret);
1609
1610         /*
1611          * Contrary to mono_arch_allocate_vars (), the information should describe
1612          * where the arguments are at the beginning of the method, not where they can be
1613          * accessed during the execution of the method. The later makes no sense for the
1614          * global register allocator, since a variable can be in more than one location.
1615          */
1616         if (sig_ret->type != MONO_TYPE_VOID) {
1617                 switch (cinfo->ret.storage) {
1618                 case ArgInIReg:
1619                 case ArgInFloatSSEReg:
1620                 case ArgInDoubleSSEReg:
1621                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1622                                 cfg->vret_addr->opcode = OP_REGVAR;
1623                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1624                         }
1625                         else {
1626                                 cfg->ret->opcode = OP_REGVAR;
1627                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1628                         }
1629                         break;
1630                 case ArgValuetypeInReg:
1631                         cfg->ret->opcode = OP_REGOFFSET;
1632                         cfg->ret->inst_basereg = -1;
1633                         cfg->ret->inst_offset = -1;
1634                         break;
1635                 default:
1636                         g_assert_not_reached ();
1637                 }
1638         }
1639
1640         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1641                 ArgInfo *ainfo = &cinfo->args [i];
1642                 MonoType *arg_type;
1643
1644                 ins = cfg->args [i];
1645
1646                 if (sig->hasthis && (i == 0))
1647                         arg_type = &mono_defaults.object_class->byval_arg;
1648                 else
1649                         arg_type = sig->params [i - sig->hasthis];
1650
1651                 switch (ainfo->storage) {
1652                 case ArgInIReg:
1653                 case ArgInFloatSSEReg:
1654                 case ArgInDoubleSSEReg:
1655                         ins->opcode = OP_REGVAR;
1656                         ins->inst_c0 = ainfo->reg;
1657                         break;
1658                 case ArgOnStack:
1659                         ins->opcode = OP_REGOFFSET;
1660                         ins->inst_basereg = -1;
1661                         ins->inst_offset = -1;
1662                         break;
1663                 case ArgValuetypeInReg:
1664                         /* Dummy */
1665                         ins->opcode = OP_NOP;
1666                         break;
1667                 default:
1668                         g_assert_not_reached ();
1669                 }
1670         }
1671 }
1672
1673 void
1674 mono_arch_allocate_vars (MonoCompile *cfg)
1675 {
1676         MonoType *sig_ret;
1677         MonoMethodSignature *sig;
1678         MonoMethodHeader *header;
1679         MonoInst *ins;
1680         int i, offset;
1681         guint32 locals_stack_size, locals_stack_align;
1682         gint32 *offsets;
1683         CallInfo *cinfo;
1684
1685         header = cfg->header;
1686
1687         sig = mono_method_signature (cfg->method);
1688
1689         cinfo = cfg->arch.cinfo;
1690         sig_ret = mini_replace_type (sig->ret);
1691
1692         mono_arch_compute_omit_fp (cfg);
1693
1694         /*
1695          * We use the ABI calling conventions for managed code as well.
1696          * Exception: valuetypes are only sometimes passed or returned in registers.
1697          */
1698
1699         /*
1700          * The stack looks like this:
1701          * <incoming arguments passed on the stack>
1702          * <return value>
1703          * <lmf/caller saved registers>
1704          * <locals>
1705          * <spill area>
1706          * <localloc area>  -> grows dynamically
1707          * <params area>
1708          */
1709
1710         if (cfg->arch.omit_fp) {
1711                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1712                 cfg->frame_reg = AMD64_RSP;
1713                 offset = 0;
1714         } else {
1715                 /* Locals are allocated backwards from %fp */
1716                 cfg->frame_reg = AMD64_RBP;
1717                 offset = 0;
1718         }
1719
1720         cfg->arch.saved_iregs = cfg->used_int_regs;
1721         if (cfg->method->save_lmf)
1722                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1723                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1724
1725         if (cfg->arch.omit_fp)
1726                 cfg->arch.reg_save_area_offset = offset;
1727         /* Reserve space for callee saved registers */
1728         for (i = 0; i < AMD64_NREG; ++i)
1729                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1730                         offset += sizeof(mgreg_t);
1731                 }
1732         if (!cfg->arch.omit_fp)
1733                 cfg->arch.reg_save_area_offset = -offset;
1734
1735         if (sig_ret->type != MONO_TYPE_VOID) {
1736                 switch (cinfo->ret.storage) {
1737                 case ArgInIReg:
1738                 case ArgInFloatSSEReg:
1739                 case ArgInDoubleSSEReg:
1740                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1741                                 if (cfg->globalra) {
1742                                         cfg->vret_addr->opcode = OP_REGVAR;
1743                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1744                                 } else {
1745                                         /* The register is volatile */
1746                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1747                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1748                                         if (cfg->arch.omit_fp) {
1749                                                 cfg->vret_addr->inst_offset = offset;
1750                                                 offset += 8;
1751                                         } else {
1752                                                 offset += 8;
1753                                                 cfg->vret_addr->inst_offset = -offset;
1754                                         }
1755                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1756                                                 printf ("vret_addr =");
1757                                                 mono_print_ins (cfg->vret_addr);
1758                                         }
1759                                 }
1760                         }
1761                         else {
1762                                 cfg->ret->opcode = OP_REGVAR;
1763                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1764                         }
1765                         break;
1766                 case ArgValuetypeInReg:
1767                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1768                         cfg->ret->opcode = OP_REGOFFSET;
1769                         cfg->ret->inst_basereg = cfg->frame_reg;
1770                         if (cfg->arch.omit_fp) {
1771                                 cfg->ret->inst_offset = offset;
1772                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1773                         } else {
1774                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1775                                 cfg->ret->inst_offset = - offset;
1776                         }
1777                         break;
1778                 default:
1779                         g_assert_not_reached ();
1780                 }
1781                 if (!cfg->globalra)
1782                         cfg->ret->dreg = cfg->ret->inst_c0;
1783         }
1784
1785         /* Allocate locals */
1786         if (!cfg->globalra) {
1787                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1788                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1789                         char *mname = mono_method_full_name (cfg->method, TRUE);
1790                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1791                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1792                         g_free (mname);
1793                         return;
1794                 }
1795
1796                 if (locals_stack_align) {
1797                         offset += (locals_stack_align - 1);
1798                         offset &= ~(locals_stack_align - 1);
1799                 }
1800                 if (cfg->arch.omit_fp) {
1801                         cfg->locals_min_stack_offset = offset;
1802                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1803                 } else {
1804                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1805                         cfg->locals_max_stack_offset = - offset;
1806                 }
1807
1808                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1809                         if (offsets [i] != -1) {
1810                                 MonoInst *ins = cfg->varinfo [i];
1811                                 ins->opcode = OP_REGOFFSET;
1812                                 ins->inst_basereg = cfg->frame_reg;
1813                                 if (cfg->arch.omit_fp)
1814                                         ins->inst_offset = (offset + offsets [i]);
1815                                 else
1816                                         ins->inst_offset = - (offset + offsets [i]);
1817                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1818                         }
1819                 }
1820                 offset += locals_stack_size;
1821         }
1822
1823         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1824                 g_assert (!cfg->arch.omit_fp);
1825                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1826                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1827         }
1828
1829         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1830                 ins = cfg->args [i];
1831                 if (ins->opcode != OP_REGVAR) {
1832                         ArgInfo *ainfo = &cinfo->args [i];
1833                         gboolean inreg = TRUE;
1834                         MonoType *arg_type;
1835
1836                         if (sig->hasthis && (i == 0))
1837                                 arg_type = &mono_defaults.object_class->byval_arg;
1838                         else
1839                                 arg_type = sig->params [i - sig->hasthis];
1840
1841                         if (cfg->globalra) {
1842                                 /* The new allocator needs info about the original locations of the arguments */
1843                                 switch (ainfo->storage) {
1844                                 case ArgInIReg:
1845                                 case ArgInFloatSSEReg:
1846                                 case ArgInDoubleSSEReg:
1847                                         ins->opcode = OP_REGVAR;
1848                                         ins->inst_c0 = ainfo->reg;
1849                                         break;
1850                                 case ArgOnStack:
1851                                         g_assert (!cfg->arch.omit_fp);
1852                                         ins->opcode = OP_REGOFFSET;
1853                                         ins->inst_basereg = cfg->frame_reg;
1854                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1855                                         break;
1856                                 case ArgValuetypeInReg:
1857                                         ins->opcode = OP_REGOFFSET;
1858                                         ins->inst_basereg = cfg->frame_reg;
1859                                         /* These arguments are saved to the stack in the prolog */
1860                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1861                                         if (cfg->arch.omit_fp) {
1862                                                 ins->inst_offset = offset;
1863                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1864                                         } else {
1865                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1866                                                 ins->inst_offset = - offset;
1867                                         }
1868                                         break;
1869                                 default:
1870                                         g_assert_not_reached ();
1871                                 }
1872
1873                                 continue;
1874                         }
1875
1876                         /* FIXME: Allocate volatile arguments to registers */
1877                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1878                                 inreg = FALSE;
1879
1880                         /*
1881                          * Under AMD64, all registers used to pass arguments to functions
1882                          * are volatile across calls.
1883                          * FIXME: Optimize this.
1884                          */
1885                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1886                                 inreg = FALSE;
1887
1888                         ins->opcode = OP_REGOFFSET;
1889
1890                         switch (ainfo->storage) {
1891                         case ArgInIReg:
1892                         case ArgInFloatSSEReg:
1893                         case ArgInDoubleSSEReg:
1894                                 if (inreg) {
1895                                         ins->opcode = OP_REGVAR;
1896                                         ins->dreg = ainfo->reg;
1897                                 }
1898                                 break;
1899                         case ArgOnStack:
1900                                 g_assert (!cfg->arch.omit_fp);
1901                                 ins->opcode = OP_REGOFFSET;
1902                                 ins->inst_basereg = cfg->frame_reg;
1903                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1904                                 break;
1905                         case ArgValuetypeInReg:
1906                                 break;
1907                         case ArgValuetypeAddrInIReg: {
1908                                 MonoInst *indir;
1909                                 g_assert (!cfg->arch.omit_fp);
1910
1911                                 MONO_INST_NEW (cfg, indir, 0);
1912                                 indir->opcode = OP_REGOFFSET;
1913                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1914                                         indir->inst_basereg = cfg->frame_reg;
1915                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1916                                         offset += (sizeof (gpointer));
1917                                         indir->inst_offset = - offset;
1918                                 }
1919                                 else {
1920                                         indir->inst_basereg = cfg->frame_reg;
1921                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1922                                 }
1923
1924                                 ins->opcode = OP_VTARG_ADDR;
1925                                 ins->inst_left = indir;
1926
1927                                 break;
1928                         }
1929                         default:
1930                                 NOT_IMPLEMENTED;
1931                         }
1932
1933                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1934                                 ins->opcode = OP_REGOFFSET;
1935                                 ins->inst_basereg = cfg->frame_reg;
1936                                 /* These arguments are saved to the stack in the prolog */
1937                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1938                                 if (cfg->arch.omit_fp) {
1939                                         ins->inst_offset = offset;
1940                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1941                                         // Arguments are yet supported by the stack map creation code
1942                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1943                                 } else {
1944                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1945                                         ins->inst_offset = - offset;
1946                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1947                                 }
1948                         }
1949                 }
1950         }
1951
1952         cfg->stack_offset = offset;
1953 }
1954
1955 void
1956 mono_arch_create_vars (MonoCompile *cfg)
1957 {
1958         MonoMethodSignature *sig;
1959         CallInfo *cinfo;
1960         MonoType *sig_ret;
1961
1962         sig = mono_method_signature (cfg->method);
1963
1964         if (!cfg->arch.cinfo)
1965                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1966         cinfo = cfg->arch.cinfo;
1967
1968         if (cinfo->ret.storage == ArgValuetypeInReg)
1969                 cfg->ret_var_is_local = TRUE;
1970
1971         sig_ret = mini_replace_type (sig->ret);
1972         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1973                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1974                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1975                         printf ("vret_addr = ");
1976                         mono_print_ins (cfg->vret_addr);
1977                 }
1978         }
1979
1980         if (cfg->gen_seq_points) {
1981                 MonoInst *ins;
1982
1983                 if (cfg->compile_aot) {
1984                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1985                         ins->flags |= MONO_INST_VOLATILE;
1986                         cfg->arch.seq_point_info_var = ins;
1987                 }
1988
1989             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1990                 ins->flags |= MONO_INST_VOLATILE;
1991                 cfg->arch.ss_trigger_page_var = ins;
1992         }
1993
1994 #ifdef MONO_AMD64_NO_PUSHES
1995         /*
1996          * When this is set, we pass arguments on the stack by moves, and by allocating
1997          * a bigger stack frame, instead of pushes.
1998          * Pushes complicate exception handling because the arguments on the stack have
1999          * to be popped each time a frame is unwound. They also make fp elimination
2000          * impossible.
2001          * FIXME: This doesn't work inside filter/finally clauses, since those execute
2002          * on a new frame which doesn't include a param area.
2003          */
2004         cfg->arch.no_pushes = TRUE;
2005 #endif
2006
2007         if (cfg->method->save_lmf)
2008                 cfg->create_lmf_var = TRUE;
2009
2010         if (cfg->method->save_lmf) {
2011                 cfg->lmf_ir = TRUE;
2012 #if !defined(HOST_WIN32)
2013                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2014                         cfg->lmf_ir_mono_lmf = TRUE;
2015 #endif
2016         }
2017
2018 #ifndef MONO_AMD64_NO_PUSHES
2019         cfg->arch_eh_jit_info = 1;
2020 #endif
2021 }
2022
2023 static void
2024 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2025 {
2026         MonoInst *ins;
2027
2028         switch (storage) {
2029         case ArgInIReg:
2030                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2031                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2032                 ins->sreg1 = tree->dreg;
2033                 MONO_ADD_INS (cfg->cbb, ins);
2034                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2035                 break;
2036         case ArgInFloatSSEReg:
2037                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2038                 ins->dreg = mono_alloc_freg (cfg);
2039                 ins->sreg1 = tree->dreg;
2040                 MONO_ADD_INS (cfg->cbb, ins);
2041
2042                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2043                 break;
2044         case ArgInDoubleSSEReg:
2045                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2046                 ins->dreg = mono_alloc_freg (cfg);
2047                 ins->sreg1 = tree->dreg;
2048                 MONO_ADD_INS (cfg->cbb, ins);
2049
2050                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2051
2052                 break;
2053         default:
2054                 g_assert_not_reached ();
2055         }
2056 }
2057
2058 static int
2059 arg_storage_to_load_membase (ArgStorage storage)
2060 {
2061         switch (storage) {
2062         case ArgInIReg:
2063 #if defined(__mono_ilp32__)
2064                 return OP_LOADI8_MEMBASE;
2065 #else
2066                 return OP_LOAD_MEMBASE;
2067 #endif
2068         case ArgInDoubleSSEReg:
2069                 return OP_LOADR8_MEMBASE;
2070         case ArgInFloatSSEReg:
2071                 return OP_LOADR4_MEMBASE;
2072         default:
2073                 g_assert_not_reached ();
2074         }
2075
2076         return -1;
2077 }
2078
2079 static void
2080 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2081 {
2082         MonoInst *arg;
2083         MonoMethodSignature *tmp_sig;
2084         int sig_reg;
2085
2086         if (call->tail_call)
2087                 NOT_IMPLEMENTED;
2088
2089         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2090
2091         /*
2092          * mono_ArgIterator_Setup assumes the signature cookie is
2093          * passed first and all the arguments which were before it are
2094          * passed on the stack after the signature. So compensate by
2095          * passing a different signature.
2096          */
2097         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2098         tmp_sig->param_count -= call->signature->sentinelpos;
2099         tmp_sig->sentinelpos = 0;
2100         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2101
2102         sig_reg = mono_alloc_ireg (cfg);
2103         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2104
2105         if (cfg->arch.no_pushes) {
2106                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2107         } else {
2108                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2109                 arg->sreg1 = sig_reg;
2110                 MONO_ADD_INS (cfg->cbb, arg);
2111         }
2112 }
2113
2114 static inline LLVMArgStorage
2115 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2116 {
2117         switch (storage) {
2118         case ArgInIReg:
2119                 return LLVMArgInIReg;
2120         case ArgNone:
2121                 return LLVMArgNone;
2122         default:
2123                 g_assert_not_reached ();
2124                 return LLVMArgNone;
2125         }
2126 }
2127
2128 #ifdef ENABLE_LLVM
2129 LLVMCallInfo*
2130 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2131 {
2132         int i, n;
2133         CallInfo *cinfo;
2134         ArgInfo *ainfo;
2135         int j;
2136         LLVMCallInfo *linfo;
2137         MonoType *t, *sig_ret;
2138
2139         n = sig->param_count + sig->hasthis;
2140         sig_ret = mini_replace_type (sig->ret);
2141
2142         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2143
2144         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2145
2146         /*
2147          * LLVM always uses the native ABI while we use our own ABI, the
2148          * only difference is the handling of vtypes:
2149          * - we only pass/receive them in registers in some cases, and only
2150          *   in 1 or 2 integer registers.
2151          */
2152         if (cinfo->ret.storage == ArgValuetypeInReg) {
2153                 if (sig->pinvoke) {
2154                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2155                         cfg->disable_llvm = TRUE;
2156                         return linfo;
2157                 }
2158
2159                 linfo->ret.storage = LLVMArgVtypeInReg;
2160                 for (j = 0; j < 2; ++j)
2161                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2162         }
2163
2164         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2165                 /* Vtype returned using a hidden argument */
2166                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2167                 linfo->vret_arg_index = cinfo->vret_arg_index;
2168         }
2169
2170         for (i = 0; i < n; ++i) {
2171                 ainfo = cinfo->args + i;
2172
2173                 if (i >= sig->hasthis)
2174                         t = sig->params [i - sig->hasthis];
2175                 else
2176                         t = &mono_defaults.int_class->byval_arg;
2177
2178                 linfo->args [i].storage = LLVMArgNone;
2179
2180                 switch (ainfo->storage) {
2181                 case ArgInIReg:
2182                         linfo->args [i].storage = LLVMArgInIReg;
2183                         break;
2184                 case ArgInDoubleSSEReg:
2185                 case ArgInFloatSSEReg:
2186                         linfo->args [i].storage = LLVMArgInFPReg;
2187                         break;
2188                 case ArgOnStack:
2189                         if (MONO_TYPE_ISSTRUCT (t)) {
2190                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2191                         } else {
2192                                 linfo->args [i].storage = LLVMArgInIReg;
2193                                 if (!t->byref) {
2194                                         if (t->type == MONO_TYPE_R4)
2195                                                 linfo->args [i].storage = LLVMArgInFPReg;
2196                                         else if (t->type == MONO_TYPE_R8)
2197                                                 linfo->args [i].storage = LLVMArgInFPReg;
2198                                 }
2199                         }
2200                         break;
2201                 case ArgValuetypeInReg:
2202                         if (sig->pinvoke) {
2203                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2204                                 cfg->disable_llvm = TRUE;
2205                                 return linfo;
2206                         }
2207
2208                         linfo->args [i].storage = LLVMArgVtypeInReg;
2209                         for (j = 0; j < 2; ++j)
2210                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2211                         break;
2212                 default:
2213                         cfg->exception_message = g_strdup ("ainfo->storage");
2214                         cfg->disable_llvm = TRUE;
2215                         break;
2216                 }
2217         }
2218
2219         return linfo;
2220 }
2221 #endif
2222
2223 void
2224 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2225 {
2226         MonoInst *arg, *in;
2227         MonoMethodSignature *sig;
2228         MonoType *sig_ret;
2229         int i, n, stack_size;
2230         CallInfo *cinfo;
2231         ArgInfo *ainfo;
2232
2233         stack_size = 0;
2234
2235         sig = call->signature;
2236         n = sig->param_count + sig->hasthis;
2237
2238         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2239
2240         sig_ret = sig->ret;
2241
2242         if (COMPILE_LLVM (cfg)) {
2243                 /* We shouldn't be called in the llvm case */
2244                 cfg->disable_llvm = TRUE;
2245                 return;
2246         }
2247
2248         if (cinfo->need_stack_align) {
2249                 if (!cfg->arch.no_pushes)
2250                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2251         }
2252
2253         /*
2254          * Emit all arguments which are passed on the stack to prevent register
2255          * allocation problems.
2256          */
2257         if (cfg->arch.no_pushes) {
2258                 for (i = 0; i < n; ++i) {
2259                         MonoType *t;
2260                         ainfo = cinfo->args + i;
2261
2262                         in = call->args [i];
2263
2264                         if (sig->hasthis && i == 0)
2265                                 t = &mono_defaults.object_class->byval_arg;
2266                         else
2267                                 t = sig->params [i - sig->hasthis];
2268
2269                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2270                                 if (!t->byref) {
2271                                         if (t->type == MONO_TYPE_R4)
2272                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2273                                         else if (t->type == MONO_TYPE_R8)
2274                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2275                                         else
2276                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2277                                 } else {
2278                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2279                                 }
2280                                 if (cfg->compute_gc_maps) {
2281                                         MonoInst *def;
2282
2283                                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2284                                 }
2285                         }
2286                 }
2287         }
2288
2289         /*
2290          * Emit all parameters passed in registers in non-reverse order for better readability
2291          * and to help the optimization in emit_prolog ().
2292          */
2293         for (i = 0; i < n; ++i) {
2294                 ainfo = cinfo->args + i;
2295
2296                 in = call->args [i];
2297
2298                 if (ainfo->storage == ArgInIReg)
2299                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2300         }
2301
2302         for (i = n - 1; i >= 0; --i) {
2303                 ainfo = cinfo->args + i;
2304
2305                 in = call->args [i];
2306
2307                 switch (ainfo->storage) {
2308                 case ArgInIReg:
2309                         /* Already done */
2310                         break;
2311                 case ArgInFloatSSEReg:
2312                 case ArgInDoubleSSEReg:
2313                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2314                         break;
2315                 case ArgOnStack:
2316                 case ArgValuetypeInReg:
2317                 case ArgValuetypeAddrInIReg:
2318                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2319                                 MonoInst *call_inst = (MonoInst*)call;
2320                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2321                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2322                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2323                                 guint32 align;
2324                                 guint32 size;
2325
2326                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2327                                         size = sizeof (MonoTypedRef);
2328                                         align = sizeof (gpointer);
2329                                 }
2330                                 else {
2331                                         if (sig->pinvoke)
2332                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2333                                         else {
2334                                                 /*
2335                                                  * Other backends use mono_type_stack_size (), but that
2336                                                  * aligns the size to 8, which is larger than the size of
2337                                                  * the source, leading to reads of invalid memory if the
2338                                                  * source is at the end of address space.
2339                                                  */
2340                                                 size = mono_class_value_size (in->klass, &align);
2341                                         }
2342                                 }
2343                                 g_assert (in->klass);
2344
2345                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2346                                         /* Avoid asserts in emit_memcpy () */
2347                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2348                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2349                                         /* Continue normally */
2350                                 }
2351
2352                                 if (size > 0) {
2353                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2354                                         arg->sreg1 = in->dreg;
2355                                         arg->klass = in->klass;
2356                                         arg->backend.size = size;
2357                                         arg->inst_p0 = call;
2358                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2359                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2360
2361                                         MONO_ADD_INS (cfg->cbb, arg);
2362                                 }
2363                         } else {
2364                                 if (cfg->arch.no_pushes) {
2365                                         /* Already done */
2366                                 } else {
2367                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2368                                         arg->sreg1 = in->dreg;
2369                                         if (!sig->params [i - sig->hasthis]->byref) {
2370                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2371                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2372                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2373                                                         arg->inst_destbasereg = X86_ESP;
2374                                                         arg->inst_offset = 0;
2375                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2376                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2377                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2378                                                         arg->inst_destbasereg = X86_ESP;
2379                                                         arg->inst_offset = 0;
2380                                                 }
2381                                         }
2382                                         MONO_ADD_INS (cfg->cbb, arg);
2383                                 }
2384                         }
2385                         break;
2386                 default:
2387                         g_assert_not_reached ();
2388                 }
2389
2390                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2391                         /* Emit the signature cookie just before the implicit arguments */
2392                         emit_sig_cookie (cfg, call, cinfo);
2393         }
2394
2395         /* Handle the case where there are no implicit arguments */
2396         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2397                 emit_sig_cookie (cfg, call, cinfo);
2398
2399         sig_ret = mini_replace_type (sig->ret);
2400         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2401                 MonoInst *vtarg;
2402
2403                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2404                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2405                                 /*
2406                                  * Tell the JIT to use a more efficient calling convention: call using
2407                                  * OP_CALL, compute the result location after the call, and save the
2408                                  * result there.
2409                                  */
2410                                 call->vret_in_reg = TRUE;
2411                                 /*
2412                                  * Nullify the instruction computing the vret addr to enable
2413                                  * future optimizations.
2414                                  */
2415                                 if (call->vret_var)
2416                                         NULLIFY_INS (call->vret_var);
2417                         } else {
2418                                 if (call->tail_call)
2419                                         NOT_IMPLEMENTED;
2420                                 /*
2421                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2422                                  * the stack. Push the address here, so the call instruction can
2423                                  * access it.
2424                                  */
2425                                 if (!cfg->arch.vret_addr_loc) {
2426                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2427                                         /* Prevent it from being register allocated or optimized away */
2428                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2429                                 }
2430
2431                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2432                         }
2433                 }
2434                 else {
2435                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2436                         vtarg->sreg1 = call->vret_var->dreg;
2437                         vtarg->dreg = mono_alloc_preg (cfg);
2438                         MONO_ADD_INS (cfg->cbb, vtarg);
2439
2440                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2441                 }
2442         }
2443
2444 #ifdef HOST_WIN32
2445         if (call->inst.opcode != OP_TAILCALL) {
2446                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2447         }
2448 #endif
2449
2450         if (cfg->method->save_lmf) {
2451                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2452                 MONO_ADD_INS (cfg->cbb, arg);
2453         }
2454
2455         call->stack_usage = cinfo->stack_usage;
2456 }
2457
2458 void
2459 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2460 {
2461         MonoInst *arg;
2462         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2463         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2464         int size = ins->backend.size;
2465
2466         if (ainfo->storage == ArgValuetypeInReg) {
2467                 MonoInst *load;
2468                 int part;
2469
2470                 for (part = 0; part < 2; ++part) {
2471                         if (ainfo->pair_storage [part] == ArgNone)
2472                                 continue;
2473
2474                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2475                         load->inst_basereg = src->dreg;
2476                         load->inst_offset = part * sizeof(mgreg_t);
2477
2478                         switch (ainfo->pair_storage [part]) {
2479                         case ArgInIReg:
2480                                 load->dreg = mono_alloc_ireg (cfg);
2481                                 break;
2482                         case ArgInDoubleSSEReg:
2483                         case ArgInFloatSSEReg:
2484                                 load->dreg = mono_alloc_freg (cfg);
2485                                 break;
2486                         default:
2487                                 g_assert_not_reached ();
2488                         }
2489                         MONO_ADD_INS (cfg->cbb, load);
2490
2491                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2492                 }
2493         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2494                 MonoInst *vtaddr, *load;
2495                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2496
2497                 g_assert (!cfg->arch.no_pushes);
2498
2499                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2500                 cfg->has_indirection = TRUE;
2501                 load->inst_p0 = vtaddr;
2502                 vtaddr->flags |= MONO_INST_INDIRECT;
2503                 load->type = STACK_MP;
2504                 load->klass = vtaddr->klass;
2505                 load->dreg = mono_alloc_ireg (cfg);
2506                 MONO_ADD_INS (cfg->cbb, load);
2507                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2508
2509                 if (ainfo->pair_storage [0] == ArgInIReg) {
2510                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2511                         arg->dreg = mono_alloc_ireg (cfg);
2512                         arg->sreg1 = load->dreg;
2513                         arg->inst_imm = 0;
2514                         MONO_ADD_INS (cfg->cbb, arg);
2515                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2516                 } else {
2517                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2518                         arg->sreg1 = load->dreg;
2519                         MONO_ADD_INS (cfg->cbb, arg);
2520                 }
2521         } else {
2522                 if (size == 8) {
2523                         if (cfg->arch.no_pushes) {
2524                                 int dreg = mono_alloc_ireg (cfg);
2525
2526                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2527                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2528                         } else {
2529                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2530                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2531                                 arg->inst_basereg = src->dreg;
2532                                 arg->inst_offset = 0;
2533                                 MONO_ADD_INS (cfg->cbb, arg);
2534                         }
2535                 } else if (size <= 40) {
2536                         if (cfg->arch.no_pushes) {
2537                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2538                         } else {
2539                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2540                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2541                         }
2542                 } else {
2543                         if (cfg->arch.no_pushes) {
2544                                 // FIXME: Code growth
2545                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2546                         } else {
2547                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2548                                 arg->inst_basereg = src->dreg;
2549                                 arg->inst_offset = 0;
2550                                 arg->inst_imm = size;
2551                                 MONO_ADD_INS (cfg->cbb, arg);
2552                         }
2553                 }
2554
2555                 if (cfg->compute_gc_maps) {
2556                         MonoInst *def;
2557                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2558                 }
2559         }
2560 }
2561
2562 void
2563 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2564 {
2565         MonoType *ret = mini_replace_type (mono_method_signature (method)->ret);
2566
2567         if (ret->type == MONO_TYPE_R4) {
2568                 if (COMPILE_LLVM (cfg))
2569                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2570                 else
2571                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2572                 return;
2573         } else if (ret->type == MONO_TYPE_R8) {
2574                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2575                 return;
2576         }
2577
2578         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2579 }
2580
2581 #endif /* DISABLE_JIT */
2582
2583 #define EMIT_COND_BRANCH(ins,cond,sign) \
2584         if (ins->inst_true_bb->native_offset) { \
2585                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2586         } else { \
2587                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2588                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2589             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2590                         x86_branch8 (code, cond, 0, sign); \
2591                 else \
2592                         x86_branch32 (code, cond, 0, sign); \
2593 }
2594
2595 typedef struct {
2596         MonoMethodSignature *sig;
2597         CallInfo *cinfo;
2598 } ArchDynCallInfo;
2599
2600 static gboolean
2601 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2602 {
2603         int i;
2604
2605 #ifdef HOST_WIN32
2606         return FALSE;
2607 #endif
2608
2609         switch (cinfo->ret.storage) {
2610         case ArgNone:
2611         case ArgInIReg:
2612                 break;
2613         case ArgValuetypeInReg: {
2614                 ArgInfo *ainfo = &cinfo->ret;
2615
2616                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2617                         return FALSE;
2618                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2619                         return FALSE;
2620                 break;
2621         }
2622         default:
2623                 return FALSE;
2624         }
2625
2626         for (i = 0; i < cinfo->nargs; ++i) {
2627                 ArgInfo *ainfo = &cinfo->args [i];
2628                 switch (ainfo->storage) {
2629                 case ArgInIReg:
2630                         break;
2631                 case ArgValuetypeInReg:
2632                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2633                                 return FALSE;
2634                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2635                                 return FALSE;
2636                         break;
2637                 default:
2638                         return FALSE;
2639                 }
2640         }
2641
2642         return TRUE;
2643 }
2644
2645 /*
2646  * mono_arch_dyn_call_prepare:
2647  *
2648  *   Return a pointer to an arch-specific structure which contains information
2649  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2650  * supported for SIG.
2651  * This function is equivalent to ffi_prep_cif in libffi.
2652  */
2653 MonoDynCallInfo*
2654 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2655 {
2656         ArchDynCallInfo *info;
2657         CallInfo *cinfo;
2658
2659         cinfo = get_call_info (NULL, NULL, sig);
2660
2661         if (!dyn_call_supported (sig, cinfo)) {
2662                 g_free (cinfo);
2663                 return NULL;
2664         }
2665
2666         info = g_new0 (ArchDynCallInfo, 1);
2667         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2668         info->sig = sig;
2669         info->cinfo = cinfo;
2670
2671         return (MonoDynCallInfo*)info;
2672 }
2673
2674 /*
2675  * mono_arch_dyn_call_free:
2676  *
2677  *   Free a MonoDynCallInfo structure.
2678  */
2679 void
2680 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2681 {
2682         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2683
2684         g_free (ainfo->cinfo);
2685         g_free (ainfo);
2686 }
2687
2688 #if !defined(__native_client__)
2689 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2690 #define GREG_TO_PTR(greg) (gpointer)(greg)
2691 #else
2692 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2693 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2694 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2695 #endif
2696
2697 /*
2698  * mono_arch_get_start_dyn_call:
2699  *
2700  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2701  * store the result into BUF.
2702  * ARGS should be an array of pointers pointing to the arguments.
2703  * RET should point to a memory buffer large enought to hold the result of the
2704  * call.
2705  * This function should be as fast as possible, any work which does not depend
2706  * on the actual values of the arguments should be done in
2707  * mono_arch_dyn_call_prepare ().
2708  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2709  * libffi.
2710  */
2711 void
2712 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2713 {
2714         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2715         DynCallArgs *p = (DynCallArgs*)buf;
2716         int arg_index, greg, i, pindex;
2717         MonoMethodSignature *sig = dinfo->sig;
2718
2719         g_assert (buf_len >= sizeof (DynCallArgs));
2720
2721         p->res = 0;
2722         p->ret = ret;
2723
2724         arg_index = 0;
2725         greg = 0;
2726         pindex = 0;
2727
2728         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2729                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2730                 if (!sig->hasthis)
2731                         pindex = 1;
2732         }
2733
2734         if (dinfo->cinfo->vtype_retaddr)
2735                 p->regs [greg ++] = PTR_TO_GREG(ret);
2736
2737         for (i = pindex; i < sig->param_count; i++) {
2738                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2739                 gpointer *arg = args [arg_index ++];
2740
2741                 if (t->byref) {
2742                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2743                         continue;
2744                 }
2745
2746                 switch (t->type) {
2747                 case MONO_TYPE_STRING:
2748                 case MONO_TYPE_CLASS:
2749                 case MONO_TYPE_ARRAY:
2750                 case MONO_TYPE_SZARRAY:
2751                 case MONO_TYPE_OBJECT:
2752                 case MONO_TYPE_PTR:
2753                 case MONO_TYPE_I:
2754                 case MONO_TYPE_U:
2755 #if !defined(__mono_ilp32__)
2756                 case MONO_TYPE_I8:
2757                 case MONO_TYPE_U8:
2758 #endif
2759                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2760                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2761                         break;
2762 #if defined(__mono_ilp32__)
2763                 case MONO_TYPE_I8:
2764                 case MONO_TYPE_U8:
2765                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2766                         p->regs [greg ++] = *(guint64*)(arg);
2767                         break;
2768 #endif
2769                 case MONO_TYPE_BOOLEAN:
2770                 case MONO_TYPE_U1:
2771                         p->regs [greg ++] = *(guint8*)(arg);
2772                         break;
2773                 case MONO_TYPE_I1:
2774                         p->regs [greg ++] = *(gint8*)(arg);
2775                         break;
2776                 case MONO_TYPE_I2:
2777                         p->regs [greg ++] = *(gint16*)(arg);
2778                         break;
2779                 case MONO_TYPE_U2:
2780                 case MONO_TYPE_CHAR:
2781                         p->regs [greg ++] = *(guint16*)(arg);
2782                         break;
2783                 case MONO_TYPE_I4:
2784                         p->regs [greg ++] = *(gint32*)(arg);
2785                         break;
2786                 case MONO_TYPE_U4:
2787                         p->regs [greg ++] = *(guint32*)(arg);
2788                         break;
2789                 case MONO_TYPE_GENERICINST:
2790                     if (MONO_TYPE_IS_REFERENCE (t)) {
2791                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2792                                 break;
2793                         } else {
2794                                 /* Fall through */
2795                         }
2796                 case MONO_TYPE_VALUETYPE: {
2797                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2798
2799                         g_assert (ainfo->storage == ArgValuetypeInReg);
2800                         if (ainfo->pair_storage [0] != ArgNone) {
2801                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2802                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2803                         }
2804                         if (ainfo->pair_storage [1] != ArgNone) {
2805                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2806                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2807                         }
2808                         break;
2809                 }
2810                 default:
2811                         g_assert_not_reached ();
2812                 }
2813         }
2814
2815         g_assert (greg <= PARAM_REGS);
2816 }
2817
2818 /*
2819  * mono_arch_finish_dyn_call:
2820  *
2821  *   Store the result of a dyn call into the return value buffer passed to
2822  * start_dyn_call ().
2823  * This function should be as fast as possible, any work which does not depend
2824  * on the actual values of the arguments should be done in
2825  * mono_arch_dyn_call_prepare ().
2826  */
2827 void
2828 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2829 {
2830         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2831         MonoMethodSignature *sig = dinfo->sig;
2832         guint8 *ret = ((DynCallArgs*)buf)->ret;
2833         mgreg_t res = ((DynCallArgs*)buf)->res;
2834         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2835
2836         switch (sig_ret->type) {
2837         case MONO_TYPE_VOID:
2838                 *(gpointer*)ret = NULL;
2839                 break;
2840         case MONO_TYPE_STRING:
2841         case MONO_TYPE_CLASS:
2842         case MONO_TYPE_ARRAY:
2843         case MONO_TYPE_SZARRAY:
2844         case MONO_TYPE_OBJECT:
2845         case MONO_TYPE_I:
2846         case MONO_TYPE_U:
2847         case MONO_TYPE_PTR:
2848                 *(gpointer*)ret = GREG_TO_PTR(res);
2849                 break;
2850         case MONO_TYPE_I1:
2851                 *(gint8*)ret = res;
2852                 break;
2853         case MONO_TYPE_U1:
2854         case MONO_TYPE_BOOLEAN:
2855                 *(guint8*)ret = res;
2856                 break;
2857         case MONO_TYPE_I2:
2858                 *(gint16*)ret = res;
2859                 break;
2860         case MONO_TYPE_U2:
2861         case MONO_TYPE_CHAR:
2862                 *(guint16*)ret = res;
2863                 break;
2864         case MONO_TYPE_I4:
2865                 *(gint32*)ret = res;
2866                 break;
2867         case MONO_TYPE_U4:
2868                 *(guint32*)ret = res;
2869                 break;
2870         case MONO_TYPE_I8:
2871                 *(gint64*)ret = res;
2872                 break;
2873         case MONO_TYPE_U8:
2874                 *(guint64*)ret = res;
2875                 break;
2876         case MONO_TYPE_GENERICINST:
2877                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2878                         *(gpointer*)ret = GREG_TO_PTR(res);
2879                         break;
2880                 } else {
2881                         /* Fall through */
2882                 }
2883         case MONO_TYPE_VALUETYPE:
2884                 if (dinfo->cinfo->vtype_retaddr) {
2885                         /* Nothing to do */
2886                 } else {
2887                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2888
2889                         g_assert (ainfo->storage == ArgValuetypeInReg);
2890
2891                         if (ainfo->pair_storage [0] != ArgNone) {
2892                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2893                                 ((mgreg_t*)ret)[0] = res;
2894                         }
2895
2896                         g_assert (ainfo->pair_storage [1] == ArgNone);
2897                 }
2898                 break;
2899         default:
2900                 g_assert_not_reached ();
2901         }
2902 }
2903
2904 /* emit an exception if condition is fail */
2905 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2906         do {                                                        \
2907                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2908                 if (tins == NULL) {                                                                             \
2909                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2910                                         MONO_PATCH_INFO_EXC, exc_name);  \
2911                         x86_branch32 (code, cond, 0, signed);               \
2912                 } else {        \
2913                         EMIT_COND_BRANCH (tins, cond, signed);  \
2914                 }                       \
2915         } while (0);
2916
2917 #define EMIT_FPCOMPARE(code) do { \
2918         amd64_fcompp (code); \
2919         amd64_fnstsw (code); \
2920 } while (0);
2921
2922 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2923     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2924         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2925         amd64_ ##op (code); \
2926         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2927         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2928 } while (0);
2929
2930 static guint8*
2931 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2932 {
2933         gboolean no_patch = FALSE;
2934
2935         /*
2936          * FIXME: Add support for thunks
2937          */
2938         {
2939                 gboolean near_call = FALSE;
2940
2941                 /*
2942                  * Indirect calls are expensive so try to make a near call if possible.
2943                  * The caller memory is allocated by the code manager so it is
2944                  * guaranteed to be at a 32 bit offset.
2945                  */
2946
2947                 if (patch_type != MONO_PATCH_INFO_ABS) {
2948                         /* The target is in memory allocated using the code manager */
2949                         near_call = TRUE;
2950
2951                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2952                                 if (((MonoMethod*)data)->klass->image->aot_module)
2953                                         /* The callee might be an AOT method */
2954                                         near_call = FALSE;
2955                                 if (((MonoMethod*)data)->dynamic)
2956                                         /* The target is in malloc-ed memory */
2957                                         near_call = FALSE;
2958                         }
2959
2960                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2961                                 /*
2962                                  * The call might go directly to a native function without
2963                                  * the wrapper.
2964                                  */
2965                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2966                                 if (mi) {
2967                                         gconstpointer target = mono_icall_get_wrapper (mi);
2968                                         if ((((guint64)target) >> 32) != 0)
2969                                                 near_call = FALSE;
2970                                 }
2971                         }
2972                 }
2973                 else {
2974                         MonoJumpInfo *jinfo = NULL;
2975
2976                         if (cfg->abs_patches)
2977                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2978                         if (jinfo) {
2979                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2980                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2981                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2982                                                 near_call = TRUE;
2983                                         no_patch = TRUE;
2984                                 } else {
2985                                         /*
2986                                          * This is not really an optimization, but required because the
2987                                          * generic class init trampolines use R11 to pass the vtable.
2988                                          */
2989                                         near_call = TRUE;
2990                                 }
2991                         } else {
2992                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2993                                 if (info) {
2994                                         if (info->func == info->wrapper) {
2995                                                 /* No wrapper */
2996                                                 if ((((guint64)info->func) >> 32) == 0)
2997                                                         near_call = TRUE;
2998                                         }
2999                                         else {
3000                                                 /* See the comment in mono_codegen () */
3001                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3002                                                         near_call = TRUE;
3003                                         }
3004                                 }
3005                                 else if ((((guint64)data) >> 32) == 0) {
3006                                         near_call = TRUE;
3007                                         no_patch = TRUE;
3008                                 }
3009                         }
3010                 }
3011
3012                 if (cfg->method->dynamic)
3013                         /* These methods are allocated using malloc */
3014                         near_call = FALSE;
3015
3016 #ifdef MONO_ARCH_NOMAP32BIT
3017                 near_call = FALSE;
3018 #endif
3019 #if defined(__native_client__)
3020                 /* Always use near_call == TRUE for Native Client */
3021                 near_call = TRUE;
3022 #endif
3023                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3024                 if (optimize_for_xen)
3025                         near_call = FALSE;
3026
3027                 if (cfg->compile_aot) {
3028                         near_call = TRUE;
3029                         no_patch = TRUE;
3030                 }
3031
3032                 if (near_call) {
3033                         /*
3034                          * Align the call displacement to an address divisible by 4 so it does
3035                          * not span cache lines. This is required for code patching to work on SMP
3036                          * systems.
3037                          */
3038                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3039                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3040                                 amd64_padding (code, pad_size);
3041                         }
3042                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3043                         amd64_call_code (code, 0);
3044                 }
3045                 else {
3046                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3047                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3048                         amd64_call_reg (code, GP_SCRATCH_REG);
3049                 }
3050         }
3051
3052         return code;
3053 }
3054
3055 static inline guint8*
3056 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3057 {
3058 #ifdef HOST_WIN32
3059         if (win64_adjust_stack)
3060                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3061 #endif
3062         code = emit_call_body (cfg, code, patch_type, data);
3063 #ifdef HOST_WIN32
3064         if (win64_adjust_stack)
3065                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3066 #endif
3067
3068         return code;
3069 }
3070
3071 static inline int
3072 store_membase_imm_to_store_membase_reg (int opcode)
3073 {
3074         switch (opcode) {
3075         case OP_STORE_MEMBASE_IMM:
3076                 return OP_STORE_MEMBASE_REG;
3077         case OP_STOREI4_MEMBASE_IMM:
3078                 return OP_STOREI4_MEMBASE_REG;
3079         case OP_STOREI8_MEMBASE_IMM:
3080                 return OP_STOREI8_MEMBASE_REG;
3081         }
3082
3083         return -1;
3084 }
3085
3086 #ifndef DISABLE_JIT
3087
3088 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3089
3090 /*
3091  * mono_arch_peephole_pass_1:
3092  *
3093  *   Perform peephole opts which should/can be performed before local regalloc
3094  */
3095 void
3096 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3097 {
3098         MonoInst *ins, *n;
3099
3100         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3101                 MonoInst *last_ins = ins->prev;
3102
3103                 switch (ins->opcode) {
3104                 case OP_ADD_IMM:
3105                 case OP_IADD_IMM:
3106                 case OP_LADD_IMM:
3107                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3108                                 /*
3109                                  * X86_LEA is like ADD, but doesn't have the
3110                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3111                                  * its operand to 64 bit.
3112                                  */
3113                                 ins->opcode = OP_X86_LEA_MEMBASE;
3114                                 ins->inst_basereg = ins->sreg1;
3115                         }
3116                         break;
3117                 case OP_LXOR:
3118                 case OP_IXOR:
3119                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3120                                 MonoInst *ins2;
3121
3122                                 /*
3123                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3124                                  * the latter has length 2-3 instead of 6 (reverse constant
3125                                  * propagation). These instruction sequences are very common
3126                                  * in the initlocals bblock.
3127                                  */
3128                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3129                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3130                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3131                                                 ins2->sreg1 = ins->dreg;
3132                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3133                                                 /* Continue */
3134                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3135                                                 NULLIFY_INS (ins2);
3136                                                 /* Continue */
3137                                         } else {
3138                                                 break;
3139                                         }
3140                                 }
3141                         }
3142                         break;
3143                 case OP_COMPARE_IMM:
3144                 case OP_LCOMPARE_IMM:
3145                         /* OP_COMPARE_IMM (reg, 0)
3146                          * -->
3147                          * OP_AMD64_TEST_NULL (reg)
3148                          */
3149                         if (!ins->inst_imm)
3150                                 ins->opcode = OP_AMD64_TEST_NULL;
3151                         break;
3152                 case OP_ICOMPARE_IMM:
3153                         if (!ins->inst_imm)
3154                                 ins->opcode = OP_X86_TEST_NULL;
3155                         break;
3156                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3157                         /*
3158                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3159                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3160                          * -->
3161                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3162                          * OP_COMPARE_IMM reg, imm
3163                          *
3164                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3165                          */
3166                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3167                             ins->inst_basereg == last_ins->inst_destbasereg &&
3168                             ins->inst_offset == last_ins->inst_offset) {
3169                                         ins->opcode = OP_ICOMPARE_IMM;
3170                                         ins->sreg1 = last_ins->sreg1;
3171
3172                                         /* check if we can remove cmp reg,0 with test null */
3173                                         if (!ins->inst_imm)
3174                                                 ins->opcode = OP_X86_TEST_NULL;
3175                                 }
3176
3177                         break;
3178                 }
3179
3180                 mono_peephole_ins (bb, ins);
3181         }
3182 }
3183
3184 void
3185 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3186 {
3187         MonoInst *ins, *n;
3188
3189         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3190                 switch (ins->opcode) {
3191                 case OP_ICONST:
3192                 case OP_I8CONST: {
3193                         /* reg = 0 -> XOR (reg, reg) */
3194                         /* XOR sets cflags on x86, so we cant do it always */
3195                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
3196                                 ins->opcode = OP_LXOR;
3197                                 ins->sreg1 = ins->dreg;
3198                                 ins->sreg2 = ins->dreg;
3199                                 /* Fall through */
3200                         } else {
3201                                 break;
3202                         }
3203                 }
3204                 case OP_LXOR:
3205                         /*
3206                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3207                          * 0 result into 64 bits.
3208                          */
3209                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3210                                 ins->opcode = OP_IXOR;
3211                         }
3212                         /* Fall through */
3213                 case OP_IXOR:
3214                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3215                                 MonoInst *ins2;
3216
3217                                 /*
3218                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3219                                  * the latter has length 2-3 instead of 6 (reverse constant
3220                                  * propagation). These instruction sequences are very common
3221                                  * in the initlocals bblock.
3222                                  */
3223                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3224                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3225                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3226                                                 ins2->sreg1 = ins->dreg;
3227                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3228                                                 /* Continue */
3229                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3230                                                 NULLIFY_INS (ins2);
3231                                                 /* Continue */
3232                                         } else {
3233                                                 break;
3234                                         }
3235                                 }
3236                         }
3237                         break;
3238                 case OP_IADD_IMM:
3239                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3240                                 ins->opcode = OP_X86_INC_REG;
3241                         break;
3242                 case OP_ISUB_IMM:
3243                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3244                                 ins->opcode = OP_X86_DEC_REG;
3245                         break;
3246                 }
3247
3248                 mono_peephole_ins (bb, ins);
3249         }
3250 }
3251
3252 #define NEW_INS(cfg,ins,dest,op) do {   \
3253                 MONO_INST_NEW ((cfg), (dest), (op)); \
3254         (dest)->cil_code = (ins)->cil_code; \
3255         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3256         } while (0)
3257
3258 /*
3259  * mono_arch_lowering_pass:
3260  *
3261  *  Converts complex opcodes into simpler ones so that each IR instruction
3262  * corresponds to one machine instruction.
3263  */
3264 void
3265 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3266 {
3267         MonoInst *ins, *n, *temp;
3268
3269         /*
3270          * FIXME: Need to add more instructions, but the current machine
3271          * description can't model some parts of the composite instructions like
3272          * cdq.
3273          */
3274         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3275                 switch (ins->opcode) {
3276                 case OP_DIV_IMM:
3277                 case OP_REM_IMM:
3278                 case OP_IDIV_IMM:
3279                 case OP_IDIV_UN_IMM:
3280                 case OP_IREM_UN_IMM:
3281                 case OP_LREM_IMM:
3282                 case OP_IREM_IMM:
3283                         mono_decompose_op_imm (cfg, bb, ins);
3284                         break;
3285                 case OP_COMPARE_IMM:
3286                 case OP_LCOMPARE_IMM:
3287                         if (!amd64_is_imm32 (ins->inst_imm)) {
3288                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3289                                 temp->inst_c0 = ins->inst_imm;
3290                                 temp->dreg = mono_alloc_ireg (cfg);
3291                                 ins->opcode = OP_COMPARE;
3292                                 ins->sreg2 = temp->dreg;
3293                         }
3294                         break;
3295 #ifndef __mono_ilp32__
3296                 case OP_LOAD_MEMBASE:
3297 #endif
3298                 case OP_LOADI8_MEMBASE:
3299 #ifndef __native_client_codegen__
3300                 /*  Don't generate memindex opcodes (to simplify */
3301                 /*  read sandboxing) */
3302                         if (!amd64_is_imm32 (ins->inst_offset)) {
3303                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3304                                 temp->inst_c0 = ins->inst_offset;
3305                                 temp->dreg = mono_alloc_ireg (cfg);
3306                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3307                                 ins->inst_indexreg = temp->dreg;
3308                         }
3309 #endif
3310                         break;
3311 #ifndef __mono_ilp32__
3312                 case OP_STORE_MEMBASE_IMM:
3313 #endif
3314                 case OP_STOREI8_MEMBASE_IMM:
3315                         if (!amd64_is_imm32 (ins->inst_imm)) {
3316                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3317                                 temp->inst_c0 = ins->inst_imm;
3318                                 temp->dreg = mono_alloc_ireg (cfg);
3319                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3320                                 ins->sreg1 = temp->dreg;
3321                         }
3322                         break;
3323 #ifdef MONO_ARCH_SIMD_INTRINSICS
3324                 case OP_EXPAND_I1: {
3325                                 int temp_reg1 = mono_alloc_ireg (cfg);
3326                                 int temp_reg2 = mono_alloc_ireg (cfg);
3327                                 int original_reg = ins->sreg1;
3328
3329                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3330                                 temp->sreg1 = original_reg;
3331                                 temp->dreg = temp_reg1;
3332
3333                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3334                                 temp->sreg1 = temp_reg1;
3335                                 temp->dreg = temp_reg2;
3336                                 temp->inst_imm = 8;
3337
3338                                 NEW_INS (cfg, ins, temp, OP_LOR);
3339                                 temp->sreg1 = temp->dreg = temp_reg2;
3340                                 temp->sreg2 = temp_reg1;
3341
3342                                 ins->opcode = OP_EXPAND_I2;
3343                                 ins->sreg1 = temp_reg2;
3344                         }
3345                         break;
3346 #endif
3347                 default:
3348                         break;
3349                 }
3350         }
3351
3352         bb->max_vreg = cfg->next_vreg;
3353 }
3354
3355 static const int
3356 branch_cc_table [] = {
3357         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3358         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3359         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3360 };
3361
3362 /* Maps CMP_... constants to X86_CC_... constants */
3363 static const int
3364 cc_table [] = {
3365         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3366         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3367 };
3368
3369 static const int
3370 cc_signed_table [] = {
3371         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3372         FALSE, FALSE, FALSE, FALSE
3373 };
3374
3375 /*#include "cprop.c"*/
3376
3377 static unsigned char*
3378 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3379 {
3380         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3381
3382         if (size == 1)
3383                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3384         else if (size == 2)
3385                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3386         return code;
3387 }
3388
3389 static unsigned char*
3390 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3391 {
3392         int sreg = tree->sreg1;
3393         int need_touch = FALSE;
3394
3395 #if defined(HOST_WIN32)
3396         need_touch = TRUE;
3397 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3398         if (!tree->flags & MONO_INST_INIT)
3399                 need_touch = TRUE;
3400 #endif
3401
3402         if (need_touch) {
3403                 guint8* br[5];
3404
3405                 /*
3406                  * Under Windows:
3407                  * If requested stack size is larger than one page,
3408                  * perform stack-touch operation
3409                  */
3410                 /*
3411                  * Generate stack probe code.
3412                  * Under Windows, it is necessary to allocate one page at a time,
3413                  * "touching" stack after each successful sub-allocation. This is
3414                  * because of the way stack growth is implemented - there is a
3415                  * guard page before the lowest stack page that is currently commited.
3416                  * Stack normally grows sequentially so OS traps access to the
3417                  * guard page and commits more pages when needed.
3418                  */
3419                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3420                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3421
3422                 br[2] = code; /* loop */
3423                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3424                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3425                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3426                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3427                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3428                 amd64_patch (br[3], br[2]);
3429                 amd64_test_reg_reg (code, sreg, sreg);
3430                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3431                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3432
3433                 br[1] = code; x86_jump8 (code, 0);
3434
3435                 amd64_patch (br[0], code);
3436                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3437                 amd64_patch (br[1], code);
3438                 amd64_patch (br[4], code);
3439         }
3440         else
3441                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3442
3443         if (tree->flags & MONO_INST_INIT) {
3444                 int offset = 0;
3445                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3446                         amd64_push_reg (code, AMD64_RAX);
3447                         offset += 8;
3448                 }
3449                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3450                         amd64_push_reg (code, AMD64_RCX);
3451                         offset += 8;
3452                 }
3453                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3454                         amd64_push_reg (code, AMD64_RDI);
3455                         offset += 8;
3456                 }
3457
3458                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3459                 if (sreg != AMD64_RCX)
3460                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3461                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3462
3463                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3464                 if (cfg->param_area && cfg->arch.no_pushes)
3465                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3466                 amd64_cld (code);
3467 #if defined(__default_codegen__)
3468                 amd64_prefix (code, X86_REP_PREFIX);
3469                 amd64_stosl (code);
3470 #elif defined(__native_client_codegen__)
3471                 /* NaCl stos pseudo-instruction */
3472                 amd64_codegen_pre(code);
3473                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3474                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3475                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3476                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3477                 amd64_prefix (code, X86_REP_PREFIX);
3478                 amd64_stosl (code);
3479                 amd64_codegen_post(code);
3480 #endif /* __native_client_codegen__ */
3481
3482                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3483                         amd64_pop_reg (code, AMD64_RDI);
3484                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3485                         amd64_pop_reg (code, AMD64_RCX);
3486                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3487                         amd64_pop_reg (code, AMD64_RAX);
3488         }
3489         return code;
3490 }
3491
3492 static guint8*
3493 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3494 {
3495         CallInfo *cinfo;
3496         guint32 quad;
3497
3498         /* Move return value to the target register */
3499         /* FIXME: do this in the local reg allocator */
3500         switch (ins->opcode) {
3501         case OP_CALL:
3502         case OP_CALL_REG:
3503         case OP_CALL_MEMBASE:
3504         case OP_LCALL:
3505         case OP_LCALL_REG:
3506         case OP_LCALL_MEMBASE:
3507                 g_assert (ins->dreg == AMD64_RAX);
3508                 break;
3509         case OP_FCALL:
3510         case OP_FCALL_REG:
3511         case OP_FCALL_MEMBASE:
3512                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3513                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3514                 }
3515                 else {
3516                         if (ins->dreg != AMD64_XMM0)
3517                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3518                 }
3519                 break;
3520         case OP_VCALL:
3521         case OP_VCALL_REG:
3522         case OP_VCALL_MEMBASE:
3523         case OP_VCALL2:
3524         case OP_VCALL2_REG:
3525         case OP_VCALL2_MEMBASE:
3526                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3527                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3528                         MonoInst *loc = cfg->arch.vret_addr_loc;
3529
3530                         /* Load the destination address */
3531                         g_assert (loc->opcode == OP_REGOFFSET);
3532                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3533
3534                         for (quad = 0; quad < 2; quad ++) {
3535                                 switch (cinfo->ret.pair_storage [quad]) {
3536                                 case ArgInIReg:
3537                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3538                                         break;
3539                                 case ArgInFloatSSEReg:
3540                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3541                                         break;
3542                                 case ArgInDoubleSSEReg:
3543                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3544                                         break;
3545                                 case ArgNone:
3546                                         break;
3547                                 default:
3548                                         NOT_IMPLEMENTED;
3549                                 }
3550                         }
3551                 }
3552                 break;
3553         }
3554
3555         return code;
3556 }
3557
3558 #endif /* DISABLE_JIT */
3559
3560 #ifdef __APPLE__
3561 static int tls_gs_offset;
3562 #endif
3563
3564 gboolean
3565 mono_amd64_have_tls_get (void)
3566 {
3567 #ifdef __APPLE__
3568         static gboolean have_tls_get = FALSE;
3569         static gboolean inited = FALSE;
3570         guint8 *ins;
3571
3572         if (inited)
3573                 return have_tls_get;
3574
3575         ins = (guint8*)pthread_getspecific;
3576
3577         /*
3578          * We're looking for these two instructions:
3579          *
3580          * mov    %gs:[offset](,%rdi,8),%rax
3581          * retq
3582          */
3583         have_tls_get = ins [0] == 0x65 &&
3584                        ins [1] == 0x48 &&
3585                        ins [2] == 0x8b &&
3586                        ins [3] == 0x04 &&
3587                        ins [4] == 0xfd &&
3588                        ins [6] == 0x00 &&
3589                        ins [7] == 0x00 &&
3590                        ins [8] == 0x00 &&
3591                        ins [9] == 0xc3;
3592
3593         inited = TRUE;
3594
3595         tls_gs_offset = ins[5];
3596
3597         return have_tls_get;
3598 #else
3599         return TRUE;
3600 #endif
3601 }
3602
3603 int
3604 mono_amd64_get_tls_gs_offset (void)
3605 {
3606 #ifdef TARGET_OSX
3607         return tls_gs_offset;
3608 #else
3609         g_assert_not_reached ();
3610         return -1;
3611 #endif
3612 }
3613
3614 /*
3615  * mono_amd64_emit_tls_get:
3616  * @code: buffer to store code to
3617  * @dreg: hard register where to place the result
3618  * @tls_offset: offset info
3619  *
3620  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3621  * the dreg register the item in the thread local storage identified
3622  * by tls_offset.
3623  *
3624  * Returns: a pointer to the end of the stored code
3625  */
3626 guint8*
3627 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3628 {
3629 #ifdef HOST_WIN32
3630         if (tls_offset < 64) {
3631                 x86_prefix (code, X86_GS_PREFIX);
3632                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3633         } else {
3634                 guint8 *buf [16];
3635
3636                 g_assert (tls_offset < 0x440);
3637                 /* Load TEB->TlsExpansionSlots */
3638                 x86_prefix (code, X86_GS_PREFIX);
3639                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3640                 amd64_test_reg_reg (code, dreg, dreg);
3641                 buf [0] = code;
3642                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3643                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3644                 amd64_patch (buf [0], code);
3645         }
3646 #elif defined(__APPLE__)
3647         x86_prefix (code, X86_GS_PREFIX);
3648         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3649 #else
3650         if (optimize_for_xen) {
3651                 x86_prefix (code, X86_FS_PREFIX);
3652                 amd64_mov_reg_mem (code, dreg, 0, 8);
3653                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3654         } else {
3655                 x86_prefix (code, X86_FS_PREFIX);
3656                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3657         }
3658 #endif
3659         return code;
3660 }
3661
3662 static guint8*
3663 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3664 {
3665         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3666 #ifdef TARGET_OSX
3667         if (dreg != offset_reg)
3668                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3669         amd64_prefix (code, X86_GS_PREFIX);
3670         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3671 #elif defined(__linux__)
3672         int tmpreg = -1;
3673
3674         if (dreg == offset_reg) {
3675                 /* Use a temporary reg by saving it to the redzone */
3676                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3677                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3678                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3679                 offset_reg = tmpreg;
3680         }
3681         x86_prefix (code, X86_FS_PREFIX);
3682         amd64_mov_reg_mem (code, dreg, 0, 8);
3683         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3684         if (tmpreg != -1)
3685                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3686 #else
3687         g_assert_not_reached ();
3688 #endif
3689         return code;
3690 }
3691
3692 static guint8*
3693 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3694 {
3695 #ifdef HOST_WIN32
3696         g_assert_not_reached ();
3697 #elif defined(__APPLE__)
3698         x86_prefix (code, X86_GS_PREFIX);
3699         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3700 #else
3701         g_assert (!optimize_for_xen);
3702         x86_prefix (code, X86_FS_PREFIX);
3703         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3704 #endif
3705         return code;
3706 }
3707
3708 static guint8*
3709 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3710 {
3711         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3712 #ifdef HOST_WIN32
3713         g_assert_not_reached ();
3714 #elif defined(__APPLE__)
3715         x86_prefix (code, X86_GS_PREFIX);
3716         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3717 #else
3718         x86_prefix (code, X86_FS_PREFIX);
3719         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3720 #endif
3721         return code;
3722 }
3723
3724  /*
3725  * mono_arch_translate_tls_offset:
3726  *
3727  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3728  */
3729 int
3730 mono_arch_translate_tls_offset (int offset)
3731 {
3732 #ifdef __APPLE__
3733         return tls_gs_offset + (offset * 8);
3734 #else
3735         return offset;
3736 #endif
3737 }
3738
3739 /*
3740  * emit_setup_lmf:
3741  *
3742  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3743  */
3744 static guint8*
3745 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3746 {
3747         /*
3748          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3749          */
3750         /*
3751          * sp is saved right before calls but we need to save it here too so
3752          * async stack walks would work.
3753          */
3754         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3755         /* Save rbp */
3756         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3757         if (cfg->arch.omit_fp && cfa_offset != -1)
3758                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3759
3760         /* These can't contain refs */
3761         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3762         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3763         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3764         /* These are handled automatically by the stack marking code */
3765         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3766
3767         return code;
3768 }
3769
3770 #define REAL_PRINT_REG(text,reg) \
3771 mono_assert (reg >= 0); \
3772 amd64_push_reg (code, AMD64_RAX); \
3773 amd64_push_reg (code, AMD64_RDX); \
3774 amd64_push_reg (code, AMD64_RCX); \
3775 amd64_push_reg (code, reg); \
3776 amd64_push_imm (code, reg); \
3777 amd64_push_imm (code, text " %d %p\n"); \
3778 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3779 amd64_call_reg (code, AMD64_RAX); \
3780 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3781 amd64_pop_reg (code, AMD64_RCX); \
3782 amd64_pop_reg (code, AMD64_RDX); \
3783 amd64_pop_reg (code, AMD64_RAX);
3784
3785 /* benchmark and set based on cpu */
3786 #define LOOP_ALIGNMENT 8
3787 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3788
3789 #ifndef DISABLE_JIT
3790 void
3791 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3792 {
3793         MonoInst *ins;
3794         MonoCallInst *call;
3795         guint offset;
3796         guint8 *code = cfg->native_code + cfg->code_len;
3797         MonoInst *last_ins = NULL;
3798         guint last_offset = 0;
3799         int max_len;
3800
3801         /* Fix max_offset estimate for each successor bb */
3802         if (cfg->opt & MONO_OPT_BRANCH) {
3803                 int current_offset = cfg->code_len;
3804                 MonoBasicBlock *current_bb;
3805                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3806                         current_bb->max_offset = current_offset;
3807                         current_offset += current_bb->max_length;
3808                 }
3809         }
3810
3811         if (cfg->opt & MONO_OPT_LOOP) {
3812                 int pad, align = LOOP_ALIGNMENT;
3813                 /* set alignment depending on cpu */
3814                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3815                         pad = align - pad;
3816                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3817                         amd64_padding (code, pad);
3818                         cfg->code_len += pad;
3819                         bb->native_offset = cfg->code_len;
3820                 }
3821         }
3822
3823 #if defined(__native_client_codegen__)
3824         /* For Native Client, all indirect call/jump targets must be */
3825         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3826         /* indirectly as well.                                       */
3827         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3828                                       (bb->flags & BB_EXCEPTION_HANDLER);
3829
3830         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3831                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3832                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3833                 cfg->code_len += pad;
3834                 bb->native_offset = cfg->code_len;
3835         }
3836 #endif  /*__native_client_codegen__*/
3837
3838         if (cfg->verbose_level > 2)
3839                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3840
3841         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3842                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3843                 g_assert (!cfg->compile_aot);
3844
3845                 cov->data [bb->dfn].cil_code = bb->cil_code;
3846                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3847                 /* this is not thread save, but good enough */
3848                 amd64_inc_membase (code, AMD64_R11, 0);
3849         }
3850
3851         offset = code - cfg->native_code;
3852
3853         mono_debug_open_block (cfg, bb, offset);
3854
3855     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3856                 x86_breakpoint (code);
3857
3858         MONO_BB_FOR_EACH_INS (bb, ins) {
3859                 offset = code - cfg->native_code;
3860
3861                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3862
3863 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3864
3865                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3866                         cfg->code_size *= 2;
3867                         cfg->native_code = mono_realloc_native_code(cfg);
3868                         code = cfg->native_code + offset;
3869                         cfg->stat_code_reallocs++;
3870                 }
3871
3872                 if (cfg->debug_info)
3873                         mono_debug_record_line_number (cfg, ins, offset);
3874
3875                 switch (ins->opcode) {
3876                 case OP_BIGMUL:
3877                         amd64_mul_reg (code, ins->sreg2, TRUE);
3878                         break;
3879                 case OP_BIGMUL_UN:
3880                         amd64_mul_reg (code, ins->sreg2, FALSE);
3881                         break;
3882                 case OP_X86_SETEQ_MEMBASE:
3883                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3884                         break;
3885                 case OP_STOREI1_MEMBASE_IMM:
3886                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3887                         break;
3888                 case OP_STOREI2_MEMBASE_IMM:
3889                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3890                         break;
3891                 case OP_STOREI4_MEMBASE_IMM:
3892                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3893                         break;
3894                 case OP_STOREI1_MEMBASE_REG:
3895                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3896                         break;
3897                 case OP_STOREI2_MEMBASE_REG:
3898                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3899                         break;
3900                 /* In AMD64 NaCl, pointers are 4 bytes, */
3901                 /*  so STORE_* != STOREI8_*. Likewise below. */
3902                 case OP_STORE_MEMBASE_REG:
3903                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3904                         break;
3905                 case OP_STOREI8_MEMBASE_REG:
3906                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3907                         break;
3908                 case OP_STOREI4_MEMBASE_REG:
3909                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3910                         break;
3911                 case OP_STORE_MEMBASE_IMM:
3912 #ifndef __native_client_codegen__
3913                         /* In NaCl, this could be a PCONST type, which could */
3914                         /* mean a pointer type was copied directly into the  */
3915                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3916                         /* the value would be 0x00000000FFFFFFFF which is    */
3917                         /* not proper for an imm32 unless you cast it.       */
3918                         g_assert (amd64_is_imm32 (ins->inst_imm));
3919 #endif
3920                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3921                         break;
3922                 case OP_STOREI8_MEMBASE_IMM:
3923                         g_assert (amd64_is_imm32 (ins->inst_imm));
3924                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3925                         break;
3926                 case OP_LOAD_MEM:
3927 #ifdef __mono_ilp32__
3928                         /* In ILP32, pointers are 4 bytes, so separate these */
3929                         /* cases, use literal 8 below where we really want 8 */
3930                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3931                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3932                         break;
3933 #endif
3934                 case OP_LOADI8_MEM:
3935                         // FIXME: Decompose this earlier
3936                         if (amd64_is_imm32 (ins->inst_imm))
3937                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3938                         else {
3939                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3940                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3941                         }
3942                         break;
3943                 case OP_LOADI4_MEM:
3944                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3945                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3946                         break;
3947                 case OP_LOADU4_MEM:
3948                         // FIXME: Decompose this earlier
3949                         if (amd64_is_imm32 (ins->inst_imm))
3950                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3951                         else {
3952                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3953                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3954                         }
3955                         break;
3956                 case OP_LOADU1_MEM:
3957                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3958                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3959                         break;
3960                 case OP_LOADU2_MEM:
3961                         /* For NaCl, pointers are 4 bytes, so separate these */
3962                         /* cases, use literal 8 below where we really want 8 */
3963                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3964                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3965                         break;
3966                 case OP_LOAD_MEMBASE:
3967                         g_assert (amd64_is_imm32 (ins->inst_offset));
3968                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3969                         break;
3970                 case OP_LOADI8_MEMBASE:
3971                         /* Use literal 8 instead of sizeof pointer or */
3972                         /* register, we really want 8 for this opcode */
3973                         g_assert (amd64_is_imm32 (ins->inst_offset));
3974                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3975                         break;
3976                 case OP_LOADI4_MEMBASE:
3977                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3978                         break;
3979                 case OP_LOADU4_MEMBASE:
3980                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3981                         break;
3982                 case OP_LOADU1_MEMBASE:
3983                         /* The cpu zero extends the result into 64 bits */
3984                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3985                         break;
3986                 case OP_LOADI1_MEMBASE:
3987                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3988                         break;
3989                 case OP_LOADU2_MEMBASE:
3990                         /* The cpu zero extends the result into 64 bits */
3991                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3992                         break;
3993                 case OP_LOADI2_MEMBASE:
3994                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3995                         break;
3996                 case OP_AMD64_LOADI8_MEMINDEX:
3997                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3998                         break;
3999                 case OP_LCONV_TO_I1:
4000                 case OP_ICONV_TO_I1:
4001                 case OP_SEXT_I1:
4002                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4003                         break;
4004                 case OP_LCONV_TO_I2:
4005                 case OP_ICONV_TO_I2:
4006                 case OP_SEXT_I2:
4007                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4008                         break;
4009                 case OP_LCONV_TO_U1:
4010                 case OP_ICONV_TO_U1:
4011                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4012                         break;
4013                 case OP_LCONV_TO_U2:
4014                 case OP_ICONV_TO_U2:
4015                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4016                         break;
4017                 case OP_ZEXT_I4:
4018                         /* Clean out the upper word */
4019                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4020                         break;
4021                 case OP_SEXT_I4:
4022                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4023                         break;
4024                 case OP_COMPARE:
4025                 case OP_LCOMPARE:
4026                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4027                         break;
4028                 case OP_COMPARE_IMM:
4029 #if defined(__mono_ilp32__)
4030                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4031                         g_assert (amd64_is_imm32 (ins->inst_imm));
4032                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4033                         break;
4034 #endif
4035                 case OP_LCOMPARE_IMM:
4036                         g_assert (amd64_is_imm32 (ins->inst_imm));
4037                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4038                         break;
4039                 case OP_X86_COMPARE_REG_MEMBASE:
4040                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4041                         break;
4042                 case OP_X86_TEST_NULL:
4043                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4044                         break;
4045                 case OP_AMD64_TEST_NULL:
4046                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4047                         break;
4048
4049                 case OP_X86_ADD_REG_MEMBASE:
4050                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4051                         break;
4052                 case OP_X86_SUB_REG_MEMBASE:
4053                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4054                         break;
4055                 case OP_X86_AND_REG_MEMBASE:
4056                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4057                         break;
4058                 case OP_X86_OR_REG_MEMBASE:
4059                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4060                         break;
4061                 case OP_X86_XOR_REG_MEMBASE:
4062                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4063                         break;
4064
4065                 case OP_X86_ADD_MEMBASE_IMM:
4066                         /* FIXME: Make a 64 version too */
4067                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4068                         break;
4069                 case OP_X86_SUB_MEMBASE_IMM:
4070                         g_assert (amd64_is_imm32 (ins->inst_imm));
4071                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4072                         break;
4073                 case OP_X86_AND_MEMBASE_IMM:
4074                         g_assert (amd64_is_imm32 (ins->inst_imm));
4075                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4076                         break;
4077                 case OP_X86_OR_MEMBASE_IMM:
4078                         g_assert (amd64_is_imm32 (ins->inst_imm));
4079                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4080                         break;
4081                 case OP_X86_XOR_MEMBASE_IMM:
4082                         g_assert (amd64_is_imm32 (ins->inst_imm));
4083                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4084                         break;
4085                 case OP_X86_ADD_MEMBASE_REG:
4086                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4087                         break;
4088                 case OP_X86_SUB_MEMBASE_REG:
4089                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4090                         break;
4091                 case OP_X86_AND_MEMBASE_REG:
4092                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4093                         break;
4094                 case OP_X86_OR_MEMBASE_REG:
4095                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4096                         break;
4097                 case OP_X86_XOR_MEMBASE_REG:
4098                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4099                         break;
4100                 case OP_X86_INC_MEMBASE:
4101                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4102                         break;
4103                 case OP_X86_INC_REG:
4104                         amd64_inc_reg_size (code, ins->dreg, 4);
4105                         break;
4106                 case OP_X86_DEC_MEMBASE:
4107                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4108                         break;
4109                 case OP_X86_DEC_REG:
4110                         amd64_dec_reg_size (code, ins->dreg, 4);
4111                         break;
4112                 case OP_X86_MUL_REG_MEMBASE:
4113                 case OP_X86_MUL_MEMBASE_REG:
4114                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4115                         break;
4116                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4117                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4118                         break;
4119                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4120                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4121                         break;
4122                 case OP_AMD64_COMPARE_MEMBASE_REG:
4123                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4124                         break;
4125                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4126                         g_assert (amd64_is_imm32 (ins->inst_imm));
4127                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4128                         break;
4129                 case OP_X86_COMPARE_MEMBASE8_IMM:
4130                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4131                         break;
4132                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4133                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4134                         break;
4135                 case OP_AMD64_COMPARE_REG_MEMBASE:
4136                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4137                         break;
4138
4139                 case OP_AMD64_ADD_REG_MEMBASE:
4140                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4141                         break;
4142                 case OP_AMD64_SUB_REG_MEMBASE:
4143                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4144                         break;
4145                 case OP_AMD64_AND_REG_MEMBASE:
4146                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4147                         break;
4148                 case OP_AMD64_OR_REG_MEMBASE:
4149                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4150                         break;
4151                 case OP_AMD64_XOR_REG_MEMBASE:
4152                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4153                         break;
4154
4155                 case OP_AMD64_ADD_MEMBASE_REG:
4156                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4157                         break;
4158                 case OP_AMD64_SUB_MEMBASE_REG:
4159                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4160                         break;
4161                 case OP_AMD64_AND_MEMBASE_REG:
4162                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4163                         break;
4164                 case OP_AMD64_OR_MEMBASE_REG:
4165                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4166                         break;
4167                 case OP_AMD64_XOR_MEMBASE_REG:
4168                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4169                         break;
4170
4171                 case OP_AMD64_ADD_MEMBASE_IMM:
4172                         g_assert (amd64_is_imm32 (ins->inst_imm));
4173                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4174                         break;
4175                 case OP_AMD64_SUB_MEMBASE_IMM:
4176                         g_assert (amd64_is_imm32 (ins->inst_imm));
4177                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4178                         break;
4179                 case OP_AMD64_AND_MEMBASE_IMM:
4180                         g_assert (amd64_is_imm32 (ins->inst_imm));
4181                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4182                         break;
4183                 case OP_AMD64_OR_MEMBASE_IMM:
4184                         g_assert (amd64_is_imm32 (ins->inst_imm));
4185                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4186                         break;
4187                 case OP_AMD64_XOR_MEMBASE_IMM:
4188                         g_assert (amd64_is_imm32 (ins->inst_imm));
4189                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4190                         break;
4191
4192                 case OP_BREAK:
4193                         amd64_breakpoint (code);
4194                         break;
4195                 case OP_RELAXED_NOP:
4196                         x86_prefix (code, X86_REP_PREFIX);
4197                         x86_nop (code);
4198                         break;
4199                 case OP_HARD_NOP:
4200                         x86_nop (code);
4201                         break;
4202                 case OP_NOP:
4203                 case OP_DUMMY_USE:
4204                 case OP_DUMMY_STORE:
4205                 case OP_DUMMY_ICONST:
4206                 case OP_DUMMY_R8CONST:
4207                 case OP_NOT_REACHED:
4208                 case OP_NOT_NULL:
4209                         break;
4210                 case OP_SEQ_POINT: {
4211                         int i;
4212
4213                         /*
4214                          * Read from the single stepping trigger page. This will cause a
4215                          * SIGSEGV when single stepping is enabled.
4216                          * We do this _before_ the breakpoint, so single stepping after
4217                          * a breakpoint is hit will step to the next IL offset.
4218                          */
4219                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4220                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4221
4222                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4223                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4224                         }
4225
4226                         /*
4227                          * This is the address which is saved in seq points,
4228                          */
4229                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4230
4231                         if (cfg->compile_aot) {
4232                                 guint32 offset = code - cfg->native_code;
4233                                 guint32 val;
4234                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4235
4236                                 /* Load info var */
4237                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4238                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4239                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4240                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4241                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4242                         } else {
4243                                 /*
4244                                  * A placeholder for a possible breakpoint inserted by
4245                                  * mono_arch_set_breakpoint ().
4246                                  */
4247                                 for (i = 0; i < breakpoint_size; ++i)
4248                                         x86_nop (code);
4249                         }
4250                         /*
4251                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4252                          * to another IL offset.
4253                          */
4254                         x86_nop (code);
4255                         break;
4256                 }
4257                 case OP_ADDCC:
4258                 case OP_LADDCC:
4259                 case OP_LADD:
4260                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4261                         break;
4262                 case OP_ADC:
4263                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4264                         break;
4265                 case OP_ADD_IMM:
4266                 case OP_LADD_IMM:
4267                         g_assert (amd64_is_imm32 (ins->inst_imm));
4268                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4269                         break;
4270                 case OP_ADC_IMM:
4271                         g_assert (amd64_is_imm32 (ins->inst_imm));
4272                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4273                         break;
4274                 case OP_SUBCC:
4275                 case OP_LSUBCC:
4276                 case OP_LSUB:
4277                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4278                         break;
4279                 case OP_SBB:
4280                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4281                         break;
4282                 case OP_SUB_IMM:
4283                 case OP_LSUB_IMM:
4284                         g_assert (amd64_is_imm32 (ins->inst_imm));
4285                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4286                         break;
4287                 case OP_SBB_IMM:
4288                         g_assert (amd64_is_imm32 (ins->inst_imm));
4289                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4290                         break;
4291                 case OP_LAND:
4292                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4293                         break;
4294                 case OP_AND_IMM:
4295                 case OP_LAND_IMM:
4296                         g_assert (amd64_is_imm32 (ins->inst_imm));
4297                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4298                         break;
4299                 case OP_LMUL:
4300                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4301                         break;
4302                 case OP_MUL_IMM:
4303                 case OP_LMUL_IMM:
4304                 case OP_IMUL_IMM: {
4305                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4306
4307                         switch (ins->inst_imm) {
4308                         case 2:
4309                                 /* MOV r1, r2 */
4310                                 /* ADD r1, r1 */
4311                                 if (ins->dreg != ins->sreg1)
4312                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4313                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4314                                 break;
4315                         case 3:
4316                                 /* LEA r1, [r2 + r2*2] */
4317                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4318                                 break;
4319                         case 5:
4320                                 /* LEA r1, [r2 + r2*4] */
4321                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4322                                 break;
4323                         case 6:
4324                                 /* LEA r1, [r2 + r2*2] */
4325                                 /* ADD r1, r1          */
4326                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4327                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4328                                 break;
4329                         case 9:
4330                                 /* LEA r1, [r2 + r2*8] */
4331                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4332                                 break;
4333                         case 10:
4334                                 /* LEA r1, [r2 + r2*4] */
4335                                 /* ADD r1, r1          */
4336                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4337                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4338                                 break;
4339                         case 12:
4340                                 /* LEA r1, [r2 + r2*2] */
4341                                 /* SHL r1, 2           */
4342                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4343                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4344                                 break;
4345                         case 25:
4346                                 /* LEA r1, [r2 + r2*4] */
4347                                 /* LEA r1, [r1 + r1*4] */
4348                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4349                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4350                                 break;
4351                         case 100:
4352                                 /* LEA r1, [r2 + r2*4] */
4353                                 /* SHL r1, 2           */
4354                                 /* LEA r1, [r1 + r1*4] */
4355                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4356                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4357                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4358                                 break;
4359                         default:
4360                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4361                                 break;
4362                         }
4363                         break;
4364                 }
4365                 case OP_LDIV:
4366                 case OP_LREM:
4367 #if defined( __native_client_codegen__ )
4368                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4369                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4370 #endif
4371                         /* Regalloc magic makes the div/rem cases the same */
4372                         if (ins->sreg2 == AMD64_RDX) {
4373                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4374                                 amd64_cdq (code);
4375                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4376                         } else {
4377                                 amd64_cdq (code);
4378                                 amd64_div_reg (code, ins->sreg2, TRUE);
4379                         }
4380                         break;
4381                 case OP_LDIV_UN:
4382                 case OP_LREM_UN:
4383 #if defined( __native_client_codegen__ )
4384                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4385                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4386 #endif
4387                         if (ins->sreg2 == AMD64_RDX) {
4388                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4389                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4390                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4391                         } else {
4392                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4393                                 amd64_div_reg (code, ins->sreg2, FALSE);
4394                         }
4395                         break;
4396                 case OP_IDIV:
4397                 case OP_IREM:
4398 #if defined( __native_client_codegen__ )
4399                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4400                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4401 #endif
4402                         if (ins->sreg2 == AMD64_RDX) {
4403                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4404                                 amd64_cdq_size (code, 4);
4405                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4406                         } else {
4407                                 amd64_cdq_size (code, 4);
4408                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4409                         }
4410                         break;
4411                 case OP_IDIV_UN:
4412                 case OP_IREM_UN:
4413 #if defined( __native_client_codegen__ )
4414                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4415                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4416 #endif
4417                         if (ins->sreg2 == AMD64_RDX) {
4418                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4419                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4420                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4421                         } else {
4422                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4423                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4424                         }
4425                         break;
4426                 case OP_LMUL_OVF:
4427                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4428                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4429                         break;
4430                 case OP_LOR:
4431                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4432                         break;
4433                 case OP_OR_IMM:
4434                 case OP_LOR_IMM:
4435                         g_assert (amd64_is_imm32 (ins->inst_imm));
4436                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4437                         break;
4438                 case OP_LXOR:
4439                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4440                         break;
4441                 case OP_XOR_IMM:
4442                 case OP_LXOR_IMM:
4443                         g_assert (amd64_is_imm32 (ins->inst_imm));
4444                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4445                         break;
4446                 case OP_LSHL:
4447                         g_assert (ins->sreg2 == AMD64_RCX);
4448                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4449                         break;
4450                 case OP_LSHR:
4451                         g_assert (ins->sreg2 == AMD64_RCX);
4452                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4453                         break;
4454                 case OP_SHR_IMM:
4455                         g_assert (amd64_is_imm32 (ins->inst_imm));
4456                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4457                         break;
4458                 case OP_LSHR_IMM:
4459                         g_assert (amd64_is_imm32 (ins->inst_imm));
4460                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4461                         break;
4462                 case OP_SHR_UN_IMM:
4463                         g_assert (amd64_is_imm32 (ins->inst_imm));
4464                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4465                         break;
4466                 case OP_LSHR_UN_IMM:
4467                         g_assert (amd64_is_imm32 (ins->inst_imm));
4468                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4469                         break;
4470                 case OP_LSHR_UN:
4471                         g_assert (ins->sreg2 == AMD64_RCX);
4472                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4473                         break;
4474                 case OP_SHL_IMM:
4475                         g_assert (amd64_is_imm32 (ins->inst_imm));
4476                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4477                         break;
4478                 case OP_LSHL_IMM:
4479                         g_assert (amd64_is_imm32 (ins->inst_imm));
4480                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4481                         break;
4482
4483                 case OP_IADDCC:
4484                 case OP_IADD:
4485                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4486                         break;
4487                 case OP_IADC:
4488                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4489                         break;
4490                 case OP_IADD_IMM:
4491                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4492                         break;
4493                 case OP_IADC_IMM:
4494                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4495                         break;
4496                 case OP_ISUBCC:
4497                 case OP_ISUB:
4498                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4499                         break;
4500                 case OP_ISBB:
4501                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4502                         break;
4503                 case OP_ISUB_IMM:
4504                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4505                         break;
4506                 case OP_ISBB_IMM:
4507                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4508                         break;
4509                 case OP_IAND:
4510                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4511                         break;
4512                 case OP_IAND_IMM:
4513                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4514                         break;
4515                 case OP_IOR:
4516                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4517                         break;
4518                 case OP_IOR_IMM:
4519                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4520                         break;
4521                 case OP_IXOR:
4522                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4523                         break;
4524                 case OP_IXOR_IMM:
4525                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4526                         break;
4527                 case OP_INEG:
4528                         amd64_neg_reg_size (code, ins->sreg1, 4);
4529                         break;
4530                 case OP_INOT:
4531                         amd64_not_reg_size (code, ins->sreg1, 4);
4532                         break;
4533                 case OP_ISHL:
4534                         g_assert (ins->sreg2 == AMD64_RCX);
4535                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4536                         break;
4537                 case OP_ISHR:
4538                         g_assert (ins->sreg2 == AMD64_RCX);
4539                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4540                         break;
4541                 case OP_ISHR_IMM:
4542                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4543                         break;
4544                 case OP_ISHR_UN_IMM:
4545                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4546                         break;
4547                 case OP_ISHR_UN:
4548                         g_assert (ins->sreg2 == AMD64_RCX);
4549                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4550                         break;
4551                 case OP_ISHL_IMM:
4552                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4553                         break;
4554                 case OP_IMUL:
4555                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4556                         break;
4557                 case OP_IMUL_OVF:
4558                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4559                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4560                         break;
4561                 case OP_IMUL_OVF_UN:
4562                 case OP_LMUL_OVF_UN: {
4563                         /* the mul operation and the exception check should most likely be split */
4564                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4565                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4566                         /*g_assert (ins->sreg2 == X86_EAX);
4567                         g_assert (ins->dreg == X86_EAX);*/
4568                         if (ins->sreg2 == X86_EAX) {
4569                                 non_eax_reg = ins->sreg1;
4570                         } else if (ins->sreg1 == X86_EAX) {
4571                                 non_eax_reg = ins->sreg2;
4572                         } else {
4573                                 /* no need to save since we're going to store to it anyway */
4574                                 if (ins->dreg != X86_EAX) {
4575                                         saved_eax = TRUE;
4576                                         amd64_push_reg (code, X86_EAX);
4577                                 }
4578                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4579                                 non_eax_reg = ins->sreg2;
4580                         }
4581                         if (ins->dreg == X86_EDX) {
4582                                 if (!saved_eax) {
4583                                         saved_eax = TRUE;
4584                                         amd64_push_reg (code, X86_EAX);
4585                                 }
4586                         } else {
4587                                 saved_edx = TRUE;
4588                                 amd64_push_reg (code, X86_EDX);
4589                         }
4590                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4591                         /* save before the check since pop and mov don't change the flags */
4592                         if (ins->dreg != X86_EAX)
4593                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4594                         if (saved_edx)
4595                                 amd64_pop_reg (code, X86_EDX);
4596                         if (saved_eax)
4597                                 amd64_pop_reg (code, X86_EAX);
4598                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4599                         break;
4600                 }
4601                 case OP_ICOMPARE:
4602                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4603                         break;
4604                 case OP_ICOMPARE_IMM:
4605                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4606                         break;
4607                 case OP_IBEQ:
4608                 case OP_IBLT:
4609                 case OP_IBGT:
4610                 case OP_IBGE:
4611                 case OP_IBLE:
4612                 case OP_LBEQ:
4613                 case OP_LBLT:
4614                 case OP_LBGT:
4615                 case OP_LBGE:
4616                 case OP_LBLE:
4617                 case OP_IBNE_UN:
4618                 case OP_IBLT_UN:
4619                 case OP_IBGT_UN:
4620                 case OP_IBGE_UN:
4621                 case OP_IBLE_UN:
4622                 case OP_LBNE_UN:
4623                 case OP_LBLT_UN:
4624                 case OP_LBGT_UN:
4625                 case OP_LBGE_UN:
4626                 case OP_LBLE_UN:
4627                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4628                         break;
4629
4630                 case OP_CMOV_IEQ:
4631                 case OP_CMOV_IGE:
4632                 case OP_CMOV_IGT:
4633                 case OP_CMOV_ILE:
4634                 case OP_CMOV_ILT:
4635                 case OP_CMOV_INE_UN:
4636                 case OP_CMOV_IGE_UN:
4637                 case OP_CMOV_IGT_UN:
4638                 case OP_CMOV_ILE_UN:
4639                 case OP_CMOV_ILT_UN:
4640                 case OP_CMOV_LEQ:
4641                 case OP_CMOV_LGE:
4642                 case OP_CMOV_LGT:
4643                 case OP_CMOV_LLE:
4644                 case OP_CMOV_LLT:
4645                 case OP_CMOV_LNE_UN:
4646                 case OP_CMOV_LGE_UN:
4647                 case OP_CMOV_LGT_UN:
4648                 case OP_CMOV_LLE_UN:
4649                 case OP_CMOV_LLT_UN:
4650                         g_assert (ins->dreg == ins->sreg1);
4651                         /* This needs to operate on 64 bit values */
4652                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4653                         break;
4654
4655                 case OP_LNOT:
4656                         amd64_not_reg (code, ins->sreg1);
4657                         break;
4658                 case OP_LNEG:
4659                         amd64_neg_reg (code, ins->sreg1);
4660                         break;
4661
4662                 case OP_ICONST:
4663                 case OP_I8CONST:
4664                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4665                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4666                         else
4667                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4668                         break;
4669                 case OP_AOTCONST:
4670                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4671                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4672                         break;
4673                 case OP_JUMP_TABLE:
4674                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4675                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4676                         break;
4677                 case OP_MOVE:
4678                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4679                         break;
4680                 case OP_AMD64_SET_XMMREG_R4: {
4681                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4682                         break;
4683                 }
4684                 case OP_AMD64_SET_XMMREG_R8: {
4685                         if (ins->dreg != ins->sreg1)
4686                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4687                         break;
4688                 }
4689                 case OP_TAILCALL: {
4690                         MonoCallInst *call = (MonoCallInst*)ins;
4691                         int i, save_area_offset;
4692
4693                         g_assert (!cfg->method->save_lmf);
4694
4695                         /* Restore callee saved registers */
4696                         save_area_offset = cfg->arch.reg_save_area_offset;
4697                         for (i = 0; i < AMD64_NREG; ++i)
4698                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4699                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4700                                         save_area_offset += 8;
4701                                 }
4702
4703                         if (cfg->arch.omit_fp) {
4704                                 if (cfg->arch.stack_alloc_size)
4705                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4706                                 // FIXME:
4707                                 if (call->stack_usage)
4708                                         NOT_IMPLEMENTED;
4709                         } else {
4710                                 /* Copy arguments on the stack to our argument area */
4711                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4712                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4713                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4714                                 }
4715
4716                                 amd64_leave (code);
4717                         }
4718
4719                         offset = code - cfg->native_code;
4720                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4721                         if (cfg->compile_aot)
4722                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4723                         else
4724                                 amd64_set_reg_template (code, AMD64_R11);
4725                         amd64_jump_reg (code, AMD64_R11);
4726                         ins->flags |= MONO_INST_GC_CALLSITE;
4727                         ins->backend.pc_offset = code - cfg->native_code;
4728                         break;
4729                 }
4730                 case OP_CHECK_THIS:
4731                         /* ensure ins->sreg1 is not NULL */
4732                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4733                         break;
4734                 case OP_ARGLIST: {
4735                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4736                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4737                         break;
4738                 }
4739                 case OP_CALL:
4740                 case OP_FCALL:
4741                 case OP_LCALL:
4742                 case OP_VCALL:
4743                 case OP_VCALL2:
4744                 case OP_VOIDCALL:
4745                         call = (MonoCallInst*)ins;
4746                         /*
4747                          * The AMD64 ABI forces callers to know about varargs.
4748                          */
4749                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4750                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4751                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4752                                 /*
4753                                  * Since the unmanaged calling convention doesn't contain a
4754                                  * 'vararg' entry, we have to treat every pinvoke call as a
4755                                  * potential vararg call.
4756                                  */
4757                                 guint32 nregs, i;
4758                                 nregs = 0;
4759                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4760                                         if (call->used_fregs & (1 << i))
4761                                                 nregs ++;
4762                                 if (!nregs)
4763                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4764                                 else
4765                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4766                         }
4767
4768                         if (ins->flags & MONO_INST_HAS_METHOD)
4769                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4770                         else
4771                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4772                         ins->flags |= MONO_INST_GC_CALLSITE;
4773                         ins->backend.pc_offset = code - cfg->native_code;
4774                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4775                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4776                         code = emit_move_return_value (cfg, ins, code);
4777                         break;
4778                 case OP_FCALL_REG:
4779                 case OP_LCALL_REG:
4780                 case OP_VCALL_REG:
4781                 case OP_VCALL2_REG:
4782                 case OP_VOIDCALL_REG:
4783                 case OP_CALL_REG:
4784                         call = (MonoCallInst*)ins;
4785
4786                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4787                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4788                                 ins->sreg1 = AMD64_R11;
4789                         }
4790
4791                         /*
4792                          * The AMD64 ABI forces callers to know about varargs.
4793                          */
4794                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4795                                 if (ins->sreg1 == AMD64_RAX) {
4796                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4797                                         ins->sreg1 = AMD64_R11;
4798                                 }
4799                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4800                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4801                                 /*
4802                                  * Since the unmanaged calling convention doesn't contain a
4803                                  * 'vararg' entry, we have to treat every pinvoke call as a
4804                                  * potential vararg call.
4805                                  */
4806                                 guint32 nregs, i;
4807                                 nregs = 0;
4808                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4809                                         if (call->used_fregs & (1 << i))
4810                                                 nregs ++;
4811                                 if (ins->sreg1 == AMD64_RAX) {
4812                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4813                                         ins->sreg1 = AMD64_R11;
4814                                 }
4815                                 if (!nregs)
4816                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4817                                 else
4818                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4819                         }
4820
4821                         amd64_call_reg (code, ins->sreg1);
4822                         ins->flags |= MONO_INST_GC_CALLSITE;
4823                         ins->backend.pc_offset = code - cfg->native_code;
4824                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4825                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4826                         code = emit_move_return_value (cfg, ins, code);
4827                         break;
4828                 case OP_FCALL_MEMBASE:
4829                 case OP_LCALL_MEMBASE:
4830                 case OP_VCALL_MEMBASE:
4831                 case OP_VCALL2_MEMBASE:
4832                 case OP_VOIDCALL_MEMBASE:
4833                 case OP_CALL_MEMBASE:
4834                         call = (MonoCallInst*)ins;
4835
4836                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4837                         ins->flags |= MONO_INST_GC_CALLSITE;
4838                         ins->backend.pc_offset = code - cfg->native_code;
4839                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4840                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4841                         code = emit_move_return_value (cfg, ins, code);
4842                         break;
4843                 case OP_DYN_CALL: {
4844                         int i;
4845                         MonoInst *var = cfg->dyn_call_var;
4846
4847                         g_assert (var->opcode == OP_REGOFFSET);
4848
4849                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4850                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4851                         /* r10 = ftn */
4852                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4853
4854                         /* Save args buffer */
4855                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4856
4857                         /* Set argument registers */
4858                         for (i = 0; i < PARAM_REGS; ++i)
4859                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4860
4861                         /* Make the call */
4862                         amd64_call_reg (code, AMD64_R10);
4863
4864                         ins->flags |= MONO_INST_GC_CALLSITE;
4865                         ins->backend.pc_offset = code - cfg->native_code;
4866
4867                         /* Save result */
4868                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4869                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4870                         break;
4871                 }
4872                 case OP_AMD64_SAVE_SP_TO_LMF: {
4873                         MonoInst *lmf_var = cfg->lmf_var;
4874                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4875                         break;
4876                 }
4877                 case OP_X86_PUSH:
4878                         g_assert (!cfg->arch.no_pushes);
4879                         amd64_push_reg (code, ins->sreg1);
4880                         break;
4881                 case OP_X86_PUSH_IMM:
4882                         g_assert (!cfg->arch.no_pushes);
4883                         g_assert (amd64_is_imm32 (ins->inst_imm));
4884                         amd64_push_imm (code, ins->inst_imm);
4885                         break;
4886                 case OP_X86_PUSH_MEMBASE:
4887                         g_assert (!cfg->arch.no_pushes);
4888                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4889                         break;
4890                 case OP_X86_PUSH_OBJ: {
4891                         int size = ALIGN_TO (ins->inst_imm, 8);
4892
4893                         g_assert (!cfg->arch.no_pushes);
4894
4895                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4896                         amd64_push_reg (code, AMD64_RDI);
4897                         amd64_push_reg (code, AMD64_RSI);
4898                         amd64_push_reg (code, AMD64_RCX);
4899                         if (ins->inst_offset)
4900                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4901                         else
4902                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4903                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4904                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4905                         amd64_cld (code);
4906                         amd64_prefix (code, X86_REP_PREFIX);
4907                         amd64_movsd (code);
4908                         amd64_pop_reg (code, AMD64_RCX);
4909                         amd64_pop_reg (code, AMD64_RSI);
4910                         amd64_pop_reg (code, AMD64_RDI);
4911                         break;
4912                 }
4913                 case OP_X86_LEA:
4914                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4915                         break;
4916                 case OP_X86_LEA_MEMBASE:
4917                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4918                         break;
4919                 case OP_X86_XCHG:
4920                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4921                         break;
4922                 case OP_LOCALLOC:
4923                         /* keep alignment */
4924                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4925                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4926                         code = mono_emit_stack_alloc (cfg, code, ins);
4927                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4928                         if (cfg->param_area && cfg->arch.no_pushes)
4929                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4930                         break;
4931                 case OP_LOCALLOC_IMM: {
4932                         guint32 size = ins->inst_imm;
4933                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4934
4935                         if (ins->flags & MONO_INST_INIT) {
4936                                 if (size < 64) {
4937                                         int i;
4938
4939                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4940                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4941
4942                                         for (i = 0; i < size; i += 8)
4943                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4944                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4945                                 } else {
4946                                         amd64_mov_reg_imm (code, ins->dreg, size);
4947                                         ins->sreg1 = ins->dreg;
4948
4949                                         code = mono_emit_stack_alloc (cfg, code, ins);
4950                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4951                                 }
4952                         } else {
4953                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4954                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4955                         }
4956                         if (cfg->param_area && cfg->arch.no_pushes)
4957                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4958                         break;
4959                 }
4960                 case OP_THROW: {
4961                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4962                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4963                                              (gpointer)"mono_arch_throw_exception", FALSE);
4964                         ins->flags |= MONO_INST_GC_CALLSITE;
4965                         ins->backend.pc_offset = code - cfg->native_code;
4966                         break;
4967                 }
4968                 case OP_RETHROW: {
4969                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4970                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4971                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4972                         ins->flags |= MONO_INST_GC_CALLSITE;
4973                         ins->backend.pc_offset = code - cfg->native_code;
4974                         break;
4975                 }
4976                 case OP_CALL_HANDLER:
4977                         /* Align stack */
4978                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4979                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4980                         amd64_call_imm (code, 0);
4981                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4982                         /* Restore stack alignment */
4983                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4984                         break;
4985                 case OP_START_HANDLER: {
4986                         /* Even though we're saving RSP, use sizeof */
4987                         /* gpointer because spvar is of type IntPtr */
4988                         /* see: mono_create_spvar_for_region */
4989                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4990                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4991
4992                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4993                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4994                                 cfg->param_area && cfg->arch.no_pushes) {
4995                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4996                         }
4997                         break;
4998                 }
4999                 case OP_ENDFINALLY: {
5000                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5001                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5002                         amd64_ret (code);
5003                         break;
5004                 }
5005                 case OP_ENDFILTER: {
5006                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5007                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5008                         /* The local allocator will put the result into RAX */
5009                         amd64_ret (code);
5010                         break;
5011                 }
5012
5013                 case OP_LABEL:
5014                         ins->inst_c0 = code - cfg->native_code;
5015                         break;
5016                 case OP_BR:
5017                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5018                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5019                         //break;
5020                                 if (ins->inst_target_bb->native_offset) {
5021                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5022                                 } else {
5023                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5024                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5025                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5026                                                 x86_jump8 (code, 0);
5027                                         else
5028                                                 x86_jump32 (code, 0);
5029                         }
5030                         break;
5031                 case OP_BR_REG:
5032                         amd64_jump_reg (code, ins->sreg1);
5033                         break;
5034                 case OP_ICNEQ:
5035                 case OP_ICGE:
5036                 case OP_ICLE:
5037                 case OP_ICGE_UN:
5038                 case OP_ICLE_UN:
5039
5040                 case OP_CEQ:
5041                 case OP_LCEQ:
5042                 case OP_ICEQ:
5043                 case OP_CLT:
5044                 case OP_LCLT:
5045                 case OP_ICLT:
5046                 case OP_CGT:
5047                 case OP_ICGT:
5048                 case OP_LCGT:
5049                 case OP_CLT_UN:
5050                 case OP_LCLT_UN:
5051                 case OP_ICLT_UN:
5052                 case OP_CGT_UN:
5053                 case OP_LCGT_UN:
5054                 case OP_ICGT_UN:
5055                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5056                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5057                         break;
5058                 case OP_COND_EXC_EQ:
5059                 case OP_COND_EXC_NE_UN:
5060                 case OP_COND_EXC_LT:
5061                 case OP_COND_EXC_LT_UN:
5062                 case OP_COND_EXC_GT:
5063                 case OP_COND_EXC_GT_UN:
5064                 case OP_COND_EXC_GE:
5065                 case OP_COND_EXC_GE_UN:
5066                 case OP_COND_EXC_LE:
5067                 case OP_COND_EXC_LE_UN:
5068                 case OP_COND_EXC_IEQ:
5069                 case OP_COND_EXC_INE_UN:
5070                 case OP_COND_EXC_ILT:
5071                 case OP_COND_EXC_ILT_UN:
5072                 case OP_COND_EXC_IGT:
5073                 case OP_COND_EXC_IGT_UN:
5074                 case OP_COND_EXC_IGE:
5075                 case OP_COND_EXC_IGE_UN:
5076                 case OP_COND_EXC_ILE:
5077                 case OP_COND_EXC_ILE_UN:
5078                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5079                         break;
5080                 case OP_COND_EXC_OV:
5081                 case OP_COND_EXC_NO:
5082                 case OP_COND_EXC_C:
5083                 case OP_COND_EXC_NC:
5084                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5085                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5086                         break;
5087                 case OP_COND_EXC_IOV:
5088                 case OP_COND_EXC_INO:
5089                 case OP_COND_EXC_IC:
5090                 case OP_COND_EXC_INC:
5091                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5092                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5093                         break;
5094
5095                 /* floating point opcodes */
5096                 case OP_R8CONST: {
5097                         double d = *(double *)ins->inst_p0;
5098
5099                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5100                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5101                         }
5102                         else {
5103                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5104                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5105                         }
5106                         break;
5107                 }
5108                 case OP_R4CONST: {
5109                         float f = *(float *)ins->inst_p0;
5110
5111                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5112                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5113                         }
5114                         else {
5115                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5116                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5117                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5118                         }
5119                         break;
5120                 }
5121                 case OP_STORER8_MEMBASE_REG:
5122                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5123                         break;
5124                 case OP_LOADR8_MEMBASE:
5125                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5126                         break;
5127                 case OP_STORER4_MEMBASE_REG:
5128                         /* This requires a double->single conversion */
5129                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
5130                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
5131                         break;
5132                 case OP_LOADR4_MEMBASE:
5133                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5134                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5135                         break;
5136                 case OP_ICONV_TO_R4:
5137                         amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5138                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5139                         break;
5140                 case OP_ICONV_TO_R8:
5141                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5142                         break;
5143                 case OP_LCONV_TO_R4:
5144                         amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5145                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5146                         break;
5147                 case OP_LCONV_TO_R8:
5148                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5149                         break;
5150                 case OP_FCONV_TO_R4:
5151                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5152                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5153                         break;
5154                 case OP_FCONV_TO_I1:
5155                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5156                         break;
5157                 case OP_FCONV_TO_U1:
5158                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5159                         break;
5160                 case OP_FCONV_TO_I2:
5161                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5162                         break;
5163                 case OP_FCONV_TO_U2:
5164                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5165                         break;
5166                 case OP_FCONV_TO_U4:
5167                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5168                         break;
5169                 case OP_FCONV_TO_I4:
5170                 case OP_FCONV_TO_I:
5171                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5172                         break;
5173                 case OP_FCONV_TO_I8:
5174                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5175                         break;
5176                 case OP_LCONV_TO_R_UN: {
5177                         guint8 *br [2];
5178
5179                         /* Based on gcc code */
5180                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5181                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5182
5183                         /* Positive case */
5184                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5185                         br [1] = code; x86_jump8 (code, 0);
5186                         amd64_patch (br [0], code);
5187
5188                         /* Negative case */
5189                         /* Save to the red zone */
5190                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5191                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5192                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5193                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5194                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5195                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5196                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5197                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5198                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5199                         /* Restore */
5200                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5201                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5202                         amd64_patch (br [1], code);
5203                         break;
5204                 }
5205                 case OP_LCONV_TO_OVF_U4:
5206                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5207                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5208                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5209                         break;
5210                 case OP_LCONV_TO_OVF_I4_UN:
5211                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5212                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5213                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5214                         break;
5215                 case OP_FMOVE:
5216                         if (ins->dreg != ins->sreg1)
5217                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5218                         break;
5219                 case OP_FADD:
5220                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5221                         break;
5222                 case OP_FSUB:
5223                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5224                         break;
5225                 case OP_FMUL:
5226                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5227                         break;
5228                 case OP_FDIV:
5229                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5230                         break;
5231                 case OP_FNEG: {
5232                         static double r8_0 = -0.0;
5233
5234                         g_assert (ins->sreg1 == ins->dreg);
5235
5236                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5237                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5238                         break;
5239                 }
5240                 case OP_SIN:
5241                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5242                         break;
5243                 case OP_COS:
5244                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5245                         break;
5246                 case OP_ABS: {
5247                         static guint64 d = 0x7fffffffffffffffUL;
5248
5249                         g_assert (ins->sreg1 == ins->dreg);
5250
5251                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5252                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5253                         break;
5254                 }
5255                 case OP_SQRT:
5256                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5257                         break;
5258                 case OP_IMIN:
5259                         g_assert (cfg->opt & MONO_OPT_CMOV);
5260                         g_assert (ins->dreg == ins->sreg1);
5261                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5262                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5263                         break;
5264                 case OP_IMIN_UN:
5265                         g_assert (cfg->opt & MONO_OPT_CMOV);
5266                         g_assert (ins->dreg == ins->sreg1);
5267                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5268                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5269                         break;
5270                 case OP_IMAX:
5271                         g_assert (cfg->opt & MONO_OPT_CMOV);
5272                         g_assert (ins->dreg == ins->sreg1);
5273                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5274                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5275                         break;
5276                 case OP_IMAX_UN:
5277                         g_assert (cfg->opt & MONO_OPT_CMOV);
5278                         g_assert (ins->dreg == ins->sreg1);
5279                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5280                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5281                         break;
5282                 case OP_LMIN:
5283                         g_assert (cfg->opt & MONO_OPT_CMOV);
5284                         g_assert (ins->dreg == ins->sreg1);
5285                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5286                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5287                         break;
5288                 case OP_LMIN_UN:
5289                         g_assert (cfg->opt & MONO_OPT_CMOV);
5290                         g_assert (ins->dreg == ins->sreg1);
5291                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5292                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5293                         break;
5294                 case OP_LMAX:
5295                         g_assert (cfg->opt & MONO_OPT_CMOV);
5296                         g_assert (ins->dreg == ins->sreg1);
5297                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5298                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5299                         break;
5300                 case OP_LMAX_UN:
5301                         g_assert (cfg->opt & MONO_OPT_CMOV);
5302                         g_assert (ins->dreg == ins->sreg1);
5303                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5304                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5305                         break;
5306                 case OP_X86_FPOP:
5307                         break;
5308                 case OP_FCOMPARE:
5309                         /*
5310                          * The two arguments are swapped because the fbranch instructions
5311                          * depend on this for the non-sse case to work.
5312                          */
5313                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5314                         break;
5315                 case OP_FCNEQ:
5316                 case OP_FCEQ: {
5317                         /* zeroing the register at the start results in
5318                          * shorter and faster code (we can also remove the widening op)
5319                          */
5320                         guchar *unordered_check;
5321                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5322                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5323                         unordered_check = code;
5324                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5325
5326                         if (ins->opcode == OP_FCEQ) {
5327                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5328                                 amd64_patch (unordered_check, code);
5329                         } else {
5330                                 guchar *jump_to_end;
5331                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5332                                 jump_to_end = code;
5333                                 x86_jump8 (code, 0);
5334                                 amd64_patch (unordered_check, code);
5335                                 amd64_inc_reg (code, ins->dreg);
5336                                 amd64_patch (jump_to_end, code);
5337                         }
5338                         break;
5339                 }
5340                 case OP_FCLT:
5341                 case OP_FCLT_UN:
5342                         /* zeroing the register at the start results in
5343                          * shorter and faster code (we can also remove the widening op)
5344                          */
5345                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5346                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5347                         if (ins->opcode == OP_FCLT_UN) {
5348                                 guchar *unordered_check = code;
5349                                 guchar *jump_to_end;
5350                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5351                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5352                                 jump_to_end = code;
5353                                 x86_jump8 (code, 0);
5354                                 amd64_patch (unordered_check, code);
5355                                 amd64_inc_reg (code, ins->dreg);
5356                                 amd64_patch (jump_to_end, code);
5357                         } else {
5358                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5359                         }
5360                         break;
5361                 case OP_FCLE: {
5362                         guchar *unordered_check;
5363                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5364                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5365                         unordered_check = code;
5366                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5367                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5368                         amd64_patch (unordered_check, code);
5369                         break;
5370                 }
5371                 case OP_FCGT:
5372                 case OP_FCGT_UN: {
5373                         /* zeroing the register at the start results in
5374                          * shorter and faster code (we can also remove the widening op)
5375                          */
5376                         guchar *unordered_check;
5377                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5378                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5379                         if (ins->opcode == OP_FCGT) {
5380                                 unordered_check = code;
5381                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5382                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5383                                 amd64_patch (unordered_check, code);
5384                         } else {
5385                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5386                         }
5387                         break;
5388                 }
5389                 case OP_FCGE: {
5390                         guchar *unordered_check;
5391                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5392                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5393                         unordered_check = code;
5394                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5395                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5396                         amd64_patch (unordered_check, code);
5397                         break;
5398                 }
5399
5400                 case OP_FCLT_MEMBASE:
5401                 case OP_FCGT_MEMBASE:
5402                 case OP_FCLT_UN_MEMBASE:
5403                 case OP_FCGT_UN_MEMBASE:
5404                 case OP_FCEQ_MEMBASE: {
5405                         guchar *unordered_check, *jump_to_end;
5406                         int x86_cond;
5407
5408                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5409                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5410
5411                         switch (ins->opcode) {
5412                         case OP_FCEQ_MEMBASE:
5413                                 x86_cond = X86_CC_EQ;
5414                                 break;
5415                         case OP_FCLT_MEMBASE:
5416                         case OP_FCLT_UN_MEMBASE:
5417                                 x86_cond = X86_CC_LT;
5418                                 break;
5419                         case OP_FCGT_MEMBASE:
5420                         case OP_FCGT_UN_MEMBASE:
5421                                 x86_cond = X86_CC_GT;
5422                                 break;
5423                         default:
5424                                 g_assert_not_reached ();
5425                         }
5426
5427                         unordered_check = code;
5428                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5429                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5430
5431                         switch (ins->opcode) {
5432                         case OP_FCEQ_MEMBASE:
5433                         case OP_FCLT_MEMBASE:
5434                         case OP_FCGT_MEMBASE:
5435                                 amd64_patch (unordered_check, code);
5436                                 break;
5437                         case OP_FCLT_UN_MEMBASE:
5438                         case OP_FCGT_UN_MEMBASE:
5439                                 jump_to_end = code;
5440                                 x86_jump8 (code, 0);
5441                                 amd64_patch (unordered_check, code);
5442                                 amd64_inc_reg (code, ins->dreg);
5443                                 amd64_patch (jump_to_end, code);
5444                                 break;
5445                         default:
5446                                 break;
5447                         }
5448                         break;
5449                 }
5450                 case OP_FBEQ: {
5451                         guchar *jump = code;
5452                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5453                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5454                         amd64_patch (jump, code);
5455                         break;
5456                 }
5457                 case OP_FBNE_UN:
5458                         /* Branch if C013 != 100 */
5459                         /* branch if !ZF or (PF|CF) */
5460                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5461                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5462                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5463                         break;
5464                 case OP_FBLT:
5465                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5466                         break;
5467                 case OP_FBLT_UN:
5468                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5469                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5470                         break;
5471                 case OP_FBGT:
5472                 case OP_FBGT_UN:
5473                         if (ins->opcode == OP_FBGT) {
5474                                 guchar *br1;
5475
5476                                 /* skip branch if C1=1 */
5477                                 br1 = code;
5478                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5479                                 /* branch if (C0 | C3) = 1 */
5480                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5481                                 amd64_patch (br1, code);
5482                                 break;
5483                         } else {
5484                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5485                         }
5486                         break;
5487                 case OP_FBGE: {
5488                         /* Branch if C013 == 100 or 001 */
5489                         guchar *br1;
5490
5491                         /* skip branch if C1=1 */
5492                         br1 = code;
5493                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5494                         /* branch if (C0 | C3) = 1 */
5495                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5496                         amd64_patch (br1, code);
5497                         break;
5498                 }
5499                 case OP_FBGE_UN:
5500                         /* Branch if C013 == 000 */
5501                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5502                         break;
5503                 case OP_FBLE: {
5504                         /* Branch if C013=000 or 100 */
5505                         guchar *br1;
5506
5507                         /* skip branch if C1=1 */
5508                         br1 = code;
5509                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5510                         /* branch if C0=0 */
5511                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5512                         amd64_patch (br1, code);
5513                         break;
5514                 }
5515                 case OP_FBLE_UN:
5516                         /* Branch if C013 != 001 */
5517                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5518                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5519                         break;
5520                 case OP_CKFINITE:
5521                         /* Transfer value to the fp stack */
5522                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5523                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5524                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5525
5526                         amd64_push_reg (code, AMD64_RAX);
5527                         amd64_fxam (code);
5528                         amd64_fnstsw (code);
5529                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5530                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5531                         amd64_pop_reg (code, AMD64_RAX);
5532                         amd64_fstp (code, 0);
5533                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5534                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5535                         break;
5536                 case OP_TLS_GET: {
5537                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5538                         break;
5539                 }
5540                 case OP_TLS_GET_REG:
5541                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5542                         break;
5543                 case OP_TLS_SET: {
5544                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5545                         break;
5546                 }
5547                 case OP_TLS_SET_REG: {
5548                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5549                         break;
5550                 }
5551                 case OP_MEMORY_BARRIER: {
5552                         switch (ins->backend.memory_barrier_kind) {
5553                         case StoreLoadBarrier:
5554                         case FullBarrier:
5555                                 /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
5556                                 x86_prefix (code, X86_LOCK_PREFIX);
5557                                 amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
5558                                 break;
5559                         }
5560                         break;
5561                 }
5562                 case OP_ATOMIC_ADD_I4:
5563                 case OP_ATOMIC_ADD_I8: {
5564                         int dreg = ins->dreg;
5565                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5566
5567                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5568                                 dreg = AMD64_R11;
5569
5570                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5571                         amd64_prefix (code, X86_LOCK_PREFIX);
5572                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5573                         /* dreg contains the old value, add with sreg2 value */
5574                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5575
5576                         if (ins->dreg != dreg)
5577                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5578
5579                         break;
5580                 }
5581                 case OP_ATOMIC_EXCHANGE_I4:
5582                 case OP_ATOMIC_EXCHANGE_I8: {
5583                         guchar *br[2];
5584                         int sreg2 = ins->sreg2;
5585                         int breg = ins->inst_basereg;
5586                         guint32 size;
5587                         gboolean need_push = FALSE, rdx_pushed = FALSE;
5588
5589                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
5590                                 size = 8;
5591                         else
5592                                 size = 4;
5593
5594                         /*
5595                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5596                          * an explanation of how this works.
5597                          */
5598
5599                         /* cmpxchg uses eax as comperand, need to make sure we can use it
5600                          * hack to overcome limits in x86 reg allocator
5601                          * (req: dreg == eax and sreg2 != eax and breg != eax)
5602                          */
5603                         g_assert (ins->dreg == AMD64_RAX);
5604
5605                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
5606                                 /* Highly unlikely, but possible */
5607                                 need_push = TRUE;
5608
5609                         /* The pushes invalidate rsp */
5610                         if ((breg == AMD64_RAX) || need_push) {
5611                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
5612                                 breg = AMD64_R11;
5613                         }
5614
5615                         /* We need the EAX reg for the comparand */
5616                         if (ins->sreg2 == AMD64_RAX) {
5617                                 if (breg != AMD64_R11) {
5618                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5619                                         sreg2 = AMD64_R11;
5620                                 } else {
5621                                         g_assert (need_push);
5622                                         amd64_push_reg (code, AMD64_RDX);
5623                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
5624                                         sreg2 = AMD64_RDX;
5625                                         rdx_pushed = TRUE;
5626                                 }
5627                         }
5628
5629                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
5630
5631                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
5632                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
5633                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
5634                         amd64_patch (br [1], br [0]);
5635
5636                         if (rdx_pushed)
5637                                 amd64_pop_reg (code, AMD64_RDX);
5638
5639                         break;
5640                 }
5641                 case OP_ATOMIC_CAS_I4:
5642                 case OP_ATOMIC_CAS_I8: {
5643                         guint32 size;
5644
5645                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5646                                 size = 8;
5647                         else
5648                                 size = 4;
5649
5650                         /*
5651                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5652                          * an explanation of how this works.
5653                          */
5654                         g_assert (ins->sreg3 == AMD64_RAX);
5655                         g_assert (ins->sreg1 != AMD64_RAX);
5656                         g_assert (ins->sreg1 != ins->sreg2);
5657
5658                         amd64_prefix (code, X86_LOCK_PREFIX);
5659                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5660
5661                         if (ins->dreg != AMD64_RAX)
5662                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5663                         break;
5664                 }
5665                 case OP_CARD_TABLE_WBARRIER: {
5666                         int ptr = ins->sreg1;
5667                         int value = ins->sreg2;
5668                         guchar *br = 0;
5669                         int nursery_shift, card_table_shift;
5670                         gpointer card_table_mask;
5671                         size_t nursery_size;
5672
5673                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5674                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5675                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5676
5677                         /*If either point to the stack we can simply avoid the WB. This happens due to
5678                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5679                          */
5680                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5681                                 continue;
5682
5683                         /*
5684                          * We need one register we can clobber, we choose EDX and make sreg1
5685                          * fixed EAX to work around limitations in the local register allocator.
5686                          * sreg2 might get allocated to EDX, but that is not a problem since
5687                          * we use it before clobbering EDX.
5688                          */
5689                         g_assert (ins->sreg1 == AMD64_RAX);
5690
5691                         /*
5692                          * This is the code we produce:
5693                          *
5694                          *   edx = value
5695                          *   edx >>= nursery_shift
5696                          *   cmp edx, (nursery_start >> nursery_shift)
5697                          *   jne done
5698                          *   edx = ptr
5699                          *   edx >>= card_table_shift
5700                          *   edx += cardtable
5701                          *   [edx] = 1
5702                          * done:
5703                          */
5704
5705                         if (mono_gc_card_table_nursery_check ()) {
5706                                 if (value != AMD64_RDX)
5707                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5708                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5709                                 if (shifted_nursery_start >> 31) {
5710                                         /*
5711                                          * The value we need to compare against is 64 bits, so we need
5712                                          * another spare register.  We use RBX, which we save and
5713                                          * restore.
5714                                          */
5715                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5716                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5717                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5718                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5719                                 } else {
5720                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5721                                 }
5722                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5723                         }
5724                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5725                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5726                         if (card_table_mask)
5727                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5728
5729                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5730                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5731
5732                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5733
5734                         if (mono_gc_card_table_nursery_check ())
5735                                 x86_patch (br, code);
5736                         break;
5737                 }
5738 #ifdef MONO_ARCH_SIMD_INTRINSICS
5739                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5740                 case OP_ADDPS:
5741                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5742                         break;
5743                 case OP_DIVPS:
5744                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5745                         break;
5746                 case OP_MULPS:
5747                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5748                         break;
5749                 case OP_SUBPS:
5750                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5751                         break;
5752                 case OP_MAXPS:
5753                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5754                         break;
5755                 case OP_MINPS:
5756                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5757                         break;
5758                 case OP_COMPPS:
5759                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5760                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5761                         break;
5762                 case OP_ANDPS:
5763                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5764                         break;
5765                 case OP_ANDNPS:
5766                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5767                         break;
5768                 case OP_ORPS:
5769                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5770                         break;
5771                 case OP_XORPS:
5772                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5773                         break;
5774                 case OP_SQRTPS:
5775                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5776                         break;
5777                 case OP_RSQRTPS:
5778                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5779                         break;
5780                 case OP_RCPPS:
5781                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5782                         break;
5783                 case OP_ADDSUBPS:
5784                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5785                         break;
5786                 case OP_HADDPS:
5787                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5788                         break;
5789                 case OP_HSUBPS:
5790                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5791                         break;
5792                 case OP_DUPPS_HIGH:
5793                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5794                         break;
5795                 case OP_DUPPS_LOW:
5796                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5797                         break;
5798
5799                 case OP_PSHUFLEW_HIGH:
5800                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5801                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5802                         break;
5803                 case OP_PSHUFLEW_LOW:
5804                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5805                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5806                         break;
5807                 case OP_PSHUFLED:
5808                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5809                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5810                         break;
5811                 case OP_SHUFPS:
5812                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5813                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5814                         break;
5815                 case OP_SHUFPD:
5816                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5817                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5818                         break;
5819
5820                 case OP_ADDPD:
5821                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5822                         break;
5823                 case OP_DIVPD:
5824                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5825                         break;
5826                 case OP_MULPD:
5827                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5828                         break;
5829                 case OP_SUBPD:
5830                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5831                         break;
5832                 case OP_MAXPD:
5833                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5834                         break;
5835                 case OP_MINPD:
5836                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5837                         break;
5838                 case OP_COMPPD:
5839                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5840                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5841                         break;
5842                 case OP_ANDPD:
5843                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5844                         break;
5845                 case OP_ANDNPD:
5846                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5847                         break;
5848                 case OP_ORPD:
5849                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5850                         break;
5851                 case OP_XORPD:
5852                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5853                         break;
5854                 case OP_SQRTPD:
5855                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5856                         break;
5857                 case OP_ADDSUBPD:
5858                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5859                         break;
5860                 case OP_HADDPD:
5861                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5862                         break;
5863                 case OP_HSUBPD:
5864                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5865                         break;
5866                 case OP_DUPPD:
5867                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5868                         break;
5869
5870                 case OP_EXTRACT_MASK:
5871                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5872                         break;
5873
5874                 case OP_PAND:
5875                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5876                         break;
5877                 case OP_POR:
5878                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5879                         break;
5880                 case OP_PXOR:
5881                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5882                         break;
5883
5884                 case OP_PADDB:
5885                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5886                         break;
5887                 case OP_PADDW:
5888                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5889                         break;
5890                 case OP_PADDD:
5891                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5892                         break;
5893                 case OP_PADDQ:
5894                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5895                         break;
5896
5897                 case OP_PSUBB:
5898                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5899                         break;
5900                 case OP_PSUBW:
5901                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5902                         break;
5903                 case OP_PSUBD:
5904                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5905                         break;
5906                 case OP_PSUBQ:
5907                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5908                         break;
5909
5910                 case OP_PMAXB_UN:
5911                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5912                         break;
5913                 case OP_PMAXW_UN:
5914                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5915                         break;
5916                 case OP_PMAXD_UN:
5917                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5918                         break;
5919
5920                 case OP_PMAXB:
5921                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_PMAXW:
5924                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_PMAXD:
5927                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929
5930                 case OP_PAVGB_UN:
5931                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5932                         break;
5933                 case OP_PAVGW_UN:
5934                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5935                         break;
5936
5937                 case OP_PMINB_UN:
5938                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5939                         break;
5940                 case OP_PMINW_UN:
5941                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5942                         break;
5943                 case OP_PMIND_UN:
5944                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946
5947                 case OP_PMINB:
5948                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5949                         break;
5950                 case OP_PMINW:
5951                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5952                         break;
5953                 case OP_PMIND:
5954                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5955                         break;
5956
5957                 case OP_PCMPEQB:
5958                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5959                         break;
5960                 case OP_PCMPEQW:
5961                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963                 case OP_PCMPEQD:
5964                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5965                         break;
5966                 case OP_PCMPEQQ:
5967                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5968                         break;
5969
5970                 case OP_PCMPGTB:
5971                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5972                         break;
5973                 case OP_PCMPGTW:
5974                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5975                         break;
5976                 case OP_PCMPGTD:
5977                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5978                         break;
5979                 case OP_PCMPGTQ:
5980                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5981                         break;
5982
5983                 case OP_PSUM_ABS_DIFF:
5984                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5985                         break;
5986
5987                 case OP_UNPACK_LOWB:
5988                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990                 case OP_UNPACK_LOWW:
5991                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5992                         break;
5993                 case OP_UNPACK_LOWD:
5994                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5995                         break;
5996                 case OP_UNPACK_LOWQ:
5997                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5998                         break;
5999                 case OP_UNPACK_LOWPS:
6000                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6001                         break;
6002                 case OP_UNPACK_LOWPD:
6003                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005
6006                 case OP_UNPACK_HIGHB:
6007                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_UNPACK_HIGHW:
6010                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_UNPACK_HIGHD:
6013                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6014                         break;
6015                 case OP_UNPACK_HIGHQ:
6016                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6017                         break;
6018                 case OP_UNPACK_HIGHPS:
6019                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6020                         break;
6021                 case OP_UNPACK_HIGHPD:
6022                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024
6025                 case OP_PACKW:
6026                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028                 case OP_PACKD:
6029                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6030                         break;
6031                 case OP_PACKW_UN:
6032                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_PACKD_UN:
6035                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037
6038                 case OP_PADDB_SAT_UN:
6039                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6040                         break;
6041                 case OP_PSUBB_SAT_UN:
6042                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6043                         break;
6044                 case OP_PADDW_SAT_UN:
6045                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_PSUBW_SAT_UN:
6048                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6049                         break;
6050
6051                 case OP_PADDB_SAT:
6052                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_PSUBB_SAT:
6055                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057                 case OP_PADDW_SAT:
6058                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_PSUBW_SAT:
6061                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063
6064                 case OP_PMULW:
6065                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_PMULD:
6068                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070                 case OP_PMULQ:
6071                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PMULW_HIGH_UN:
6074                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076                 case OP_PMULW_HIGH:
6077                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079
6080                 case OP_PSHRW:
6081                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6082                         break;
6083                 case OP_PSHRW_REG:
6084                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6085                         break;
6086
6087                 case OP_PSARW:
6088                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6089                         break;
6090                 case OP_PSARW_REG:
6091                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6092                         break;
6093
6094                 case OP_PSHLW:
6095                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6096                         break;
6097                 case OP_PSHLW_REG:
6098                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6099                         break;
6100
6101                 case OP_PSHRD:
6102                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6103                         break;
6104                 case OP_PSHRD_REG:
6105                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6106                         break;
6107
6108                 case OP_PSARD:
6109                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6110                         break;
6111                 case OP_PSARD_REG:
6112                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6113                         break;
6114
6115                 case OP_PSHLD:
6116                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6117                         break;
6118                 case OP_PSHLD_REG:
6119                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6120                         break;
6121
6122                 case OP_PSHRQ:
6123                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6124                         break;
6125                 case OP_PSHRQ_REG:
6126                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6127                         break;
6128
6129                 /*TODO: This is appart of the sse spec but not added
6130                 case OP_PSARQ:
6131                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6132                         break;
6133                 case OP_PSARQ_REG:
6134                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6135                         break;
6136                 */
6137
6138                 case OP_PSHLQ:
6139                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6140                         break;
6141                 case OP_PSHLQ_REG:
6142                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6143                         break;
6144                 case OP_CVTDQ2PD:
6145                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6146                         break;
6147                 case OP_CVTDQ2PS:
6148                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6149                         break;
6150                 case OP_CVTPD2DQ:
6151                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6152                         break;
6153                 case OP_CVTPD2PS:
6154                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6155                         break;
6156                 case OP_CVTPS2DQ:
6157                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6158                         break;
6159                 case OP_CVTPS2PD:
6160                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6161                         break;
6162                 case OP_CVTTPD2DQ:
6163                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6164                         break;
6165                 case OP_CVTTPS2DQ:
6166                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6167                         break;
6168
6169                 case OP_ICONV_TO_X:
6170                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6171                         break;
6172                 case OP_EXTRACT_I4:
6173                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6174                         break;
6175                 case OP_EXTRACT_I8:
6176                         if (ins->inst_c0) {
6177                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
6178                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
6179                         } else {
6180                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6181                         }
6182                         break;
6183                 case OP_EXTRACT_I1:
6184                 case OP_EXTRACT_U1:
6185                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6186                         if (ins->inst_c0)
6187                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6188                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6189                         break;
6190                 case OP_EXTRACT_I2:
6191                 case OP_EXTRACT_U2:
6192                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6193                         if (ins->inst_c0)
6194                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6195                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6196                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6197                         break;
6198                 case OP_EXTRACT_R8:
6199                         if (ins->inst_c0)
6200                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6201                         else
6202                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6203                         break;
6204                 case OP_INSERT_I2:
6205                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6206                         break;
6207                 case OP_EXTRACTX_U2:
6208                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6209                         break;
6210                 case OP_INSERTX_U1_SLOW:
6211                         /*sreg1 is the extracted ireg (scratch)
6212                         /sreg2 is the to be inserted ireg (scratch)
6213                         /dreg is the xreg to receive the value*/
6214
6215                         /*clear the bits from the extracted word*/
6216                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6217                         /*shift the value to insert if needed*/
6218                         if (ins->inst_c0 & 1)
6219                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6220                         /*join them together*/
6221                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6222                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6223                         break;
6224                 case OP_INSERTX_I4_SLOW:
6225                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6226                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6227                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6228                         break;
6229                 case OP_INSERTX_I8_SLOW:
6230                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
6231                         if (ins->inst_c0)
6232                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
6233                         else
6234                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
6235                         break;
6236
6237                 case OP_INSERTX_R4_SLOW:
6238                         switch (ins->inst_c0) {
6239                         case 0:
6240                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6241                                 break;
6242                         case 1:
6243                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6244                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6245                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6246                                 break;
6247                         case 2:
6248                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6249                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6250                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6251                                 break;
6252                         case 3:
6253                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6254                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6255                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6256                                 break;
6257                         }
6258                         break;
6259                 case OP_INSERTX_R8_SLOW:
6260                         if (ins->inst_c0)
6261                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6262                         else
6263                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6264                         break;
6265                 case OP_STOREX_MEMBASE_REG:
6266                 case OP_STOREX_MEMBASE:
6267                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6268                         break;
6269                 case OP_LOADX_MEMBASE:
6270                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6271                         break;
6272                 case OP_LOADX_ALIGNED_MEMBASE:
6273                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6274                         break;
6275                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6276                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6277                         break;
6278                 case OP_STOREX_NTA_MEMBASE_REG:
6279                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6280                         break;
6281                 case OP_PREFETCH_MEMBASE:
6282                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6283                         break;
6284
6285                 case OP_XMOVE:
6286                         /*FIXME the peephole pass should have killed this*/
6287                         if (ins->dreg != ins->sreg1)
6288                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6289                         break;
6290                 case OP_XZERO:
6291                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6292                         break;
6293                 case OP_ICONV_TO_R8_RAW:
6294                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6295                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6296                         break;
6297
6298                 case OP_FCONV_TO_R8_X:
6299                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6300                         break;
6301
6302                 case OP_XCONV_R8_TO_I4:
6303                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6304                         switch (ins->backend.source_opcode) {
6305                         case OP_FCONV_TO_I1:
6306                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6307                                 break;
6308                         case OP_FCONV_TO_U1:
6309                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6310                                 break;
6311                         case OP_FCONV_TO_I2:
6312                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6313                                 break;
6314                         case OP_FCONV_TO_U2:
6315                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6316                                 break;
6317                         }
6318                         break;
6319
6320                 case OP_EXPAND_I2:
6321                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6322                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6323                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6324                         break;
6325                 case OP_EXPAND_I4:
6326                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6327                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6328                         break;
6329                 case OP_EXPAND_I8:
6330                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6331                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6332                         break;
6333                 case OP_EXPAND_R4:
6334                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6335                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6336                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6337                         break;
6338                 case OP_EXPAND_R8:
6339                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6340                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6341                         break;
6342 #endif
6343                 case OP_LIVERANGE_START: {
6344                         if (cfg->verbose_level > 1)
6345                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6346                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6347                         break;
6348                 }
6349                 case OP_LIVERANGE_END: {
6350                         if (cfg->verbose_level > 1)
6351                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6352                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6353                         break;
6354                 }
6355                 case OP_NACL_GC_SAFE_POINT: {
6356 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6357                         if (cfg->compile_aot)
6358                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6359                         else {
6360                                 guint8 *br [1];
6361
6362                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6363                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6364                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6365                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6366                                 amd64_patch (br[0], code);
6367                         }
6368 #endif
6369                         break;
6370                 }
6371                 case OP_GC_LIVENESS_DEF:
6372                 case OP_GC_LIVENESS_USE:
6373                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6374                         ins->backend.pc_offset = code - cfg->native_code;
6375                         break;
6376                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6377                         ins->backend.pc_offset = code - cfg->native_code;
6378                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6379                         break;
6380                 default:
6381                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6382                         g_assert_not_reached ();
6383                 }
6384
6385                 if ((code - cfg->native_code - offset) > max_len) {
6386 #if !defined(__native_client_codegen__)
6387                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6388                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6389                         g_assert_not_reached ();
6390 #endif
6391                 }
6392
6393                 last_ins = ins;
6394                 last_offset = offset;
6395         }
6396
6397         cfg->code_len = code - cfg->native_code;
6398 }
6399
6400 #endif /* DISABLE_JIT */
6401
6402 void
6403 mono_arch_register_lowlevel_calls (void)
6404 {
6405         /* The signature doesn't matter */
6406         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6407 }
6408
6409 void
6410 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6411 {
6412         MonoJumpInfo *patch_info;
6413         gboolean compile_aot = !run_cctors;
6414
6415         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6416                 unsigned char *ip = patch_info->ip.i + code;
6417                 unsigned char *target;
6418
6419                 if (compile_aot) {
6420                         switch (patch_info->type) {
6421                         case MONO_PATCH_INFO_BB:
6422                         case MONO_PATCH_INFO_LABEL:
6423                                 break;
6424                         default:
6425                                 /* No need to patch these */
6426                                 continue;
6427                         }
6428                 }
6429
6430                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6431
6432                 switch (patch_info->type) {
6433                 case MONO_PATCH_INFO_NONE:
6434                         continue;
6435                 case MONO_PATCH_INFO_METHOD_REL:
6436                 case MONO_PATCH_INFO_R8:
6437                 case MONO_PATCH_INFO_R4:
6438                         g_assert_not_reached ();
6439                         continue;
6440                 case MONO_PATCH_INFO_BB:
6441                         break;
6442                 default:
6443                         break;
6444                 }
6445
6446                 /*
6447                  * Debug code to help track down problems where the target of a near call is
6448                  * is not valid.
6449                  */
6450                 if (amd64_is_near_call (ip)) {
6451                         gint64 disp = (guint8*)target - (guint8*)ip;
6452
6453                         if (!amd64_is_imm32 (disp)) {
6454                                 printf ("TYPE: %d\n", patch_info->type);
6455                                 switch (patch_info->type) {
6456                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6457                                         printf ("V: %s\n", patch_info->data.name);
6458                                         break;
6459                                 case MONO_PATCH_INFO_METHOD_JUMP:
6460                                 case MONO_PATCH_INFO_METHOD:
6461                                         printf ("V: %s\n", patch_info->data.method->name);
6462                                         break;
6463                                 default:
6464                                         break;
6465                                 }
6466                         }
6467                 }
6468
6469                 amd64_patch (ip, (gpointer)target);
6470         }
6471 }
6472
6473 #ifndef DISABLE_JIT
6474
6475 static int
6476 get_max_epilog_size (MonoCompile *cfg)
6477 {
6478         int max_epilog_size = 16;
6479
6480         if (cfg->method->save_lmf)
6481                 max_epilog_size += 256;
6482
6483         if (mono_jit_trace_calls != NULL)
6484                 max_epilog_size += 50;
6485
6486         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6487                 max_epilog_size += 50;
6488
6489         max_epilog_size += (AMD64_NREG * 2);
6490
6491         return max_epilog_size;
6492 }
6493
6494 /*
6495  * This macro is used for testing whenever the unwinder works correctly at every point
6496  * where an async exception can happen.
6497  */
6498 /* This will generate a SIGSEGV at the given point in the code */
6499 #define async_exc_point(code) do { \
6500     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6501          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6502              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6503          cfg->arch.async_point_count ++; \
6504     } \
6505 } while (0)
6506
6507 guint8 *
6508 mono_arch_emit_prolog (MonoCompile *cfg)
6509 {
6510         MonoMethod *method = cfg->method;
6511         MonoBasicBlock *bb;
6512         MonoMethodSignature *sig;
6513         MonoInst *ins;
6514         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6515         guint8 *code;
6516         CallInfo *cinfo;
6517         MonoInst *lmf_var = cfg->lmf_var;
6518         gboolean args_clobbered = FALSE;
6519         gboolean trace = FALSE;
6520 #ifdef __native_client_codegen__
6521         guint alignment_check;
6522 #endif
6523
6524         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
6525
6526 #if defined(__default_codegen__)
6527         code = cfg->native_code = g_malloc (cfg->code_size);
6528 #elif defined(__native_client_codegen__)
6529         /* native_code_alloc is not 32-byte aligned, native_code is. */
6530         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6531
6532         /* Align native_code to next nearest kNaclAlignment byte. */
6533         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6534         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6535
6536         code = cfg->native_code;
6537
6538         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6539         g_assert (alignment_check == 0);
6540 #endif
6541
6542         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6543                 trace = TRUE;
6544
6545         /* Amount of stack space allocated by register saving code */
6546         pos = 0;
6547
6548         /* Offset between RSP and the CFA */
6549         cfa_offset = 0;
6550
6551         /*
6552          * The prolog consists of the following parts:
6553          * FP present:
6554          * - push rbp, mov rbp, rsp
6555          * - save callee saved regs using pushes
6556          * - allocate frame
6557          * - save rgctx if needed
6558          * - save lmf if needed
6559          * FP not present:
6560          * - allocate frame
6561          * - save rgctx if needed
6562          * - save lmf if needed
6563          * - save callee saved regs using moves
6564          */
6565
6566         // CFA = sp + 8
6567         cfa_offset = 8;
6568         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6569         // IP saved at CFA - 8
6570         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6571         async_exc_point (code);
6572         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6573
6574         if (!cfg->arch.omit_fp) {
6575                 amd64_push_reg (code, AMD64_RBP);
6576                 cfa_offset += 8;
6577                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6578                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6579                 async_exc_point (code);
6580 #ifdef HOST_WIN32
6581                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6582 #endif
6583                 /* These are handled automatically by the stack marking code */
6584                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6585
6586                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6587                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6588                 async_exc_point (code);
6589 #ifdef HOST_WIN32
6590                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6591 #endif
6592         }
6593
6594         /* The param area is always at offset 0 from sp */
6595         /* This needs to be allocated here, since it has to come after the spill area */
6596         if (cfg->arch.no_pushes && cfg->param_area) {
6597                 if (cfg->arch.omit_fp)
6598                         // FIXME:
6599                         g_assert_not_reached ();
6600                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6601         }
6602
6603         if (cfg->arch.omit_fp) {
6604                 /*
6605                  * On enter, the stack is misaligned by the pushing of the return
6606                  * address. It is either made aligned by the pushing of %rbp, or by
6607                  * this.
6608                  */
6609                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6610                 if ((alloc_size % 16) == 0) {
6611                         alloc_size += 8;
6612                         /* Mark the padding slot as NOREF */
6613                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6614                 }
6615         } else {
6616                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6617                 if (cfg->stack_offset != alloc_size) {
6618                         /* Mark the padding slot as NOREF */
6619                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6620                 }
6621                 cfg->arch.sp_fp_offset = alloc_size;
6622                 alloc_size -= pos;
6623         }
6624
6625         cfg->arch.stack_alloc_size = alloc_size;
6626
6627         /* Allocate stack frame */
6628         if (alloc_size) {
6629                 /* See mono_emit_stack_alloc */
6630 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6631                 guint32 remaining_size = alloc_size;
6632                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6633                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6634                 guint32 offset = code - cfg->native_code;
6635                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6636                         while (required_code_size >= (cfg->code_size - offset))
6637                                 cfg->code_size *= 2;
6638                         cfg->native_code = mono_realloc_native_code (cfg);
6639                         code = cfg->native_code + offset;
6640                         cfg->stat_code_reallocs++;
6641                 }
6642
6643                 while (remaining_size >= 0x1000) {
6644                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6645                         if (cfg->arch.omit_fp) {
6646                                 cfa_offset += 0x1000;
6647                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6648                         }
6649                         async_exc_point (code);
6650 #ifdef HOST_WIN32
6651                         if (cfg->arch.omit_fp)
6652                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6653 #endif
6654
6655                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6656                         remaining_size -= 0x1000;
6657                 }
6658                 if (remaining_size) {
6659                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6660                         if (cfg->arch.omit_fp) {
6661                                 cfa_offset += remaining_size;
6662                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6663                                 async_exc_point (code);
6664                         }
6665 #ifdef HOST_WIN32
6666                         if (cfg->arch.omit_fp)
6667                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6668 #endif
6669                 }
6670 #else
6671                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6672                 if (cfg->arch.omit_fp) {
6673                         cfa_offset += alloc_size;
6674                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6675                         async_exc_point (code);
6676                 }
6677 #endif
6678         }
6679
6680         /* Stack alignment check */
6681 #if 0
6682         {
6683                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6684                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6685                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6686                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6687                 amd64_breakpoint (code);
6688         }
6689 #endif
6690
6691         if (mini_get_debug_options ()->init_stacks) {
6692                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6693
6694                 /* Save registers to the red zone */
6695                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6696                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6697
6698                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6699                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6700                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6701
6702                 amd64_cld (code);
6703 #if defined(__default_codegen__)
6704                 amd64_prefix (code, X86_REP_PREFIX);
6705                 amd64_stosl (code);
6706 #elif defined(__native_client_codegen__)
6707                 /* NaCl stos pseudo-instruction */
6708                 amd64_codegen_pre (code);
6709                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6710                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6711                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6712                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6713                 amd64_prefix (code, X86_REP_PREFIX);
6714                 amd64_stosl (code);
6715                 amd64_codegen_post (code);
6716 #endif /* __native_client_codegen__ */
6717
6718                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6719                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6720         }
6721
6722         /* Save LMF */
6723         if (method->save_lmf)
6724                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6725
6726         /* Save callee saved registers */
6727         if (cfg->arch.omit_fp) {
6728                 save_area_offset = cfg->arch.reg_save_area_offset;
6729                 /* Save caller saved registers after sp is adjusted */
6730                 /* The registers are saved at the bottom of the frame */
6731                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6732         } else {
6733                 /* The registers are saved just below the saved rbp */
6734                 save_area_offset = cfg->arch.reg_save_area_offset;
6735         }
6736
6737         for (i = 0; i < AMD64_NREG; ++i) {
6738                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6739                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6740
6741                         if (cfg->arch.omit_fp) {
6742                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6743                                 /* These are handled automatically by the stack marking code */
6744                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6745                         } else {
6746                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6747                                 // FIXME: GC
6748                         }
6749
6750                         save_area_offset += 8;
6751                         async_exc_point (code);
6752                 }
6753         }
6754
6755         /* store runtime generic context */
6756         if (cfg->rgctx_var) {
6757                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6758                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6759
6760                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6761
6762                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6763                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6764         }
6765
6766         /* compute max_length in order to use short forward jumps */
6767         max_epilog_size = get_max_epilog_size (cfg);
6768         if (cfg->opt & MONO_OPT_BRANCH) {
6769                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6770                         MonoInst *ins;
6771                         int max_length = 0;
6772
6773                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6774                                 max_length += 6;
6775                         /* max alignment for loops */
6776                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6777                                 max_length += LOOP_ALIGNMENT;
6778 #ifdef __native_client_codegen__
6779                         /* max alignment for native client */
6780                         max_length += kNaClAlignment;
6781 #endif
6782
6783                         MONO_BB_FOR_EACH_INS (bb, ins) {
6784 #ifdef __native_client_codegen__
6785                                 {
6786                                         int space_in_block = kNaClAlignment -
6787                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6788                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6789                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6790                                                 max_length += space_in_block;
6791                                         }
6792                                 }
6793 #endif  /*__native_client_codegen__*/
6794                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6795                         }
6796
6797                         /* Take prolog and epilog instrumentation into account */
6798                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6799                                 max_length += max_epilog_size;
6800
6801                         bb->max_length = max_length;
6802                 }
6803         }
6804
6805         sig = mono_method_signature (method);
6806         pos = 0;
6807
6808         cinfo = cfg->arch.cinfo;
6809
6810         if (sig->ret->type != MONO_TYPE_VOID) {
6811                 /* Save volatile arguments to the stack */
6812                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6813                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6814         }
6815
6816         /* Keep this in sync with emit_load_volatile_arguments */
6817         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6818                 ArgInfo *ainfo = cinfo->args + i;
6819                 gint32 stack_offset;
6820                 MonoType *arg_type;
6821
6822                 ins = cfg->args [i];
6823
6824                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6825                         /* Unused arguments */
6826                         continue;
6827
6828                 if (sig->hasthis && (i == 0))
6829                         arg_type = &mono_defaults.object_class->byval_arg;
6830                 else
6831                         arg_type = sig->params [i - sig->hasthis];
6832
6833                 stack_offset = ainfo->offset + ARGS_OFFSET;
6834
6835                 if (cfg->globalra) {
6836                         /* All the other moves are done by the register allocator */
6837                         switch (ainfo->storage) {
6838                         case ArgInFloatSSEReg:
6839                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6840                                 break;
6841                         case ArgValuetypeInReg:
6842                                 for (quad = 0; quad < 2; quad ++) {
6843                                         switch (ainfo->pair_storage [quad]) {
6844                                         case ArgInIReg:
6845                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6846                                                 break;
6847                                         case ArgInFloatSSEReg:
6848                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6849                                                 break;
6850                                         case ArgInDoubleSSEReg:
6851                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6852                                                 break;
6853                                         case ArgNone:
6854                                                 break;
6855                                         default:
6856                                                 g_assert_not_reached ();
6857                                         }
6858                                 }
6859                                 break;
6860                         default:
6861                                 break;
6862                         }
6863
6864                         continue;
6865                 }
6866
6867                 /* Save volatile arguments to the stack */
6868                 if (ins->opcode != OP_REGVAR) {
6869                         switch (ainfo->storage) {
6870                         case ArgInIReg: {
6871                                 guint32 size = 8;
6872
6873                                 /* FIXME: I1 etc */
6874                                 /*
6875                                 if (stack_offset & 0x1)
6876                                         size = 1;
6877                                 else if (stack_offset & 0x2)
6878                                         size = 2;
6879                                 else if (stack_offset & 0x4)
6880                                         size = 4;
6881                                 else
6882                                         size = 8;
6883                                 */
6884                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6885
6886                                 /*
6887                                  * Save the original location of 'this',
6888                                  * get_generic_info_from_stack_frame () needs this to properly look up
6889                                  * the argument value during the handling of async exceptions.
6890                                  */
6891                                 if (ins == cfg->args [0]) {
6892                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6893                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6894                                 }
6895                                 break;
6896                         }
6897                         case ArgInFloatSSEReg:
6898                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6899                                 break;
6900                         case ArgInDoubleSSEReg:
6901                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6902                                 break;
6903                         case ArgValuetypeInReg:
6904                                 for (quad = 0; quad < 2; quad ++) {
6905                                         switch (ainfo->pair_storage [quad]) {
6906                                         case ArgInIReg:
6907                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6908                                                 break;
6909                                         case ArgInFloatSSEReg:
6910                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6911                                                 break;
6912                                         case ArgInDoubleSSEReg:
6913                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6914                                                 break;
6915                                         case ArgNone:
6916                                                 break;
6917                                         default:
6918                                                 g_assert_not_reached ();
6919                                         }
6920                                 }
6921                                 break;
6922                         case ArgValuetypeAddrInIReg:
6923                                 if (ainfo->pair_storage [0] == ArgInIReg)
6924                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6925                                 break;
6926                         default:
6927                                 break;
6928                         }
6929                 } else {
6930                         /* Argument allocated to (non-volatile) register */
6931                         switch (ainfo->storage) {
6932                         case ArgInIReg:
6933                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6934                                 break;
6935                         case ArgOnStack:
6936                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6937                                 break;
6938                         default:
6939                                 g_assert_not_reached ();
6940                         }
6941
6942                         if (ins == cfg->args [0]) {
6943                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6944                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6945                         }
6946                 }
6947         }
6948
6949         if (cfg->method->save_lmf)
6950                 args_clobbered = TRUE;
6951
6952         if (trace) {
6953                 args_clobbered = TRUE;
6954                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6955         }
6956
6957         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6958                 args_clobbered = TRUE;
6959
6960         /*
6961          * Optimize the common case of the first bblock making a call with the same
6962          * arguments as the method. This works because the arguments are still in their
6963          * original argument registers.
6964          * FIXME: Generalize this
6965          */
6966         if (!args_clobbered) {
6967                 MonoBasicBlock *first_bb = cfg->bb_entry;
6968                 MonoInst *next;
6969
6970                 next = mono_bb_first_ins (first_bb);
6971                 if (!next && first_bb->next_bb) {
6972                         first_bb = first_bb->next_bb;
6973                         next = mono_bb_first_ins (first_bb);
6974                 }
6975
6976                 if (first_bb->in_count > 1)
6977                         next = NULL;
6978
6979                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6980                         ArgInfo *ainfo = cinfo->args + i;
6981                         gboolean match = FALSE;
6982
6983                         ins = cfg->args [i];
6984                         if (ins->opcode != OP_REGVAR) {
6985                                 switch (ainfo->storage) {
6986                                 case ArgInIReg: {
6987                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6988                                                 if (next->dreg == ainfo->reg) {
6989                                                         NULLIFY_INS (next);
6990                                                         match = TRUE;
6991                                                 } else {
6992                                                         next->opcode = OP_MOVE;
6993                                                         next->sreg1 = ainfo->reg;
6994                                                         /* Only continue if the instruction doesn't change argument regs */
6995                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6996                                                                 match = TRUE;
6997                                                 }
6998                                         }
6999                                         break;
7000                                 }
7001                                 default:
7002                                         break;
7003                                 }
7004                         } else {
7005                                 /* Argument allocated to (non-volatile) register */
7006                                 switch (ainfo->storage) {
7007                                 case ArgInIReg:
7008                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7009                                                 NULLIFY_INS (next);
7010                                                 match = TRUE;
7011                                         }
7012                                         break;
7013                                 default:
7014                                         break;
7015                                 }
7016                         }
7017
7018                         if (match) {
7019                                 next = next->next;
7020                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7021                                 if (!next)
7022                                         break;
7023                         }
7024                 }
7025         }
7026
7027         if (cfg->gen_seq_points) {
7028                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7029
7030                 /* Initialize seq_point_info_var */
7031                 if (cfg->compile_aot) {
7032                         /* Initialize the variable from a GOT slot */
7033                         /* Same as OP_AOTCONST */
7034                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7035                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7036                         g_assert (info_var->opcode == OP_REGOFFSET);
7037                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7038                 }
7039
7040                 /* Initialize ss_trigger_page_var */
7041                 ins = cfg->arch.ss_trigger_page_var;
7042
7043                 g_assert (ins->opcode == OP_REGOFFSET);
7044
7045                 if (cfg->compile_aot) {
7046                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7047                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7048                 } else {
7049                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7050                 }
7051                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7052         }
7053
7054         cfg->code_len = code - cfg->native_code;
7055
7056         g_assert (cfg->code_len < cfg->code_size);
7057
7058         return code;
7059 }
7060
7061 void
7062 mono_arch_emit_epilog (MonoCompile *cfg)
7063 {
7064         MonoMethod *method = cfg->method;
7065         int quad, pos, i;
7066         guint8 *code;
7067         int max_epilog_size;
7068         CallInfo *cinfo;
7069         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7070         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7071
7072         max_epilog_size = get_max_epilog_size (cfg);
7073
7074         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7075                 cfg->code_size *= 2;
7076                 cfg->native_code = mono_realloc_native_code (cfg);
7077                 cfg->stat_code_reallocs++;
7078         }
7079
7080         code = cfg->native_code + cfg->code_len;
7081
7082         cfg->has_unwind_info_for_epilog = TRUE;
7083
7084         /* Mark the start of the epilog */
7085         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7086
7087         /* Save the uwind state which is needed by the out-of-line code */
7088         mono_emit_unwind_op_remember_state (cfg, code);
7089
7090         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7091                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7092
7093         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7094         pos = 0;
7095
7096         if (method->save_lmf) {
7097                 /* check if we need to restore protection of the stack after a stack overflow */
7098                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7099                         guint8 *patch;
7100                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7101                         /* we load the value in a separate instruction: this mechanism may be
7102                          * used later as a safer way to do thread interruption
7103                          */
7104                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7105                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7106                         patch = code;
7107                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7108                         /* note that the call trampoline will preserve eax/edx */
7109                         x86_call_reg (code, X86_ECX);
7110                         x86_patch (patch, code);
7111                 } else {
7112                         /* FIXME: maybe save the jit tls in the prolog */
7113                 }
7114                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7115                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7116                 }
7117         }
7118
7119         /* Restore callee saved regs */
7120         for (i = 0; i < AMD64_NREG; ++i) {
7121                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7122                         /* Restore only used_int_regs, not arch.saved_iregs */
7123                         if (cfg->used_int_regs & (1 << i)) {
7124                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7125                                 mono_emit_unwind_op_same_value (cfg, code, i);
7126                                 async_exc_point (code);
7127                         }
7128                         save_area_offset += 8;
7129                 }
7130         }
7131
7132         /* Load returned vtypes into registers if needed */
7133         cinfo = cfg->arch.cinfo;
7134         if (cinfo->ret.storage == ArgValuetypeInReg) {
7135                 ArgInfo *ainfo = &cinfo->ret;
7136                 MonoInst *inst = cfg->ret;
7137
7138                 for (quad = 0; quad < 2; quad ++) {
7139                         switch (ainfo->pair_storage [quad]) {
7140                         case ArgInIReg:
7141                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), sizeof(mgreg_t));
7142                                 break;
7143                         case ArgInFloatSSEReg:
7144                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7145                                 break;
7146                         case ArgInDoubleSSEReg:
7147                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7148                                 break;
7149                         case ArgNone:
7150                                 break;
7151                         default:
7152                                 g_assert_not_reached ();
7153                         }
7154                 }
7155         }
7156
7157         if (cfg->arch.omit_fp) {
7158                 if (cfg->arch.stack_alloc_size) {
7159                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7160                 }
7161         } else {
7162                 amd64_leave (code);
7163                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7164         }
7165         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7166         async_exc_point (code);
7167         amd64_ret (code);
7168
7169         /* Restore the unwind state to be the same as before the epilog */
7170         mono_emit_unwind_op_restore_state (cfg, code);
7171
7172         cfg->code_len = code - cfg->native_code;
7173
7174         g_assert (cfg->code_len < cfg->code_size);
7175 }
7176
7177 void
7178 mono_arch_emit_exceptions (MonoCompile *cfg)
7179 {
7180         MonoJumpInfo *patch_info;
7181         int nthrows, i;
7182         guint8 *code;
7183         MonoClass *exc_classes [16];
7184         guint8 *exc_throw_start [16], *exc_throw_end [16];
7185         guint32 code_size = 0;
7186
7187         /* Compute needed space */
7188         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7189                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7190                         code_size += 40;
7191                 if (patch_info->type == MONO_PATCH_INFO_R8)
7192                         code_size += 8 + 15; /* sizeof (double) + alignment */
7193                 if (patch_info->type == MONO_PATCH_INFO_R4)
7194                         code_size += 4 + 15; /* sizeof (float) + alignment */
7195                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7196                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7197         }
7198
7199 #ifdef __native_client_codegen__
7200         /* Give us extra room on Native Client.  This could be   */
7201         /* more carefully calculated, but bundle alignment makes */
7202         /* it much trickier, so *2 like other places is good.    */
7203         code_size *= 2;
7204 #endif
7205
7206         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7207                 cfg->code_size *= 2;
7208                 cfg->native_code = mono_realloc_native_code (cfg);
7209                 cfg->stat_code_reallocs++;
7210         }
7211
7212         code = cfg->native_code + cfg->code_len;
7213
7214         /* add code to raise exceptions */
7215         nthrows = 0;
7216         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7217                 switch (patch_info->type) {
7218                 case MONO_PATCH_INFO_EXC: {
7219                         MonoClass *exc_class;
7220                         guint8 *buf, *buf2;
7221                         guint32 throw_ip;
7222
7223                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7224
7225                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7226                         g_assert (exc_class);
7227                         throw_ip = patch_info->ip.i;
7228
7229                         //x86_breakpoint (code);
7230                         /* Find a throw sequence for the same exception class */
7231                         for (i = 0; i < nthrows; ++i)
7232                                 if (exc_classes [i] == exc_class)
7233                                         break;
7234                         if (i < nthrows) {
7235                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7236                                 x86_jump_code (code, exc_throw_start [i]);
7237                                 patch_info->type = MONO_PATCH_INFO_NONE;
7238                         }
7239                         else {
7240                                 buf = code;
7241                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7242                                 buf2 = code;
7243
7244                                 if (nthrows < 16) {
7245                                         exc_classes [nthrows] = exc_class;
7246                                         exc_throw_start [nthrows] = code;
7247                                 }
7248                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7249
7250                                 patch_info->type = MONO_PATCH_INFO_NONE;
7251
7252                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7253
7254                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7255                                 while (buf < buf2)
7256                                         x86_nop (buf);
7257
7258                                 if (nthrows < 16) {
7259                                         exc_throw_end [nthrows] = code;
7260                                         nthrows ++;
7261                                 }
7262                         }
7263                         break;
7264                 }
7265                 default:
7266                         /* do nothing */
7267                         break;
7268                 }
7269                 g_assert(code < cfg->native_code + cfg->code_size);
7270         }
7271
7272         /* Handle relocations with RIP relative addressing */
7273         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7274                 gboolean remove = FALSE;
7275                 guint8 *orig_code = code;
7276
7277                 switch (patch_info->type) {
7278                 case MONO_PATCH_INFO_R8:
7279                 case MONO_PATCH_INFO_R4: {
7280                         guint8 *pos, *patch_pos;
7281                         guint32 target_pos;
7282
7283                         /* The SSE opcodes require a 16 byte alignment */
7284 #if defined(__default_codegen__)
7285                         code = (guint8*)ALIGN_TO (code, 16);
7286 #elif defined(__native_client_codegen__)
7287                         {
7288                                 /* Pad this out with HLT instructions  */
7289                                 /* or we can get garbage bytes emitted */
7290                                 /* which will fail validation          */
7291                                 guint8 *aligned_code;
7292                                 /* extra align to make room for  */
7293                                 /* mov/push below                      */
7294                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7295                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7296                                 /* The technique of hiding data in an  */
7297                                 /* instruction has a problem here: we  */
7298                                 /* need the data aligned to a 16-byte  */
7299                                 /* boundary but the instruction cannot */
7300                                 /* cross the bundle boundary. so only  */
7301                                 /* odd multiples of 16 can be used     */
7302                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7303                                         aligned_code += 16;
7304                                 }
7305                                 while (code < aligned_code) {
7306                                         *(code++) = 0xf4; /* hlt */
7307                                 }
7308                         }
7309 #endif
7310
7311                         pos = cfg->native_code + patch_info->ip.i;
7312                         if (IS_REX (pos [1])) {
7313                                 patch_pos = pos + 5;
7314                                 target_pos = code - pos - 9;
7315                         }
7316                         else {
7317                                 patch_pos = pos + 4;
7318                                 target_pos = code - pos - 8;
7319                         }
7320
7321                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7322 #ifdef __native_client_codegen__
7323                                 /* Hide 64-bit data in a         */
7324                                 /* "mov imm64, r11" instruction. */
7325                                 /* write it before the start of  */
7326                                 /* the data*/
7327                                 *(code-2) = 0x49; /* prefix      */
7328                                 *(code-1) = 0xbb; /* mov X, %r11 */
7329 #endif
7330                                 *(double*)code = *(double*)patch_info->data.target;
7331                                 code += sizeof (double);
7332                         } else {
7333 #ifdef __native_client_codegen__
7334                                 /* Hide 32-bit data in a        */
7335                                 /* "push imm32" instruction.    */
7336                                 *(code-1) = 0x68; /* push */
7337 #endif
7338                                 *(float*)code = *(float*)patch_info->data.target;
7339                                 code += sizeof (float);
7340                         }
7341
7342                         *(guint32*)(patch_pos) = target_pos;
7343
7344                         remove = TRUE;
7345                         break;
7346                 }
7347                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7348                         guint8 *pos;
7349
7350                         if (cfg->compile_aot)
7351                                 continue;
7352
7353                         /*loading is faster against aligned addresses.*/
7354                         code = (guint8*)ALIGN_TO (code, 8);
7355                         memset (orig_code, 0, code - orig_code);
7356
7357                         pos = cfg->native_code + patch_info->ip.i;
7358
7359                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7360                         if (IS_REX (pos [1]))
7361                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7362                         else
7363                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7364
7365                         *(gpointer*)code = (gpointer)patch_info->data.target;
7366                         code += sizeof (gpointer);
7367
7368                         remove = TRUE;
7369                         break;
7370                 }
7371                 default:
7372                         break;
7373                 }
7374
7375                 if (remove) {
7376                         if (patch_info == cfg->patch_info)
7377                                 cfg->patch_info = patch_info->next;
7378                         else {
7379                                 MonoJumpInfo *tmp;
7380
7381                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7382                                         ;
7383                                 tmp->next = patch_info->next;
7384                         }
7385                 }
7386                 g_assert (code < cfg->native_code + cfg->code_size);
7387         }
7388
7389         cfg->code_len = code - cfg->native_code;
7390
7391         g_assert (cfg->code_len < cfg->code_size);
7392
7393 }
7394
7395 #endif /* DISABLE_JIT */
7396
7397 void*
7398 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7399 {
7400         guchar *code = p;
7401         CallInfo *cinfo = NULL;
7402         MonoMethodSignature *sig;
7403         MonoInst *inst;
7404         int i, n, stack_area = 0;
7405
7406         /* Keep this in sync with mono_arch_get_argument_info */
7407
7408         if (enable_arguments) {
7409                 /* Allocate a new area on the stack and save arguments there */
7410                 sig = mono_method_signature (cfg->method);
7411
7412                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
7413
7414                 n = sig->param_count + sig->hasthis;
7415
7416                 stack_area = ALIGN_TO (n * 8, 16);
7417
7418                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7419
7420                 for (i = 0; i < n; ++i) {
7421                         inst = cfg->args [i];
7422
7423                         if (inst->opcode == OP_REGVAR)
7424                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7425                         else {
7426                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7427                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7428                         }
7429                 }
7430         }
7431
7432         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7433         amd64_set_reg_template (code, AMD64_ARG_REG1);
7434         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7435         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7436
7437         if (enable_arguments)
7438                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7439
7440         return code;
7441 }
7442
7443 enum {
7444         SAVE_NONE,
7445         SAVE_STRUCT,
7446         SAVE_EAX,
7447         SAVE_EAX_EDX,
7448         SAVE_XMM
7449 };
7450
7451 void*
7452 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7453 {
7454         guchar *code = p;
7455         int save_mode = SAVE_NONE;
7456         MonoMethod *method = cfg->method;
7457         MonoType *ret_type = mini_replace_type (mono_method_signature (method)->ret);
7458         int i;
7459
7460         switch (ret_type->type) {
7461         case MONO_TYPE_VOID:
7462                 /* special case string .ctor icall */
7463                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7464                         save_mode = SAVE_EAX;
7465                 else
7466                         save_mode = SAVE_NONE;
7467                 break;
7468         case MONO_TYPE_I8:
7469         case MONO_TYPE_U8:
7470                 save_mode = SAVE_EAX;
7471                 break;
7472         case MONO_TYPE_R4:
7473         case MONO_TYPE_R8:
7474                 save_mode = SAVE_XMM;
7475                 break;
7476         case MONO_TYPE_GENERICINST:
7477                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7478                         save_mode = SAVE_EAX;
7479                         break;
7480                 }
7481                 /* Fall through */
7482         case MONO_TYPE_VALUETYPE:
7483                 save_mode = SAVE_STRUCT;
7484                 break;
7485         default:
7486                 save_mode = SAVE_EAX;
7487                 break;
7488         }
7489
7490         /* Save the result and copy it into the proper argument register */
7491         switch (save_mode) {
7492         case SAVE_EAX:
7493                 amd64_push_reg (code, AMD64_RAX);
7494                 /* Align stack */
7495                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7496                 if (enable_arguments)
7497                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7498                 break;
7499         case SAVE_STRUCT:
7500                 /* FIXME: */
7501                 if (enable_arguments)
7502                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7503                 break;
7504         case SAVE_XMM:
7505                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7506                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7507                 /* Align stack */
7508                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7509                 /*
7510                  * The result is already in the proper argument register so no copying
7511                  * needed.
7512                  */
7513                 break;
7514         case SAVE_NONE:
7515                 break;
7516         default:
7517                 g_assert_not_reached ();
7518         }
7519
7520         /* Set %al since this is a varargs call */
7521         if (save_mode == SAVE_XMM)
7522                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7523         else
7524                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7525
7526         if (preserve_argument_registers) {
7527                 for (i = 0; i < PARAM_REGS; ++i)
7528                         amd64_push_reg (code, param_regs [i]);
7529         }
7530
7531         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7532         amd64_set_reg_template (code, AMD64_ARG_REG1);
7533         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7534
7535         if (preserve_argument_registers) {
7536                 for (i = PARAM_REGS - 1; i >= 0; --i)
7537                         amd64_pop_reg (code, param_regs [i]);
7538         }
7539
7540         /* Restore result */
7541         switch (save_mode) {
7542         case SAVE_EAX:
7543                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7544                 amd64_pop_reg (code, AMD64_RAX);
7545                 break;
7546         case SAVE_STRUCT:
7547                 /* FIXME: */
7548                 break;
7549         case SAVE_XMM:
7550                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7551                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7552                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7553                 break;
7554         case SAVE_NONE:
7555                 break;
7556         default:
7557                 g_assert_not_reached ();
7558         }
7559
7560         return code;
7561 }
7562
7563 void
7564 mono_arch_flush_icache (guint8 *code, gint size)
7565 {
7566         /* Not needed */
7567 }
7568
7569 void
7570 mono_arch_flush_register_windows (void)
7571 {
7572 }
7573
7574 gboolean
7575 mono_arch_is_inst_imm (gint64 imm)
7576 {
7577         return amd64_is_imm32 (imm);
7578 }
7579
7580 /*
7581  * Determine whenever the trap whose info is in SIGINFO is caused by
7582  * integer overflow.
7583  */
7584 gboolean
7585 mono_arch_is_int_overflow (void *sigctx, void *info)
7586 {
7587         MonoContext ctx;
7588         guint8* rip;
7589         int reg;
7590         gint64 value;
7591
7592         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
7593
7594         rip = (guint8*)ctx.rip;
7595
7596         if (IS_REX (rip [0])) {
7597                 reg = amd64_rex_b (rip [0]);
7598                 rip ++;
7599         }
7600         else
7601                 reg = 0;
7602
7603         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7604                 /* idiv REG */
7605                 reg += x86_modrm_rm (rip [1]);
7606
7607                 switch (reg) {
7608                 case AMD64_RAX:
7609                         value = ctx.rax;
7610                         break;
7611                 case AMD64_RBX:
7612                         value = ctx.rbx;
7613                         break;
7614                 case AMD64_RCX:
7615                         value = ctx.rcx;
7616                         break;
7617                 case AMD64_RDX:
7618                         value = ctx.rdx;
7619                         break;
7620                 case AMD64_RBP:
7621                         value = ctx.rbp;
7622                         break;
7623                 case AMD64_RSP:
7624                         value = ctx.rsp;
7625                         break;
7626                 case AMD64_RSI:
7627                         value = ctx.rsi;
7628                         break;
7629                 case AMD64_RDI:
7630                         value = ctx.rdi;
7631                         break;
7632                 case AMD64_R12:
7633                         value = ctx.r12;
7634                         break;
7635                 case AMD64_R13:
7636                         value = ctx.r13;
7637                         break;
7638                 case AMD64_R14:
7639                         value = ctx.r14;
7640                         break;
7641                 case AMD64_R15:
7642                         value = ctx.r15;
7643                         break;
7644                 default:
7645                         g_assert_not_reached ();
7646                         reg = -1;
7647                 }
7648
7649                 if (value == -1)
7650                         return TRUE;
7651         }
7652
7653         return FALSE;
7654 }
7655
7656 guint32
7657 mono_arch_get_patch_offset (guint8 *code)
7658 {
7659         return 3;
7660 }
7661
7662 /**
7663  * mono_breakpoint_clean_code:
7664  *
7665  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7666  * breakpoints in the original code, they are removed in the copy.
7667  *
7668  * Returns TRUE if no sw breakpoint was present.
7669  */
7670 gboolean
7671 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7672 {
7673         int i;
7674         gboolean can_write = TRUE;
7675         /*
7676          * If method_start is non-NULL we need to perform bound checks, since we access memory
7677          * at code - offset we could go before the start of the method and end up in a different
7678          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7679          * instead.
7680          */
7681         if (!method_start || code - offset >= method_start) {
7682                 memcpy (buf, code - offset, size);
7683         } else {
7684                 int diff = code - method_start;
7685                 memset (buf, 0, size);
7686                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7687         }
7688         code -= offset;
7689         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7690                 int idx = mono_breakpoint_info_index [i];
7691                 guint8 *ptr;
7692                 if (idx < 1)
7693                         continue;
7694                 ptr = mono_breakpoint_info [idx].address;
7695                 if (ptr >= code && ptr < code + size) {
7696                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7697                         can_write = FALSE;
7698                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7699                         buf [ptr - code] = saved_byte;
7700                 }
7701         }
7702         return can_write;
7703 }
7704
7705 #if defined(__native_client_codegen__)
7706 /* For membase calls, we want the base register. for Native Client,  */
7707 /* all indirect calls have the following sequence with the given sizes: */
7708 /* mov %eXX,%eXX                                [2-3]   */
7709 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7710 /* and $0xffffffffffffffe0,%r11d                [4]     */
7711 /* add %r15,%r11                                [3]     */
7712 /* callq *%r11                                  [3]     */
7713
7714
7715 /* Determine if code points to a NaCl call-through-register sequence, */
7716 /* (i.e., the last 3 instructions listed above) */
7717 int
7718 is_nacl_call_reg_sequence(guint8* code)
7719 {
7720         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7721                                "\x4d\x03\xdf"     /* add */
7722                                "\x41\xff\xd3";   /* call */
7723         return memcmp(code, sequence, 10) == 0;
7724 }
7725
7726 /* Determine if code points to the first opcode of the mov membase component */
7727 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7728 /* (there could be a REX prefix before the opcode but it is ignored) */
7729 static int
7730 is_nacl_indirect_call_membase_sequence(guint8* code)
7731 {
7732                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7733         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7734                /* and that src reg = dest reg */
7735                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7736                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7737                IS_REX(code[2]) &&
7738                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7739                /* and has dst of r11 and base of r15 */
7740                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7741                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7742 }
7743 #endif /* __native_client_codegen__ */
7744
7745 int
7746 mono_arch_get_this_arg_reg (guint8 *code)
7747 {
7748         return AMD64_ARG_REG1;
7749 }
7750
7751 gpointer
7752 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7753 {
7754         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7755 }
7756
7757 #define MAX_ARCH_DELEGATE_PARAMS 10
7758
7759 static gpointer
7760 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7761 {
7762         guint8 *code, *start;
7763         int i;
7764
7765         if (has_target) {
7766                 start = code = mono_global_codeman_reserve (64);
7767
7768                 /* Replace the this argument with the target */
7769                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7770                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7771                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7772
7773                 g_assert ((code - start) < 64);
7774         } else {
7775                 start = code = mono_global_codeman_reserve (64);
7776
7777                 if (param_count == 0) {
7778                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7779                 } else {
7780                         /* We have to shift the arguments left */
7781                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7782                         for (i = 0; i < param_count; ++i) {
7783 #ifdef HOST_WIN32
7784                                 if (i < 3)
7785                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7786                                 else
7787                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7788 #else
7789                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7790 #endif
7791                         }
7792
7793                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7794                 }
7795                 g_assert ((code - start) < 64);
7796         }
7797
7798         nacl_global_codeman_validate(&start, 64, &code);
7799
7800         mono_debug_add_delegate_trampoline (start, code - start);
7801
7802         if (code_len)
7803                 *code_len = code - start;
7804
7805
7806         if (mono_jit_map_is_enabled ()) {
7807                 char *buff;
7808                 if (has_target)
7809                         buff = (char*)"delegate_invoke_has_target";
7810                 else
7811                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7812                 mono_emit_jit_tramp (start, code - start, buff);
7813                 if (!has_target)
7814                         g_free (buff);
7815         }
7816
7817         return start;
7818 }
7819
7820 /*
7821  * mono_arch_get_delegate_invoke_impls:
7822  *
7823  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7824  * trampolines.
7825  */
7826 GSList*
7827 mono_arch_get_delegate_invoke_impls (void)
7828 {
7829         GSList *res = NULL;
7830         guint8 *code;
7831         guint32 code_len;
7832         int i;
7833         char *tramp_name;
7834
7835         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7836         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7837
7838         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7839                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7840                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7841                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7842                 g_free (tramp_name);
7843         }
7844
7845         return res;
7846 }
7847
7848 gpointer
7849 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7850 {
7851         guint8 *code, *start;
7852         int i;
7853
7854         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7855                 return NULL;
7856
7857         /* FIXME: Support more cases */
7858         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
7859                 return NULL;
7860
7861         if (has_target) {
7862                 static guint8* cached = NULL;
7863
7864                 if (cached)
7865                         return cached;
7866
7867                 if (mono_aot_only)
7868                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7869                 else
7870                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7871
7872                 mono_memory_barrier ();
7873
7874                 cached = start;
7875         } else {
7876                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7877                 for (i = 0; i < sig->param_count; ++i)
7878                         if (!mono_is_regsize_var (sig->params [i]))
7879                                 return NULL;
7880                 if (sig->param_count > 4)
7881                         return NULL;
7882
7883                 code = cache [sig->param_count];
7884                 if (code)
7885                         return code;
7886
7887                 if (mono_aot_only) {
7888                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7889                         start = mono_aot_get_trampoline (name);
7890                         g_free (name);
7891                 } else {
7892                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7893                 }
7894
7895                 mono_memory_barrier ();
7896
7897                 cache [sig->param_count] = start;
7898         }
7899
7900         return start;
7901 }
7902 void
7903 mono_arch_finish_init (void)
7904 {
7905 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7906         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7907 #endif
7908 }
7909
7910 void
7911 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7912 {
7913 }
7914
7915 #if defined(__default_codegen__)
7916 #define CMP_SIZE (6 + 1)
7917 #define CMP_REG_REG_SIZE (4 + 1)
7918 #define BR_SMALL_SIZE 2
7919 #define BR_LARGE_SIZE 6
7920 #define MOV_REG_IMM_SIZE 10
7921 #define MOV_REG_IMM_32BIT_SIZE 6
7922 #define JUMP_REG_SIZE (2 + 1)
7923 #elif defined(__native_client_codegen__)
7924 /* NaCl N-byte instructions can be padded up to N-1 bytes */
7925 #define CMP_SIZE ((6 + 1) * 2 - 1)
7926 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
7927 #define BR_SMALL_SIZE (2 * 2 - 1)
7928 #define BR_LARGE_SIZE (6 * 2 - 1)
7929 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
7930 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
7931 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
7932 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
7933 /* Jump membase's size is large and unpredictable    */
7934 /* in native client, just pad it out a whole bundle. */
7935 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
7936 #endif
7937
7938 static int
7939 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7940 {
7941         int i, distance = 0;
7942         for (i = start; i < target; ++i)
7943                 distance += imt_entries [i]->chunk_size;
7944         return distance;
7945 }
7946
7947 /*
7948  * LOCKING: called with the domain lock held
7949  */
7950 gpointer
7951 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7952         gpointer fail_tramp)
7953 {
7954         int i;
7955         int size = 0;
7956         guint8 *code, *start;
7957         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7958
7959         for (i = 0; i < count; ++i) {
7960                 MonoIMTCheckItem *item = imt_entries [i];
7961                 if (item->is_equals) {
7962                         if (item->check_target_idx) {
7963                                 if (!item->compare_done) {
7964                                         if (amd64_is_imm32 (item->key))
7965                                                 item->chunk_size += CMP_SIZE;
7966                                         else
7967                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7968                                 }
7969                                 if (item->has_target_code) {
7970                                         item->chunk_size += MOV_REG_IMM_SIZE;
7971                                 } else {
7972                                         if (vtable_is_32bit)
7973                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7974                                         else
7975                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7976 #ifdef __native_client_codegen__
7977                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7978 #endif
7979                                 }
7980                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7981                         } else {
7982                                 if (fail_tramp) {
7983                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7984                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7985                                 } else {
7986                                         if (vtable_is_32bit)
7987                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7988                                         else
7989                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7990                                         item->chunk_size += JUMP_REG_SIZE;
7991                                         /* with assert below:
7992                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7993                                          */
7994 #ifdef __native_client_codegen__
7995                                         item->chunk_size += JUMP_MEMBASE_SIZE;
7996 #endif
7997                                 }
7998                         }
7999                 } else {
8000                         if (amd64_is_imm32 (item->key))
8001                                 item->chunk_size += CMP_SIZE;
8002                         else
8003                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8004                         item->chunk_size += BR_LARGE_SIZE;
8005                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8006                 }
8007                 size += item->chunk_size;
8008         }
8009 #if defined(__native_client__) && defined(__native_client_codegen__)
8010         /* In Native Client, we don't re-use thunks, allocate from the */
8011         /* normal code manager paths. */
8012         code = mono_domain_code_reserve (domain, size);
8013 #else
8014         if (fail_tramp)
8015                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8016         else
8017                 code = mono_domain_code_reserve (domain, size);
8018 #endif
8019         start = code;
8020         for (i = 0; i < count; ++i) {
8021                 MonoIMTCheckItem *item = imt_entries [i];
8022                 item->code_target = code;
8023                 if (item->is_equals) {
8024                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8025
8026                         if (item->check_target_idx || fail_case) {
8027                                 if (!item->compare_done || fail_case) {
8028                                         if (amd64_is_imm32 (item->key))
8029                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8030                                         else {
8031                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8032                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8033                                         }
8034                                 }
8035                                 item->jmp_code = code;
8036                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8037                                 if (item->has_target_code) {
8038                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8039                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8040                                 } else {
8041                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8042                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8043                                 }
8044
8045                                 if (fail_case) {
8046                                         amd64_patch (item->jmp_code, code);
8047                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8048                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8049                                         item->jmp_code = NULL;
8050                                 }
8051                         } else {
8052                                 /* enable the commented code to assert on wrong method */
8053 #if 0
8054                                 if (amd64_is_imm32 (item->key))
8055                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8056                                 else {
8057                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8058                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8059                                 }
8060                                 item->jmp_code = code;
8061                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8062                                 /* See the comment below about R10 */
8063                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8064                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8065                                 amd64_patch (item->jmp_code, code);
8066                                 amd64_breakpoint (code);
8067                                 item->jmp_code = NULL;
8068 #else
8069                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8070                                    needs to be preserved.  R10 needs
8071                                    to be preserved for calls which
8072                                    require a runtime generic context,
8073                                    but interface calls don't. */
8074                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8075                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8076 #endif
8077                         }
8078                 } else {
8079                         if (amd64_is_imm32 (item->key))
8080                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8081                         else {
8082                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8083                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8084                         }
8085                         item->jmp_code = code;
8086                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8087                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8088                         else
8089                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8090                 }
8091                 g_assert (code - item->code_target <= item->chunk_size);
8092         }
8093         /* patch the branches to get to the target items */
8094         for (i = 0; i < count; ++i) {
8095                 MonoIMTCheckItem *item = imt_entries [i];
8096                 if (item->jmp_code) {
8097                         if (item->check_target_idx) {
8098                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8099                         }
8100                 }
8101         }
8102
8103         if (!fail_tramp)
8104                 mono_stats.imt_thunks_size += code - start;
8105         g_assert (code - start <= size);
8106
8107         nacl_domain_code_validate(domain, &start, size, &code);
8108
8109         return start;
8110 }
8111
8112 MonoMethod*
8113 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8114 {
8115         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8116 }
8117
8118 MonoVTable*
8119 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8120 {
8121         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8122 }
8123
8124 GSList*
8125 mono_arch_get_cie_program (void)
8126 {
8127         GSList *l = NULL;
8128
8129         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8130         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8131
8132         return l;
8133 }
8134
8135 MonoInst*
8136 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8137 {
8138         MonoInst *ins = NULL;
8139         int opcode = 0;
8140
8141         if (cmethod->klass == mono_defaults.math_class) {
8142                 if (strcmp (cmethod->name, "Sin") == 0) {
8143                         opcode = OP_SIN;
8144                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8145                         opcode = OP_COS;
8146                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8147                         opcode = OP_SQRT;
8148                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8149                         opcode = OP_ABS;
8150                 }
8151
8152                 if (opcode) {
8153                         MONO_INST_NEW (cfg, ins, opcode);
8154                         ins->type = STACK_R8;
8155                         ins->dreg = mono_alloc_freg (cfg);
8156                         ins->sreg1 = args [0]->dreg;
8157                         MONO_ADD_INS (cfg->cbb, ins);
8158                 }
8159
8160                 opcode = 0;
8161                 if (cfg->opt & MONO_OPT_CMOV) {
8162                         if (strcmp (cmethod->name, "Min") == 0) {
8163                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8164                                         opcode = OP_IMIN;
8165                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8166                                         opcode = OP_IMIN_UN;
8167                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8168                                         opcode = OP_LMIN;
8169                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8170                                         opcode = OP_LMIN_UN;
8171                         } else if (strcmp (cmethod->name, "Max") == 0) {
8172                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8173                                         opcode = OP_IMAX;
8174                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8175                                         opcode = OP_IMAX_UN;
8176                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8177                                         opcode = OP_LMAX;
8178                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8179                                         opcode = OP_LMAX_UN;
8180                         }
8181                 }
8182
8183                 if (opcode) {
8184                         MONO_INST_NEW (cfg, ins, opcode);
8185                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8186                         ins->dreg = mono_alloc_ireg (cfg);
8187                         ins->sreg1 = args [0]->dreg;
8188                         ins->sreg2 = args [1]->dreg;
8189                         MONO_ADD_INS (cfg->cbb, ins);
8190                 }
8191
8192 #if 0
8193                 /* OP_FREM is not IEEE compatible */
8194                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
8195                         MONO_INST_NEW (cfg, ins, OP_FREM);
8196                         ins->inst_i0 = args [0];
8197                         ins->inst_i1 = args [1];
8198                 }
8199 #endif
8200         }
8201
8202         /*
8203          * Can't implement CompareExchange methods this way since they have
8204          * three arguments.
8205          */
8206
8207         return ins;
8208 }
8209
8210 gboolean
8211 mono_arch_print_tree (MonoInst *tree, int arity)
8212 {
8213         return 0;
8214 }
8215
8216 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8217
8218 mgreg_t
8219 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8220 {
8221         switch (reg) {
8222         case AMD64_RCX: return ctx->rcx;
8223         case AMD64_RDX: return ctx->rdx;
8224         case AMD64_RBX: return ctx->rbx;
8225         case AMD64_RBP: return ctx->rbp;
8226         case AMD64_RSP: return ctx->rsp;
8227         default:
8228                 return _CTX_REG (ctx, rax, reg);
8229         }
8230 }
8231
8232 void
8233 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8234 {
8235         switch (reg) {
8236         case AMD64_RCX:
8237                 ctx->rcx = val;
8238                 break;
8239         case AMD64_RDX:
8240                 ctx->rdx = val;
8241                 break;
8242         case AMD64_RBX:
8243                 ctx->rbx = val;
8244                 break;
8245         case AMD64_RBP:
8246                 ctx->rbp = val;
8247                 break;
8248         case AMD64_RSP:
8249                 ctx->rsp = val;
8250                 break;
8251         default:
8252                 _CTX_REG (ctx, rax, reg) = val;
8253         }
8254 }
8255
8256 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
8257 gpointer
8258 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8259 {
8260         int offset;
8261         gpointer *sp, old_value;
8262         char *bp;
8263         const unsigned char *handler;
8264
8265         /*Decode the first instruction to figure out where did we store the spvar*/
8266         /*Our jit MUST generate the following:
8267          mov    %rsp, ?(%rbp)
8268
8269          Which is encoded as: REX.W 0x89 mod_rm
8270          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
8271                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
8272                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
8273
8274         FIXME can we generate frameless methods on this case?
8275
8276         */
8277         handler = clause->handler_start;
8278
8279         /*REX.W*/
8280         if (*handler != 0x48)
8281                 return NULL;
8282         ++handler;
8283
8284         /*mov r, r/m */
8285         if (*handler != 0x89)
8286                 return NULL;
8287         ++handler;
8288
8289         if (*handler == 0x65)
8290                 offset = *(signed char*)(handler + 1);
8291         else if (*handler == 0xA5)
8292                 offset = *(int*)(handler + 1);
8293         else
8294                 return NULL;
8295
8296         /*Load the spvar*/
8297         bp = MONO_CONTEXT_GET_BP (ctx);
8298         sp = *(gpointer*)(bp + offset);
8299
8300         old_value = *sp;
8301         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8302                 return old_value;
8303
8304         *sp = new_value;
8305
8306         return old_value;
8307 }
8308
8309 /*
8310  * mono_arch_emit_load_aotconst:
8311  *
8312  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8313  * TARGET from the mscorlib GOT in full-aot code.
8314  * On AMD64, the result is placed into R11.
8315  */
8316 guint8*
8317 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8318 {
8319         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8320         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8321
8322         return code;
8323 }
8324
8325 /*
8326  * mono_arch_get_trampolines:
8327  *
8328  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8329  * for AOT.
8330  */
8331 GSList *
8332 mono_arch_get_trampolines (gboolean aot)
8333 {
8334         return mono_amd64_get_exception_trampolines (aot);
8335 }
8336
8337 /* Soft Debug support */
8338 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8339
8340 /*
8341  * mono_arch_set_breakpoint:
8342  *
8343  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8344  * The location should contain code emitted by OP_SEQ_POINT.
8345  */
8346 void
8347 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8348 {
8349         guint8 *code = ip;
8350         guint8 *orig_code = code;
8351
8352         if (ji->from_aot) {
8353                 guint32 native_offset = ip - (guint8*)ji->code_start;
8354                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8355
8356                 g_assert (info->bp_addrs [native_offset] == 0);
8357                 info->bp_addrs [native_offset] = bp_trigger_page;
8358         } else {
8359                 /*
8360                  * In production, we will use int3 (has to fix the size in the md
8361                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8362                  * instead.
8363                  */
8364                 g_assert (code [0] == 0x90);
8365                 if (breakpoint_size == 8) {
8366                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8367                 } else {
8368                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8369                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8370                 }
8371
8372                 g_assert (code - orig_code == breakpoint_size);
8373         }
8374 }
8375
8376 /*
8377  * mono_arch_clear_breakpoint:
8378  *
8379  *   Clear the breakpoint at IP.
8380  */
8381 void
8382 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8383 {
8384         guint8 *code = ip;
8385         int i;
8386
8387         if (ji->from_aot) {
8388                 guint32 native_offset = ip - (guint8*)ji->code_start;
8389                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8390
8391                 g_assert (info->bp_addrs [native_offset] == 0);
8392                 info->bp_addrs [native_offset] = info;
8393         } else {
8394                 for (i = 0; i < breakpoint_size; ++i)
8395                         x86_nop (code);
8396         }
8397 }
8398
8399 gboolean
8400 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8401 {
8402 #ifdef HOST_WIN32
8403         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8404         return FALSE;
8405 #else
8406         siginfo_t* sinfo = (siginfo_t*) info;
8407         /* Sometimes the address is off by 4 */
8408         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8409                 return TRUE;
8410         else
8411                 return FALSE;
8412 #endif
8413 }
8414
8415 /*
8416  * mono_arch_skip_breakpoint:
8417  *
8418  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8419  * we resume, the instruction is not executed again.
8420  */
8421 void
8422 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8423 {
8424         if (ji->from_aot) {
8425                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8426                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8427         } else {
8428                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8429         }
8430 }
8431
8432 /*
8433  * mono_arch_start_single_stepping:
8434  *
8435  *   Start single stepping.
8436  */
8437 void
8438 mono_arch_start_single_stepping (void)
8439 {
8440         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8441 }
8442
8443 /*
8444  * mono_arch_stop_single_stepping:
8445  *
8446  *   Stop single stepping.
8447  */
8448 void
8449 mono_arch_stop_single_stepping (void)
8450 {
8451         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8452 }
8453
8454 /*
8455  * mono_arch_is_single_step_event:
8456  *
8457  *   Return whenever the machine state in SIGCTX corresponds to a single
8458  * step event.
8459  */
8460 gboolean
8461 mono_arch_is_single_step_event (void *info, void *sigctx)
8462 {
8463 #ifdef HOST_WIN32
8464         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
8465         return FALSE;
8466 #else
8467         siginfo_t* sinfo = (siginfo_t*) info;
8468         /* Sometimes the address is off by 4 */
8469         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8470                 return TRUE;
8471         else
8472                 return FALSE;
8473 #endif
8474 }
8475
8476 /*
8477  * mono_arch_skip_single_step:
8478  *
8479  *   Modify CTX so the ip is placed after the single step trigger instruction,
8480  * we resume, the instruction is not executed again.
8481  */
8482 void
8483 mono_arch_skip_single_step (MonoContext *ctx)
8484 {
8485         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8486 }
8487
8488 /*
8489  * mono_arch_create_seq_point_info:
8490  *
8491  *   Return a pointer to a data structure which is used by the sequence
8492  * point implementation in AOTed code.
8493  */
8494 gpointer
8495 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8496 {
8497         SeqPointInfo *info;
8498         MonoJitInfo *ji;
8499         int i;
8500
8501         // FIXME: Add a free function
8502
8503         mono_domain_lock (domain);
8504         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8505                                                                 code);
8506         mono_domain_unlock (domain);
8507
8508         if (!info) {
8509                 ji = mono_jit_info_table_find (domain, (char*)code);
8510                 g_assert (ji);
8511
8512                 // FIXME: Optimize the size
8513                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8514
8515                 info->ss_trigger_page = ss_trigger_page;
8516                 info->bp_trigger_page = bp_trigger_page;
8517                 /* Initialize to a valid address */
8518                 for (i = 0; i < ji->code_size; ++i)
8519                         info->bp_addrs [i] = info;
8520
8521                 mono_domain_lock (domain);
8522                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8523                                                          code, info);
8524                 mono_domain_unlock (domain);
8525         }
8526
8527         return info;
8528 }
8529
8530 void
8531 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8532 {
8533         ext->lmf.previous_lmf = prev_lmf;
8534         /* Mark that this is a MonoLMFExt */
8535         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8536         ext->lmf.rsp = (gssize)ext;
8537 }
8538
8539 #endif
8540
8541 gboolean
8542 mono_arch_opcode_supported (int opcode)
8543 {
8544         switch (opcode) {
8545         case OP_ATOMIC_ADD_I4:
8546         case OP_ATOMIC_ADD_I8:
8547         case OP_ATOMIC_EXCHANGE_I4:
8548         case OP_ATOMIC_EXCHANGE_I8:
8549         case OP_ATOMIC_CAS_I4:
8550         case OP_ATOMIC_CAS_I8:
8551                 return TRUE;
8552         default:
8553                 return FALSE;
8554         }
8555 }