mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/metadata/gc-internal.h>
  27 #include <mono/utils/mono-math.h>
  28 #include <mono/utils/mono-mmap.h>
  29
  30 #include "trace.h"
  31 #include "ir-emit.h"
  32 #include "mini-amd64.h"
  33 #include "cpu-amd64.h"
  34 #include "debugger-agent.h"
  35 #include "mini-gc.h"
  36
  37 static gint lmf_tls_offset = -1;
  38 static gint lmf_addr_tls_offset = -1;
  39 static gint appdomain_tls_offset = -1;
  40
  41 #ifdef MONO_XEN_OPT
  42 static gboolean optimize_for_xen = TRUE;
  43 #else
  44 #define optimize_for_xen 0
  45 #endif
  46
  47 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  48
  49 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  50
  51 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  52
  53 #ifdef HOST_WIN32
  54 /* Under windows, the calling convention is never stdcall */
  55 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  56 #else
  57 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  58 #endif
  59
  60 /* This mutex protects architecture specific caches */
  61 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  62 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  63 static CRITICAL_SECTION mini_arch_mutex;
  64
  65 MonoBreakpointInfo
  66 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  67
  68 /*
  69  * The code generated for sequence points reads from this location, which is
  70  * made read-only when single stepping is enabled.
  71  */
  72 static gpointer ss_trigger_page;
  73
  74 /* Enabled breakpoints read from this trigger page */
  75 static gpointer bp_trigger_page;
  76
  77 /* The size of the breakpoint sequence */
  78 static int breakpoint_size;
  79
  80 /* The size of the breakpoint instruction causing the actual fault */
  81 static int breakpoint_fault_size;
  82
  83 /* The size of the single step instruction causing the actual fault */
  84 static int single_step_fault_size;
  85
  86 #ifdef HOST_WIN32
  87 /* On Win64 always reserve first 32 bytes for first four arguments */
  88 #define ARGS_OFFSET 48
  89 #else
  90 #define ARGS_OFFSET 16
  91 #endif
  92 #define GP_SCRATCH_REG AMD64_R11
  93
  94 /*
  95  * AMD64 register usage:
  96  * - callee saved registers are used for global register allocation
  97  * - %r11 is used for materializing 64 bit constants in opcodes
  98  * - the rest is used for local allocation
  99  */
 100
 101 /*
 102  * Floating point comparison results:
 103  *                  ZF PF CF
 104  * A > B            0  0  0
 105  * A < B            0  0  1
 106  * A = B            1  0  0
 107  * A > B            0  0  0
 108  * UNORDERED        1  1  1
 109  */
 110
 111 const char*
 112 mono_arch_regname (int reg)
 113 {
 114         switch (reg) {
 115         case AMD64_RAX: return "%rax";
 116         case AMD64_RBX: return "%rbx";
 117         case AMD64_RCX: return "%rcx";
 118         case AMD64_RDX: return "%rdx";
 119         case AMD64_RSP: return "%rsp";
 120         case AMD64_RBP: return "%rbp";
 121         case AMD64_RDI: return "%rdi";
 122         case AMD64_RSI: return "%rsi";
 123         case AMD64_R8: return "%r8";
 124         case AMD64_R9: return "%r9";
 125         case AMD64_R10: return "%r10";
 126         case AMD64_R11: return "%r11";
 127         case AMD64_R12: return "%r12";
 128         case AMD64_R13: return "%r13";
 129         case AMD64_R14: return "%r14";
 130         case AMD64_R15: return "%r15";
 131         }
 132         return "unknown";
 133 }
 134
 135 static const char * packed_xmmregs [] = {
 136         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 137         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 138 };
 139
 140 static const char * single_xmmregs [] = {
 141         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 142         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 143 };
 144
 145 const char*
 146 mono_arch_fregname (int reg)
 147 {
 148         if (reg < AMD64_XMM_NREG)
 149                 return single_xmmregs [reg];
 150         else
 151                 return "unknown";
 152 }
 153
 154 const char *
 155 mono_arch_xregname (int reg)
 156 {
 157         if (reg < AMD64_XMM_NREG)
 158                 return packed_xmmregs [reg];
 159         else
 160                 return "unknown";
 161 }
 162
 163 G_GNUC_UNUSED static void
 164 break_count (void)
 165 {
 166 }
 167
 168 G_GNUC_UNUSED static gboolean
 169 debug_count (void)
 170 {
 171         static int count = 0;
 172         count ++;
 173
 174         if (!getenv ("COUNT"))
 175                 return TRUE;
 176
 177         if (count == atoi (getenv ("COUNT"))) {
 178                 break_count ();
 179         }
 180
 181         if (count > atoi (getenv ("COUNT"))) {
 182                 return FALSE;
 183         }
 184
 185         return TRUE;
 186 }
 187
 188 static gboolean
 189 debug_omit_fp (void)
 190 {
 191 #if 0
 192         return debug_count ();
 193 #else
 194         return TRUE;
 195 #endif
 196 }
 197
 198 static inline gboolean
 199 amd64_is_near_call (guint8 *code)
 200 {
 201         /* Skip REX */
 202         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 203                 code += 1;
 204
 205         return code [0] == 0xe8;
 206 }
 207
 208 static inline void
 209 amd64_patch (unsigned char* code, gpointer target)
 210 {
 211         guint8 rex = 0;
 212
 213         /* Skip REX */
 214         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 215                 rex = code [0];
 216                 code += 1;
 217         }
 218
 219         if ((code [0] & 0xf8) == 0xb8) {
 220                 /* amd64_set_reg_template */
 221                 *(guint64*)(code + 1) = (guint64)target;
 222         }
 223         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 224                 /* mov 0(%rip), %dreg */
 225                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 226         }
 227         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 228                 /* call *<OFFSET>(%rip) */
 229                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 230         }
 231         else if ((code [0] == 0xe8)) {
 232                 /* call <DISP> */
 233                 gint64 disp = (guint8*)target - (guint8*)code;
 234                 g_assert (amd64_is_imm32 (disp));
 235                 x86_patch (code, (unsigned char*)target);
 236         }
 237         else
 238                 x86_patch (code, (unsigned char*)target);
 239 }
 240
 241 void
 242 mono_amd64_patch (unsigned char* code, gpointer target)
 243 {
 244         amd64_patch (code, target);
 245 }
 246
 247 typedef enum {
 248         ArgInIReg,
 249         ArgInFloatSSEReg,
 250         ArgInDoubleSSEReg,
 251         ArgOnStack,
 252         ArgValuetypeInReg,
 253         ArgValuetypeAddrInIReg,
 254         ArgNone /* only in pair_storage */
 255 } ArgStorage;
 256
 257 typedef struct {
 258         gint16 offset;
 259         gint8  reg;
 260         ArgStorage storage;
 261
 262         /* Only if storage == ArgValuetypeInReg */
 263         ArgStorage pair_storage [2];
 264         gint8 pair_regs [2];
 265         int nregs;
 266 } ArgInfo;
 267
 268 typedef struct {
 269         int nargs;
 270         guint32 stack_usage;
 271         guint32 reg_usage;
 272         guint32 freg_usage;
 273         gboolean need_stack_align;
 274         gboolean vtype_retaddr;
 275         /* The index of the vret arg in the argument list */
 276         int vret_arg_index;
 277         ArgInfo ret;
 278         ArgInfo sig_cookie;
 279         ArgInfo args [1];
 280 } CallInfo;
 281
 282 #define DEBUG(a) if (cfg->verbose_level > 1) a
 283
 284 #ifdef HOST_WIN32
 285 #define PARAM_REGS 4
 286
 287 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 288
 289 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 290 #else
 291 #define PARAM_REGS 6
 292
 293 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 294
 295  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 296 #endif
 297
 298 static void inline
 299 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 300 {
 301     ainfo->offset = *stack_size;
 302
 303     if (*gr >= PARAM_REGS) {
 304                 ainfo->storage = ArgOnStack;
 305                 (*stack_size) += sizeof (gpointer);
 306     }
 307     else {
 308                 ainfo->storage = ArgInIReg;
 309                 ainfo->reg = param_regs [*gr];
 310                 (*gr) ++;
 311     }
 312 }
 313
 314 #ifdef HOST_WIN32
 315 #define FLOAT_PARAM_REGS 4
 316 #else
 317 #define FLOAT_PARAM_REGS 8
 318 #endif
 319
 320 static void inline
 321 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 322 {
 323     ainfo->offset = *stack_size;
 324
 325     if (*gr >= FLOAT_PARAM_REGS) {
 326                 ainfo->storage = ArgOnStack;
 327                 (*stack_size) += sizeof (gpointer);
 328     }
 329     else {
 330                 /* A double register */
 331                 if (is_double)
 332                         ainfo->storage = ArgInDoubleSSEReg;
 333                 else
 334                         ainfo->storage = ArgInFloatSSEReg;
 335                 ainfo->reg = *gr;
 336                 (*gr) += 1;
 337     }
 338 }
 339
 340 typedef enum ArgumentClass {
 341         ARG_CLASS_NO_CLASS,
 342         ARG_CLASS_MEMORY,
 343         ARG_CLASS_INTEGER,
 344         ARG_CLASS_SSE
 345 } ArgumentClass;
 346
 347 static ArgumentClass
 348 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 349 {
 350         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 351         MonoType *ptype;
 352
 353         ptype = mini_type_get_underlying_type (NULL, type);
 354         switch (ptype->type) {
 355         case MONO_TYPE_BOOLEAN:
 356         case MONO_TYPE_CHAR:
 357         case MONO_TYPE_I1:
 358         case MONO_TYPE_U1:
 359         case MONO_TYPE_I2:
 360         case MONO_TYPE_U2:
 361         case MONO_TYPE_I4:
 362         case MONO_TYPE_U4:
 363         case MONO_TYPE_I:
 364         case MONO_TYPE_U:
 365         case MONO_TYPE_STRING:
 366         case MONO_TYPE_OBJECT:
 367         case MONO_TYPE_CLASS:
 368         case MONO_TYPE_SZARRAY:
 369         case MONO_TYPE_PTR:
 370         case MONO_TYPE_FNPTR:
 371         case MONO_TYPE_ARRAY:
 372         case MONO_TYPE_I8:
 373         case MONO_TYPE_U8:
 374                 class2 = ARG_CLASS_INTEGER;
 375                 break;
 376         case MONO_TYPE_R4:
 377         case MONO_TYPE_R8:
 378 #ifdef HOST_WIN32
 379                 class2 = ARG_CLASS_INTEGER;
 380 #else
 381                 class2 = ARG_CLASS_SSE;
 382 #endif
 383                 break;
 384
 385         case MONO_TYPE_TYPEDBYREF:
 386                 g_assert_not_reached ();
 387
 388         case MONO_TYPE_GENERICINST:
 389                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 390                         class2 = ARG_CLASS_INTEGER;
 391                         break;
 392                 }
 393                 /* fall through */
 394         case MONO_TYPE_VALUETYPE: {
 395                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 396                 int i;
 397
 398                 for (i = 0; i < info->num_fields; ++i) {
 399                         class2 = class1;
 400                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 401                 }
 402                 break;
 403         }
 404         default:
 405                 g_assert_not_reached ();
 406         }
 407
 408         /* Merge */
 409         if (class1 == class2)
 410                 ;
 411         else if (class1 == ARG_CLASS_NO_CLASS)
 412                 class1 = class2;
 413         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 414                 class1 = ARG_CLASS_MEMORY;
 415         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 416                 class1 = ARG_CLASS_INTEGER;
 417         else
 418                 class1 = ARG_CLASS_SSE;
 419
 420         return class1;
 421 }
 422
 423 static void
 424 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 425                            gboolean is_return,
 426                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 427 {
 428         guint32 size, quad, nquads, i;
 429         ArgumentClass args [2];
 430         MonoMarshalType *info = NULL;
 431         MonoClass *klass;
 432         MonoGenericSharingContext tmp_gsctx;
 433         gboolean pass_on_stack = FALSE;
 434
 435         /*
 436          * The gsctx currently contains no data, it is only used for checking whenever
 437          * open types are allowed, some callers like mono_arch_get_argument_info ()
 438          * don't pass it to us, so work around that.
 439          */
 440         if (!gsctx)
 441                 gsctx = &tmp_gsctx;
 442
 443         klass = mono_class_from_mono_type (type);
 444         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 445 #ifndef HOST_WIN32
 446         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 447                 /* We pass and return vtypes of size 8 in a register */
 448         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 449                 pass_on_stack = TRUE;
 450         }
 451 #else
 452         if (!sig->pinvoke) {
 453                 pass_on_stack = TRUE;
 454         }
 455 #endif
 456
 457         if (pass_on_stack) {
 458                 /* Allways pass in memory */
 459                 ainfo->offset = *stack_size;
 460                 *stack_size += ALIGN_TO (size, 8);
 461                 ainfo->storage = ArgOnStack;
 462
 463                 return;
 464         }
 465
 466         /* FIXME: Handle structs smaller than 8 bytes */
 467         //if ((size % 8) != 0)
 468         //      NOT_IMPLEMENTED;
 469
 470         if (size > 8)
 471                 nquads = 2;
 472         else
 473                 nquads = 1;
 474
 475         if (!sig->pinvoke) {
 476                 /* Always pass in 1 or 2 integer registers */
 477                 args [0] = ARG_CLASS_INTEGER;
 478                 args [1] = ARG_CLASS_INTEGER;
 479                 /* Only the simplest cases are supported */
 480                 if (is_return && nquads != 1) {
 481                         args [0] = ARG_CLASS_MEMORY;
 482                         args [1] = ARG_CLASS_MEMORY;
 483                 }
 484         } else {
 485                 /*
 486                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 487                  * The X87 and SSEUP stuff is left out since there are no such types in
 488                  * the CLR.
 489                  */
 490                 info = mono_marshal_load_type_info (klass);
 491                 g_assert (info);
 492
 493 #ifndef HOST_WIN32
 494                 if (info->native_size > 16) {
 495                         ainfo->offset = *stack_size;
 496                         *stack_size += ALIGN_TO (info->native_size, 8);
 497                         ainfo->storage = ArgOnStack;
 498
 499                         return;
 500                 }
 501 #else
 502                 switch (info->native_size) {
 503                 case 1: case 2: case 4: case 8:
 504                         break;
 505                 default:
 506                         if (is_return) {
 507                                 ainfo->storage = ArgOnStack;
 508                                 ainfo->offset = *stack_size;
 509                                 *stack_size += ALIGN_TO (info->native_size, 8);
 510                         }
 511                         else {
 512                                 ainfo->storage = ArgValuetypeAddrInIReg;
 513
 514                                 if (*gr < PARAM_REGS) {
 515                                         ainfo->pair_storage [0] = ArgInIReg;
 516                                         ainfo->pair_regs [0] = param_regs [*gr];
 517                                         (*gr) ++;
 518                                 }
 519                                 else {
 520                                         ainfo->pair_storage [0] = ArgOnStack;
 521                                         ainfo->offset = *stack_size;
 522                                         *stack_size += 8;
 523                                 }
 524                         }
 525
 526                         return;
 527                 }
 528 #endif
 529
 530                 args [0] = ARG_CLASS_NO_CLASS;
 531                 args [1] = ARG_CLASS_NO_CLASS;
 532                 for (quad = 0; quad < nquads; ++quad) {
 533                         int size;
 534                         guint32 align;
 535                         ArgumentClass class1;
 536
 537                         if (info->num_fields == 0)
 538                                 class1 = ARG_CLASS_MEMORY;
 539                         else
 540                                 class1 = ARG_CLASS_NO_CLASS;
 541                         for (i = 0; i < info->num_fields; ++i) {
 542                                 size = mono_marshal_type_size (info->fields [i].field->type,
 543                                                                                            info->fields [i].mspec,
 544                                                                                            &align, TRUE, klass->unicode);
 545                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 546                                         /* Unaligned field */
 547                                         NOT_IMPLEMENTED;
 548                                 }
 549
 550                                 /* Skip fields in other quad */
 551                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 552                                         continue;
 553                                 if ((quad == 1) && (info->fields [i].offset < 8))
 554                                         continue;
 555
 556                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 557                         }
 558                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 559                         args [quad] = class1;
 560                 }
 561         }
 562
 563         /* Post merger cleanup */
 564         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 565                 args [0] = args [1] = ARG_CLASS_MEMORY;
 566
 567         /* Allocate registers */
 568         {
 569                 int orig_gr = *gr;
 570                 int orig_fr = *fr;
 571
 572                 ainfo->storage = ArgValuetypeInReg;
 573                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 574                 ainfo->nregs = nquads;
 575                 for (quad = 0; quad < nquads; ++quad) {
 576                         switch (args [quad]) {
 577                         case ARG_CLASS_INTEGER:
 578                                 if (*gr >= PARAM_REGS)
 579                                         args [quad] = ARG_CLASS_MEMORY;
 580                                 else {
 581                                         ainfo->pair_storage [quad] = ArgInIReg;
 582                                         if (is_return)
 583                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 584                                         else
 585                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 586                                         (*gr) ++;
 587                                 }
 588                                 break;
 589                         case ARG_CLASS_SSE:
 590                                 if (*fr >= FLOAT_PARAM_REGS)
 591                                         args [quad] = ARG_CLASS_MEMORY;
 592                                 else {
 593                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 594                                         ainfo->pair_regs [quad] = *fr;
 595                                         (*fr) ++;
 596                                 }
 597                                 break;
 598                         case ARG_CLASS_MEMORY:
 599                                 break;
 600                         default:
 601                                 g_assert_not_reached ();
 602                         }
 603                 }
 604
 605                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 606                         /* Revert possible register assignments */
 607                         *gr = orig_gr;
 608                         *fr = orig_fr;
 609
 610                         ainfo->offset = *stack_size;
 611                         if (sig->pinvoke)
 612                                 *stack_size += ALIGN_TO (info->native_size, 8);
 613                         else
 614                                 *stack_size += nquads * sizeof (gpointer);
 615                         ainfo->storage = ArgOnStack;
 616                 }
 617         }
 618 }
 619
 620 /*
 621  * get_call_info:
 622  *
 623  *  Obtain information about a call according to the calling convention.
 624  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 625  * Draft Version 0.23" document for more information.
 626  */
 627 static CallInfo*
 628 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 629 {
 630         guint32 i, gr, fr, pstart;
 631         MonoType *ret_type;
 632         int n = sig->hasthis + sig->param_count;
 633         guint32 stack_size = 0;
 634         CallInfo *cinfo;
 635         gboolean is_pinvoke = sig->pinvoke;
 636
 637         if (mp)
 638                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 639         else
 640                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 641
 642         cinfo->nargs = n;
 643
 644         gr = 0;
 645         fr = 0;
 646
 647         /* return value */
 648         {
 649                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 650                 switch (ret_type->type) {
 651                 case MONO_TYPE_BOOLEAN:
 652                 case MONO_TYPE_I1:
 653                 case MONO_TYPE_U1:
 654                 case MONO_TYPE_I2:
 655                 case MONO_TYPE_U2:
 656                 case MONO_TYPE_CHAR:
 657                 case MONO_TYPE_I4:
 658                 case MONO_TYPE_U4:
 659                 case MONO_TYPE_I:
 660                 case MONO_TYPE_U:
 661                 case MONO_TYPE_PTR:
 662                 case MONO_TYPE_FNPTR:
 663                 case MONO_TYPE_CLASS:
 664                 case MONO_TYPE_OBJECT:
 665                 case MONO_TYPE_SZARRAY:
 666                 case MONO_TYPE_ARRAY:
 667                 case MONO_TYPE_STRING:
 668                         cinfo->ret.storage = ArgInIReg;
 669                         cinfo->ret.reg = AMD64_RAX;
 670                         break;
 671                 case MONO_TYPE_U8:
 672                 case MONO_TYPE_I8:
 673                         cinfo->ret.storage = ArgInIReg;
 674                         cinfo->ret.reg = AMD64_RAX;
 675                         break;
 676                 case MONO_TYPE_R4:
 677                         cinfo->ret.storage = ArgInFloatSSEReg;
 678                         cinfo->ret.reg = AMD64_XMM0;
 679                         break;
 680                 case MONO_TYPE_R8:
 681                         cinfo->ret.storage = ArgInDoubleSSEReg;
 682                         cinfo->ret.reg = AMD64_XMM0;
 683                         break;
 684                 case MONO_TYPE_GENERICINST:
 685                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 686                                 cinfo->ret.storage = ArgInIReg;
 687                                 cinfo->ret.reg = AMD64_RAX;
 688                                 break;
 689                         }
 690                         /* fall through */
 691                 case MONO_TYPE_VALUETYPE: {
 692                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 693
 694                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 695                         if (cinfo->ret.storage == ArgOnStack) {
 696                                 cinfo->vtype_retaddr = TRUE;
 697                                 /* The caller passes the address where the value is stored */
 698                         }
 699                         break;
 700                 }
 701                 case MONO_TYPE_TYPEDBYREF:
 702                         /* Same as a valuetype with size 24 */
 703                         cinfo->vtype_retaddr = TRUE;
 704                         break;
 705                 case MONO_TYPE_VOID:
 706                         break;
 707                 default:
 708                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 709                 }
 710         }
 711
 712         pstart = 0;
 713         /*
 714          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 715          * the first argument, allowing 'this' to be always passed in the first arg reg.
 716          * Also do this if the first argument is a reference type, since virtual calls
 717          * are sometimes made using calli without sig->hasthis set, like in the delegate
 718          * invoke wrappers.
 719          */
 720         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 721                 if (sig->hasthis) {
 722                         add_general (&gr, &stack_size, cinfo->args + 0);
 723                 } else {
 724                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 725                         pstart = 1;
 726                 }
 727                 add_general (&gr, &stack_size, &cinfo->ret);
 728                 cinfo->vret_arg_index = 1;
 729         } else {
 730                 /* this */
 731                 if (sig->hasthis)
 732                         add_general (&gr, &stack_size, cinfo->args + 0);
 733
 734                 if (cinfo->vtype_retaddr)
 735                         add_general (&gr, &stack_size, &cinfo->ret);
 736         }
 737
 738         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 739                 gr = PARAM_REGS;
 740                 fr = FLOAT_PARAM_REGS;
 741
 742                 /* Emit the signature cookie just before the implicit arguments */
 743                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 744         }
 745
 746         for (i = pstart; i < sig->param_count; ++i) {
 747                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 748                 MonoType *ptype;
 749
 750 #ifdef HOST_WIN32
 751                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 752                 if (gr > fr)
 753                         fr = gr;
 754                 else if (fr > gr)
 755                         gr = fr;
 756 #endif
 757
 758                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 759                         /* We allways pass the sig cookie on the stack for simplicity */
 760                         /*
 761                          * Prevent implicit arguments + the sig cookie from being passed
 762                          * in registers.
 763                          */
 764                         gr = PARAM_REGS;
 765                         fr = FLOAT_PARAM_REGS;
 766
 767                         /* Emit the signature cookie just before the implicit arguments */
 768                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 769                 }
 770
 771                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 772                 switch (ptype->type) {
 773                 case MONO_TYPE_BOOLEAN:
 774                 case MONO_TYPE_I1:
 775                 case MONO_TYPE_U1:
 776                         add_general (&gr, &stack_size, ainfo);
 777                         break;
 778                 case MONO_TYPE_I2:
 779                 case MONO_TYPE_U2:
 780                 case MONO_TYPE_CHAR:
 781                         add_general (&gr, &stack_size, ainfo);
 782                         break;
 783                 case MONO_TYPE_I4:
 784                 case MONO_TYPE_U4:
 785                         add_general (&gr, &stack_size, ainfo);
 786                         break;
 787                 case MONO_TYPE_I:
 788                 case MONO_TYPE_U:
 789                 case MONO_TYPE_PTR:
 790                 case MONO_TYPE_FNPTR:
 791                 case MONO_TYPE_CLASS:
 792                 case MONO_TYPE_OBJECT:
 793                 case MONO_TYPE_STRING:
 794                 case MONO_TYPE_SZARRAY:
 795                 case MONO_TYPE_ARRAY:
 796                         add_general (&gr, &stack_size, ainfo);
 797                         break;
 798                 case MONO_TYPE_GENERICINST:
 799                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 800                                 add_general (&gr, &stack_size, ainfo);
 801                                 break;
 802                         }
 803                         /* fall through */
 804                 case MONO_TYPE_VALUETYPE:
 805                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 806                         break;
 807                 case MONO_TYPE_TYPEDBYREF:
 808 #ifdef HOST_WIN32
 809                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 810 #else
 811                         stack_size += sizeof (MonoTypedRef);
 812                         ainfo->storage = ArgOnStack;
 813 #endif
 814                         break;
 815                 case MONO_TYPE_U8:
 816                 case MONO_TYPE_I8:
 817                         add_general (&gr, &stack_size, ainfo);
 818                         break;
 819                 case MONO_TYPE_R4:
 820                         add_float (&fr, &stack_size, ainfo, FALSE);
 821                         break;
 822                 case MONO_TYPE_R8:
 823                         add_float (&fr, &stack_size, ainfo, TRUE);
 824                         break;
 825                 default:
 826                         g_assert_not_reached ();
 827                 }
 828         }
 829
 830         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 831                 gr = PARAM_REGS;
 832                 fr = FLOAT_PARAM_REGS;
 833
 834                 /* Emit the signature cookie just before the implicit arguments */
 835                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 836         }
 837
 838 #ifdef HOST_WIN32
 839         // There always is 32 bytes reserved on the stack when calling on Winx64
 840         stack_size += 0x20;
 841 #endif
 842
 843         if (stack_size & 0x8) {
 844                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 845                 cinfo->need_stack_align = TRUE;
 846                 stack_size += 8;
 847         }
 848
 849         cinfo->stack_usage = stack_size;
 850         cinfo->reg_usage = gr;
 851         cinfo->freg_usage = fr;
 852         return cinfo;
 853 }
 854
 855 /*
 856  * mono_arch_get_argument_info:
 857  * @csig:  a method signature
 858  * @param_count: the number of parameters to consider
 859  * @arg_info: an array to store the result infos
 860  *
 861  * Gathers information on parameters such as size, alignment and
 862  * padding. arg_info should be large enought to hold param_count + 1 entries.
 863  *
 864  * Returns the size of the argument area on the stack.
 865  */
 866 int
 867 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 868 {
 869         int k;
 870         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
 871         guint32 args_size = cinfo->stack_usage;
 872
 873         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 874         if (csig->hasthis) {
 875                 arg_info [0].offset = 0;
 876         }
 877
 878         for (k = 0; k < param_count; k++) {
 879                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 880                 /* FIXME: */
 881                 arg_info [k + 1].size = 0;
 882         }
 883
 884         g_free (cinfo);
 885
 886         return args_size;
 887 }
 888
 889 gboolean
 890 mono_amd64_tail_call_supported (MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
 891 {
 892         CallInfo *c1, *c2;
 893         gboolean res;
 894
 895         c1 = get_call_info (NULL, NULL, caller_sig);
 896         c2 = get_call_info (NULL, NULL, callee_sig);
 897         res = c1->stack_usage >= c2->stack_usage;
 898         if (callee_sig->ret && MONO_TYPE_ISSTRUCT (callee_sig->ret) && c2->ret.storage != ArgValuetypeInReg)
 899                 /* An address on the callee's stack is passed as the first argument */
 900                 res = FALSE;
 901
 902         g_free (c1);
 903         g_free (c2);
 904
 905         return res;
 906 }
 907
 908 static int
 909 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 910 {
 911 #ifndef _MSC_VER
 912         __asm__ __volatile__ ("cpuid"
 913                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 914                 : "a" (id));
 915 #else
 916         int info[4];
 917         __cpuid(info, id);
 918         *p_eax = info[0];
 919         *p_ebx = info[1];
 920         *p_ecx = info[2];
 921         *p_edx = info[3];
 922 #endif
 923         return 1;
 924 }
 925
 926 /*
 927  * Initialize the cpu to execute managed code.
 928  */
 929 void
 930 mono_arch_cpu_init (void)
 931 {
 932 #ifndef _MSC_VER
 933         guint16 fpcw;
 934
 935         /* spec compliance requires running with double precision */
 936         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 937         fpcw &= ~X86_FPCW_PRECC_MASK;
 938         fpcw |= X86_FPCW_PREC_DOUBLE;
 939         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 940         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 941 #else
 942         /* TODO: This is crashing on Win64 right now.
 943         * _control87 (_PC_53, MCW_PC);
 944         */
 945 #endif
 946 }
 947
 948 /*
 949  * Initialize architecture specific code.
 950  */
 951 void
 952 mono_arch_init (void)
 953 {
 954         int flags;
 955
 956         InitializeCriticalSection (&mini_arch_mutex);
 957
 958 #ifdef MONO_ARCH_NOMAP32BIT
 959         flags = MONO_MMAP_READ;
 960         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
 961         breakpoint_size = 13;
 962         breakpoint_fault_size = 3;
 963         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
 964         single_step_fault_size = 5;
 965 #else
 966         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
 967         /* amd64_mov_reg_mem () */
 968         breakpoint_size = 8;
 969         breakpoint_fault_size = 8;
 970         single_step_fault_size = 8;
 971 #endif
 972
 973         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 974         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 975         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 976
 977         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
 978         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
 979         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
 980 }
 981
 982 /*
 983  * Cleanup architecture specific code.
 984  */
 985 void
 986 mono_arch_cleanup (void)
 987 {
 988         DeleteCriticalSection (&mini_arch_mutex);
 989 }
 990
 991 /*
 992  * This function returns the optimizations supported on this cpu.
 993  */
 994 guint32
 995 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 996 {
 997         int eax, ebx, ecx, edx;
 998         guint32 opts = 0;
 999
1000         *exclude_mask = 0;
1001         /* Feature Flags function, flags returned in EDX. */
1002         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1003                 if (edx & (1 << 15)) {
1004                         opts |= MONO_OPT_CMOV;
1005                         if (edx & 1)
1006                                 opts |= MONO_OPT_FCMOV;
1007                         else
1008                                 *exclude_mask |= MONO_OPT_FCMOV;
1009                 } else
1010                         *exclude_mask |= MONO_OPT_CMOV;
1011         }
1012
1013         return opts;
1014 }
1015
1016 /*
1017  * This function test for all SSE functions supported.
1018  *
1019  * Returns a bitmask corresponding to all supported versions.
1020  *
1021  */
1022 guint32
1023 mono_arch_cpu_enumerate_simd_versions (void)
1024 {
1025         int eax, ebx, ecx, edx;
1026         guint32 sse_opts = 0;
1027
1028         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1029                 if (edx & (1 << 25))
1030                         sse_opts |= SIMD_VERSION_SSE1;
1031                 if (edx & (1 << 26))
1032                         sse_opts |= SIMD_VERSION_SSE2;
1033                 if (ecx & (1 << 0))
1034                         sse_opts |= SIMD_VERSION_SSE3;
1035                 if (ecx & (1 << 9))
1036                         sse_opts |= SIMD_VERSION_SSSE3;
1037                 if (ecx & (1 << 19))
1038                         sse_opts |= SIMD_VERSION_SSE41;
1039                 if (ecx & (1 << 20))
1040                         sse_opts |= SIMD_VERSION_SSE42;
1041         }
1042
1043         /* Yes, all this needs to be done to check for sse4a.
1044            See: "Amd: CPUID Specification"
1045          */
1046         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1047                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1048                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1049                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1050                         if (ecx & (1 << 6))
1051                                 sse_opts |= SIMD_VERSION_SSE4a;
1052                 }
1053         }
1054
1055         return sse_opts;
1056 }
1057
1058 #ifndef DISABLE_JIT
1059
1060 GList *
1061 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1062 {
1063         GList *vars = NULL;
1064         int i;
1065
1066         for (i = 0; i < cfg->num_varinfo; i++) {
1067                 MonoInst *ins = cfg->varinfo [i];
1068                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1069
1070                 /* unused vars */
1071                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1072                         continue;
1073
1074                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1075                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1076                         continue;
1077
1078                 if (mono_is_regsize_var (ins->inst_vtype)) {
1079                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1080                         g_assert (i == vmv->idx);
1081                         vars = g_list_prepend (vars, vmv);
1082                 }
1083         }
1084
1085         vars = mono_varlist_sort (cfg, vars, 0);
1086
1087         return vars;
1088 }
1089
1090 /**
1091  * mono_arch_compute_omit_fp:
1092  *
1093  *   Determine whenever the frame pointer can be eliminated.
1094  */
1095 static void
1096 mono_arch_compute_omit_fp (MonoCompile *cfg)
1097 {
1098         MonoMethodSignature *sig;
1099         MonoMethodHeader *header;
1100         int i, locals_size;
1101         CallInfo *cinfo;
1102
1103         if (cfg->arch.omit_fp_computed)
1104                 return;
1105
1106         header = cfg->header;
1107
1108         sig = mono_method_signature (cfg->method);
1109
1110         if (!cfg->arch.cinfo)
1111                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1112         cinfo = cfg->arch.cinfo;
1113
1114         /*
1115          * FIXME: Remove some of the restrictions.
1116          */
1117         cfg->arch.omit_fp = TRUE;
1118         cfg->arch.omit_fp_computed = TRUE;
1119
1120         if (cfg->disable_omit_fp)
1121                 cfg->arch.omit_fp = FALSE;
1122
1123         if (!debug_omit_fp ())
1124                 cfg->arch.omit_fp = FALSE;
1125         /*
1126         if (cfg->method->save_lmf)
1127                 cfg->arch.omit_fp = FALSE;
1128         */
1129         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1130                 cfg->arch.omit_fp = FALSE;
1131         if (header->num_clauses)
1132                 cfg->arch.omit_fp = FALSE;
1133         if (cfg->param_area)
1134                 cfg->arch.omit_fp = FALSE;
1135         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1136                 cfg->arch.omit_fp = FALSE;
1137         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1138                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1139                 cfg->arch.omit_fp = FALSE;
1140         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1141                 ArgInfo *ainfo = &cinfo->args [i];
1142
1143                 if (ainfo->storage == ArgOnStack) {
1144                         /*
1145                          * The stack offset can only be determined when the frame
1146                          * size is known.
1147                          */
1148                         cfg->arch.omit_fp = FALSE;
1149                 }
1150         }
1151
1152         locals_size = 0;
1153         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1154                 MonoInst *ins = cfg->varinfo [i];
1155                 int ialign;
1156
1157                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1158         }
1159 }
1160
1161 GList *
1162 mono_arch_get_global_int_regs (MonoCompile *cfg)
1163 {
1164         GList *regs = NULL;
1165
1166         mono_arch_compute_omit_fp (cfg);
1167
1168         if (cfg->globalra) {
1169                 if (cfg->arch.omit_fp)
1170                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1171
1172                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1173                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1174                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1175                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1176                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1177
1178                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1179                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1180                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1181                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1182                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1183                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1184                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1185                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1186         } else {
1187                 if (cfg->arch.omit_fp)
1188                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1189
1190                 /* We use the callee saved registers for global allocation */
1191                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1192                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1193                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1194                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1195                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1196 #ifdef HOST_WIN32
1197                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1198                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1199 #endif
1200         }
1201
1202         return regs;
1203 }
1204
1205 GList*
1206 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1207 {
1208         GList *regs = NULL;
1209         int i;
1210
1211         /* All XMM registers */
1212         for (i = 0; i < 16; ++i)
1213                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1214
1215         return regs;
1216 }
1217
1218 GList*
1219 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1220 {
1221         static GList *r = NULL;
1222
1223         if (r == NULL) {
1224                 GList *regs = NULL;
1225
1226                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1227                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1228                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1229                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1230                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1231                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1232
1233                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1234                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1235                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1236                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1237                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1238                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1239                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1240                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1241
1242                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1243         }
1244
1245         return r;
1246 }
1247
1248 GList*
1249 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1250 {
1251         int i;
1252         static GList *r = NULL;
1253
1254         if (r == NULL) {
1255                 GList *regs = NULL;
1256
1257                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1258                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1259
1260                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1261         }
1262
1263         return r;
1264 }
1265
1266 /*
1267  * mono_arch_regalloc_cost:
1268  *
1269  *  Return the cost, in number of memory references, of the action of
1270  * allocating the variable VMV into a register during global register
1271  * allocation.
1272  */
1273 guint32
1274 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1275 {
1276         MonoInst *ins = cfg->varinfo [vmv->idx];
1277
1278         if (cfg->method->save_lmf)
1279                 /* The register is already saved */
1280                 /* substract 1 for the invisible store in the prolog */
1281                 return (ins->opcode == OP_ARG) ? 0 : 1;
1282         else
1283                 /* push+pop */
1284                 return (ins->opcode == OP_ARG) ? 1 : 2;
1285 }
1286
1287 /*
1288  * mono_arch_fill_argument_info:
1289  *
1290  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1291  * of the method.
1292  */
1293 void
1294 mono_arch_fill_argument_info (MonoCompile *cfg)
1295 {
1296         MonoMethodSignature *sig;
1297         MonoMethodHeader *header;
1298         MonoInst *ins;
1299         int i;
1300         CallInfo *cinfo;
1301
1302         header = cfg->header;
1303
1304         sig = mono_method_signature (cfg->method);
1305
1306         cinfo = cfg->arch.cinfo;
1307
1308         /*
1309          * Contrary to mono_arch_allocate_vars (), the information should describe
1310          * where the arguments are at the beginning of the method, not where they can be
1311          * accessed during the execution of the method. The later makes no sense for the
1312          * global register allocator, since a variable can be in more than one location.
1313          */
1314         if (sig->ret->type != MONO_TYPE_VOID) {
1315                 switch (cinfo->ret.storage) {
1316                 case ArgInIReg:
1317                 case ArgInFloatSSEReg:
1318                 case ArgInDoubleSSEReg:
1319                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1320                                 cfg->vret_addr->opcode = OP_REGVAR;
1321                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1322                         }
1323                         else {
1324                                 cfg->ret->opcode = OP_REGVAR;
1325                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1326                         }
1327                         break;
1328                 case ArgValuetypeInReg:
1329                         cfg->ret->opcode = OP_REGOFFSET;
1330                         cfg->ret->inst_basereg = -1;
1331                         cfg->ret->inst_offset = -1;
1332                         break;
1333                 default:
1334                         g_assert_not_reached ();
1335                 }
1336         }
1337
1338         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1339                 ArgInfo *ainfo = &cinfo->args [i];
1340                 MonoType *arg_type;
1341
1342                 ins = cfg->args [i];
1343
1344                 if (sig->hasthis && (i == 0))
1345                         arg_type = &mono_defaults.object_class->byval_arg;
1346                 else
1347                         arg_type = sig->params [i - sig->hasthis];
1348
1349                 switch (ainfo->storage) {
1350                 case ArgInIReg:
1351                 case ArgInFloatSSEReg:
1352                 case ArgInDoubleSSEReg:
1353                         ins->opcode = OP_REGVAR;
1354                         ins->inst_c0 = ainfo->reg;
1355                         break;
1356                 case ArgOnStack:
1357                         ins->opcode = OP_REGOFFSET;
1358                         ins->inst_basereg = -1;
1359                         ins->inst_offset = -1;
1360                         break;
1361                 case ArgValuetypeInReg:
1362                         /* Dummy */
1363                         ins->opcode = OP_NOP;
1364                         break;
1365                 default:
1366                         g_assert_not_reached ();
1367                 }
1368         }
1369 }
1370
1371 void
1372 mono_arch_allocate_vars (MonoCompile *cfg)
1373 {
1374         MonoMethodSignature *sig;
1375         MonoMethodHeader *header;
1376         MonoInst *ins;
1377         int i, offset;
1378         guint32 locals_stack_size, locals_stack_align;
1379         gint32 *offsets;
1380         CallInfo *cinfo;
1381
1382         header = cfg->header;
1383
1384         sig = mono_method_signature (cfg->method);
1385
1386         cinfo = cfg->arch.cinfo;
1387
1388         mono_arch_compute_omit_fp (cfg);
1389
1390         /*
1391          * We use the ABI calling conventions for managed code as well.
1392          * Exception: valuetypes are only sometimes passed or returned in registers.
1393          */
1394
1395         /*
1396          * The stack looks like this:
1397          * <incoming arguments passed on the stack>
1398          * <return value>
1399          * <lmf/caller saved registers>
1400          * <locals>
1401          * <spill area>
1402          * <localloc area>  -> grows dynamically
1403          * <params area>
1404          */
1405
1406         if (cfg->arch.omit_fp) {
1407                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1408                 cfg->frame_reg = AMD64_RSP;
1409                 offset = 0;
1410         } else {
1411                 /* Locals are allocated backwards from %fp */
1412                 cfg->frame_reg = AMD64_RBP;
1413                 offset = 0;
1414         }
1415
1416         if (cfg->method->save_lmf) {
1417                 /* Reserve stack space for saving LMF */
1418                 if (cfg->arch.omit_fp) {
1419                         cfg->arch.lmf_offset = offset;
1420                         offset += sizeof (MonoLMF);
1421                 }
1422                 else {
1423                         offset += sizeof (MonoLMF);
1424                         cfg->arch.lmf_offset = -offset;
1425                 }
1426         } else {
1427                 if (cfg->arch.omit_fp)
1428                         cfg->arch.reg_save_area_offset = offset;
1429                 /* Reserve space for caller saved registers */
1430                 for (i = 0; i < AMD64_NREG; ++i)
1431                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1432                                 offset += sizeof (gpointer);
1433                         }
1434         }
1435
1436         if (sig->ret->type != MONO_TYPE_VOID) {
1437                 switch (cinfo->ret.storage) {
1438                 case ArgInIReg:
1439                 case ArgInFloatSSEReg:
1440                 case ArgInDoubleSSEReg:
1441                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1442                                 if (cfg->globalra) {
1443                                         cfg->vret_addr->opcode = OP_REGVAR;
1444                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1445                                 } else {
1446                                         /* The register is volatile */
1447                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1448                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1449                                         if (cfg->arch.omit_fp) {
1450                                                 cfg->vret_addr->inst_offset = offset;
1451                                                 offset += 8;
1452                                         } else {
1453                                                 offset += 8;
1454                                                 cfg->vret_addr->inst_offset = -offset;
1455                                         }
1456                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1457                                                 printf ("vret_addr =");
1458                                                 mono_print_ins (cfg->vret_addr);
1459                                         }
1460                                 }
1461                         }
1462                         else {
1463                                 cfg->ret->opcode = OP_REGVAR;
1464                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1465                         }
1466                         break;
1467                 case ArgValuetypeInReg:
1468                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1469                         cfg->ret->opcode = OP_REGOFFSET;
1470                         cfg->ret->inst_basereg = cfg->frame_reg;
1471                         if (cfg->arch.omit_fp) {
1472                                 cfg->ret->inst_offset = offset;
1473                                 offset += 16;
1474                         } else {
1475                                 offset += 16;
1476                                 cfg->ret->inst_offset = - offset;
1477                         }
1478                         break;
1479                 default:
1480                         g_assert_not_reached ();
1481                 }
1482                 if (!cfg->globalra)
1483                         cfg->ret->dreg = cfg->ret->inst_c0;
1484         }
1485
1486         /* Allocate locals */
1487         if (!cfg->globalra) {
1488                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1489                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1490                         char *mname = mono_method_full_name (cfg->method, TRUE);
1491                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1492                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1493                         g_free (mname);
1494                         return;
1495                 }
1496
1497                 if (locals_stack_align) {
1498                         offset += (locals_stack_align - 1);
1499                         offset &= ~(locals_stack_align - 1);
1500                 }
1501                 if (cfg->arch.omit_fp) {
1502                         cfg->locals_min_stack_offset = offset;
1503                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1504                 } else {
1505                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1506                         cfg->locals_max_stack_offset = - offset;
1507                 }
1508
1509                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1510                         if (offsets [i] != -1) {
1511                                 MonoInst *ins = cfg->varinfo [i];
1512                                 ins->opcode = OP_REGOFFSET;
1513                                 ins->inst_basereg = cfg->frame_reg;
1514                                 if (cfg->arch.omit_fp)
1515                                         ins->inst_offset = (offset + offsets [i]);
1516                                 else
1517                                         ins->inst_offset = - (offset + offsets [i]);
1518                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1519                         }
1520                 }
1521                 offset += locals_stack_size;
1522         }
1523
1524         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1525                 g_assert (!cfg->arch.omit_fp);
1526                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1527                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1528         }
1529
1530         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1531                 ins = cfg->args [i];
1532                 if (ins->opcode != OP_REGVAR) {
1533                         ArgInfo *ainfo = &cinfo->args [i];
1534                         gboolean inreg = TRUE;
1535                         MonoType *arg_type;
1536
1537                         if (sig->hasthis && (i == 0))
1538                                 arg_type = &mono_defaults.object_class->byval_arg;
1539                         else
1540                                 arg_type = sig->params [i - sig->hasthis];
1541
1542                         if (cfg->globalra) {
1543                                 /* The new allocator needs info about the original locations of the arguments */
1544                                 switch (ainfo->storage) {
1545                                 case ArgInIReg:
1546                                 case ArgInFloatSSEReg:
1547                                 case ArgInDoubleSSEReg:
1548                                         ins->opcode = OP_REGVAR;
1549                                         ins->inst_c0 = ainfo->reg;
1550                                         break;
1551                                 case ArgOnStack:
1552                                         g_assert (!cfg->arch.omit_fp);
1553                                         ins->opcode = OP_REGOFFSET;
1554                                         ins->inst_basereg = cfg->frame_reg;
1555                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1556                                         break;
1557                                 case ArgValuetypeInReg:
1558                                         ins->opcode = OP_REGOFFSET;
1559                                         ins->inst_basereg = cfg->frame_reg;
1560                                         /* These arguments are saved to the stack in the prolog */
1561                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1562                                         if (cfg->arch.omit_fp) {
1563                                                 ins->inst_offset = offset;
1564                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (gpointer) : sizeof (gpointer);
1565                                         } else {
1566                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (gpointer) : sizeof (gpointer);
1567                                                 ins->inst_offset = - offset;
1568                                         }
1569                                         break;
1570                                 default:
1571                                         g_assert_not_reached ();
1572                                 }
1573
1574                                 continue;
1575                         }
1576
1577                         /* FIXME: Allocate volatile arguments to registers */
1578                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1579                                 inreg = FALSE;
1580
1581                         /*
1582                          * Under AMD64, all registers used to pass arguments to functions
1583                          * are volatile across calls.
1584                          * FIXME: Optimize this.
1585                          */
1586                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1587                                 inreg = FALSE;
1588
1589                         ins->opcode = OP_REGOFFSET;
1590
1591                         switch (ainfo->storage) {
1592                         case ArgInIReg:
1593                         case ArgInFloatSSEReg:
1594                         case ArgInDoubleSSEReg:
1595                                 if (inreg) {
1596                                         ins->opcode = OP_REGVAR;
1597                                         ins->dreg = ainfo->reg;
1598                                 }
1599                                 break;
1600                         case ArgOnStack:
1601                                 g_assert (!cfg->arch.omit_fp);
1602                                 ins->opcode = OP_REGOFFSET;
1603                                 ins->inst_basereg = cfg->frame_reg;
1604                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1605                                 break;
1606                         case ArgValuetypeInReg:
1607                                 break;
1608                         case ArgValuetypeAddrInIReg: {
1609                                 MonoInst *indir;
1610                                 g_assert (!cfg->arch.omit_fp);
1611
1612                                 MONO_INST_NEW (cfg, indir, 0);
1613                                 indir->opcode = OP_REGOFFSET;
1614                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1615                                         indir->inst_basereg = cfg->frame_reg;
1616                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1617                                         offset += (sizeof (gpointer));
1618                                         indir->inst_offset = - offset;
1619                                 }
1620                                 else {
1621                                         indir->inst_basereg = cfg->frame_reg;
1622                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1623                                 }
1624
1625                                 ins->opcode = OP_VTARG_ADDR;
1626                                 ins->inst_left = indir;
1627
1628                                 break;
1629                         }
1630                         default:
1631                                 NOT_IMPLEMENTED;
1632                         }
1633
1634                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1635                                 ins->opcode = OP_REGOFFSET;
1636                                 ins->inst_basereg = cfg->frame_reg;
1637                                 /* These arguments are saved to the stack in the prolog */
1638                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1639                                 if (cfg->arch.omit_fp) {
1640                                         ins->inst_offset = offset;
1641                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (gpointer) : sizeof (gpointer);
1642                                         // Arguments are yet supported by the stack map creation code
1643                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1644                                 } else {
1645                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (gpointer) : sizeof (gpointer);
1646                                         ins->inst_offset = - offset;
1647                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1648                                 }
1649                         }
1650                 }
1651         }
1652
1653         cfg->stack_offset = offset;
1654 }
1655
1656 void
1657 mono_arch_create_vars (MonoCompile *cfg)
1658 {
1659         MonoMethodSignature *sig;
1660         CallInfo *cinfo;
1661
1662         sig = mono_method_signature (cfg->method);
1663
1664         if (!cfg->arch.cinfo)
1665                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1666         cinfo = cfg->arch.cinfo;
1667
1668         if (cinfo->ret.storage == ArgValuetypeInReg)
1669                 cfg->ret_var_is_local = TRUE;
1670
1671         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1672                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1673                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1674                         printf ("vret_addr = ");
1675                         mono_print_ins (cfg->vret_addr);
1676                 }
1677         }
1678
1679         if (cfg->gen_seq_points) {
1680                 MonoInst *ins;
1681
1682             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1683                 ins->flags |= MONO_INST_VOLATILE;
1684                 cfg->arch.ss_trigger_page_var = ins;
1685         }
1686
1687 #ifdef MONO_AMD64_NO_PUSHES
1688         /*
1689          * When this is set, we pass arguments on the stack by moves, and by allocating
1690          * a bigger stack frame, instead of pushes.
1691          * Pushes complicate exception handling because the arguments on the stack have
1692          * to be popped each time a frame is unwound. They also make fp elimination
1693          * impossible.
1694          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1695          * on a new frame which doesn't include a param area.
1696          */
1697         cfg->arch.no_pushes = TRUE;
1698 #endif
1699 }
1700
1701 static void
1702 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1703 {
1704         MonoInst *ins;
1705
1706         switch (storage) {
1707         case ArgInIReg:
1708                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1709                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1710                 ins->sreg1 = tree->dreg;
1711                 MONO_ADD_INS (cfg->cbb, ins);
1712                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1713                 break;
1714         case ArgInFloatSSEReg:
1715                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1716                 ins->dreg = mono_alloc_freg (cfg);
1717                 ins->sreg1 = tree->dreg;
1718                 MONO_ADD_INS (cfg->cbb, ins);
1719
1720                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1721                 break;
1722         case ArgInDoubleSSEReg:
1723                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1724                 ins->dreg = mono_alloc_freg (cfg);
1725                 ins->sreg1 = tree->dreg;
1726                 MONO_ADD_INS (cfg->cbb, ins);
1727
1728                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1729
1730                 break;
1731         default:
1732                 g_assert_not_reached ();
1733         }
1734 }
1735
1736 static int
1737 arg_storage_to_load_membase (ArgStorage storage)
1738 {
1739         switch (storage) {
1740         case ArgInIReg:
1741                 return OP_LOAD_MEMBASE;
1742         case ArgInDoubleSSEReg:
1743                 return OP_LOADR8_MEMBASE;
1744         case ArgInFloatSSEReg:
1745                 return OP_LOADR4_MEMBASE;
1746         default:
1747                 g_assert_not_reached ();
1748         }
1749
1750         return -1;
1751 }
1752
1753 static void
1754 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1755 {
1756         MonoInst *arg;
1757         MonoMethodSignature *tmp_sig;
1758         MonoInst *sig_arg;
1759
1760         if (call->tail_call)
1761                 NOT_IMPLEMENTED;
1762
1763         /* FIXME: Add support for signature tokens to AOT */
1764         cfg->disable_aot = TRUE;
1765
1766         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1767
1768         /*
1769          * mono_ArgIterator_Setup assumes the signature cookie is
1770          * passed first and all the arguments which were before it are
1771          * passed on the stack after the signature. So compensate by
1772          * passing a different signature.
1773          */
1774         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1775         tmp_sig->param_count -= call->signature->sentinelpos;
1776         tmp_sig->sentinelpos = 0;
1777         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1778
1779         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1780         sig_arg->dreg = mono_alloc_ireg (cfg);
1781         sig_arg->inst_p0 = tmp_sig;
1782         MONO_ADD_INS (cfg->cbb, sig_arg);
1783
1784         if (cfg->arch.no_pushes) {
1785                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1786         } else {
1787                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1788                 arg->sreg1 = sig_arg->dreg;
1789                 MONO_ADD_INS (cfg->cbb, arg);
1790         }
1791 }
1792
1793 static inline LLVMArgStorage
1794 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1795 {
1796         switch (storage) {
1797         case ArgInIReg:
1798                 return LLVMArgInIReg;
1799         case ArgNone:
1800                 return LLVMArgNone;
1801         default:
1802                 g_assert_not_reached ();
1803                 return LLVMArgNone;
1804         }
1805 }
1806
1807 #ifdef ENABLE_LLVM
1808 LLVMCallInfo*
1809 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1810 {
1811         int i, n;
1812         CallInfo *cinfo;
1813         ArgInfo *ainfo;
1814         int j;
1815         LLVMCallInfo *linfo;
1816         MonoType *t;
1817
1818         n = sig->param_count + sig->hasthis;
1819
1820         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1821
1822         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1823
1824         /*
1825          * LLVM always uses the native ABI while we use our own ABI, the
1826          * only difference is the handling of vtypes:
1827          * - we only pass/receive them in registers in some cases, and only
1828          *   in 1 or 2 integer registers.
1829          */
1830         if (cinfo->ret.storage == ArgValuetypeInReg) {
1831                 if (sig->pinvoke) {
1832                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1833                         cfg->disable_llvm = TRUE;
1834                         return linfo;
1835                 }
1836
1837                 linfo->ret.storage = LLVMArgVtypeInReg;
1838                 for (j = 0; j < 2; ++j)
1839                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1840         }
1841
1842         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1843                 /* Vtype returned using a hidden argument */
1844                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1845                 linfo->vret_arg_index = cinfo->vret_arg_index;
1846         }
1847
1848         for (i = 0; i < n; ++i) {
1849                 ainfo = cinfo->args + i;
1850
1851                 if (i >= sig->hasthis)
1852                         t = sig->params [i - sig->hasthis];
1853                 else
1854                         t = &mono_defaults.int_class->byval_arg;
1855
1856                 linfo->args [i].storage = LLVMArgNone;
1857
1858                 switch (ainfo->storage) {
1859                 case ArgInIReg:
1860                         linfo->args [i].storage = LLVMArgInIReg;
1861                         break;
1862                 case ArgInDoubleSSEReg:
1863                 case ArgInFloatSSEReg:
1864                         linfo->args [i].storage = LLVMArgInFPReg;
1865                         break;
1866                 case ArgOnStack:
1867                         if (MONO_TYPE_ISSTRUCT (t)) {
1868                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1869                         } else {
1870                                 linfo->args [i].storage = LLVMArgInIReg;
1871                                 if (!t->byref) {
1872                                         if (t->type == MONO_TYPE_R4)
1873                                                 linfo->args [i].storage = LLVMArgInFPReg;
1874                                         else if (t->type == MONO_TYPE_R8)
1875                                                 linfo->args [i].storage = LLVMArgInFPReg;
1876                                 }
1877                         }
1878                         break;
1879                 case ArgValuetypeInReg:
1880                         if (sig->pinvoke) {
1881                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1882                                 cfg->disable_llvm = TRUE;
1883                                 return linfo;
1884                         }
1885
1886                         linfo->args [i].storage = LLVMArgVtypeInReg;
1887                         for (j = 0; j < 2; ++j)
1888                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1889                         break;
1890                 default:
1891                         cfg->exception_message = g_strdup ("ainfo->storage");
1892                         cfg->disable_llvm = TRUE;
1893                         break;
1894                 }
1895         }
1896
1897         return linfo;
1898 }
1899 #endif
1900
1901 void
1902 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1903 {
1904         MonoInst *arg, *in;
1905         MonoMethodSignature *sig;
1906         int i, n, stack_size;
1907         CallInfo *cinfo;
1908         ArgInfo *ainfo;
1909
1910         stack_size = 0;
1911
1912         sig = call->signature;
1913         n = sig->param_count + sig->hasthis;
1914
1915         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1916
1917         if (COMPILE_LLVM (cfg)) {
1918                 /* We shouldn't be called in the llvm case */
1919                 cfg->disable_llvm = TRUE;
1920                 return;
1921         }
1922
1923         if (cinfo->need_stack_align) {
1924                 if (!cfg->arch.no_pushes)
1925                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1926         }
1927
1928         /*
1929          * Emit all arguments which are passed on the stack to prevent register
1930          * allocation problems.
1931          */
1932         if (cfg->arch.no_pushes) {
1933                 for (i = 0; i < n; ++i) {
1934                         MonoType *t;
1935                         ainfo = cinfo->args + i;
1936
1937                         in = call->args [i];
1938
1939                         if (sig->hasthis && i == 0)
1940                                 t = &mono_defaults.object_class->byval_arg;
1941                         else
1942                                 t = sig->params [i - sig->hasthis];
1943
1944                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1945                                 if (!t->byref) {
1946                                         if (t->type == MONO_TYPE_R4)
1947                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1948                                         else if (t->type == MONO_TYPE_R8)
1949                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1950                                         else
1951                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1952                                 } else {
1953                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1954                                 }
1955                         }
1956                 }
1957         }
1958
1959         /*
1960          * Emit all parameters passed in registers in non-reverse order for better readability
1961          * and to help the optimization in emit_prolog ().
1962          */
1963         for (i = 0; i < n; ++i) {
1964                 ainfo = cinfo->args + i;
1965
1966                 in = call->args [i];
1967
1968                 if (ainfo->storage == ArgInIReg)
1969                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1970         }
1971
1972         for (i = n - 1; i >= 0; --i) {
1973                 ainfo = cinfo->args + i;
1974
1975                 in = call->args [i];
1976
1977                 switch (ainfo->storage) {
1978                 case ArgInIReg:
1979                         /* Already done */
1980                         break;
1981                 case ArgInFloatSSEReg:
1982                 case ArgInDoubleSSEReg:
1983                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1984                         break;
1985                 case ArgOnStack:
1986                 case ArgValuetypeInReg:
1987                 case ArgValuetypeAddrInIReg:
1988                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1989                                 MonoInst *call_inst = (MonoInst*)call;
1990                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1991                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1992                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1993                                 guint32 align;
1994                                 guint32 size;
1995
1996                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1997                                         size = sizeof (MonoTypedRef);
1998                                         align = sizeof (gpointer);
1999                                 }
2000                                 else {
2001                                         if (sig->pinvoke)
2002                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2003                                         else {
2004                                                 /*
2005                                                  * Other backends use mono_type_stack_size (), but that
2006                                                  * aligns the size to 8, which is larger than the size of
2007                                                  * the source, leading to reads of invalid memory if the
2008                                                  * source is at the end of address space.
2009                                                  */
2010                                                 size = mono_class_value_size (in->klass, &align);
2011                                         }
2012                                 }
2013                                 g_assert (in->klass);
2014
2015                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2016                                         /* Avoid asserts in emit_memcpy () */
2017                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2018                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2019                                         /* Continue normally */
2020                                 }
2021
2022                                 if (size > 0) {
2023                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2024                                         arg->sreg1 = in->dreg;
2025                                         arg->klass = in->klass;
2026                                         arg->backend.size = size;
2027                                         arg->inst_p0 = call;
2028                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2029                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2030
2031                                         MONO_ADD_INS (cfg->cbb, arg);
2032                                 }
2033                         } else {
2034                                 if (cfg->arch.no_pushes) {
2035                                         /* Already done */
2036                                 } else {
2037                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2038                                         arg->sreg1 = in->dreg;
2039                                         if (!sig->params [i - sig->hasthis]->byref) {
2040                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2041                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2042                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2043                                                         arg->inst_destbasereg = X86_ESP;
2044                                                         arg->inst_offset = 0;
2045                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2046                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2047                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2048                                                         arg->inst_destbasereg = X86_ESP;
2049                                                         arg->inst_offset = 0;
2050                                                 }
2051                                         }
2052                                         MONO_ADD_INS (cfg->cbb, arg);
2053                                 }
2054                         }
2055                         break;
2056                 default:
2057                         g_assert_not_reached ();
2058                 }
2059
2060                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2061                         /* Emit the signature cookie just before the implicit arguments */
2062                         emit_sig_cookie (cfg, call, cinfo);
2063         }
2064
2065         /* Handle the case where there are no implicit arguments */
2066         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2067                 emit_sig_cookie (cfg, call, cinfo);
2068
2069         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2070                 MonoInst *vtarg;
2071
2072                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2073                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2074                                 /*
2075                                  * Tell the JIT to use a more efficient calling convention: call using
2076                                  * OP_CALL, compute the result location after the call, and save the
2077                                  * result there.
2078                                  */
2079                                 call->vret_in_reg = TRUE;
2080                                 /*
2081                                  * Nullify the instruction computing the vret addr to enable
2082                                  * future optimizations.
2083                                  */
2084                                 if (call->vret_var)
2085                                         NULLIFY_INS (call->vret_var);
2086                         } else {
2087                                 if (call->tail_call)
2088                                         NOT_IMPLEMENTED;
2089                                 /*
2090                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2091                                  * the stack. Push the address here, so the call instruction can
2092                                  * access it.
2093                                  */
2094                                 if (!cfg->arch.vret_addr_loc) {
2095                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2096                                         /* Prevent it from being register allocated or optimized away */
2097                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2098                                 }
2099
2100                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2101                         }
2102                 }
2103                 else {
2104                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2105                         vtarg->sreg1 = call->vret_var->dreg;
2106                         vtarg->dreg = mono_alloc_preg (cfg);
2107                         MONO_ADD_INS (cfg->cbb, vtarg);
2108
2109                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2110                 }
2111         }
2112
2113 #ifdef HOST_WIN32
2114         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2115                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2116         }
2117 #endif
2118
2119         if (cfg->method->save_lmf) {
2120                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2121                 MONO_ADD_INS (cfg->cbb, arg);
2122         }
2123
2124         call->stack_usage = cinfo->stack_usage;
2125 }
2126
2127 void
2128 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2129 {
2130         MonoInst *arg;
2131         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2132         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2133         int size = ins->backend.size;
2134
2135         if (ainfo->storage == ArgValuetypeInReg) {
2136                 MonoInst *load;
2137                 int part;
2138
2139                 for (part = 0; part < 2; ++part) {
2140                         if (ainfo->pair_storage [part] == ArgNone)
2141                                 continue;
2142
2143                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2144                         load->inst_basereg = src->dreg;
2145                         load->inst_offset = part * sizeof (gpointer);
2146
2147                         switch (ainfo->pair_storage [part]) {
2148                         case ArgInIReg:
2149                                 load->dreg = mono_alloc_ireg (cfg);
2150                                 break;
2151                         case ArgInDoubleSSEReg:
2152                         case ArgInFloatSSEReg:
2153                                 load->dreg = mono_alloc_freg (cfg);
2154                                 break;
2155                         default:
2156                                 g_assert_not_reached ();
2157                         }
2158                         MONO_ADD_INS (cfg->cbb, load);
2159
2160                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2161                 }
2162         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2163                 MonoInst *vtaddr, *load;
2164                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2165
2166                 g_assert (!cfg->arch.no_pushes);
2167
2168                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2169                 load->inst_p0 = vtaddr;
2170                 vtaddr->flags |= MONO_INST_INDIRECT;
2171                 load->type = STACK_MP;
2172                 load->klass = vtaddr->klass;
2173                 load->dreg = mono_alloc_ireg (cfg);
2174                 MONO_ADD_INS (cfg->cbb, load);
2175                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2176
2177                 if (ainfo->pair_storage [0] == ArgInIReg) {
2178                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2179                         arg->dreg = mono_alloc_ireg (cfg);
2180                         arg->sreg1 = load->dreg;
2181                         arg->inst_imm = 0;
2182                         MONO_ADD_INS (cfg->cbb, arg);
2183                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2184                 } else {
2185                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2186                         arg->sreg1 = load->dreg;
2187                         MONO_ADD_INS (cfg->cbb, arg);
2188                 }
2189         } else {
2190                 if (size == 8) {
2191                         if (cfg->arch.no_pushes) {
2192                                 int dreg = mono_alloc_ireg (cfg);
2193
2194                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2195                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2196                         } else {
2197                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2198                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2199                                 arg->inst_basereg = src->dreg;
2200                                 arg->inst_offset = 0;
2201                                 MONO_ADD_INS (cfg->cbb, arg);
2202                         }
2203                 } else if (size <= 40) {
2204                         if (cfg->arch.no_pushes) {
2205                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2206                         } else {
2207                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2208                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2209                         }
2210                 } else {
2211                         if (cfg->arch.no_pushes) {
2212                                 // FIXME: Code growth
2213                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2214                         } else {
2215                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2216                                 arg->inst_basereg = src->dreg;
2217                                 arg->inst_offset = 0;
2218                                 arg->inst_imm = size;
2219                                 MONO_ADD_INS (cfg->cbb, arg);
2220                         }
2221                 }
2222         }
2223 }
2224
2225 void
2226 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2227 {
2228         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2229
2230         if (ret->type == MONO_TYPE_R4) {
2231                 if (COMPILE_LLVM (cfg))
2232                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2233                 else
2234                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2235                 return;
2236         } else if (ret->type == MONO_TYPE_R8) {
2237                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2238                 return;
2239         }
2240
2241         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2242 }
2243
2244 #endif /* DISABLE_JIT */
2245
2246 #define EMIT_COND_BRANCH(ins,cond,sign) \
2247         if (ins->inst_true_bb->native_offset) { \
2248                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2249         } else { \
2250                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2251                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2252             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2253                         x86_branch8 (code, cond, 0, sign); \
2254                 else \
2255                         x86_branch32 (code, cond, 0, sign); \
2256 }
2257
2258 typedef struct {
2259         MonoMethodSignature *sig;
2260         CallInfo *cinfo;
2261 } ArchDynCallInfo;
2262
2263 typedef struct {
2264         mgreg_t regs [PARAM_REGS];
2265         mgreg_t res;
2266         guint8 *ret;
2267 } DynCallArgs;
2268
2269 static gboolean
2270 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2271 {
2272         int i;
2273
2274 #ifdef HOST_WIN32
2275         return FALSE;
2276 #endif
2277
2278         switch (cinfo->ret.storage) {
2279         case ArgNone:
2280         case ArgInIReg:
2281                 break;
2282         case ArgValuetypeInReg: {
2283                 ArgInfo *ainfo = &cinfo->ret;
2284
2285                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2286                         return FALSE;
2287                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2288                         return FALSE;
2289                 break;
2290         }
2291         default:
2292                 return FALSE;
2293         }
2294
2295         for (i = 0; i < cinfo->nargs; ++i) {
2296                 ArgInfo *ainfo = &cinfo->args [i];
2297                 switch (ainfo->storage) {
2298                 case ArgInIReg:
2299                         break;
2300                 case ArgValuetypeInReg:
2301                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2302                                 return FALSE;
2303                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2304                                 return FALSE;
2305                         break;
2306                 default:
2307                         return FALSE;
2308                 }
2309         }
2310
2311         return TRUE;
2312 }
2313
2314 /*
2315  * mono_arch_dyn_call_prepare:
2316  *
2317  *   Return a pointer to an arch-specific structure which contains information
2318  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2319  * supported for SIG.
2320  * This function is equivalent to ffi_prep_cif in libffi.
2321  */
2322 MonoDynCallInfo*
2323 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2324 {
2325         ArchDynCallInfo *info;
2326         CallInfo *cinfo;
2327
2328         cinfo = get_call_info (NULL, NULL, sig);
2329
2330         if (!dyn_call_supported (sig, cinfo)) {
2331                 g_free (cinfo);
2332                 return NULL;
2333         }
2334
2335         info = g_new0 (ArchDynCallInfo, 1);
2336         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2337         info->sig = sig;
2338         info->cinfo = cinfo;
2339
2340         return (MonoDynCallInfo*)info;
2341 }
2342
2343 /*
2344  * mono_arch_dyn_call_free:
2345  *
2346  *   Free a MonoDynCallInfo structure.
2347  */
2348 void
2349 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2350 {
2351         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2352
2353         g_free (ainfo->cinfo);
2354         g_free (ainfo);
2355 }
2356
2357 /*
2358  * mono_arch_get_start_dyn_call:
2359  *
2360  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2361  * store the result into BUF.
2362  * ARGS should be an array of pointers pointing to the arguments.
2363  * RET should point to a memory buffer large enought to hold the result of the
2364  * call.
2365  * This function should be as fast as possible, any work which does not depend
2366  * on the actual values of the arguments should be done in
2367  * mono_arch_dyn_call_prepare ().
2368  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2369  * libffi.
2370  */
2371 void
2372 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2373 {
2374         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2375         DynCallArgs *p = (DynCallArgs*)buf;
2376         int arg_index, greg, i, pindex;
2377         MonoMethodSignature *sig = dinfo->sig;
2378
2379         g_assert (buf_len >= sizeof (DynCallArgs));
2380
2381         p->res = 0;
2382         p->ret = ret;
2383
2384         arg_index = 0;
2385         greg = 0;
2386         pindex = 0;
2387
2388         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2389                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2390                 if (!sig->hasthis)
2391                         pindex = 1;
2392         }
2393
2394         if (dinfo->cinfo->vtype_retaddr)
2395                 p->regs [greg ++] = (mgreg_t)ret;
2396
2397         for (i = pindex; i < sig->param_count; i++) {
2398                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2399                 gpointer *arg = args [arg_index ++];
2400
2401                 if (t->byref) {
2402                         p->regs [greg ++] = (mgreg_t)*(arg);
2403                         continue;
2404                 }
2405
2406                 switch (t->type) {
2407                 case MONO_TYPE_STRING:
2408                 case MONO_TYPE_CLASS:
2409                 case MONO_TYPE_ARRAY:
2410                 case MONO_TYPE_SZARRAY:
2411                 case MONO_TYPE_OBJECT:
2412                 case MONO_TYPE_PTR:
2413                 case MONO_TYPE_I:
2414                 case MONO_TYPE_U:
2415                 case MONO_TYPE_I8:
2416                 case MONO_TYPE_U8:
2417                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2418                         p->regs [greg ++] = (mgreg_t)*(arg);
2419                         break;
2420                 case MONO_TYPE_BOOLEAN:
2421                 case MONO_TYPE_U1:
2422                         p->regs [greg ++] = *(guint8*)(arg);
2423                         break;
2424                 case MONO_TYPE_I1:
2425                         p->regs [greg ++] = *(gint8*)(arg);
2426                         break;
2427                 case MONO_TYPE_I2:
2428                         p->regs [greg ++] = *(gint16*)(arg);
2429                         break;
2430                 case MONO_TYPE_U2:
2431                 case MONO_TYPE_CHAR:
2432                         p->regs [greg ++] = *(guint16*)(arg);
2433                         break;
2434                 case MONO_TYPE_I4:
2435                         p->regs [greg ++] = *(gint32*)(arg);
2436                         break;
2437                 case MONO_TYPE_U4:
2438                         p->regs [greg ++] = *(guint32*)(arg);
2439                         break;
2440                 case MONO_TYPE_GENERICINST:
2441                     if (MONO_TYPE_IS_REFERENCE (t)) {
2442                                 p->regs [greg ++] = (mgreg_t)*(arg);
2443                                 break;
2444                         } else {
2445                                 /* Fall through */
2446                         }
2447                 case MONO_TYPE_VALUETYPE: {
2448                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2449
2450                         g_assert (ainfo->storage == ArgValuetypeInReg);
2451                         if (ainfo->pair_storage [0] != ArgNone) {
2452                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2453                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2454                         }
2455                         if (ainfo->pair_storage [1] != ArgNone) {
2456                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2457                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2458                         }
2459                         break;
2460                 }
2461                 default:
2462                         g_assert_not_reached ();
2463                 }
2464         }
2465
2466         g_assert (greg <= PARAM_REGS);
2467 }
2468
2469 /*
2470  * mono_arch_finish_dyn_call:
2471  *
2472  *   Store the result of a dyn call into the return value buffer passed to
2473  * start_dyn_call ().
2474  * This function should be as fast as possible, any work which does not depend
2475  * on the actual values of the arguments should be done in
2476  * mono_arch_dyn_call_prepare ().
2477  */
2478 void
2479 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2480 {
2481         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2482         MonoMethodSignature *sig = dinfo->sig;
2483         guint8 *ret = ((DynCallArgs*)buf)->ret;
2484         mgreg_t res = ((DynCallArgs*)buf)->res;
2485
2486         switch (mono_type_get_underlying_type (sig->ret)->type) {
2487         case MONO_TYPE_VOID:
2488                 *(gpointer*)ret = NULL;
2489                 break;
2490         case MONO_TYPE_STRING:
2491         case MONO_TYPE_CLASS:
2492         case MONO_TYPE_ARRAY:
2493         case MONO_TYPE_SZARRAY:
2494         case MONO_TYPE_OBJECT:
2495         case MONO_TYPE_I:
2496         case MONO_TYPE_U:
2497         case MONO_TYPE_PTR:
2498                 *(gpointer*)ret = (gpointer)res;
2499                 break;
2500         case MONO_TYPE_I1:
2501                 *(gint8*)ret = res;
2502                 break;
2503         case MONO_TYPE_U1:
2504         case MONO_TYPE_BOOLEAN:
2505                 *(guint8*)ret = res;
2506                 break;
2507         case MONO_TYPE_I2:
2508                 *(gint16*)ret = res;
2509                 break;
2510         case MONO_TYPE_U2:
2511         case MONO_TYPE_CHAR:
2512                 *(guint16*)ret = res;
2513                 break;
2514         case MONO_TYPE_I4:
2515                 *(gint32*)ret = res;
2516                 break;
2517         case MONO_TYPE_U4:
2518                 *(guint32*)ret = res;
2519                 break;
2520         case MONO_TYPE_I8:
2521                 *(gint64*)ret = res;
2522                 break;
2523         case MONO_TYPE_U8:
2524                 *(guint64*)ret = res;
2525                 break;
2526         case MONO_TYPE_GENERICINST:
2527                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2528                         *(gpointer*)ret = (gpointer)res;
2529                         break;
2530                 } else {
2531                         /* Fall through */
2532                 }
2533         case MONO_TYPE_VALUETYPE:
2534                 if (dinfo->cinfo->vtype_retaddr) {
2535                         /* Nothing to do */
2536                 } else {
2537                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2538
2539                         g_assert (ainfo->storage == ArgValuetypeInReg);
2540
2541                         if (ainfo->pair_storage [0] != ArgNone) {
2542                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2543                                 ((mgreg_t*)ret)[0] = res;
2544                         }
2545
2546                         g_assert (ainfo->pair_storage [1] == ArgNone);
2547                 }
2548                 break;
2549         default:
2550                 g_assert_not_reached ();
2551         }
2552 }
2553
2554 /* emit an exception if condition is fail */
2555 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2556         do {                                                        \
2557                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2558                 if (tins == NULL) {                                                                             \
2559                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2560                                         MONO_PATCH_INFO_EXC, exc_name);  \
2561                         x86_branch32 (code, cond, 0, signed);               \
2562                 } else {        \
2563                         EMIT_COND_BRANCH (tins, cond, signed);  \
2564                 }                       \
2565         } while (0);
2566
2567 #define EMIT_FPCOMPARE(code) do { \
2568         amd64_fcompp (code); \
2569         amd64_fnstsw (code); \
2570 } while (0);
2571
2572 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2573     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2574         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2575         amd64_ ##op (code); \
2576         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2577         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2578 } while (0);
2579
2580 static guint8*
2581 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2582 {
2583         gboolean no_patch = FALSE;
2584
2585         /*
2586          * FIXME: Add support for thunks
2587          */
2588         {
2589                 gboolean near_call = FALSE;
2590
2591                 /*
2592                  * Indirect calls are expensive so try to make a near call if possible.
2593                  * The caller memory is allocated by the code manager so it is
2594                  * guaranteed to be at a 32 bit offset.
2595                  */
2596
2597                 if (patch_type != MONO_PATCH_INFO_ABS) {
2598                         /* The target is in memory allocated using the code manager */
2599                         near_call = TRUE;
2600
2601                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2602                                 if (((MonoMethod*)data)->klass->image->aot_module)
2603                                         /* The callee might be an AOT method */
2604                                         near_call = FALSE;
2605                                 if (((MonoMethod*)data)->dynamic)
2606                                         /* The target is in malloc-ed memory */
2607                                         near_call = FALSE;
2608                         }
2609
2610                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2611                                 /*
2612                                  * The call might go directly to a native function without
2613                                  * the wrapper.
2614                                  */
2615                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2616                                 if (mi) {
2617                                         gconstpointer target = mono_icall_get_wrapper (mi);
2618                                         if ((((guint64)target) >> 32) != 0)
2619                                                 near_call = FALSE;
2620                                 }
2621                         }
2622                 }
2623                 else {
2624                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2625                                 /*
2626                                  * This is not really an optimization, but required because the
2627                                  * generic class init trampolines use R11 to pass the vtable.
2628                                  */
2629                                 near_call = TRUE;
2630                         } else {
2631                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2632                                 if (info) {
2633                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2634                                                 strstr (cfg->method->name, info->name)) {
2635                                                 /* A call to the wrapped function */
2636                                                 if ((((guint64)data) >> 32) == 0)
2637                                                         near_call = TRUE;
2638                                                 no_patch = TRUE;
2639                                         }
2640                                         else if (info->func == info->wrapper) {
2641                                                 /* No wrapper */
2642                                                 if ((((guint64)info->func) >> 32) == 0)
2643                                                         near_call = TRUE;
2644                                         }
2645                                         else {
2646                                                 /* See the comment in mono_codegen () */
2647                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2648                                                         near_call = TRUE;
2649                                         }
2650                                 }
2651                                 else if ((((guint64)data) >> 32) == 0) {
2652                                         near_call = TRUE;
2653                                         no_patch = TRUE;
2654                                 }
2655                         }
2656                 }
2657
2658                 if (cfg->method->dynamic)
2659                         /* These methods are allocated using malloc */
2660                         near_call = FALSE;
2661
2662 #ifdef MONO_ARCH_NOMAP32BIT
2663                 near_call = FALSE;
2664 #endif
2665
2666                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2667                 if (optimize_for_xen)
2668                         near_call = FALSE;
2669
2670                 if (cfg->compile_aot) {
2671                         near_call = TRUE;
2672                         no_patch = TRUE;
2673                 }
2674
2675                 if (near_call) {
2676                         /*
2677                          * Align the call displacement to an address divisible by 4 so it does
2678                          * not span cache lines. This is required for code patching to work on SMP
2679                          * systems.
2680                          */
2681                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2682                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2683                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2684                         amd64_call_code (code, 0);
2685                 }
2686                 else {
2687                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2688                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2689                         amd64_call_reg (code, GP_SCRATCH_REG);
2690                 }
2691         }
2692
2693         return code;
2694 }
2695
2696 static inline guint8*
2697 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2698 {
2699 #ifdef HOST_WIN32
2700         if (win64_adjust_stack)
2701                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2702 #endif
2703         code = emit_call_body (cfg, code, patch_type, data);
2704 #ifdef HOST_WIN32
2705         if (win64_adjust_stack)
2706                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2707 #endif
2708
2709         return code;
2710 }
2711
2712 static inline int
2713 store_membase_imm_to_store_membase_reg (int opcode)
2714 {
2715         switch (opcode) {
2716         case OP_STORE_MEMBASE_IMM:
2717                 return OP_STORE_MEMBASE_REG;
2718         case OP_STOREI4_MEMBASE_IMM:
2719                 return OP_STOREI4_MEMBASE_REG;
2720         case OP_STOREI8_MEMBASE_IMM:
2721                 return OP_STOREI8_MEMBASE_REG;
2722         }
2723
2724         return -1;
2725 }
2726
2727 #ifndef DISABLE_JIT
2728
2729 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2730
2731 /*
2732  * mono_arch_peephole_pass_1:
2733  *
2734  *   Perform peephole opts which should/can be performed before local regalloc
2735  */
2736 void
2737 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2738 {
2739         MonoInst *ins, *n;
2740
2741         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2742                 MonoInst *last_ins = ins->prev;
2743
2744                 switch (ins->opcode) {
2745                 case OP_ADD_IMM:
2746                 case OP_IADD_IMM:
2747                 case OP_LADD_IMM:
2748                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2749                                 /*
2750                                  * X86_LEA is like ADD, but doesn't have the
2751                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2752                                  * its operand to 64 bit.
2753                                  */
2754                                 ins->opcode = OP_X86_LEA_MEMBASE;
2755                                 ins->inst_basereg = ins->sreg1;
2756                         }
2757                         break;
2758                 case OP_LXOR:
2759                 case OP_IXOR:
2760                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2761                                 MonoInst *ins2;
2762
2763                                 /*
2764                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2765                                  * the latter has length 2-3 instead of 6 (reverse constant
2766                                  * propagation). These instruction sequences are very common
2767                                  * in the initlocals bblock.
2768                                  */
2769                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2770                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2771                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2772                                                 ins2->sreg1 = ins->dreg;
2773                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2774                                                 /* Continue */
2775                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2776                                                 NULLIFY_INS (ins2);
2777                                                 /* Continue */
2778                                         } else {
2779                                                 break;
2780                                         }
2781                                 }
2782                         }
2783                         break;
2784                 case OP_COMPARE_IMM:
2785                 case OP_LCOMPARE_IMM:
2786                         /* OP_COMPARE_IMM (reg, 0)
2787                          * -->
2788                          * OP_AMD64_TEST_NULL (reg)
2789                          */
2790                         if (!ins->inst_imm)
2791                                 ins->opcode = OP_AMD64_TEST_NULL;
2792                         break;
2793                 case OP_ICOMPARE_IMM:
2794                         if (!ins->inst_imm)
2795                                 ins->opcode = OP_X86_TEST_NULL;
2796                         break;
2797                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2798                         /*
2799                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2800                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2801                          * -->
2802                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2803                          * OP_COMPARE_IMM reg, imm
2804                          *
2805                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2806                          */
2807                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2808                             ins->inst_basereg == last_ins->inst_destbasereg &&
2809                             ins->inst_offset == last_ins->inst_offset) {
2810                                         ins->opcode = OP_ICOMPARE_IMM;
2811                                         ins->sreg1 = last_ins->sreg1;
2812
2813                                         /* check if we can remove cmp reg,0 with test null */
2814                                         if (!ins->inst_imm)
2815                                                 ins->opcode = OP_X86_TEST_NULL;
2816                                 }
2817
2818                         break;
2819                 }
2820
2821                 mono_peephole_ins (bb, ins);
2822         }
2823 }
2824
2825 void
2826 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2827 {
2828         MonoInst *ins, *n;
2829
2830         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2831                 switch (ins->opcode) {
2832                 case OP_ICONST:
2833                 case OP_I8CONST: {
2834                         /* reg = 0 -> XOR (reg, reg) */
2835                         /* XOR sets cflags on x86, so we cant do it always */
2836                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2837                                 ins->opcode = OP_LXOR;
2838                                 ins->sreg1 = ins->dreg;
2839                                 ins->sreg2 = ins->dreg;
2840                                 /* Fall through */
2841                         } else {
2842                                 break;
2843                         }
2844                 }
2845                 case OP_LXOR:
2846                         /*
2847                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2848                          * 0 result into 64 bits.
2849                          */
2850                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2851                                 ins->opcode = OP_IXOR;
2852                         }
2853                         /* Fall through */
2854                 case OP_IXOR:
2855                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2856                                 MonoInst *ins2;
2857
2858                                 /*
2859                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2860                                  * the latter has length 2-3 instead of 6 (reverse constant
2861                                  * propagation). These instruction sequences are very common
2862                                  * in the initlocals bblock.
2863                                  */
2864                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2865                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2866                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2867                                                 ins2->sreg1 = ins->dreg;
2868                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
2869                                                 /* Continue */
2870                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2871                                                 NULLIFY_INS (ins2);
2872                                                 /* Continue */
2873                                         } else {
2874                                                 break;
2875                                         }
2876                                 }
2877                         }
2878                         break;
2879                 case OP_IADD_IMM:
2880                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2881                                 ins->opcode = OP_X86_INC_REG;
2882                         break;
2883                 case OP_ISUB_IMM:
2884                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2885                                 ins->opcode = OP_X86_DEC_REG;
2886                         break;
2887                 }
2888
2889                 mono_peephole_ins (bb, ins);
2890         }
2891 }
2892
2893 #define NEW_INS(cfg,ins,dest,op) do {   \
2894                 MONO_INST_NEW ((cfg), (dest), (op)); \
2895         (dest)->cil_code = (ins)->cil_code; \
2896         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2897         } while (0)
2898
2899 /*
2900  * mono_arch_lowering_pass:
2901  *
2902  *  Converts complex opcodes into simpler ones so that each IR instruction
2903  * corresponds to one machine instruction.
2904  */
2905 void
2906 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2907 {
2908         MonoInst *ins, *n, *temp;
2909
2910         /*
2911          * FIXME: Need to add more instructions, but the current machine
2912          * description can't model some parts of the composite instructions like
2913          * cdq.
2914          */
2915         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2916                 switch (ins->opcode) {
2917                 case OP_DIV_IMM:
2918                 case OP_REM_IMM:
2919                 case OP_IDIV_IMM:
2920                 case OP_IDIV_UN_IMM:
2921                 case OP_IREM_UN_IMM:
2922                         mono_decompose_op_imm (cfg, bb, ins);
2923                         break;
2924                 case OP_IREM_IMM:
2925                         /* Keep the opcode if we can implement it efficiently */
2926                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2927                                 mono_decompose_op_imm (cfg, bb, ins);
2928                         break;
2929                 case OP_COMPARE_IMM:
2930                 case OP_LCOMPARE_IMM:
2931                         if (!amd64_is_imm32 (ins->inst_imm)) {
2932                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2933                                 temp->inst_c0 = ins->inst_imm;
2934                                 temp->dreg = mono_alloc_ireg (cfg);
2935                                 ins->opcode = OP_COMPARE;
2936                                 ins->sreg2 = temp->dreg;
2937                         }
2938                         break;
2939                 case OP_LOAD_MEMBASE:
2940                 case OP_LOADI8_MEMBASE:
2941                         if (!amd64_is_imm32 (ins->inst_offset)) {
2942                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2943                                 temp->inst_c0 = ins->inst_offset;
2944                                 temp->dreg = mono_alloc_ireg (cfg);
2945                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2946                                 ins->inst_indexreg = temp->dreg;
2947                         }
2948                         break;
2949                 case OP_STORE_MEMBASE_IMM:
2950                 case OP_STOREI8_MEMBASE_IMM:
2951                         if (!amd64_is_imm32 (ins->inst_imm)) {
2952                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2953                                 temp->inst_c0 = ins->inst_imm;
2954                                 temp->dreg = mono_alloc_ireg (cfg);
2955                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2956                                 ins->sreg1 = temp->dreg;
2957                         }
2958                         break;
2959 #ifdef MONO_ARCH_SIMD_INTRINSICS
2960                 case OP_EXPAND_I1: {
2961                                 int temp_reg1 = mono_alloc_ireg (cfg);
2962                                 int temp_reg2 = mono_alloc_ireg (cfg);
2963                                 int original_reg = ins->sreg1;
2964
2965                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2966                                 temp->sreg1 = original_reg;
2967                                 temp->dreg = temp_reg1;
2968
2969                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2970                                 temp->sreg1 = temp_reg1;
2971                                 temp->dreg = temp_reg2;
2972                                 temp->inst_imm = 8;
2973
2974                                 NEW_INS (cfg, ins, temp, OP_LOR);
2975                                 temp->sreg1 = temp->dreg = temp_reg2;
2976                                 temp->sreg2 = temp_reg1;
2977
2978                                 ins->opcode = OP_EXPAND_I2;
2979                                 ins->sreg1 = temp_reg2;
2980                         }
2981                         break;
2982 #endif
2983                 default:
2984                         break;
2985                 }
2986         }
2987
2988         bb->max_vreg = cfg->next_vreg;
2989 }
2990
2991 static const int
2992 branch_cc_table [] = {
2993         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2994         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2995         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2996 };
2997
2998 /* Maps CMP_... constants to X86_CC_... constants */
2999 static const int
3000 cc_table [] = {
3001         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3002         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3003 };
3004
3005 static const int
3006 cc_signed_table [] = {
3007         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3008         FALSE, FALSE, FALSE, FALSE
3009 };
3010
3011 /*#include "cprop.c"*/
3012
3013 static unsigned char*
3014 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3015 {
3016         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3017
3018         if (size == 1)
3019                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3020         else if (size == 2)
3021                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3022         return code;
3023 }
3024
3025 static unsigned char*
3026 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3027 {
3028         int sreg = tree->sreg1;
3029         int need_touch = FALSE;
3030
3031 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3032         if (!tree->flags & MONO_INST_INIT)
3033                 need_touch = TRUE;
3034 #endif
3035
3036         if (need_touch) {
3037                 guint8* br[5];
3038
3039                 /*
3040                  * Under Windows:
3041                  * If requested stack size is larger than one page,
3042                  * perform stack-touch operation
3043                  */
3044                 /*
3045                  * Generate stack probe code.
3046                  * Under Windows, it is necessary to allocate one page at a time,
3047                  * "touching" stack after each successful sub-allocation. This is
3048                  * because of the way stack growth is implemented - there is a
3049                  * guard page before the lowest stack page that is currently commited.
3050                  * Stack normally grows sequentially so OS traps access to the
3051                  * guard page and commits more pages when needed.
3052                  */
3053                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3054                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3055
3056                 br[2] = code; /* loop */
3057                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3058                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3059                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3060                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3061                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3062                 amd64_patch (br[3], br[2]);
3063                 amd64_test_reg_reg (code, sreg, sreg);
3064                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3065                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3066
3067                 br[1] = code; x86_jump8 (code, 0);
3068
3069                 amd64_patch (br[0], code);
3070                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3071                 amd64_patch (br[1], code);
3072                 amd64_patch (br[4], code);
3073         }
3074         else
3075                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3076
3077         if (tree->flags & MONO_INST_INIT) {
3078                 int offset = 0;
3079                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3080                         amd64_push_reg (code, AMD64_RAX);
3081                         offset += 8;
3082                 }
3083                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3084                         amd64_push_reg (code, AMD64_RCX);
3085                         offset += 8;
3086                 }
3087                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3088                         amd64_push_reg (code, AMD64_RDI);
3089                         offset += 8;
3090                 }
3091
3092                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3093                 if (sreg != AMD64_RCX)
3094                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3095                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3096
3097                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3098                 if (cfg->param_area && cfg->arch.no_pushes)
3099                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3100                 amd64_cld (code);
3101                 amd64_prefix (code, X86_REP_PREFIX);
3102                 amd64_stosl (code);
3103
3104                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3105                         amd64_pop_reg (code, AMD64_RDI);
3106                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3107                         amd64_pop_reg (code, AMD64_RCX);
3108                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3109                         amd64_pop_reg (code, AMD64_RAX);
3110         }
3111         return code;
3112 }
3113
3114 static guint8*
3115 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3116 {
3117         CallInfo *cinfo;
3118         guint32 quad;
3119
3120         /* Move return value to the target register */
3121         /* FIXME: do this in the local reg allocator */
3122         switch (ins->opcode) {
3123         case OP_CALL:
3124         case OP_CALL_REG:
3125         case OP_CALL_MEMBASE:
3126         case OP_LCALL:
3127         case OP_LCALL_REG:
3128         case OP_LCALL_MEMBASE:
3129                 g_assert (ins->dreg == AMD64_RAX);
3130                 break;
3131         case OP_FCALL:
3132         case OP_FCALL_REG:
3133         case OP_FCALL_MEMBASE:
3134                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3135                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3136                 }
3137                 else {
3138                         if (ins->dreg != AMD64_XMM0)
3139                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3140                 }
3141                 break;
3142         case OP_VCALL:
3143         case OP_VCALL_REG:
3144         case OP_VCALL_MEMBASE:
3145         case OP_VCALL2:
3146         case OP_VCALL2_REG:
3147         case OP_VCALL2_MEMBASE:
3148                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3149                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3150                         MonoInst *loc = cfg->arch.vret_addr_loc;
3151
3152                         /* Load the destination address */
3153                         g_assert (loc->opcode == OP_REGOFFSET);
3154                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3155
3156                         for (quad = 0; quad < 2; quad ++) {
3157                                 switch (cinfo->ret.pair_storage [quad]) {
3158                                 case ArgInIReg:
3159                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3160                                         break;
3161                                 case ArgInFloatSSEReg:
3162                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3163                                         break;
3164                                 case ArgInDoubleSSEReg:
3165                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3166                                         break;
3167                                 case ArgNone:
3168                                         break;
3169                                 default:
3170                                         NOT_IMPLEMENTED;
3171                                 }
3172                         }
3173                 }
3174                 break;
3175         }
3176
3177         return code;
3178 }
3179
3180 #endif /* DISABLE_JIT */
3181
3182 /*
3183  * mono_amd64_emit_tls_get:
3184  * @code: buffer to store code to
3185  * @dreg: hard register where to place the result
3186  * @tls_offset: offset info
3187  *
3188  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3189  * the dreg register the item in the thread local storage identified
3190  * by tls_offset.
3191  *
3192  * Returns: a pointer to the end of the stored code
3193  */
3194 guint8*
3195 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3196 {
3197 #ifdef HOST_WIN32
3198         g_assert (tls_offset < 64);
3199         x86_prefix (code, X86_GS_PREFIX);
3200         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3201 #else
3202         if (optimize_for_xen) {
3203                 x86_prefix (code, X86_FS_PREFIX);
3204                 amd64_mov_reg_mem (code, dreg, 0, 8);
3205                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3206         } else {
3207                 x86_prefix (code, X86_FS_PREFIX);
3208                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3209         }
3210 #endif
3211         return code;
3212 }
3213
3214 #define REAL_PRINT_REG(text,reg) \
3215 mono_assert (reg >= 0); \
3216 amd64_push_reg (code, AMD64_RAX); \
3217 amd64_push_reg (code, AMD64_RDX); \
3218 amd64_push_reg (code, AMD64_RCX); \
3219 amd64_push_reg (code, reg); \
3220 amd64_push_imm (code, reg); \
3221 amd64_push_imm (code, text " %d %p\n"); \
3222 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3223 amd64_call_reg (code, AMD64_RAX); \
3224 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3225 amd64_pop_reg (code, AMD64_RCX); \
3226 amd64_pop_reg (code, AMD64_RDX); \
3227 amd64_pop_reg (code, AMD64_RAX);
3228
3229 /* benchmark and set based on cpu */
3230 #define LOOP_ALIGNMENT 8
3231 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3232
3233 #ifndef DISABLE_JIT
3234
3235 void
3236 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3237 {
3238         MonoInst *ins;
3239         MonoCallInst *call;
3240         guint offset;
3241         guint8 *code = cfg->native_code + cfg->code_len;
3242         MonoInst *last_ins = NULL;
3243         guint last_offset = 0;
3244         int max_len;
3245
3246         /* Fix max_offset estimate for each successor bb */
3247         if (cfg->opt & MONO_OPT_BRANCH) {
3248                 int current_offset = cfg->code_len;
3249                 MonoBasicBlock *current_bb;
3250                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3251                         current_bb->max_offset = current_offset;
3252                         current_offset += current_bb->max_length;
3253                 }
3254         }
3255
3256         if (cfg->opt & MONO_OPT_LOOP) {
3257                 int pad, align = LOOP_ALIGNMENT;
3258                 /* set alignment depending on cpu */
3259                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3260                         pad = align - pad;
3261                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3262                         amd64_padding (code, pad);
3263                         cfg->code_len += pad;
3264                         bb->native_offset = cfg->code_len;
3265                 }
3266         }
3267
3268         if (cfg->verbose_level > 2)
3269                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3270
3271         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3272                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3273                 g_assert (!cfg->compile_aot);
3274
3275                 cov->data [bb->dfn].cil_code = bb->cil_code;
3276                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3277                 /* this is not thread save, but good enough */
3278                 amd64_inc_membase (code, AMD64_R11, 0);
3279         }
3280
3281         offset = code - cfg->native_code;
3282
3283         mono_debug_open_block (cfg, bb, offset);
3284
3285     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3286                 x86_breakpoint (code);
3287
3288         MONO_BB_FOR_EACH_INS (bb, ins) {
3289                 offset = code - cfg->native_code;
3290
3291                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3292
3293                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3294                         cfg->code_size *= 2;
3295                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3296                         code = cfg->native_code + offset;
3297                         mono_jit_stats.code_reallocs++;
3298                 }
3299
3300                 if (cfg->debug_info)
3301                         mono_debug_record_line_number (cfg, ins, offset);
3302
3303                 switch (ins->opcode) {
3304                 case OP_BIGMUL:
3305                         amd64_mul_reg (code, ins->sreg2, TRUE);
3306                         break;
3307                 case OP_BIGMUL_UN:
3308                         amd64_mul_reg (code, ins->sreg2, FALSE);
3309                         break;
3310                 case OP_X86_SETEQ_MEMBASE:
3311                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3312                         break;
3313                 case OP_STOREI1_MEMBASE_IMM:
3314                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3315                         break;
3316                 case OP_STOREI2_MEMBASE_IMM:
3317                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3318                         break;
3319                 case OP_STOREI4_MEMBASE_IMM:
3320                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3321                         break;
3322                 case OP_STOREI1_MEMBASE_REG:
3323                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3324                         break;
3325                 case OP_STOREI2_MEMBASE_REG:
3326                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3327                         break;
3328                 case OP_STORE_MEMBASE_REG:
3329                 case OP_STOREI8_MEMBASE_REG:
3330                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3331                         break;
3332                 case OP_STOREI4_MEMBASE_REG:
3333                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3334                         break;
3335                 case OP_STORE_MEMBASE_IMM:
3336                 case OP_STOREI8_MEMBASE_IMM:
3337                         g_assert (amd64_is_imm32 (ins->inst_imm));
3338                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3339                         break;
3340                 case OP_LOAD_MEM:
3341                 case OP_LOADI8_MEM:
3342                         // FIXME: Decompose this earlier
3343                         if (amd64_is_imm32 (ins->inst_imm))
3344                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3345                         else {
3346                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3347                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3348                         }
3349                         break;
3350                 case OP_LOADI4_MEM:
3351                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3352                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3353                         break;
3354                 case OP_LOADU4_MEM:
3355                         // FIXME: Decompose this earlier
3356                         if (amd64_is_imm32 (ins->inst_imm))
3357                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3358                         else {
3359                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3360                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3361                         }
3362                         break;
3363                 case OP_LOADU1_MEM:
3364                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3365                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3366                         break;
3367                 case OP_LOADU2_MEM:
3368                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3369                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3370                         break;
3371                 case OP_LOAD_MEMBASE:
3372                 case OP_LOADI8_MEMBASE:
3373                         g_assert (amd64_is_imm32 (ins->inst_offset));
3374                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3375                         break;
3376                 case OP_LOADI4_MEMBASE:
3377                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3378                         break;
3379                 case OP_LOADU4_MEMBASE:
3380                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3381                         break;
3382                 case OP_LOADU1_MEMBASE:
3383                         /* The cpu zero extends the result into 64 bits */
3384                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3385                         break;
3386                 case OP_LOADI1_MEMBASE:
3387                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3388                         break;
3389                 case OP_LOADU2_MEMBASE:
3390                         /* The cpu zero extends the result into 64 bits */
3391                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3392                         break;
3393                 case OP_LOADI2_MEMBASE:
3394                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3395                         break;
3396                 case OP_AMD64_LOADI8_MEMINDEX:
3397                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3398                         break;
3399                 case OP_LCONV_TO_I1:
3400                 case OP_ICONV_TO_I1:
3401                 case OP_SEXT_I1:
3402                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3403                         break;
3404                 case OP_LCONV_TO_I2:
3405                 case OP_ICONV_TO_I2:
3406                 case OP_SEXT_I2:
3407                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3408                         break;
3409                 case OP_LCONV_TO_U1:
3410                 case OP_ICONV_TO_U1:
3411                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3412                         break;
3413                 case OP_LCONV_TO_U2:
3414                 case OP_ICONV_TO_U2:
3415                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3416                         break;
3417                 case OP_ZEXT_I4:
3418                         /* Clean out the upper word */
3419                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3420                         break;
3421                 case OP_SEXT_I4:
3422                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3423                         break;
3424                 case OP_COMPARE:
3425                 case OP_LCOMPARE:
3426                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3427                         break;
3428                 case OP_COMPARE_IMM:
3429                 case OP_LCOMPARE_IMM:
3430                         g_assert (amd64_is_imm32 (ins->inst_imm));
3431                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3432                         break;
3433                 case OP_X86_COMPARE_REG_MEMBASE:
3434                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3435                         break;
3436                 case OP_X86_TEST_NULL:
3437                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3438                         break;
3439                 case OP_AMD64_TEST_NULL:
3440                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3441                         break;
3442
3443                 case OP_X86_ADD_REG_MEMBASE:
3444                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3445                         break;
3446                 case OP_X86_SUB_REG_MEMBASE:
3447                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3448                         break;
3449                 case OP_X86_AND_REG_MEMBASE:
3450                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3451                         break;
3452                 case OP_X86_OR_REG_MEMBASE:
3453                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3454                         break;
3455                 case OP_X86_XOR_REG_MEMBASE:
3456                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3457                         break;
3458
3459                 case OP_X86_ADD_MEMBASE_IMM:
3460                         /* FIXME: Make a 64 version too */
3461                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3462                         break;
3463                 case OP_X86_SUB_MEMBASE_IMM:
3464                         g_assert (amd64_is_imm32 (ins->inst_imm));
3465                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3466                         break;
3467                 case OP_X86_AND_MEMBASE_IMM:
3468                         g_assert (amd64_is_imm32 (ins->inst_imm));
3469                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3470                         break;
3471                 case OP_X86_OR_MEMBASE_IMM:
3472                         g_assert (amd64_is_imm32 (ins->inst_imm));
3473                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3474                         break;
3475                 case OP_X86_XOR_MEMBASE_IMM:
3476                         g_assert (amd64_is_imm32 (ins->inst_imm));
3477                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3478                         break;
3479                 case OP_X86_ADD_MEMBASE_REG:
3480                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3481                         break;
3482                 case OP_X86_SUB_MEMBASE_REG:
3483                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3484                         break;
3485                 case OP_X86_AND_MEMBASE_REG:
3486                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3487                         break;
3488                 case OP_X86_OR_MEMBASE_REG:
3489                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3490                         break;
3491                 case OP_X86_XOR_MEMBASE_REG:
3492                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3493                         break;
3494                 case OP_X86_INC_MEMBASE:
3495                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3496                         break;
3497                 case OP_X86_INC_REG:
3498                         amd64_inc_reg_size (code, ins->dreg, 4);
3499                         break;
3500                 case OP_X86_DEC_MEMBASE:
3501                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3502                         break;
3503                 case OP_X86_DEC_REG:
3504                         amd64_dec_reg_size (code, ins->dreg, 4);
3505                         break;
3506                 case OP_X86_MUL_REG_MEMBASE:
3507                 case OP_X86_MUL_MEMBASE_REG:
3508                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3509                         break;
3510                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3511                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3512                         break;
3513                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3514                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3515                         break;
3516                 case OP_AMD64_COMPARE_MEMBASE_REG:
3517                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3518                         break;
3519                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3520                         g_assert (amd64_is_imm32 (ins->inst_imm));
3521                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3522                         break;
3523                 case OP_X86_COMPARE_MEMBASE8_IMM:
3524                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3525                         break;
3526                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3527                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3528                         break;
3529                 case OP_AMD64_COMPARE_REG_MEMBASE:
3530                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3531                         break;
3532
3533                 case OP_AMD64_ADD_REG_MEMBASE:
3534                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3535                         break;
3536                 case OP_AMD64_SUB_REG_MEMBASE:
3537                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3538                         break;
3539                 case OP_AMD64_AND_REG_MEMBASE:
3540                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3541                         break;
3542                 case OP_AMD64_OR_REG_MEMBASE:
3543                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3544                         break;
3545                 case OP_AMD64_XOR_REG_MEMBASE:
3546                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3547                         break;
3548
3549                 case OP_AMD64_ADD_MEMBASE_REG:
3550                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3551                         break;
3552                 case OP_AMD64_SUB_MEMBASE_REG:
3553                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3554                         break;
3555                 case OP_AMD64_AND_MEMBASE_REG:
3556                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3557                         break;
3558                 case OP_AMD64_OR_MEMBASE_REG:
3559                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3560                         break;
3561                 case OP_AMD64_XOR_MEMBASE_REG:
3562                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3563                         break;
3564
3565                 case OP_AMD64_ADD_MEMBASE_IMM:
3566                         g_assert (amd64_is_imm32 (ins->inst_imm));
3567                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3568                         break;
3569                 case OP_AMD64_SUB_MEMBASE_IMM:
3570                         g_assert (amd64_is_imm32 (ins->inst_imm));
3571                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3572                         break;
3573                 case OP_AMD64_AND_MEMBASE_IMM:
3574                         g_assert (amd64_is_imm32 (ins->inst_imm));
3575                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3576                         break;
3577                 case OP_AMD64_OR_MEMBASE_IMM:
3578                         g_assert (amd64_is_imm32 (ins->inst_imm));
3579                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3580                         break;
3581                 case OP_AMD64_XOR_MEMBASE_IMM:
3582                         g_assert (amd64_is_imm32 (ins->inst_imm));
3583                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3584                         break;
3585
3586                 case OP_BREAK:
3587                         amd64_breakpoint (code);
3588                         break;
3589                 case OP_RELAXED_NOP:
3590                         x86_prefix (code, X86_REP_PREFIX);
3591                         x86_nop (code);
3592                         break;
3593                 case OP_HARD_NOP:
3594                         x86_nop (code);
3595                         break;
3596                 case OP_NOP:
3597                 case OP_DUMMY_USE:
3598                 case OP_DUMMY_STORE:
3599                 case OP_NOT_REACHED:
3600                 case OP_NOT_NULL:
3601                         break;
3602                 case OP_SEQ_POINT: {
3603                         int i;
3604
3605                         if (cfg->compile_aot)
3606                                 NOT_IMPLEMENTED;
3607
3608                         /*
3609                          * Read from the single stepping trigger page. This will cause a
3610                          * SIGSEGV when single stepping is enabled.
3611                          * We do this _before_ the breakpoint, so single stepping after
3612                          * a breakpoint is hit will step to the next IL offset.
3613                          */
3614                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3615                                 if (((guint64)ss_trigger_page >> 32) == 0)
3616                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3617                                 else {
3618                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
3619
3620                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3621                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3622                                 }
3623                         }
3624
3625                         /*
3626                          * This is the address which is saved in seq points,
3627                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3628                          * from the address of the instruction causing the fault.
3629                          */
3630                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3631
3632                         /*
3633                          * A placeholder for a possible breakpoint inserted by
3634                          * mono_arch_set_breakpoint ().
3635                          */
3636                         for (i = 0; i < breakpoint_size; ++i)
3637                                 x86_nop (code);
3638                         break;
3639                 }
3640                 case OP_ADDCC:
3641                 case OP_LADD:
3642                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3643                         break;
3644                 case OP_ADC:
3645                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3646                         break;
3647                 case OP_ADD_IMM:
3648                 case OP_LADD_IMM:
3649                         g_assert (amd64_is_imm32 (ins->inst_imm));
3650                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3651                         break;
3652                 case OP_ADC_IMM:
3653                         g_assert (amd64_is_imm32 (ins->inst_imm));
3654                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3655                         break;
3656                 case OP_SUBCC:
3657                 case OP_LSUB:
3658                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3659                         break;
3660                 case OP_SBB:
3661                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3662                         break;
3663                 case OP_SUB_IMM:
3664                 case OP_LSUB_IMM:
3665                         g_assert (amd64_is_imm32 (ins->inst_imm));
3666                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3667                         break;
3668                 case OP_SBB_IMM:
3669                         g_assert (amd64_is_imm32 (ins->inst_imm));
3670                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3671                         break;
3672                 case OP_LAND:
3673                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3674                         break;
3675                 case OP_AND_IMM:
3676                 case OP_LAND_IMM:
3677                         g_assert (amd64_is_imm32 (ins->inst_imm));
3678                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3679                         break;
3680                 case OP_LMUL:
3681                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3682                         break;
3683                 case OP_MUL_IMM:
3684                 case OP_LMUL_IMM:
3685                 case OP_IMUL_IMM: {
3686                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3687
3688                         switch (ins->inst_imm) {
3689                         case 2:
3690                                 /* MOV r1, r2 */
3691                                 /* ADD r1, r1 */
3692                                 if (ins->dreg != ins->sreg1)
3693                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3694                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3695                                 break;
3696                         case 3:
3697                                 /* LEA r1, [r2 + r2*2] */
3698                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3699                                 break;
3700                         case 5:
3701                                 /* LEA r1, [r2 + r2*4] */
3702                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3703                                 break;
3704                         case 6:
3705                                 /* LEA r1, [r2 + r2*2] */
3706                                 /* ADD r1, r1          */
3707                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3708                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3709                                 break;
3710                         case 9:
3711                                 /* LEA r1, [r2 + r2*8] */
3712                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3713                                 break;
3714                         case 10:
3715                                 /* LEA r1, [r2 + r2*4] */
3716                                 /* ADD r1, r1          */
3717                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3718                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3719                                 break;
3720                         case 12:
3721                                 /* LEA r1, [r2 + r2*2] */
3722                                 /* SHL r1, 2           */
3723                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3724                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3725                                 break;
3726                         case 25:
3727                                 /* LEA r1, [r2 + r2*4] */
3728                                 /* LEA r1, [r1 + r1*4] */
3729                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3730                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3731                                 break;
3732                         case 100:
3733                                 /* LEA r1, [r2 + r2*4] */
3734                                 /* SHL r1, 2           */
3735                                 /* LEA r1, [r1 + r1*4] */
3736                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3737                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3738                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3739                                 break;
3740                         default:
3741                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3742                                 break;
3743                         }
3744                         break;
3745                 }
3746                 case OP_LDIV:
3747                 case OP_LREM:
3748                         /* Regalloc magic makes the div/rem cases the same */
3749                         if (ins->sreg2 == AMD64_RDX) {
3750                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3751                                 amd64_cdq (code);
3752                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3753                         } else {
3754                                 amd64_cdq (code);
3755                                 amd64_div_reg (code, ins->sreg2, TRUE);
3756                         }
3757                         break;
3758                 case OP_LDIV_UN:
3759                 case OP_LREM_UN:
3760                         if (ins->sreg2 == AMD64_RDX) {
3761                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3762                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3763                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3764                         } else {
3765                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3766                                 amd64_div_reg (code, ins->sreg2, FALSE);
3767                         }
3768                         break;
3769                 case OP_IDIV:
3770                 case OP_IREM:
3771                         if (ins->sreg2 == AMD64_RDX) {
3772                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3773                                 amd64_cdq_size (code, 4);
3774                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3775                         } else {
3776                                 amd64_cdq_size (code, 4);
3777                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3778                         }
3779                         break;
3780                 case OP_IDIV_UN:
3781                 case OP_IREM_UN:
3782                         if (ins->sreg2 == AMD64_RDX) {
3783                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3784                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3785                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3786                         } else {
3787                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3788                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3789                         }
3790                         break;
3791                 case OP_IREM_IMM: {
3792                         int power = mono_is_power_of_two (ins->inst_imm);
3793
3794                         g_assert (ins->sreg1 == X86_EAX);
3795                         g_assert (ins->dreg == X86_EAX);
3796                         g_assert (power >= 0);
3797
3798                         if (power == 0) {
3799                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3800                                 break;
3801                         }
3802
3803                         /* Based on gcc code */
3804
3805                         /* Add compensation for negative dividents */
3806                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3807                         if (power > 1)
3808                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3809                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3810                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3811                         /* Compute remainder */
3812                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3813                         /* Remove compensation */
3814                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3815                         break;
3816                 }
3817                 case OP_LMUL_OVF:
3818                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3819                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3820                         break;
3821                 case OP_LOR:
3822                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3823                         break;
3824                 case OP_OR_IMM:
3825                 case OP_LOR_IMM:
3826                         g_assert (amd64_is_imm32 (ins->inst_imm));
3827                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3828                         break;
3829                 case OP_LXOR:
3830                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3831                         break;
3832                 case OP_XOR_IMM:
3833                 case OP_LXOR_IMM:
3834                         g_assert (amd64_is_imm32 (ins->inst_imm));
3835                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3836                         break;
3837                 case OP_LSHL:
3838                         g_assert (ins->sreg2 == AMD64_RCX);
3839                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3840                         break;
3841                 case OP_LSHR:
3842                         g_assert (ins->sreg2 == AMD64_RCX);
3843                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3844                         break;
3845                 case OP_SHR_IMM:
3846                         g_assert (amd64_is_imm32 (ins->inst_imm));
3847                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3848                         break;
3849                 case OP_LSHR_IMM:
3850                         g_assert (amd64_is_imm32 (ins->inst_imm));
3851                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3852                         break;
3853                 case OP_SHR_UN_IMM:
3854                         g_assert (amd64_is_imm32 (ins->inst_imm));
3855                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3856                         break;
3857                 case OP_LSHR_UN_IMM:
3858                         g_assert (amd64_is_imm32 (ins->inst_imm));
3859                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3860                         break;
3861                 case OP_LSHR_UN:
3862                         g_assert (ins->sreg2 == AMD64_RCX);
3863                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3864                         break;
3865                 case OP_SHL_IMM:
3866                         g_assert (amd64_is_imm32 (ins->inst_imm));
3867                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3868                         break;
3869                 case OP_LSHL_IMM:
3870                         g_assert (amd64_is_imm32 (ins->inst_imm));
3871                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3872                         break;
3873
3874                 case OP_IADDCC:
3875                 case OP_IADD:
3876                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3877                         break;
3878                 case OP_IADC:
3879                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3880                         break;
3881                 case OP_IADD_IMM:
3882                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3883                         break;
3884                 case OP_IADC_IMM:
3885                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3886                         break;
3887                 case OP_ISUBCC:
3888                 case OP_ISUB:
3889                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3890                         break;
3891                 case OP_ISBB:
3892                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3893                         break;
3894                 case OP_ISUB_IMM:
3895                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3896                         break;
3897                 case OP_ISBB_IMM:
3898                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3899                         break;
3900                 case OP_IAND:
3901                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3902                         break;
3903                 case OP_IAND_IMM:
3904                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3905                         break;
3906                 case OP_IOR:
3907                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3908                         break;
3909                 case OP_IOR_IMM:
3910                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3911                         break;
3912                 case OP_IXOR:
3913                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3914                         break;
3915                 case OP_IXOR_IMM:
3916                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3917                         break;
3918                 case OP_INEG:
3919                         amd64_neg_reg_size (code, ins->sreg1, 4);
3920                         break;
3921                 case OP_INOT:
3922                         amd64_not_reg_size (code, ins->sreg1, 4);
3923                         break;
3924                 case OP_ISHL:
3925                         g_assert (ins->sreg2 == AMD64_RCX);
3926                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3927                         break;
3928                 case OP_ISHR:
3929                         g_assert (ins->sreg2 == AMD64_RCX);
3930                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3931                         break;
3932                 case OP_ISHR_IMM:
3933                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3934                         break;
3935                 case OP_ISHR_UN_IMM:
3936                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3937                         break;
3938                 case OP_ISHR_UN:
3939                         g_assert (ins->sreg2 == AMD64_RCX);
3940                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3941                         break;
3942                 case OP_ISHL_IMM:
3943                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3944                         break;
3945                 case OP_IMUL:
3946                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3947                         break;
3948                 case OP_IMUL_OVF:
3949                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3950                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3951                         break;
3952                 case OP_IMUL_OVF_UN:
3953                 case OP_LMUL_OVF_UN: {
3954                         /* the mul operation and the exception check should most likely be split */
3955                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3956                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3957                         /*g_assert (ins->sreg2 == X86_EAX);
3958                         g_assert (ins->dreg == X86_EAX);*/
3959                         if (ins->sreg2 == X86_EAX) {
3960                                 non_eax_reg = ins->sreg1;
3961                         } else if (ins->sreg1 == X86_EAX) {
3962                                 non_eax_reg = ins->sreg2;
3963                         } else {
3964                                 /* no need to save since we're going to store to it anyway */
3965                                 if (ins->dreg != X86_EAX) {
3966                                         saved_eax = TRUE;
3967                                         amd64_push_reg (code, X86_EAX);
3968                                 }
3969                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3970                                 non_eax_reg = ins->sreg2;
3971                         }
3972                         if (ins->dreg == X86_EDX) {
3973                                 if (!saved_eax) {
3974                                         saved_eax = TRUE;
3975                                         amd64_push_reg (code, X86_EAX);
3976                                 }
3977                         } else {
3978                                 saved_edx = TRUE;
3979                                 amd64_push_reg (code, X86_EDX);
3980                         }
3981                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3982                         /* save before the check since pop and mov don't change the flags */
3983                         if (ins->dreg != X86_EAX)
3984                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3985                         if (saved_edx)
3986                                 amd64_pop_reg (code, X86_EDX);
3987                         if (saved_eax)
3988                                 amd64_pop_reg (code, X86_EAX);
3989                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3990                         break;
3991                 }
3992                 case OP_ICOMPARE:
3993                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3994                         break;
3995                 case OP_ICOMPARE_IMM:
3996                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3997                         break;
3998                 case OP_IBEQ:
3999                 case OP_IBLT:
4000                 case OP_IBGT:
4001                 case OP_IBGE:
4002                 case OP_IBLE:
4003                 case OP_LBEQ:
4004                 case OP_LBLT:
4005                 case OP_LBGT:
4006                 case OP_LBGE:
4007                 case OP_LBLE:
4008                 case OP_IBNE_UN:
4009                 case OP_IBLT_UN:
4010                 case OP_IBGT_UN:
4011                 case OP_IBGE_UN:
4012                 case OP_IBLE_UN:
4013                 case OP_LBNE_UN:
4014                 case OP_LBLT_UN:
4015                 case OP_LBGT_UN:
4016                 case OP_LBGE_UN:
4017                 case OP_LBLE_UN:
4018                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4019                         break;
4020
4021                 case OP_CMOV_IEQ:
4022                 case OP_CMOV_IGE:
4023                 case OP_CMOV_IGT:
4024                 case OP_CMOV_ILE:
4025                 case OP_CMOV_ILT:
4026                 case OP_CMOV_INE_UN:
4027                 case OP_CMOV_IGE_UN:
4028                 case OP_CMOV_IGT_UN:
4029                 case OP_CMOV_ILE_UN:
4030                 case OP_CMOV_ILT_UN:
4031                 case OP_CMOV_LEQ:
4032                 case OP_CMOV_LGE:
4033                 case OP_CMOV_LGT:
4034                 case OP_CMOV_LLE:
4035                 case OP_CMOV_LLT:
4036                 case OP_CMOV_LNE_UN:
4037                 case OP_CMOV_LGE_UN:
4038                 case OP_CMOV_LGT_UN:
4039                 case OP_CMOV_LLE_UN:
4040                 case OP_CMOV_LLT_UN:
4041                         g_assert (ins->dreg == ins->sreg1);
4042                         /* This needs to operate on 64 bit values */
4043                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4044                         break;
4045
4046                 case OP_LNOT:
4047                         amd64_not_reg (code, ins->sreg1);
4048                         break;
4049                 case OP_LNEG:
4050                         amd64_neg_reg (code, ins->sreg1);
4051                         break;
4052
4053                 case OP_ICONST:
4054                 case OP_I8CONST:
4055                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4056                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4057                         else
4058                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4059                         break;
4060                 case OP_AOTCONST:
4061                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4062                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4063                         break;
4064                 case OP_JUMP_TABLE:
4065                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4066                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4067                         break;
4068                 case OP_MOVE:
4069                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4070                         break;
4071                 case OP_AMD64_SET_XMMREG_R4: {
4072                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4073                         break;
4074                 }
4075                 case OP_AMD64_SET_XMMREG_R8: {
4076                         if (ins->dreg != ins->sreg1)
4077                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4078                         break;
4079                 }
4080                 case OP_TAILCALL: {
4081                         MonoCallInst *call = (MonoCallInst*)ins;
4082                         int pos = 0, i;
4083
4084                         /* FIXME: no tracing support... */
4085                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4086                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4087
4088                         g_assert (!cfg->method->save_lmf);
4089
4090                         if (cfg->arch.omit_fp) {
4091                                 guint32 save_offset = 0;
4092                                 /* Pop callee-saved registers */
4093                                 for (i = 0; i < AMD64_NREG; ++i)
4094                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4095                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4096                                                 save_offset += 8;
4097                                         }
4098                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4099
4100                                 // FIXME:
4101                                 if (call->stack_usage)
4102                                         NOT_IMPLEMENTED;
4103                         }
4104                         else {
4105                                 for (i = 0; i < AMD64_NREG; ++i)
4106                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4107                                                 pos -= sizeof (gpointer);
4108
4109                                 /* Restore callee-saved registers */
4110                                 for (i = AMD64_NREG - 1; i > 0; --i) {
4111                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4112                                                 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4113                                                 pos += 8;
4114                                         }
4115                                 }
4116
4117                                 /* Copy arguments on the stack to our argument area */
4118                                 for (i = 0; i < call->stack_usage; i += 8) {
4119                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, 8);
4120                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, 8);
4121                                 }
4122
4123                                 if (pos)
4124                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4125
4126                                 amd64_leave (code);
4127                         }
4128
4129                         offset = code - cfg->native_code;
4130                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4131                         if (cfg->compile_aot)
4132                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4133                         else
4134                                 amd64_set_reg_template (code, AMD64_R11);
4135                         amd64_jump_reg (code, AMD64_R11);
4136                         break;
4137                 }
4138                 case OP_CHECK_THIS:
4139                         /* ensure ins->sreg1 is not NULL */
4140                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4141                         break;
4142                 case OP_ARGLIST: {
4143                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4144                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4145                         break;
4146                 }
4147                 case OP_CALL:
4148                 case OP_FCALL:
4149                 case OP_LCALL:
4150                 case OP_VCALL:
4151                 case OP_VCALL2:
4152                 case OP_VOIDCALL:
4153                         call = (MonoCallInst*)ins;
4154                         /*
4155                          * The AMD64 ABI forces callers to know about varargs.
4156                          */
4157                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4158                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4159                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4160                                 /*
4161                                  * Since the unmanaged calling convention doesn't contain a
4162                                  * 'vararg' entry, we have to treat every pinvoke call as a
4163                                  * potential vararg call.
4164                                  */
4165                                 guint32 nregs, i;
4166                                 nregs = 0;
4167                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4168                                         if (call->used_fregs & (1 << i))
4169                                                 nregs ++;
4170                                 if (!nregs)
4171                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4172                                 else
4173                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4174                         }
4175
4176                         if (ins->flags & MONO_INST_HAS_METHOD)
4177                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4178                         else
4179                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4180                         ins->flags |= MONO_INST_GC_CALLSITE;
4181                         ins->backend.pc_offset = code - cfg->native_code;
4182                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4183                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4184                         code = emit_move_return_value (cfg, ins, code);
4185                         break;
4186                 case OP_FCALL_REG:
4187                 case OP_LCALL_REG:
4188                 case OP_VCALL_REG:
4189                 case OP_VCALL2_REG:
4190                 case OP_VOIDCALL_REG:
4191                 case OP_CALL_REG:
4192                         call = (MonoCallInst*)ins;
4193
4194                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4195                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4196                                 ins->sreg1 = AMD64_R11;
4197                         }
4198
4199                         /*
4200                          * The AMD64 ABI forces callers to know about varargs.
4201                          */
4202                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4203                                 if (ins->sreg1 == AMD64_RAX) {
4204                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4205                                         ins->sreg1 = AMD64_R11;
4206                                 }
4207                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4208                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4209                                 /*
4210                                  * Since the unmanaged calling convention doesn't contain a
4211                                  * 'vararg' entry, we have to treat every pinvoke call as a
4212                                  * potential vararg call.
4213                                  */
4214                                 guint32 nregs, i;
4215                                 nregs = 0;
4216                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4217                                         if (call->used_fregs & (1 << i))
4218                                                 nregs ++;
4219                                 if (ins->sreg1 == AMD64_RAX) {
4220                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4221                                         ins->sreg1 = AMD64_R11;
4222                                 }
4223                                 if (!nregs)
4224                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4225                                 else
4226                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4227                         }
4228
4229                         amd64_call_reg (code, ins->sreg1);
4230                         ins->flags |= MONO_INST_GC_CALLSITE;
4231                         ins->backend.pc_offset = code - cfg->native_code;
4232                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4233                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4234                         code = emit_move_return_value (cfg, ins, code);
4235                         break;
4236                 case OP_FCALL_MEMBASE:
4237                 case OP_LCALL_MEMBASE:
4238                 case OP_VCALL_MEMBASE:
4239                 case OP_VCALL2_MEMBASE:
4240                 case OP_VOIDCALL_MEMBASE:
4241                 case OP_CALL_MEMBASE:
4242                         call = (MonoCallInst*)ins;
4243
4244                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4245                         ins->flags |= MONO_INST_GC_CALLSITE;
4246                         ins->backend.pc_offset = code - cfg->native_code;
4247                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4248                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4249                         code = emit_move_return_value (cfg, ins, code);
4250                         break;
4251                 case OP_DYN_CALL: {
4252                         int i;
4253                         MonoInst *var = cfg->dyn_call_var;
4254
4255                         g_assert (var->opcode == OP_REGOFFSET);
4256
4257                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4258                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4259                         /* r10 = ftn */
4260                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4261
4262                         /* Save args buffer */
4263                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4264
4265                         /* Set argument registers */
4266                         for (i = 0; i < PARAM_REGS; ++i)
4267                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4268
4269                         /* Make the call */
4270                         amd64_call_reg (code, AMD64_R10);
4271
4272                         ins->flags |= MONO_INST_GC_CALLSITE;
4273                         ins->backend.pc_offset = code - cfg->native_code;
4274
4275                         /* Save result */
4276                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4277                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4278                         break;
4279                 }
4280                 case OP_AMD64_SAVE_SP_TO_LMF:
4281                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4282                         break;
4283                 case OP_X86_PUSH:
4284                         g_assert (!cfg->arch.no_pushes);
4285                         amd64_push_reg (code, ins->sreg1);
4286                         break;
4287                 case OP_X86_PUSH_IMM:
4288                         g_assert (!cfg->arch.no_pushes);
4289                         g_assert (amd64_is_imm32 (ins->inst_imm));
4290                         amd64_push_imm (code, ins->inst_imm);
4291                         break;
4292                 case OP_X86_PUSH_MEMBASE:
4293                         g_assert (!cfg->arch.no_pushes);
4294                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4295                         break;
4296                 case OP_X86_PUSH_OBJ: {
4297                         int size = ALIGN_TO (ins->inst_imm, 8);
4298
4299                         g_assert (!cfg->arch.no_pushes);
4300
4301                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4302                         amd64_push_reg (code, AMD64_RDI);
4303                         amd64_push_reg (code, AMD64_RSI);
4304                         amd64_push_reg (code, AMD64_RCX);
4305                         if (ins->inst_offset)
4306                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4307                         else
4308                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4309                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4310                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4311                         amd64_cld (code);
4312                         amd64_prefix (code, X86_REP_PREFIX);
4313                         amd64_movsd (code);
4314                         amd64_pop_reg (code, AMD64_RCX);
4315                         amd64_pop_reg (code, AMD64_RSI);
4316                         amd64_pop_reg (code, AMD64_RDI);
4317                         break;
4318                 }
4319                 case OP_X86_LEA:
4320                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4321                         break;
4322                 case OP_X86_LEA_MEMBASE:
4323                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4324                         break;
4325                 case OP_X86_XCHG:
4326                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4327                         break;
4328                 case OP_LOCALLOC:
4329                         /* keep alignment */
4330                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4331                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4332                         code = mono_emit_stack_alloc (cfg, code, ins);
4333                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4334                         if (cfg->param_area && cfg->arch.no_pushes)
4335                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4336                         break;
4337                 case OP_LOCALLOC_IMM: {
4338                         guint32 size = ins->inst_imm;
4339                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4340
4341                         if (ins->flags & MONO_INST_INIT) {
4342                                 if (size < 64) {
4343                                         int i;
4344
4345                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4346                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4347
4348                                         for (i = 0; i < size; i += 8)
4349                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4350                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4351                                 } else {
4352                                         amd64_mov_reg_imm (code, ins->dreg, size);
4353                                         ins->sreg1 = ins->dreg;
4354
4355                                         code = mono_emit_stack_alloc (cfg, code, ins);
4356                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4357                                 }
4358                         } else {
4359                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4360                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4361                         }
4362                         if (cfg->param_area && cfg->arch.no_pushes)
4363                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4364                         break;
4365                 }
4366                 case OP_THROW: {
4367                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4368                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4369                                              (gpointer)"mono_arch_throw_exception", FALSE);
4370                         break;
4371                 }
4372                 case OP_RETHROW: {
4373                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4374                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4375                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4376                         break;
4377                 }
4378                 case OP_CALL_HANDLER:
4379                         /* Align stack */
4380                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4381                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4382                         amd64_call_imm (code, 0);
4383                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4384                         /* Restore stack alignment */
4385                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4386                         break;
4387                 case OP_START_HANDLER: {
4388                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4389                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4390
4391                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4392                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4393                                 cfg->param_area && cfg->arch.no_pushes) {
4394                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4395                         }
4396                         break;
4397                 }
4398                 case OP_ENDFINALLY: {
4399                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4400                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4401                         amd64_ret (code);
4402                         break;
4403                 }
4404                 case OP_ENDFILTER: {
4405                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4406                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4407                         /* The local allocator will put the result into RAX */
4408                         amd64_ret (code);
4409                         break;
4410                 }
4411
4412                 case OP_LABEL:
4413                         ins->inst_c0 = code - cfg->native_code;
4414                         break;
4415                 case OP_BR:
4416                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4417                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4418                         //break;
4419                                 if (ins->inst_target_bb->native_offset) {
4420                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4421                                 } else {
4422                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4423                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4424                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4425                                                 x86_jump8 (code, 0);
4426                                         else
4427                                                 x86_jump32 (code, 0);
4428                         }
4429                         break;
4430                 case OP_BR_REG:
4431                         amd64_jump_reg (code, ins->sreg1);
4432                         break;
4433                 case OP_CEQ:
4434                 case OP_LCEQ:
4435                 case OP_ICEQ:
4436                 case OP_CLT:
4437                 case OP_LCLT:
4438                 case OP_ICLT:
4439                 case OP_CGT:
4440                 case OP_ICGT:
4441                 case OP_LCGT:
4442                 case OP_CLT_UN:
4443                 case OP_LCLT_UN:
4444                 case OP_ICLT_UN:
4445                 case OP_CGT_UN:
4446                 case OP_LCGT_UN:
4447                 case OP_ICGT_UN:
4448                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4449                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4450                         break;
4451                 case OP_COND_EXC_EQ:
4452                 case OP_COND_EXC_NE_UN:
4453                 case OP_COND_EXC_LT:
4454                 case OP_COND_EXC_LT_UN:
4455                 case OP_COND_EXC_GT:
4456                 case OP_COND_EXC_GT_UN:
4457                 case OP_COND_EXC_GE:
4458                 case OP_COND_EXC_GE_UN:
4459                 case OP_COND_EXC_LE:
4460                 case OP_COND_EXC_LE_UN:
4461                 case OP_COND_EXC_IEQ:
4462                 case OP_COND_EXC_INE_UN:
4463                 case OP_COND_EXC_ILT:
4464                 case OP_COND_EXC_ILT_UN:
4465                 case OP_COND_EXC_IGT:
4466                 case OP_COND_EXC_IGT_UN:
4467                 case OP_COND_EXC_IGE:
4468                 case OP_COND_EXC_IGE_UN:
4469                 case OP_COND_EXC_ILE:
4470                 case OP_COND_EXC_ILE_UN:
4471                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4472                         break;
4473                 case OP_COND_EXC_OV:
4474                 case OP_COND_EXC_NO:
4475                 case OP_COND_EXC_C:
4476                 case OP_COND_EXC_NC:
4477                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4478                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4479                         break;
4480                 case OP_COND_EXC_IOV:
4481                 case OP_COND_EXC_INO:
4482                 case OP_COND_EXC_IC:
4483                 case OP_COND_EXC_INC:
4484                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4485                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4486                         break;
4487
4488                 /* floating point opcodes */
4489                 case OP_R8CONST: {
4490                         double d = *(double *)ins->inst_p0;
4491
4492                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4493                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4494                         }
4495                         else {
4496                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4497                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4498                         }
4499                         break;
4500                 }
4501                 case OP_R4CONST: {
4502                         float f = *(float *)ins->inst_p0;
4503
4504                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4505                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4506                         }
4507                         else {
4508                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4509                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4510                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4511                         }
4512                         break;
4513                 }
4514                 case OP_STORER8_MEMBASE_REG:
4515                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4516                         break;
4517                 case OP_LOADR8_MEMBASE:
4518                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4519                         break;
4520                 case OP_STORER4_MEMBASE_REG:
4521                         /* This requires a double->single conversion */
4522                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4523                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4524                         break;
4525                 case OP_LOADR4_MEMBASE:
4526                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4527                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4528                         break;
4529                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4530                 case OP_ICONV_TO_R8:
4531                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4532                         break;
4533                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4534                 case OP_LCONV_TO_R8:
4535                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4536                         break;
4537                 case OP_FCONV_TO_R4:
4538                         /* FIXME: nothing to do ?? */
4539                         break;
4540                 case OP_FCONV_TO_I1:
4541                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4542                         break;
4543                 case OP_FCONV_TO_U1:
4544                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4545                         break;
4546                 case OP_FCONV_TO_I2:
4547                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4548                         break;
4549                 case OP_FCONV_TO_U2:
4550                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4551                         break;
4552                 case OP_FCONV_TO_U4:
4553                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4554                         break;
4555                 case OP_FCONV_TO_I4:
4556                 case OP_FCONV_TO_I:
4557                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4558                         break;
4559                 case OP_FCONV_TO_I8:
4560                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4561                         break;
4562                 case OP_LCONV_TO_R_UN: {
4563                         guint8 *br [2];
4564
4565                         /* Based on gcc code */
4566                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4567                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4568
4569                         /* Positive case */
4570                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4571                         br [1] = code; x86_jump8 (code, 0);
4572                         amd64_patch (br [0], code);
4573
4574                         /* Negative case */
4575                         /* Save to the red zone */
4576                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4577                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4578                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4579                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4580                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4581                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4582                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4583                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4584                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4585                         /* Restore */
4586                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4587                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4588                         amd64_patch (br [1], code);
4589                         break;
4590                 }
4591                 case OP_LCONV_TO_OVF_U4:
4592                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4593                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4594                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4595                         break;
4596                 case OP_LCONV_TO_OVF_I4_UN:
4597                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4598                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4599                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4600                         break;
4601                 case OP_FMOVE:
4602                         if (ins->dreg != ins->sreg1)
4603                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4604                         break;
4605                 case OP_FADD:
4606                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4607                         break;
4608                 case OP_FSUB:
4609                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4610                         break;
4611                 case OP_FMUL:
4612                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4613                         break;
4614                 case OP_FDIV:
4615                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4616                         break;
4617                 case OP_FNEG: {
4618                         static double r8_0 = -0.0;
4619
4620                         g_assert (ins->sreg1 == ins->dreg);
4621
4622                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4623                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4624                         break;
4625                 }
4626                 case OP_SIN:
4627                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4628                         break;
4629                 case OP_COS:
4630                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4631                         break;
4632                 case OP_ABS: {
4633                         static guint64 d = 0x7fffffffffffffffUL;
4634
4635                         g_assert (ins->sreg1 == ins->dreg);
4636
4637                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4638                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4639                         break;
4640                 }
4641                 case OP_SQRT:
4642                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4643                         break;
4644                 case OP_IMIN:
4645                         g_assert (cfg->opt & MONO_OPT_CMOV);
4646                         g_assert (ins->dreg == ins->sreg1);
4647                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4648                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4649                         break;
4650                 case OP_IMIN_UN:
4651                         g_assert (cfg->opt & MONO_OPT_CMOV);
4652                         g_assert (ins->dreg == ins->sreg1);
4653                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4654                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4655                         break;
4656                 case OP_IMAX:
4657                         g_assert (cfg->opt & MONO_OPT_CMOV);
4658                         g_assert (ins->dreg == ins->sreg1);
4659                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4660                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4661                         break;
4662                 case OP_IMAX_UN:
4663                         g_assert (cfg->opt & MONO_OPT_CMOV);
4664                         g_assert (ins->dreg == ins->sreg1);
4665                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4666                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4667                         break;
4668                 case OP_LMIN:
4669                         g_assert (cfg->opt & MONO_OPT_CMOV);
4670                         g_assert (ins->dreg == ins->sreg1);
4671                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4672                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4673                         break;
4674                 case OP_LMIN_UN:
4675                         g_assert (cfg->opt & MONO_OPT_CMOV);
4676                         g_assert (ins->dreg == ins->sreg1);
4677                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4678                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4679                         break;
4680                 case OP_LMAX:
4681                         g_assert (cfg->opt & MONO_OPT_CMOV);
4682                         g_assert (ins->dreg == ins->sreg1);
4683                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4684                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4685                         break;
4686                 case OP_LMAX_UN:
4687                         g_assert (cfg->opt & MONO_OPT_CMOV);
4688                         g_assert (ins->dreg == ins->sreg1);
4689                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4690                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4691                         break;
4692                 case OP_X86_FPOP:
4693                         break;
4694                 case OP_FCOMPARE:
4695                         /*
4696                          * The two arguments are swapped because the fbranch instructions
4697                          * depend on this for the non-sse case to work.
4698                          */
4699                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4700                         break;
4701                 case OP_FCEQ: {
4702                         /* zeroing the register at the start results in
4703                          * shorter and faster code (we can also remove the widening op)
4704                          */
4705                         guchar *unordered_check;
4706                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4707                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4708                         unordered_check = code;
4709                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4710                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4711                         amd64_patch (unordered_check, code);
4712                         break;
4713                 }
4714                 case OP_FCLT:
4715                 case OP_FCLT_UN:
4716                         /* zeroing the register at the start results in
4717                          * shorter and faster code (we can also remove the widening op)
4718                          */
4719                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4720                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4721                         if (ins->opcode == OP_FCLT_UN) {
4722                                 guchar *unordered_check = code;
4723                                 guchar *jump_to_end;
4724                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4725                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4726                                 jump_to_end = code;
4727                                 x86_jump8 (code, 0);
4728                                 amd64_patch (unordered_check, code);
4729                                 amd64_inc_reg (code, ins->dreg);
4730                                 amd64_patch (jump_to_end, code);
4731                         } else {
4732                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4733                         }
4734                         break;
4735                 case OP_FCGT:
4736                 case OP_FCGT_UN: {
4737                         /* zeroing the register at the start results in
4738                          * shorter and faster code (we can also remove the widening op)
4739                          */
4740                         guchar *unordered_check;
4741                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4742                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4743                         if (ins->opcode == OP_FCGT) {
4744                                 unordered_check = code;
4745                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4746                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4747                                 amd64_patch (unordered_check, code);
4748                         } else {
4749                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4750                         }
4751                         break;
4752                 }
4753                 case OP_FCLT_MEMBASE:
4754                 case OP_FCGT_MEMBASE:
4755                 case OP_FCLT_UN_MEMBASE:
4756                 case OP_FCGT_UN_MEMBASE:
4757                 case OP_FCEQ_MEMBASE: {
4758                         guchar *unordered_check, *jump_to_end;
4759                         int x86_cond;
4760
4761                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4762                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4763
4764                         switch (ins->opcode) {
4765                         case OP_FCEQ_MEMBASE:
4766                                 x86_cond = X86_CC_EQ;
4767                                 break;
4768                         case OP_FCLT_MEMBASE:
4769                         case OP_FCLT_UN_MEMBASE:
4770                                 x86_cond = X86_CC_LT;
4771                                 break;
4772                         case OP_FCGT_MEMBASE:
4773                         case OP_FCGT_UN_MEMBASE:
4774                                 x86_cond = X86_CC_GT;
4775                                 break;
4776                         default:
4777                                 g_assert_not_reached ();
4778                         }
4779
4780                         unordered_check = code;
4781                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4782                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4783
4784                         switch (ins->opcode) {
4785                         case OP_FCEQ_MEMBASE:
4786                         case OP_FCLT_MEMBASE:
4787                         case OP_FCGT_MEMBASE:
4788                                 amd64_patch (unordered_check, code);
4789                                 break;
4790                         case OP_FCLT_UN_MEMBASE:
4791                         case OP_FCGT_UN_MEMBASE:
4792                                 jump_to_end = code;
4793                                 x86_jump8 (code, 0);
4794                                 amd64_patch (unordered_check, code);
4795                                 amd64_inc_reg (code, ins->dreg);
4796                                 amd64_patch (jump_to_end, code);
4797                                 break;
4798                         default:
4799                                 break;
4800                         }
4801                         break;
4802                 }
4803                 case OP_FBEQ: {
4804                         guchar *jump = code;
4805                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4806                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4807                         amd64_patch (jump, code);
4808                         break;
4809                 }
4810                 case OP_FBNE_UN:
4811                         /* Branch if C013 != 100 */
4812                         /* branch if !ZF or (PF|CF) */
4813                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4814                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4815                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4816                         break;
4817                 case OP_FBLT:
4818                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4819                         break;
4820                 case OP_FBLT_UN:
4821                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4822                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4823                         break;
4824                 case OP_FBGT:
4825                 case OP_FBGT_UN:
4826                         if (ins->opcode == OP_FBGT) {
4827                                 guchar *br1;
4828
4829                                 /* skip branch if C1=1 */
4830                                 br1 = code;
4831                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4832                                 /* branch if (C0 | C3) = 1 */
4833                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4834                                 amd64_patch (br1, code);
4835                                 break;
4836                         } else {
4837                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4838                         }
4839                         break;
4840                 case OP_FBGE: {
4841                         /* Branch if C013 == 100 or 001 */
4842                         guchar *br1;
4843
4844                         /* skip branch if C1=1 */
4845                         br1 = code;
4846                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4847                         /* branch if (C0 | C3) = 1 */
4848                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4849                         amd64_patch (br1, code);
4850                         break;
4851                 }
4852                 case OP_FBGE_UN:
4853                         /* Branch if C013 == 000 */
4854                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4855                         break;
4856                 case OP_FBLE: {
4857                         /* Branch if C013=000 or 100 */
4858                         guchar *br1;
4859
4860                         /* skip branch if C1=1 */
4861                         br1 = code;
4862                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4863                         /* branch if C0=0 */
4864                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4865                         amd64_patch (br1, code);
4866                         break;
4867                 }
4868                 case OP_FBLE_UN:
4869                         /* Branch if C013 != 001 */
4870                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4871                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4872                         break;
4873                 case OP_CKFINITE:
4874                         /* Transfer value to the fp stack */
4875                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4876                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4877                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4878
4879                         amd64_push_reg (code, AMD64_RAX);
4880                         amd64_fxam (code);
4881                         amd64_fnstsw (code);
4882                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4883                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4884                         amd64_pop_reg (code, AMD64_RAX);
4885                         amd64_fstp (code, 0);
4886                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4887                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4888                         break;
4889                 case OP_TLS_GET: {
4890                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4891                         break;
4892                 }
4893                 case OP_MEMORY_BARRIER: {
4894                         /* http://blogs.sun.com/dave/resource/NHM-Pipeline-Blog-V2.txt */
4895                         x86_prefix (code, X86_LOCK_PREFIX);
4896                         amd64_alu_membase_imm (code, X86_ADD, AMD64_RSP, 0, 0);
4897                         break;
4898                 }
4899                 case OP_ATOMIC_ADD_I4:
4900                 case OP_ATOMIC_ADD_I8: {
4901                         int dreg = ins->dreg;
4902                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4903
4904                         if (dreg == ins->inst_basereg)
4905                                 dreg = AMD64_R11;
4906
4907                         if (dreg != ins->sreg2)
4908                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4909
4910                         x86_prefix (code, X86_LOCK_PREFIX);
4911                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4912
4913                         if (dreg != ins->dreg)
4914                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4915
4916                         break;
4917                 }
4918                 case OP_ATOMIC_ADD_NEW_I4:
4919                 case OP_ATOMIC_ADD_NEW_I8: {
4920                         int dreg = ins->dreg;
4921                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4922
4923                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4924                                 dreg = AMD64_R11;
4925
4926                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4927                         amd64_prefix (code, X86_LOCK_PREFIX);
4928                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4929                         /* dreg contains the old value, add with sreg2 value */
4930                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4931
4932                         if (ins->dreg != dreg)
4933                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4934
4935                         break;
4936                 }
4937                 case OP_ATOMIC_EXCHANGE_I4:
4938                 case OP_ATOMIC_EXCHANGE_I8: {
4939                         guchar *br[2];
4940                         int sreg2 = ins->sreg2;
4941                         int breg = ins->inst_basereg;
4942                         guint32 size;
4943                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4944
4945                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4946                                 size = 8;
4947                         else
4948                                 size = 4;
4949
4950                         /*
4951                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4952                          * an explanation of how this works.
4953                          */
4954
4955                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4956                          * hack to overcome limits in x86 reg allocator
4957                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4958                          */
4959                         g_assert (ins->dreg == AMD64_RAX);
4960
4961                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4962                                 /* Highly unlikely, but possible */
4963                                 need_push = TRUE;
4964
4965                         /* The pushes invalidate rsp */
4966                         if ((breg == AMD64_RAX) || need_push) {
4967                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4968                                 breg = AMD64_R11;
4969                         }
4970
4971                         /* We need the EAX reg for the comparand */
4972                         if (ins->sreg2 == AMD64_RAX) {
4973                                 if (breg != AMD64_R11) {
4974                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4975                                         sreg2 = AMD64_R11;
4976                                 } else {
4977                                         g_assert (need_push);
4978                                         amd64_push_reg (code, AMD64_RDX);
4979                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4980                                         sreg2 = AMD64_RDX;
4981                                         rdx_pushed = TRUE;
4982                                 }
4983                         }
4984
4985                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4986
4987                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4988                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4989                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4990                         amd64_patch (br [1], br [0]);
4991
4992                         if (rdx_pushed)
4993                                 amd64_pop_reg (code, AMD64_RDX);
4994
4995                         break;
4996                 }
4997                 case OP_ATOMIC_CAS_I4:
4998                 case OP_ATOMIC_CAS_I8: {
4999                         guint32 size;
5000
5001                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5002                                 size = 8;
5003                         else
5004                                 size = 4;
5005
5006                         /*
5007                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5008                          * an explanation of how this works.
5009                          */
5010                         g_assert (ins->sreg3 == AMD64_RAX);
5011                         g_assert (ins->sreg1 != AMD64_RAX);
5012                         g_assert (ins->sreg1 != ins->sreg2);
5013
5014                         amd64_prefix (code, X86_LOCK_PREFIX);
5015                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5016
5017                         if (ins->dreg != AMD64_RAX)
5018                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5019                         break;
5020                 }
5021                 case OP_CARD_TABLE_WBARRIER: {
5022                         int ptr = ins->sreg1;
5023                         int value = ins->sreg2;
5024                         guchar *br;
5025                         int nursery_shift, card_table_shift;
5026                         gpointer card_table_mask;
5027                         size_t nursery_size;
5028
5029                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5030                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5031
5032                         /*If either point to the stack we can simply avoid the WB. This happens due to
5033                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5034                          */
5035                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5036                                 continue;
5037
5038                         /*
5039                          * We need one register we can clobber, we choose EDX and make sreg1
5040                          * fixed EAX to work around limitations in the local register allocator.
5041                          * sreg2 might get allocated to EDX, but that is not a problem since
5042                          * we use it before clobbering EDX.
5043                          */
5044                         g_assert (ins->sreg1 == AMD64_RAX);
5045
5046                         /*
5047                          * This is the code we produce:
5048                          *
5049                          *   edx = value
5050                          *   edx >>= nursery_shift
5051                          *   cmp edx, (nursery_start >> nursery_shift)
5052                          *   jne done
5053                          *   edx = ptr
5054                          *   edx >>= card_table_shift
5055                          *   edx += cardtable
5056                          *   [edx] = 1
5057                          * done:
5058                          */
5059
5060                         if (value != AMD64_RDX)
5061                                 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5062                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5063                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, nursery_start >> nursery_shift);
5064                         br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5065                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5066                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5067                         if (card_table_mask)
5068                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5069
5070                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5071                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5072
5073                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5074                         x86_patch (br, code);
5075                         break;
5076                 }
5077 #ifdef MONO_ARCH_SIMD_INTRINSICS
5078                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5079                 case OP_ADDPS:
5080                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5081                         break;
5082                 case OP_DIVPS:
5083                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5084                         break;
5085                 case OP_MULPS:
5086                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5087                         break;
5088                 case OP_SUBPS:
5089                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5090                         break;
5091                 case OP_MAXPS:
5092                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5093                         break;
5094                 case OP_MINPS:
5095                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5096                         break;
5097                 case OP_COMPPS:
5098                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5099                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5100                         break;
5101                 case OP_ANDPS:
5102                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5103                         break;
5104                 case OP_ANDNPS:
5105                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5106                         break;
5107                 case OP_ORPS:
5108                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5109                         break;
5110                 case OP_XORPS:
5111                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5112                         break;
5113                 case OP_SQRTPS:
5114                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5115                         break;
5116                 case OP_RSQRTPS:
5117                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5118                         break;
5119                 case OP_RCPPS:
5120                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5121                         break;
5122                 case OP_ADDSUBPS:
5123                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5124                         break;
5125                 case OP_HADDPS:
5126                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5127                         break;
5128                 case OP_HSUBPS:
5129                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5130                         break;
5131                 case OP_DUPPS_HIGH:
5132                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5133                         break;
5134                 case OP_DUPPS_LOW:
5135                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5136                         break;
5137
5138                 case OP_PSHUFLEW_HIGH:
5139                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5140                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5141                         break;
5142                 case OP_PSHUFLEW_LOW:
5143                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5144                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5145                         break;
5146                 case OP_PSHUFLED:
5147                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5148                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5149                         break;
5150
5151                 case OP_ADDPD:
5152                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5153                         break;
5154                 case OP_DIVPD:
5155                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5156                         break;
5157                 case OP_MULPD:
5158                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5159                         break;
5160                 case OP_SUBPD:
5161                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5162                         break;
5163                 case OP_MAXPD:
5164                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5165                         break;
5166                 case OP_MINPD:
5167                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5168                         break;
5169                 case OP_COMPPD:
5170                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5171                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5172                         break;
5173                 case OP_ANDPD:
5174                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5175                         break;
5176                 case OP_ANDNPD:
5177                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5178                         break;
5179                 case OP_ORPD:
5180                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5181                         break;
5182                 case OP_XORPD:
5183                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5184                         break;
5185                 case OP_SQRTPD:
5186                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5187                         break;
5188                 case OP_ADDSUBPD:
5189                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5190                         break;
5191                 case OP_HADDPD:
5192                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5193                         break;
5194                 case OP_HSUBPD:
5195                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5196                         break;
5197                 case OP_DUPPD:
5198                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5199                         break;
5200
5201                 case OP_EXTRACT_MASK:
5202                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5203                         break;
5204
5205                 case OP_PAND:
5206                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5207                         break;
5208                 case OP_POR:
5209                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5210                         break;
5211                 case OP_PXOR:
5212                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5213                         break;
5214
5215                 case OP_PADDB:
5216                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5217                         break;
5218                 case OP_PADDW:
5219                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5220                         break;
5221                 case OP_PADDD:
5222                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5223                         break;
5224                 case OP_PADDQ:
5225                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5226                         break;
5227
5228                 case OP_PSUBB:
5229                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5230                         break;
5231                 case OP_PSUBW:
5232                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5233                         break;
5234                 case OP_PSUBD:
5235                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5236                         break;
5237                 case OP_PSUBQ:
5238                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5239                         break;
5240
5241                 case OP_PMAXB_UN:
5242                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5243                         break;
5244                 case OP_PMAXW_UN:
5245                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5246                         break;
5247                 case OP_PMAXD_UN:
5248                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5249                         break;
5250
5251                 case OP_PMAXB:
5252                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5253                         break;
5254                 case OP_PMAXW:
5255                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5256                         break;
5257                 case OP_PMAXD:
5258                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5259                         break;
5260
5261                 case OP_PAVGB_UN:
5262                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5263                         break;
5264                 case OP_PAVGW_UN:
5265                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5266                         break;
5267
5268                 case OP_PMINB_UN:
5269                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5270                         break;
5271                 case OP_PMINW_UN:
5272                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5273                         break;
5274                 case OP_PMIND_UN:
5275                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5276                         break;
5277
5278                 case OP_PMINB:
5279                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5280                         break;
5281                 case OP_PMINW:
5282                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5283                         break;
5284                 case OP_PMIND:
5285                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5286                         break;
5287
5288                 case OP_PCMPEQB:
5289                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5290                         break;
5291                 case OP_PCMPEQW:
5292                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5293                         break;
5294                 case OP_PCMPEQD:
5295                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5296                         break;
5297                 case OP_PCMPEQQ:
5298                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5299                         break;
5300
5301                 case OP_PCMPGTB:
5302                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5303                         break;
5304                 case OP_PCMPGTW:
5305                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5306                         break;
5307                 case OP_PCMPGTD:
5308                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5309                         break;
5310                 case OP_PCMPGTQ:
5311                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5312                         break;
5313
5314                 case OP_PSUM_ABS_DIFF:
5315                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5316                         break;
5317
5318                 case OP_UNPACK_LOWB:
5319                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5320                         break;
5321                 case OP_UNPACK_LOWW:
5322                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5323                         break;
5324                 case OP_UNPACK_LOWD:
5325                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5326                         break;
5327                 case OP_UNPACK_LOWQ:
5328                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5329                         break;
5330                 case OP_UNPACK_LOWPS:
5331                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5332                         break;
5333                 case OP_UNPACK_LOWPD:
5334                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5335                         break;
5336
5337                 case OP_UNPACK_HIGHB:
5338                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5339                         break;
5340                 case OP_UNPACK_HIGHW:
5341                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5342                         break;
5343                 case OP_UNPACK_HIGHD:
5344                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5345                         break;
5346                 case OP_UNPACK_HIGHQ:
5347                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5348                         break;
5349                 case OP_UNPACK_HIGHPS:
5350                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5351                         break;
5352                 case OP_UNPACK_HIGHPD:
5353                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5354                         break;
5355
5356                 case OP_PACKW:
5357                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5358                         break;
5359                 case OP_PACKD:
5360                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5361                         break;
5362                 case OP_PACKW_UN:
5363                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5364                         break;
5365                 case OP_PACKD_UN:
5366                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5367                         break;
5368
5369                 case OP_PADDB_SAT_UN:
5370                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5371                         break;
5372                 case OP_PSUBB_SAT_UN:
5373                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5374                         break;
5375                 case OP_PADDW_SAT_UN:
5376                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5377                         break;
5378                 case OP_PSUBW_SAT_UN:
5379                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5380                         break;
5381
5382                 case OP_PADDB_SAT:
5383                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5384                         break;
5385                 case OP_PSUBB_SAT:
5386                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5387                         break;
5388                 case OP_PADDW_SAT:
5389                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5390                         break;
5391                 case OP_PSUBW_SAT:
5392                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5393                         break;
5394
5395                 case OP_PMULW:
5396                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5397                         break;
5398                 case OP_PMULD:
5399                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5400                         break;
5401                 case OP_PMULQ:
5402                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5403                         break;
5404                 case OP_PMULW_HIGH_UN:
5405                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5406                         break;
5407                 case OP_PMULW_HIGH:
5408                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5409                         break;
5410
5411                 case OP_PSHRW:
5412                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5413                         break;
5414                 case OP_PSHRW_REG:
5415                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5416                         break;
5417
5418                 case OP_PSARW:
5419                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5420                         break;
5421                 case OP_PSARW_REG:
5422                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5423                         break;
5424
5425                 case OP_PSHLW:
5426                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5427                         break;
5428                 case OP_PSHLW_REG:
5429                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5430                         break;
5431
5432                 case OP_PSHRD:
5433                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5434                         break;
5435                 case OP_PSHRD_REG:
5436                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5437                         break;
5438
5439                 case OP_PSARD:
5440                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5441                         break;
5442                 case OP_PSARD_REG:
5443                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5444                         break;
5445
5446                 case OP_PSHLD:
5447                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5448                         break;
5449                 case OP_PSHLD_REG:
5450                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5451                         break;
5452
5453                 case OP_PSHRQ:
5454                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5455                         break;
5456                 case OP_PSHRQ_REG:
5457                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5458                         break;
5459
5460                 /*TODO: This is appart of the sse spec but not added
5461                 case OP_PSARQ:
5462                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5463                         break;
5464                 case OP_PSARQ_REG:
5465                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5466                         break;
5467                 */
5468
5469                 case OP_PSHLQ:
5470                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5471                         break;
5472                 case OP_PSHLQ_REG:
5473                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5474                         break;
5475
5476                 case OP_ICONV_TO_X:
5477                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5478                         break;
5479                 case OP_EXTRACT_I4:
5480                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5481                         break;
5482                 case OP_EXTRACT_I8:
5483                         if (ins->inst_c0) {
5484                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5485                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5486                         } else {
5487                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5488                         }
5489                         break;
5490                 case OP_EXTRACT_I1:
5491                 case OP_EXTRACT_U1:
5492                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5493                         if (ins->inst_c0)
5494                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5495                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5496                         break;
5497                 case OP_EXTRACT_I2:
5498                 case OP_EXTRACT_U2:
5499                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5500                         if (ins->inst_c0)
5501                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5502                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5503                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5504                         break;
5505                 case OP_EXTRACT_R8:
5506                         if (ins->inst_c0)
5507                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5508                         else
5509                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5510                         break;
5511                 case OP_INSERT_I2:
5512                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5513                         break;
5514                 case OP_EXTRACTX_U2:
5515                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5516                         break;
5517                 case OP_INSERTX_U1_SLOW:
5518                         /*sreg1 is the extracted ireg (scratch)
5519                         /sreg2 is the to be inserted ireg (scratch)
5520                         /dreg is the xreg to receive the value*/
5521
5522                         /*clear the bits from the extracted word*/
5523                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5524                         /*shift the value to insert if needed*/
5525                         if (ins->inst_c0 & 1)
5526                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5527                         /*join them together*/
5528                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5529                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5530                         break;
5531                 case OP_INSERTX_I4_SLOW:
5532                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5533                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5534                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5535                         break;
5536                 case OP_INSERTX_I8_SLOW:
5537                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5538                         if (ins->inst_c0)
5539                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5540                         else
5541                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5542                         break;
5543
5544                 case OP_INSERTX_R4_SLOW:
5545                         switch (ins->inst_c0) {
5546                         case 0:
5547                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5548                                 break;
5549                         case 1:
5550                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5551                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5552                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5553                                 break;
5554                         case 2:
5555                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5556                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5557                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5558                                 break;
5559                         case 3:
5560                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5561                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5562                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5563                                 break;
5564                         }
5565                         break;
5566                 case OP_INSERTX_R8_SLOW:
5567                         if (ins->inst_c0)
5568                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5569                         else
5570                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5571                         break;
5572                 case OP_STOREX_MEMBASE_REG:
5573                 case OP_STOREX_MEMBASE:
5574                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5575                         break;
5576                 case OP_LOADX_MEMBASE:
5577                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5578                         break;
5579                 case OP_LOADX_ALIGNED_MEMBASE:
5580                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5581                         break;
5582                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5583                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5584                         break;
5585                 case OP_STOREX_NTA_MEMBASE_REG:
5586                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5587                         break;
5588                 case OP_PREFETCH_MEMBASE:
5589                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5590                         break;
5591
5592                 case OP_XMOVE:
5593                         /*FIXME the peephole pass should have killed this*/
5594                         if (ins->dreg != ins->sreg1)
5595                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5596                         break;
5597                 case OP_XZERO:
5598                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5599                         break;
5600                 case OP_ICONV_TO_R8_RAW:
5601                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5602                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5603                         break;
5604
5605                 case OP_FCONV_TO_R8_X:
5606                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5607                         break;
5608
5609                 case OP_XCONV_R8_TO_I4:
5610                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5611                         switch (ins->backend.source_opcode) {
5612                         case OP_FCONV_TO_I1:
5613                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5614                                 break;
5615                         case OP_FCONV_TO_U1:
5616                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5617                                 break;
5618                         case OP_FCONV_TO_I2:
5619                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5620                                 break;
5621                         case OP_FCONV_TO_U2:
5622                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5623                                 break;
5624                         }
5625                         break;
5626
5627                 case OP_EXPAND_I2:
5628                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5629                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5630                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5631                         break;
5632                 case OP_EXPAND_I4:
5633                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5634                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5635                         break;
5636                 case OP_EXPAND_I8:
5637                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5638                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5639                         break;
5640                 case OP_EXPAND_R4:
5641                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5642                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5643                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5644                         break;
5645                 case OP_EXPAND_R8:
5646                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5647                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5648                         break;
5649 #endif
5650                 case OP_LIVERANGE_START: {
5651                         if (cfg->verbose_level > 1)
5652                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5653                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5654                         break;
5655                 }
5656                 case OP_LIVERANGE_END: {
5657                         if (cfg->verbose_level > 1)
5658                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5659                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5660                         break;
5661                 }
5662                 case OP_GC_LIVENESS_DEF:
5663                 case OP_GC_LIVENESS_USE:
5664                         ins->backend.pc_offset = code - cfg->native_code;
5665                         break;
5666                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
5667                         ins->backend.pc_offset = code - cfg->native_code;
5668                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
5669                         break;
5670                 default:
5671                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5672                         g_assert_not_reached ();
5673                 }
5674
5675                 if ((code - cfg->native_code - offset) > max_len) {
5676                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5677                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5678                         g_assert_not_reached ();
5679                 }
5680
5681                 last_ins = ins;
5682                 last_offset = offset;
5683         }
5684
5685         cfg->code_len = code - cfg->native_code;
5686 }
5687
5688 #endif /* DISABLE_JIT */
5689
5690 void
5691 mono_arch_register_lowlevel_calls (void)
5692 {
5693         /* The signature doesn't matter */
5694         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5695 }
5696
5697 void
5698 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5699 {
5700         MonoJumpInfo *patch_info;
5701         gboolean compile_aot = !run_cctors;
5702
5703         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5704                 unsigned char *ip = patch_info->ip.i + code;
5705                 unsigned char *target;
5706
5707                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5708
5709                 if (compile_aot) {
5710                         switch (patch_info->type) {
5711                         case MONO_PATCH_INFO_BB:
5712                         case MONO_PATCH_INFO_LABEL:
5713                                 break;
5714                         default:
5715                                 /* No need to patch these */
5716                                 continue;
5717                         }
5718                 }
5719
5720                 switch (patch_info->type) {
5721                 case MONO_PATCH_INFO_NONE:
5722                         continue;
5723                 case MONO_PATCH_INFO_METHOD_REL:
5724                 case MONO_PATCH_INFO_R8:
5725                 case MONO_PATCH_INFO_R4:
5726                         g_assert_not_reached ();
5727                         continue;
5728                 case MONO_PATCH_INFO_BB:
5729                         break;
5730                 default:
5731                         break;
5732                 }
5733
5734                 /*
5735                  * Debug code to help track down problems where the target of a near call is
5736                  * is not valid.
5737                  */
5738                 if (amd64_is_near_call (ip)) {
5739                         gint64 disp = (guint8*)target - (guint8*)ip;
5740
5741                         if (!amd64_is_imm32 (disp)) {
5742                                 printf ("TYPE: %d\n", patch_info->type);
5743                                 switch (patch_info->type) {
5744                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5745                                         printf ("V: %s\n", patch_info->data.name);
5746                                         break;
5747                                 case MONO_PATCH_INFO_METHOD_JUMP:
5748                                 case MONO_PATCH_INFO_METHOD:
5749                                         printf ("V: %s\n", patch_info->data.method->name);
5750                                         break;
5751                                 default:
5752                                         break;
5753                                 }
5754                         }
5755                 }
5756
5757                 amd64_patch (ip, (gpointer)target);
5758         }
5759 }
5760
5761 #ifndef DISABLE_JIT
5762
5763 static int
5764 get_max_epilog_size (MonoCompile *cfg)
5765 {
5766         int max_epilog_size = 16;
5767
5768         if (cfg->method->save_lmf)
5769                 max_epilog_size += 256;
5770
5771         if (mono_jit_trace_calls != NULL)
5772                 max_epilog_size += 50;
5773
5774         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5775                 max_epilog_size += 50;
5776
5777         max_epilog_size += (AMD64_NREG * 2);
5778
5779         return max_epilog_size;
5780 }
5781
5782 /*
5783  * This macro is used for testing whenever the unwinder works correctly at every point
5784  * where an async exception can happen.
5785  */
5786 /* This will generate a SIGSEGV at the given point in the code */
5787 #define async_exc_point(code) do { \
5788     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5789          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5790              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5791          cfg->arch.async_point_count ++; \
5792     } \
5793 } while (0)
5794
5795 guint8 *
5796 mono_arch_emit_prolog (MonoCompile *cfg)
5797 {
5798         MonoMethod *method = cfg->method;
5799         MonoBasicBlock *bb;
5800         MonoMethodSignature *sig;
5801         MonoInst *ins;
5802         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5803         guint8 *code;
5804         CallInfo *cinfo;
5805         gint32 lmf_offset = cfg->arch.lmf_offset;
5806         gboolean args_clobbered = FALSE;
5807         gboolean trace = FALSE;
5808
5809         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
5810
5811         code = cfg->native_code = g_malloc (cfg->code_size);
5812
5813         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5814                 trace = TRUE;
5815
5816         /* Amount of stack space allocated by register saving code */
5817         pos = 0;
5818
5819         /* Offset between RSP and the CFA */
5820         cfa_offset = 0;
5821
5822         /*
5823          * The prolog consists of the following parts:
5824          * FP present:
5825          * - push rbp, mov rbp, rsp
5826          * - save callee saved regs using pushes
5827          * - allocate frame
5828          * - save rgctx if needed
5829          * - save lmf if needed
5830          * FP not present:
5831          * - allocate frame
5832          * - save rgctx if needed
5833          * - save lmf if needed
5834          * - save callee saved regs using moves
5835          */
5836
5837         // CFA = sp + 8
5838         cfa_offset = 8;
5839         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5840         // IP saved at CFA - 8
5841         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5842         async_exc_point (code);
5843         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5844
5845         if (!cfg->arch.omit_fp) {
5846                 amd64_push_reg (code, AMD64_RBP);
5847                 cfa_offset += 8;
5848                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5849                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5850                 async_exc_point (code);
5851 #ifdef HOST_WIN32
5852                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5853 #endif
5854                 /* These are handled automatically by the stack marking code */
5855                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
5856
5857                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5858                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5859                 async_exc_point (code);
5860 #ifdef HOST_WIN32
5861                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5862 #endif
5863         }
5864
5865         /* Save callee saved registers */
5866         if (!cfg->arch.omit_fp && !method->save_lmf) {
5867                 int offset = cfa_offset;
5868
5869                 for (i = 0; i < AMD64_NREG; ++i)
5870                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5871                                 amd64_push_reg (code, i);
5872                                 pos += sizeof (gpointer);
5873                                 offset += 8;
5874                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5875                                 async_exc_point (code);
5876
5877                                 /* These are handled automatically by the stack marking code */
5878                                 mini_gc_set_slot_type_from_cfa (cfg, - offset, SLOT_NOREF);
5879                         }
5880         }
5881
5882         /* The param area is always at offset 0 from sp */
5883         /* This needs to be allocated here, since it has to come after the spill area */
5884         if (cfg->arch.no_pushes && cfg->param_area) {
5885                 if (cfg->arch.omit_fp)
5886                         // FIXME:
5887                         g_assert_not_reached ();
5888                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5889         }
5890
5891         if (cfg->arch.omit_fp) {
5892                 /*
5893                  * On enter, the stack is misaligned by the pushing of the return
5894                  * address. It is either made aligned by the pushing of %rbp, or by
5895                  * this.
5896                  */
5897                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5898                 if ((alloc_size % 16) == 0) {
5899                         alloc_size += 8;
5900                         /* Mark the padding slot as NOREF */
5901                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
5902                 }
5903         } else {
5904                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5905
5906                 alloc_size -= pos;
5907         }
5908
5909         cfg->arch.stack_alloc_size = alloc_size;
5910
5911         /* Allocate stack frame */
5912         if (alloc_size) {
5913                 /* See mono_emit_stack_alloc */
5914 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5915                 guint32 remaining_size = alloc_size;
5916                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5917                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5918                 guint32 offset = code - cfg->native_code;
5919                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5920                         while (required_code_size >= (cfg->code_size - offset))
5921                                 cfg->code_size *= 2;
5922                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5923                         code = cfg->native_code + offset;
5924                         mono_jit_stats.code_reallocs++;
5925                 }
5926
5927                 while (remaining_size >= 0x1000) {
5928                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5929                         if (cfg->arch.omit_fp) {
5930                                 cfa_offset += 0x1000;
5931                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5932                         }
5933                         async_exc_point (code);
5934 #ifdef HOST_WIN32
5935                         if (cfg->arch.omit_fp)
5936                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5937 #endif
5938
5939                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5940                         remaining_size -= 0x1000;
5941                 }
5942                 if (remaining_size) {
5943                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5944                         if (cfg->arch.omit_fp) {
5945                                 cfa_offset += remaining_size;
5946                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5947                                 async_exc_point (code);
5948                         }
5949 #ifdef HOST_WIN32
5950                         if (cfg->arch.omit_fp)
5951                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5952 #endif
5953                 }
5954 #else
5955                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5956                 if (cfg->arch.omit_fp) {
5957                         cfa_offset += alloc_size;
5958                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5959                         async_exc_point (code);
5960                 }
5961 #endif
5962         }
5963
5964         /* Stack alignment check */
5965 #if 0
5966         {
5967                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5968                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5969                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5970                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5971                 amd64_breakpoint (code);
5972         }
5973 #endif
5974
5975 #ifndef TARGET_WIN32
5976         if (mini_get_debug_options ()->init_stacks) {
5977                 /* Fill the stack frame with a dummy value to force deterministic behavior */
5978
5979                 /* Save registers to the red zone */
5980                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5981                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5982
5983                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5984                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5985                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5986
5987                 amd64_cld (code);
5988                 amd64_prefix (code, X86_REP_PREFIX);
5989                 amd64_stosl (code);
5990
5991                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5992                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5993         }
5994 #endif
5995
5996         /* Save LMF */
5997         if (method->save_lmf) {
5998                 /*
5999                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
6000                  */
6001                 /*
6002                  * sp is saved right before calls but we need to save it here too so
6003                  * async stack walks would work.
6004                  */
6005                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
6006                 /* Skip method (only needed for trampoline LMF frames) */
6007                 /* Save callee saved regs */
6008                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
6009                         int offset;
6010
6011                         switch (i) {
6012                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
6013                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
6014                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
6015                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
6016                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
6017                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
6018 #ifdef HOST_WIN32
6019                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
6020                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
6021 #endif
6022                         default:
6023                                 offset = -1;
6024                                 break;
6025                         }
6026
6027                         if (offset != -1) {
6028                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
6029                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
6030                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
6031                         }
6032                 }
6033
6034                 /* These can't contain refs */
6035                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
6036                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), SLOT_NOREF);
6037                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), SLOT_NOREF);
6038                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
6039                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
6040
6041                 /* These are handled automatically by the stack marking code */
6042                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), SLOT_NOREF);
6043                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
6044                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), SLOT_NOREF);
6045                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), SLOT_NOREF);
6046                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), SLOT_NOREF);
6047                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), SLOT_NOREF);
6048 #ifdef HOST_WIN32
6049                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), SLOT_NOREF);
6050                 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), SLOT_NOREF);
6051 #endif
6052
6053         }
6054
6055         /* Save callee saved registers */
6056         if (cfg->arch.omit_fp && !method->save_lmf) {
6057                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6058
6059                 /* Save caller saved registers after sp is adjusted */
6060                 /* The registers are saved at the bottom of the frame */
6061                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6062                 for (i = 0; i < AMD64_NREG; ++i)
6063                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6064                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
6065                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6066
6067                                 /* These are handled automatically by the stack marking code */
6068                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6069
6070                                 save_area_offset += 8;
6071                                 async_exc_point (code);
6072                         }
6073         }
6074
6075         /* store runtime generic context */
6076         if (cfg->rgctx_var) {
6077                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6078                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6079
6080                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
6081         }
6082
6083         /* compute max_length in order to use short forward jumps */
6084         max_epilog_size = get_max_epilog_size (cfg);
6085         if (cfg->opt & MONO_OPT_BRANCH) {
6086                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6087                         MonoInst *ins;
6088                         int max_length = 0;
6089
6090                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6091                                 max_length += 6;
6092                         /* max alignment for loops */
6093                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6094                                 max_length += LOOP_ALIGNMENT;
6095
6096                         MONO_BB_FOR_EACH_INS (bb, ins) {
6097                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6098                         }
6099
6100                         /* Take prolog and epilog instrumentation into account */
6101                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6102                                 max_length += max_epilog_size;
6103
6104                         bb->max_length = max_length;
6105                 }
6106         }
6107
6108         sig = mono_method_signature (method);
6109         pos = 0;
6110
6111         cinfo = cfg->arch.cinfo;
6112
6113         if (sig->ret->type != MONO_TYPE_VOID) {
6114                 /* Save volatile arguments to the stack */
6115                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6116                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6117         }
6118
6119         /* Keep this in sync with emit_load_volatile_arguments */
6120         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6121                 ArgInfo *ainfo = cinfo->args + i;
6122                 gint32 stack_offset;
6123                 MonoType *arg_type;
6124
6125                 ins = cfg->args [i];
6126
6127                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6128                         /* Unused arguments */
6129                         continue;
6130
6131                 if (sig->hasthis && (i == 0))
6132                         arg_type = &mono_defaults.object_class->byval_arg;
6133                 else
6134                         arg_type = sig->params [i - sig->hasthis];
6135
6136                 stack_offset = ainfo->offset + ARGS_OFFSET;
6137
6138                 if (cfg->globalra) {
6139                         /* All the other moves are done by the register allocator */
6140                         switch (ainfo->storage) {
6141                         case ArgInFloatSSEReg:
6142                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6143                                 break;
6144                         case ArgValuetypeInReg:
6145                                 for (quad = 0; quad < 2; quad ++) {
6146                                         switch (ainfo->pair_storage [quad]) {
6147                                         case ArgInIReg:
6148                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6149                                                 break;
6150                                         case ArgInFloatSSEReg:
6151                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6152                                                 break;
6153                                         case ArgInDoubleSSEReg:
6154                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6155                                                 break;
6156                                         case ArgNone:
6157                                                 break;
6158                                         default:
6159                                                 g_assert_not_reached ();
6160                                         }
6161                                 }
6162                                 break;
6163                         default:
6164                                 break;
6165                         }
6166
6167                         continue;
6168                 }
6169
6170                 /* Save volatile arguments to the stack */
6171                 if (ins->opcode != OP_REGVAR) {
6172                         switch (ainfo->storage) {
6173                         case ArgInIReg: {
6174                                 guint32 size = 8;
6175
6176                                 /* FIXME: I1 etc */
6177                                 /*
6178                                 if (stack_offset & 0x1)
6179                                         size = 1;
6180                                 else if (stack_offset & 0x2)
6181                                         size = 2;
6182                                 else if (stack_offset & 0x4)
6183                                         size = 4;
6184                                 else
6185                                         size = 8;
6186                                 */
6187                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6188                                 break;
6189                         }
6190                         case ArgInFloatSSEReg:
6191                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6192                                 break;
6193                         case ArgInDoubleSSEReg:
6194                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6195                                 break;
6196                         case ArgValuetypeInReg:
6197                                 for (quad = 0; quad < 2; quad ++) {
6198                                         switch (ainfo->pair_storage [quad]) {
6199                                         case ArgInIReg:
6200                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6201                                                 break;
6202                                         case ArgInFloatSSEReg:
6203                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6204                                                 break;
6205                                         case ArgInDoubleSSEReg:
6206                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6207                                                 break;
6208                                         case ArgNone:
6209                                                 break;
6210                                         default:
6211                                                 g_assert_not_reached ();
6212                                         }
6213                                 }
6214                                 break;
6215                         case ArgValuetypeAddrInIReg:
6216                                 if (ainfo->pair_storage [0] == ArgInIReg)
6217                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6218                                 break;
6219                         default:
6220                                 break;
6221                         }
6222                 } else {
6223                         /* Argument allocated to (non-volatile) register */
6224                         switch (ainfo->storage) {
6225                         case ArgInIReg:
6226                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6227                                 break;
6228                         case ArgOnStack:
6229                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6230                                 break;
6231                         default:
6232                                 g_assert_not_reached ();
6233                         }
6234                 }
6235         }
6236
6237         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6238         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6239                 guint64 domain = (guint64)cfg->domain;
6240
6241                 args_clobbered = TRUE;
6242
6243                 /*
6244                  * The call might clobber argument registers, but they are already
6245                  * saved to the stack/global regs.
6246                  */
6247                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6248                         guint8 *buf, *no_domain_branch;
6249
6250                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6251                         if (cfg->compile_aot) {
6252                                 /* AOT code is only used in the root domain */
6253                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6254                         } else {
6255                                 if ((domain >> 32) == 0)
6256                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6257                                 else
6258                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6259                         }
6260                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6261                         no_domain_branch = code;
6262                         x86_branch8 (code, X86_CC_NE, 0, 0);
6263                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6264                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6265                         buf = code;
6266                         x86_branch8 (code, X86_CC_NE, 0, 0);
6267                         amd64_patch (no_domain_branch, code);
6268                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6269                                           (gpointer)"mono_jit_thread_attach", TRUE);
6270                         amd64_patch (buf, code);
6271 #ifdef HOST_WIN32
6272                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6273                         /* FIXME: Add a separate key for LMF to avoid this */
6274                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6275 #endif
6276                 } else {
6277                         g_assert (!cfg->compile_aot);
6278                         if (cfg->compile_aot) {
6279                                 /* AOT code is only used in the root domain */
6280                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6281                         } else {
6282                                 if ((domain >> 32) == 0)
6283                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6284                                 else
6285                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6286                         }
6287                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6288                                           (gpointer)"mono_jit_thread_attach", TRUE);
6289                 }
6290         }
6291
6292         if (method->save_lmf) {
6293                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6294                         /*
6295                          * Optimized version which uses the mono_lmf TLS variable instead of
6296                          * indirection through the mono_lmf_addr TLS variable.
6297                          */
6298                         /* %rax = previous_lmf */
6299                         x86_prefix (code, X86_FS_PREFIX);
6300                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6301
6302                         /* Save previous_lmf */
6303                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6304                         /* Set new lmf */
6305                         if (lmf_offset == 0) {
6306                                 x86_prefix (code, X86_FS_PREFIX);
6307                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6308                         } else {
6309                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6310                                 x86_prefix (code, X86_FS_PREFIX);
6311                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6312                         }
6313                 } else {
6314                         if (lmf_addr_tls_offset != -1) {
6315                                 /* Load lmf quicky using the FS register */
6316                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6317 #ifdef HOST_WIN32
6318                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6319                                 /* FIXME: Add a separate key for LMF to avoid this */
6320                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6321 #endif
6322                         }
6323                         else {
6324                                 /*
6325                                  * The call might clobber argument registers, but they are already
6326                                  * saved to the stack/global regs.
6327                                  */
6328                                 args_clobbered = TRUE;
6329                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6330                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6331                         }
6332
6333                         /* Save lmf_addr */
6334                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6335                         /* Save previous_lmf */
6336                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6337                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6338                         /* Set new lmf */
6339                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6340                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6341                 }
6342         }
6343
6344         if (trace) {
6345                 args_clobbered = TRUE;
6346                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6347         }
6348
6349         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6350                 args_clobbered = TRUE;
6351
6352         /*
6353          * Optimize the common case of the first bblock making a call with the same
6354          * arguments as the method. This works because the arguments are still in their
6355          * original argument registers.
6356          * FIXME: Generalize this
6357          */
6358         if (!args_clobbered) {
6359                 MonoBasicBlock *first_bb = cfg->bb_entry;
6360                 MonoInst *next;
6361
6362                 next = mono_bb_first_ins (first_bb);
6363                 if (!next && first_bb->next_bb) {
6364                         first_bb = first_bb->next_bb;
6365                         next = mono_bb_first_ins (first_bb);
6366                 }
6367
6368                 if (first_bb->in_count > 1)
6369                         next = NULL;
6370
6371                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6372                         ArgInfo *ainfo = cinfo->args + i;
6373                         gboolean match = FALSE;
6374
6375                         ins = cfg->args [i];
6376                         if (ins->opcode != OP_REGVAR) {
6377                                 switch (ainfo->storage) {
6378                                 case ArgInIReg: {
6379                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6380                                                 if (next->dreg == ainfo->reg) {
6381                                                         NULLIFY_INS (next);
6382                                                         match = TRUE;
6383                                                 } else {
6384                                                         next->opcode = OP_MOVE;
6385                                                         next->sreg1 = ainfo->reg;
6386                                                         /* Only continue if the instruction doesn't change argument regs */
6387                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6388                                                                 match = TRUE;
6389                                                 }
6390                                         }
6391                                         break;
6392                                 }
6393                                 default:
6394                                         break;
6395                                 }
6396                         } else {
6397                                 /* Argument allocated to (non-volatile) register */
6398                                 switch (ainfo->storage) {
6399                                 case ArgInIReg:
6400                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6401                                                 NULLIFY_INS (next);
6402                                                 match = TRUE;
6403                                         }
6404                                         break;
6405                                 default:
6406                                         break;
6407                                 }
6408                         }
6409
6410                         if (match) {
6411                                 next = next->next;
6412                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6413                                 if (!next)
6414                                         break;
6415                         }
6416                 }
6417         }
6418
6419         /* Initialize ss_trigger_page_var */
6420         if (cfg->arch.ss_trigger_page_var) {
6421                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6422
6423                 g_assert (!cfg->compile_aot);
6424                 g_assert (var->opcode == OP_REGOFFSET);
6425
6426                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6427                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6428         }
6429
6430         cfg->code_len = code - cfg->native_code;
6431
6432         g_assert (cfg->code_len < cfg->code_size);
6433
6434         return code;
6435 }
6436
6437 void
6438 mono_arch_emit_epilog (MonoCompile *cfg)
6439 {
6440         MonoMethod *method = cfg->method;
6441         int quad, pos, i;
6442         guint8 *code;
6443         int max_epilog_size;
6444         CallInfo *cinfo;
6445         gint32 lmf_offset = cfg->arch.lmf_offset;
6446
6447         max_epilog_size = get_max_epilog_size (cfg);
6448
6449         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6450                 cfg->code_size *= 2;
6451                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6452                 mono_jit_stats.code_reallocs++;
6453         }
6454
6455         code = cfg->native_code + cfg->code_len;
6456
6457         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6458                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6459
6460         /* the code restoring the registers must be kept in sync with OP_JMP */
6461         pos = 0;
6462
6463         if (method->save_lmf) {
6464                 /* check if we need to restore protection of the stack after a stack overflow */
6465                 if (mono_get_jit_tls_offset () != -1) {
6466                         guint8 *patch;
6467                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6468                         /* we load the value in a separate instruction: this mechanism may be
6469                          * used later as a safer way to do thread interruption
6470                          */
6471                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6472                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6473                         patch = code;
6474                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6475                         /* note that the call trampoline will preserve eax/edx */
6476                         x86_call_reg (code, X86_ECX);
6477                         x86_patch (patch, code);
6478                 } else {
6479                         /* FIXME: maybe save the jit tls in the prolog */
6480                 }
6481                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6482                         /*
6483                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6484                          * through the mono_lmf_addr TLS variable.
6485                          */
6486                         /* reg = previous_lmf */
6487                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6488                         x86_prefix (code, X86_FS_PREFIX);
6489                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6490                 } else {
6491                         /* Restore previous lmf */
6492                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6493                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6494                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6495                 }
6496
6497                 /* Restore caller saved regs */
6498                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6499                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6500                 }
6501                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6502                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6503                 }
6504                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6505                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6506                 }
6507                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6508                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6509                 }
6510                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6511                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6512                 }
6513                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6514                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6515                 }
6516 #ifdef HOST_WIN32
6517                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6518                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6519                 }
6520                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6521                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6522                 }
6523 #endif
6524         } else {
6525
6526                 if (cfg->arch.omit_fp) {
6527                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6528
6529                         for (i = 0; i < AMD64_NREG; ++i)
6530                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6531                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6532                                         save_area_offset += 8;
6533                                 }
6534                 }
6535                 else {
6536                         for (i = 0; i < AMD64_NREG; ++i)
6537                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6538                                         pos -= sizeof (gpointer);
6539
6540                         if (pos) {
6541                                 if (pos == - sizeof (gpointer)) {
6542                                         /* Only one register, so avoid lea */
6543                                         for (i = AMD64_NREG - 1; i > 0; --i)
6544                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6545                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6546                                                 }
6547                                 }
6548                                 else {
6549                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6550
6551                                         /* Pop registers in reverse order */
6552                                         for (i = AMD64_NREG - 1; i > 0; --i)
6553                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6554                                                         amd64_pop_reg (code, i);
6555                                                 }
6556                                 }
6557                         }
6558                 }
6559         }
6560
6561         /* Load returned vtypes into registers if needed */
6562         cinfo = cfg->arch.cinfo;
6563         if (cinfo->ret.storage == ArgValuetypeInReg) {
6564                 ArgInfo *ainfo = &cinfo->ret;
6565                 MonoInst *inst = cfg->ret;
6566
6567                 for (quad = 0; quad < 2; quad ++) {
6568                         switch (ainfo->pair_storage [quad]) {
6569                         case ArgInIReg:
6570                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6571                                 break;
6572                         case ArgInFloatSSEReg:
6573                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6574                                 break;
6575                         case ArgInDoubleSSEReg:
6576                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6577                                 break;
6578                         case ArgNone:
6579                                 break;
6580                         default:
6581                                 g_assert_not_reached ();
6582                         }
6583                 }
6584         }
6585
6586         if (cfg->arch.omit_fp) {
6587                 if (cfg->arch.stack_alloc_size)
6588                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6589         } else {
6590                 amd64_leave (code);
6591         }
6592         async_exc_point (code);
6593         amd64_ret (code);
6594
6595         cfg->code_len = code - cfg->native_code;
6596
6597         g_assert (cfg->code_len < cfg->code_size);
6598 }
6599
6600 void
6601 mono_arch_emit_exceptions (MonoCompile *cfg)
6602 {
6603         MonoJumpInfo *patch_info;
6604         int nthrows, i;
6605         guint8 *code;
6606         MonoClass *exc_classes [16];
6607         guint8 *exc_throw_start [16], *exc_throw_end [16];
6608         guint32 code_size = 0;
6609
6610         /* Compute needed space */
6611         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6612                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6613                         code_size += 40;
6614                 if (patch_info->type == MONO_PATCH_INFO_R8)
6615                         code_size += 8 + 15; /* sizeof (double) + alignment */
6616                 if (patch_info->type == MONO_PATCH_INFO_R4)
6617                         code_size += 4 + 15; /* sizeof (float) + alignment */
6618                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
6619                         code_size += 8 + 7; /*sizeof (void*) + alignment */
6620         }
6621
6622         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6623                 cfg->code_size *= 2;
6624                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6625                 mono_jit_stats.code_reallocs++;
6626         }
6627
6628         code = cfg->native_code + cfg->code_len;
6629
6630         /* add code to raise exceptions */
6631         nthrows = 0;
6632         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6633                 switch (patch_info->type) {
6634                 case MONO_PATCH_INFO_EXC: {
6635                         MonoClass *exc_class;
6636                         guint8 *buf, *buf2;
6637                         guint32 throw_ip;
6638
6639                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6640
6641                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6642                         g_assert (exc_class);
6643                         throw_ip = patch_info->ip.i;
6644
6645                         //x86_breakpoint (code);
6646                         /* Find a throw sequence for the same exception class */
6647                         for (i = 0; i < nthrows; ++i)
6648                                 if (exc_classes [i] == exc_class)
6649                                         break;
6650                         if (i < nthrows) {
6651                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6652                                 x86_jump_code (code, exc_throw_start [i]);
6653                                 patch_info->type = MONO_PATCH_INFO_NONE;
6654                         }
6655                         else {
6656                                 buf = code;
6657                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6658                                 buf2 = code;
6659
6660                                 if (nthrows < 16) {
6661                                         exc_classes [nthrows] = exc_class;
6662                                         exc_throw_start [nthrows] = code;
6663                                 }
6664                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
6665
6666                                 patch_info->type = MONO_PATCH_INFO_NONE;
6667
6668                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6669
6670                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6671                                 while (buf < buf2)
6672                                         x86_nop (buf);
6673
6674                                 if (nthrows < 16) {
6675                                         exc_throw_end [nthrows] = code;
6676                                         nthrows ++;
6677                                 }
6678                         }
6679                         break;
6680                 }
6681                 default:
6682                         /* do nothing */
6683                         break;
6684                 }
6685         }
6686
6687         /* Handle relocations with RIP relative addressing */
6688         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6689                 gboolean remove = FALSE;
6690                 guint8 *orig_code = code;
6691
6692                 switch (patch_info->type) {
6693                 case MONO_PATCH_INFO_R8:
6694                 case MONO_PATCH_INFO_R4: {
6695                         guint8 *pos;
6696
6697                         /* The SSE opcodes require a 16 byte alignment */
6698                         code = (guint8*)ALIGN_TO (code, 16);
6699                         memset (orig_code, 0, code - orig_code);
6700
6701                         pos = cfg->native_code + patch_info->ip.i;
6702
6703                         if (IS_REX (pos [1]))
6704                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6705                         else
6706                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6707
6708                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6709                                 *(double*)code = *(double*)patch_info->data.target;
6710                                 code += sizeof (double);
6711                         } else {
6712                                 *(float*)code = *(float*)patch_info->data.target;
6713                                 code += sizeof (float);
6714                         }
6715
6716                         remove = TRUE;
6717                         break;
6718                 }
6719                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
6720                         guint8 *pos;
6721
6722                         if (cfg->compile_aot)
6723                                 continue;
6724
6725                         /*loading is faster against aligned addresses.*/
6726                         code = (guint8*)ALIGN_TO (code, 8);
6727                         memset (orig_code, 0, code - orig_code);
6728
6729                         pos = cfg->native_code + patch_info->ip.i;
6730
6731                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
6732                         if (IS_REX (pos [1]))
6733                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6734                         else
6735                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
6736
6737                         *(gpointer*)code = (gpointer)patch_info->data.target;
6738                         code += sizeof (gpointer);
6739
6740                         remove = TRUE;
6741                         break;
6742                 }
6743                 default:
6744                         break;
6745                 }
6746
6747                 if (remove) {
6748                         if (patch_info == cfg->patch_info)
6749                                 cfg->patch_info = patch_info->next;
6750                         else {
6751                                 MonoJumpInfo *tmp;
6752
6753                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6754                                         ;
6755                                 tmp->next = patch_info->next;
6756                         }
6757                 }
6758         }
6759
6760         cfg->code_len = code - cfg->native_code;
6761
6762         g_assert (cfg->code_len < cfg->code_size);
6763
6764 }
6765
6766 #endif /* DISABLE_JIT */
6767
6768 void*
6769 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6770 {
6771         guchar *code = p;
6772         CallInfo *cinfo = NULL;
6773         MonoMethodSignature *sig;
6774         MonoInst *inst;
6775         int i, n, stack_area = 0;
6776
6777         /* Keep this in sync with mono_arch_get_argument_info */
6778
6779         if (enable_arguments) {
6780                 /* Allocate a new area on the stack and save arguments there */
6781                 sig = mono_method_signature (cfg->method);
6782
6783                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
6784
6785                 n = sig->param_count + sig->hasthis;
6786
6787                 stack_area = ALIGN_TO (n * 8, 16);
6788
6789                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6790
6791                 for (i = 0; i < n; ++i) {
6792                         inst = cfg->args [i];
6793
6794                         if (inst->opcode == OP_REGVAR)
6795                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6796                         else {
6797                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6798                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6799                         }
6800                 }
6801         }
6802
6803         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6804         amd64_set_reg_template (code, AMD64_ARG_REG1);
6805         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6806         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6807
6808         if (enable_arguments)
6809                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6810
6811         return code;
6812 }
6813
6814 enum {
6815         SAVE_NONE,
6816         SAVE_STRUCT,
6817         SAVE_EAX,
6818         SAVE_EAX_EDX,
6819         SAVE_XMM
6820 };
6821
6822 void*
6823 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6824 {
6825         guchar *code = p;
6826         int save_mode = SAVE_NONE;
6827         MonoMethod *method = cfg->method;
6828         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6829
6830         switch (ret_type->type) {
6831         case MONO_TYPE_VOID:
6832                 /* special case string .ctor icall */
6833                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6834                         save_mode = SAVE_EAX;
6835                 else
6836                         save_mode = SAVE_NONE;
6837                 break;
6838         case MONO_TYPE_I8:
6839         case MONO_TYPE_U8:
6840                 save_mode = SAVE_EAX;
6841                 break;
6842         case MONO_TYPE_R4:
6843         case MONO_TYPE_R8:
6844                 save_mode = SAVE_XMM;
6845                 break;
6846         case MONO_TYPE_GENERICINST:
6847                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6848                         save_mode = SAVE_EAX;
6849                         break;
6850                 }
6851                 /* Fall through */
6852         case MONO_TYPE_VALUETYPE:
6853                 save_mode = SAVE_STRUCT;
6854                 break;
6855         default:
6856                 save_mode = SAVE_EAX;
6857                 break;
6858         }
6859
6860         /* Save the result and copy it into the proper argument register */
6861         switch (save_mode) {
6862         case SAVE_EAX:
6863                 amd64_push_reg (code, AMD64_RAX);
6864                 /* Align stack */
6865                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6866                 if (enable_arguments)
6867                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6868                 break;
6869         case SAVE_STRUCT:
6870                 /* FIXME: */
6871                 if (enable_arguments)
6872                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6873                 break;
6874         case SAVE_XMM:
6875                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6876                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6877                 /* Align stack */
6878                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6879                 /*
6880                  * The result is already in the proper argument register so no copying
6881                  * needed.
6882                  */
6883                 break;
6884         case SAVE_NONE:
6885                 break;
6886         default:
6887                 g_assert_not_reached ();
6888         }
6889
6890         /* Set %al since this is a varargs call */
6891         if (save_mode == SAVE_XMM)
6892                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6893         else
6894                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6895
6896         if (preserve_argument_registers) {
6897                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6898                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6899         }
6900
6901         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6902         amd64_set_reg_template (code, AMD64_ARG_REG1);
6903         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6904
6905         if (preserve_argument_registers) {
6906                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6907                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6908         }
6909
6910         /* Restore result */
6911         switch (save_mode) {
6912         case SAVE_EAX:
6913                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6914                 amd64_pop_reg (code, AMD64_RAX);
6915                 break;
6916         case SAVE_STRUCT:
6917                 /* FIXME: */
6918                 break;
6919         case SAVE_XMM:
6920                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6921                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6922                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6923                 break;
6924         case SAVE_NONE:
6925                 break;
6926         default:
6927                 g_assert_not_reached ();
6928         }
6929
6930         return code;
6931 }
6932
6933 void
6934 mono_arch_flush_icache (guint8 *code, gint size)
6935 {
6936         /* Not needed */
6937 }
6938
6939 void
6940 mono_arch_flush_register_windows (void)
6941 {
6942 }
6943
6944 gboolean
6945 mono_arch_is_inst_imm (gint64 imm)
6946 {
6947         return amd64_is_imm32 (imm);
6948 }
6949
6950 /*
6951  * Determine whenever the trap whose info is in SIGINFO is caused by
6952  * integer overflow.
6953  */
6954 gboolean
6955 mono_arch_is_int_overflow (void *sigctx, void *info)
6956 {
6957         MonoContext ctx;
6958         guint8* rip;
6959         int reg;
6960         gint64 value;
6961
6962         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6963
6964         rip = (guint8*)ctx.rip;
6965
6966         if (IS_REX (rip [0])) {
6967                 reg = amd64_rex_b (rip [0]);
6968                 rip ++;
6969         }
6970         else
6971                 reg = 0;
6972
6973         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6974                 /* idiv REG */
6975                 reg += x86_modrm_rm (rip [1]);
6976
6977                 switch (reg) {
6978                 case AMD64_RAX:
6979                         value = ctx.rax;
6980                         break;
6981                 case AMD64_RBX:
6982                         value = ctx.rbx;
6983                         break;
6984                 case AMD64_RCX:
6985                         value = ctx.rcx;
6986                         break;
6987                 case AMD64_RDX:
6988                         value = ctx.rdx;
6989                         break;
6990                 case AMD64_RBP:
6991                         value = ctx.rbp;
6992                         break;
6993                 case AMD64_RSP:
6994                         value = ctx.rsp;
6995                         break;
6996                 case AMD64_RSI:
6997                         value = ctx.rsi;
6998                         break;
6999                 case AMD64_RDI:
7000                         value = ctx.rdi;
7001                         break;
7002                 case AMD64_R12:
7003                         value = ctx.r12;
7004                         break;
7005                 case AMD64_R13:
7006                         value = ctx.r13;
7007                         break;
7008                 case AMD64_R14:
7009                         value = ctx.r14;
7010                         break;
7011                 case AMD64_R15:
7012                         value = ctx.r15;
7013                         break;
7014                 default:
7015                         g_assert_not_reached ();
7016                         reg = -1;
7017                 }
7018
7019                 if (value == -1)
7020                         return TRUE;
7021         }
7022
7023         return FALSE;
7024 }
7025
7026 guint32
7027 mono_arch_get_patch_offset (guint8 *code)
7028 {
7029         return 3;
7030 }
7031
7032 /**
7033  * mono_breakpoint_clean_code:
7034  *
7035  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7036  * breakpoints in the original code, they are removed in the copy.
7037  *
7038  * Returns TRUE if no sw breakpoint was present.
7039  */
7040 gboolean
7041 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7042 {
7043         int i;
7044         gboolean can_write = TRUE;
7045         /*
7046          * If method_start is non-NULL we need to perform bound checks, since we access memory
7047          * at code - offset we could go before the start of the method and end up in a different
7048          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7049          * instead.
7050          */
7051         if (!method_start || code - offset >= method_start) {
7052                 memcpy (buf, code - offset, size);
7053         } else {
7054                 int diff = code - method_start;
7055                 memset (buf, 0, size);
7056                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7057         }
7058         code -= offset;
7059         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
7060                 int idx = mono_breakpoint_info_index [i];
7061                 guint8 *ptr;
7062                 if (idx < 1)
7063                         continue;
7064                 ptr = mono_breakpoint_info [idx].address;
7065                 if (ptr >= code && ptr < code + size) {
7066                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
7067                         can_write = FALSE;
7068                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
7069                         buf [ptr - code] = saved_byte;
7070                 }
7071         }
7072         return can_write;
7073 }
7074
7075 int
7076 mono_arch_get_this_arg_reg (guint8 *code)
7077 {
7078         return AMD64_ARG_REG1;
7079 }
7080
7081 gpointer
7082 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7083 {
7084         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7085 }
7086
7087 #define MAX_ARCH_DELEGATE_PARAMS 10
7088
7089 static gpointer
7090 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7091 {
7092         guint8 *code, *start;
7093         int i;
7094
7095         if (has_target) {
7096                 start = code = mono_global_codeman_reserve (64);
7097
7098                 /* Replace the this argument with the target */
7099                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7100                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7101                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7102
7103                 g_assert ((code - start) < 64);
7104         } else {
7105                 start = code = mono_global_codeman_reserve (64);
7106
7107                 if (param_count == 0) {
7108                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7109                 } else {
7110                         /* We have to shift the arguments left */
7111                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7112                         for (i = 0; i < param_count; ++i) {
7113 #ifdef HOST_WIN32
7114                                 if (i < 3)
7115                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7116                                 else
7117                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7118 #else
7119                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7120 #endif
7121                         }
7122
7123                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7124                 }
7125                 g_assert ((code - start) < 64);
7126         }
7127
7128         mono_debug_add_delegate_trampoline (start, code - start);
7129
7130         if (code_len)
7131                 *code_len = code - start;
7132
7133
7134         if (mono_jit_map_is_enabled ()) {
7135                 char *buff;
7136                 if (has_target)
7137                         buff = (char*)"delegate_invoke_has_target";
7138                 else
7139                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7140                 mono_emit_jit_tramp (start, code - start, buff);
7141                 if (!has_target)
7142                         g_free (buff);
7143         }
7144
7145         return start;
7146 }
7147
7148 /*
7149  * mono_arch_get_delegate_invoke_impls:
7150  *
7151  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7152  * trampolines.
7153  */
7154 GSList*
7155 mono_arch_get_delegate_invoke_impls (void)
7156 {
7157         GSList *res = NULL;
7158         guint8 *code;
7159         guint32 code_len;
7160         int i;
7161
7162         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7163         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7164
7165         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7166                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7167                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7168         }
7169
7170         return res;
7171 }
7172
7173 gpointer
7174 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7175 {
7176         guint8 *code, *start;
7177         int i;
7178
7179         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7180                 return NULL;
7181
7182         /* FIXME: Support more cases */
7183         if (MONO_TYPE_ISSTRUCT (sig->ret))
7184                 return NULL;
7185
7186         if (has_target) {
7187                 static guint8* cached = NULL;
7188
7189                 if (cached)
7190                         return cached;
7191
7192                 if (mono_aot_only)
7193                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7194                 else
7195                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7196
7197                 mono_memory_barrier ();
7198
7199                 cached = start;
7200         } else {
7201                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7202                 for (i = 0; i < sig->param_count; ++i)
7203                         if (!mono_is_regsize_var (sig->params [i]))
7204                                 return NULL;
7205                 if (sig->param_count > 4)
7206                         return NULL;
7207
7208                 code = cache [sig->param_count];
7209                 if (code)
7210                         return code;
7211
7212                 if (mono_aot_only) {
7213                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7214                         start = mono_aot_get_trampoline (name);
7215                         g_free (name);
7216                 } else {
7217                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7218                 }
7219
7220                 mono_memory_barrier ();
7221
7222                 cache [sig->param_count] = start;
7223         }
7224
7225         return start;
7226 }
7227
7228 /*
7229  * Support for fast access to the thread-local lmf structure using the GS
7230  * segment register on NPTL + kernel 2.6.x.
7231  */
7232
7233 static gboolean tls_offset_inited = FALSE;
7234
7235 void
7236 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7237 {
7238         if (!tls_offset_inited) {
7239 #ifdef HOST_WIN32
7240                 /*
7241                  * We need to init this multiple times, since when we are first called, the key might not
7242                  * be initialized yet.
7243                  */
7244                 appdomain_tls_offset = mono_domain_get_tls_key ();
7245                 lmf_tls_offset = mono_get_jit_tls_key ();
7246                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7247
7248                 /* Only 64 tls entries can be accessed using inline code */
7249                 if (appdomain_tls_offset >= 64)
7250                         appdomain_tls_offset = -1;
7251                 if (lmf_tls_offset >= 64)
7252                         lmf_tls_offset = -1;
7253 #else
7254                 tls_offset_inited = TRUE;
7255 #ifdef MONO_XEN_OPT
7256                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7257 #endif
7258                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7259                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7260                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7261 #endif
7262         }
7263 }
7264
7265 void
7266 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7267 {
7268 }
7269
7270 #ifdef MONO_ARCH_HAVE_IMT
7271
7272 #define CMP_SIZE (6 + 1)
7273 #define CMP_REG_REG_SIZE (4 + 1)
7274 #define BR_SMALL_SIZE 2
7275 #define BR_LARGE_SIZE 6
7276 #define MOV_REG_IMM_SIZE 10
7277 #define MOV_REG_IMM_32BIT_SIZE 6
7278 #define JUMP_REG_SIZE (2 + 1)
7279
7280 static int
7281 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7282 {
7283         int i, distance = 0;
7284         for (i = start; i < target; ++i)
7285                 distance += imt_entries [i]->chunk_size;
7286         return distance;
7287 }
7288
7289 /*
7290  * LOCKING: called with the domain lock held
7291  */
7292 gpointer
7293 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7294         gpointer fail_tramp)
7295 {
7296         int i;
7297         int size = 0;
7298         guint8 *code, *start;
7299         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7300
7301         for (i = 0; i < count; ++i) {
7302                 MonoIMTCheckItem *item = imt_entries [i];
7303                 if (item->is_equals) {
7304                         if (item->check_target_idx) {
7305                                 if (!item->compare_done) {
7306                                         if (amd64_is_imm32 (item->key))
7307                                                 item->chunk_size += CMP_SIZE;
7308                                         else
7309                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7310                                 }
7311                                 if (item->has_target_code) {
7312                                         item->chunk_size += MOV_REG_IMM_SIZE;
7313                                 } else {
7314                                         if (vtable_is_32bit)
7315                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7316                                         else
7317                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7318                                 }
7319                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7320                         } else {
7321                                 if (fail_tramp) {
7322                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7323                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7324                                 } else {
7325                                         if (vtable_is_32bit)
7326                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7327                                         else
7328                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7329                                         item->chunk_size += JUMP_REG_SIZE;
7330                                         /* with assert below:
7331                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7332                                          */
7333                                 }
7334                         }
7335                 } else {
7336                         if (amd64_is_imm32 (item->key))
7337                                 item->chunk_size += CMP_SIZE;
7338                         else
7339                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7340                         item->chunk_size += BR_LARGE_SIZE;
7341                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7342                 }
7343                 size += item->chunk_size;
7344         }
7345         if (fail_tramp)
7346                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7347         else
7348                 code = mono_domain_code_reserve (domain, size);
7349         start = code;
7350         for (i = 0; i < count; ++i) {
7351                 MonoIMTCheckItem *item = imt_entries [i];
7352                 item->code_target = code;
7353                 if (item->is_equals) {
7354                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7355
7356                         if (item->check_target_idx || fail_case) {
7357                                 if (!item->compare_done || fail_case) {
7358                                         if (amd64_is_imm32 (item->key))
7359                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7360                                         else {
7361                                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7362                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7363                                         }
7364                                 }
7365                                 item->jmp_code = code;
7366                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7367                                 if (item->has_target_code) {
7368                                         amd64_mov_reg_imm (code, AMD64_R11, item->value.target_code);
7369                                         amd64_jump_reg (code, AMD64_R11);
7370                                 } else {
7371                                         amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7372                                         amd64_jump_membase (code, AMD64_R11, 0);
7373                                 }
7374
7375                                 if (fail_case) {
7376                                         amd64_patch (item->jmp_code, code);
7377                                         amd64_mov_reg_imm (code, AMD64_R11, fail_tramp);
7378                                         amd64_jump_reg (code, AMD64_R11);
7379                                         item->jmp_code = NULL;
7380                                 }
7381                         } else {
7382                                 /* enable the commented code to assert on wrong method */
7383 #if 0
7384                                 if (amd64_is_imm32 (item->key))
7385                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7386                                 else {
7387                                         amd64_mov_reg_imm (code, AMD64_R11, item->key);
7388                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7389                                 }
7390                                 item->jmp_code = code;
7391                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7392                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7393                                 amd64_jump_membase (code, AMD64_R11, 0);
7394                                 amd64_patch (item->jmp_code, code);
7395                                 amd64_breakpoint (code);
7396                                 item->jmp_code = NULL;
7397 #else
7398                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7399                                 amd64_jump_membase (code, AMD64_R11, 0);
7400 #endif
7401                         }
7402                 } else {
7403                         if (amd64_is_imm32 (item->key))
7404                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7405                         else {
7406                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7407                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7408                         }
7409                         item->jmp_code = code;
7410                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7411                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7412                         else
7413                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7414                 }
7415                 g_assert (code - item->code_target <= item->chunk_size);
7416         }
7417         /* patch the branches to get to the target items */
7418         for (i = 0; i < count; ++i) {
7419                 MonoIMTCheckItem *item = imt_entries [i];
7420                 if (item->jmp_code) {
7421                         if (item->check_target_idx) {
7422                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7423                         }
7424                 }
7425         }
7426
7427         if (!fail_tramp)
7428                 mono_stats.imt_thunks_size += code - start;
7429         g_assert (code - start <= size);
7430
7431         return start;
7432 }
7433
7434 MonoMethod*
7435 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7436 {
7437         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7438 }
7439 #endif
7440
7441 MonoVTable*
7442 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7443 {
7444         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7445 }
7446
7447 GSList*
7448 mono_arch_get_cie_program (void)
7449 {
7450         GSList *l = NULL;
7451
7452         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7453         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7454
7455         return l;
7456 }
7457
7458 MonoInst*
7459 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7460 {
7461         MonoInst *ins = NULL;
7462         int opcode = 0;
7463
7464         if (cmethod->klass == mono_defaults.math_class) {
7465                 if (strcmp (cmethod->name, "Sin") == 0) {
7466                         opcode = OP_SIN;
7467                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7468                         opcode = OP_COS;
7469                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7470                         opcode = OP_SQRT;
7471                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7472                         opcode = OP_ABS;
7473                 }
7474
7475                 if (opcode) {
7476                         MONO_INST_NEW (cfg, ins, opcode);
7477                         ins->type = STACK_R8;
7478                         ins->dreg = mono_alloc_freg (cfg);
7479                         ins->sreg1 = args [0]->dreg;
7480                         MONO_ADD_INS (cfg->cbb, ins);
7481                 }
7482
7483                 opcode = 0;
7484                 if (cfg->opt & MONO_OPT_CMOV) {
7485                         if (strcmp (cmethod->name, "Min") == 0) {
7486                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7487                                         opcode = OP_IMIN;
7488                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7489                                         opcode = OP_IMIN_UN;
7490                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7491                                         opcode = OP_LMIN;
7492                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7493                                         opcode = OP_LMIN_UN;
7494                         } else if (strcmp (cmethod->name, "Max") == 0) {
7495                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7496                                         opcode = OP_IMAX;
7497                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7498                                         opcode = OP_IMAX_UN;
7499                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7500                                         opcode = OP_LMAX;
7501                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7502                                         opcode = OP_LMAX_UN;
7503                         }
7504                 }
7505
7506                 if (opcode) {
7507                         MONO_INST_NEW (cfg, ins, opcode);
7508                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7509                         ins->dreg = mono_alloc_ireg (cfg);
7510                         ins->sreg1 = args [0]->dreg;
7511                         ins->sreg2 = args [1]->dreg;
7512                         MONO_ADD_INS (cfg->cbb, ins);
7513                 }
7514
7515 #if 0
7516                 /* OP_FREM is not IEEE compatible */
7517                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7518                         MONO_INST_NEW (cfg, ins, OP_FREM);
7519                         ins->inst_i0 = args [0];
7520                         ins->inst_i1 = args [1];
7521                 }
7522 #endif
7523         }
7524
7525         /*
7526          * Can't implement CompareExchange methods this way since they have
7527          * three arguments.
7528          */
7529
7530         return ins;
7531 }
7532
7533 gboolean
7534 mono_arch_print_tree (MonoInst *tree, int arity)
7535 {
7536         return 0;
7537 }
7538
7539 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7540 {
7541         MonoInst* ins;
7542
7543         if (appdomain_tls_offset == -1)
7544                 return NULL;
7545
7546         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7547         ins->inst_offset = appdomain_tls_offset;
7548         return ins;
7549 }
7550
7551 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7552
7553 gpointer
7554 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7555 {
7556         switch (reg) {
7557         case AMD64_RCX: return (gpointer)ctx->rcx;
7558         case AMD64_RDX: return (gpointer)ctx->rdx;
7559         case AMD64_RBX: return (gpointer)ctx->rbx;
7560         case AMD64_RBP: return (gpointer)ctx->rbp;
7561         case AMD64_RSP: return (gpointer)ctx->rsp;
7562         default:
7563                 if (reg < 8)
7564                         return _CTX_REG (ctx, rax, reg);
7565                 else if (reg >= 12)
7566                         return _CTX_REG (ctx, r12, reg - 12);
7567                 else
7568                         g_assert_not_reached ();
7569         }
7570 }
7571
7572 /*MONO_ARCH_HAVE_HANDLER_BLOCK_GUARD*/
7573 gpointer
7574 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
7575 {
7576         int offset;
7577         gpointer *sp, old_value;
7578         char *bp;
7579         const unsigned char *handler;
7580
7581         /*Decode the first instruction to figure out where did we store the spvar*/
7582         /*Our jit MUST generate the following:
7583          mov    %rsp, ?(%rbp)
7584
7585          Which is encoded as: REX.W 0x89 mod_rm
7586          mod_rm (rsp, rbp, imm) which can be: (imm will never be zero)
7587                 mod (reg + imm8):  01 reg(rsp): 100 rm(rbp): 101 -> 01100101 (0x65)
7588                 mod (reg + imm32): 10 reg(rsp): 100 rm(rbp): 101 -> 10100101 (0xA5)
7589
7590         FIXME can we generate frameless methods on this case?
7591
7592         */
7593         handler = clause->handler_start;
7594
7595         /*REX.W*/
7596         if (*handler != 0x48)
7597                 return NULL;
7598         ++handler;
7599
7600         /*mov r, r/m */
7601         if (*handler != 0x89)
7602                 return NULL;
7603         ++handler;
7604
7605         if (*handler == 0x65)
7606                 offset = *(signed char*)(handler + 1);
7607         else if (*handler == 0xA5)
7608                 offset = *(int*)(handler + 1);
7609         else
7610                 return NULL;
7611
7612         /*Load the spvar*/
7613         bp = MONO_CONTEXT_GET_BP (ctx);
7614         sp = *(gpointer*)(bp + offset);
7615
7616         old_value = *sp;
7617         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
7618                 return old_value;
7619
7620         *sp = new_value;
7621
7622         return old_value;
7623 }
7624
7625 /*
7626  * mono_arch_emit_load_aotconst:
7627  *
7628  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
7629  * TARGET from the mscorlib GOT in full-aot code.
7630  * On AMD64, the result is placed into R11.
7631  */
7632 guint8*
7633 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
7634 {
7635         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
7636         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
7637
7638         return code;
7639 }
7640
7641 /*
7642  * mono_arch_get_trampolines:
7643  *
7644  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
7645  * for AOT.
7646  */
7647 GSList *
7648 mono_arch_get_trampolines (gboolean aot)
7649 {
7650         return mono_amd64_get_exception_trampolines (aot);
7651 }
7652
7653 /* Soft Debug support */
7654 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7655
7656 /*
7657  * mono_arch_set_breakpoint:
7658  *
7659  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7660  * The location should contain code emitted by OP_SEQ_POINT.
7661  */
7662 void
7663 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7664 {
7665         guint8 *code = ip;
7666         guint8 *orig_code = code;
7667
7668         /*
7669          * In production, we will use int3 (has to fix the size in the md
7670          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7671          * instead.
7672          */
7673         g_assert (code [0] == 0x90);
7674         if (breakpoint_size == 8) {
7675                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7676         } else {
7677                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7678                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7679         }
7680
7681         g_assert (code - orig_code == breakpoint_size);
7682 }
7683
7684 /*
7685  * mono_arch_clear_breakpoint:
7686  *
7687  *   Clear the breakpoint at IP.
7688  */
7689 void
7690 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7691 {
7692         guint8 *code = ip;
7693         int i;
7694
7695         for (i = 0; i < breakpoint_size; ++i)
7696                 x86_nop (code);
7697 }
7698
7699 gboolean
7700 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7701 {
7702 #ifdef HOST_WIN32
7703         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7704         return FALSE;
7705 #else
7706         siginfo_t* sinfo = (siginfo_t*) info;
7707         /* Sometimes the address is off by 4 */
7708         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7709                 return TRUE;
7710         else
7711                 return FALSE;
7712 #endif
7713 }
7714
7715 /*
7716  * mono_arch_get_ip_for_breakpoint:
7717  *
7718  *   Convert the ip in CTX to the address where a breakpoint was placed.
7719  */
7720 guint8*
7721 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7722 {
7723         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7724
7725         /* ip points to the instruction causing the fault */
7726         ip -= (breakpoint_size - breakpoint_fault_size);
7727
7728         return ip;
7729 }
7730
7731 /*
7732  * mono_arch_skip_breakpoint:
7733  *
7734  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7735  * we resume, the instruction is not executed again.
7736  */
7737 void
7738 mono_arch_skip_breakpoint (MonoContext *ctx)
7739 {
7740         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7741 }
7742
7743 /*
7744  * mono_arch_start_single_stepping:
7745  *
7746  *   Start single stepping.
7747  */
7748 void
7749 mono_arch_start_single_stepping (void)
7750 {
7751         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7752 }
7753
7754 /*
7755  * mono_arch_stop_single_stepping:
7756  *
7757  *   Stop single stepping.
7758  */
7759 void
7760 mono_arch_stop_single_stepping (void)
7761 {
7762         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7763 }
7764
7765 /*
7766  * mono_arch_is_single_step_event:
7767  *
7768  *   Return whenever the machine state in SIGCTX corresponds to a single
7769  * step event.
7770  */
7771 gboolean
7772 mono_arch_is_single_step_event (void *info, void *sigctx)
7773 {
7774 #ifdef HOST_WIN32
7775         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7776         return FALSE;
7777 #else
7778         siginfo_t* sinfo = (siginfo_t*) info;
7779         /* Sometimes the address is off by 4 */
7780         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7781                 return TRUE;
7782         else
7783                 return FALSE;
7784 #endif
7785 }
7786
7787 /*
7788  * mono_arch_get_ip_for_single_step:
7789  *
7790  *   Convert the ip in CTX to the address stored in seq_points.
7791  */
7792 guint8*
7793 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7794 {
7795         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7796
7797         ip += single_step_fault_size;
7798
7799         return ip;
7800 }
7801
7802 /*
7803  * mono_arch_skip_single_step:
7804  *
7805  *   Modify CTX so the ip is placed after the single step trigger instruction,
7806  * we resume, the instruction is not executed again.
7807  */
7808 void
7809 mono_arch_skip_single_step (MonoContext *ctx)
7810 {
7811         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7812 }
7813
7814 /*
7815  * mono_arch_create_seq_point_info:
7816  *
7817  *   Return a pointer to a data structure which is used by the sequence
7818  * point implementation in AOTed code.
7819  */
7820 gpointer
7821 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7822 {
7823         NOT_IMPLEMENTED;
7824         return NULL;
7825 }
7826
7827 #endif