mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42 static gint thread_tls_offset = -1;
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef PLATFORM_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  66 static CRITICAL_SECTION mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 #ifdef PLATFORM_WIN32
  72 /* On Win64 always reserve first 32 bytes for first four arguments */
  73 #define ARGS_OFFSET 48
  74 #else
  75 #define ARGS_OFFSET 16
  76 #endif
  77 #define GP_SCRATCH_REG AMD64_R11
  78
  79 /*
  80  * AMD64 register usage:
  81  * - callee saved registers are used for global register allocation
  82  * - %r11 is used for materializing 64 bit constants in opcodes
  83  * - the rest is used for local allocation
  84  */
  85
  86 /*
  87  * Floating point comparison results:
  88  *                  ZF PF CF
  89  * A > B            0  0  0
  90  * A < B            0  0  1
  91  * A = B            1  0  0
  92  * A > B            0  0  0
  93  * UNORDERED        1  1  1
  94  */
  95
  96 void mini_emit_memcpy2 (MonoCompile *cfg, int destreg, int doffset, int srcreg, int soffset, int size, int align);
  97
  98 const char*
  99 mono_arch_regname (int reg)
 100 {
 101         switch (reg) {
 102         case AMD64_RAX: return "%rax";
 103         case AMD64_RBX: return "%rbx";
 104         case AMD64_RCX: return "%rcx";
 105         case AMD64_RDX: return "%rdx";
 106         case AMD64_RSP: return "%rsp";
 107         case AMD64_RBP: return "%rbp";
 108         case AMD64_RDI: return "%rdi";
 109         case AMD64_RSI: return "%rsi";
 110         case AMD64_R8: return "%r8";
 111         case AMD64_R9: return "%r9";
 112         case AMD64_R10: return "%r10";
 113         case AMD64_R11: return "%r11";
 114         case AMD64_R12: return "%r12";
 115         case AMD64_R13: return "%r13";
 116         case AMD64_R14: return "%r14";
 117         case AMD64_R15: return "%r15";
 118         }
 119         return "unknown";
 120 }
 121
 122 static const char * xmmregs [] = {
 123         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 124         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 125 };
 126
 127 const char*
 128 mono_arch_fregname (int reg)
 129 {
 130         if (reg < AMD64_XMM_NREG)
 131                 return xmmregs [reg];
 132         else
 133                 return "unknown";
 134 }
 135
 136 G_GNUC_UNUSED static void
 137 break_count (void)
 138 {
 139 }
 140
 141 G_GNUC_UNUSED static gboolean
 142 debug_count (void)
 143 {
 144         static int count = 0;
 145         count ++;
 146
 147         if (!getenv ("COUNT"))
 148                 return TRUE;
 149
 150         if (count == atoi (getenv ("COUNT"))) {
 151                 break_count ();
 152         }
 153
 154         if (count > atoi (getenv ("COUNT"))) {
 155                 return FALSE;
 156         }
 157
 158         return TRUE;
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 static inline void
 182 amd64_patch (unsigned char* code, gpointer target)
 183 {
 184         guint8 rex = 0;
 185
 186         /* Skip REX */
 187         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 188                 rex = code [0];
 189                 code += 1;
 190         }
 191
 192         if ((code [0] & 0xf8) == 0xb8) {
 193                 /* amd64_set_reg_template */
 194                 *(guint64*)(code + 1) = (guint64)target;
 195         }
 196         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 197                 /* mov 0(%rip), %dreg */
 198                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 199         }
 200         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 201                 /* call *<OFFSET>(%rip) */
 202                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 203         }
 204         else if ((code [0] == 0xe8)) {
 205                 /* call <DISP> */
 206                 gint64 disp = (guint8*)target - (guint8*)code;
 207                 g_assert (amd64_is_imm32 (disp));
 208                 x86_patch (code, (unsigned char*)target);
 209         }
 210         else
 211                 x86_patch (code, (unsigned char*)target);
 212 }
 213
 214 void
 215 mono_amd64_patch (unsigned char* code, gpointer target)
 216 {
 217         amd64_patch (code, target);
 218 }
 219
 220 typedef enum {
 221         ArgInIReg,
 222         ArgInFloatSSEReg,
 223         ArgInDoubleSSEReg,
 224         ArgOnStack,
 225         ArgValuetypeInReg,
 226         ArgValuetypeAddrInIReg,
 227         ArgNone /* only in pair_storage */
 228 } ArgStorage;
 229
 230 typedef struct {
 231         gint16 offset;
 232         gint8  reg;
 233         ArgStorage storage;
 234
 235         /* Only if storage == ArgValuetypeInReg */
 236         ArgStorage pair_storage [2];
 237         gint8 pair_regs [2];
 238 } ArgInfo;
 239
 240 typedef struct {
 241         int nargs;
 242         guint32 stack_usage;
 243         guint32 reg_usage;
 244         guint32 freg_usage;
 245         gboolean need_stack_align;
 246         ArgInfo ret;
 247         ArgInfo sig_cookie;
 248         ArgInfo args [1];
 249 } CallInfo;
 250
 251 #define DEBUG(a) if (cfg->verbose_level > 1) a
 252
 253 #define NEW_ICONST(cfg,dest,val) do {   \
 254                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 255                 (dest)->opcode = OP_ICONST;     \
 256                 (dest)->inst_c0 = (val);        \
 257                 (dest)->type = STACK_I4;        \
 258         } while (0)
 259
 260 #ifdef PLATFORM_WIN32
 261 #define PARAM_REGS 4
 262
 263 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 264
 265 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 266 #else
 267 #define PARAM_REGS 6
 268
 269 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 270
 271  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 272 #endif
 273
 274 static void inline
 275 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 276 {
 277     ainfo->offset = *stack_size;
 278
 279     if (*gr >= PARAM_REGS) {
 280                 ainfo->storage = ArgOnStack;
 281                 (*stack_size) += sizeof (gpointer);
 282     }
 283     else {
 284                 ainfo->storage = ArgInIReg;
 285                 ainfo->reg = param_regs [*gr];
 286                 (*gr) ++;
 287     }
 288 }
 289
 290 #ifdef PLATFORM_WIN32
 291 #define FLOAT_PARAM_REGS 4
 292 #else
 293 #define FLOAT_PARAM_REGS 8
 294 #endif
 295
 296 static void inline
 297 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 298 {
 299     ainfo->offset = *stack_size;
 300
 301     if (*gr >= FLOAT_PARAM_REGS) {
 302                 ainfo->storage = ArgOnStack;
 303                 (*stack_size) += sizeof (gpointer);
 304     }
 305     else {
 306                 /* A double register */
 307                 if (is_double)
 308                         ainfo->storage = ArgInDoubleSSEReg;
 309                 else
 310                         ainfo->storage = ArgInFloatSSEReg;
 311                 ainfo->reg = *gr;
 312                 (*gr) += 1;
 313     }
 314 }
 315
 316 typedef enum ArgumentClass {
 317         ARG_CLASS_NO_CLASS,
 318         ARG_CLASS_MEMORY,
 319         ARG_CLASS_INTEGER,
 320         ARG_CLASS_SSE
 321 } ArgumentClass;
 322
 323 static ArgumentClass
 324 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 325 {
 326         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 327         MonoType *ptype;
 328
 329         ptype = mono_type_get_underlying_type (type);
 330         switch (ptype->type) {
 331         case MONO_TYPE_BOOLEAN:
 332         case MONO_TYPE_CHAR:
 333         case MONO_TYPE_I1:
 334         case MONO_TYPE_U1:
 335         case MONO_TYPE_I2:
 336         case MONO_TYPE_U2:
 337         case MONO_TYPE_I4:
 338         case MONO_TYPE_U4:
 339         case MONO_TYPE_I:
 340         case MONO_TYPE_U:
 341         case MONO_TYPE_STRING:
 342         case MONO_TYPE_OBJECT:
 343         case MONO_TYPE_CLASS:
 344         case MONO_TYPE_SZARRAY:
 345         case MONO_TYPE_PTR:
 346         case MONO_TYPE_FNPTR:
 347         case MONO_TYPE_ARRAY:
 348         case MONO_TYPE_I8:
 349         case MONO_TYPE_U8:
 350                 class2 = ARG_CLASS_INTEGER;
 351                 break;
 352         case MONO_TYPE_R4:
 353         case MONO_TYPE_R8:
 354 #ifdef PLATFORM_WIN32
 355                 class2 = ARG_CLASS_INTEGER;
 356 #else
 357                 class2 = ARG_CLASS_SSE;
 358 #endif
 359                 break;
 360
 361         case MONO_TYPE_TYPEDBYREF:
 362                 g_assert_not_reached ();
 363
 364         case MONO_TYPE_GENERICINST:
 365                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 366                         class2 = ARG_CLASS_INTEGER;
 367                         break;
 368                 }
 369                 /* fall through */
 370         case MONO_TYPE_VALUETYPE: {
 371                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 372                 int i;
 373
 374                 for (i = 0; i < info->num_fields; ++i) {
 375                         class2 = class1;
 376                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 377                 }
 378                 break;
 379         }
 380         default:
 381                 g_assert_not_reached ();
 382         }
 383
 384         /* Merge */
 385         if (class1 == class2)
 386                 ;
 387         else if (class1 == ARG_CLASS_NO_CLASS)
 388                 class1 = class2;
 389         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 390                 class1 = ARG_CLASS_MEMORY;
 391         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 392                 class1 = ARG_CLASS_INTEGER;
 393         else
 394                 class1 = ARG_CLASS_SSE;
 395
 396         return class1;
 397 }
 398
 399 static void
 400 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 401                gboolean is_return,
 402                guint32 *gr, guint32 *fr, guint32 *stack_size)
 403 {
 404         guint32 size, quad, nquads, i;
 405         ArgumentClass args [2];
 406         MonoMarshalType *info;
 407         MonoClass *klass;
 408
 409         klass = mono_class_from_mono_type (type);
 410         if (sig->pinvoke)
 411                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 412         else
 413                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 414 #ifndef PLATFORM_WIN32
 415         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 416                 /* We pass and return vtypes of size 8 in a register */
 417         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 418 #else
 419         if (!sig->pinvoke) {
 420 #endif
 421                 /* Allways pass in memory */
 422                 ainfo->offset = *stack_size;
 423                 *stack_size += ALIGN_TO (size, 8);
 424                 ainfo->storage = ArgOnStack;
 425
 426                 return;
 427         }
 428
 429         /* FIXME: Handle structs smaller than 8 bytes */
 430         //if ((size % 8) != 0)
 431         //      NOT_IMPLEMENTED;
 432
 433         if (size > 8)
 434                 nquads = 2;
 435         else
 436                 nquads = 1;
 437
 438         if (!sig->pinvoke) {
 439                 /* Always pass in 1 or 2 integer registers */
 440                 args [0] = ARG_CLASS_INTEGER;
 441                 args [1] = ARG_CLASS_INTEGER;
 442                 /* Only the simplest cases are supported */
 443                 if (is_return && nquads != 1) {
 444                         args [0] = ARG_CLASS_MEMORY;
 445                         args [1] = ARG_CLASS_MEMORY;
 446                 }
 447         } else {
 448                 /*
 449                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 450                  * The X87 and SSEUP stuff is left out since there are no such types in
 451                  * the CLR.
 452                  */
 453                 info = mono_marshal_load_type_info (klass);
 454                 g_assert (info);
 455
 456 #ifndef PLATFORM_WIN32
 457                 if (info->native_size > 16) {
 458                         ainfo->offset = *stack_size;
 459                         *stack_size += ALIGN_TO (info->native_size, 8);
 460                         ainfo->storage = ArgOnStack;
 461
 462                         return;
 463                 }
 464 #else
 465                 switch (info->native_size) {
 466                 case 1: case 2: case 4: case 8:
 467                         break;
 468                 default:
 469                         if (is_return) {
 470                                 ainfo->storage = ArgOnStack;
 471                                 ainfo->offset = *stack_size;
 472                                 *stack_size += ALIGN_TO (info->native_size, 8);
 473                         }
 474                         else {
 475                                 ainfo->storage = ArgValuetypeAddrInIReg;
 476
 477                                 if (*gr < PARAM_REGS) {
 478                                         ainfo->pair_storage [0] = ArgInIReg;
 479                                         ainfo->pair_regs [0] = param_regs [*gr];
 480                                         (*gr) ++;
 481                                 }
 482                                 else {
 483                                         ainfo->pair_storage [0] = ArgOnStack;
 484                                         ainfo->offset = *stack_size;
 485                                         *stack_size += 8;
 486                                 }
 487                         }
 488
 489                         return;
 490                 }
 491 #endif
 492
 493                 args [0] = ARG_CLASS_NO_CLASS;
 494                 args [1] = ARG_CLASS_NO_CLASS;
 495                 for (quad = 0; quad < nquads; ++quad) {
 496                         int size;
 497                         guint32 align;
 498                         ArgumentClass class1;
 499
 500                         if (info->num_fields == 0)
 501                                 class1 = ARG_CLASS_MEMORY;
 502                         else
 503                                 class1 = ARG_CLASS_NO_CLASS;
 504                         for (i = 0; i < info->num_fields; ++i) {
 505                                 size = mono_marshal_type_size (info->fields [i].field->type,
 506                                                                                            info->fields [i].mspec,
 507                                                                                            &align, TRUE, klass->unicode);
 508                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 509                                         /* Unaligned field */
 510                                         NOT_IMPLEMENTED;
 511                                 }
 512
 513                                 /* Skip fields in other quad */
 514                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 515                                         continue;
 516                                 if ((quad == 1) && (info->fields [i].offset < 8))
 517                                         continue;
 518
 519                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 520                         }
 521                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 522                         args [quad] = class1;
 523                 }
 524         }
 525
 526         /* Post merger cleanup */
 527         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 528                 args [0] = args [1] = ARG_CLASS_MEMORY;
 529
 530         /* Allocate registers */
 531         {
 532                 int orig_gr = *gr;
 533                 int orig_fr = *fr;
 534
 535                 ainfo->storage = ArgValuetypeInReg;
 536                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 537                 for (quad = 0; quad < nquads; ++quad) {
 538                         switch (args [quad]) {
 539                         case ARG_CLASS_INTEGER:
 540                                 if (*gr >= PARAM_REGS)
 541                                         args [quad] = ARG_CLASS_MEMORY;
 542                                 else {
 543                                         ainfo->pair_storage [quad] = ArgInIReg;
 544                                         if (is_return)
 545                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 546                                         else
 547                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 548                                         (*gr) ++;
 549                                 }
 550                                 break;
 551                         case ARG_CLASS_SSE:
 552                                 if (*fr >= FLOAT_PARAM_REGS)
 553                                         args [quad] = ARG_CLASS_MEMORY;
 554                                 else {
 555                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 556                                         ainfo->pair_regs [quad] = *fr;
 557                                         (*fr) ++;
 558                                 }
 559                                 break;
 560                         case ARG_CLASS_MEMORY:
 561                                 break;
 562                         default:
 563                                 g_assert_not_reached ();
 564                         }
 565                 }
 566
 567                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 568                         /* Revert possible register assignments */
 569                         *gr = orig_gr;
 570                         *fr = orig_fr;
 571
 572                         ainfo->offset = *stack_size;
 573                         if (sig->pinvoke)
 574                                 *stack_size += ALIGN_TO (info->native_size, 8);
 575                         else
 576                                 *stack_size += nquads * sizeof (gpointer);
 577                         ainfo->storage = ArgOnStack;
 578                 }
 579         }
 580 }
 581
 582 /*
 583  * get_call_info:
 584  *
 585  *  Obtain information about a call according to the calling convention.
 586  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 587  * Draft Version 0.23" document for more information.
 588  */
 589 static CallInfo*
 590 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 591 {
 592         guint32 i, gr, fr;
 593         MonoType *ret_type;
 594         int n = sig->hasthis + sig->param_count;
 595         guint32 stack_size = 0;
 596         CallInfo *cinfo;
 597
 598         if (mp)
 599                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 600         else
 601                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 602
 603         gr = 0;
 604         fr = 0;
 605
 606         /* return value */
 607         {
 608                 ret_type = mono_type_get_underlying_type (sig->ret);
 609                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 610                 switch (ret_type->type) {
 611                 case MONO_TYPE_BOOLEAN:
 612                 case MONO_TYPE_I1:
 613                 case MONO_TYPE_U1:
 614                 case MONO_TYPE_I2:
 615                 case MONO_TYPE_U2:
 616                 case MONO_TYPE_CHAR:
 617                 case MONO_TYPE_I4:
 618                 case MONO_TYPE_U4:
 619                 case MONO_TYPE_I:
 620                 case MONO_TYPE_U:
 621                 case MONO_TYPE_PTR:
 622                 case MONO_TYPE_FNPTR:
 623                 case MONO_TYPE_CLASS:
 624                 case MONO_TYPE_OBJECT:
 625                 case MONO_TYPE_SZARRAY:
 626                 case MONO_TYPE_ARRAY:
 627                 case MONO_TYPE_STRING:
 628                         cinfo->ret.storage = ArgInIReg;
 629                         cinfo->ret.reg = AMD64_RAX;
 630                         break;
 631                 case MONO_TYPE_U8:
 632                 case MONO_TYPE_I8:
 633                         cinfo->ret.storage = ArgInIReg;
 634                         cinfo->ret.reg = AMD64_RAX;
 635                         break;
 636                 case MONO_TYPE_R4:
 637                         cinfo->ret.storage = ArgInFloatSSEReg;
 638                         cinfo->ret.reg = AMD64_XMM0;
 639                         break;
 640                 case MONO_TYPE_R8:
 641                         cinfo->ret.storage = ArgInDoubleSSEReg;
 642                         cinfo->ret.reg = AMD64_XMM0;
 643                         break;
 644                 case MONO_TYPE_GENERICINST:
 645                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 646                                 cinfo->ret.storage = ArgInIReg;
 647                                 cinfo->ret.reg = AMD64_RAX;
 648                                 break;
 649                         }
 650                         /* fall through */
 651                 case MONO_TYPE_VALUETYPE: {
 652                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 653
 654                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 655                         if (cinfo->ret.storage == ArgOnStack)
 656                                 /* The caller passes the address where the value is stored */
 657                                 add_general (&gr, &stack_size, &cinfo->ret);
 658                         break;
 659                 }
 660                 case MONO_TYPE_TYPEDBYREF:
 661                         /* Same as a valuetype with size 24 */
 662                         add_general (&gr, &stack_size, &cinfo->ret);
 663                         ;
 664                         break;
 665                 case MONO_TYPE_VOID:
 666                         break;
 667                 default:
 668                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 669                 }
 670         }
 671
 672         /* this */
 673         if (sig->hasthis)
 674                 add_general (&gr, &stack_size, cinfo->args + 0);
 675
 676         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 677                 gr = PARAM_REGS;
 678                 fr = FLOAT_PARAM_REGS;
 679
 680                 /* Emit the signature cookie just before the implicit arguments */
 681                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 682         }
 683
 684         for (i = 0; i < sig->param_count; ++i) {
 685                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 686                 MonoType *ptype;
 687
 688 #ifdef PLATFORM_WIN32
 689                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 690                 if (gr > fr)
 691                         fr = gr;
 692                 else if (fr > gr)
 693                         gr = fr;
 694 #endif
 695
 696                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 697                         /* We allways pass the sig cookie on the stack for simplicity */
 698                         /*
 699                          * Prevent implicit arguments + the sig cookie from being passed
 700                          * in registers.
 701                          */
 702                         gr = PARAM_REGS;
 703                         fr = FLOAT_PARAM_REGS;
 704
 705                         /* Emit the signature cookie just before the implicit arguments */
 706                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 707                 }
 708
 709                 if (sig->params [i]->byref) {
 710                         add_general (&gr, &stack_size, ainfo);
 711                         continue;
 712                 }
 713                 ptype = mono_type_get_underlying_type (sig->params [i]);
 714                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 715                 switch (ptype->type) {
 716                 case MONO_TYPE_BOOLEAN:
 717                 case MONO_TYPE_I1:
 718                 case MONO_TYPE_U1:
 719                         add_general (&gr, &stack_size, ainfo);
 720                         break;
 721                 case MONO_TYPE_I2:
 722                 case MONO_TYPE_U2:
 723                 case MONO_TYPE_CHAR:
 724                         add_general (&gr, &stack_size, ainfo);
 725                         break;
 726                 case MONO_TYPE_I4:
 727                 case MONO_TYPE_U4:
 728                         add_general (&gr, &stack_size, ainfo);
 729                         break;
 730                 case MONO_TYPE_I:
 731                 case MONO_TYPE_U:
 732                 case MONO_TYPE_PTR:
 733                 case MONO_TYPE_FNPTR:
 734                 case MONO_TYPE_CLASS:
 735                 case MONO_TYPE_OBJECT:
 736                 case MONO_TYPE_STRING:
 737                 case MONO_TYPE_SZARRAY:
 738                 case MONO_TYPE_ARRAY:
 739                         add_general (&gr, &stack_size, ainfo);
 740                         break;
 741                 case MONO_TYPE_GENERICINST:
 742                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 743                                 add_general (&gr, &stack_size, ainfo);
 744                                 break;
 745                         }
 746                         /* fall through */
 747                 case MONO_TYPE_VALUETYPE:
 748                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 749                         break;
 750                 case MONO_TYPE_TYPEDBYREF:
 751 #ifdef PLATFORM_WIN32
 752                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 753 #else
 754                         stack_size += sizeof (MonoTypedRef);
 755                         ainfo->storage = ArgOnStack;
 756 #endif
 757                         break;
 758                 case MONO_TYPE_U8:
 759                 case MONO_TYPE_I8:
 760                         add_general (&gr, &stack_size, ainfo);
 761                         break;
 762                 case MONO_TYPE_R4:
 763                         add_float (&fr, &stack_size, ainfo, FALSE);
 764                         break;
 765                 case MONO_TYPE_R8:
 766                         add_float (&fr, &stack_size, ainfo, TRUE);
 767                         break;
 768                 default:
 769                         g_assert_not_reached ();
 770                 }
 771         }
 772
 773         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 774                 gr = PARAM_REGS;
 775                 fr = FLOAT_PARAM_REGS;
 776
 777                 /* Emit the signature cookie just before the implicit arguments */
 778                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 779         }
 780
 781 #ifdef PLATFORM_WIN32
 782         // There always is 32 bytes reserved on the stack when calling on Winx64
 783         stack_size += 0x20;
 784 #endif
 785
 786         if (stack_size & 0x8) {
 787                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 788                 cinfo->need_stack_align = TRUE;
 789                 stack_size += 8;
 790         }
 791
 792         cinfo->stack_usage = stack_size;
 793         cinfo->reg_usage = gr;
 794         cinfo->freg_usage = fr;
 795         return cinfo;
 796 }
 797
 798 /*
 799  * mono_arch_get_argument_info:
 800  * @csig:  a method signature
 801  * @param_count: the number of parameters to consider
 802  * @arg_info: an array to store the result infos
 803  *
 804  * Gathers information on parameters such as size, alignment and
 805  * padding. arg_info should be large enought to hold param_count + 1 entries.
 806  *
 807  * Returns the size of the argument area on the stack.
 808  */
 809 int
 810 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 811 {
 812         int k;
 813         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 814         guint32 args_size = cinfo->stack_usage;
 815
 816         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 817         if (csig->hasthis) {
 818                 arg_info [0].offset = 0;
 819         }
 820
 821         for (k = 0; k < param_count; k++) {
 822                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 823                 /* FIXME: */
 824                 arg_info [k + 1].size = 0;
 825         }
 826
 827         g_free (cinfo);
 828
 829         return args_size;
 830 }
 831
 832 static int
 833 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 834 {
 835 #ifndef _MSC_VER
 836         __asm__ __volatile__ ("cpuid"
 837                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 838                 : "a" (id));
 839 #else
 840         int info[4];
 841         __cpuid(info, id);
 842         *p_eax = info[0];
 843         *p_ebx = info[1];
 844         *p_ecx = info[2];
 845         *p_edx = info[3];
 846 #endif
 847         return 1;
 848 }
 849
 850 /*
 851  * Initialize the cpu to execute managed code.
 852  */
 853 void
 854 mono_arch_cpu_init (void)
 855 {
 856 #ifndef _MSC_VER
 857         guint16 fpcw;
 858
 859         /* spec compliance requires running with double precision */
 860         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 861         fpcw &= ~X86_FPCW_PRECC_MASK;
 862         fpcw |= X86_FPCW_PREC_DOUBLE;
 863         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 864         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 865 #else
 866         /* TODO: This is crashing on Win64 right now.
 867         * _control87 (_PC_53, MCW_PC);
 868         */
 869 #endif
 870 }
 871
 872 /*
 873  * Initialize architecture specific code.
 874  */
 875 void
 876 mono_arch_init (void)
 877 {
 878         InitializeCriticalSection (&mini_arch_mutex);
 879 }
 880
 881 /*
 882  * Cleanup architecture specific code.
 883  */
 884 void
 885 mono_arch_cleanup (void)
 886 {
 887         DeleteCriticalSection (&mini_arch_mutex);
 888 }
 889
 890 /*
 891  * This function returns the optimizations supported on this cpu.
 892  */
 893 guint32
 894 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 895 {
 896         int eax, ebx, ecx, edx;
 897         guint32 opts = 0;
 898
 899         /* FIXME: AMD64 */
 900
 901         *exclude_mask = 0;
 902         /* Feature Flags function, flags returned in EDX. */
 903         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 904                 if (edx & (1 << 15)) {
 905                         opts |= MONO_OPT_CMOV;
 906                         if (edx & 1)
 907                                 opts |= MONO_OPT_FCMOV;
 908                         else
 909                                 *exclude_mask |= MONO_OPT_FCMOV;
 910                 } else
 911                         *exclude_mask |= MONO_OPT_CMOV;
 912         }
 913 #ifdef PLATFORM_WIN32
 914         /* FIXME */
 915         *exclude_mask |= (MONO_OPT_PEEPHOLE | MONO_OPT_BRANCH);
 916 #endif
 917         return opts;
 918 }
 919
 920 GList *
 921 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 922 {
 923         GList *vars = NULL;
 924         int i;
 925
 926         for (i = 0; i < cfg->num_varinfo; i++) {
 927                 MonoInst *ins = cfg->varinfo [i];
 928                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 929
 930                 /* unused vars */
 931                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 932                         continue;
 933
 934                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 935                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 936                         continue;
 937
 938                 if (mono_is_regsize_var (ins->inst_vtype)) {
 939                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 940                         g_assert (i == vmv->idx);
 941                         vars = g_list_prepend (vars, vmv);
 942                 }
 943         }
 944
 945         vars = mono_varlist_sort (cfg, vars, 0);
 946
 947         return vars;
 948 }
 949
 950 /**
 951  * mono_arch_compute_omit_fp:
 952  *
 953  *   Determine whenever the frame pointer can be eliminated.
 954  */
 955 static void
 956 mono_arch_compute_omit_fp (MonoCompile *cfg)
 957 {
 958         MonoMethodSignature *sig;
 959         MonoMethodHeader *header;
 960         int i, locals_size;
 961         CallInfo *cinfo;
 962
 963         if (cfg->arch.omit_fp_computed)
 964                 return;
 965
 966         header = mono_method_get_header (cfg->method);
 967
 968         sig = mono_method_signature (cfg->method);
 969
 970         if (!cfg->arch.cinfo)
 971                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
 972         cinfo = cfg->arch.cinfo;
 973
 974         /*
 975          * FIXME: Remove some of the restrictions.
 976          */
 977         cfg->arch.omit_fp = TRUE;
 978         cfg->arch.omit_fp_computed = TRUE;
 979
 980         if (cfg->disable_omit_fp)
 981                 cfg->arch.omit_fp = FALSE;
 982
 983         if (!debug_omit_fp ())
 984                 cfg->arch.omit_fp = FALSE;
 985         /*
 986         if (cfg->method->save_lmf)
 987                 cfg->arch.omit_fp = FALSE;
 988         */
 989         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 990                 cfg->arch.omit_fp = FALSE;
 991         if (header->num_clauses)
 992                 cfg->arch.omit_fp = FALSE;
 993         if (cfg->param_area)
 994                 cfg->arch.omit_fp = FALSE;
 995         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 996                 cfg->arch.omit_fp = FALSE;
 997         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 998                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 999                 cfg->arch.omit_fp = FALSE;
1000         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1001                 ArgInfo *ainfo = &cinfo->args [i];
1002
1003                 if (ainfo->storage == ArgOnStack) {
1004                         /*
1005                          * The stack offset can only be determined when the frame
1006                          * size is known.
1007                          */
1008                         cfg->arch.omit_fp = FALSE;
1009                 }
1010         }
1011
1012         locals_size = 0;
1013         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1014                 MonoInst *ins = cfg->varinfo [i];
1015                 int ialign;
1016
1017                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1018         }
1019
1020         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1021                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1022                 cfg->arch.omit_fp = FALSE;
1023         }
1024 }
1025
1026 GList *
1027 mono_arch_get_global_int_regs (MonoCompile *cfg)
1028 {
1029         GList *regs = NULL;
1030
1031         mono_arch_compute_omit_fp (cfg);
1032
1033         if (cfg->globalra) {
1034                 if (cfg->arch.omit_fp)
1035                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1036
1037                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1038                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1039                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1040                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1041                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1042
1043                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1044                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1045                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1046                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1047                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1048                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1049                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1050                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1051         } else {
1052                 if (cfg->arch.omit_fp)
1053                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1054
1055                 /* We use the callee saved registers for global allocation */
1056                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1057                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1058                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1059                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1060                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1061         }
1062
1063         return regs;
1064 }
1065
1066 GList*
1067 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1068 {
1069         GList *regs = NULL;
1070         int i;
1071
1072         /* All XMM registers */
1073         for (i = 0; i < 16; ++i)
1074                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1075
1076         return regs;
1077 }
1078
1079 GList*
1080 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1081 {
1082         static GList *r = NULL;
1083
1084         if (r == NULL) {
1085                 GList *regs = NULL;
1086
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1093
1094                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1095                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1096                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1097                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1099                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1101                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1102
1103                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1104         }
1105
1106         return r;
1107 }
1108
1109 GList*
1110 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1111 {
1112         int i;
1113         static GList *r = NULL;
1114
1115         if (r == NULL) {
1116                 GList *regs = NULL;
1117
1118                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1119                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1120
1121                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1122         }
1123
1124         return r;
1125 }
1126
1127 /*
1128  * mono_arch_regalloc_cost:
1129  *
1130  *  Return the cost, in number of memory references, of the action of
1131  * allocating the variable VMV into a register during global register
1132  * allocation.
1133  */
1134 guint32
1135 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1136 {
1137         MonoInst *ins = cfg->varinfo [vmv->idx];
1138
1139         if (cfg->method->save_lmf)
1140                 /* The register is already saved */
1141                 /* substract 1 for the invisible store in the prolog */
1142                 return (ins->opcode == OP_ARG) ? 0 : 1;
1143         else
1144                 /* push+pop */
1145                 return (ins->opcode == OP_ARG) ? 1 : 2;
1146 }
1147
1148 /*
1149  * mono_arch_fill_argument_info:
1150  *
1151  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1152  * of the method.
1153  */
1154 void
1155 mono_arch_fill_argument_info (MonoCompile *cfg)
1156 {
1157         MonoMethodSignature *sig;
1158         MonoMethodHeader *header;
1159         MonoInst *ins;
1160         int i;
1161         CallInfo *cinfo;
1162
1163         header = mono_method_get_header (cfg->method);
1164
1165         sig = mono_method_signature (cfg->method);
1166
1167         cinfo = cfg->arch.cinfo;
1168
1169         /*
1170          * Contrary to mono_arch_allocate_vars (), the information should describe
1171          * where the arguments are at the beginning of the method, not where they can be
1172          * accessed during the execution of the method. The later makes no sense for the
1173          * global register allocator, since a variable can be in more than one location.
1174          */
1175         if (sig->ret->type != MONO_TYPE_VOID) {
1176                 switch (cinfo->ret.storage) {
1177                 case ArgInIReg:
1178                 case ArgInFloatSSEReg:
1179                 case ArgInDoubleSSEReg:
1180                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1181                                 cfg->vret_addr->opcode = OP_REGVAR;
1182                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1183                         }
1184                         else {
1185                                 cfg->ret->opcode = OP_REGVAR;
1186                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1187                         }
1188                         break;
1189                 case ArgValuetypeInReg:
1190                         cfg->ret->opcode = OP_REGOFFSET;
1191                         cfg->ret->inst_basereg = -1;
1192                         cfg->ret->inst_offset = -1;
1193                         break;
1194                 default:
1195                         g_assert_not_reached ();
1196                 }
1197         }
1198
1199         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1200                 ArgInfo *ainfo = &cinfo->args [i];
1201                 MonoType *arg_type;
1202
1203                 ins = cfg->args [i];
1204
1205                 if (sig->hasthis && (i == 0))
1206                         arg_type = &mono_defaults.object_class->byval_arg;
1207                 else
1208                         arg_type = sig->params [i - sig->hasthis];
1209
1210                 switch (ainfo->storage) {
1211                 case ArgInIReg:
1212                 case ArgInFloatSSEReg:
1213                 case ArgInDoubleSSEReg:
1214                         ins->opcode = OP_REGVAR;
1215                         ins->inst_c0 = ainfo->reg;
1216                         break;
1217                 case ArgOnStack:
1218                         ins->opcode = OP_REGOFFSET;
1219                         ins->inst_basereg = -1;
1220                         ins->inst_offset = -1;
1221                         break;
1222                 case ArgValuetypeInReg:
1223                         /* Dummy */
1224                         ins->opcode = OP_NOP;
1225                         break;
1226                 default:
1227                         g_assert_not_reached ();
1228                 }
1229         }
1230 }
1231
1232 void
1233 mono_arch_allocate_vars (MonoCompile *cfg)
1234 {
1235         MonoMethodSignature *sig;
1236         MonoMethodHeader *header;
1237         MonoInst *ins;
1238         int i, offset;
1239         guint32 locals_stack_size, locals_stack_align;
1240         gint32 *offsets;
1241         CallInfo *cinfo;
1242
1243         header = mono_method_get_header (cfg->method);
1244
1245         sig = mono_method_signature (cfg->method);
1246
1247         cinfo = cfg->arch.cinfo;
1248
1249         mono_arch_compute_omit_fp (cfg);
1250
1251         /*
1252          * We use the ABI calling conventions for managed code as well.
1253          * Exception: valuetypes are never passed or returned in registers.
1254          */
1255
1256         if (cfg->arch.omit_fp) {
1257                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1258                 cfg->frame_reg = AMD64_RSP;
1259                 offset = 0;
1260         } else {
1261                 /* Locals are allocated backwards from %fp */
1262                 cfg->frame_reg = AMD64_RBP;
1263                 offset = 0;
1264         }
1265
1266         if (cfg->method->save_lmf) {
1267                 /* Reserve stack space for saving LMF */
1268                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1269                 g_assert (offset == 0);
1270                 if (cfg->arch.omit_fp) {
1271                         cfg->arch.lmf_offset = offset;
1272                         offset += sizeof (MonoLMF);
1273                 }
1274                 else {
1275                         offset += sizeof (MonoLMF);
1276                         cfg->arch.lmf_offset = -offset;
1277                 }
1278         } else {
1279                 if (cfg->arch.omit_fp)
1280                         cfg->arch.reg_save_area_offset = offset;
1281                 /* Reserve space for caller saved registers */
1282                 for (i = 0; i < AMD64_NREG; ++i)
1283                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1284                                 offset += sizeof (gpointer);
1285                         }
1286         }
1287
1288         if (sig->ret->type != MONO_TYPE_VOID) {
1289                 switch (cinfo->ret.storage) {
1290                 case ArgInIReg:
1291                 case ArgInFloatSSEReg:
1292                 case ArgInDoubleSSEReg:
1293                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1294                                 if (cfg->globalra) {
1295                                         cfg->vret_addr->opcode = OP_REGVAR;
1296                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1297                                 } else {
1298                                         /* The register is volatile */
1299                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1300                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1301                                         if (cfg->arch.omit_fp) {
1302                                                 cfg->vret_addr->inst_offset = offset;
1303                                                 offset += 8;
1304                                         } else {
1305                                                 offset += 8;
1306                                                 cfg->vret_addr->inst_offset = -offset;
1307                                         }
1308                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1309                                                 printf ("vret_addr =");
1310                                                 mono_print_ins (cfg->vret_addr);
1311                                         }
1312                                 }
1313                         }
1314                         else {
1315                                 cfg->ret->opcode = OP_REGVAR;
1316                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1317                         }
1318                         break;
1319                 case ArgValuetypeInReg:
1320                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1321                         cfg->ret->opcode = OP_REGOFFSET;
1322                         cfg->ret->inst_basereg = cfg->frame_reg;
1323                         if (cfg->arch.omit_fp) {
1324                                 cfg->ret->inst_offset = offset;
1325                                 offset += 16;
1326                         } else {
1327                                 offset += 16;
1328                                 cfg->ret->inst_offset = - offset;
1329                         }
1330                         break;
1331                 default:
1332                         g_assert_not_reached ();
1333                 }
1334                 if (!cfg->globalra)
1335                         cfg->ret->dreg = cfg->ret->inst_c0;
1336         }
1337
1338         /* Allocate locals */
1339         if (!cfg->globalra) {
1340                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1341                 if (locals_stack_align) {
1342                         offset += (locals_stack_align - 1);
1343                         offset &= ~(locals_stack_align - 1);
1344                 }
1345                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1346                         if (offsets [i] != -1) {
1347                                 MonoInst *ins = cfg->varinfo [i];
1348                                 ins->opcode = OP_REGOFFSET;
1349                                 ins->inst_basereg = cfg->frame_reg;
1350                                 if (cfg->arch.omit_fp)
1351                                         ins->inst_offset = (offset + offsets [i]);
1352                                 else
1353                                         ins->inst_offset = - (offset + offsets [i]);
1354                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1355                         }
1356                 }
1357                 offset += locals_stack_size;
1358         }
1359
1360         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1361                 g_assert (!cfg->arch.omit_fp);
1362                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1363                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1364         }
1365
1366         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1367                 ins = cfg->args [i];
1368                 if (ins->opcode != OP_REGVAR) {
1369                         ArgInfo *ainfo = &cinfo->args [i];
1370                         gboolean inreg = TRUE;
1371                         MonoType *arg_type;
1372
1373                         if (sig->hasthis && (i == 0))
1374                                 arg_type = &mono_defaults.object_class->byval_arg;
1375                         else
1376                                 arg_type = sig->params [i - sig->hasthis];
1377
1378                         if (cfg->globalra) {
1379                                 /* The new allocator needs info about the original locations of the arguments */
1380                                 switch (ainfo->storage) {
1381                                 case ArgInIReg:
1382                                 case ArgInFloatSSEReg:
1383                                 case ArgInDoubleSSEReg:
1384                                         ins->opcode = OP_REGVAR;
1385                                         ins->inst_c0 = ainfo->reg;
1386                                         break;
1387                                 case ArgOnStack:
1388                                         g_assert (!cfg->arch.omit_fp);
1389                                         ins->opcode = OP_REGOFFSET;
1390                                         ins->inst_basereg = cfg->frame_reg;
1391                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1392                                         break;
1393                                 case ArgValuetypeInReg:
1394                                         ins->opcode = OP_REGOFFSET;
1395                                         ins->inst_basereg = cfg->frame_reg;
1396                                         /* These arguments are saved to the stack in the prolog */
1397                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1398                                         if (cfg->arch.omit_fp) {
1399                                                 ins->inst_offset = offset;
1400                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1401                                         } else {
1402                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1403                                                 ins->inst_offset = - offset;
1404                                         }
1405                                         break;
1406                                 default:
1407                                         g_assert_not_reached ();
1408                                 }
1409
1410                                 continue;
1411                         }
1412
1413                         /* FIXME: Allocate volatile arguments to registers */
1414                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1415                                 inreg = FALSE;
1416
1417                         /*
1418                          * Under AMD64, all registers used to pass arguments to functions
1419                          * are volatile across calls.
1420                          * FIXME: Optimize this.
1421                          */
1422                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1423                                 inreg = FALSE;
1424
1425                         ins->opcode = OP_REGOFFSET;
1426
1427                         switch (ainfo->storage) {
1428                         case ArgInIReg:
1429                         case ArgInFloatSSEReg:
1430                         case ArgInDoubleSSEReg:
1431                                 if (inreg) {
1432                                         ins->opcode = OP_REGVAR;
1433                                         ins->dreg = ainfo->reg;
1434                                 }
1435                                 break;
1436                         case ArgOnStack:
1437                                 g_assert (!cfg->arch.omit_fp);
1438                                 ins->opcode = OP_REGOFFSET;
1439                                 ins->inst_basereg = cfg->frame_reg;
1440                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1441                                 break;
1442                         case ArgValuetypeInReg:
1443                                 break;
1444                         case ArgValuetypeAddrInIReg: {
1445                                 MonoInst *indir;
1446                                 g_assert (!cfg->arch.omit_fp);
1447
1448                                 MONO_INST_NEW (cfg, indir, 0);
1449                                 indir->opcode = OP_REGOFFSET;
1450                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1451                                         indir->inst_basereg = cfg->frame_reg;
1452                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1453                                         offset += (sizeof (gpointer));
1454                                         indir->inst_offset = - offset;
1455                                 }
1456                                 else {
1457                                         indir->inst_basereg = cfg->frame_reg;
1458                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1459                                 }
1460
1461                                 ins->opcode = OP_VTARG_ADDR;
1462                                 ins->inst_left = indir;
1463
1464                                 break;
1465                         }
1466                         default:
1467                                 NOT_IMPLEMENTED;
1468                         }
1469
1470                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1471                                 ins->opcode = OP_REGOFFSET;
1472                                 ins->inst_basereg = cfg->frame_reg;
1473                                 /* These arguments are saved to the stack in the prolog */
1474                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1475                                 if (cfg->arch.omit_fp) {
1476                                         ins->inst_offset = offset;
1477                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1478                                 } else {
1479                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1480                                         ins->inst_offset = - offset;
1481                                 }
1482                         }
1483                 }
1484         }
1485
1486         cfg->stack_offset = offset;
1487 }
1488
1489 void
1490 mono_arch_create_vars (MonoCompile *cfg)
1491 {
1492         MonoMethodSignature *sig;
1493         CallInfo *cinfo;
1494
1495         sig = mono_method_signature (cfg->method);
1496
1497         if (!cfg->arch.cinfo)
1498                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1499         cinfo = cfg->arch.cinfo;
1500
1501         if (cinfo->ret.storage == ArgValuetypeInReg)
1502                 cfg->ret_var_is_local = TRUE;
1503
1504         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1505                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1506                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1507                         printf ("vret_addr = ");
1508                         mono_print_ins (cfg->vret_addr);
1509                 }
1510         }
1511 }
1512
1513 static void
1514 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1515 {
1516         switch (storage) {
1517         case ArgInIReg:
1518                 arg->opcode = OP_OUTARG_REG;
1519                 arg->inst_left = tree;
1520                 arg->inst_call = call;
1521                 arg->backend.reg3 = reg;
1522                 break;
1523         case ArgInFloatSSEReg:
1524                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1525                 arg->inst_left = tree;
1526                 arg->inst_call = call;
1527                 arg->backend.reg3 = reg;
1528                 break;
1529         case ArgInDoubleSSEReg:
1530                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1531                 arg->inst_left = tree;
1532                 arg->inst_call = call;
1533                 arg->backend.reg3 = reg;
1534                 break;
1535         default:
1536                 g_assert_not_reached ();
1537         }
1538 }
1539
1540 static void
1541 add_outarg_reg2 (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1542 {
1543         MonoInst *ins;
1544
1545         switch (storage) {
1546         case ArgInIReg:
1547                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1548                 ins->dreg = mono_alloc_ireg (cfg);
1549                 ins->sreg1 = tree->dreg;
1550                 MONO_ADD_INS (cfg->cbb, ins);
1551                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1552                 break;
1553         case ArgInFloatSSEReg:
1554                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1555                 ins->dreg = mono_alloc_freg (cfg);
1556                 ins->sreg1 = tree->dreg;
1557                 MONO_ADD_INS (cfg->cbb, ins);
1558
1559                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1560                 break;
1561         case ArgInDoubleSSEReg:
1562                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1563                 ins->dreg = mono_alloc_freg (cfg);
1564                 ins->sreg1 = tree->dreg;
1565                 MONO_ADD_INS (cfg->cbb, ins);
1566
1567                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1568
1569                 break;
1570         default:
1571                 g_assert_not_reached ();
1572         }
1573 }
1574
1575 static int
1576 arg_storage_to_ldind (ArgStorage storage)
1577 {
1578         switch (storage) {
1579         case ArgInIReg:
1580                 return CEE_LDIND_I;
1581         case ArgInDoubleSSEReg:
1582                 return CEE_LDIND_R8;
1583         case ArgInFloatSSEReg:
1584                 return CEE_LDIND_R4;
1585         default:
1586                 g_assert_not_reached ();
1587         }
1588
1589         return -1;
1590 }
1591
1592 static int
1593 arg_storage_to_load_membase (ArgStorage storage)
1594 {
1595         switch (storage) {
1596         case ArgInIReg:
1597                 return OP_LOAD_MEMBASE;
1598         case ArgInDoubleSSEReg:
1599                 return OP_LOADR8_MEMBASE;
1600         case ArgInFloatSSEReg:
1601                 return OP_LOADR4_MEMBASE;
1602         default:
1603                 g_assert_not_reached ();
1604         }
1605
1606         return -1;
1607 }
1608
1609 static void
1610 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1611 {
1612         MonoInst *arg;
1613         MonoMethodSignature *tmp_sig;
1614         MonoInst *sig_arg;
1615
1616         /* FIXME: Add support for signature tokens to AOT */
1617         cfg->disable_aot = TRUE;
1618
1619         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1620
1621         /*
1622          * mono_ArgIterator_Setup assumes the signature cookie is
1623          * passed first and all the arguments which were before it are
1624          * passed on the stack after the signature. So compensate by
1625          * passing a different signature.
1626          */
1627         tmp_sig = mono_metadata_signature_dup (call->signature);
1628         tmp_sig->param_count -= call->signature->sentinelpos;
1629         tmp_sig->sentinelpos = 0;
1630         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1631
1632         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1633         sig_arg->inst_p0 = tmp_sig;
1634
1635         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1636         arg->inst_left = sig_arg;
1637         arg->type = STACK_PTR;
1638
1639         /* prepend, so they get reversed */
1640         arg->next = call->out_args;
1641         call->out_args = arg;
1642 }
1643
1644 /*
1645  * take the arguments and generate the arch-specific
1646  * instructions to properly call the function in call.
1647  * This includes pushing, moving arguments to the right register
1648  * etc.
1649  */
1650 MonoCallInst*
1651 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1652         MonoInst *arg, *in;
1653         MonoMethodSignature *sig;
1654         int i, n, stack_size;
1655         CallInfo *cinfo;
1656         ArgInfo *ainfo;
1657
1658         stack_size = 0;
1659
1660         sig = call->signature;
1661         n = sig->param_count + sig->hasthis;
1662
1663         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1664
1665         if (cfg->method->save_lmf) {
1666                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1667                 arg->next = call->out_args;
1668                 call->out_args = arg;
1669         }
1670
1671         for (i = 0; i < n; ++i) {
1672                 ainfo = cinfo->args + i;
1673
1674                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1675                         /* Emit the signature cookie just before the implicit arguments */
1676                         emit_sig_cookie (cfg, call, cinfo);
1677                 }
1678
1679                 if (is_virtual && i == 0) {
1680                         /* the argument will be attached to the call instruction */
1681                         in = call->args [i];
1682                 } else {
1683                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1684                         in = call->args [i];
1685                         arg->cil_code = in->cil_code;
1686                         arg->inst_left = in;
1687                         arg->type = in->type;
1688                         /* prepend, so they get reversed */
1689                         arg->next = call->out_args;
1690                         call->out_args = arg;
1691 #if 0
1692                         if (!cinfo->stack_usage)
1693                                 /* Keep the assignments to the arg registers in order if possible */
1694                                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1695                         else
1696                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1697 #endif
1698
1699                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1700                                 guint32 align;
1701                                 guint32 size;
1702
1703                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1704                                         size = sizeof (MonoTypedRef);
1705                                         align = sizeof (gpointer);
1706                                 }
1707                                 else
1708                                 if (sig->pinvoke)
1709                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1710                                 else {
1711                                         /*
1712                                          * Other backends use mini_type_stack_size (), but that
1713                                          * aligns the size to 8, which is larger than the size of
1714                                          * the source, leading to reads of invalid memory if the
1715                                          * source is at the end of address space.
1716                                          */
1717                                         size = mono_class_value_size (in->klass, &align);
1718                                 }
1719                                 if (ainfo->storage == ArgValuetypeInReg) {
1720                                         if (ainfo->pair_storage [1] == ArgNone) {
1721                                                 MonoInst *load;
1722
1723                                                 /* Simpler case */
1724
1725                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1726                                                 load->inst_left = in;
1727
1728                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1729                                         }
1730                                         else {
1731                                                 /* Trees can't be shared so make a copy */
1732                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1733                                                 MonoInst *load, *load2, *offset_ins;
1734
1735                                                 /* Reg1 */
1736                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1737                                                 load->ssa_op = MONO_SSA_LOAD;
1738                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1739
1740                                                 NEW_ICONST (cfg, offset_ins, 0);
1741                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1742                                                 load2->inst_left = load;
1743                                                 load2->inst_right = offset_ins;
1744
1745                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1746                                                 load->inst_left = load2;
1747
1748                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1749
1750                                                 /* Reg2 */
1751                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1752                                                 load->ssa_op = MONO_SSA_LOAD;
1753                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1754
1755                                                 NEW_ICONST (cfg, offset_ins, 8);
1756                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1757                                                 load2->inst_left = load;
1758                                                 load2->inst_right = offset_ins;
1759
1760                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1761                                                 load->inst_left = load2;
1762
1763                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1764                                                 arg->cil_code = in->cil_code;
1765                                                 arg->type = in->type;
1766                                                 /* prepend, so they get reversed */
1767                                                 arg->next = call->out_args;
1768                                                 call->out_args = arg;
1769
1770                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1771
1772                                                 /* Prepend a copy inst */
1773                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1774                                                 arg->cil_code = in->cil_code;
1775                                                 arg->ssa_op = MONO_SSA_STORE;
1776                                                 arg->inst_left = vtaddr;
1777                                                 arg->inst_right = in;
1778                                                 arg->type = in->type;
1779
1780                                                 /* prepend, so they get reversed */
1781                                                 arg->next = call->out_args;
1782                                                 call->out_args = arg;
1783                                         }
1784                                 }
1785                                 else if (ainfo->storage == ArgValuetypeAddrInIReg){
1786
1787                                         /* Add a temp variable to the method*/
1788                                         MonoInst *load;
1789                                         MonoInst *vtaddr = mono_compile_create_var (cfg, &in->klass->byval_arg, OP_LOCAL);
1790
1791                                         MONO_INST_NEW (cfg, load, OP_LDADDR);
1792                                         load->ssa_op = MONO_SSA_LOAD;
1793                                         load->inst_left = vtaddr;
1794
1795                                         if (ainfo->pair_storage [0] == ArgInIReg) {
1796                                                 /* Inserted after the copy.  Load the address of the temp to the argument regster.*/
1797                                                 arg->opcode = OP_OUTARG_REG;
1798                                                 arg->inst_left = load;
1799                                                 arg->inst_call = call;
1800                                                 arg->backend.reg3 =  ainfo->pair_regs [0];
1801                                         }
1802                                         else {
1803                                                 /* Inserted after the copy.  Load the address of the temp on the stack.*/
1804                                                 arg->opcode = OP_OUTARG_VT;
1805                                                 arg->inst_left = load;
1806                                                 arg->type = STACK_PTR;
1807                                                 arg->klass = mono_defaults.int_class;
1808                                                 arg->backend.is_pinvoke = sig->pinvoke;
1809                                                 arg->inst_imm = size;
1810                                         }
1811
1812                                         /*Copy the argument to the temp variable.*/
1813                                         MONO_INST_NEW (cfg, load, OP_MEMCPY);
1814                                         load->backend.memcpy_args = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoMemcpyArgs));
1815                                         load->backend.memcpy_args->size = size;
1816                                         load->backend.memcpy_args->align = align;
1817                                         load->inst_left = (cfg)->varinfo [vtaddr->inst_c0];
1818                                         load->inst_right = in->inst_i0;
1819
1820                                         // FIXME:
1821                                         g_assert_not_reached ();
1822                                         //MONO_INST_LIST_ADD (&load->node, &call->out_args);
1823                                 }
1824                                 else {
1825                                         arg->opcode = OP_OUTARG_VT;
1826                                         arg->klass = in->klass;
1827                                         arg->backend.is_pinvoke = sig->pinvoke;
1828                                         arg->inst_imm = size;
1829                                 }
1830                         }
1831                         else {
1832                                 switch (ainfo->storage) {
1833                                 case ArgInIReg:
1834                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1835                                         break;
1836                                 case ArgInFloatSSEReg:
1837                                 case ArgInDoubleSSEReg:
1838                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1839                                         break;
1840                                 case ArgOnStack:
1841                                         arg->opcode = OP_OUTARG;
1842                                         if (!sig->params [i - sig->hasthis]->byref) {
1843                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1844                                                         arg->opcode = OP_OUTARG_R4;
1845                                                 else
1846                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1847                                                                 arg->opcode = OP_OUTARG_R8;
1848                                         }
1849                                         break;
1850                                 default:
1851                                         g_assert_not_reached ();
1852                                 }
1853                         }
1854                 }
1855         }
1856
1857         /* Handle the case where there are no implicit arguments */
1858         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1859                 emit_sig_cookie (cfg, call, cinfo);
1860         }
1861
1862         if (cinfo->ret.storage == ArgValuetypeInReg) {
1863                 /* This is needed by mono_arch_emit_this_vret_args () */
1864                 if (!cfg->arch.vret_addr_loc) {
1865                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1866                         /* Prevent it from being register allocated or optimized away */
1867                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1868                 }
1869         }
1870
1871         if (cinfo->need_stack_align) {
1872                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1873                 arg->inst_c0 = 8;
1874                 /* prepend, so they get reversed */
1875                 arg->next = call->out_args;
1876                 call->out_args = arg;
1877         }
1878
1879 #ifdef PLATFORM_WIN32
1880         /* Always reserve 32 bytes of stack space on Win64 */
1881         /*MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1882         arg->inst_c0 = 32;
1883         MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);*/
1884         NOT_IMPLEMENTED;
1885 #endif
1886
1887 #if 0
1888         if (cfg->method->save_lmf) {
1889                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1890                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1891         }
1892 #endif
1893
1894         call->stack_usage = cinfo->stack_usage;
1895         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1896         cfg->flags |= MONO_CFG_HAS_CALLS;
1897
1898         return call;
1899 }
1900
1901 static void
1902 emit_sig_cookie2 (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1903 {
1904         MonoInst *arg;
1905         MonoMethodSignature *tmp_sig;
1906         MonoInst *sig_arg;
1907
1908         if (call->tail_call)
1909                 NOT_IMPLEMENTED;
1910
1911         /* FIXME: Add support for signature tokens to AOT */
1912         cfg->disable_aot = TRUE;
1913
1914         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1915
1916         /*
1917          * mono_ArgIterator_Setup assumes the signature cookie is
1918          * passed first and all the arguments which were before it are
1919          * passed on the stack after the signature. So compensate by
1920          * passing a different signature.
1921          */
1922         tmp_sig = mono_metadata_signature_dup (call->signature);
1923         tmp_sig->param_count -= call->signature->sentinelpos;
1924         tmp_sig->sentinelpos = 0;
1925         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1926
1927         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1928         sig_arg->dreg = mono_alloc_ireg (cfg);
1929         sig_arg->inst_p0 = tmp_sig;
1930         MONO_ADD_INS (cfg->cbb, sig_arg);
1931
1932         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1933         arg->sreg1 = sig_arg->dreg;
1934         MONO_ADD_INS (cfg->cbb, arg);
1935 }
1936
1937 void
1938 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1939 {
1940         MonoInst *arg, *in;
1941         MonoMethodSignature *sig;
1942         int i, n, stack_size;
1943         CallInfo *cinfo;
1944         ArgInfo *ainfo;
1945
1946         stack_size = 0;
1947
1948         sig = call->signature;
1949         n = sig->param_count + sig->hasthis;
1950
1951         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1952
1953         if (cinfo->need_stack_align) {
1954                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1955         }
1956
1957         /*
1958          * Emit all parameters passed in registers in non-reverse order for better readability
1959          * and to help the optimization in emit_prolog ().
1960          */
1961         for (i = 0; i < n; ++i) {
1962                 ainfo = cinfo->args + i;
1963
1964                 in = call->args [i];
1965
1966                 if (ainfo->storage == ArgInIReg)
1967                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1968         }
1969
1970         for (i = n - 1; i >= 0; --i) {
1971                 ainfo = cinfo->args + i;
1972
1973                 in = call->args [i];
1974
1975                 switch (ainfo->storage) {
1976                 case ArgInIReg:
1977                         /* Already done */
1978                         break;
1979                 case ArgInFloatSSEReg:
1980                 case ArgInDoubleSSEReg:
1981                         add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1982                         break;
1983                 case ArgOnStack:
1984                 case ArgValuetypeInReg:
1985                 case ArgValuetypeAddrInIReg:
1986                         if (ainfo->storage == ArgOnStack && call->tail_call)
1987                                 NOT_IMPLEMENTED;
1988                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1989                                 guint32 align;
1990                                 guint32 size;
1991
1992                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1993                                         size = sizeof (MonoTypedRef);
1994                                         align = sizeof (gpointer);
1995                                 }
1996                                 else {
1997                                         if (sig->pinvoke)
1998                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1999                                         else {
2000                                                 /*
2001                                                  * Other backends use mono_type_stack_size (), but that
2002                                                  * aligns the size to 8, which is larger than the size of
2003                                                  * the source, leading to reads of invalid memory if the
2004                                                  * source is at the end of address space.
2005                                                  */
2006                                                 size = mono_class_value_size (in->klass, &align);
2007                                         }
2008                                 }
2009                                 g_assert (in->klass);
2010
2011                                 if (size > 0) {
2012                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2013                                         arg->sreg1 = in->dreg;
2014                                         arg->klass = in->klass;
2015                                         arg->backend.size = size;
2016                                         arg->inst_p0 = call;
2017                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2018                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2019
2020                                         MONO_ADD_INS (cfg->cbb, arg);
2021                                 }
2022                         } else {
2023                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2024                                 arg->sreg1 = in->dreg;
2025                                 if (!sig->params [i - sig->hasthis]->byref) {
2026                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2027                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2028                                                 arg->opcode = OP_STORER4_MEMBASE_REG;
2029                                                 arg->inst_destbasereg = X86_ESP;
2030                                                 arg->inst_offset = 0;
2031                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2032                                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2033                                                 arg->opcode = OP_STORER8_MEMBASE_REG;
2034                                                 arg->inst_destbasereg = X86_ESP;
2035                                                 arg->inst_offset = 0;
2036                                         }
2037                                 }
2038                                 MONO_ADD_INS (cfg->cbb, arg);
2039                         }
2040                         break;
2041                 default:
2042                         g_assert_not_reached ();
2043                 }
2044
2045                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2046                         /* Emit the signature cookie just before the implicit arguments */
2047                         emit_sig_cookie2 (cfg, call, cinfo);
2048                 }
2049         }
2050
2051         /* Handle the case where there are no implicit arguments */
2052         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
2053                 emit_sig_cookie2 (cfg, call, cinfo);
2054         }
2055
2056         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2057                 MonoInst *vtarg;
2058
2059                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2060                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2061                                 /*
2062                                  * Tell the JIT to use a more efficient calling convention: call using
2063                                  * OP_CALL, compute the result location after the call, and save the
2064                                  * result there.
2065                                  */
2066                                 call->vret_in_reg = TRUE;
2067                                 /*
2068                                  * Nullify the instruction computing the vret addr to enable
2069                                  * future optimizations.
2070                                  */
2071                                 if (call->vret_var)
2072                                         NULLIFY_INS (call->vret_var);
2073                         } else {
2074                                 if (call->tail_call)
2075                                         NOT_IMPLEMENTED;
2076                                 /*
2077                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2078                                  * the stack. Push the address here, so the call instruction can
2079                                  * access it.
2080                                  */
2081                                 if (!cfg->arch.vret_addr_loc) {
2082                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2083                                         /* Prevent it from being register allocated or optimized away */
2084                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2085                                 }
2086
2087                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2088                         }
2089                 }
2090                 else {
2091                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2092                         vtarg->sreg1 = call->vret_var->dreg;
2093                         vtarg->dreg = mono_alloc_preg (cfg);
2094                         MONO_ADD_INS (cfg->cbb, vtarg);
2095
2096                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2097                 }
2098         }
2099
2100 #ifdef PLATFORM_WIN32
2101         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2102                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2103         }
2104 #endif
2105
2106         if (cfg->method->save_lmf) {
2107                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2108                 MONO_ADD_INS (cfg->cbb, arg);
2109         }
2110
2111         call->stack_usage = cinfo->stack_usage;
2112 }
2113
2114 void
2115 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2116 {
2117         MonoInst *arg;
2118         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2119         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2120         int size = ins->backend.size;
2121
2122         if (ainfo->storage == ArgValuetypeInReg) {
2123                 MonoInst *load;
2124                 int part;
2125
2126                 for (part = 0; part < 2; ++part) {
2127                         if (ainfo->pair_storage [part] == ArgNone)
2128                                 continue;
2129
2130                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2131                         load->inst_basereg = src->dreg;
2132                         load->inst_offset = part * sizeof (gpointer);
2133
2134                         switch (ainfo->pair_storage [part]) {
2135                         case ArgInIReg:
2136                                 load->dreg = mono_alloc_ireg (cfg);
2137                                 break;
2138                         case ArgInDoubleSSEReg:
2139                         case ArgInFloatSSEReg:
2140                                 load->dreg = mono_alloc_freg (cfg);
2141                                 break;
2142                         default:
2143                                 g_assert_not_reached ();
2144                         }
2145                         MONO_ADD_INS (cfg->cbb, load);
2146
2147                         add_outarg_reg2 (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2148                 }
2149         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2150                 MonoInst *vtaddr, *load;
2151                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2152
2153                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2154                 load->inst_p0 = vtaddr;
2155                 vtaddr->flags |= MONO_INST_INDIRECT;
2156                 load->type = STACK_MP;
2157                 load->klass = vtaddr->klass;
2158                 load->dreg = mono_alloc_ireg (cfg);
2159                 MONO_ADD_INS (cfg->cbb, load);
2160                 mini_emit_memcpy2 (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2161
2162                 if (ainfo->pair_storage [0] == ArgInIReg) {
2163                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2164                         arg->dreg = ainfo->pair_regs [0];
2165                         arg->sreg1 = load->dreg;
2166                         arg->inst_imm = 0;
2167                         MONO_ADD_INS (cfg->cbb, arg);
2168                 } else {
2169                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2170                         arg->sreg1 = load->dreg;
2171                         MONO_ADD_INS (cfg->cbb, arg);
2172                 }
2173         } else {
2174                 if (size == 8) {
2175                         /* Can't use this for < 8 since it does an 8 byte memory load */
2176                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2177                         arg->inst_basereg = src->dreg;
2178                         arg->inst_offset = 0;
2179                         MONO_ADD_INS (cfg->cbb, arg);
2180                 } else if (size <= 40) {
2181                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2182                         mini_emit_memcpy2 (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2183                 } else {
2184                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2185                         arg->inst_basereg = src->dreg;
2186                         arg->inst_offset = 0;
2187                         arg->inst_imm = size;
2188                         MONO_ADD_INS (cfg->cbb, arg);
2189                 }
2190         }
2191 }
2192
2193 void
2194 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2195 {
2196         MonoType *ret = mono_type_get_underlying_type (mono_method_signature (method)->ret);
2197
2198         if (!ret->byref) {
2199                 if (ret->type == MONO_TYPE_R4) {
2200                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2201                         return;
2202                 } else if (ret->type == MONO_TYPE_R8) {
2203                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2204                         return;
2205                 }
2206         }
2207
2208         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2209 }
2210
2211 #define EMIT_COND_BRANCH(ins,cond,sign) \
2212 if (ins->flags & MONO_INST_BRLABEL) { \
2213         if (ins->inst_i0->inst_c0) { \
2214                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
2215         } else { \
2216                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
2217                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2218                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
2219                         x86_branch8 (code, cond, 0, sign); \
2220                 else \
2221                         x86_branch32 (code, cond, 0, sign); \
2222         } \
2223 } else { \
2224         if (ins->inst_true_bb->native_offset) { \
2225                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2226         } else { \
2227                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2228                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2229                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
2230                         x86_branch8 (code, cond, 0, sign); \
2231                 else \
2232                         x86_branch32 (code, cond, 0, sign); \
2233         } \
2234 }
2235
2236 /* emit an exception if condition is fail */
2237 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2238         do {                                                        \
2239                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2240                 if (tins == NULL) {                                                                             \
2241                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2242                                         MONO_PATCH_INFO_EXC, exc_name);  \
2243                         x86_branch32 (code, cond, 0, signed);               \
2244                 } else {        \
2245                         EMIT_COND_BRANCH (tins, cond, signed);  \
2246                 }                       \
2247         } while (0);
2248
2249 #define EMIT_FPCOMPARE(code) do { \
2250         amd64_fcompp (code); \
2251         amd64_fnstsw (code); \
2252 } while (0);
2253
2254 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2255     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2256         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2257         amd64_ ##op (code); \
2258         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2259         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2260 } while (0);
2261
2262 static guint8*
2263 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2264 {
2265         gboolean no_patch = FALSE;
2266
2267         /*
2268          * FIXME: Add support for thunks
2269          */
2270         {
2271                 gboolean near_call = FALSE;
2272
2273                 /*
2274                  * Indirect calls are expensive so try to make a near call if possible.
2275                  * The caller memory is allocated by the code manager so it is
2276                  * guaranteed to be at a 32 bit offset.
2277                  */
2278
2279                 if (patch_type != MONO_PATCH_INFO_ABS) {
2280                         /* The target is in memory allocated using the code manager */
2281                         near_call = TRUE;
2282
2283                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2284                                 if (((MonoMethod*)data)->klass->image->aot_module)
2285                                         /* The callee might be an AOT method */
2286                                         near_call = FALSE;
2287                                 if (((MonoMethod*)data)->dynamic)
2288                                         /* The target is in malloc-ed memory */
2289                                         near_call = FALSE;
2290                         }
2291
2292                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2293                                 /*
2294                                  * The call might go directly to a native function without
2295                                  * the wrapper.
2296                                  */
2297                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2298                                 if (mi) {
2299                                         gconstpointer target = mono_icall_get_wrapper (mi);
2300                                         if ((((guint64)target) >> 32) != 0)
2301                                                 near_call = FALSE;
2302                                 }
2303                         }
2304                 }
2305                 else {
2306                         if (mono_find_class_init_trampoline_by_addr (data))
2307                                 near_call = TRUE;
2308                         else {
2309                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2310                                 if (info) {
2311                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2312                                                 strstr (cfg->method->name, info->name)) {
2313                                                 /* A call to the wrapped function */
2314                                                 if ((((guint64)data) >> 32) == 0)
2315                                                         near_call = TRUE;
2316                                                 no_patch = TRUE;
2317                                         }
2318                                         else if (info->func == info->wrapper) {
2319                                                 /* No wrapper */
2320                                                 if ((((guint64)info->func) >> 32) == 0)
2321                                                         near_call = TRUE;
2322                                         }
2323                                         else {
2324                                                 /* See the comment in mono_codegen () */
2325                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2326                                                         near_call = TRUE;
2327                                         }
2328                                 }
2329                                 else if ((((guint64)data) >> 32) == 0) {
2330                                         near_call = TRUE;
2331                                         no_patch = TRUE;
2332                                 }
2333                         }
2334                 }
2335
2336                 if (cfg->method->dynamic)
2337                         /* These methods are allocated using malloc */
2338                         near_call = FALSE;
2339
2340                 if (cfg->compile_aot)
2341                         near_call = TRUE;
2342
2343 #ifdef MONO_ARCH_NOMAP32BIT
2344                 near_call = FALSE;
2345 #endif
2346
2347                 if (near_call) {
2348                         /*
2349                          * Align the call displacement to an address divisible by 4 so it does
2350                          * not span cache lines. This is required for code patching to work on SMP
2351                          * systems.
2352                          */
2353                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2354                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2355                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2356                         amd64_call_code (code, 0);
2357                 }
2358                 else {
2359                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2360                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2361                         amd64_call_reg (code, GP_SCRATCH_REG);
2362                 }
2363         }
2364
2365         return code;
2366 }
2367
2368 static inline guint8*
2369 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2370 {
2371 #ifdef PLATFORM_WIN32
2372         if (win64_adjust_stack)
2373                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2374 #endif
2375         code = emit_call_body (cfg, code, patch_type, data);
2376 #ifdef PLATFORM_WIN32
2377         if (win64_adjust_stack)
2378                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2379 #endif
2380
2381         return code;
2382 }
2383
2384 static inline int
2385 store_membase_imm_to_store_membase_reg (int opcode)
2386 {
2387         switch (opcode) {
2388         case OP_STORE_MEMBASE_IMM:
2389                 return OP_STORE_MEMBASE_REG;
2390         case OP_STOREI4_MEMBASE_IMM:
2391                 return OP_STOREI4_MEMBASE_REG;
2392         case OP_STOREI8_MEMBASE_IMM:
2393                 return OP_STOREI8_MEMBASE_REG;
2394         }
2395
2396         return -1;
2397 }
2398
2399 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2400
2401 /*
2402  * mono_arch_peephole_pass_1:
2403  *
2404  *   Perform peephole opts which should/can be performed before local regalloc
2405  */
2406 void
2407 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2408 {
2409         MonoInst *ins, *n;
2410
2411         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2412                 MonoInst *last_ins = ins->prev;
2413
2414                 switch (ins->opcode) {
2415                 case OP_ADD_IMM:
2416                 case OP_IADD_IMM:
2417                 case OP_LADD_IMM:
2418                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2419                                 /*
2420                                  * X86_LEA is like ADD, but doesn't have the
2421                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2422                                  * its operand to 64 bit.
2423                                  */
2424                                 ins->opcode = OP_X86_LEA_MEMBASE;
2425                                 ins->inst_basereg = ins->sreg1;
2426                         }
2427                         break;
2428                 case OP_LXOR:
2429                 case OP_IXOR:
2430                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2431                                 MonoInst *ins2;
2432
2433                                 /*
2434                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2435                                  * the latter has length 2-3 instead of 6 (reverse constant
2436                                  * propagation). These instruction sequences are very common
2437                                  * in the initlocals bblock.
2438                                  */
2439                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2440                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2441                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2442                                                 ins2->sreg1 = ins->dreg;
2443                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2444                                                 /* Continue */
2445                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2446                                                 NULLIFY_INS (ins2);
2447                                                 /* Continue */
2448                                         } else {
2449                                                 break;
2450                                         }
2451                                 }
2452                         }
2453                         break;
2454                 case OP_COMPARE_IMM:
2455                 case OP_LCOMPARE_IMM:
2456                         /* OP_COMPARE_IMM (reg, 0)
2457                          * -->
2458                          * OP_AMD64_TEST_NULL (reg)
2459                          */
2460                         if (!ins->inst_imm)
2461                                 ins->opcode = OP_AMD64_TEST_NULL;
2462                         break;
2463                 case OP_ICOMPARE_IMM:
2464                         if (!ins->inst_imm)
2465                                 ins->opcode = OP_X86_TEST_NULL;
2466                         break;
2467                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2468                         /*
2469                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2470                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2471                          * -->
2472                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2473                          * OP_COMPARE_IMM reg, imm
2474                          *
2475                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2476                          */
2477                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2478                             ins->inst_basereg == last_ins->inst_destbasereg &&
2479                             ins->inst_offset == last_ins->inst_offset) {
2480                                         ins->opcode = OP_ICOMPARE_IMM;
2481                                         ins->sreg1 = last_ins->sreg1;
2482
2483                                         /* check if we can remove cmp reg,0 with test null */
2484                                         if (!ins->inst_imm)
2485                                                 ins->opcode = OP_X86_TEST_NULL;
2486                                 }
2487
2488                         break;
2489                 }
2490
2491                 mono_peephole_ins (bb, ins);
2492         }
2493 }
2494
2495 void
2496 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2497 {
2498         MonoInst *ins, *n;
2499
2500         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2501                 switch (ins->opcode) {
2502                 case OP_ICONST:
2503                 case OP_I8CONST: {
2504                         /* reg = 0 -> XOR (reg, reg) */
2505                         /* XOR sets cflags on x86, so we cant do it always */
2506                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2507                                 ins->opcode = OP_LXOR;
2508                                 ins->sreg1 = ins->dreg;
2509                                 ins->sreg2 = ins->dreg;
2510                                 /* Fall through */
2511                         } else {
2512                                 break;
2513                         }
2514                 }
2515                 case OP_LXOR:
2516                         /*
2517                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2518                          * 0 result into 64 bits.
2519                          */
2520                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2521                                 ins->opcode = OP_IXOR;
2522                         }
2523                         /* Fall through */
2524                 case OP_IXOR:
2525                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2526                                 MonoInst *ins2;
2527
2528                                 /*
2529                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2530                                  * the latter has length 2-3 instead of 6 (reverse constant
2531                                  * propagation). These instruction sequences are very common
2532                                  * in the initlocals bblock.
2533                                  */
2534                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2535                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2536                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2537                                                 ins2->sreg1 = ins->dreg;
2538                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2539                                                 /* Continue */
2540                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2541                                                 NULLIFY_INS (ins2);
2542                                                 /* Continue */
2543                                         } else {
2544                                                 break;
2545                                         }
2546                                 }
2547                         }
2548                         break;
2549                 case OP_IADD_IMM:
2550                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2551                                 ins->opcode = OP_X86_INC_REG;
2552                         break;
2553                 case OP_ISUB_IMM:
2554                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2555                                 ins->opcode = OP_X86_DEC_REG;
2556                         break;
2557                 }
2558
2559                 mono_peephole_ins (bb, ins);
2560         }
2561 }
2562
2563 #define NEW_INS(cfg,ins,dest,op) do {   \
2564                 MONO_INST_NEW ((cfg), (dest), (op)); \
2565         (dest)->cil_code = (ins)->cil_code; \
2566         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2567         } while (0)
2568
2569 /*
2570  * mono_arch_lowering_pass:
2571  *
2572  *  Converts complex opcodes into simpler ones so that each IR instruction
2573  * corresponds to one machine instruction.
2574  */
2575 void
2576 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2577 {
2578         MonoInst *ins, *n, *temp;
2579
2580         if (bb->max_vreg > cfg->rs->next_vreg)
2581                 cfg->rs->next_vreg = bb->max_vreg;
2582
2583         /*
2584          * FIXME: Need to add more instructions, but the current machine
2585          * description can't model some parts of the composite instructions like
2586          * cdq.
2587          */
2588         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2589                 switch (ins->opcode) {
2590                 case OP_DIV_IMM:
2591                 case OP_REM_IMM:
2592                 case OP_IDIV_IMM:
2593                 case OP_IREM_IMM:
2594                 case OP_IDIV_UN_IMM:
2595                 case OP_IREM_UN_IMM:
2596                         mono_decompose_op_imm (cfg, bb, ins);
2597                         break;
2598                 case OP_COMPARE_IMM:
2599                 case OP_LCOMPARE_IMM:
2600                         if (!amd64_is_imm32 (ins->inst_imm)) {
2601                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2602                                 temp->inst_c0 = ins->inst_imm;
2603                                 if (cfg->globalra)
2604                                         temp->dreg = mono_alloc_ireg (cfg);
2605                                 else
2606                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2607                                 ins->opcode = OP_COMPARE;
2608                                 ins->sreg2 = temp->dreg;
2609                         }
2610                         break;
2611                 case OP_LOAD_MEMBASE:
2612                 case OP_LOADI8_MEMBASE:
2613                         if (!amd64_is_imm32 (ins->inst_offset)) {
2614                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2615                                 temp->inst_c0 = ins->inst_offset;
2616                                 if (cfg->globalra)
2617                                         temp->dreg = mono_alloc_ireg (cfg);
2618                                 else
2619                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2620                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2621                                 ins->inst_indexreg = temp->dreg;
2622                         }
2623                         break;
2624                 case OP_STORE_MEMBASE_IMM:
2625                 case OP_STOREI8_MEMBASE_IMM:
2626                         if (!amd64_is_imm32 (ins->inst_imm)) {
2627                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2628                                 temp->inst_c0 = ins->inst_imm;
2629                                 if (cfg->globalra)
2630                                         temp->dreg = mono_alloc_ireg (cfg);
2631                                 else
2632                                         temp->dreg = mono_regstate_next_int (cfg->rs);
2633                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2634                                 ins->sreg1 = temp->dreg;
2635                         }
2636                         break;
2637                 default:
2638                         break;
2639                 }
2640         }
2641
2642         bb->max_vreg = cfg->rs->next_vreg;
2643 }
2644
2645 static const int
2646 branch_cc_table [] = {
2647         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2648         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2649         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2650 };
2651
2652 /* Maps CMP_... constants to X86_CC_... constants */
2653 static const int
2654 cc_table [] = {
2655         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2656         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2657 };
2658
2659 static const int
2660 cc_signed_table [] = {
2661         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2662         FALSE, FALSE, FALSE, FALSE
2663 };
2664
2665 /*#include "cprop.c"*/
2666
2667 static unsigned char*
2668 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2669 {
2670         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2671
2672         if (size == 1)
2673                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2674         else if (size == 2)
2675                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2676         return code;
2677 }
2678
2679 static unsigned char*
2680 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2681 {
2682         int sreg = tree->sreg1;
2683         int need_touch = FALSE;
2684
2685 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2686         if (!tree->flags & MONO_INST_INIT)
2687                 need_touch = TRUE;
2688 #endif
2689
2690         if (need_touch) {
2691                 guint8* br[5];
2692
2693                 /*
2694                  * Under Windows:
2695                  * If requested stack size is larger than one page,
2696                  * perform stack-touch operation
2697                  */
2698                 /*
2699                  * Generate stack probe code.
2700                  * Under Windows, it is necessary to allocate one page at a time,
2701                  * "touching" stack after each successful sub-allocation. This is
2702                  * because of the way stack growth is implemented - there is a
2703                  * guard page before the lowest stack page that is currently commited.
2704                  * Stack normally grows sequentially so OS traps access to the
2705                  * guard page and commits more pages when needed.
2706                  */
2707                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2708                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2709
2710                 br[2] = code; /* loop */
2711                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2712                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2713                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2714                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2715                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2716                 amd64_patch (br[3], br[2]);
2717                 amd64_test_reg_reg (code, sreg, sreg);
2718                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2719                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2720
2721                 br[1] = code; x86_jump8 (code, 0);
2722
2723                 amd64_patch (br[0], code);
2724                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2725                 amd64_patch (br[1], code);
2726                 amd64_patch (br[4], code);
2727         }
2728         else
2729                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2730
2731         if (tree->flags & MONO_INST_INIT) {
2732                 int offset = 0;
2733                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2734                         amd64_push_reg (code, AMD64_RAX);
2735                         offset += 8;
2736                 }
2737                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2738                         amd64_push_reg (code, AMD64_RCX);
2739                         offset += 8;
2740                 }
2741                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2742                         amd64_push_reg (code, AMD64_RDI);
2743                         offset += 8;
2744                 }
2745
2746                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2747                 if (sreg != AMD64_RCX)
2748                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2749                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2750
2751                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2752                 amd64_cld (code);
2753                 amd64_prefix (code, X86_REP_PREFIX);
2754                 amd64_stosl (code);
2755
2756                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2757                         amd64_pop_reg (code, AMD64_RDI);
2758                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2759                         amd64_pop_reg (code, AMD64_RCX);
2760                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2761                         amd64_pop_reg (code, AMD64_RAX);
2762         }
2763         return code;
2764 }
2765
2766 static guint8*
2767 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2768 {
2769         CallInfo *cinfo;
2770         guint32 quad;
2771
2772         /* Move return value to the target register */
2773         /* FIXME: do this in the local reg allocator */
2774         switch (ins->opcode) {
2775         case OP_CALL:
2776         case OP_CALL_REG:
2777         case OP_CALL_MEMBASE:
2778         case OP_LCALL:
2779         case OP_LCALL_REG:
2780         case OP_LCALL_MEMBASE:
2781                 g_assert (ins->dreg == AMD64_RAX);
2782                 break;
2783         case OP_FCALL:
2784         case OP_FCALL_REG:
2785         case OP_FCALL_MEMBASE:
2786                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2787                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2788                 }
2789                 else {
2790                         if (ins->dreg != AMD64_XMM0)
2791                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2792                 }
2793                 break;
2794         case OP_VCALL:
2795         case OP_VCALL_REG:
2796         case OP_VCALL_MEMBASE:
2797         case OP_VCALL2:
2798         case OP_VCALL2_REG:
2799         case OP_VCALL2_MEMBASE:
2800                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2801                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2802                         MonoInst *loc = cfg->arch.vret_addr_loc;
2803
2804                         /* Load the destination address */
2805                         g_assert (loc->opcode == OP_REGOFFSET);
2806                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2807
2808                         for (quad = 0; quad < 2; quad ++) {
2809                                 switch (cinfo->ret.pair_storage [quad]) {
2810                                 case ArgInIReg:
2811                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2812                                         break;
2813                                 case ArgInFloatSSEReg:
2814                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2815                                         break;
2816                                 case ArgInDoubleSSEReg:
2817                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2818                                         break;
2819                                 case ArgNone:
2820                                         break;
2821                                 default:
2822                                         NOT_IMPLEMENTED;
2823                                 }
2824                         }
2825                 }
2826                 break;
2827         }
2828
2829         return code;
2830 }
2831
2832 /*
2833  * emit_tls_get:
2834  * @code: buffer to store code to
2835  * @dreg: hard register where to place the result
2836  * @tls_offset: offset info
2837  *
2838  * emit_tls_get emits in @code the native code that puts in the dreg register
2839  * the item in the thread local storage identified by tls_offset.
2840  *
2841  * Returns: a pointer to the end of the stored code
2842  */
2843 static guint8*
2844 emit_tls_get (guint8* code, int dreg, int tls_offset)
2845 {
2846 #ifdef PLATFORM_WIN32
2847         g_assert (tls_offset < 64);
2848         x86_prefix (code, X86_GS_PREFIX);
2849         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2850 #else
2851         if (optimize_for_xen) {
2852                 x86_prefix (code, X86_FS_PREFIX);
2853                 amd64_mov_reg_mem (code, dreg, 0, 8);
2854                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2855         } else {
2856                 x86_prefix (code, X86_FS_PREFIX);
2857                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2858         }
2859 #endif
2860         return code;
2861 }
2862
2863 /*
2864  * emit_load_volatile_arguments:
2865  *
2866  *  Load volatile arguments from the stack to the original input registers.
2867  * Required before a tail call.
2868  */
2869 static guint8*
2870 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2871 {
2872         MonoMethod *method = cfg->method;
2873         MonoMethodSignature *sig;
2874         MonoInst *ins;
2875         CallInfo *cinfo;
2876         guint32 i, quad;
2877
2878         /* FIXME: Generate intermediate code instead */
2879
2880         sig = mono_method_signature (method);
2881
2882         cinfo = cfg->arch.cinfo;
2883
2884         /* This is the opposite of the code in emit_prolog */
2885         if (sig->ret->type != MONO_TYPE_VOID) {
2886                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2887                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2888         }
2889
2890         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2891                 ArgInfo *ainfo = cinfo->args + i;
2892                 MonoType *arg_type;
2893                 ins = cfg->args [i];
2894
2895                 if (sig->hasthis && (i == 0))
2896                         arg_type = &mono_defaults.object_class->byval_arg;
2897                 else
2898                         arg_type = sig->params [i - sig->hasthis];
2899
2900                 if (ins->opcode != OP_REGVAR) {
2901                         switch (ainfo->storage) {
2902                         case ArgInIReg: {
2903                                 guint32 size = 8;
2904
2905                                 /* FIXME: I1 etc */
2906                                 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2907                                 break;
2908                         }
2909                         case ArgInFloatSSEReg:
2910                                 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2911                                 break;
2912                         case ArgInDoubleSSEReg:
2913                                 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2914                                 break;
2915                         case ArgValuetypeInReg:
2916                                 for (quad = 0; quad < 2; quad ++) {
2917                                         switch (ainfo->pair_storage [quad]) {
2918                                         case ArgInIReg:
2919                                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2920                                                 break;
2921                                         case ArgInFloatSSEReg:
2922                                         case ArgInDoubleSSEReg:
2923                                                 g_assert_not_reached ();
2924                                                 break;
2925                                         case ArgNone:
2926                                                 break;
2927                                         default:
2928                                                 g_assert_not_reached ();
2929                                         }
2930                                 }
2931                                 break;
2932                         case ArgValuetypeAddrInIReg:
2933                                 if (ainfo->pair_storage [0] == ArgInIReg)
2934                                         amd64_mov_reg_membase (code, ainfo->pair_regs [0], ins->inst_left->inst_basereg, ins->inst_left->inst_offset,  sizeof (gpointer));
2935                                 break;
2936                         default:
2937                                 break;
2938                         }
2939                 }
2940                 else {
2941                         g_assert (ainfo->storage == ArgInIReg);
2942
2943                         amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2944                 }
2945         }
2946
2947         return code;
2948 }
2949
2950 #define REAL_PRINT_REG(text,reg) \
2951 mono_assert (reg >= 0); \
2952 amd64_push_reg (code, AMD64_RAX); \
2953 amd64_push_reg (code, AMD64_RDX); \
2954 amd64_push_reg (code, AMD64_RCX); \
2955 amd64_push_reg (code, reg); \
2956 amd64_push_imm (code, reg); \
2957 amd64_push_imm (code, text " %d %p\n"); \
2958 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2959 amd64_call_reg (code, AMD64_RAX); \
2960 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2961 amd64_pop_reg (code, AMD64_RCX); \
2962 amd64_pop_reg (code, AMD64_RDX); \
2963 amd64_pop_reg (code, AMD64_RAX);
2964
2965 /* benchmark and set based on cpu */
2966 #define LOOP_ALIGNMENT 8
2967 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2968
2969 void
2970 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2971 {
2972         MonoInst *ins;
2973         MonoCallInst *call;
2974         guint offset;
2975         guint8 *code = cfg->native_code + cfg->code_len;
2976         MonoInst *last_ins = NULL;
2977         guint last_offset = 0;
2978         int max_len, cpos;
2979
2980         if (cfg->opt & MONO_OPT_LOOP) {
2981                 int pad, align = LOOP_ALIGNMENT;
2982                 /* set alignment depending on cpu */
2983                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2984                         pad = align - pad;
2985                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2986                         amd64_padding (code, pad);
2987                         cfg->code_len += pad;
2988                         bb->native_offset = cfg->code_len;
2989                 }
2990         }
2991
2992         if (cfg->verbose_level > 2)
2993                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2994
2995         cpos = bb->max_offset;
2996
2997         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2998                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2999                 g_assert (!cfg->compile_aot);
3000                 cpos += 6;
3001
3002                 cov->data [bb->dfn].cil_code = bb->cil_code;
3003                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3004                 /* this is not thread save, but good enough */
3005                 amd64_inc_membase (code, AMD64_R11, 0);
3006         }
3007
3008         offset = code - cfg->native_code;
3009
3010         mono_debug_open_block (cfg, bb, offset);
3011
3012         MONO_BB_FOR_EACH_INS (bb, ins) {
3013                 offset = code - cfg->native_code;
3014
3015                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3016
3017                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3018                         cfg->code_size *= 2;
3019                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3020                         code = cfg->native_code + offset;
3021                         mono_jit_stats.code_reallocs++;
3022                 }
3023
3024                 if (cfg->debug_info)
3025                         mono_debug_record_line_number (cfg, ins, offset);
3026
3027                 switch (ins->opcode) {
3028                 case OP_BIGMUL:
3029                         amd64_mul_reg (code, ins->sreg2, TRUE);
3030                         break;
3031                 case OP_BIGMUL_UN:
3032                         amd64_mul_reg (code, ins->sreg2, FALSE);
3033                         break;
3034                 case OP_X86_SETEQ_MEMBASE:
3035                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3036                         break;
3037                 case OP_STOREI1_MEMBASE_IMM:
3038                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3039                         break;
3040                 case OP_STOREI2_MEMBASE_IMM:
3041                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3042                         break;
3043                 case OP_STOREI4_MEMBASE_IMM:
3044                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3045                         break;
3046                 case OP_STOREI1_MEMBASE_REG:
3047                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3048                         break;
3049                 case OP_STOREI2_MEMBASE_REG:
3050                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3051                         break;
3052                 case OP_STORE_MEMBASE_REG:
3053                 case OP_STOREI8_MEMBASE_REG:
3054                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3055                         break;
3056                 case OP_STOREI4_MEMBASE_REG:
3057                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3058                         break;
3059                 case OP_STORE_MEMBASE_IMM:
3060                 case OP_STOREI8_MEMBASE_IMM:
3061                         g_assert (amd64_is_imm32 (ins->inst_imm));
3062                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3063                         break;
3064                 case OP_LOAD_MEM:
3065                 case OP_LOADI8_MEM:
3066                         // FIXME: Decompose this earlier
3067                         if (amd64_is_imm32 (ins->inst_imm))
3068                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3069                         else {
3070                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3071                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3072                         }
3073                         break;
3074                 case OP_LOADI4_MEM:
3075                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3076                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3077                         break;
3078                 case OP_LOADU4_MEM:
3079                         // FIXME: Decompose this earlier
3080                         if (cfg->new_ir) {
3081                                 if (amd64_is_imm32 (ins->inst_imm))
3082                                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3083                                 else {
3084                                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3085                                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3086                                 }
3087                         } else {
3088                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
3089                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3090                         }
3091                         break;
3092                 case OP_LOADU1_MEM:
3093                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3094                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3095                         break;
3096                 case OP_LOADU2_MEM:
3097                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3098                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3099                         break;
3100                 case OP_LOAD_MEMBASE:
3101                 case OP_LOADI8_MEMBASE:
3102                         g_assert (amd64_is_imm32 (ins->inst_offset));
3103                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3104                         break;
3105                 case OP_LOADI4_MEMBASE:
3106                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3107                         break;
3108                 case OP_LOADU4_MEMBASE:
3109                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3110                         break;
3111                 case OP_LOADU1_MEMBASE:
3112                         /* The cpu zero extends the result into 64 bits */
3113                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3114                         break;
3115                 case OP_LOADI1_MEMBASE:
3116                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3117                         break;
3118                 case OP_LOADU2_MEMBASE:
3119                         /* The cpu zero extends the result into 64 bits */
3120                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3121                         break;
3122                 case OP_LOADI2_MEMBASE:
3123                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3124                         break;
3125                 case OP_AMD64_LOADI8_MEMINDEX:
3126                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3127                         break;
3128                 case OP_LCONV_TO_I1:
3129                 case OP_ICONV_TO_I1:
3130                 case OP_SEXT_I1:
3131                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3132                         break;
3133                 case OP_LCONV_TO_I2:
3134                 case OP_ICONV_TO_I2:
3135                 case OP_SEXT_I2:
3136                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3137                         break;
3138                 case OP_LCONV_TO_U1:
3139                 case OP_ICONV_TO_U1:
3140                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3141                         break;
3142                 case OP_LCONV_TO_U2:
3143                 case OP_ICONV_TO_U2:
3144                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3145                         break;
3146                 case OP_ZEXT_I4:
3147                         /* Clean out the upper word */
3148                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3149                         break;
3150                 case OP_SEXT_I4:
3151                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3152                         break;
3153                 case OP_COMPARE:
3154                 case OP_LCOMPARE:
3155                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3156                         break;
3157                 case OP_COMPARE_IMM:
3158                 case OP_LCOMPARE_IMM:
3159                         g_assert (amd64_is_imm32 (ins->inst_imm));
3160                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3161                         break;
3162                 case OP_X86_COMPARE_REG_MEMBASE:
3163                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3164                         break;
3165                 case OP_X86_TEST_NULL:
3166                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3167                         break;
3168                 case OP_AMD64_TEST_NULL:
3169                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3170                         break;
3171
3172                 case OP_X86_ADD_REG_MEMBASE:
3173                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3174                         break;
3175                 case OP_X86_SUB_REG_MEMBASE:
3176                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3177                         break;
3178                 case OP_X86_AND_REG_MEMBASE:
3179                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3180                         break;
3181                 case OP_X86_OR_REG_MEMBASE:
3182                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3183                         break;
3184                 case OP_X86_XOR_REG_MEMBASE:
3185                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3186                         break;
3187
3188                 case OP_X86_ADD_MEMBASE_IMM:
3189                         /* FIXME: Make a 64 version too */
3190                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3191                         break;
3192                 case OP_X86_SUB_MEMBASE_IMM:
3193                         g_assert (amd64_is_imm32 (ins->inst_imm));
3194                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3195                         break;
3196                 case OP_X86_AND_MEMBASE_IMM:
3197                         g_assert (amd64_is_imm32 (ins->inst_imm));
3198                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3199                         break;
3200                 case OP_X86_OR_MEMBASE_IMM:
3201                         g_assert (amd64_is_imm32 (ins->inst_imm));
3202                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3203                         break;
3204                 case OP_X86_XOR_MEMBASE_IMM:
3205                         g_assert (amd64_is_imm32 (ins->inst_imm));
3206                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3207                         break;
3208                 case OP_X86_ADD_MEMBASE_REG:
3209                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3210                         break;
3211                 case OP_X86_SUB_MEMBASE_REG:
3212                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3213                         break;
3214                 case OP_X86_AND_MEMBASE_REG:
3215                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3216                         break;
3217                 case OP_X86_OR_MEMBASE_REG:
3218                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3219                         break;
3220                 case OP_X86_XOR_MEMBASE_REG:
3221                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3222                         break;
3223                 case OP_X86_INC_MEMBASE:
3224                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3225                         break;
3226                 case OP_X86_INC_REG:
3227                         amd64_inc_reg_size (code, ins->dreg, 4);
3228                         break;
3229                 case OP_X86_DEC_MEMBASE:
3230                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3231                         break;
3232                 case OP_X86_DEC_REG:
3233                         amd64_dec_reg_size (code, ins->dreg, 4);
3234                         break;
3235                 case OP_X86_MUL_REG_MEMBASE:
3236                 case OP_X86_MUL_MEMBASE_REG:
3237                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3238                         break;
3239                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3240                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3241                         break;
3242                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3243                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3244                         break;
3245                 case OP_AMD64_COMPARE_MEMBASE_REG:
3246                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3247                         break;
3248                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3249                         g_assert (amd64_is_imm32 (ins->inst_imm));
3250                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3251                         break;
3252                 case OP_X86_COMPARE_MEMBASE8_IMM:
3253                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3254                         break;
3255                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3256                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3257                         break;
3258                 case OP_AMD64_COMPARE_REG_MEMBASE:
3259                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3260                         break;
3261
3262                 case OP_AMD64_ADD_REG_MEMBASE:
3263                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3264                         break;
3265                 case OP_AMD64_SUB_REG_MEMBASE:
3266                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3267                         break;
3268                 case OP_AMD64_AND_REG_MEMBASE:
3269                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3270                         break;
3271                 case OP_AMD64_OR_REG_MEMBASE:
3272                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3273                         break;
3274                 case OP_AMD64_XOR_REG_MEMBASE:
3275                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3276                         break;
3277
3278                 case OP_AMD64_ADD_MEMBASE_REG:
3279                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3280                         break;
3281                 case OP_AMD64_SUB_MEMBASE_REG:
3282                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3283                         break;
3284                 case OP_AMD64_AND_MEMBASE_REG:
3285                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3286                         break;
3287                 case OP_AMD64_OR_MEMBASE_REG:
3288                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3289                         break;
3290                 case OP_AMD64_XOR_MEMBASE_REG:
3291                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3292                         break;
3293
3294                 case OP_AMD64_ADD_MEMBASE_IMM:
3295                         g_assert (amd64_is_imm32 (ins->inst_imm));
3296                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3297                         break;
3298                 case OP_AMD64_SUB_MEMBASE_IMM:
3299                         g_assert (amd64_is_imm32 (ins->inst_imm));
3300                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3301                         break;
3302                 case OP_AMD64_AND_MEMBASE_IMM:
3303                         g_assert (amd64_is_imm32 (ins->inst_imm));
3304                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3305                         break;
3306                 case OP_AMD64_OR_MEMBASE_IMM:
3307                         g_assert (amd64_is_imm32 (ins->inst_imm));
3308                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3309                         break;
3310                 case OP_AMD64_XOR_MEMBASE_IMM:
3311                         g_assert (amd64_is_imm32 (ins->inst_imm));
3312                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3313                         break;
3314
3315                 case OP_BREAK:
3316                         amd64_breakpoint (code);
3317                         break;
3318                 case OP_NOP:
3319                 case OP_DUMMY_USE:
3320                 case OP_DUMMY_STORE:
3321                 case OP_NOT_REACHED:
3322                 case OP_NOT_NULL:
3323                         break;
3324                 case OP_ADDCC:
3325                 case OP_LADD:
3326                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3327                         break;
3328                 case OP_ADC:
3329                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3330                         break;
3331                 case OP_ADD_IMM:
3332                 case OP_LADD_IMM:
3333                         g_assert (amd64_is_imm32 (ins->inst_imm));
3334                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3335                         break;
3336                 case OP_ADC_IMM:
3337                         g_assert (amd64_is_imm32 (ins->inst_imm));
3338                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3339                         break;
3340                 case OP_SUBCC:
3341                 case OP_LSUB:
3342                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3343                         break;
3344                 case OP_SBB:
3345                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3346                         break;
3347                 case OP_SUB_IMM:
3348                 case OP_LSUB_IMM:
3349                         g_assert (amd64_is_imm32 (ins->inst_imm));
3350                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3351                         break;
3352                 case OP_SBB_IMM:
3353                         g_assert (amd64_is_imm32 (ins->inst_imm));
3354                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3355                         break;
3356                 case OP_LAND:
3357                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3358                         break;
3359                 case OP_AND_IMM:
3360                 case OP_LAND_IMM:
3361                         g_assert (amd64_is_imm32 (ins->inst_imm));
3362                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3363                         break;
3364                 case OP_LMUL:
3365                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3366                         break;
3367                 case OP_MUL_IMM:
3368                 case OP_LMUL_IMM:
3369                 case OP_IMUL_IMM: {
3370                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3371
3372                         switch (ins->inst_imm) {
3373                         case 2:
3374                                 /* MOV r1, r2 */
3375                                 /* ADD r1, r1 */
3376                                 if (ins->dreg != ins->sreg1)
3377                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3378                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3379                                 break;
3380                         case 3:
3381                                 /* LEA r1, [r2 + r2*2] */
3382                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3383                                 break;
3384                         case 5:
3385                                 /* LEA r1, [r2 + r2*4] */
3386                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3387                                 break;
3388                         case 6:
3389                                 /* LEA r1, [r2 + r2*2] */
3390                                 /* ADD r1, r1          */
3391                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3392                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3393                                 break;
3394                         case 9:
3395                                 /* LEA r1, [r2 + r2*8] */
3396                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3397                                 break;
3398                         case 10:
3399                                 /* LEA r1, [r2 + r2*4] */
3400                                 /* ADD r1, r1          */
3401                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3402                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3403                                 break;
3404                         case 12:
3405                                 /* LEA r1, [r2 + r2*2] */
3406                                 /* SHL r1, 2           */
3407                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3408                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3409                                 break;
3410                         case 25:
3411                                 /* LEA r1, [r2 + r2*4] */
3412                                 /* LEA r1, [r1 + r1*4] */
3413                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3414                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3415                                 break;
3416                         case 100:
3417                                 /* LEA r1, [r2 + r2*4] */
3418                                 /* SHL r1, 2           */
3419                                 /* LEA r1, [r1 + r1*4] */
3420                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3421                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3422                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3423                                 break;
3424                         default:
3425                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3426                                 break;
3427                         }
3428                         break;
3429                 }
3430                 case OP_LDIV:
3431                 case OP_LREM:
3432                         /* Regalloc magic makes the div/rem cases the same */
3433                         if (ins->sreg2 == AMD64_RDX) {
3434                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3435                                 amd64_cdq (code);
3436                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3437                         } else {
3438                                 amd64_cdq (code);
3439                                 amd64_div_reg (code, ins->sreg2, TRUE);
3440                         }
3441                         break;
3442                 case OP_LDIV_UN:
3443                 case OP_LREM_UN:
3444                         if (ins->sreg2 == AMD64_RDX) {
3445                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3446                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3447                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3448                         } else {
3449                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3450                                 amd64_div_reg (code, ins->sreg2, FALSE);
3451                         }
3452                         break;
3453                 case OP_IDIV:
3454                 case OP_IREM:
3455                         if (ins->sreg2 == AMD64_RDX) {
3456                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3457                                 amd64_cdq_size (code, 4);
3458                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3459                         } else {
3460                                 amd64_cdq_size (code, 4);
3461                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3462                         }
3463                         break;
3464                 case OP_IDIV_UN:
3465                 case OP_IREM_UN:
3466                         if (ins->sreg2 == AMD64_RDX) {
3467                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3468                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3469                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3470                         } else {
3471                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3472                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3473                         }
3474                         break;
3475                 case OP_LMUL_OVF:
3476                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3477                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3478                         break;
3479                 case OP_LOR:
3480                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3481                         break;
3482                 case OP_OR_IMM:
3483                 case OP_LOR_IMM:
3484                         g_assert (amd64_is_imm32 (ins->inst_imm));
3485                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3486                         break;
3487                 case OP_LXOR:
3488                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3489                         break;
3490                 case OP_XOR_IMM:
3491                 case OP_LXOR_IMM:
3492                         g_assert (amd64_is_imm32 (ins->inst_imm));
3493                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3494                         break;
3495                 case OP_LSHL:
3496                         g_assert (ins->sreg2 == AMD64_RCX);
3497                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3498                         break;
3499                 case OP_LSHR:
3500                         g_assert (ins->sreg2 == AMD64_RCX);
3501                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3502                         break;
3503                 case OP_SHR_IMM:
3504                         g_assert (amd64_is_imm32 (ins->inst_imm));
3505                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3506                         break;
3507                 case OP_LSHR_IMM:
3508                         g_assert (amd64_is_imm32 (ins->inst_imm));
3509                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3510                         break;
3511                 case OP_SHR_UN_IMM:
3512                         g_assert (amd64_is_imm32 (ins->inst_imm));
3513                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3514                         break;
3515                 case OP_LSHR_UN_IMM:
3516                         g_assert (amd64_is_imm32 (ins->inst_imm));
3517                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3518                         break;
3519                 case OP_LSHR_UN:
3520                         g_assert (ins->sreg2 == AMD64_RCX);
3521                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3522                         break;
3523                 case OP_SHL_IMM:
3524                         g_assert (amd64_is_imm32 (ins->inst_imm));
3525                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3526                         break;
3527                 case OP_LSHL_IMM:
3528                         g_assert (amd64_is_imm32 (ins->inst_imm));
3529                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3530                         break;
3531
3532                 case OP_IADDCC:
3533                 case OP_IADD:
3534                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3535                         break;
3536                 case OP_IADC:
3537                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3538                         break;
3539                 case OP_IADD_IMM:
3540                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3541                         break;
3542                 case OP_IADC_IMM:
3543                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3544                         break;
3545                 case OP_ISUBCC:
3546                 case OP_ISUB:
3547                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3548                         break;
3549                 case OP_ISBB:
3550                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3551                         break;
3552                 case OP_ISUB_IMM:
3553                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3554                         break;
3555                 case OP_ISBB_IMM:
3556                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3557                         break;
3558                 case OP_IAND:
3559                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3560                         break;
3561                 case OP_IAND_IMM:
3562                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3563                         break;
3564                 case OP_IOR:
3565                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3566                         break;
3567                 case OP_IOR_IMM:
3568                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3569                         break;
3570                 case OP_IXOR:
3571                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3572                         break;
3573                 case OP_IXOR_IMM:
3574                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3575                         break;
3576                 case OP_INEG:
3577                         amd64_neg_reg_size (code, ins->sreg1, 4);
3578                         break;
3579                 case OP_INOT:
3580                         amd64_not_reg_size (code, ins->sreg1, 4);
3581                         break;
3582                 case OP_ISHL:
3583                         g_assert (ins->sreg2 == AMD64_RCX);
3584                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3585                         break;
3586                 case OP_ISHR:
3587                         g_assert (ins->sreg2 == AMD64_RCX);
3588                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3589                         break;
3590                 case OP_ISHR_IMM:
3591                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3592                         break;
3593                 case OP_ISHR_UN_IMM:
3594                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3595                         break;
3596                 case OP_ISHR_UN:
3597                         g_assert (ins->sreg2 == AMD64_RCX);
3598                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3599                         break;
3600                 case OP_ISHL_IMM:
3601                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3602                         break;
3603                 case OP_IMUL:
3604                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3605                         break;
3606                 case OP_IMUL_OVF:
3607                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3608                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3609                         break;
3610                 case OP_IMUL_OVF_UN:
3611                 case OP_LMUL_OVF_UN: {
3612                         /* the mul operation and the exception check should most likely be split */
3613                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3614                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3615                         /*g_assert (ins->sreg2 == X86_EAX);
3616                         g_assert (ins->dreg == X86_EAX);*/
3617                         if (ins->sreg2 == X86_EAX) {
3618                                 non_eax_reg = ins->sreg1;
3619                         } else if (ins->sreg1 == X86_EAX) {
3620                                 non_eax_reg = ins->sreg2;
3621                         } else {
3622                                 /* no need to save since we're going to store to it anyway */
3623                                 if (ins->dreg != X86_EAX) {
3624                                         saved_eax = TRUE;
3625                                         amd64_push_reg (code, X86_EAX);
3626                                 }
3627                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3628                                 non_eax_reg = ins->sreg2;
3629                         }
3630                         if (ins->dreg == X86_EDX) {
3631                                 if (!saved_eax) {
3632                                         saved_eax = TRUE;
3633                                         amd64_push_reg (code, X86_EAX);
3634                                 }
3635                         } else {
3636                                 saved_edx = TRUE;
3637                                 amd64_push_reg (code, X86_EDX);
3638                         }
3639                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3640                         /* save before the check since pop and mov don't change the flags */
3641                         if (ins->dreg != X86_EAX)
3642                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3643                         if (saved_edx)
3644                                 amd64_pop_reg (code, X86_EDX);
3645                         if (saved_eax)
3646                                 amd64_pop_reg (code, X86_EAX);
3647                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3648                         break;
3649                 }
3650                 case OP_ICOMPARE:
3651                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3652                         break;
3653                 case OP_ICOMPARE_IMM:
3654                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3655                         break;
3656                 case OP_IBEQ:
3657                 case OP_IBLT:
3658                 case OP_IBGT:
3659                 case OP_IBGE:
3660                 case OP_IBLE:
3661                 case OP_LBEQ:
3662                 case OP_LBLT:
3663                 case OP_LBGT:
3664                 case OP_LBGE:
3665                 case OP_LBLE:
3666                 case OP_IBNE_UN:
3667                 case OP_IBLT_UN:
3668                 case OP_IBGT_UN:
3669                 case OP_IBGE_UN:
3670                 case OP_IBLE_UN:
3671                 case OP_LBNE_UN:
3672                 case OP_LBLT_UN:
3673                 case OP_LBGT_UN:
3674                 case OP_LBGE_UN:
3675                 case OP_LBLE_UN:
3676                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3677                         break;
3678
3679                 case OP_CMOV_IEQ:
3680                 case OP_CMOV_IGE:
3681                 case OP_CMOV_IGT:
3682                 case OP_CMOV_ILE:
3683                 case OP_CMOV_ILT:
3684                 case OP_CMOV_INE_UN:
3685                 case OP_CMOV_IGE_UN:
3686                 case OP_CMOV_IGT_UN:
3687                 case OP_CMOV_ILE_UN:
3688                 case OP_CMOV_ILT_UN:
3689                 case OP_CMOV_LEQ:
3690                 case OP_CMOV_LGE:
3691                 case OP_CMOV_LGT:
3692                 case OP_CMOV_LLE:
3693                 case OP_CMOV_LLT:
3694                 case OP_CMOV_LNE_UN:
3695                 case OP_CMOV_LGE_UN:
3696                 case OP_CMOV_LGT_UN:
3697                 case OP_CMOV_LLE_UN:
3698                 case OP_CMOV_LLT_UN:
3699                         g_assert (ins->dreg == ins->sreg1);
3700                         /* This needs to operate on 64 bit values */
3701                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3702                         break;
3703
3704                 case OP_LNOT:
3705                         amd64_not_reg (code, ins->sreg1);
3706                         break;
3707                 case OP_LNEG:
3708                         amd64_neg_reg (code, ins->sreg1);
3709                         break;
3710
3711                 case OP_ICONST:
3712                 case OP_I8CONST:
3713                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3714                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3715                         else
3716                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3717                         break;
3718                 case OP_AOTCONST:
3719                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3720                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3721                         break;
3722                 case OP_JUMP_TABLE:
3723                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3724                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3725                         break;
3726                 case OP_MOVE:
3727                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3728                         break;
3729                 case OP_AMD64_SET_XMMREG_R4: {
3730                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3731                         break;
3732                 }
3733                 case OP_AMD64_SET_XMMREG_R8: {
3734                         if (ins->dreg != ins->sreg1)
3735                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3736                         break;
3737                 }
3738                 case OP_JMP:
3739                 case OP_TAILCALL: {
3740                         /*
3741                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3742                          * Keep in sync with the code in emit_epilog.
3743                          */
3744                         int pos = 0, i;
3745
3746                         /* FIXME: no tracing support... */
3747                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3748                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3749
3750                         g_assert (!cfg->method->save_lmf);
3751
3752                         if (ins->opcode == OP_JMP)
3753                                 code = emit_load_volatile_arguments (cfg, code);
3754
3755                         if (cfg->arch.omit_fp) {
3756                                 guint32 save_offset = 0;
3757                                 /* Pop callee-saved registers */
3758                                 for (i = 0; i < AMD64_NREG; ++i)
3759                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3760                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3761                                                 save_offset += 8;
3762                                         }
3763                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3764                         }
3765                         else {
3766                                 for (i = 0; i < AMD64_NREG; ++i)
3767                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3768                                                 pos -= sizeof (gpointer);
3769
3770                                 if (pos)
3771                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3772
3773                                 /* Pop registers in reverse order */
3774                                 for (i = AMD64_NREG - 1; i > 0; --i)
3775                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3776                                                 amd64_pop_reg (code, i);
3777                                         }
3778
3779                                 amd64_leave (code);
3780                         }
3781
3782                         offset = code - cfg->native_code;
3783                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3784                         if (cfg->compile_aot)
3785                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3786                         else
3787                                 amd64_set_reg_template (code, AMD64_R11);
3788                         amd64_jump_reg (code, AMD64_R11);
3789                         break;
3790                 }
3791                 case OP_CHECK_THIS:
3792                         /* ensure ins->sreg1 is not NULL */
3793                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3794                         break;
3795                 case OP_ARGLIST: {
3796                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3797                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3798                         break;
3799                 }
3800                 case OP_CALL:
3801                 case OP_FCALL:
3802                 case OP_LCALL:
3803                 case OP_VCALL:
3804                 case OP_VCALL2:
3805                 case OP_VOIDCALL:
3806                         call = (MonoCallInst*)ins;
3807                         /*
3808                          * The AMD64 ABI forces callers to know about varargs.
3809                          */
3810                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3811                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3812                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3813                                 /*
3814                                  * Since the unmanaged calling convention doesn't contain a
3815                                  * 'vararg' entry, we have to treat every pinvoke call as a
3816                                  * potential vararg call.
3817                                  */
3818                                 guint32 nregs, i;
3819                                 nregs = 0;
3820                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3821                                         if (call->used_fregs & (1 << i))
3822                                                 nregs ++;
3823                                 if (!nregs)
3824                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3825                                 else
3826                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3827                         }
3828
3829                         if (ins->flags & MONO_INST_HAS_METHOD)
3830                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3831                         else
3832                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3833                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3834                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3835                         code = emit_move_return_value (cfg, ins, code);
3836                         break;
3837                 case OP_FCALL_REG:
3838                 case OP_LCALL_REG:
3839                 case OP_VCALL_REG:
3840                 case OP_VCALL2_REG:
3841                 case OP_VOIDCALL_REG:
3842                 case OP_CALL_REG:
3843                         call = (MonoCallInst*)ins;
3844
3845                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3846                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3847                                 ins->sreg1 = AMD64_R11;
3848                         }
3849
3850                         /*
3851                          * The AMD64 ABI forces callers to know about varargs.
3852                          */
3853                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3854                                 if (ins->sreg1 == AMD64_RAX) {
3855                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3856                                         ins->sreg1 = AMD64_R11;
3857                                 }
3858                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3859                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3860                                 /*
3861                                  * Since the unmanaged calling convention doesn't contain a
3862                                  * 'vararg' entry, we have to treat every pinvoke call as a
3863                                  * potential vararg call.
3864                                  */
3865                                 guint32 nregs, i;
3866                                 nregs = 0;
3867                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3868                                         if (call->used_fregs & (1 << i))
3869                                                 nregs ++;
3870                                 if (ins->sreg1 == AMD64_RAX) {
3871                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3872                                         ins->sreg1 = AMD64_R11;
3873                                 }
3874                                 if (!nregs)
3875                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3876                                 else
3877                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3878                         }
3879
3880                         amd64_call_reg (code, ins->sreg1);
3881                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3882                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3883                         code = emit_move_return_value (cfg, ins, code);
3884                         break;
3885                 case OP_FCALL_MEMBASE:
3886                 case OP_LCALL_MEMBASE:
3887                 case OP_VCALL_MEMBASE:
3888                 case OP_VCALL2_MEMBASE:
3889                 case OP_VOIDCALL_MEMBASE:
3890                 case OP_CALL_MEMBASE:
3891                         call = (MonoCallInst*)ins;
3892
3893                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3894                                 /*
3895                                  * Can't use R11 because it is clobbered by the trampoline
3896                                  * code, and the reg value is needed by get_vcall_slot_addr.
3897                                  */
3898                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3899                                 ins->sreg1 = AMD64_RAX;
3900                         }
3901
3902                         if (call->method && ins->inst_offset < 0) {
3903                                 gssize val;
3904
3905                                 /*
3906                                  * This is a possible IMT call so save the IMT method in the proper
3907                                  * register. We don't use the generic code in method-to-ir.c, because
3908                                  * we need to disassemble this in get_vcall_slot_addr (), so we have to
3909                                  * maintain control over the layout of the code.
3910                                  * Also put the base reg in %rax to simplify find_imt_method ().
3911                                  */
3912                                 if (ins->sreg1 != AMD64_RAX) {
3913                                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3914                                         ins->sreg1 = AMD64_RAX;
3915                                 }
3916                                 val = (gssize)(gpointer)call->method;
3917
3918                                 // FIXME: Generics sharing
3919 #if 0
3920                                 if ((((guint64)val) >> 32) == 0)
3921                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3922                                 else
3923                                         amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3924 #endif
3925                         }
3926
3927                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3928                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3929                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3930                         code = emit_move_return_value (cfg, ins, code);
3931                         break;
3932                 case OP_AMD64_SAVE_SP_TO_LMF:
3933                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3934                         break;
3935                 case OP_OUTARG:
3936                 case OP_X86_PUSH:
3937                         amd64_push_reg (code, ins->sreg1);
3938                         break;
3939                 case OP_X86_PUSH_IMM:
3940                         g_assert (amd64_is_imm32 (ins->inst_imm));
3941                         amd64_push_imm (code, ins->inst_imm);
3942                         break;
3943                 case OP_X86_PUSH_MEMBASE:
3944                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3945                         break;
3946                 case OP_X86_PUSH_OBJ:
3947                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3948                         amd64_push_reg (code, AMD64_RDI);
3949                         amd64_push_reg (code, AMD64_RSI);
3950                         amd64_push_reg (code, AMD64_RCX);
3951                         if (ins->inst_offset)
3952                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3953                         else
3954                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3955                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3956                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3957                         amd64_cld (code);
3958                         amd64_prefix (code, X86_REP_PREFIX);
3959                         amd64_movsd (code);
3960                         amd64_pop_reg (code, AMD64_RCX);
3961                         amd64_pop_reg (code, AMD64_RSI);
3962                         amd64_pop_reg (code, AMD64_RDI);
3963                         break;
3964                 case OP_X86_LEA:
3965                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3966                         break;
3967                 case OP_X86_LEA_MEMBASE:
3968                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3969                         break;
3970                 case OP_X86_XCHG:
3971                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3972                         break;
3973                 case OP_LOCALLOC:
3974                         /* keep alignment */
3975                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3976                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3977                         code = mono_emit_stack_alloc (code, ins);
3978                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3979                         break;
3980                 case OP_LOCALLOC_IMM: {
3981                         guint32 size = ins->inst_imm;
3982                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3983
3984                         if (ins->flags & MONO_INST_INIT) {
3985                                 if (size < 64) {
3986                                         int i;
3987
3988                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3989                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3990
3991                                         for (i = 0; i < size; i += 8)
3992                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
3993                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3994                                 } else {
3995                                         amd64_mov_reg_imm (code, ins->dreg, size);
3996                                         ins->sreg1 = ins->dreg;
3997
3998                                         code = mono_emit_stack_alloc (code, ins);
3999                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4000                                 }
4001                         } else {
4002                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4003                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4004                         }
4005                         break;
4006                 }
4007                 case OP_THROW: {
4008                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4009                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4010                                              (gpointer)"mono_arch_throw_exception", FALSE);
4011                         break;
4012                 }
4013                 case OP_RETHROW: {
4014                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4015                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4016                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4017                         break;
4018                 }
4019                 case OP_CALL_HANDLER:
4020                         /* Align stack */
4021                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4022                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4023                         amd64_call_imm (code, 0);
4024                         /* Restore stack alignment */
4025                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4026                         break;
4027                 case OP_START_HANDLER: {
4028                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4029                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4030                         break;
4031                 }
4032                 case OP_ENDFINALLY: {
4033                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4034                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4035                         amd64_ret (code);
4036                         break;
4037                 }
4038                 case OP_ENDFILTER: {
4039                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4040                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4041                         /* The local allocator will put the result into RAX */
4042                         amd64_ret (code);
4043                         break;
4044                 }
4045
4046                 case OP_LABEL:
4047                         ins->inst_c0 = code - cfg->native_code;
4048                         break;
4049                 case OP_BR:
4050                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4051                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4052                         //break;
4053                         if (ins->flags & MONO_INST_BRLABEL) {
4054                                 if (ins->inst_i0->inst_c0) {
4055                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
4056                                 } else {
4057                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
4058                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4059                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
4060                                                 x86_jump8 (code, 0);
4061                                         else
4062                                                 x86_jump32 (code, 0);
4063                                 }
4064                         } else {
4065                                 if (ins->inst_target_bb->native_offset) {
4066                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4067                                 } else {
4068                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4069                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4070                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
4071                                                 x86_jump8 (code, 0);
4072                                         else
4073                                                 x86_jump32 (code, 0);
4074                                 }
4075                         }
4076                         break;
4077                 case OP_BR_REG:
4078                         amd64_jump_reg (code, ins->sreg1);
4079                         break;
4080                 case OP_CEQ:
4081                 case OP_LCEQ:
4082                 case OP_ICEQ:
4083                 case OP_CLT:
4084                 case OP_LCLT:
4085                 case OP_ICLT:
4086                 case OP_CGT:
4087                 case OP_ICGT:
4088                 case OP_LCGT:
4089                 case OP_CLT_UN:
4090                 case OP_LCLT_UN:
4091                 case OP_ICLT_UN:
4092                 case OP_CGT_UN:
4093                 case OP_LCGT_UN:
4094                 case OP_ICGT_UN:
4095                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4096                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4097                         break;
4098                 case OP_COND_EXC_EQ:
4099                 case OP_COND_EXC_NE_UN:
4100                 case OP_COND_EXC_LT:
4101                 case OP_COND_EXC_LT_UN:
4102                 case OP_COND_EXC_GT:
4103                 case OP_COND_EXC_GT_UN:
4104                 case OP_COND_EXC_GE:
4105                 case OP_COND_EXC_GE_UN:
4106                 case OP_COND_EXC_LE:
4107                 case OP_COND_EXC_LE_UN:
4108                 case OP_COND_EXC_IEQ:
4109                 case OP_COND_EXC_INE_UN:
4110                 case OP_COND_EXC_ILT:
4111                 case OP_COND_EXC_ILT_UN:
4112                 case OP_COND_EXC_IGT:
4113                 case OP_COND_EXC_IGT_UN:
4114                 case OP_COND_EXC_IGE:
4115                 case OP_COND_EXC_IGE_UN:
4116                 case OP_COND_EXC_ILE:
4117                 case OP_COND_EXC_ILE_UN:
4118                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4119                         break;
4120                 case OP_COND_EXC_OV:
4121                 case OP_COND_EXC_NO:
4122                 case OP_COND_EXC_C:
4123                 case OP_COND_EXC_NC:
4124                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4125                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4126                         break;
4127                 case OP_COND_EXC_IOV:
4128                 case OP_COND_EXC_INO:
4129                 case OP_COND_EXC_IC:
4130                 case OP_COND_EXC_INC:
4131                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4132                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4133                         break;
4134
4135                 /* floating point opcodes */
4136                 case OP_R8CONST: {
4137                         double d = *(double *)ins->inst_p0;
4138
4139                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4140                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4141                         }
4142                         else {
4143                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4144                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4145                         }
4146                         break;
4147                 }
4148                 case OP_R4CONST: {
4149                         float f = *(float *)ins->inst_p0;
4150
4151                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4152                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4153                         }
4154                         else {
4155                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4156                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4157                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4158                         }
4159                         break;
4160                 }
4161                 case OP_STORER8_MEMBASE_REG:
4162                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4163                         break;
4164                 case OP_LOADR8_SPILL_MEMBASE:
4165                         g_assert_not_reached ();
4166                         break;
4167                 case OP_LOADR8_MEMBASE:
4168                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4169                         break;
4170                 case OP_STORER4_MEMBASE_REG:
4171                         /* This requires a double->single conversion */
4172                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4173                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4174                         break;
4175                 case OP_LOADR4_MEMBASE:
4176                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4177                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4178                         break;
4179                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4180                 case OP_ICONV_TO_R8:
4181                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4182                         break;
4183                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4184                 case OP_LCONV_TO_R8:
4185                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4186                         break;
4187                 case OP_FCONV_TO_R4:
4188                         /* FIXME: nothing to do ?? */
4189                         break;
4190                 case OP_FCONV_TO_I1:
4191                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4192                         break;
4193                 case OP_FCONV_TO_U1:
4194                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4195                         break;
4196                 case OP_FCONV_TO_I2:
4197                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4198                         break;
4199                 case OP_FCONV_TO_U2:
4200                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4201                         break;
4202                 case OP_FCONV_TO_U4:
4203                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4204                         break;
4205                 case OP_FCONV_TO_I4:
4206                 case OP_FCONV_TO_I:
4207                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4208                         break;
4209                 case OP_FCONV_TO_I8:
4210                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4211                         break;
4212                 case OP_LCONV_TO_R_UN: {
4213                         guint8 *br [2];
4214
4215                         /* Based on gcc code */
4216                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4217                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4218
4219                         /* Positive case */
4220                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4221                         br [1] = code; x86_jump8 (code, 0);
4222                         amd64_patch (br [0], code);
4223
4224                         /* Negative case */
4225                         /* Save to the red zone */
4226                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4227                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4228                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4229                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4230                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4231                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4232                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4233                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4234                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4235                         /* Restore */
4236                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4237                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4238                         amd64_patch (br [1], code);
4239                         break;
4240                 }
4241                 case OP_LCONV_TO_OVF_U4:
4242                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4243                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4244                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4245                         break;
4246                 case OP_LCONV_TO_OVF_I4_UN:
4247                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4248                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4249                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4250                         break;
4251                 case OP_FMOVE:
4252                         if (ins->dreg != ins->sreg1)
4253                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4254                         break;
4255                 case OP_FADD:
4256                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4257                         break;
4258                 case OP_FSUB:
4259                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4260                         break;
4261                 case OP_FMUL:
4262                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4263                         break;
4264                 case OP_FDIV:
4265                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4266                         break;
4267                 case OP_FNEG: {
4268                         static double r8_0 = -0.0;
4269
4270                         g_assert (ins->sreg1 == ins->dreg);
4271
4272                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4273                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4274                         break;
4275                 }
4276                 case OP_SIN:
4277                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4278                         break;
4279                 case OP_COS:
4280                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4281                         break;
4282                 case OP_ABS: {
4283                         static guint64 d = 0x7fffffffffffffffUL;
4284
4285                         g_assert (ins->sreg1 == ins->dreg);
4286
4287                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4288                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4289                         break;
4290                 }
4291                 case OP_SQRT:
4292                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4293                         break;
4294                 case OP_IMIN:
4295                         g_assert (cfg->opt & MONO_OPT_CMOV);
4296                         g_assert (ins->dreg == ins->sreg1);
4297                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4298                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4299                         break;
4300                 case OP_IMIN_UN:
4301                         g_assert (cfg->opt & MONO_OPT_CMOV);
4302                         g_assert (ins->dreg == ins->sreg1);
4303                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4304                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4305                         break;
4306                 case OP_IMAX:
4307                         g_assert (cfg->opt & MONO_OPT_CMOV);
4308                         g_assert (ins->dreg == ins->sreg1);
4309                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4310                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4311                         break;
4312                 case OP_IMAX_UN:
4313                         g_assert (cfg->opt & MONO_OPT_CMOV);
4314                         g_assert (ins->dreg == ins->sreg1);
4315                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4316                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4317                         break;
4318                 case OP_LMIN:
4319                         g_assert (cfg->opt & MONO_OPT_CMOV);
4320                         g_assert (ins->dreg == ins->sreg1);
4321                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4322                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4323                         break;
4324                 case OP_LMIN_UN:
4325                         g_assert (cfg->opt & MONO_OPT_CMOV);
4326                         g_assert (ins->dreg == ins->sreg1);
4327                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4328                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4329                         break;
4330                 case OP_LMAX:
4331                         g_assert (cfg->opt & MONO_OPT_CMOV);
4332                         g_assert (ins->dreg == ins->sreg1);
4333                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4334                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4335                         break;
4336                 case OP_LMAX_UN:
4337                         g_assert (cfg->opt & MONO_OPT_CMOV);
4338                         g_assert (ins->dreg == ins->sreg1);
4339                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4340                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4341                         break;
4342                 case OP_X86_FPOP:
4343                         break;
4344                 case OP_FCOMPARE:
4345                         /*
4346                          * The two arguments are swapped because the fbranch instructions
4347                          * depend on this for the non-sse case to work.
4348                          */
4349                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4350                         break;
4351                 case OP_FCEQ: {
4352                         /* zeroing the register at the start results in
4353                          * shorter and faster code (we can also remove the widening op)
4354                          */
4355                         guchar *unordered_check;
4356                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4357                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4358                         unordered_check = code;
4359                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4360                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4361                         amd64_patch (unordered_check, code);
4362                         break;
4363                 }
4364                 case OP_FCLT:
4365                 case OP_FCLT_UN:
4366                         /* zeroing the register at the start results in
4367                          * shorter and faster code (we can also remove the widening op)
4368                          */
4369                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4370                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4371                         if (ins->opcode == OP_FCLT_UN) {
4372                                 guchar *unordered_check = code;
4373                                 guchar *jump_to_end;
4374                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4375                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4376                                 jump_to_end = code;
4377                                 x86_jump8 (code, 0);
4378                                 amd64_patch (unordered_check, code);
4379                                 amd64_inc_reg (code, ins->dreg);
4380                                 amd64_patch (jump_to_end, code);
4381                         } else {
4382                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4383                         }
4384                         break;
4385                 case OP_FCGT:
4386                 case OP_FCGT_UN: {
4387                         /* zeroing the register at the start results in
4388                          * shorter and faster code (we can also remove the widening op)
4389                          */
4390                         guchar *unordered_check;
4391                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4392                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4393                         if (ins->opcode == OP_FCGT) {
4394                                 unordered_check = code;
4395                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4396                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4397                                 amd64_patch (unordered_check, code);
4398                         } else {
4399                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4400                         }
4401                         break;
4402                 }
4403                 case OP_FCLT_MEMBASE:
4404                 case OP_FCGT_MEMBASE:
4405                 case OP_FCLT_UN_MEMBASE:
4406                 case OP_FCGT_UN_MEMBASE:
4407                 case OP_FCEQ_MEMBASE: {
4408                         guchar *unordered_check, *jump_to_end;
4409                         int x86_cond;
4410
4411                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4412                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4413
4414                         switch (ins->opcode) {
4415                         case OP_FCEQ_MEMBASE:
4416                                 x86_cond = X86_CC_EQ;
4417                                 break;
4418                         case OP_FCLT_MEMBASE:
4419                         case OP_FCLT_UN_MEMBASE:
4420                                 x86_cond = X86_CC_LT;
4421                                 break;
4422                         case OP_FCGT_MEMBASE:
4423                         case OP_FCGT_UN_MEMBASE:
4424                                 x86_cond = X86_CC_GT;
4425                                 break;
4426                         default:
4427                                 g_assert_not_reached ();
4428                         }
4429
4430                         unordered_check = code;
4431                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4432                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4433
4434                         switch (ins->opcode) {
4435                         case OP_FCEQ_MEMBASE:
4436                         case OP_FCLT_MEMBASE:
4437                         case OP_FCGT_MEMBASE:
4438                                 amd64_patch (unordered_check, code);
4439                                 break;
4440                         case OP_FCLT_UN_MEMBASE:
4441                         case OP_FCGT_UN_MEMBASE:
4442                                 jump_to_end = code;
4443                                 x86_jump8 (code, 0);
4444                                 amd64_patch (unordered_check, code);
4445                                 amd64_inc_reg (code, ins->dreg);
4446                                 amd64_patch (jump_to_end, code);
4447                                 break;
4448                         default:
4449                                 break;
4450                         }
4451                         break;
4452                 }
4453                 case OP_FBEQ: {
4454                         guchar *jump = code;
4455                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4456                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4457                         amd64_patch (jump, code);
4458                         break;
4459                 }
4460                 case OP_FBNE_UN:
4461                         /* Branch if C013 != 100 */
4462                         /* branch if !ZF or (PF|CF) */
4463                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4464                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4465                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4466                         break;
4467                 case OP_FBLT:
4468                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4469                         break;
4470                 case OP_FBLT_UN:
4471                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4472                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4473                         break;
4474                 case OP_FBGT:
4475                 case OP_FBGT_UN:
4476                         if (ins->opcode == OP_FBGT) {
4477                                 guchar *br1;
4478
4479                                 /* skip branch if C1=1 */
4480                                 br1 = code;
4481                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4482                                 /* branch if (C0 | C3) = 1 */
4483                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4484                                 amd64_patch (br1, code);
4485                                 break;
4486                         } else {
4487                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4488                         }
4489                         break;
4490                 case OP_FBGE: {
4491                         /* Branch if C013 == 100 or 001 */
4492                         guchar *br1;
4493
4494                         /* skip branch if C1=1 */
4495                         br1 = code;
4496                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4497                         /* branch if (C0 | C3) = 1 */
4498                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4499                         amd64_patch (br1, code);
4500                         break;
4501                 }
4502                 case OP_FBGE_UN:
4503                         /* Branch if C013 == 000 */
4504                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4505                         break;
4506                 case OP_FBLE: {
4507                         /* Branch if C013=000 or 100 */
4508                         guchar *br1;
4509
4510                         /* skip branch if C1=1 */
4511                         br1 = code;
4512                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4513                         /* branch if C0=0 */
4514                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4515                         amd64_patch (br1, code);
4516                         break;
4517                 }
4518                 case OP_FBLE_UN:
4519                         /* Branch if C013 != 001 */
4520                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4521                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4522                         break;
4523                 case OP_CKFINITE:
4524                         /* Transfer value to the fp stack */
4525                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4526                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4527                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4528
4529                         amd64_push_reg (code, AMD64_RAX);
4530                         amd64_fxam (code);
4531                         amd64_fnstsw (code);
4532                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4533                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4534                         amd64_pop_reg (code, AMD64_RAX);
4535                         amd64_fstp (code, 0);
4536                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4537                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4538                         break;
4539                 case OP_TLS_GET: {
4540                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4541                         break;
4542                 }
4543                 case OP_MEMORY_BARRIER: {
4544                         /* Not needed on amd64 */
4545                         break;
4546                 }
4547                 case OP_ATOMIC_ADD_I4:
4548                 case OP_ATOMIC_ADD_I8: {
4549                         int dreg = ins->dreg;
4550                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4551
4552                         if (dreg == ins->inst_basereg)
4553                                 dreg = AMD64_R11;
4554
4555                         if (dreg != ins->sreg2)
4556                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4557
4558                         x86_prefix (code, X86_LOCK_PREFIX);
4559                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4560
4561                         if (dreg != ins->dreg)
4562                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4563
4564                         break;
4565                 }
4566                 case OP_ATOMIC_ADD_NEW_I4:
4567                 case OP_ATOMIC_ADD_NEW_I8: {
4568                         int dreg = ins->dreg;
4569                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4570
4571                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4572                                 dreg = AMD64_R11;
4573
4574                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4575                         amd64_prefix (code, X86_LOCK_PREFIX);
4576                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4577                         /* dreg contains the old value, add with sreg2 value */
4578                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4579
4580                         if (ins->dreg != dreg)
4581                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4582
4583                         break;
4584                 }
4585                 case OP_ATOMIC_EXCHANGE_I4:
4586                 case OP_ATOMIC_EXCHANGE_I8:
4587                 case OP_ATOMIC_CAS_IMM_I4: {
4588                         guchar *br[2];
4589                         int sreg2 = ins->sreg2;
4590                         int breg = ins->inst_basereg;
4591                         guint32 size;
4592                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4593
4594                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4595                                 size = 8;
4596                         else
4597                                 size = 4;
4598
4599                         /*
4600                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4601                          * an explanation of how this works.
4602                          */
4603
4604                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4605                          * hack to overcome limits in x86 reg allocator
4606                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4607                          */
4608                         g_assert (ins->dreg == AMD64_RAX);
4609
4610                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4611                                 /* Highly unlikely, but possible */
4612                                 need_push = TRUE;
4613
4614                         /* The pushes invalidate rsp */
4615                         if ((breg == AMD64_RAX) || need_push) {
4616                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4617                                 breg = AMD64_R11;
4618                         }
4619
4620                         /* We need the EAX reg for the comparand */
4621                         if (ins->sreg2 == AMD64_RAX) {
4622                                 if (breg != AMD64_R11) {
4623                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4624                                         sreg2 = AMD64_R11;
4625                                 } else {
4626                                         g_assert (need_push);
4627                                         amd64_push_reg (code, AMD64_RDX);
4628                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4629                                         sreg2 = AMD64_RDX;
4630                                         rdx_pushed = TRUE;
4631                                 }
4632                         }
4633
4634                         if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4635                                 if (ins->backend.data == NULL)
4636                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4637                                 else
4638                                         amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4639
4640                                 amd64_prefix (code, X86_LOCK_PREFIX);
4641                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4642                         } else {
4643                                 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4644
4645                                 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4646                                 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4647                                 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4648                                 amd64_patch (br [1], br [0]);
4649                         }
4650
4651                         if (rdx_pushed)
4652                                 amd64_pop_reg (code, AMD64_RDX);
4653
4654                         break;
4655                 }
4656                 default:
4657                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4658                         g_assert_not_reached ();
4659                 }
4660
4661                 if ((code - cfg->native_code - offset) > max_len) {
4662                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4663                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4664                         g_assert_not_reached ();
4665                 }
4666
4667                 cpos += max_len;
4668
4669                 last_ins = ins;
4670                 last_offset = offset;
4671         }
4672
4673         cfg->code_len = code - cfg->native_code;
4674 }
4675
4676 void
4677 mono_arch_register_lowlevel_calls (void)
4678 {
4679         /* The signature doesn't matter */
4680         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4681 }
4682
4683 void
4684 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4685 {
4686         MonoJumpInfo *patch_info;
4687         gboolean compile_aot = !run_cctors;
4688
4689         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4690                 unsigned char *ip = patch_info->ip.i + code;
4691                 unsigned char *target;
4692
4693                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4694
4695                 if (compile_aot) {
4696                         switch (patch_info->type) {
4697                         case MONO_PATCH_INFO_BB:
4698                         case MONO_PATCH_INFO_LABEL:
4699                                 break;
4700                         default:
4701                                 /* No need to patch these */
4702                                 continue;
4703                         }
4704                 }
4705
4706                 switch (patch_info->type) {
4707                 case MONO_PATCH_INFO_NONE:
4708                         continue;
4709                 case MONO_PATCH_INFO_METHOD_REL:
4710                 case MONO_PATCH_INFO_R8:
4711                 case MONO_PATCH_INFO_R4:
4712                         g_assert_not_reached ();
4713                         continue;
4714                 case MONO_PATCH_INFO_BB:
4715                         break;
4716                 default:
4717                         break;
4718                 }
4719
4720                 /*
4721                  * Debug code to help track down problems where the target of a near call is
4722                  * is not valid.
4723                  */
4724                 if (amd64_is_near_call (ip)) {
4725                         gint64 disp = (guint8*)target - (guint8*)ip;
4726
4727                         if (!amd64_is_imm32 (disp)) {
4728                                 printf ("TYPE: %d\n", patch_info->type);
4729                                 switch (patch_info->type) {
4730                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4731                                         printf ("V: %s\n", patch_info->data.name);
4732                                         break;
4733                                 case MONO_PATCH_INFO_METHOD_JUMP:
4734                                 case MONO_PATCH_INFO_METHOD:
4735                                         printf ("V: %s\n", patch_info->data.method->name);
4736                                         break;
4737                                 default:
4738                                         break;
4739                                 }
4740                         }
4741                 }
4742
4743                 amd64_patch (ip, (gpointer)target);
4744         }
4745 }
4746
4747 static int
4748 get_max_epilog_size (MonoCompile *cfg)
4749 {
4750         int max_epilog_size = 16;
4751
4752         if (cfg->method->save_lmf)
4753                 max_epilog_size += 256;
4754
4755         if (mono_jit_trace_calls != NULL)
4756                 max_epilog_size += 50;
4757
4758         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4759                 max_epilog_size += 50;
4760
4761         max_epilog_size += (AMD64_NREG * 2);
4762
4763         return max_epilog_size;
4764 }
4765
4766 /*
4767  * This macro is used for testing whenever the unwinder works correctly at every point
4768  * where an async exception can happen.
4769  */
4770 /* This will generate a SIGSEGV at the given point in the code */
4771 #define async_exc_point(code) do { \
4772     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4773          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4774              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4775          cfg->arch.async_point_count ++; \
4776     } \
4777 } while (0)
4778
4779 guint8 *
4780 mono_arch_emit_prolog (MonoCompile *cfg)
4781 {
4782         MonoMethod *method = cfg->method;
4783         MonoBasicBlock *bb;
4784         MonoMethodSignature *sig;
4785         MonoInst *ins;
4786         int alloc_size, pos, max_offset, i, quad, max_epilog_size;
4787         guint8 *code;
4788         CallInfo *cinfo;
4789         gint32 lmf_offset = cfg->arch.lmf_offset;
4790         gboolean args_clobbered = FALSE;
4791         gboolean trace = FALSE;
4792
4793         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4794
4795         code = cfg->native_code = g_malloc (cfg->code_size);
4796
4797         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4798                 trace = TRUE;
4799
4800         /* Amount of stack space allocated by register saving code */
4801         pos = 0;
4802
4803         /*
4804          * The prolog consists of the following parts:
4805          * FP present:
4806          * - push rbp, mov rbp, rsp
4807          * - save callee saved regs using pushes
4808          * - allocate frame
4809          * - save rgctx if needed
4810          * - save lmf if needed
4811          * FP not present:
4812          * - allocate frame
4813          * - save rgctx if needed
4814          * - save lmf if needed
4815          * - save callee saved regs using moves
4816          */
4817
4818         async_exc_point (code);
4819
4820         if (!cfg->arch.omit_fp) {
4821                 amd64_push_reg (code, AMD64_RBP);
4822                 async_exc_point (code);
4823 #ifdef PLATFORM_WIN32
4824                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4825 #endif
4826
4827                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4828                 async_exc_point (code);
4829 #ifdef PLATFORM_WIN32
4830                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4831 #endif
4832         }
4833
4834         /* Save callee saved registers */
4835         if (!cfg->arch.omit_fp && !method->save_lmf) {
4836                 for (i = 0; i < AMD64_NREG; ++i)
4837                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4838                                 amd64_push_reg (code, i);
4839                                 pos += sizeof (gpointer);
4840                                 async_exc_point (code);
4841                         }
4842         }
4843
4844         if (cfg->arch.omit_fp) {
4845                 /*
4846                  * On enter, the stack is misaligned by the the pushing of the return
4847                  * address. It is either made aligned by the pushing of %rbp, or by
4848                  * this.
4849                  */
4850                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4851                 if ((alloc_size % 16) == 0)
4852                         alloc_size += 8;
4853         } else {
4854                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4855
4856                 alloc_size -= pos;
4857         }
4858
4859         cfg->arch.stack_alloc_size = alloc_size;
4860
4861         /* Allocate stack frame */
4862         if (alloc_size) {
4863                 /* See mono_emit_stack_alloc */
4864 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4865                 guint32 remaining_size = alloc_size;
4866                 while (remaining_size >= 0x1000) {
4867                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4868                         async_exc_point (code);
4869 #ifdef PLATFORM_WIN32
4870                         if (cfg->arch.omit_fp)
4871                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4872 #endif
4873
4874                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4875                         remaining_size -= 0x1000;
4876                 }
4877                 if (remaining_size) {
4878                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4879                         async_exc_point (code);
4880 #ifdef PLATFORM_WIN32
4881                         if (cfg->arch.omit_fp)
4882                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4883 #endif
4884                 }
4885 #else
4886                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4887                 async_exc_point (code);
4888 #endif
4889         }
4890
4891         /* Stack alignment check */
4892 #if 0
4893         {
4894                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4895                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4896                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4897                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4898                 amd64_breakpoint (code);
4899         }
4900 #endif
4901
4902         /* Save LMF */
4903         if (method->save_lmf) {
4904                 /*
4905                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4906                  */
4907                 /* sp is saved right before calls */
4908                 /* Skip method (only needed for trampoline LMF frames) */
4909                 /* Save callee saved regs */
4910                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4911                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4912                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4913                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4914                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4915                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4916         }
4917
4918         /* Save callee saved registers */
4919         if (cfg->arch.omit_fp && !method->save_lmf) {
4920                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4921
4922                 /* Save caller saved registers after sp is adjusted */
4923                 /* The registers are saved at the bottom of the frame */
4924                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4925                 for (i = 0; i < AMD64_NREG; ++i)
4926                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4927                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4928                                 save_area_offset += 8;
4929                                 async_exc_point (code);
4930                         }
4931         }
4932
4933         /* store runtime generic context */
4934         if (cfg->rgctx_var) {
4935                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4936                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4937
4938                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4939         }
4940
4941         /* compute max_offset in order to use short forward jumps */
4942         max_offset = 0;
4943         max_epilog_size = get_max_epilog_size (cfg);
4944         if (cfg->opt & MONO_OPT_BRANCH) {
4945                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4946                         MonoInst *ins;
4947                         bb->max_offset = max_offset;
4948
4949                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4950                                 max_offset += 6;
4951                         /* max alignment for loops */
4952                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4953                                 max_offset += LOOP_ALIGNMENT;
4954
4955                         MONO_BB_FOR_EACH_INS (bb, ins) {
4956                                 if (ins->opcode == OP_LABEL)
4957                                         ins->inst_c1 = max_offset;
4958
4959                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4960                         }
4961
4962                         if (mono_jit_trace_calls && bb == cfg->bb_exit)
4963                                 /* The tracing code can be quite large */
4964                                 max_offset += max_epilog_size;
4965                 }
4966         }
4967
4968         sig = mono_method_signature (method);
4969         pos = 0;
4970
4971         cinfo = cfg->arch.cinfo;
4972
4973         if (sig->ret->type != MONO_TYPE_VOID) {
4974                 /* Save volatile arguments to the stack */
4975                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4976                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4977         }
4978
4979         /* Keep this in sync with emit_load_volatile_arguments */
4980         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4981                 ArgInfo *ainfo = cinfo->args + i;
4982                 gint32 stack_offset;
4983                 MonoType *arg_type;
4984
4985                 ins = cfg->args [i];
4986
4987                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4988                         /* Unused arguments */
4989                         continue;
4990
4991                 if (sig->hasthis && (i == 0))
4992                         arg_type = &mono_defaults.object_class->byval_arg;
4993                 else
4994                         arg_type = sig->params [i - sig->hasthis];
4995
4996                 stack_offset = ainfo->offset + ARGS_OFFSET;
4997
4998                 if (cfg->globalra) {
4999                         /* All the other moves are done by the register allocator */
5000                         switch (ainfo->storage) {
5001                         case ArgInFloatSSEReg:
5002                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5003                                 break;
5004                         case ArgValuetypeInReg:
5005                                 for (quad = 0; quad < 2; quad ++) {
5006                                         switch (ainfo->pair_storage [quad]) {
5007                                         case ArgInIReg:
5008                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5009                                                 break;
5010                                         case ArgInFloatSSEReg:
5011                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5012                                                 break;
5013                                         case ArgInDoubleSSEReg:
5014                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5015                                                 break;
5016                                         case ArgNone:
5017                                                 break;
5018                                         default:
5019                                                 g_assert_not_reached ();
5020                                         }
5021                                 }
5022                                 break;
5023                         default:
5024                                 break;
5025                         }
5026
5027                         continue;
5028                 }
5029
5030                 /* Save volatile arguments to the stack */
5031                 if (ins->opcode != OP_REGVAR) {
5032                         switch (ainfo->storage) {
5033                         case ArgInIReg: {
5034                                 guint32 size = 8;
5035
5036                                 /* FIXME: I1 etc */
5037                                 /*
5038                                 if (stack_offset & 0x1)
5039                                         size = 1;
5040                                 else if (stack_offset & 0x2)
5041                                         size = 2;
5042                                 else if (stack_offset & 0x4)
5043                                         size = 4;
5044                                 else
5045                                         size = 8;
5046                                 */
5047                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5048                                 break;
5049                         }
5050                         case ArgInFloatSSEReg:
5051                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5052                                 break;
5053                         case ArgInDoubleSSEReg:
5054                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5055                                 break;
5056                         case ArgValuetypeInReg:
5057                                 for (quad = 0; quad < 2; quad ++) {
5058                                         switch (ainfo->pair_storage [quad]) {
5059                                         case ArgInIReg:
5060                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5061                                                 break;
5062                                         case ArgInFloatSSEReg:
5063                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5064                                                 break;
5065                                         case ArgInDoubleSSEReg:
5066                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5067                                                 break;
5068                                         case ArgNone:
5069                                                 break;
5070                                         default:
5071                                                 g_assert_not_reached ();
5072                                         }
5073                                 }
5074                                 break;
5075                         case ArgValuetypeAddrInIReg:
5076                                 if (ainfo->pair_storage [0] == ArgInIReg)
5077                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5078                                 break;
5079                         default:
5080                                 break;
5081                         }
5082                 } else {
5083                         /* Argument allocated to (non-volatile) register */
5084                         switch (ainfo->storage) {
5085                         case ArgInIReg:
5086                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5087                                 break;
5088                         case ArgOnStack:
5089                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5090                                 break;
5091                         default:
5092                                 g_assert_not_reached ();
5093                         }
5094                 }
5095         }
5096
5097         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5098         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5099                 guint64 domain = (guint64)cfg->domain;
5100
5101                 args_clobbered = TRUE;
5102
5103                 /*
5104                  * The call might clobber argument registers, but they are already
5105                  * saved to the stack/global regs.
5106                  */
5107                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5108                         guint8 *buf, *no_domain_branch;
5109
5110                         code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5111                         if ((domain >> 32) == 0)
5112                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5113                         else
5114                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5115                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5116                         no_domain_branch = code;
5117                         x86_branch8 (code, X86_CC_NE, 0, 0);
5118                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5119                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5120                         buf = code;
5121                         x86_branch8 (code, X86_CC_NE, 0, 0);
5122                         amd64_patch (no_domain_branch, code);
5123                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5124                                           (gpointer)"mono_jit_thread_attach", TRUE);
5125                         amd64_patch (buf, code);
5126 #ifdef PLATFORM_WIN32
5127                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5128                         /* FIXME: Add a separate key for LMF to avoid this */
5129                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5130 #endif
5131                 } else {
5132                         g_assert (!cfg->compile_aot);
5133                         if ((domain >> 32) == 0)
5134                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5135                         else
5136                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5137                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5138                                           (gpointer)"mono_jit_thread_attach", TRUE);
5139                 }
5140         }
5141
5142         if (method->save_lmf) {
5143                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5144                         /*
5145                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5146                          * through the mono_lmf_addr TLS variable.
5147                          */
5148                         /* %rax = previous_lmf */
5149                         x86_prefix (code, X86_FS_PREFIX);
5150                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5151
5152                         /* Save previous_lmf */
5153                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5154                         /* Set new lmf */
5155                         if (lmf_offset == 0) {
5156                                 x86_prefix (code, X86_FS_PREFIX);
5157                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5158                         } else {
5159                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5160                                 x86_prefix (code, X86_FS_PREFIX);
5161                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5162                         }
5163                 } else {
5164                         if (lmf_addr_tls_offset != -1) {
5165                                 /* Load lmf quicky using the FS register */
5166                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5167 #ifdef PLATFORM_WIN32
5168                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5169                                 /* FIXME: Add a separate key for LMF to avoid this */
5170                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5171 #endif
5172                         }
5173                         else {
5174                                 /*
5175                                  * The call might clobber argument registers, but they are already
5176                                  * saved to the stack/global regs.
5177                                  */
5178                                 args_clobbered = TRUE;
5179                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5180                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
5181                         }
5182
5183                         /* Save lmf_addr */
5184                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5185                         /* Save previous_lmf */
5186                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5187                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5188                         /* Set new lmf */
5189                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5190                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5191                 }
5192         }
5193
5194         if (trace) {
5195                 args_clobbered = TRUE;
5196                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5197         }
5198
5199         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5200                 args_clobbered = TRUE;
5201
5202         /*
5203          * Optimize the common case of the first bblock making a call with the same
5204          * arguments as the method. This works because the arguments are still in their
5205          * original argument registers.
5206          * FIXME: Generalize this
5207          */
5208         if (!args_clobbered) {
5209                 MonoBasicBlock *first_bb = cfg->bb_entry;
5210                 MonoInst *next;
5211
5212                 next = mono_bb_first_ins (first_bb);
5213                 if (!next && first_bb->next_bb) {
5214                         first_bb = first_bb->next_bb;
5215                         next = mono_bb_first_ins (first_bb);
5216                 }
5217
5218                 if (first_bb->in_count > 1)
5219                         next = NULL;
5220
5221                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5222                         ArgInfo *ainfo = cinfo->args + i;
5223                         gboolean match = FALSE;
5224
5225                         ins = cfg->args [i];
5226                         if (ins->opcode != OP_REGVAR) {
5227                                 switch (ainfo->storage) {
5228                                 case ArgInIReg: {
5229                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5230                                                 if (next->dreg == ainfo->reg) {
5231                                                         NULLIFY_INS (next);
5232                                                         match = TRUE;
5233                                                 } else {
5234                                                         next->opcode = OP_MOVE;
5235                                                         next->sreg1 = ainfo->reg;
5236                                                         /* Only continue if the instruction doesn't change argument regs */
5237                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5238                                                                 match = TRUE;
5239                                                 }
5240                                         }
5241                                         break;
5242                                 }
5243                                 default:
5244                                         break;
5245                                 }
5246                         } else {
5247                                 /* Argument allocated to (non-volatile) register */
5248                                 switch (ainfo->storage) {
5249                                 case ArgInIReg:
5250                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5251                                                 NULLIFY_INS (next);
5252                                                 match = TRUE;
5253                                         }
5254                                         break;
5255                                 default:
5256                                         break;
5257                                 }
5258                         }
5259
5260                         if (match) {
5261                                 next = next->next;
5262                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5263                                 if (!next)
5264                                         break;
5265                         }
5266                 }
5267         }
5268
5269         cfg->code_len = code - cfg->native_code;
5270
5271         g_assert (cfg->code_len < cfg->code_size);
5272
5273         return code;
5274 }
5275
5276 void
5277 mono_arch_emit_epilog (MonoCompile *cfg)
5278 {
5279         MonoMethod *method = cfg->method;
5280         int quad, pos, i;
5281         guint8 *code;
5282         int max_epilog_size;
5283         CallInfo *cinfo;
5284         gint32 lmf_offset = cfg->arch.lmf_offset;
5285
5286         max_epilog_size = get_max_epilog_size (cfg);
5287
5288         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5289                 cfg->code_size *= 2;
5290                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5291                 mono_jit_stats.code_reallocs++;
5292         }
5293
5294         code = cfg->native_code + cfg->code_len;
5295
5296         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5297                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5298
5299         /* the code restoring the registers must be kept in sync with OP_JMP */
5300         pos = 0;
5301
5302         if (method->save_lmf) {
5303                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5304                         /*
5305                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
5306                          * through the mono_lmf_addr TLS variable.
5307                          */
5308                         /* reg = previous_lmf */
5309                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5310                         x86_prefix (code, X86_FS_PREFIX);
5311                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5312                 } else {
5313                         /* Restore previous lmf */
5314                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5315                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5316                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5317                 }
5318
5319                 /* Restore caller saved regs */
5320                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5321                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5322                 }
5323                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5324                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5325                 }
5326                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5327                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5328                 }
5329                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5330                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5331                 }
5332                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5333                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5334                 }
5335                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5336                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5337                 }
5338         } else {
5339
5340                 if (cfg->arch.omit_fp) {
5341                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5342
5343                         for (i = 0; i < AMD64_NREG; ++i)
5344                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5345                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5346                                         save_area_offset += 8;
5347                                 }
5348                 }
5349                 else {
5350                         for (i = 0; i < AMD64_NREG; ++i)
5351                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5352                                         pos -= sizeof (gpointer);
5353
5354                         if (pos) {
5355                                 if (pos == - sizeof (gpointer)) {
5356                                         /* Only one register, so avoid lea */
5357                                         for (i = AMD64_NREG - 1; i > 0; --i)
5358                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5359                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5360                                                 }
5361                                 }
5362                                 else {
5363                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5364
5365                                         /* Pop registers in reverse order */
5366                                         for (i = AMD64_NREG - 1; i > 0; --i)
5367                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5368                                                         amd64_pop_reg (code, i);
5369                                                 }
5370                                 }
5371                         }
5372                 }
5373         }
5374
5375         /* Load returned vtypes into registers if needed */
5376         cinfo = cfg->arch.cinfo;
5377         if (cinfo->ret.storage == ArgValuetypeInReg) {
5378                 ArgInfo *ainfo = &cinfo->ret;
5379                 MonoInst *inst = cfg->ret;
5380
5381                 for (quad = 0; quad < 2; quad ++) {
5382                         switch (ainfo->pair_storage [quad]) {
5383                         case ArgInIReg:
5384                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5385                                 break;
5386                         case ArgInFloatSSEReg:
5387                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5388                                 break;
5389                         case ArgInDoubleSSEReg:
5390                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5391                                 break;
5392                         case ArgNone:
5393                                 break;
5394                         default:
5395                                 g_assert_not_reached ();
5396                         }
5397                 }
5398         }
5399
5400         if (cfg->arch.omit_fp) {
5401                 if (cfg->arch.stack_alloc_size)
5402                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5403         } else {
5404                 amd64_leave (code);
5405         }
5406         async_exc_point (code);
5407         amd64_ret (code);
5408
5409         cfg->code_len = code - cfg->native_code;
5410
5411         g_assert (cfg->code_len < cfg->code_size);
5412
5413         if (cfg->arch.omit_fp) {
5414                 /*
5415                  * Encode the stack size into used_int_regs so the exception handler
5416                  * can access it.
5417                  */
5418                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5419                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5420         }
5421 }
5422
5423 void
5424 mono_arch_emit_exceptions (MonoCompile *cfg)
5425 {
5426         MonoJumpInfo *patch_info;
5427         int nthrows, i;
5428         guint8 *code;
5429         MonoClass *exc_classes [16];
5430         guint8 *exc_throw_start [16], *exc_throw_end [16];
5431         guint32 code_size = 0;
5432
5433         /* Compute needed space */
5434         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5435                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5436                         code_size += 40;
5437                 if (patch_info->type == MONO_PATCH_INFO_R8)
5438                         code_size += 8 + 15; /* sizeof (double) + alignment */
5439                 if (patch_info->type == MONO_PATCH_INFO_R4)
5440                         code_size += 4 + 15; /* sizeof (float) + alignment */
5441         }
5442
5443         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5444                 cfg->code_size *= 2;
5445                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5446                 mono_jit_stats.code_reallocs++;
5447         }
5448
5449         code = cfg->native_code + cfg->code_len;
5450
5451         /* add code to raise exceptions */
5452         nthrows = 0;
5453         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5454                 switch (patch_info->type) {
5455                 case MONO_PATCH_INFO_EXC: {
5456                         MonoClass *exc_class;
5457                         guint8 *buf, *buf2;
5458                         guint32 throw_ip;
5459
5460                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5461
5462                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5463                         g_assert (exc_class);
5464                         throw_ip = patch_info->ip.i;
5465
5466                         //x86_breakpoint (code);
5467                         /* Find a throw sequence for the same exception class */
5468                         for (i = 0; i < nthrows; ++i)
5469                                 if (exc_classes [i] == exc_class)
5470                                         break;
5471                         if (i < nthrows) {
5472                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5473                                 x86_jump_code (code, exc_throw_start [i]);
5474                                 patch_info->type = MONO_PATCH_INFO_NONE;
5475                         }
5476                         else {
5477                                 buf = code;
5478                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5479                                 buf2 = code;
5480
5481                                 if (nthrows < 16) {
5482                                         exc_classes [nthrows] = exc_class;
5483                                         exc_throw_start [nthrows] = code;
5484                                 }
5485                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5486
5487                                 patch_info->type = MONO_PATCH_INFO_NONE;
5488
5489                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5490
5491                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5492                                 while (buf < buf2)
5493                                         x86_nop (buf);
5494
5495                                 if (nthrows < 16) {
5496                                         exc_throw_end [nthrows] = code;
5497                                         nthrows ++;
5498                                 }
5499                         }
5500                         break;
5501                 }
5502                 default:
5503                         /* do nothing */
5504                         break;
5505                 }
5506         }
5507
5508         /* Handle relocations with RIP relative addressing */
5509         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5510                 gboolean remove = FALSE;
5511
5512                 switch (patch_info->type) {
5513                 case MONO_PATCH_INFO_R8:
5514                 case MONO_PATCH_INFO_R4: {
5515                         guint8 *pos;
5516
5517                         /* The SSE opcodes require a 16 byte alignment */
5518                         code = (guint8*)ALIGN_TO (code, 16);
5519
5520                         pos = cfg->native_code + patch_info->ip.i;
5521
5522                         if (IS_REX (pos [1]))
5523                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5524                         else
5525                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5526
5527                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5528                                 *(double*)code = *(double*)patch_info->data.target;
5529                                 code += sizeof (double);
5530                         } else {
5531                                 *(float*)code = *(float*)patch_info->data.target;
5532                                 code += sizeof (float);
5533                         }
5534
5535                         remove = TRUE;
5536                         break;
5537                 }
5538                 default:
5539                         break;
5540                 }
5541
5542                 if (remove) {
5543                         if (patch_info == cfg->patch_info)
5544                                 cfg->patch_info = patch_info->next;
5545                         else {
5546                                 MonoJumpInfo *tmp;
5547
5548                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5549                                         ;
5550                                 tmp->next = patch_info->next;
5551                         }
5552                 }
5553         }
5554
5555         cfg->code_len = code - cfg->native_code;
5556
5557         g_assert (cfg->code_len < cfg->code_size);
5558
5559 }
5560
5561 void*
5562 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5563 {
5564         guchar *code = p;
5565         CallInfo *cinfo = NULL;
5566         MonoMethodSignature *sig;
5567         MonoInst *inst;
5568         int i, n, stack_area = 0;
5569
5570         /* Keep this in sync with mono_arch_get_argument_info */
5571
5572         if (enable_arguments) {
5573                 /* Allocate a new area on the stack and save arguments there */
5574                 sig = mono_method_signature (cfg->method);
5575
5576                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5577
5578                 n = sig->param_count + sig->hasthis;
5579
5580                 stack_area = ALIGN_TO (n * 8, 16);
5581
5582                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5583
5584                 for (i = 0; i < n; ++i) {
5585                         inst = cfg->args [i];
5586
5587                         if (inst->opcode == OP_REGVAR)
5588                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5589                         else {
5590                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5591                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5592                         }
5593                 }
5594         }
5595
5596         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5597         amd64_set_reg_template (code, AMD64_ARG_REG1);
5598         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5599         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5600
5601         if (enable_arguments)
5602                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5603
5604         return code;
5605 }
5606
5607 enum {
5608         SAVE_NONE,
5609         SAVE_STRUCT,
5610         SAVE_EAX,
5611         SAVE_EAX_EDX,
5612         SAVE_XMM
5613 };
5614
5615 void*
5616 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5617 {
5618         guchar *code = p;
5619         int save_mode = SAVE_NONE;
5620         MonoMethod *method = cfg->method;
5621         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
5622
5623         switch (rtype) {
5624         case MONO_TYPE_VOID:
5625                 /* special case string .ctor icall */
5626                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5627                         save_mode = SAVE_EAX;
5628                 else
5629                         save_mode = SAVE_NONE;
5630                 break;
5631         case MONO_TYPE_I8:
5632         case MONO_TYPE_U8:
5633                 save_mode = SAVE_EAX;
5634                 break;
5635         case MONO_TYPE_R4:
5636         case MONO_TYPE_R8:
5637                 save_mode = SAVE_XMM;
5638                 break;
5639         case MONO_TYPE_GENERICINST:
5640                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5641                         save_mode = SAVE_EAX;
5642                         break;
5643                 }
5644                 /* Fall through */
5645         case MONO_TYPE_VALUETYPE:
5646                 save_mode = SAVE_STRUCT;
5647                 break;
5648         default:
5649                 save_mode = SAVE_EAX;
5650                 break;
5651         }
5652
5653         /* Save the result and copy it into the proper argument register */
5654         switch (save_mode) {
5655         case SAVE_EAX:
5656                 amd64_push_reg (code, AMD64_RAX);
5657                 /* Align stack */
5658                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5659                 if (enable_arguments)
5660                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5661                 break;
5662         case SAVE_STRUCT:
5663                 /* FIXME: */
5664                 if (enable_arguments)
5665                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5666                 break;
5667         case SAVE_XMM:
5668                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5669                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5670                 /* Align stack */
5671                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5672                 /*
5673                  * The result is already in the proper argument register so no copying
5674                  * needed.
5675                  */
5676                 break;
5677         case SAVE_NONE:
5678                 break;
5679         default:
5680                 g_assert_not_reached ();
5681         }
5682
5683         /* Set %al since this is a varargs call */
5684         if (save_mode == SAVE_XMM)
5685                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5686         else
5687                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5688
5689         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5690         amd64_set_reg_template (code, AMD64_ARG_REG1);
5691         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5692
5693         /* Restore result */
5694         switch (save_mode) {
5695         case SAVE_EAX:
5696                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5697                 amd64_pop_reg (code, AMD64_RAX);
5698                 break;
5699         case SAVE_STRUCT:
5700                 /* FIXME: */
5701                 break;
5702         case SAVE_XMM:
5703                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5704                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5705                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5706                 break;
5707         case SAVE_NONE:
5708                 break;
5709         default:
5710                 g_assert_not_reached ();
5711         }
5712
5713         return code;
5714 }
5715
5716 void
5717 mono_arch_flush_icache (guint8 *code, gint size)
5718 {
5719         /* Not needed */
5720 }
5721
5722 void
5723 mono_arch_flush_register_windows (void)
5724 {
5725 }
5726
5727 gboolean
5728 mono_arch_is_inst_imm (gint64 imm)
5729 {
5730         return amd64_is_imm32 (imm);
5731 }
5732
5733 /*
5734  * Determine whenever the trap whose info is in SIGINFO is caused by
5735  * integer overflow.
5736  */
5737 gboolean
5738 mono_arch_is_int_overflow (void *sigctx, void *info)
5739 {
5740         MonoContext ctx;
5741         guint8* rip;
5742         int reg;
5743         gint64 value;
5744
5745         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5746
5747         rip = (guint8*)ctx.rip;
5748
5749         if (IS_REX (rip [0])) {
5750                 reg = amd64_rex_b (rip [0]);
5751                 rip ++;
5752         }
5753         else
5754                 reg = 0;
5755
5756         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5757                 /* idiv REG */
5758                 reg += x86_modrm_rm (rip [1]);
5759
5760                 switch (reg) {
5761                 case AMD64_RAX:
5762                         value = ctx.rax;
5763                         break;
5764                 case AMD64_RBX:
5765                         value = ctx.rbx;
5766                         break;
5767                 case AMD64_RCX:
5768                         value = ctx.rcx;
5769                         break;
5770                 case AMD64_RDX:
5771                         value = ctx.rdx;
5772                         break;
5773                 case AMD64_RBP:
5774                         value = ctx.rbp;
5775                         break;
5776                 case AMD64_RSP:
5777                         value = ctx.rsp;
5778                         break;
5779                 case AMD64_RSI:
5780                         value = ctx.rsi;
5781                         break;
5782                 case AMD64_RDI:
5783                         value = ctx.rdi;
5784                         break;
5785                 case AMD64_R12:
5786                         value = ctx.r12;
5787                         break;
5788                 case AMD64_R13:
5789                         value = ctx.r13;
5790                         break;
5791                 case AMD64_R14:
5792                         value = ctx.r14;
5793                         break;
5794                 case AMD64_R15:
5795                         value = ctx.r15;
5796                         break;
5797                 default:
5798                         g_assert_not_reached ();
5799                         reg = -1;
5800                 }
5801
5802                 if (value == -1)
5803                         return TRUE;
5804         }
5805
5806         return FALSE;
5807 }
5808
5809 guint32
5810 mono_arch_get_patch_offset (guint8 *code)
5811 {
5812         return 3;
5813 }
5814
5815 /**
5816  * mono_breakpoint_clean_code:
5817  *
5818  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5819  * breakpoints in the original code, they are removed in the copy.
5820  *
5821  * Returns TRUE if no sw breakpoint was present.
5822  */
5823 gboolean
5824 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5825 {
5826         int i;
5827         gboolean can_write = TRUE;
5828         /*
5829          * If method_start is non-NULL we need to perform bound checks, since we access memory
5830          * at code - offset we could go before the start of the method and end up in a different
5831          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5832          * instead.
5833          */
5834         if (!method_start || code - offset >= method_start) {
5835                 memcpy (buf, code - offset, size);
5836         } else {
5837                 int diff = code - method_start;
5838                 memset (buf, 0, size);
5839                 memcpy (buf + offset - diff, method_start, diff + size - offset);
5840         }
5841         code -= offset;
5842         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5843                 int idx = mono_breakpoint_info_index [i];
5844                 guint8 *ptr;
5845                 if (idx < 1)
5846                         continue;
5847                 ptr = mono_breakpoint_info [idx].address;
5848                 if (ptr >= code && ptr < code + size) {
5849                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5850                         can_write = FALSE;
5851                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5852                         buf [ptr - code] = saved_byte;
5853                 }
5854         }
5855         return can_write;
5856 }
5857
5858 gpointer
5859 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5860 {
5861         guint8 buf [10];
5862         guint32 reg;
5863         gint32 disp;
5864         guint8 rex = 0;
5865
5866         mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5867         code = buf + 9;
5868
5869         *displacement = 0;
5870
5871         /* go to the start of the call instruction
5872          *
5873          * address_byte = (m << 6) | (o << 3) | reg
5874          * call opcode: 0xff address_byte displacement
5875          * 0xff m=1,o=2 imm8
5876          * 0xff m=2,o=2 imm32
5877          */
5878         code -= 7;
5879
5880         /*
5881          * A given byte sequence can match more than case here, so we have to be
5882          * really careful about the ordering of the cases. Longer sequences
5883          * come first.
5884          */
5885 #ifdef MONO_ARCH_HAVE_IMT
5886         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5887                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5888                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5889                  * ff 50 fc                call   *0xfffffffc(%rax)
5890                  */
5891                 reg = amd64_modrm_rm (code [5]);
5892                 disp = (signed char)code [6];
5893                 /* R10 is clobbered by the IMT thunk code */
5894                 g_assert (reg != AMD64_R10);
5895         }
5896 #else
5897         if (0) {
5898         }
5899 #endif
5900         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5901                         /*
5902                          * This is a interface call
5903                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5904                          * ff 10                  callq  *(%rax)
5905                          */
5906                 if (IS_REX (code [4]))
5907                         rex = code [4];
5908                 reg = amd64_modrm_rm (code [6]);
5909                 disp = 0;
5910                 /* R10 is clobbered by the IMT thunk code */
5911                 g_assert (reg != AMD64_R10);
5912         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5913                 /* call OFFSET(%rip) */
5914                 disp = *(guint32*)(code + 3);
5915                 return (gpointer*)(code + disp + 7);
5916         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5917                 /* call *[r12+disp32] */
5918                 if (IS_REX (code [-1]))
5919                         rex = code [-1];
5920                 reg = AMD64_RSP;
5921                 disp = *(gint32*)(code + 3);
5922         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5923                 /* call *[reg+disp32] */
5924                 if (IS_REX (code [0]))
5925                         rex = code [0];
5926                 reg = amd64_modrm_rm (code [2]);
5927                 disp = *(gint32*)(code + 3);
5928                 /* R10 is clobbered by the IMT thunk code */
5929                 g_assert (reg != AMD64_R10);
5930         } else if (code [2] == 0xe8) {
5931                 /* call <ADDR> */
5932                 return NULL;
5933         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5934                 /* call *[r12+disp32] */
5935                 if (IS_REX (code [2]))
5936                         rex = code [2];
5937                 reg = AMD64_RSP;
5938                 disp = *(gint8*)(code + 6);
5939         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5940                 /* call *%reg */
5941                 return NULL;
5942         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5943                 /* call *[reg+disp8] */
5944                 if (IS_REX (code [3]))
5945                         rex = code [3];
5946                 reg = amd64_modrm_rm (code [5]);
5947                 disp = *(gint8*)(code + 6);
5948                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5949         }
5950         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5951                         /*
5952                          * This is a interface call: should check the above code can't catch it earlier
5953                          * 8b 40 30   mov    0x30(%eax),%eax
5954                          * ff 10      call   *(%eax)
5955                          */
5956                 if (IS_REX (code [4]))
5957                         rex = code [4];
5958                 reg = amd64_modrm_rm (code [6]);
5959                 disp = 0;
5960         }
5961         else
5962                 g_assert_not_reached ();
5963
5964         reg += amd64_rex_b (rex);
5965
5966         /* R11 is clobbered by the trampoline code */
5967         g_assert (reg != AMD64_R11);
5968
5969         *displacement = disp;
5970         return regs [reg];
5971 }
5972
5973 gpointer*
5974 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5975 {
5976         gpointer vt;
5977         int displacement;
5978         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5979         if (!vt)
5980                 return NULL;
5981         return (gpointer*)((char*)vt + displacement);
5982 }
5983
5984 int
5985 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
5986 {
5987         int this_reg = AMD64_ARG_REG1;
5988
5989         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5990                 CallInfo *cinfo;
5991
5992                 if (!gsctx && code)
5993                         gsctx = mono_get_generic_context_from_code (code);
5994
5995                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5996
5997                 if (cinfo->ret.storage != ArgValuetypeInReg)
5998                         this_reg = AMD64_ARG_REG2;
5999                 g_free (cinfo);
6000         }
6001
6002         return this_reg;
6003 }
6004
6005 gpointer
6006 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
6007 {
6008         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6009 }
6010
6011 #define MAX_ARCH_DELEGATE_PARAMS 10
6012
6013 gpointer
6014 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6015 {
6016         guint8 *code, *start;
6017         int i;
6018
6019         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6020                 return NULL;
6021
6022         /* FIXME: Support more cases */
6023         if (MONO_TYPE_ISSTRUCT (sig->ret))
6024                 return NULL;
6025
6026         if (has_target) {
6027                 static guint8* cached = NULL;
6028
6029                 if (cached)
6030                         return cached;
6031
6032                 start = code = mono_global_codeman_reserve (64);
6033
6034                 /* Replace the this argument with the target */
6035                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6036                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6037                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6038
6039                 g_assert ((code - start) < 64);
6040
6041                 mono_debug_add_delegate_trampoline (start, code - start);
6042
6043                 mono_memory_barrier ();
6044
6045                 cached = start;
6046         } else {
6047                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6048                 for (i = 0; i < sig->param_count; ++i)
6049                         if (!mono_is_regsize_var (sig->params [i]))
6050                                 return NULL;
6051                 if (sig->param_count > 4)
6052                         return NULL;
6053
6054                 code = cache [sig->param_count];
6055                 if (code)
6056                         return code;
6057
6058                 start = code = mono_global_codeman_reserve (64);
6059
6060                 if (sig->param_count == 0) {
6061                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6062                 } else {
6063                         /* We have to shift the arguments left */
6064                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6065                         for (i = 0; i < sig->param_count; ++i)
6066                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6067
6068                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6069                 }
6070                 g_assert ((code - start) < 64);
6071
6072                 mono_debug_add_delegate_trampoline (start, code - start);
6073
6074                 mono_memory_barrier ();
6075
6076                 cache [sig->param_count] = start;
6077         }
6078
6079         return start;
6080 }
6081
6082 /*
6083  * Support for fast access to the thread-local lmf structure using the GS
6084  * segment register on NPTL + kernel 2.6.x.
6085  */
6086
6087 static gboolean tls_offset_inited = FALSE;
6088
6089 void
6090 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6091 {
6092         if (!tls_offset_inited) {
6093 #ifdef PLATFORM_WIN32
6094                 /*
6095                  * We need to init this multiple times, since when we are first called, the key might not
6096                  * be initialized yet.
6097                  */
6098                 appdomain_tls_offset = mono_domain_get_tls_key ();
6099                 lmf_tls_offset = mono_get_jit_tls_key ();
6100                 thread_tls_offset = mono_thread_get_tls_key ();
6101                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6102
6103                 /* Only 64 tls entries can be accessed using inline code */
6104                 if (appdomain_tls_offset >= 64)
6105                         appdomain_tls_offset = -1;
6106                 if (lmf_tls_offset >= 64)
6107                         lmf_tls_offset = -1;
6108                 if (thread_tls_offset >= 64)
6109                         thread_tls_offset = -1;
6110 #else
6111                 tls_offset_inited = TRUE;
6112 #ifdef MONO_XEN_OPT
6113                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6114 #endif
6115                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6116                 lmf_tls_offset = mono_get_lmf_tls_offset ();
6117                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6118                 thread_tls_offset = mono_thread_get_tls_offset ();
6119 #endif
6120         }
6121 }
6122
6123 void
6124 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6125 {
6126 }
6127
6128 void
6129 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
6130 {
6131         MonoCallInst *call = (MonoCallInst*)inst;
6132         CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
6133
6134         if (vt_reg != -1) {
6135                 MonoInst *vtarg;
6136
6137                 if (cinfo->ret.storage == ArgValuetypeInReg) {
6138                         /*
6139                          * The valuetype is in RAX:RDX after the call, need to be copied to
6140                          * the stack. Save the address here, so the call instruction can
6141                          * access it.
6142                          */
6143                         MonoInst *loc = cfg->arch.vret_addr_loc;
6144
6145                         g_assert (loc);
6146                         g_assert (loc->opcode == OP_REGOFFSET);
6147
6148                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, loc->inst_basereg, loc->inst_offset, vt_reg);
6149                 } else {
6150                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
6151                         vtarg->sreg1 = vt_reg;
6152                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
6153                         mono_bblock_add_inst (cfg->cbb, vtarg);
6154
6155                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
6156                 }
6157         }
6158
6159         /* add the this argument */
6160         if (this_reg != -1) {
6161                 MonoInst *this;
6162                 MONO_INST_NEW (cfg, this, OP_MOVE);
6163                 this->type = this_type;
6164                 this->sreg1 = this_reg;
6165                 this->dreg = mono_regstate_next_int (cfg->rs);
6166                 mono_bblock_add_inst (cfg->cbb, this);
6167
6168                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
6169         }
6170 }
6171
6172 #ifdef MONO_ARCH_HAVE_IMT
6173
6174 #define CMP_SIZE (6 + 1)
6175 #define CMP_REG_REG_SIZE (4 + 1)
6176 #define BR_SMALL_SIZE 2
6177 #define BR_LARGE_SIZE 6
6178 #define MOV_REG_IMM_SIZE 10
6179 #define MOV_REG_IMM_32BIT_SIZE 6
6180 #define JUMP_REG_SIZE (2 + 1)
6181
6182 static int
6183 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6184 {
6185         int i, distance = 0;
6186         for (i = start; i < target; ++i)
6187                 distance += imt_entries [i]->chunk_size;
6188         return distance;
6189 }
6190
6191 /*
6192  * LOCKING: called with the domain lock held
6193  */
6194 gpointer
6195 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count)
6196 {
6197         int i;
6198         int size = 0;
6199         guint8 *code, *start;
6200         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6201
6202         for (i = 0; i < count; ++i) {
6203                 MonoIMTCheckItem *item = imt_entries [i];
6204                 if (item->is_equals) {
6205                         if (item->check_target_idx) {
6206                                 if (!item->compare_done) {
6207                                         if (amd64_is_imm32 (item->method))
6208                                                 item->chunk_size += CMP_SIZE;
6209                                         else
6210                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6211                                 }
6212                                 if (vtable_is_32bit)
6213                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6214                                 else
6215                                         item->chunk_size += MOV_REG_IMM_SIZE;
6216                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6217                         } else {
6218                                 if (vtable_is_32bit)
6219                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6220                                 else
6221                                         item->chunk_size += MOV_REG_IMM_SIZE;
6222                                 item->chunk_size += JUMP_REG_SIZE;
6223                                 /* with assert below:
6224                                  * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6225                                  */
6226                         }
6227                 } else {
6228                         if (amd64_is_imm32 (item->method))
6229                                 item->chunk_size += CMP_SIZE;
6230                         else
6231                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6232                         item->chunk_size += BR_LARGE_SIZE;
6233                         imt_entries [item->check_target_idx]->compare_done = TRUE;
6234                 }
6235                 size += item->chunk_size;
6236         }
6237         code = mono_code_manager_reserve (domain->code_mp, size);
6238         start = code;
6239         for (i = 0; i < count; ++i) {
6240                 MonoIMTCheckItem *item = imt_entries [i];
6241                 item->code_target = code;
6242                 if (item->is_equals) {
6243                         if (item->check_target_idx) {
6244                                 if (!item->compare_done) {
6245                                         if (amd64_is_imm32 (item->method))
6246                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6247                                         else {
6248                                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6249                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6250                                         }
6251                                 }
6252                                 item->jmp_code = code;
6253                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6254                                 /* See the comment below about R10 */
6255                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6256                                 amd64_jump_membase (code, AMD64_R10, 0);
6257                         } else {
6258                                 /* enable the commented code to assert on wrong method */
6259 #if 0
6260                                 if (amd64_is_imm32 (item->method))
6261                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6262                                 else {
6263                                         amd64_mov_reg_imm (code, AMD64_R10, item->method);
6264                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6265                                 }
6266                                 item->jmp_code = code;
6267                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6268                                 /* See the comment below about R10 */
6269                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6270                                 amd64_jump_membase (code, AMD64_R10, 0);
6271                                 amd64_patch (item->jmp_code, code);
6272                                 amd64_breakpoint (code);
6273                                 item->jmp_code = NULL;
6274 #else
6275                                 /* We're using R10 here because R11
6276                                    needs to be preserved.  R10 needs
6277                                    to be preserved for calls which
6278                                    require a runtime generic context,
6279                                    but interface calls don't. */
6280                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6281                                 amd64_jump_membase (code, AMD64_R10, 0);
6282 #endif
6283                         }
6284                 } else {
6285                         if (amd64_is_imm32 (item->method))
6286                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6287                         else {
6288                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6289                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6290                         }
6291                         item->jmp_code = code;
6292                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6293                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6294                         else
6295                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6296                 }
6297                 g_assert (code - item->code_target <= item->chunk_size);
6298         }
6299         /* patch the branches to get to the target items */
6300         for (i = 0; i < count; ++i) {
6301                 MonoIMTCheckItem *item = imt_entries [i];
6302                 if (item->jmp_code) {
6303                         if (item->check_target_idx) {
6304                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6305                         }
6306                 }
6307         }
6308
6309         mono_stats.imt_thunks_size += code - start;
6310         g_assert (code - start <= size);
6311
6312         return start;
6313 }
6314
6315 MonoMethod*
6316 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6317 {
6318         return regs [MONO_ARCH_IMT_REG];
6319 }
6320
6321 MonoObject*
6322 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6323 {
6324         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6325 }
6326
6327 void
6328 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call)
6329 {
6330         /* Done by the implementation of the CALL_MEMBASE opcodes */
6331 }
6332 #endif
6333
6334 MonoVTable*
6335 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6336 {
6337         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6338 }
6339
6340 MonoInst*
6341 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6342 {
6343         MonoInst *ins = NULL;
6344
6345         if (cmethod->klass == mono_defaults.math_class) {
6346                 if (strcmp (cmethod->name, "Sin") == 0) {
6347                         MONO_INST_NEW (cfg, ins, OP_SIN);
6348                         ins->inst_i0 = args [0];
6349                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6350                         MONO_INST_NEW (cfg, ins, OP_COS);
6351                         ins->inst_i0 = args [0];
6352                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6353                         MONO_INST_NEW (cfg, ins, OP_SQRT);
6354                         ins->inst_i0 = args [0];
6355                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6356                         MONO_INST_NEW (cfg, ins, OP_ABS);
6357                         ins->inst_i0 = args [0];
6358                 }
6359
6360                 if (cfg->opt & MONO_OPT_CMOV) {
6361                         int opcode = 0;
6362
6363                         if (strcmp (cmethod->name, "Min") == 0) {
6364                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6365                                         opcode = OP_IMIN;
6366                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6367                                         opcode = OP_IMIN_UN;
6368                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6369                                         opcode = OP_LMIN;
6370                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6371                                         opcode = OP_LMIN_UN;
6372                         } else if (strcmp (cmethod->name, "Max") == 0) {
6373                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6374                                         opcode = OP_IMAX;
6375                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6376                                         opcode = OP_IMAX_UN;
6377                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6378                                         opcode = OP_LMAX;
6379                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6380                                         opcode = OP_LMAX_UN;
6381                         }
6382
6383                         if (opcode) {
6384                                 MONO_INST_NEW (cfg, ins, opcode);
6385                                 ins->inst_i0 = args [0];
6386                                 ins->inst_i1 = args [1];
6387                         }
6388                 }
6389
6390 #if 0
6391                 /* OP_FREM is not IEEE compatible */
6392                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6393                         MONO_INST_NEW (cfg, ins, OP_FREM);
6394                         ins->inst_i0 = args [0];
6395                         ins->inst_i1 = args [1];
6396                 }
6397 #endif
6398         }
6399
6400         return ins;
6401 }
6402
6403 MonoInst*
6404 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6405 {
6406         MonoInst *ins = NULL;
6407         int opcode = 0;
6408
6409         if (cmethod->klass == mono_defaults.math_class) {
6410                 if (strcmp (cmethod->name, "Sin") == 0) {
6411                         opcode = OP_SIN;
6412                 } else if (strcmp (cmethod->name, "Cos") == 0) {
6413                         opcode = OP_COS;
6414                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6415                         opcode = OP_SQRT;
6416                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6417                         opcode = OP_ABS;
6418                 }
6419
6420                 if (opcode) {
6421                         MONO_INST_NEW (cfg, ins, opcode);
6422                         ins->type = STACK_R8;
6423                         ins->dreg = mono_alloc_freg (cfg);
6424                         ins->sreg1 = args [0]->dreg;
6425                         MONO_ADD_INS (cfg->cbb, ins);
6426                 }
6427
6428                 opcode = 0;
6429                 if (cfg->opt & MONO_OPT_CMOV) {
6430                         if (strcmp (cmethod->name, "Min") == 0) {
6431                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6432                                         opcode = OP_IMIN;
6433                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6434                                         opcode = OP_IMIN_UN;
6435                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6436                                         opcode = OP_LMIN;
6437                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6438                                         opcode = OP_LMIN_UN;
6439                         } else if (strcmp (cmethod->name, "Max") == 0) {
6440                                 if (fsig->params [0]->type == MONO_TYPE_I4)
6441                                         opcode = OP_IMAX;
6442                                 if (fsig->params [0]->type == MONO_TYPE_U4)
6443                                         opcode = OP_IMAX_UN;
6444                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
6445                                         opcode = OP_LMAX;
6446                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
6447                                         opcode = OP_LMAX_UN;
6448                         }
6449                 }
6450
6451                 if (opcode) {
6452                         MONO_INST_NEW (cfg, ins, opcode);
6453                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6454                         ins->dreg = mono_alloc_ireg (cfg);
6455                         ins->sreg1 = args [0]->dreg;
6456                         ins->sreg2 = args [1]->dreg;
6457                         MONO_ADD_INS (cfg->cbb, ins);
6458                 }
6459
6460 #if 0
6461                 /* OP_FREM is not IEEE compatible */
6462                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6463                         MONO_INST_NEW (cfg, ins, OP_FREM);
6464                         ins->inst_i0 = args [0];
6465                         ins->inst_i1 = args [1];
6466                 }
6467 #endif
6468         }
6469
6470         /*
6471          * Can't implement CompareExchange methods this way since they have
6472          * three arguments.
6473          */
6474
6475         return ins;
6476 }
6477
6478 gboolean
6479 mono_arch_print_tree (MonoInst *tree, int arity)
6480 {
6481         return 0;
6482 }
6483
6484 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6485 {
6486         MonoInst* ins;
6487
6488         if (appdomain_tls_offset == -1)
6489                 return NULL;
6490
6491         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6492         ins->inst_offset = appdomain_tls_offset;
6493         return ins;
6494 }
6495
6496 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6497 {
6498         MonoInst* ins;
6499
6500         if (thread_tls_offset == -1)
6501                 return NULL;
6502
6503         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6504         ins->inst_offset = thread_tls_offset;
6505         return ins;
6506 }
6507
6508 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6509
6510 gpointer
6511 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6512 {
6513         switch (reg) {
6514         case AMD64_RCX: return (gpointer)ctx->rcx;
6515         case AMD64_RDX: return (gpointer)ctx->rdx;
6516         case AMD64_RBX: return (gpointer)ctx->rbx;
6517         case AMD64_RBP: return (gpointer)ctx->rbp;
6518         case AMD64_RSP: return (gpointer)ctx->rsp;
6519         default:
6520                 if (reg < 8)
6521                         return _CTX_REG (ctx, rax, reg);
6522                 else if (reg >= 12)
6523                         return _CTX_REG (ctx, r12, reg - 12);
6524                 else
6525                         g_assert_not_reached ();
6526         }
6527 }