mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 MonoBreakpointInfo
  69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  70
  71 /*
  72  * The code generated for sequence points reads from this location, which is
  73  * made read-only when single stepping is enabled.
  74  */
  75 static gpointer ss_trigger_page;
  76
  77 /* Enabled breakpoints read from this trigger page */
  78 static gpointer bp_trigger_page;
  79
  80 /* The size of the breakpoint sequence */
  81 static int breakpoint_size;
  82
  83 /* The size of the breakpoint instruction causing the actual fault */
  84 static int breakpoint_fault_size;
  85
  86 /* The size of the single step instruction causing the actual fault */
  87 static int single_step_fault_size;
  88
  89 /* The single step trampoline */
  90 static gpointer ss_trampoline;
  91
  92 /* Offset between fp and the first argument in the callee */
  93 #define ARGS_OFFSET 16
  94 #define GP_SCRATCH_REG AMD64_R11
  95
  96 /*
  97  * AMD64 register usage:
  98  * - callee saved registers are used for global register allocation
  99  * - %r11 is used for materializing 64 bit constants in opcodes
 100  * - the rest is used for local allocation
 101  */
 102
 103 /*
 104  * Floating point comparison results:
 105  *                  ZF PF CF
 106  * A > B            0  0  0
 107  * A < B            0  0  1
 108  * A = B            1  0  0
 109  * A > B            0  0  0
 110  * UNORDERED        1  1  1
 111  */
 112
 113 const char*
 114 mono_arch_regname (int reg)
 115 {
 116         switch (reg) {
 117         case AMD64_RAX: return "%rax";
 118         case AMD64_RBX: return "%rbx";
 119         case AMD64_RCX: return "%rcx";
 120         case AMD64_RDX: return "%rdx";
 121         case AMD64_RSP: return "%rsp";
 122         case AMD64_RBP: return "%rbp";
 123         case AMD64_RDI: return "%rdi";
 124         case AMD64_RSI: return "%rsi";
 125         case AMD64_R8: return "%r8";
 126         case AMD64_R9: return "%r9";
 127         case AMD64_R10: return "%r10";
 128         case AMD64_R11: return "%r11";
 129         case AMD64_R12: return "%r12";
 130         case AMD64_R13: return "%r13";
 131         case AMD64_R14: return "%r14";
 132         case AMD64_R15: return "%r15";
 133         }
 134         return "unknown";
 135 }
 136
 137 static const char * packed_xmmregs [] = {
 138         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 139         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 140 };
 141
 142 static const char * single_xmmregs [] = {
 143         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 144         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 145 };
 146
 147 const char*
 148 mono_arch_fregname (int reg)
 149 {
 150         if (reg < AMD64_XMM_NREG)
 151                 return single_xmmregs [reg];
 152         else
 153                 return "unknown";
 154 }
 155
 156 const char *
 157 mono_arch_xregname (int reg)
 158 {
 159         if (reg < AMD64_XMM_NREG)
 160                 return packed_xmmregs [reg];
 161         else
 162                 return "unknown";
 163 }
 164
 165 static gboolean
 166 debug_omit_fp (void)
 167 {
 168 #if 0
 169         return mono_debug_count ();
 170 #else
 171         return TRUE;
 172 #endif
 173 }
 174
 175 static inline gboolean
 176 amd64_is_near_call (guint8 *code)
 177 {
 178         /* Skip REX */
 179         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 180                 code += 1;
 181
 182         return code [0] == 0xe8;
 183 }
 184
 185 #ifdef __native_client_codegen__
 186
 187 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 188 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 189 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 190 /* We only want to force bundle alignment for the top level instruction,    */
 191 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 192 static MonoNativeTlsKey nacl_instruction_depth;
 193
 194 static MonoNativeTlsKey nacl_rex_tag;
 195 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 196
 197 void
 198 amd64_nacl_clear_legacy_prefix_tag ()
 199 {
 200         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 201 }
 202
 203 void
 204 amd64_nacl_tag_legacy_prefix (guint8* code)
 205 {
 206         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 207                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 208 }
 209
 210 void
 211 amd64_nacl_tag_rex (guint8* code)
 212 {
 213         mono_native_tls_set_value (nacl_rex_tag, code);
 214 }
 215
 216 guint8*
 217 amd64_nacl_get_legacy_prefix_tag ()
 218 {
 219         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 220 }
 221
 222 guint8*
 223 amd64_nacl_get_rex_tag ()
 224 {
 225         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 226 }
 227
 228 /* Increment the instruction "depth" described above */
 229 void
 230 amd64_nacl_instruction_pre ()
 231 {
 232         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 233         depth++;
 234         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 235 }
 236
 237 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 238 /* alignment if depth == 0 (top level instruction)                          */
 239 /* IN: start, end    pointers to instruction beginning and end              */
 240 /* OUT: start, end   pointers to beginning and end after possible alignment */
 241 /* GLOBALS: nacl_instruction_depth     defined above                        */
 242 void
 243 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 244 {
 245         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 246         depth--;
 247         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 248
 249         g_assert ( depth >= 0 );
 250         if (depth == 0) {
 251                 uintptr_t space_in_block;
 252                 uintptr_t instlen;
 253                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 254                 /* if legacy prefix is present, and if it was emitted before */
 255                 /* the start of the instruction sequence, adjust the start   */
 256                 if (prefix != NULL && prefix < *start) {
 257                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 258                         *start = prefix;
 259                 }
 260                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 261                 instlen = (uintptr_t)(*end - *start);
 262                 /* Only check for instructions which are less than        */
 263                 /* kNaClAlignment. The only instructions that should ever */
 264                 /* be that long are call sequences, which are already     */
 265                 /* padded out to align the return to the next bundle.     */
 266                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 267                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 268                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 269                         const size_t length = (size_t)((*end)-(*start));
 270                         g_assert (length < MAX_NACL_INST_LENGTH);
 271
 272                         memcpy (copy_of_instruction, *start, length);
 273                         *start = mono_arch_nacl_pad (*start, space_in_block);
 274                         memcpy (*start, copy_of_instruction, length);
 275                         *end = *start + length;
 276                 }
 277                 amd64_nacl_clear_legacy_prefix_tag ();
 278                 amd64_nacl_tag_rex (NULL);
 279         }
 280 }
 281
 282 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 283 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 284 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 285 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 286 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 287 /* IN:      code                                                            */
 288 /*             pointer to current instruction stream (in the                */
 289 /*             middle of an instruction, after opcode is emitted)           */
 290 /*          basereg/offset/dreg                                             */
 291 /*             operands of normal membase address                           */
 292 /* OUT:     code                                                            */
 293 /*             pointer to the end of the membase/memindex emit              */
 294 /* GLOBALS: nacl_rex_tag                                                    */
 295 /*             position in instruction stream that rex prefix was emitted   */
 296 /*          nacl_legacy_prefix_tag                                          */
 297 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 298 void
 299 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 300 {
 301         gint8 true_basereg = basereg;
 302
 303         /* Cache these values, they might change  */
 304         /* as new instructions are emitted below. */
 305         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 306         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 307
 308         /* 'basereg' is given masked to 0x7 at this point, so check */
 309         /* the rex prefix to see if this is an extended register.   */
 310         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 311                 true_basereg |= 0x8;
 312         }
 313
 314 #define X86_LEA_OPCODE (0x8D)
 315
 316         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 317                 guint8* old_instruction_start;
 318
 319                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 320                 /* 32-bits of the old base register (new index register)     */
 321                 guint8 buf[32];
 322                 guint8* buf_ptr = buf;
 323                 size_t insert_len;
 324
 325                 g_assert (rex_tag != NULL);
 326
 327                 if (IS_REX(*rex_tag)) {
 328                         /* The old rex.B should be the new rex.X */
 329                         if (*rex_tag & AMD64_REX_B) {
 330                                 *rex_tag |= AMD64_REX_X;
 331                         }
 332                         /* Since our new base is %r15 set rex.B */
 333                         *rex_tag |= AMD64_REX_B;
 334                 } else {
 335                         /* Shift the instruction by one byte  */
 336                         /* so we can insert a rex prefix      */
 337                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 338                         *code += 1;
 339                         /* New rex prefix only needs rex.B for %r15 base */
 340                         *rex_tag = AMD64_REX(AMD64_REX_B);
 341                 }
 342
 343                 if (legacy_prefix_tag) {
 344                         old_instruction_start = legacy_prefix_tag;
 345                 } else {
 346                         old_instruction_start = rex_tag;
 347                 }
 348
 349                 /* Clears the upper 32-bits of the previous base register */
 350                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 351                 insert_len = buf_ptr - buf;
 352
 353                 /* Move the old instruction forward to make */
 354                 /* room for 'mov' stored in 'buf_ptr'       */
 355                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 356                 *code += insert_len;
 357                 memcpy (old_instruction_start, buf, insert_len);
 358
 359                 /* Sandboxed replacement for the normal membase_emit */
 360                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 361
 362         } else {
 363                 /* Normal default behavior, emit membase memory location */
 364                 x86_membase_emit_body (*code, dreg, basereg, offset);
 365         }
 366 }
 367
 368
 369 static inline unsigned char*
 370 amd64_skip_nops (unsigned char* code)
 371 {
 372         guint8 in_nop;
 373         do {
 374                 in_nop = 0;
 375                 if (   code[0] == 0x90) {
 376                         in_nop = 1;
 377                         code += 1;
 378                 }
 379                 if (   code[0] == 0x66 && code[1] == 0x90) {
 380                         in_nop = 1;
 381                         code += 2;
 382                 }
 383                 if (code[0] == 0x0f && code[1] == 0x1f
 384                  && code[2] == 0x00) {
 385                         in_nop = 1;
 386                         code += 3;
 387                 }
 388                 if (code[0] == 0x0f && code[1] == 0x1f
 389                  && code[2] == 0x40 && code[3] == 0x00) {
 390                         in_nop = 1;
 391                         code += 4;
 392                 }
 393                 if (code[0] == 0x0f && code[1] == 0x1f
 394                  && code[2] == 0x44 && code[3] == 0x00
 395                  && code[4] == 0x00) {
 396                         in_nop = 1;
 397                         code += 5;
 398                 }
 399                 if (code[0] == 0x66 && code[1] == 0x0f
 400                  && code[2] == 0x1f && code[3] == 0x44
 401                  && code[4] == 0x00 && code[5] == 0x00) {
 402                         in_nop = 1;
 403                         code += 6;
 404                 }
 405                 if (code[0] == 0x0f && code[1] == 0x1f
 406                  && code[2] == 0x80 && code[3] == 0x00
 407                  && code[4] == 0x00 && code[5] == 0x00
 408                  && code[6] == 0x00) {
 409                         in_nop = 1;
 410                         code += 7;
 411                 }
 412                 if (code[0] == 0x0f && code[1] == 0x1f
 413                  && code[2] == 0x84 && code[3] == 0x00
 414                  && code[4] == 0x00 && code[5] == 0x00
 415                  && code[6] == 0x00 && code[7] == 0x00) {
 416                         in_nop = 1;
 417                         code += 8;
 418                 }
 419         } while ( in_nop );
 420         return code;
 421 }
 422
 423 guint8*
 424 mono_arch_nacl_skip_nops (guint8* code)
 425 {
 426   return amd64_skip_nops(code);
 427 }
 428
 429 #endif /*__native_client_codegen__*/
 430
 431 static inline void
 432 amd64_patch (unsigned char* code, gpointer target)
 433 {
 434         guint8 rex = 0;
 435
 436 #ifdef __native_client_codegen__
 437         code = amd64_skip_nops (code);
 438 #endif
 439 #if defined(__native_client_codegen__) && defined(__native_client__)
 440         if (nacl_is_code_address (code)) {
 441                 /* For tail calls, code is patched after being installed */
 442                 /* but not through the normal "patch callsite" method.   */
 443                 unsigned char buf[kNaClAlignment];
 444                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 445                 int ret;
 446                 memcpy (buf, aligned_code, kNaClAlignment);
 447                 /* Patch a temp buffer of bundle size, */
 448                 /* then install to actual location.    */
 449                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 450                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 451                 g_assert (ret == 0);
 452                 return;
 453         }
 454         target = nacl_modify_patch_target (target);
 455 #endif
 456
 457         /* Skip REX */
 458         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 459                 rex = code [0];
 460                 code += 1;
 461         }
 462
 463         if ((code [0] & 0xf8) == 0xb8) {
 464                 /* amd64_set_reg_template */
 465                 *(guint64*)(code + 1) = (guint64)target;
 466         }
 467         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 468                 /* mov 0(%rip), %dreg */
 469                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 470         }
 471         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 472                 /* call *<OFFSET>(%rip) */
 473                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 474         }
 475         else if (code [0] == 0xe8) {
 476                 /* call <DISP> */
 477                 gint64 disp = (guint8*)target - (guint8*)code;
 478                 g_assert (amd64_is_imm32 (disp));
 479                 x86_patch (code, (unsigned char*)target);
 480         }
 481         else
 482                 x86_patch (code, (unsigned char*)target);
 483 }
 484
 485 void
 486 mono_amd64_patch (unsigned char* code, gpointer target)
 487 {
 488         amd64_patch (code, target);
 489 }
 490
 491 typedef enum {
 492         ArgInIReg,
 493         ArgInFloatSSEReg,
 494         ArgInDoubleSSEReg,
 495         ArgOnStack,
 496         ArgValuetypeInReg,
 497         ArgValuetypeAddrInIReg,
 498         ArgNone /* only in pair_storage */
 499 } ArgStorage;
 500
 501 typedef struct {
 502         gint16 offset;
 503         gint8  reg;
 504         ArgStorage storage;
 505
 506         /* Only if storage == ArgValuetypeInReg */
 507         ArgStorage pair_storage [2];
 508         gint8 pair_regs [2];
 509         /* The size of each pair */
 510         int pair_size [2];
 511         int nregs;
 512 } ArgInfo;
 513
 514 typedef struct {
 515         int nargs;
 516         guint32 stack_usage;
 517         guint32 reg_usage;
 518         guint32 freg_usage;
 519         gboolean need_stack_align;
 520         gboolean vtype_retaddr;
 521         /* The index of the vret arg in the argument list */
 522         int vret_arg_index;
 523         ArgInfo ret;
 524         ArgInfo sig_cookie;
 525         ArgInfo args [1];
 526 } CallInfo;
 527
 528 #define DEBUG(a) if (cfg->verbose_level > 1) a
 529
 530 #ifdef TARGET_WIN32
 531 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 532
 533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #else
 535 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 536
 537  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 538 #endif
 539
 540 static void inline
 541 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 542 {
 543     ainfo->offset = *stack_size;
 544
 545     if (*gr >= PARAM_REGS) {
 546                 ainfo->storage = ArgOnStack;
 547                 /* Since the same stack slot size is used for all arg */
 548                 /*  types, it needs to be big enough to hold them all */
 549                 (*stack_size) += sizeof(mgreg_t);
 550     }
 551     else {
 552                 ainfo->storage = ArgInIReg;
 553                 ainfo->reg = param_regs [*gr];
 554                 (*gr) ++;
 555     }
 556 }
 557
 558 #ifdef TARGET_WIN32
 559 #define FLOAT_PARAM_REGS 4
 560 #else
 561 #define FLOAT_PARAM_REGS 8
 562 #endif
 563
 564 static void inline
 565 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 566 {
 567     ainfo->offset = *stack_size;
 568
 569     if (*gr >= FLOAT_PARAM_REGS) {
 570                 ainfo->storage = ArgOnStack;
 571                 /* Since the same stack slot size is used for both float */
 572                 /*  types, it needs to be big enough to hold them both */
 573                 (*stack_size) += sizeof(mgreg_t);
 574     }
 575     else {
 576                 /* A double register */
 577                 if (is_double)
 578                         ainfo->storage = ArgInDoubleSSEReg;
 579                 else
 580                         ainfo->storage = ArgInFloatSSEReg;
 581                 ainfo->reg = *gr;
 582                 (*gr) += 1;
 583     }
 584 }
 585
 586 typedef enum ArgumentClass {
 587         ARG_CLASS_NO_CLASS,
 588         ARG_CLASS_MEMORY,
 589         ARG_CLASS_INTEGER,
 590         ARG_CLASS_SSE
 591 } ArgumentClass;
 592
 593 static ArgumentClass
 594 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 595 {
 596         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 597         MonoType *ptype;
 598
 599         ptype = mini_get_underlying_type (type);
 600         switch (ptype->type) {
 601         case MONO_TYPE_I1:
 602         case MONO_TYPE_U1:
 603         case MONO_TYPE_I2:
 604         case MONO_TYPE_U2:
 605         case MONO_TYPE_I4:
 606         case MONO_TYPE_U4:
 607         case MONO_TYPE_I:
 608         case MONO_TYPE_U:
 609         case MONO_TYPE_STRING:
 610         case MONO_TYPE_OBJECT:
 611         case MONO_TYPE_CLASS:
 612         case MONO_TYPE_SZARRAY:
 613         case MONO_TYPE_PTR:
 614         case MONO_TYPE_FNPTR:
 615         case MONO_TYPE_ARRAY:
 616         case MONO_TYPE_I8:
 617         case MONO_TYPE_U8:
 618                 class2 = ARG_CLASS_INTEGER;
 619                 break;
 620         case MONO_TYPE_R4:
 621         case MONO_TYPE_R8:
 622 #ifdef TARGET_WIN32
 623                 class2 = ARG_CLASS_INTEGER;
 624 #else
 625                 class2 = ARG_CLASS_SSE;
 626 #endif
 627                 break;
 628
 629         case MONO_TYPE_TYPEDBYREF:
 630                 g_assert_not_reached ();
 631
 632         case MONO_TYPE_GENERICINST:
 633                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 634                         class2 = ARG_CLASS_INTEGER;
 635                         break;
 636                 }
 637                 /* fall through */
 638         case MONO_TYPE_VALUETYPE: {
 639                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 640                 int i;
 641
 642                 for (i = 0; i < info->num_fields; ++i) {
 643                         class2 = class1;
 644                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 645                 }
 646                 break;
 647         }
 648         default:
 649                 g_assert_not_reached ();
 650         }
 651
 652         /* Merge */
 653         if (class1 == class2)
 654                 ;
 655         else if (class1 == ARG_CLASS_NO_CLASS)
 656                 class1 = class2;
 657         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 658                 class1 = ARG_CLASS_MEMORY;
 659         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 660                 class1 = ARG_CLASS_INTEGER;
 661         else
 662                 class1 = ARG_CLASS_SSE;
 663
 664         return class1;
 665 }
 666 #ifdef __native_client_codegen__
 667
 668 /* Default alignment for Native Client is 32-byte. */
 669 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 670
 671 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 672 /* Check that alignment doesn't cross an alignment boundary.             */
 673 guint8*
 674 mono_arch_nacl_pad(guint8 *code, int pad)
 675 {
 676         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 677
 678         if (pad == 0) return code;
 679         /* assertion: alignment cannot cross a block boundary */
 680         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 681                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 682         while (pad >= kMaxPadding) {
 683                 amd64_padding (code, kMaxPadding);
 684                 pad -= kMaxPadding;
 685         }
 686         if (pad != 0) amd64_padding (code, pad);
 687         return code;
 688 }
 689 #endif
 690
 691 static int
 692 count_fields_nested (MonoClass *klass)
 693 {
 694         MonoMarshalType *info;
 695         int i, count;
 696
 697         info = mono_marshal_load_type_info (klass);
 698         g_assert(info);
 699         count = 0;
 700         for (i = 0; i < info->num_fields; ++i) {
 701                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 702                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 703                 else
 704                         count ++;
 705         }
 706         return count;
 707 }
 708
 709 static int
 710 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 711 {
 712         MonoMarshalType *info;
 713         int i;
 714
 715         info = mono_marshal_load_type_info (klass);
 716         g_assert(info);
 717         for (i = 0; i < info->num_fields; ++i) {
 718                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 719                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 720                 } else {
 721                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 722                         fields [index].offset += offset;
 723                         index ++;
 724                 }
 725         }
 726         return index;
 727 }
 728
 729 static void
 730 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 731                            gboolean is_return,
 732                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 733 {
 734         guint32 size, quad, nquads, i, nfields;
 735         /* Keep track of the size used in each quad so we can */
 736         /* use the right size when copying args/return vars.  */
 737         guint32 quadsize [2] = {8, 8};
 738         ArgumentClass args [2];
 739         MonoMarshalType *info = NULL;
 740         MonoMarshalField *fields = NULL;
 741         MonoClass *klass;
 742         gboolean pass_on_stack = FALSE;
 743
 744         klass = mono_class_from_mono_type (type);
 745         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 746 #ifndef TARGET_WIN32
 747         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 748                 /* We pass and return vtypes of size 8 in a register */
 749         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 750                 pass_on_stack = TRUE;
 751         }
 752 #else
 753         if (!sig->pinvoke) {
 754                 pass_on_stack = TRUE;
 755         }
 756 #endif
 757
 758         /* If this struct can't be split up naturally into 8-byte */
 759         /* chunks (registers), pass it on the stack.              */
 760         if (sig->pinvoke && !pass_on_stack) {
 761                 guint32 align;
 762                 guint32 field_size;
 763
 764                 info = mono_marshal_load_type_info (klass);
 765                 g_assert (info);
 766
 767                 /*
 768                  * Collect field information recursively to be able to
 769                  * handle nested structures.
 770                  */
 771                 nfields = count_fields_nested (klass);
 772                 fields = g_new0 (MonoMarshalField, nfields);
 773                 collect_field_info_nested (klass, fields, 0, 0);
 774
 775                 for (i = 0; i < nfields; ++i) {
 776                         field_size = mono_marshal_type_size (fields [i].field->type,
 777                                                            fields [i].mspec,
 778                                                            &align, TRUE, klass->unicode);
 779                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 780                                 pass_on_stack = TRUE;
 781                                 break;
 782                         }
 783                 }
 784         }
 785
 786 #ifndef TARGET_WIN32
 787         if (size == 0) {
 788                 ainfo->storage = ArgValuetypeInReg;
 789                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 790                 return;
 791         }
 792 #endif
 793
 794         if (pass_on_stack) {
 795                 /* Allways pass in memory */
 796                 ainfo->offset = *stack_size;
 797                 *stack_size += ALIGN_TO (size, 8);
 798                 ainfo->storage = ArgOnStack;
 799
 800                 g_free (fields);
 801                 return;
 802         }
 803
 804         /* FIXME: Handle structs smaller than 8 bytes */
 805         //if ((size % 8) != 0)
 806         //      NOT_IMPLEMENTED;
 807
 808         if (size > 8)
 809                 nquads = 2;
 810         else
 811                 nquads = 1;
 812
 813         if (!sig->pinvoke) {
 814                 int n = mono_class_value_size (klass, NULL);
 815
 816                 quadsize [0] = n >= 8 ? 8 : n;
 817                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 818
 819                 /* Always pass in 1 or 2 integer registers */
 820                 args [0] = ARG_CLASS_INTEGER;
 821                 args [1] = ARG_CLASS_INTEGER;
 822                 /* Only the simplest cases are supported */
 823                 if (is_return && nquads != 1) {
 824                         args [0] = ARG_CLASS_MEMORY;
 825                         args [1] = ARG_CLASS_MEMORY;
 826                 }
 827         } else {
 828                 /*
 829                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 830                  * The X87 and SSEUP stuff is left out since there are no such types in
 831                  * the CLR.
 832                  */
 833                 g_assert (info);
 834
 835                 if (!fields) {
 836                         ainfo->storage = ArgValuetypeInReg;
 837                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 838                         return;
 839                 }
 840
 841 #ifndef TARGET_WIN32
 842                 if (info->native_size > 16) {
 843                         ainfo->offset = *stack_size;
 844                         *stack_size += ALIGN_TO (info->native_size, 8);
 845                         ainfo->storage = ArgOnStack;
 846
 847                         g_free (fields);
 848                         return;
 849                 }
 850 #else
 851                 switch (info->native_size) {
 852                 case 1: case 2: case 4: case 8:
 853                         break;
 854                 default:
 855                         if (is_return) {
 856                                 ainfo->storage = ArgOnStack;
 857                                 ainfo->offset = *stack_size;
 858                                 *stack_size += ALIGN_TO (info->native_size, 8);
 859                         }
 860                         else {
 861                                 ainfo->storage = ArgValuetypeAddrInIReg;
 862
 863                                 if (*gr < PARAM_REGS) {
 864                                         ainfo->pair_storage [0] = ArgInIReg;
 865                                         ainfo->pair_regs [0] = param_regs [*gr];
 866                                         (*gr) ++;
 867                                 }
 868                                 else {
 869                                         ainfo->pair_storage [0] = ArgOnStack;
 870                                         ainfo->offset = *stack_size;
 871                                         *stack_size += 8;
 872                                 }
 873                         }
 874
 875                         g_free (fields);
 876                         return;
 877                 }
 878 #endif
 879
 880                 args [0] = ARG_CLASS_NO_CLASS;
 881                 args [1] = ARG_CLASS_NO_CLASS;
 882                 for (quad = 0; quad < nquads; ++quad) {
 883                         int size;
 884                         guint32 align;
 885                         ArgumentClass class1;
 886
 887                         if (nfields == 0)
 888                                 class1 = ARG_CLASS_MEMORY;
 889                         else
 890                                 class1 = ARG_CLASS_NO_CLASS;
 891                         for (i = 0; i < nfields; ++i) {
 892                                 size = mono_marshal_type_size (fields [i].field->type,
 893                                                                                            fields [i].mspec,
 894                                                                                            &align, TRUE, klass->unicode);
 895                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 896                                         /* Unaligned field */
 897                                         NOT_IMPLEMENTED;
 898                                 }
 899
 900                                 /* Skip fields in other quad */
 901                                 if ((quad == 0) && (fields [i].offset >= 8))
 902                                         continue;
 903                                 if ((quad == 1) && (fields [i].offset < 8))
 904                                         continue;
 905
 906                                 /* How far into this quad this data extends.*/
 907                                 /* (8 is size of quad) */
 908                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 909
 910                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 911                         }
 912                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 913                         args [quad] = class1;
 914                 }
 915         }
 916
 917         g_free (fields);
 918
 919         /* Post merger cleanup */
 920         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 921                 args [0] = args [1] = ARG_CLASS_MEMORY;
 922
 923         /* Allocate registers */
 924         {
 925                 int orig_gr = *gr;
 926                 int orig_fr = *fr;
 927
 928                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 929                         quadsize [0] ++;
 930                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 931                         quadsize [1] ++;
 932
 933                 ainfo->storage = ArgValuetypeInReg;
 934                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 935                 g_assert (quadsize [0] <= 8);
 936                 g_assert (quadsize [1] <= 8);
 937                 ainfo->pair_size [0] = quadsize [0];
 938                 ainfo->pair_size [1] = quadsize [1];
 939                 ainfo->nregs = nquads;
 940                 for (quad = 0; quad < nquads; ++quad) {
 941                         switch (args [quad]) {
 942                         case ARG_CLASS_INTEGER:
 943                                 if (*gr >= PARAM_REGS)
 944                                         args [quad] = ARG_CLASS_MEMORY;
 945                                 else {
 946                                         ainfo->pair_storage [quad] = ArgInIReg;
 947                                         if (is_return)
 948                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 949                                         else
 950                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 951                                         (*gr) ++;
 952                                 }
 953                                 break;
 954                         case ARG_CLASS_SSE:
 955                                 if (*fr >= FLOAT_PARAM_REGS)
 956                                         args [quad] = ARG_CLASS_MEMORY;
 957                                 else {
 958                                         if (quadsize[quad] <= 4)
 959                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 960                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 961                                         ainfo->pair_regs [quad] = *fr;
 962                                         (*fr) ++;
 963                                 }
 964                                 break;
 965                         case ARG_CLASS_MEMORY:
 966                                 break;
 967                         default:
 968                                 g_assert_not_reached ();
 969                         }
 970                 }
 971
 972                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 973                         /* Revert possible register assignments */
 974                         *gr = orig_gr;
 975                         *fr = orig_fr;
 976
 977                         ainfo->offset = *stack_size;
 978                         if (sig->pinvoke)
 979                                 *stack_size += ALIGN_TO (info->native_size, 8);
 980                         else
 981                                 *stack_size += nquads * sizeof(mgreg_t);
 982                         ainfo->storage = ArgOnStack;
 983                 }
 984         }
 985 }
 986
 987 /*
 988  * get_call_info:
 989  *
 990  *  Obtain information about a call according to the calling convention.
 991  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 992  * Draft Version 0.23" document for more information.
 993  */
 994 static CallInfo*
 995 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 996 {
 997         guint32 i, gr, fr, pstart;
 998         MonoType *ret_type;
 999         int n = sig->hasthis + sig->param_count;
1000         guint32 stack_size = 0;
1001         CallInfo *cinfo;
1002         gboolean is_pinvoke = sig->pinvoke;
1003
1004         if (mp)
1005                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1006         else
1007                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1008
1009         cinfo->nargs = n;
1010
1011         gr = 0;
1012         fr = 0;
1013
1014 #ifdef TARGET_WIN32
1015         /* Reserve space where the callee can save the argument registers */
1016         stack_size = 4 * sizeof (mgreg_t);
1017 #endif
1018
1019         /* return value */
1020         ret_type = mini_get_underlying_type (sig->ret);
1021         switch (ret_type->type) {
1022         case MONO_TYPE_I1:
1023         case MONO_TYPE_U1:
1024         case MONO_TYPE_I2:
1025         case MONO_TYPE_U2:
1026         case MONO_TYPE_I4:
1027         case MONO_TYPE_U4:
1028         case MONO_TYPE_I:
1029         case MONO_TYPE_U:
1030         case MONO_TYPE_PTR:
1031         case MONO_TYPE_FNPTR:
1032         case MONO_TYPE_CLASS:
1033         case MONO_TYPE_OBJECT:
1034         case MONO_TYPE_SZARRAY:
1035         case MONO_TYPE_ARRAY:
1036         case MONO_TYPE_STRING:
1037                 cinfo->ret.storage = ArgInIReg;
1038                 cinfo->ret.reg = AMD64_RAX;
1039                 break;
1040         case MONO_TYPE_U8:
1041         case MONO_TYPE_I8:
1042                 cinfo->ret.storage = ArgInIReg;
1043                 cinfo->ret.reg = AMD64_RAX;
1044                 break;
1045         case MONO_TYPE_R4:
1046                 cinfo->ret.storage = ArgInFloatSSEReg;
1047                 cinfo->ret.reg = AMD64_XMM0;
1048                 break;
1049         case MONO_TYPE_R8:
1050                 cinfo->ret.storage = ArgInDoubleSSEReg;
1051                 cinfo->ret.reg = AMD64_XMM0;
1052                 break;
1053         case MONO_TYPE_GENERICINST:
1054                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1055                         cinfo->ret.storage = ArgInIReg;
1056                         cinfo->ret.reg = AMD64_RAX;
1057                         break;
1058                 }
1059                 /* fall through */
1060 #if defined( __native_client_codegen__ )
1061         case MONO_TYPE_TYPEDBYREF:
1062 #endif
1063         case MONO_TYPE_VALUETYPE: {
1064                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1065
1066                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1067                 if (cinfo->ret.storage == ArgOnStack) {
1068                         cinfo->vtype_retaddr = TRUE;
1069                         /* The caller passes the address where the value is stored */
1070                 }
1071                 break;
1072         }
1073 #if !defined( __native_client_codegen__ )
1074         case MONO_TYPE_TYPEDBYREF:
1075                 /* Same as a valuetype with size 24 */
1076                 cinfo->vtype_retaddr = TRUE;
1077                 break;
1078 #endif
1079         case MONO_TYPE_VOID:
1080                 break;
1081         default:
1082                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1083         }
1084
1085         pstart = 0;
1086         /*
1087          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1088          * the first argument, allowing 'this' to be always passed in the first arg reg.
1089          * Also do this if the first argument is a reference type, since virtual calls
1090          * are sometimes made using calli without sig->hasthis set, like in the delegate
1091          * invoke wrappers.
1092          */
1093         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1094                 if (sig->hasthis) {
1095                         add_general (&gr, &stack_size, cinfo->args + 0);
1096                 } else {
1097                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1098                         pstart = 1;
1099                 }
1100                 add_general (&gr, &stack_size, &cinfo->ret);
1101                 cinfo->vret_arg_index = 1;
1102         } else {
1103                 /* this */
1104                 if (sig->hasthis)
1105                         add_general (&gr, &stack_size, cinfo->args + 0);
1106
1107                 if (cinfo->vtype_retaddr)
1108                         add_general (&gr, &stack_size, &cinfo->ret);
1109         }
1110
1111         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1112                 gr = PARAM_REGS;
1113                 fr = FLOAT_PARAM_REGS;
1114
1115                 /* Emit the signature cookie just before the implicit arguments */
1116                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1117         }
1118
1119         for (i = pstart; i < sig->param_count; ++i) {
1120                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1121                 MonoType *ptype;
1122
1123 #ifdef TARGET_WIN32
1124                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1125                 if (gr > fr)
1126                         fr = gr;
1127                 else if (fr > gr)
1128                         gr = fr;
1129 #endif
1130
1131                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1132                         /* We allways pass the sig cookie on the stack for simplicity */
1133                         /*
1134                          * Prevent implicit arguments + the sig cookie from being passed
1135                          * in registers.
1136                          */
1137                         gr = PARAM_REGS;
1138                         fr = FLOAT_PARAM_REGS;
1139
1140                         /* Emit the signature cookie just before the implicit arguments */
1141                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1142                 }
1143
1144                 ptype = mini_get_underlying_type (sig->params [i]);
1145                 switch (ptype->type) {
1146                 case MONO_TYPE_I1:
1147                 case MONO_TYPE_U1:
1148                         add_general (&gr, &stack_size, ainfo);
1149                         break;
1150                 case MONO_TYPE_I2:
1151                 case MONO_TYPE_U2:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I4:
1155                 case MONO_TYPE_U4:
1156                         add_general (&gr, &stack_size, ainfo);
1157                         break;
1158                 case MONO_TYPE_I:
1159                 case MONO_TYPE_U:
1160                 case MONO_TYPE_PTR:
1161                 case MONO_TYPE_FNPTR:
1162                 case MONO_TYPE_CLASS:
1163                 case MONO_TYPE_OBJECT:
1164                 case MONO_TYPE_STRING:
1165                 case MONO_TYPE_SZARRAY:
1166                 case MONO_TYPE_ARRAY:
1167                         add_general (&gr, &stack_size, ainfo);
1168                         break;
1169                 case MONO_TYPE_GENERICINST:
1170                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1171                                 add_general (&gr, &stack_size, ainfo);
1172                                 break;
1173                         }
1174                         /* fall through */
1175                 case MONO_TYPE_VALUETYPE:
1176                 case MONO_TYPE_TYPEDBYREF:
1177                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178                         break;
1179                 case MONO_TYPE_U8:
1180
1181                 case MONO_TYPE_I8:
1182                         add_general (&gr, &stack_size, ainfo);
1183                         break;
1184                 case MONO_TYPE_R4:
1185                         add_float (&fr, &stack_size, ainfo, FALSE);
1186                         break;
1187                 case MONO_TYPE_R8:
1188                         add_float (&fr, &stack_size, ainfo, TRUE);
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1196                 gr = PARAM_REGS;
1197                 fr = FLOAT_PARAM_REGS;
1198
1199                 /* Emit the signature cookie just before the implicit arguments */
1200                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1201         }
1202
1203         cinfo->stack_usage = stack_size;
1204         cinfo->reg_usage = gr;
1205         cinfo->freg_usage = fr;
1206         return cinfo;
1207 }
1208
1209 /*
1210  * mono_arch_get_argument_info:
1211  * @csig:  a method signature
1212  * @param_count: the number of parameters to consider
1213  * @arg_info: an array to store the result infos
1214  *
1215  * Gathers information on parameters such as size, alignment and
1216  * padding. arg_info should be large enought to hold param_count + 1 entries.
1217  *
1218  * Returns the size of the argument area on the stack.
1219  */
1220 int
1221 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1222 {
1223         int k;
1224         CallInfo *cinfo = get_call_info (NULL, csig);
1225         guint32 args_size = cinfo->stack_usage;
1226
1227         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1228         if (csig->hasthis) {
1229                 arg_info [0].offset = 0;
1230         }
1231
1232         for (k = 0; k < param_count; k++) {
1233                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1234                 /* FIXME: */
1235                 arg_info [k + 1].size = 0;
1236         }
1237
1238         g_free (cinfo);
1239
1240         return args_size;
1241 }
1242
1243 gboolean
1244 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1245 {
1246         CallInfo *c1, *c2;
1247         gboolean res;
1248         MonoType *callee_ret;
1249
1250         c1 = get_call_info (NULL, caller_sig);
1251         c2 = get_call_info (NULL, callee_sig);
1252         res = c1->stack_usage >= c2->stack_usage;
1253         callee_ret = mini_get_underlying_type (callee_sig->ret);
1254         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1255                 /* An address on the callee's stack is passed as the first argument */
1256                 res = FALSE;
1257
1258         g_free (c1);
1259         g_free (c2);
1260
1261         return res;
1262 }
1263
1264 /*
1265  * Initialize the cpu to execute managed code.
1266  */
1267 void
1268 mono_arch_cpu_init (void)
1269 {
1270 #ifndef _MSC_VER
1271         guint16 fpcw;
1272
1273         /* spec compliance requires running with double precision */
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275         fpcw &= ~X86_FPCW_PRECC_MASK;
1276         fpcw |= X86_FPCW_PREC_DOUBLE;
1277         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1278         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 #else
1280         /* TODO: This is crashing on Win64 right now.
1281         * _control87 (_PC_53, MCW_PC);
1282         */
1283 #endif
1284 }
1285
1286 /*
1287  * Initialize architecture specific code.
1288  */
1289 void
1290 mono_arch_init (void)
1291 {
1292         int flags;
1293
1294         mono_mutex_init_recursive (&mini_arch_mutex);
1295 #if defined(__native_client_codegen__)
1296         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1297         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1298         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1299         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1300 #endif
1301
1302 #ifdef MONO_ARCH_NOMAP32BIT
1303         flags = MONO_MMAP_READ;
1304         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1305         breakpoint_size = 13;
1306         breakpoint_fault_size = 3;
1307 #else
1308         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1309         /* amd64_mov_reg_mem () */
1310         breakpoint_size = 8;
1311         breakpoint_fault_size = 8;
1312 #endif
1313
1314         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1315         single_step_fault_size = 4;
1316
1317         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1318         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1319         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1320
1321         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1322         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1323         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1324         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1325 }
1326
1327 /*
1328  * Cleanup architecture specific code.
1329  */
1330 void
1331 mono_arch_cleanup (void)
1332 {
1333         mono_mutex_destroy (&mini_arch_mutex);
1334 #if defined(__native_client_codegen__)
1335         mono_native_tls_free (nacl_instruction_depth);
1336         mono_native_tls_free (nacl_rex_tag);
1337         mono_native_tls_free (nacl_legacy_prefix_tag);
1338 #endif
1339 }
1340
1341 /*
1342  * This function returns the optimizations supported on this cpu.
1343  */
1344 guint32
1345 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1346 {
1347         guint32 opts = 0;
1348
1349         *exclude_mask = 0;
1350
1351         if (mono_hwcap_x86_has_cmov) {
1352                 opts |= MONO_OPT_CMOV;
1353
1354                 if (mono_hwcap_x86_has_fcmov)
1355                         opts |= MONO_OPT_FCMOV;
1356                 else
1357                         *exclude_mask |= MONO_OPT_FCMOV;
1358         } else {
1359                 *exclude_mask |= MONO_OPT_CMOV;
1360         }
1361
1362         return opts;
1363 }
1364
1365 /*
1366  * This function test for all SSE functions supported.
1367  *
1368  * Returns a bitmask corresponding to all supported versions.
1369  *
1370  */
1371 guint32
1372 mono_arch_cpu_enumerate_simd_versions (void)
1373 {
1374         guint32 sse_opts = 0;
1375
1376         if (mono_hwcap_x86_has_sse1)
1377                 sse_opts |= SIMD_VERSION_SSE1;
1378
1379         if (mono_hwcap_x86_has_sse2)
1380                 sse_opts |= SIMD_VERSION_SSE2;
1381
1382         if (mono_hwcap_x86_has_sse3)
1383                 sse_opts |= SIMD_VERSION_SSE3;
1384
1385         if (mono_hwcap_x86_has_ssse3)
1386                 sse_opts |= SIMD_VERSION_SSSE3;
1387
1388         if (mono_hwcap_x86_has_sse41)
1389                 sse_opts |= SIMD_VERSION_SSE41;
1390
1391         if (mono_hwcap_x86_has_sse42)
1392                 sse_opts |= SIMD_VERSION_SSE42;
1393
1394         if (mono_hwcap_x86_has_sse4a)
1395                 sse_opts |= SIMD_VERSION_SSE4a;
1396
1397         return sse_opts;
1398 }
1399
1400 #ifndef DISABLE_JIT
1401
1402 GList *
1403 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1404 {
1405         GList *vars = NULL;
1406         int i;
1407
1408         for (i = 0; i < cfg->num_varinfo; i++) {
1409                 MonoInst *ins = cfg->varinfo [i];
1410                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1411
1412                 /* unused vars */
1413                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1414                         continue;
1415
1416                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1417                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1418                         continue;
1419
1420                 if (mono_is_regsize_var (ins->inst_vtype)) {
1421                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1422                         g_assert (i == vmv->idx);
1423                         vars = g_list_prepend (vars, vmv);
1424                 }
1425         }
1426
1427         vars = mono_varlist_sort (cfg, vars, 0);
1428
1429         return vars;
1430 }
1431
1432 /**
1433  * mono_arch_compute_omit_fp:
1434  *
1435  *   Determine whenever the frame pointer can be eliminated.
1436  */
1437 static void
1438 mono_arch_compute_omit_fp (MonoCompile *cfg)
1439 {
1440         MonoMethodSignature *sig;
1441         MonoMethodHeader *header;
1442         int i, locals_size;
1443         CallInfo *cinfo;
1444
1445         if (cfg->arch.omit_fp_computed)
1446                 return;
1447
1448         header = cfg->header;
1449
1450         sig = mono_method_signature (cfg->method);
1451
1452         if (!cfg->arch.cinfo)
1453                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1454         cinfo = cfg->arch.cinfo;
1455
1456         /*
1457          * FIXME: Remove some of the restrictions.
1458          */
1459         cfg->arch.omit_fp = TRUE;
1460         cfg->arch.omit_fp_computed = TRUE;
1461
1462 #ifdef __native_client_codegen__
1463         /* NaCl modules may not change the value of RBP, so it cannot be */
1464         /* used as a normal register, but it can be used as a frame pointer*/
1465         cfg->disable_omit_fp = TRUE;
1466         cfg->arch.omit_fp = FALSE;
1467 #endif
1468
1469         if (cfg->disable_omit_fp)
1470                 cfg->arch.omit_fp = FALSE;
1471
1472         if (!debug_omit_fp ())
1473                 cfg->arch.omit_fp = FALSE;
1474         /*
1475         if (cfg->method->save_lmf)
1476                 cfg->arch.omit_fp = FALSE;
1477         */
1478         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1479                 cfg->arch.omit_fp = FALSE;
1480         if (header->num_clauses)
1481                 cfg->arch.omit_fp = FALSE;
1482         if (cfg->param_area)
1483                 cfg->arch.omit_fp = FALSE;
1484         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1485                 cfg->arch.omit_fp = FALSE;
1486         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1487                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1488                 cfg->arch.omit_fp = FALSE;
1489         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1490                 ArgInfo *ainfo = &cinfo->args [i];
1491
1492                 if (ainfo->storage == ArgOnStack) {
1493                         /*
1494                          * The stack offset can only be determined when the frame
1495                          * size is known.
1496                          */
1497                         cfg->arch.omit_fp = FALSE;
1498                 }
1499         }
1500
1501         locals_size = 0;
1502         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1503                 MonoInst *ins = cfg->varinfo [i];
1504                 int ialign;
1505
1506                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1507         }
1508 }
1509
1510 GList *
1511 mono_arch_get_global_int_regs (MonoCompile *cfg)
1512 {
1513         GList *regs = NULL;
1514
1515         mono_arch_compute_omit_fp (cfg);
1516
1517         if (cfg->arch.omit_fp)
1518                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1519
1520         /* We use the callee saved registers for global allocation */
1521         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1522         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1523         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1524         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1525 #ifndef __native_client_codegen__
1526         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1527 #endif
1528 #ifdef TARGET_WIN32
1529         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1530         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1531 #endif
1532
1533         return regs;
1534 }
1535
1536 GList*
1537 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1538 {
1539         GList *regs = NULL;
1540         int i;
1541
1542         /* All XMM registers */
1543         for (i = 0; i < 16; ++i)
1544                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1545
1546         return regs;
1547 }
1548
1549 GList*
1550 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1551 {
1552         static GList *r = NULL;
1553
1554         if (r == NULL) {
1555                 GList *regs = NULL;
1556
1557                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1558                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1559                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1560                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1561                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1562 #ifndef __native_client_codegen__
1563                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1564 #endif
1565
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1568                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1569                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1570                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1571                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1572                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1573                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1574
1575                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1576         }
1577
1578         return r;
1579 }
1580
1581 GList*
1582 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1583 {
1584         int i;
1585         static GList *r = NULL;
1586
1587         if (r == NULL) {
1588                 GList *regs = NULL;
1589
1590                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1591                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1592
1593                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1594         }
1595
1596         return r;
1597 }
1598
1599 /*
1600  * mono_arch_regalloc_cost:
1601  *
1602  *  Return the cost, in number of memory references, of the action of
1603  * allocating the variable VMV into a register during global register
1604  * allocation.
1605  */
1606 guint32
1607 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1608 {
1609         MonoInst *ins = cfg->varinfo [vmv->idx];
1610
1611         if (cfg->method->save_lmf)
1612                 /* The register is already saved */
1613                 /* substract 1 for the invisible store in the prolog */
1614                 return (ins->opcode == OP_ARG) ? 0 : 1;
1615         else
1616                 /* push+pop */
1617                 return (ins->opcode == OP_ARG) ? 1 : 2;
1618 }
1619
1620 /*
1621  * mono_arch_fill_argument_info:
1622  *
1623  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1624  * of the method.
1625  */
1626 void
1627 mono_arch_fill_argument_info (MonoCompile *cfg)
1628 {
1629         MonoType *sig_ret;
1630         MonoMethodSignature *sig;
1631         MonoInst *ins;
1632         int i;
1633         CallInfo *cinfo;
1634
1635         sig = mono_method_signature (cfg->method);
1636
1637         cinfo = cfg->arch.cinfo;
1638         sig_ret = mini_get_underlying_type (sig->ret);
1639
1640         /*
1641          * Contrary to mono_arch_allocate_vars (), the information should describe
1642          * where the arguments are at the beginning of the method, not where they can be
1643          * accessed during the execution of the method. The later makes no sense for the
1644          * global register allocator, since a variable can be in more than one location.
1645          */
1646         if (sig_ret->type != MONO_TYPE_VOID) {
1647                 switch (cinfo->ret.storage) {
1648                 case ArgInIReg:
1649                 case ArgInFloatSSEReg:
1650                 case ArgInDoubleSSEReg:
1651                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1652                                 cfg->vret_addr->opcode = OP_REGVAR;
1653                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1654                         }
1655                         else {
1656                                 cfg->ret->opcode = OP_REGVAR;
1657                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1658                         }
1659                         break;
1660                 case ArgValuetypeInReg:
1661                         cfg->ret->opcode = OP_REGOFFSET;
1662                         cfg->ret->inst_basereg = -1;
1663                         cfg->ret->inst_offset = -1;
1664                         break;
1665                 default:
1666                         g_assert_not_reached ();
1667                 }
1668         }
1669
1670         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1671                 ArgInfo *ainfo = &cinfo->args [i];
1672
1673                 ins = cfg->args [i];
1674
1675                 switch (ainfo->storage) {
1676                 case ArgInIReg:
1677                 case ArgInFloatSSEReg:
1678                 case ArgInDoubleSSEReg:
1679                         ins->opcode = OP_REGVAR;
1680                         ins->inst_c0 = ainfo->reg;
1681                         break;
1682                 case ArgOnStack:
1683                         ins->opcode = OP_REGOFFSET;
1684                         ins->inst_basereg = -1;
1685                         ins->inst_offset = -1;
1686                         break;
1687                 case ArgValuetypeInReg:
1688                         /* Dummy */
1689                         ins->opcode = OP_NOP;
1690                         break;
1691                 default:
1692                         g_assert_not_reached ();
1693                 }
1694         }
1695 }
1696
1697 void
1698 mono_arch_allocate_vars (MonoCompile *cfg)
1699 {
1700         MonoType *sig_ret;
1701         MonoMethodSignature *sig;
1702         MonoInst *ins;
1703         int i, offset;
1704         guint32 locals_stack_size, locals_stack_align;
1705         gint32 *offsets;
1706         CallInfo *cinfo;
1707
1708         sig = mono_method_signature (cfg->method);
1709
1710         cinfo = cfg->arch.cinfo;
1711         sig_ret = mini_get_underlying_type (sig->ret);
1712
1713         mono_arch_compute_omit_fp (cfg);
1714
1715         /*
1716          * We use the ABI calling conventions for managed code as well.
1717          * Exception: valuetypes are only sometimes passed or returned in registers.
1718          */
1719
1720         /*
1721          * The stack looks like this:
1722          * <incoming arguments passed on the stack>
1723          * <return value>
1724          * <lmf/caller saved registers>
1725          * <locals>
1726          * <spill area>
1727          * <localloc area>  -> grows dynamically
1728          * <params area>
1729          */
1730
1731         if (cfg->arch.omit_fp) {
1732                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1733                 cfg->frame_reg = AMD64_RSP;
1734                 offset = 0;
1735         } else {
1736                 /* Locals are allocated backwards from %fp */
1737                 cfg->frame_reg = AMD64_RBP;
1738                 offset = 0;
1739         }
1740
1741         cfg->arch.saved_iregs = cfg->used_int_regs;
1742         if (cfg->method->save_lmf)
1743                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1744                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1745
1746         if (cfg->arch.omit_fp)
1747                 cfg->arch.reg_save_area_offset = offset;
1748         /* Reserve space for callee saved registers */
1749         for (i = 0; i < AMD64_NREG; ++i)
1750                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1751                         offset += sizeof(mgreg_t);
1752                 }
1753         if (!cfg->arch.omit_fp)
1754                 cfg->arch.reg_save_area_offset = -offset;
1755
1756         if (sig_ret->type != MONO_TYPE_VOID) {
1757                 switch (cinfo->ret.storage) {
1758                 case ArgInIReg:
1759                 case ArgInFloatSSEReg:
1760                 case ArgInDoubleSSEReg:
1761                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1762                                 /* The register is volatile */
1763                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1764                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1765                                 if (cfg->arch.omit_fp) {
1766                                         cfg->vret_addr->inst_offset = offset;
1767                                         offset += 8;
1768                                 } else {
1769                                         offset += 8;
1770                                         cfg->vret_addr->inst_offset = -offset;
1771                                 }
1772                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1773                                         printf ("vret_addr =");
1774                                         mono_print_ins (cfg->vret_addr);
1775                                 }
1776                         }
1777                         else {
1778                                 cfg->ret->opcode = OP_REGVAR;
1779                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1780                         }
1781                         break;
1782                 case ArgValuetypeInReg:
1783                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1784                         cfg->ret->opcode = OP_REGOFFSET;
1785                         cfg->ret->inst_basereg = cfg->frame_reg;
1786                         if (cfg->arch.omit_fp) {
1787                                 cfg->ret->inst_offset = offset;
1788                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1789                         } else {
1790                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1791                                 cfg->ret->inst_offset = - offset;
1792                         }
1793                         break;
1794                 default:
1795                         g_assert_not_reached ();
1796                 }
1797                 cfg->ret->dreg = cfg->ret->inst_c0;
1798         }
1799
1800         /* Allocate locals */
1801         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1802         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1803                 char *mname = mono_method_full_name (cfg->method, TRUE);
1804                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1805                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1806                 g_free (mname);
1807                 return;
1808         }
1809
1810         if (locals_stack_align) {
1811                 offset += (locals_stack_align - 1);
1812                 offset &= ~(locals_stack_align - 1);
1813         }
1814         if (cfg->arch.omit_fp) {
1815                 cfg->locals_min_stack_offset = offset;
1816                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1817         } else {
1818                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1819                 cfg->locals_max_stack_offset = - offset;
1820         }
1821
1822         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1823                 if (offsets [i] != -1) {
1824                         MonoInst *ins = cfg->varinfo [i];
1825                         ins->opcode = OP_REGOFFSET;
1826                         ins->inst_basereg = cfg->frame_reg;
1827                         if (cfg->arch.omit_fp)
1828                                 ins->inst_offset = (offset + offsets [i]);
1829                         else
1830                                 ins->inst_offset = - (offset + offsets [i]);
1831                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1832                 }
1833         }
1834         offset += locals_stack_size;
1835
1836         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1837                 g_assert (!cfg->arch.omit_fp);
1838                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1839                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1840         }
1841
1842         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1843                 ins = cfg->args [i];
1844                 if (ins->opcode != OP_REGVAR) {
1845                         ArgInfo *ainfo = &cinfo->args [i];
1846                         gboolean inreg = TRUE;
1847
1848                         /* FIXME: Allocate volatile arguments to registers */
1849                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1850                                 inreg = FALSE;
1851
1852                         /*
1853                          * Under AMD64, all registers used to pass arguments to functions
1854                          * are volatile across calls.
1855                          * FIXME: Optimize this.
1856                          */
1857                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1858                                 inreg = FALSE;
1859
1860                         ins->opcode = OP_REGOFFSET;
1861
1862                         switch (ainfo->storage) {
1863                         case ArgInIReg:
1864                         case ArgInFloatSSEReg:
1865                         case ArgInDoubleSSEReg:
1866                                 if (inreg) {
1867                                         ins->opcode = OP_REGVAR;
1868                                         ins->dreg = ainfo->reg;
1869                                 }
1870                                 break;
1871                         case ArgOnStack:
1872                                 g_assert (!cfg->arch.omit_fp);
1873                                 ins->opcode = OP_REGOFFSET;
1874                                 ins->inst_basereg = cfg->frame_reg;
1875                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1876                                 break;
1877                         case ArgValuetypeInReg:
1878                                 break;
1879                         case ArgValuetypeAddrInIReg: {
1880                                 MonoInst *indir;
1881                                 g_assert (!cfg->arch.omit_fp);
1882
1883                                 MONO_INST_NEW (cfg, indir, 0);
1884                                 indir->opcode = OP_REGOFFSET;
1885                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1886                                         indir->inst_basereg = cfg->frame_reg;
1887                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1888                                         offset += (sizeof (gpointer));
1889                                         indir->inst_offset = - offset;
1890                                 }
1891                                 else {
1892                                         indir->inst_basereg = cfg->frame_reg;
1893                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1894                                 }
1895
1896                                 ins->opcode = OP_VTARG_ADDR;
1897                                 ins->inst_left = indir;
1898
1899                                 break;
1900                         }
1901                         default:
1902                                 NOT_IMPLEMENTED;
1903                         }
1904
1905                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1906                                 ins->opcode = OP_REGOFFSET;
1907                                 ins->inst_basereg = cfg->frame_reg;
1908                                 /* These arguments are saved to the stack in the prolog */
1909                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1910                                 if (cfg->arch.omit_fp) {
1911                                         ins->inst_offset = offset;
1912                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1913                                         // Arguments are yet supported by the stack map creation code
1914                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1915                                 } else {
1916                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1917                                         ins->inst_offset = - offset;
1918                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1919                                 }
1920                         }
1921                 }
1922         }
1923
1924         cfg->stack_offset = offset;
1925 }
1926
1927 void
1928 mono_arch_create_vars (MonoCompile *cfg)
1929 {
1930         MonoMethodSignature *sig;
1931         CallInfo *cinfo;
1932         MonoType *sig_ret;
1933
1934         sig = mono_method_signature (cfg->method);
1935
1936         if (!cfg->arch.cinfo)
1937                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1938         cinfo = cfg->arch.cinfo;
1939
1940         if (cinfo->ret.storage == ArgValuetypeInReg)
1941                 cfg->ret_var_is_local = TRUE;
1942
1943         sig_ret = mini_get_underlying_type (sig->ret);
1944         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1945                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1946                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1947                         printf ("vret_addr = ");
1948                         mono_print_ins (cfg->vret_addr);
1949                 }
1950         }
1951
1952         if (cfg->gen_sdb_seq_points) {
1953                 MonoInst *ins;
1954
1955                 if (cfg->compile_aot) {
1956                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1957                         ins->flags |= MONO_INST_VOLATILE;
1958                         cfg->arch.seq_point_info_var = ins;
1959
1960                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1961                         ins->flags |= MONO_INST_VOLATILE;
1962                         cfg->arch.ss_tramp_var = ins;
1963                 }
1964
1965             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1966                 ins->flags |= MONO_INST_VOLATILE;
1967                 cfg->arch.ss_trigger_page_var = ins;
1968         }
1969
1970         if (cfg->method->save_lmf)
1971                 cfg->create_lmf_var = TRUE;
1972
1973         if (cfg->method->save_lmf) {
1974                 cfg->lmf_ir = TRUE;
1975 #if !defined(TARGET_WIN32)
1976                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1977                         cfg->lmf_ir_mono_lmf = TRUE;
1978 #endif
1979         }
1980 }
1981
1982 static void
1983 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1984 {
1985         MonoInst *ins;
1986
1987         switch (storage) {
1988         case ArgInIReg:
1989                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1990                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1991                 ins->sreg1 = tree->dreg;
1992                 MONO_ADD_INS (cfg->cbb, ins);
1993                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1994                 break;
1995         case ArgInFloatSSEReg:
1996                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1997                 ins->dreg = mono_alloc_freg (cfg);
1998                 ins->sreg1 = tree->dreg;
1999                 MONO_ADD_INS (cfg->cbb, ins);
2000
2001                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2002                 break;
2003         case ArgInDoubleSSEReg:
2004                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2005                 ins->dreg = mono_alloc_freg (cfg);
2006                 ins->sreg1 = tree->dreg;
2007                 MONO_ADD_INS (cfg->cbb, ins);
2008
2009                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2010
2011                 break;
2012         default:
2013                 g_assert_not_reached ();
2014         }
2015 }
2016
2017 static int
2018 arg_storage_to_load_membase (ArgStorage storage)
2019 {
2020         switch (storage) {
2021         case ArgInIReg:
2022 #if defined(__mono_ilp32__)
2023                 return OP_LOADI8_MEMBASE;
2024 #else
2025                 return OP_LOAD_MEMBASE;
2026 #endif
2027         case ArgInDoubleSSEReg:
2028                 return OP_LOADR8_MEMBASE;
2029         case ArgInFloatSSEReg:
2030                 return OP_LOADR4_MEMBASE;
2031         default:
2032                 g_assert_not_reached ();
2033         }
2034
2035         return -1;
2036 }
2037
2038 static void
2039 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2040 {
2041         MonoMethodSignature *tmp_sig;
2042         int sig_reg;
2043
2044         if (call->tail_call)
2045                 NOT_IMPLEMENTED;
2046
2047         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2048
2049         /*
2050          * mono_ArgIterator_Setup assumes the signature cookie is
2051          * passed first and all the arguments which were before it are
2052          * passed on the stack after the signature. So compensate by
2053          * passing a different signature.
2054          */
2055         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2056         tmp_sig->param_count -= call->signature->sentinelpos;
2057         tmp_sig->sentinelpos = 0;
2058         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2059
2060         sig_reg = mono_alloc_ireg (cfg);
2061         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2062
2063         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2064 }
2065
2066 #ifdef ENABLE_LLVM
2067 static inline LLVMArgStorage
2068 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2069 {
2070         switch (storage) {
2071         case ArgInIReg:
2072                 return LLVMArgInIReg;
2073         case ArgNone:
2074                 return LLVMArgNone;
2075         default:
2076                 g_assert_not_reached ();
2077                 return LLVMArgNone;
2078         }
2079 }
2080
2081 LLVMCallInfo*
2082 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2083 {
2084         int i, n;
2085         CallInfo *cinfo;
2086         ArgInfo *ainfo;
2087         int j;
2088         LLVMCallInfo *linfo;
2089         MonoType *t, *sig_ret;
2090
2091         n = sig->param_count + sig->hasthis;
2092         sig_ret = mini_get_underlying_type (sig->ret);
2093
2094         cinfo = get_call_info (cfg->mempool, sig);
2095
2096         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2097
2098         /*
2099          * LLVM always uses the native ABI while we use our own ABI, the
2100          * only difference is the handling of vtypes:
2101          * - we only pass/receive them in registers in some cases, and only
2102          *   in 1 or 2 integer registers.
2103          */
2104         if (cinfo->ret.storage == ArgValuetypeInReg) {
2105                 if (sig->pinvoke) {
2106                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2107                         cfg->disable_llvm = TRUE;
2108                         return linfo;
2109                 }
2110
2111                 linfo->ret.storage = LLVMArgVtypeInReg;
2112                 for (j = 0; j < 2; ++j)
2113                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2114         }
2115
2116         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2117                 /* Vtype returned using a hidden argument */
2118                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2119                 linfo->vret_arg_index = cinfo->vret_arg_index;
2120         }
2121
2122         for (i = 0; i < n; ++i) {
2123                 ainfo = cinfo->args + i;
2124
2125                 if (i >= sig->hasthis)
2126                         t = sig->params [i - sig->hasthis];
2127                 else
2128                         t = &mono_defaults.int_class->byval_arg;
2129
2130                 linfo->args [i].storage = LLVMArgNone;
2131
2132                 switch (ainfo->storage) {
2133                 case ArgInIReg:
2134                         linfo->args [i].storage = LLVMArgInIReg;
2135                         break;
2136                 case ArgInDoubleSSEReg:
2137                 case ArgInFloatSSEReg:
2138                         linfo->args [i].storage = LLVMArgInFPReg;
2139                         break;
2140                 case ArgOnStack:
2141                         if (MONO_TYPE_ISSTRUCT (t)) {
2142                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2143                         } else {
2144                                 linfo->args [i].storage = LLVMArgInIReg;
2145                                 if (!t->byref) {
2146                                         if (t->type == MONO_TYPE_R4)
2147                                                 linfo->args [i].storage = LLVMArgInFPReg;
2148                                         else if (t->type == MONO_TYPE_R8)
2149                                                 linfo->args [i].storage = LLVMArgInFPReg;
2150                                 }
2151                         }
2152                         break;
2153                 case ArgValuetypeInReg:
2154                         if (sig->pinvoke) {
2155                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2156                                 cfg->disable_llvm = TRUE;
2157                                 return linfo;
2158                         }
2159
2160                         linfo->args [i].storage = LLVMArgVtypeInReg;
2161                         for (j = 0; j < 2; ++j)
2162                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2163                         break;
2164                 default:
2165                         cfg->exception_message = g_strdup ("ainfo->storage");
2166                         cfg->disable_llvm = TRUE;
2167                         break;
2168                 }
2169         }
2170
2171         return linfo;
2172 }
2173 #endif
2174
2175 void
2176 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2177 {
2178         MonoInst *arg, *in;
2179         MonoMethodSignature *sig;
2180         MonoType *sig_ret;
2181         int i, n;
2182         CallInfo *cinfo;
2183         ArgInfo *ainfo;
2184
2185         sig = call->signature;
2186         n = sig->param_count + sig->hasthis;
2187
2188         cinfo = get_call_info (cfg->mempool, sig);
2189
2190         sig_ret = sig->ret;
2191
2192         if (COMPILE_LLVM (cfg)) {
2193                 /* We shouldn't be called in the llvm case */
2194                 cfg->disable_llvm = TRUE;
2195                 return;
2196         }
2197
2198         /*
2199          * Emit all arguments which are passed on the stack to prevent register
2200          * allocation problems.
2201          */
2202         for (i = 0; i < n; ++i) {
2203                 MonoType *t;
2204                 ainfo = cinfo->args + i;
2205
2206                 in = call->args [i];
2207
2208                 if (sig->hasthis && i == 0)
2209                         t = &mono_defaults.object_class->byval_arg;
2210                 else
2211                         t = sig->params [i - sig->hasthis];
2212
2213                 t = mini_get_underlying_type (t);
2214                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2215                         if (!t->byref) {
2216                                 if (t->type == MONO_TYPE_R4)
2217                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2218                                 else if (t->type == MONO_TYPE_R8)
2219                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2220                                 else
2221                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2222                         } else {
2223                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2224                         }
2225                         if (cfg->compute_gc_maps) {
2226                                 MonoInst *def;
2227
2228                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2229                         }
2230                 }
2231         }
2232
2233         /*
2234          * Emit all parameters passed in registers in non-reverse order for better readability
2235          * and to help the optimization in emit_prolog ().
2236          */
2237         for (i = 0; i < n; ++i) {
2238                 ainfo = cinfo->args + i;
2239
2240                 in = call->args [i];
2241
2242                 if (ainfo->storage == ArgInIReg)
2243                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2244         }
2245
2246         for (i = n - 1; i >= 0; --i) {
2247                 MonoType *t;
2248
2249                 ainfo = cinfo->args + i;
2250
2251                 in = call->args [i];
2252
2253                 if (sig->hasthis && i == 0)
2254                         t = &mono_defaults.object_class->byval_arg;
2255                 else
2256                         t = sig->params [i - sig->hasthis];
2257                 t = mini_get_underlying_type (t);
2258
2259                 switch (ainfo->storage) {
2260                 case ArgInIReg:
2261                         /* Already done */
2262                         break;
2263                 case ArgInFloatSSEReg:
2264                 case ArgInDoubleSSEReg:
2265                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2266                         break;
2267                 case ArgOnStack:
2268                 case ArgValuetypeInReg:
2269                 case ArgValuetypeAddrInIReg:
2270                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2271                                 MonoInst *call_inst = (MonoInst*)call;
2272                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2273                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2274                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
2275                                 guint32 align;
2276                                 guint32 size;
2277
2278                                 if (t->type == MONO_TYPE_TYPEDBYREF) {
2279                                         size = sizeof (MonoTypedRef);
2280                                         align = sizeof (gpointer);
2281                                 }
2282                                 else {
2283                                         if (sig->pinvoke)
2284                                                 size = mono_type_native_stack_size (t, &align);
2285                                         else {
2286                                                 /*
2287                                                  * Other backends use mono_type_stack_size (), but that
2288                                                  * aligns the size to 8, which is larger than the size of
2289                                                  * the source, leading to reads of invalid memory if the
2290                                                  * source is at the end of address space.
2291                                                  */
2292                                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2293                                         }
2294                                 }
2295                                 g_assert (in->klass);
2296
2297                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2298                                         /* Avoid asserts in emit_memcpy () */
2299                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2300                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2301                                         /* Continue normally */
2302                                 }
2303
2304                                 if (size > 0) {
2305                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2306                                         arg->sreg1 = in->dreg;
2307                                         arg->klass = mono_class_from_mono_type (t);
2308                                         arg->backend.size = size;
2309                                         arg->inst_p0 = call;
2310                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2311                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2312
2313                                         MONO_ADD_INS (cfg->cbb, arg);
2314                                 }
2315                         }
2316                         break;
2317                 default:
2318                         g_assert_not_reached ();
2319                 }
2320
2321                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2322                         /* Emit the signature cookie just before the implicit arguments */
2323                         emit_sig_cookie (cfg, call, cinfo);
2324         }
2325
2326         /* Handle the case where there are no implicit arguments */
2327         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2328                 emit_sig_cookie (cfg, call, cinfo);
2329
2330         sig_ret = mini_get_underlying_type (sig->ret);
2331         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2332                 MonoInst *vtarg;
2333
2334                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2335                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2336                                 /*
2337                                  * Tell the JIT to use a more efficient calling convention: call using
2338                                  * OP_CALL, compute the result location after the call, and save the
2339                                  * result there.
2340                                  */
2341                                 call->vret_in_reg = TRUE;
2342                                 /*
2343                                  * Nullify the instruction computing the vret addr to enable
2344                                  * future optimizations.
2345                                  */
2346                                 if (call->vret_var)
2347                                         NULLIFY_INS (call->vret_var);
2348                         } else {
2349                                 if (call->tail_call)
2350                                         NOT_IMPLEMENTED;
2351                                 /*
2352                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2353                                  * the stack. Push the address here, so the call instruction can
2354                                  * access it.
2355                                  */
2356                                 if (!cfg->arch.vret_addr_loc) {
2357                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2358                                         /* Prevent it from being register allocated or optimized away */
2359                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2360                                 }
2361
2362                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2363                         }
2364                 }
2365                 else {
2366                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2367                         vtarg->sreg1 = call->vret_var->dreg;
2368                         vtarg->dreg = mono_alloc_preg (cfg);
2369                         MONO_ADD_INS (cfg->cbb, vtarg);
2370
2371                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2372                 }
2373         }
2374
2375         if (cfg->method->save_lmf) {
2376                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2377                 MONO_ADD_INS (cfg->cbb, arg);
2378         }
2379
2380         call->stack_usage = cinfo->stack_usage;
2381 }
2382
2383 void
2384 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2385 {
2386         MonoInst *arg;
2387         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2388         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2389         int size = ins->backend.size;
2390
2391         if (ainfo->storage == ArgValuetypeInReg) {
2392                 MonoInst *load;
2393                 int part;
2394
2395                 for (part = 0; part < 2; ++part) {
2396                         if (ainfo->pair_storage [part] == ArgNone)
2397                                 continue;
2398
2399                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2400                         load->inst_basereg = src->dreg;
2401                         load->inst_offset = part * sizeof(mgreg_t);
2402
2403                         switch (ainfo->pair_storage [part]) {
2404                         case ArgInIReg:
2405                                 load->dreg = mono_alloc_ireg (cfg);
2406                                 break;
2407                         case ArgInDoubleSSEReg:
2408                         case ArgInFloatSSEReg:
2409                                 load->dreg = mono_alloc_freg (cfg);
2410                                 break;
2411                         default:
2412                                 g_assert_not_reached ();
2413                         }
2414                         MONO_ADD_INS (cfg->cbb, load);
2415
2416                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2417                 }
2418         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2419                 MonoInst *vtaddr, *load;
2420                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2421
2422                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2423                 cfg->has_indirection = TRUE;
2424                 load->inst_p0 = vtaddr;
2425                 vtaddr->flags |= MONO_INST_INDIRECT;
2426                 load->type = STACK_MP;
2427                 load->klass = vtaddr->klass;
2428                 load->dreg = mono_alloc_ireg (cfg);
2429                 MONO_ADD_INS (cfg->cbb, load);
2430                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2431
2432                 if (ainfo->pair_storage [0] == ArgInIReg) {
2433                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2434                         arg->dreg = mono_alloc_ireg (cfg);
2435                         arg->sreg1 = load->dreg;
2436                         arg->inst_imm = 0;
2437                         MONO_ADD_INS (cfg->cbb, arg);
2438                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2439                 } else {
2440                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2441                 }
2442         } else {
2443                 if (size == 8) {
2444                         int dreg = mono_alloc_ireg (cfg);
2445
2446                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2447                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2448                 } else if (size <= 40) {
2449                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2450                 } else {
2451                         // FIXME: Code growth
2452                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2453                 }
2454
2455                 if (cfg->compute_gc_maps) {
2456                         MonoInst *def;
2457                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2458                 }
2459         }
2460 }
2461
2462 void
2463 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2464 {
2465         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2466
2467         if (ret->type == MONO_TYPE_R4) {
2468                 if (COMPILE_LLVM (cfg))
2469                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2470                 else
2471                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2472                 return;
2473         } else if (ret->type == MONO_TYPE_R8) {
2474                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2475                 return;
2476         }
2477
2478         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2479 }
2480
2481 #endif /* DISABLE_JIT */
2482
2483 #define EMIT_COND_BRANCH(ins,cond,sign) \
2484         if (ins->inst_true_bb->native_offset) { \
2485                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2486         } else { \
2487                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2488                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2489             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2490                         x86_branch8 (code, cond, 0, sign); \
2491                 else \
2492                         x86_branch32 (code, cond, 0, sign); \
2493 }
2494
2495 typedef struct {
2496         MonoMethodSignature *sig;
2497         CallInfo *cinfo;
2498 } ArchDynCallInfo;
2499
2500 static gboolean
2501 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2502 {
2503         int i;
2504
2505 #ifdef HOST_WIN32
2506         return FALSE;
2507 #endif
2508
2509         switch (cinfo->ret.storage) {
2510         case ArgNone:
2511         case ArgInIReg:
2512                 break;
2513         case ArgValuetypeInReg: {
2514                 ArgInfo *ainfo = &cinfo->ret;
2515
2516                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2517                         return FALSE;
2518                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2519                         return FALSE;
2520                 break;
2521         }
2522         default:
2523                 return FALSE;
2524         }
2525
2526         for (i = 0; i < cinfo->nargs; ++i) {
2527                 ArgInfo *ainfo = &cinfo->args [i];
2528                 switch (ainfo->storage) {
2529                 case ArgInIReg:
2530                         break;
2531                 case ArgValuetypeInReg:
2532                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2533                                 return FALSE;
2534                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2535                                 return FALSE;
2536                         break;
2537                 default:
2538                         return FALSE;
2539                 }
2540         }
2541
2542         return TRUE;
2543 }
2544
2545 /*
2546  * mono_arch_dyn_call_prepare:
2547  *
2548  *   Return a pointer to an arch-specific structure which contains information
2549  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2550  * supported for SIG.
2551  * This function is equivalent to ffi_prep_cif in libffi.
2552  */
2553 MonoDynCallInfo*
2554 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2555 {
2556         ArchDynCallInfo *info;
2557         CallInfo *cinfo;
2558
2559         cinfo = get_call_info (NULL, sig);
2560
2561         if (!dyn_call_supported (sig, cinfo)) {
2562                 g_free (cinfo);
2563                 return NULL;
2564         }
2565
2566         info = g_new0 (ArchDynCallInfo, 1);
2567         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2568         info->sig = sig;
2569         info->cinfo = cinfo;
2570
2571         return (MonoDynCallInfo*)info;
2572 }
2573
2574 /*
2575  * mono_arch_dyn_call_free:
2576  *
2577  *   Free a MonoDynCallInfo structure.
2578  */
2579 void
2580 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2581 {
2582         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2583
2584         g_free (ainfo->cinfo);
2585         g_free (ainfo);
2586 }
2587
2588 #if !defined(__native_client__)
2589 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2590 #define GREG_TO_PTR(greg) (gpointer)(greg)
2591 #else
2592 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2593 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2594 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2595 #endif
2596
2597 /*
2598  * mono_arch_get_start_dyn_call:
2599  *
2600  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2601  * store the result into BUF.
2602  * ARGS should be an array of pointers pointing to the arguments.
2603  * RET should point to a memory buffer large enought to hold the result of the
2604  * call.
2605  * This function should be as fast as possible, any work which does not depend
2606  * on the actual values of the arguments should be done in
2607  * mono_arch_dyn_call_prepare ().
2608  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2609  * libffi.
2610  */
2611 void
2612 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2613 {
2614         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2615         DynCallArgs *p = (DynCallArgs*)buf;
2616         int arg_index, greg, i, pindex;
2617         MonoMethodSignature *sig = dinfo->sig;
2618
2619         g_assert (buf_len >= sizeof (DynCallArgs));
2620
2621         p->res = 0;
2622         p->ret = ret;
2623
2624         arg_index = 0;
2625         greg = 0;
2626         pindex = 0;
2627
2628         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2629                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2630                 if (!sig->hasthis)
2631                         pindex = 1;
2632         }
2633
2634         if (dinfo->cinfo->vtype_retaddr)
2635                 p->regs [greg ++] = PTR_TO_GREG(ret);
2636
2637         for (i = pindex; i < sig->param_count; i++) {
2638                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2639                 gpointer *arg = args [arg_index ++];
2640
2641                 if (t->byref) {
2642                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2643                         continue;
2644                 }
2645
2646                 switch (t->type) {
2647                 case MONO_TYPE_STRING:
2648                 case MONO_TYPE_CLASS:
2649                 case MONO_TYPE_ARRAY:
2650                 case MONO_TYPE_SZARRAY:
2651                 case MONO_TYPE_OBJECT:
2652                 case MONO_TYPE_PTR:
2653                 case MONO_TYPE_I:
2654                 case MONO_TYPE_U:
2655 #if !defined(__mono_ilp32__)
2656                 case MONO_TYPE_I8:
2657                 case MONO_TYPE_U8:
2658 #endif
2659                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2660                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2661                         break;
2662 #if defined(__mono_ilp32__)
2663                 case MONO_TYPE_I8:
2664                 case MONO_TYPE_U8:
2665                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2666                         p->regs [greg ++] = *(guint64*)(arg);
2667                         break;
2668 #endif
2669                 case MONO_TYPE_U1:
2670                         p->regs [greg ++] = *(guint8*)(arg);
2671                         break;
2672                 case MONO_TYPE_I1:
2673                         p->regs [greg ++] = *(gint8*)(arg);
2674                         break;
2675                 case MONO_TYPE_I2:
2676                         p->regs [greg ++] = *(gint16*)(arg);
2677                         break;
2678                 case MONO_TYPE_U2:
2679                         p->regs [greg ++] = *(guint16*)(arg);
2680                         break;
2681                 case MONO_TYPE_I4:
2682                         p->regs [greg ++] = *(gint32*)(arg);
2683                         break;
2684                 case MONO_TYPE_U4:
2685                         p->regs [greg ++] = *(guint32*)(arg);
2686                         break;
2687                 case MONO_TYPE_GENERICINST:
2688                     if (MONO_TYPE_IS_REFERENCE (t)) {
2689                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2690                                 break;
2691                         } else {
2692                                 /* Fall through */
2693                         }
2694                 case MONO_TYPE_VALUETYPE: {
2695                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2696
2697                         g_assert (ainfo->storage == ArgValuetypeInReg);
2698                         if (ainfo->pair_storage [0] != ArgNone) {
2699                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2700                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2701                         }
2702                         if (ainfo->pair_storage [1] != ArgNone) {
2703                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2704                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2705                         }
2706                         break;
2707                 }
2708                 default:
2709                         g_assert_not_reached ();
2710                 }
2711         }
2712
2713         g_assert (greg <= PARAM_REGS);
2714 }
2715
2716 /*
2717  * mono_arch_finish_dyn_call:
2718  *
2719  *   Store the result of a dyn call into the return value buffer passed to
2720  * start_dyn_call ().
2721  * This function should be as fast as possible, any work which does not depend
2722  * on the actual values of the arguments should be done in
2723  * mono_arch_dyn_call_prepare ().
2724  */
2725 void
2726 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2727 {
2728         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2729         MonoMethodSignature *sig = dinfo->sig;
2730         guint8 *ret = ((DynCallArgs*)buf)->ret;
2731         mgreg_t res = ((DynCallArgs*)buf)->res;
2732         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2733
2734         switch (sig_ret->type) {
2735         case MONO_TYPE_VOID:
2736                 *(gpointer*)ret = NULL;
2737                 break;
2738         case MONO_TYPE_STRING:
2739         case MONO_TYPE_CLASS:
2740         case MONO_TYPE_ARRAY:
2741         case MONO_TYPE_SZARRAY:
2742         case MONO_TYPE_OBJECT:
2743         case MONO_TYPE_I:
2744         case MONO_TYPE_U:
2745         case MONO_TYPE_PTR:
2746                 *(gpointer*)ret = GREG_TO_PTR(res);
2747                 break;
2748         case MONO_TYPE_I1:
2749                 *(gint8*)ret = res;
2750                 break;
2751         case MONO_TYPE_U1:
2752                 *(guint8*)ret = res;
2753                 break;
2754         case MONO_TYPE_I2:
2755                 *(gint16*)ret = res;
2756                 break;
2757         case MONO_TYPE_U2:
2758                 *(guint16*)ret = res;
2759                 break;
2760         case MONO_TYPE_I4:
2761                 *(gint32*)ret = res;
2762                 break;
2763         case MONO_TYPE_U4:
2764                 *(guint32*)ret = res;
2765                 break;
2766         case MONO_TYPE_I8:
2767                 *(gint64*)ret = res;
2768                 break;
2769         case MONO_TYPE_U8:
2770                 *(guint64*)ret = res;
2771                 break;
2772         case MONO_TYPE_GENERICINST:
2773                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2774                         *(gpointer*)ret = GREG_TO_PTR(res);
2775                         break;
2776                 } else {
2777                         /* Fall through */
2778                 }
2779         case MONO_TYPE_VALUETYPE:
2780                 if (dinfo->cinfo->vtype_retaddr) {
2781                         /* Nothing to do */
2782                 } else {
2783                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2784
2785                         g_assert (ainfo->storage == ArgValuetypeInReg);
2786
2787                         if (ainfo->pair_storage [0] != ArgNone) {
2788                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2789                                 ((mgreg_t*)ret)[0] = res;
2790                         }
2791
2792                         g_assert (ainfo->pair_storage [1] == ArgNone);
2793                 }
2794                 break;
2795         default:
2796                 g_assert_not_reached ();
2797         }
2798 }
2799
2800 /* emit an exception if condition is fail */
2801 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2802         do {                                                        \
2803                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2804                 if (tins == NULL) {                                                                             \
2805                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2806                                         MONO_PATCH_INFO_EXC, exc_name);  \
2807                         x86_branch32 (code, cond, 0, signed);               \
2808                 } else {        \
2809                         EMIT_COND_BRANCH (tins, cond, signed);  \
2810                 }                       \
2811         } while (0);
2812
2813 #define EMIT_FPCOMPARE(code) do { \
2814         amd64_fcompp (code); \
2815         amd64_fnstsw (code); \
2816 } while (0);
2817
2818 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2819     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2820         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2821         amd64_ ##op (code); \
2822         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2823         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2824 } while (0);
2825
2826 static guint8*
2827 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2828 {
2829         gboolean no_patch = FALSE;
2830
2831         /*
2832          * FIXME: Add support for thunks
2833          */
2834         {
2835                 gboolean near_call = FALSE;
2836
2837                 /*
2838                  * Indirect calls are expensive so try to make a near call if possible.
2839                  * The caller memory is allocated by the code manager so it is
2840                  * guaranteed to be at a 32 bit offset.
2841                  */
2842
2843                 if (patch_type != MONO_PATCH_INFO_ABS) {
2844                         /* The target is in memory allocated using the code manager */
2845                         near_call = TRUE;
2846
2847                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2848                                 if (((MonoMethod*)data)->klass->image->aot_module)
2849                                         /* The callee might be an AOT method */
2850                                         near_call = FALSE;
2851                                 if (((MonoMethod*)data)->dynamic)
2852                                         /* The target is in malloc-ed memory */
2853                                         near_call = FALSE;
2854                         }
2855
2856                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2857                                 /*
2858                                  * The call might go directly to a native function without
2859                                  * the wrapper.
2860                                  */
2861                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2862                                 if (mi) {
2863                                         gconstpointer target = mono_icall_get_wrapper (mi);
2864                                         if ((((guint64)target) >> 32) != 0)
2865                                                 near_call = FALSE;
2866                                 }
2867                         }
2868                 }
2869                 else {
2870                         MonoJumpInfo *jinfo = NULL;
2871
2872                         if (cfg->abs_patches)
2873                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2874                         if (jinfo) {
2875                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2876                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2877                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2878                                                 near_call = TRUE;
2879                                         no_patch = TRUE;
2880                                 } else {
2881                                         /*
2882                                          * This is not really an optimization, but required because the
2883                                          * generic class init trampolines use R11 to pass the vtable.
2884                                          */
2885                                         near_call = TRUE;
2886                                 }
2887                         } else {
2888                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2889                                 if (info) {
2890                                         if (info->func == info->wrapper) {
2891                                                 /* No wrapper */
2892                                                 if ((((guint64)info->func) >> 32) == 0)
2893                                                         near_call = TRUE;
2894                                         }
2895                                         else {
2896                                                 /* See the comment in mono_codegen () */
2897                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2898                                                         near_call = TRUE;
2899                                         }
2900                                 }
2901                                 else if ((((guint64)data) >> 32) == 0) {
2902                                         near_call = TRUE;
2903                                         no_patch = TRUE;
2904                                 }
2905                         }
2906                 }
2907
2908                 if (cfg->method->dynamic)
2909                         /* These methods are allocated using malloc */
2910                         near_call = FALSE;
2911
2912 #ifdef MONO_ARCH_NOMAP32BIT
2913                 near_call = FALSE;
2914 #endif
2915 #if defined(__native_client__)
2916                 /* Always use near_call == TRUE for Native Client */
2917                 near_call = TRUE;
2918 #endif
2919                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2920                 if (optimize_for_xen)
2921                         near_call = FALSE;
2922
2923                 if (cfg->compile_aot) {
2924                         near_call = TRUE;
2925                         no_patch = TRUE;
2926                 }
2927
2928                 if (near_call) {
2929                         /*
2930                          * Align the call displacement to an address divisible by 4 so it does
2931                          * not span cache lines. This is required for code patching to work on SMP
2932                          * systems.
2933                          */
2934                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2935                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2936                                 amd64_padding (code, pad_size);
2937                         }
2938                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2939                         amd64_call_code (code, 0);
2940                 }
2941                 else {
2942                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2943                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2944                         amd64_call_reg (code, GP_SCRATCH_REG);
2945                 }
2946         }
2947
2948         return code;
2949 }
2950
2951 static inline guint8*
2952 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2953 {
2954 #ifdef TARGET_WIN32
2955         if (win64_adjust_stack)
2956                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2957 #endif
2958         code = emit_call_body (cfg, code, patch_type, data);
2959 #ifdef TARGET_WIN32
2960         if (win64_adjust_stack)
2961                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2962 #endif
2963
2964         return code;
2965 }
2966
2967 static inline int
2968 store_membase_imm_to_store_membase_reg (int opcode)
2969 {
2970         switch (opcode) {
2971         case OP_STORE_MEMBASE_IMM:
2972                 return OP_STORE_MEMBASE_REG;
2973         case OP_STOREI4_MEMBASE_IMM:
2974                 return OP_STOREI4_MEMBASE_REG;
2975         case OP_STOREI8_MEMBASE_IMM:
2976                 return OP_STOREI8_MEMBASE_REG;
2977         }
2978
2979         return -1;
2980 }
2981
2982 #ifndef DISABLE_JIT
2983
2984 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2985
2986 /*
2987  * mono_arch_peephole_pass_1:
2988  *
2989  *   Perform peephole opts which should/can be performed before local regalloc
2990  */
2991 void
2992 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2993 {
2994         MonoInst *ins, *n;
2995
2996         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2997                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2998
2999                 switch (ins->opcode) {
3000                 case OP_ADD_IMM:
3001                 case OP_IADD_IMM:
3002                 case OP_LADD_IMM:
3003                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3004                                 /*
3005                                  * X86_LEA is like ADD, but doesn't have the
3006                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3007                                  * its operand to 64 bit.
3008                                  */
3009                                 ins->opcode = OP_X86_LEA_MEMBASE;
3010                                 ins->inst_basereg = ins->sreg1;
3011                         }
3012                         break;
3013                 case OP_LXOR:
3014                 case OP_IXOR:
3015                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3016                                 MonoInst *ins2;
3017
3018                                 /*
3019                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3020                                  * the latter has length 2-3 instead of 6 (reverse constant
3021                                  * propagation). These instruction sequences are very common
3022                                  * in the initlocals bblock.
3023                                  */
3024                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3025                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3026                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3027                                                 ins2->sreg1 = ins->dreg;
3028                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3029                                                 /* Continue */
3030                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3031                                                 NULLIFY_INS (ins2);
3032                                                 /* Continue */
3033                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3034                                                 /* Continue */
3035                                         } else {
3036                                                 break;
3037                                         }
3038                                 }
3039                         }
3040                         break;
3041                 case OP_COMPARE_IMM:
3042                 case OP_LCOMPARE_IMM:
3043                         /* OP_COMPARE_IMM (reg, 0)
3044                          * -->
3045                          * OP_AMD64_TEST_NULL (reg)
3046                          */
3047                         if (!ins->inst_imm)
3048                                 ins->opcode = OP_AMD64_TEST_NULL;
3049                         break;
3050                 case OP_ICOMPARE_IMM:
3051                         if (!ins->inst_imm)
3052                                 ins->opcode = OP_X86_TEST_NULL;
3053                         break;
3054                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3055                         /*
3056                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3057                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3058                          * -->
3059                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3060                          * OP_COMPARE_IMM reg, imm
3061                          *
3062                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3063                          */
3064                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3065                             ins->inst_basereg == last_ins->inst_destbasereg &&
3066                             ins->inst_offset == last_ins->inst_offset) {
3067                                         ins->opcode = OP_ICOMPARE_IMM;
3068                                         ins->sreg1 = last_ins->sreg1;
3069
3070                                         /* check if we can remove cmp reg,0 with test null */
3071                                         if (!ins->inst_imm)
3072                                                 ins->opcode = OP_X86_TEST_NULL;
3073                                 }
3074
3075                         break;
3076                 }
3077
3078                 mono_peephole_ins (bb, ins);
3079         }
3080 }
3081
3082 void
3083 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3084 {
3085         MonoInst *ins, *n;
3086
3087         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3088                 switch (ins->opcode) {
3089                 case OP_ICONST:
3090                 case OP_I8CONST: {
3091                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3092                         /* reg = 0 -> XOR (reg, reg) */
3093                         /* XOR sets cflags on x86, so we cant do it always */
3094                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3095                                 ins->opcode = OP_LXOR;
3096                                 ins->sreg1 = ins->dreg;
3097                                 ins->sreg2 = ins->dreg;
3098                                 /* Fall through */
3099                         } else {
3100                                 break;
3101                         }
3102                 }
3103                 case OP_LXOR:
3104                         /*
3105                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3106                          * 0 result into 64 bits.
3107                          */
3108                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3109                                 ins->opcode = OP_IXOR;
3110                         }
3111                         /* Fall through */
3112                 case OP_IXOR:
3113                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3114                                 MonoInst *ins2;
3115
3116                                 /*
3117                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3118                                  * the latter has length 2-3 instead of 6 (reverse constant
3119                                  * propagation). These instruction sequences are very common
3120                                  * in the initlocals bblock.
3121                                  */
3122                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3123                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3124                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3125                                                 ins2->sreg1 = ins->dreg;
3126                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3127                                                 /* Continue */
3128                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3129                                                 NULLIFY_INS (ins2);
3130                                                 /* Continue */
3131                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3132                                                 /* Continue */
3133                                         } else {
3134                                                 break;
3135                                         }
3136                                 }
3137                         }
3138                         break;
3139                 case OP_IADD_IMM:
3140                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3141                                 ins->opcode = OP_X86_INC_REG;
3142                         break;
3143                 case OP_ISUB_IMM:
3144                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3145                                 ins->opcode = OP_X86_DEC_REG;
3146                         break;
3147                 }
3148
3149                 mono_peephole_ins (bb, ins);
3150         }
3151 }
3152
3153 #define NEW_INS(cfg,ins,dest,op) do {   \
3154                 MONO_INST_NEW ((cfg), (dest), (op)); \
3155         (dest)->cil_code = (ins)->cil_code; \
3156         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3157         } while (0)
3158
3159 /*
3160  * mono_arch_lowering_pass:
3161  *
3162  *  Converts complex opcodes into simpler ones so that each IR instruction
3163  * corresponds to one machine instruction.
3164  */
3165 void
3166 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3167 {
3168         MonoInst *ins, *n, *temp;
3169
3170         /*
3171          * FIXME: Need to add more instructions, but the current machine
3172          * description can't model some parts of the composite instructions like
3173          * cdq.
3174          */
3175         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3176                 switch (ins->opcode) {
3177                 case OP_DIV_IMM:
3178                 case OP_REM_IMM:
3179                 case OP_IDIV_IMM:
3180                 case OP_IDIV_UN_IMM:
3181                 case OP_IREM_UN_IMM:
3182                 case OP_LREM_IMM:
3183                 case OP_IREM_IMM:
3184                         mono_decompose_op_imm (cfg, bb, ins);
3185                         break;
3186                 case OP_COMPARE_IMM:
3187                 case OP_LCOMPARE_IMM:
3188                         if (!amd64_is_imm32 (ins->inst_imm)) {
3189                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3190                                 temp->inst_c0 = ins->inst_imm;
3191                                 temp->dreg = mono_alloc_ireg (cfg);
3192                                 ins->opcode = OP_COMPARE;
3193                                 ins->sreg2 = temp->dreg;
3194                         }
3195                         break;
3196 #ifndef __mono_ilp32__
3197                 case OP_LOAD_MEMBASE:
3198 #endif
3199                 case OP_LOADI8_MEMBASE:
3200 #ifndef __native_client_codegen__
3201                 /*  Don't generate memindex opcodes (to simplify */
3202                 /*  read sandboxing) */
3203                         if (!amd64_is_imm32 (ins->inst_offset)) {
3204                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3205                                 temp->inst_c0 = ins->inst_offset;
3206                                 temp->dreg = mono_alloc_ireg (cfg);
3207                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3208                                 ins->inst_indexreg = temp->dreg;
3209                         }
3210 #endif
3211                         break;
3212 #ifndef __mono_ilp32__
3213                 case OP_STORE_MEMBASE_IMM:
3214 #endif
3215                 case OP_STOREI8_MEMBASE_IMM:
3216                         if (!amd64_is_imm32 (ins->inst_imm)) {
3217                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3218                                 temp->inst_c0 = ins->inst_imm;
3219                                 temp->dreg = mono_alloc_ireg (cfg);
3220                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3221                                 ins->sreg1 = temp->dreg;
3222                         }
3223                         break;
3224 #ifdef MONO_ARCH_SIMD_INTRINSICS
3225                 case OP_EXPAND_I1: {
3226                                 int temp_reg1 = mono_alloc_ireg (cfg);
3227                                 int temp_reg2 = mono_alloc_ireg (cfg);
3228                                 int original_reg = ins->sreg1;
3229
3230                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3231                                 temp->sreg1 = original_reg;
3232                                 temp->dreg = temp_reg1;
3233
3234                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3235                                 temp->sreg1 = temp_reg1;
3236                                 temp->dreg = temp_reg2;
3237                                 temp->inst_imm = 8;
3238
3239                                 NEW_INS (cfg, ins, temp, OP_LOR);
3240                                 temp->sreg1 = temp->dreg = temp_reg2;
3241                                 temp->sreg2 = temp_reg1;
3242
3243                                 ins->opcode = OP_EXPAND_I2;
3244                                 ins->sreg1 = temp_reg2;
3245                         }
3246                         break;
3247 #endif
3248                 default:
3249                         break;
3250                 }
3251         }
3252
3253         bb->max_vreg = cfg->next_vreg;
3254 }
3255
3256 static const int
3257 branch_cc_table [] = {
3258         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3259         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3260         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3261 };
3262
3263 /* Maps CMP_... constants to X86_CC_... constants */
3264 static const int
3265 cc_table [] = {
3266         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3267         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3268 };
3269
3270 static const int
3271 cc_signed_table [] = {
3272         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3273         FALSE, FALSE, FALSE, FALSE
3274 };
3275
3276 /*#include "cprop.c"*/
3277
3278 static unsigned char*
3279 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3280 {
3281         if (size == 8)
3282                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3283         else
3284                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3285
3286         if (size == 1)
3287                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3288         else if (size == 2)
3289                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3290         return code;
3291 }
3292
3293 static unsigned char*
3294 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3295 {
3296         int sreg = tree->sreg1;
3297         int need_touch = FALSE;
3298
3299 #if defined(TARGET_WIN32)
3300         need_touch = TRUE;
3301 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3302         if (!tree->flags & MONO_INST_INIT)
3303                 need_touch = TRUE;
3304 #endif
3305
3306         if (need_touch) {
3307                 guint8* br[5];
3308
3309                 /*
3310                  * Under Windows:
3311                  * If requested stack size is larger than one page,
3312                  * perform stack-touch operation
3313                  */
3314                 /*
3315                  * Generate stack probe code.
3316                  * Under Windows, it is necessary to allocate one page at a time,
3317                  * "touching" stack after each successful sub-allocation. This is
3318                  * because of the way stack growth is implemented - there is a
3319                  * guard page before the lowest stack page that is currently commited.
3320                  * Stack normally grows sequentially so OS traps access to the
3321                  * guard page and commits more pages when needed.
3322                  */
3323                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3324                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3325
3326                 br[2] = code; /* loop */
3327                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3328                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3329                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3330                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3331                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3332                 amd64_patch (br[3], br[2]);
3333                 amd64_test_reg_reg (code, sreg, sreg);
3334                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3335                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3336
3337                 br[1] = code; x86_jump8 (code, 0);
3338
3339                 amd64_patch (br[0], code);
3340                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3341                 amd64_patch (br[1], code);
3342                 amd64_patch (br[4], code);
3343         }
3344         else
3345                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3346
3347         if (tree->flags & MONO_INST_INIT) {
3348                 int offset = 0;
3349                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3350                         amd64_push_reg (code, AMD64_RAX);
3351                         offset += 8;
3352                 }
3353                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3354                         amd64_push_reg (code, AMD64_RCX);
3355                         offset += 8;
3356                 }
3357                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3358                         amd64_push_reg (code, AMD64_RDI);
3359                         offset += 8;
3360                 }
3361
3362                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3363                 if (sreg != AMD64_RCX)
3364                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3365                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3366
3367                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3368                 if (cfg->param_area)
3369                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3370                 amd64_cld (code);
3371 #if defined(__default_codegen__)
3372                 amd64_prefix (code, X86_REP_PREFIX);
3373                 amd64_stosl (code);
3374 #elif defined(__native_client_codegen__)
3375                 /* NaCl stos pseudo-instruction */
3376                 amd64_codegen_pre(code);
3377                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3378                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3379                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3380                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3381                 amd64_prefix (code, X86_REP_PREFIX);
3382                 amd64_stosl (code);
3383                 amd64_codegen_post(code);
3384 #endif /* __native_client_codegen__ */
3385
3386                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3387                         amd64_pop_reg (code, AMD64_RDI);
3388                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3389                         amd64_pop_reg (code, AMD64_RCX);
3390                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3391                         amd64_pop_reg (code, AMD64_RAX);
3392         }
3393         return code;
3394 }
3395
3396 static guint8*
3397 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3398 {
3399         CallInfo *cinfo;
3400         guint32 quad;
3401
3402         /* Move return value to the target register */
3403         /* FIXME: do this in the local reg allocator */
3404         switch (ins->opcode) {
3405         case OP_CALL:
3406         case OP_CALL_REG:
3407         case OP_CALL_MEMBASE:
3408         case OP_LCALL:
3409         case OP_LCALL_REG:
3410         case OP_LCALL_MEMBASE:
3411                 g_assert (ins->dreg == AMD64_RAX);
3412                 break;
3413         case OP_FCALL:
3414         case OP_FCALL_REG:
3415         case OP_FCALL_MEMBASE: {
3416                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3417                 if (rtype->type == MONO_TYPE_R4) {
3418                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3419                 }
3420                 else {
3421                         if (ins->dreg != AMD64_XMM0)
3422                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3423                 }
3424                 break;
3425         }
3426         case OP_RCALL:
3427         case OP_RCALL_REG:
3428         case OP_RCALL_MEMBASE:
3429                 if (ins->dreg != AMD64_XMM0)
3430                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3431                 break;
3432         case OP_VCALL:
3433         case OP_VCALL_REG:
3434         case OP_VCALL_MEMBASE:
3435         case OP_VCALL2:
3436         case OP_VCALL2_REG:
3437         case OP_VCALL2_MEMBASE:
3438                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3439                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3440                         MonoInst *loc = cfg->arch.vret_addr_loc;
3441
3442                         /* Load the destination address */
3443                         g_assert (loc->opcode == OP_REGOFFSET);
3444                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3445
3446                         for (quad = 0; quad < 2; quad ++) {
3447                                 switch (cinfo->ret.pair_storage [quad]) {
3448                                 case ArgInIReg:
3449                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3450                                         break;
3451                                 case ArgInFloatSSEReg:
3452                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3453                                         break;
3454                                 case ArgInDoubleSSEReg:
3455                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3456                                         break;
3457                                 case ArgNone:
3458                                         break;
3459                                 default:
3460                                         NOT_IMPLEMENTED;
3461                                 }
3462                         }
3463                 }
3464                 break;
3465         }
3466
3467         return code;
3468 }
3469
3470 #endif /* DISABLE_JIT */
3471
3472 #ifdef __APPLE__
3473 static int tls_gs_offset;
3474 #endif
3475
3476 gboolean
3477 mono_amd64_have_tls_get (void)
3478 {
3479 #ifdef TARGET_MACH
3480         static gboolean have_tls_get = FALSE;
3481         static gboolean inited = FALSE;
3482
3483         if (inited)
3484                 return have_tls_get;
3485
3486 #if MONO_HAVE_FAST_TLS
3487         guint8 *ins = (guint8*)pthread_getspecific;
3488
3489         /*
3490          * We're looking for these two instructions:
3491          *
3492          * mov    %gs:[offset](,%rdi,8),%rax
3493          * retq
3494          */
3495         have_tls_get = ins [0] == 0x65 &&
3496                        ins [1] == 0x48 &&
3497                        ins [2] == 0x8b &&
3498                        ins [3] == 0x04 &&
3499                        ins [4] == 0xfd &&
3500                        ins [6] == 0x00 &&
3501                        ins [7] == 0x00 &&
3502                        ins [8] == 0x00 &&
3503                        ins [9] == 0xc3;
3504
3505         tls_gs_offset = ins[5];
3506 #endif
3507
3508         inited = TRUE;
3509
3510         return have_tls_get;
3511 #elif defined(TARGET_ANDROID)
3512         return FALSE;
3513 #else
3514         return TRUE;
3515 #endif
3516 }
3517
3518 int
3519 mono_amd64_get_tls_gs_offset (void)
3520 {
3521 #ifdef TARGET_OSX
3522         return tls_gs_offset;
3523 #else
3524         g_assert_not_reached ();
3525         return -1;
3526 #endif
3527 }
3528
3529 /*
3530  * mono_amd64_emit_tls_get:
3531  * @code: buffer to store code to
3532  * @dreg: hard register where to place the result
3533  * @tls_offset: offset info
3534  *
3535  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3536  * the dreg register the item in the thread local storage identified
3537  * by tls_offset.
3538  *
3539  * Returns: a pointer to the end of the stored code
3540  */
3541 guint8*
3542 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3543 {
3544 #ifdef TARGET_WIN32
3545         if (tls_offset < 64) {
3546                 x86_prefix (code, X86_GS_PREFIX);
3547                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3548         } else {
3549                 guint8 *buf [16];
3550
3551                 g_assert (tls_offset < 0x440);
3552                 /* Load TEB->TlsExpansionSlots */
3553                 x86_prefix (code, X86_GS_PREFIX);
3554                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3555                 amd64_test_reg_reg (code, dreg, dreg);
3556                 buf [0] = code;
3557                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3558                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3559                 amd64_patch (buf [0], code);
3560         }
3561 #elif defined(__APPLE__)
3562         x86_prefix (code, X86_GS_PREFIX);
3563         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3564 #else
3565         if (optimize_for_xen) {
3566                 x86_prefix (code, X86_FS_PREFIX);
3567                 amd64_mov_reg_mem (code, dreg, 0, 8);
3568                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3569         } else {
3570                 x86_prefix (code, X86_FS_PREFIX);
3571                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3572         }
3573 #endif
3574         return code;
3575 }
3576
3577 static guint8*
3578 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3579 {
3580         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3581 #ifdef TARGET_OSX
3582         if (dreg != offset_reg)
3583                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3584         amd64_prefix (code, X86_GS_PREFIX);
3585         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3586 #elif defined(__linux__)
3587         int tmpreg = -1;
3588
3589         if (dreg == offset_reg) {
3590                 /* Use a temporary reg by saving it to the redzone */
3591                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3592                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3593                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3594                 offset_reg = tmpreg;
3595         }
3596         x86_prefix (code, X86_FS_PREFIX);
3597         amd64_mov_reg_mem (code, dreg, 0, 8);
3598         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3599         if (tmpreg != -1)
3600                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3601 #else
3602         g_assert_not_reached ();
3603 #endif
3604         return code;
3605 }
3606
3607 static guint8*
3608 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3609 {
3610 #ifdef TARGET_WIN32
3611         g_assert_not_reached ();
3612 #elif defined(__APPLE__)
3613         x86_prefix (code, X86_GS_PREFIX);
3614         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3615 #else
3616         g_assert (!optimize_for_xen);
3617         x86_prefix (code, X86_FS_PREFIX);
3618         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3619 #endif
3620         return code;
3621 }
3622
3623 static guint8*
3624 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3625 {
3626         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3627 #ifdef TARGET_WIN32
3628         g_assert_not_reached ();
3629 #elif defined(__APPLE__)
3630         x86_prefix (code, X86_GS_PREFIX);
3631         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3632 #else
3633         x86_prefix (code, X86_FS_PREFIX);
3634         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3635 #endif
3636         return code;
3637 }
3638
3639  /*
3640  * mono_arch_translate_tls_offset:
3641  *
3642  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3643  */
3644 int
3645 mono_arch_translate_tls_offset (int offset)
3646 {
3647 #ifdef __APPLE__
3648         return tls_gs_offset + (offset * 8);
3649 #else
3650         return offset;
3651 #endif
3652 }
3653
3654 /*
3655  * emit_setup_lmf:
3656  *
3657  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3658  */
3659 static guint8*
3660 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3661 {
3662         /*
3663          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3664          */
3665         /*
3666          * sp is saved right before calls but we need to save it here too so
3667          * async stack walks would work.
3668          */
3669         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3670         /* Save rbp */
3671         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3672         if (cfg->arch.omit_fp && cfa_offset != -1)
3673                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3674
3675         /* These can't contain refs */
3676         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3677         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3678         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3679         /* These are handled automatically by the stack marking code */
3680         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3681
3682         return code;
3683 }
3684
3685 #define REAL_PRINT_REG(text,reg) \
3686 mono_assert (reg >= 0); \
3687 amd64_push_reg (code, AMD64_RAX); \
3688 amd64_push_reg (code, AMD64_RDX); \
3689 amd64_push_reg (code, AMD64_RCX); \
3690 amd64_push_reg (code, reg); \
3691 amd64_push_imm (code, reg); \
3692 amd64_push_imm (code, text " %d %p\n"); \
3693 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3694 amd64_call_reg (code, AMD64_RAX); \
3695 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3696 amd64_pop_reg (code, AMD64_RCX); \
3697 amd64_pop_reg (code, AMD64_RDX); \
3698 amd64_pop_reg (code, AMD64_RAX);
3699
3700 /* benchmark and set based on cpu */
3701 #define LOOP_ALIGNMENT 8
3702 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3703
3704 #ifndef DISABLE_JIT
3705 void
3706 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3707 {
3708         MonoInst *ins;
3709         MonoCallInst *call;
3710         guint offset;
3711         guint8 *code = cfg->native_code + cfg->code_len;
3712         int max_len;
3713
3714         /* Fix max_offset estimate for each successor bb */
3715         if (cfg->opt & MONO_OPT_BRANCH) {
3716                 int current_offset = cfg->code_len;
3717                 MonoBasicBlock *current_bb;
3718                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3719                         current_bb->max_offset = current_offset;
3720                         current_offset += current_bb->max_length;
3721                 }
3722         }
3723
3724         if (cfg->opt & MONO_OPT_LOOP) {
3725                 int pad, align = LOOP_ALIGNMENT;
3726                 /* set alignment depending on cpu */
3727                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3728                         pad = align - pad;
3729                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3730                         amd64_padding (code, pad);
3731                         cfg->code_len += pad;
3732                         bb->native_offset = cfg->code_len;
3733                 }
3734         }
3735
3736 #if defined(__native_client_codegen__)
3737         /* For Native Client, all indirect call/jump targets must be */
3738         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3739         /* indirectly as well.                                       */
3740         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3741                                       (bb->flags & BB_EXCEPTION_HANDLER);
3742
3743         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3744                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3745                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3746                 cfg->code_len += pad;
3747                 bb->native_offset = cfg->code_len;
3748         }
3749 #endif  /*__native_client_codegen__*/
3750
3751         if (cfg->verbose_level > 2)
3752                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3753
3754         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3755                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3756                 g_assert (!cfg->compile_aot);
3757
3758                 cov->data [bb->dfn].cil_code = bb->cil_code;
3759                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3760                 /* this is not thread save, but good enough */
3761                 amd64_inc_membase (code, AMD64_R11, 0);
3762         }
3763
3764         offset = code - cfg->native_code;
3765
3766         mono_debug_open_block (cfg, bb, offset);
3767
3768     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3769                 x86_breakpoint (code);
3770
3771         MONO_BB_FOR_EACH_INS (bb, ins) {
3772                 offset = code - cfg->native_code;
3773
3774                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3775
3776 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3777
3778                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3779                         cfg->code_size *= 2;
3780                         cfg->native_code = mono_realloc_native_code(cfg);
3781                         code = cfg->native_code + offset;
3782                         cfg->stat_code_reallocs++;
3783                 }
3784
3785                 if (cfg->debug_info)
3786                         mono_debug_record_line_number (cfg, ins, offset);
3787
3788                 switch (ins->opcode) {
3789                 case OP_BIGMUL:
3790                         amd64_mul_reg (code, ins->sreg2, TRUE);
3791                         break;
3792                 case OP_BIGMUL_UN:
3793                         amd64_mul_reg (code, ins->sreg2, FALSE);
3794                         break;
3795                 case OP_X86_SETEQ_MEMBASE:
3796                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3797                         break;
3798                 case OP_STOREI1_MEMBASE_IMM:
3799                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3800                         break;
3801                 case OP_STOREI2_MEMBASE_IMM:
3802                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3803                         break;
3804                 case OP_STOREI4_MEMBASE_IMM:
3805                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3806                         break;
3807                 case OP_STOREI1_MEMBASE_REG:
3808                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3809                         break;
3810                 case OP_STOREI2_MEMBASE_REG:
3811                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3812                         break;
3813                 /* In AMD64 NaCl, pointers are 4 bytes, */
3814                 /*  so STORE_* != STOREI8_*. Likewise below. */
3815                 case OP_STORE_MEMBASE_REG:
3816                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3817                         break;
3818                 case OP_STOREI8_MEMBASE_REG:
3819                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3820                         break;
3821                 case OP_STOREI4_MEMBASE_REG:
3822                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3823                         break;
3824                 case OP_STORE_MEMBASE_IMM:
3825 #ifndef __native_client_codegen__
3826                         /* In NaCl, this could be a PCONST type, which could */
3827                         /* mean a pointer type was copied directly into the  */
3828                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3829                         /* the value would be 0x00000000FFFFFFFF which is    */
3830                         /* not proper for an imm32 unless you cast it.       */
3831                         g_assert (amd64_is_imm32 (ins->inst_imm));
3832 #endif
3833                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3834                         break;
3835                 case OP_STOREI8_MEMBASE_IMM:
3836                         g_assert (amd64_is_imm32 (ins->inst_imm));
3837                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3838                         break;
3839                 case OP_LOAD_MEM:
3840 #ifdef __mono_ilp32__
3841                         /* In ILP32, pointers are 4 bytes, so separate these */
3842                         /* cases, use literal 8 below where we really want 8 */
3843                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3844                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3845                         break;
3846 #endif
3847                 case OP_LOADI8_MEM:
3848                         // FIXME: Decompose this earlier
3849                         if (amd64_is_imm32 (ins->inst_imm))
3850                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3851                         else {
3852                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3853                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3854                         }
3855                         break;
3856                 case OP_LOADI4_MEM:
3857                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3858                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3859                         break;
3860                 case OP_LOADU4_MEM:
3861                         // FIXME: Decompose this earlier
3862                         if (amd64_is_imm32 (ins->inst_imm))
3863                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3864                         else {
3865                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3866                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3867                         }
3868                         break;
3869                 case OP_LOADU1_MEM:
3870                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3871                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3872                         break;
3873                 case OP_LOADU2_MEM:
3874                         /* For NaCl, pointers are 4 bytes, so separate these */
3875                         /* cases, use literal 8 below where we really want 8 */
3876                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3877                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3878                         break;
3879                 case OP_LOAD_MEMBASE:
3880                         g_assert (amd64_is_imm32 (ins->inst_offset));
3881                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3882                         break;
3883                 case OP_LOADI8_MEMBASE:
3884                         /* Use literal 8 instead of sizeof pointer or */
3885                         /* register, we really want 8 for this opcode */
3886                         g_assert (amd64_is_imm32 (ins->inst_offset));
3887                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3888                         break;
3889                 case OP_LOADI4_MEMBASE:
3890                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3891                         break;
3892                 case OP_LOADU4_MEMBASE:
3893                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3894                         break;
3895                 case OP_LOADU1_MEMBASE:
3896                         /* The cpu zero extends the result into 64 bits */
3897                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3898                         break;
3899                 case OP_LOADI1_MEMBASE:
3900                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3901                         break;
3902                 case OP_LOADU2_MEMBASE:
3903                         /* The cpu zero extends the result into 64 bits */
3904                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3905                         break;
3906                 case OP_LOADI2_MEMBASE:
3907                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3908                         break;
3909                 case OP_AMD64_LOADI8_MEMINDEX:
3910                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3911                         break;
3912                 case OP_LCONV_TO_I1:
3913                 case OP_ICONV_TO_I1:
3914                 case OP_SEXT_I1:
3915                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3916                         break;
3917                 case OP_LCONV_TO_I2:
3918                 case OP_ICONV_TO_I2:
3919                 case OP_SEXT_I2:
3920                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3921                         break;
3922                 case OP_LCONV_TO_U1:
3923                 case OP_ICONV_TO_U1:
3924                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3925                         break;
3926                 case OP_LCONV_TO_U2:
3927                 case OP_ICONV_TO_U2:
3928                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3929                         break;
3930                 case OP_ZEXT_I4:
3931                         /* Clean out the upper word */
3932                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3933                         break;
3934                 case OP_SEXT_I4:
3935                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3936                         break;
3937                 case OP_COMPARE:
3938                 case OP_LCOMPARE:
3939                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3940                         break;
3941                 case OP_COMPARE_IMM:
3942 #if defined(__mono_ilp32__)
3943                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3944                         g_assert (amd64_is_imm32 (ins->inst_imm));
3945                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3946                         break;
3947 #endif
3948                 case OP_LCOMPARE_IMM:
3949                         g_assert (amd64_is_imm32 (ins->inst_imm));
3950                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3951                         break;
3952                 case OP_X86_COMPARE_REG_MEMBASE:
3953                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3954                         break;
3955                 case OP_X86_TEST_NULL:
3956                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3957                         break;
3958                 case OP_AMD64_TEST_NULL:
3959                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3960                         break;
3961
3962                 case OP_X86_ADD_REG_MEMBASE:
3963                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3964                         break;
3965                 case OP_X86_SUB_REG_MEMBASE:
3966                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3967                         break;
3968                 case OP_X86_AND_REG_MEMBASE:
3969                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3970                         break;
3971                 case OP_X86_OR_REG_MEMBASE:
3972                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3973                         break;
3974                 case OP_X86_XOR_REG_MEMBASE:
3975                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3976                         break;
3977
3978                 case OP_X86_ADD_MEMBASE_IMM:
3979                         /* FIXME: Make a 64 version too */
3980                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3981                         break;
3982                 case OP_X86_SUB_MEMBASE_IMM:
3983                         g_assert (amd64_is_imm32 (ins->inst_imm));
3984                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3985                         break;
3986                 case OP_X86_AND_MEMBASE_IMM:
3987                         g_assert (amd64_is_imm32 (ins->inst_imm));
3988                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3989                         break;
3990                 case OP_X86_OR_MEMBASE_IMM:
3991                         g_assert (amd64_is_imm32 (ins->inst_imm));
3992                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3993                         break;
3994                 case OP_X86_XOR_MEMBASE_IMM:
3995                         g_assert (amd64_is_imm32 (ins->inst_imm));
3996                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3997                         break;
3998                 case OP_X86_ADD_MEMBASE_REG:
3999                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4000                         break;
4001                 case OP_X86_SUB_MEMBASE_REG:
4002                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4003                         break;
4004                 case OP_X86_AND_MEMBASE_REG:
4005                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4006                         break;
4007                 case OP_X86_OR_MEMBASE_REG:
4008                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4009                         break;
4010                 case OP_X86_XOR_MEMBASE_REG:
4011                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4012                         break;
4013                 case OP_X86_INC_MEMBASE:
4014                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4015                         break;
4016                 case OP_X86_INC_REG:
4017                         amd64_inc_reg_size (code, ins->dreg, 4);
4018                         break;
4019                 case OP_X86_DEC_MEMBASE:
4020                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4021                         break;
4022                 case OP_X86_DEC_REG:
4023                         amd64_dec_reg_size (code, ins->dreg, 4);
4024                         break;
4025                 case OP_X86_MUL_REG_MEMBASE:
4026                 case OP_X86_MUL_MEMBASE_REG:
4027                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4028                         break;
4029                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4030                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4031                         break;
4032                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4033                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4034                         break;
4035                 case OP_AMD64_COMPARE_MEMBASE_REG:
4036                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4037                         break;
4038                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4039                         g_assert (amd64_is_imm32 (ins->inst_imm));
4040                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4041                         break;
4042                 case OP_X86_COMPARE_MEMBASE8_IMM:
4043                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4044                         break;
4045                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4046                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4047                         break;
4048                 case OP_AMD64_COMPARE_REG_MEMBASE:
4049                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4050                         break;
4051
4052                 case OP_AMD64_ADD_REG_MEMBASE:
4053                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4054                         break;
4055                 case OP_AMD64_SUB_REG_MEMBASE:
4056                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4057                         break;
4058                 case OP_AMD64_AND_REG_MEMBASE:
4059                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4060                         break;
4061                 case OP_AMD64_OR_REG_MEMBASE:
4062                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4063                         break;
4064                 case OP_AMD64_XOR_REG_MEMBASE:
4065                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4066                         break;
4067
4068                 case OP_AMD64_ADD_MEMBASE_REG:
4069                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4070                         break;
4071                 case OP_AMD64_SUB_MEMBASE_REG:
4072                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4073                         break;
4074                 case OP_AMD64_AND_MEMBASE_REG:
4075                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4076                         break;
4077                 case OP_AMD64_OR_MEMBASE_REG:
4078                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4079                         break;
4080                 case OP_AMD64_XOR_MEMBASE_REG:
4081                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4082                         break;
4083
4084                 case OP_AMD64_ADD_MEMBASE_IMM:
4085                         g_assert (amd64_is_imm32 (ins->inst_imm));
4086                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4087                         break;
4088                 case OP_AMD64_SUB_MEMBASE_IMM:
4089                         g_assert (amd64_is_imm32 (ins->inst_imm));
4090                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4091                         break;
4092                 case OP_AMD64_AND_MEMBASE_IMM:
4093                         g_assert (amd64_is_imm32 (ins->inst_imm));
4094                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4095                         break;
4096                 case OP_AMD64_OR_MEMBASE_IMM:
4097                         g_assert (amd64_is_imm32 (ins->inst_imm));
4098                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4099                         break;
4100                 case OP_AMD64_XOR_MEMBASE_IMM:
4101                         g_assert (amd64_is_imm32 (ins->inst_imm));
4102                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4103                         break;
4104
4105                 case OP_BREAK:
4106                         amd64_breakpoint (code);
4107                         break;
4108                 case OP_RELAXED_NOP:
4109                         x86_prefix (code, X86_REP_PREFIX);
4110                         x86_nop (code);
4111                         break;
4112                 case OP_HARD_NOP:
4113                         x86_nop (code);
4114                         break;
4115                 case OP_NOP:
4116                 case OP_DUMMY_USE:
4117                 case OP_DUMMY_STORE:
4118                 case OP_DUMMY_ICONST:
4119                 case OP_DUMMY_R8CONST:
4120                 case OP_NOT_REACHED:
4121                 case OP_NOT_NULL:
4122                         break;
4123                 case OP_IL_SEQ_POINT:
4124                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4125                         break;
4126                 case OP_SEQ_POINT: {
4127                         int i;
4128
4129                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4130                                 if (cfg->compile_aot) {
4131                                         MonoInst *var = cfg->arch.ss_tramp_var;
4132                                         guint8 *label;
4133
4134                                         /* Load ss_tramp_var */
4135                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4136                                         /* Load the trampoline address */
4137                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4138                                         /* Call it if it is non-null */
4139                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4140                                         label = code;
4141                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4142                                         amd64_call_reg (code, AMD64_R11);
4143                                         amd64_patch (label, code);
4144                                 } else {
4145                                         /*
4146                                          * Read from the single stepping trigger page. This will cause a
4147                                          * SIGSEGV when single stepping is enabled.
4148                                          * We do this _before_ the breakpoint, so single stepping after
4149                                          * a breakpoint is hit will step to the next IL offset.
4150                                          */
4151                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4152
4153                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4154                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4155                                 }
4156                         }
4157
4158                         /*
4159                          * This is the address which is saved in seq points,
4160                          */
4161                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4162
4163                         if (cfg->compile_aot) {
4164                                 guint32 offset = code - cfg->native_code;
4165                                 guint32 val;
4166                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4167                                 guint8 *label;
4168
4169                                 /* Load info var */
4170                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4171                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4172                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4173                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4174                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4175                                 label = code;
4176                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4177                                 /* Call the trampoline */
4178                                 amd64_call_reg (code, AMD64_R11);
4179                                 amd64_patch (label, code);
4180                         } else {
4181                                 /*
4182                                  * A placeholder for a possible breakpoint inserted by
4183                                  * mono_arch_set_breakpoint ().
4184                                  */
4185                                 for (i = 0; i < breakpoint_size; ++i)
4186                                         x86_nop (code);
4187                         }
4188                         /*
4189                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4190                          * to another IL offset.
4191                          */
4192                         x86_nop (code);
4193                         break;
4194                 }
4195                 case OP_ADDCC:
4196                 case OP_LADDCC:
4197                 case OP_LADD:
4198                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4199                         break;
4200                 case OP_ADC:
4201                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4202                         break;
4203                 case OP_ADD_IMM:
4204                 case OP_LADD_IMM:
4205                         g_assert (amd64_is_imm32 (ins->inst_imm));
4206                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4207                         break;
4208                 case OP_ADC_IMM:
4209                         g_assert (amd64_is_imm32 (ins->inst_imm));
4210                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4211                         break;
4212                 case OP_SUBCC:
4213                 case OP_LSUBCC:
4214                 case OP_LSUB:
4215                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4216                         break;
4217                 case OP_SBB:
4218                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4219                         break;
4220                 case OP_SUB_IMM:
4221                 case OP_LSUB_IMM:
4222                         g_assert (amd64_is_imm32 (ins->inst_imm));
4223                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4224                         break;
4225                 case OP_SBB_IMM:
4226                         g_assert (amd64_is_imm32 (ins->inst_imm));
4227                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4228                         break;
4229                 case OP_LAND:
4230                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4231                         break;
4232                 case OP_AND_IMM:
4233                 case OP_LAND_IMM:
4234                         g_assert (amd64_is_imm32 (ins->inst_imm));
4235                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4236                         break;
4237                 case OP_LMUL:
4238                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4239                         break;
4240                 case OP_MUL_IMM:
4241                 case OP_LMUL_IMM:
4242                 case OP_IMUL_IMM: {
4243                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4244
4245                         switch (ins->inst_imm) {
4246                         case 2:
4247                                 /* MOV r1, r2 */
4248                                 /* ADD r1, r1 */
4249                                 if (ins->dreg != ins->sreg1)
4250                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4251                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4252                                 break;
4253                         case 3:
4254                                 /* LEA r1, [r2 + r2*2] */
4255                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4256                                 break;
4257                         case 5:
4258                                 /* LEA r1, [r2 + r2*4] */
4259                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4260                                 break;
4261                         case 6:
4262                                 /* LEA r1, [r2 + r2*2] */
4263                                 /* ADD r1, r1          */
4264                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4265                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4266                                 break;
4267                         case 9:
4268                                 /* LEA r1, [r2 + r2*8] */
4269                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4270                                 break;
4271                         case 10:
4272                                 /* LEA r1, [r2 + r2*4] */
4273                                 /* ADD r1, r1          */
4274                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4275                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4276                                 break;
4277                         case 12:
4278                                 /* LEA r1, [r2 + r2*2] */
4279                                 /* SHL r1, 2           */
4280                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4281                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4282                                 break;
4283                         case 25:
4284                                 /* LEA r1, [r2 + r2*4] */
4285                                 /* LEA r1, [r1 + r1*4] */
4286                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4287                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4288                                 break;
4289                         case 100:
4290                                 /* LEA r1, [r2 + r2*4] */
4291                                 /* SHL r1, 2           */
4292                                 /* LEA r1, [r1 + r1*4] */
4293                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4294                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4295                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4296                                 break;
4297                         default:
4298                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4299                                 break;
4300                         }
4301                         break;
4302                 }
4303                 case OP_LDIV:
4304                 case OP_LREM:
4305 #if defined( __native_client_codegen__ )
4306                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4307                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4308 #endif
4309                         /* Regalloc magic makes the div/rem cases the same */
4310                         if (ins->sreg2 == AMD64_RDX) {
4311                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4312                                 amd64_cdq (code);
4313                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4314                         } else {
4315                                 amd64_cdq (code);
4316                                 amd64_div_reg (code, ins->sreg2, TRUE);
4317                         }
4318                         break;
4319                 case OP_LDIV_UN:
4320                 case OP_LREM_UN:
4321 #if defined( __native_client_codegen__ )
4322                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4323                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4324 #endif
4325                         if (ins->sreg2 == AMD64_RDX) {
4326                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4327                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4328                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4329                         } else {
4330                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4331                                 amd64_div_reg (code, ins->sreg2, FALSE);
4332                         }
4333                         break;
4334                 case OP_IDIV:
4335                 case OP_IREM:
4336 #if defined( __native_client_codegen__ )
4337                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4338                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4339 #endif
4340                         if (ins->sreg2 == AMD64_RDX) {
4341                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4342                                 amd64_cdq_size (code, 4);
4343                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4344                         } else {
4345                                 amd64_cdq_size (code, 4);
4346                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4347                         }
4348                         break;
4349                 case OP_IDIV_UN:
4350                 case OP_IREM_UN:
4351 #if defined( __native_client_codegen__ )
4352                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4353                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4354 #endif
4355                         if (ins->sreg2 == AMD64_RDX) {
4356                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4357                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4358                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4359                         } else {
4360                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4361                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4362                         }
4363                         break;
4364                 case OP_LMUL_OVF:
4365                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4366                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4367                         break;
4368                 case OP_LOR:
4369                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4370                         break;
4371                 case OP_OR_IMM:
4372                 case OP_LOR_IMM:
4373                         g_assert (amd64_is_imm32 (ins->inst_imm));
4374                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4375                         break;
4376                 case OP_LXOR:
4377                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4378                         break;
4379                 case OP_XOR_IMM:
4380                 case OP_LXOR_IMM:
4381                         g_assert (amd64_is_imm32 (ins->inst_imm));
4382                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4383                         break;
4384                 case OP_LSHL:
4385                         g_assert (ins->sreg2 == AMD64_RCX);
4386                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4387                         break;
4388                 case OP_LSHR:
4389                         g_assert (ins->sreg2 == AMD64_RCX);
4390                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4391                         break;
4392                 case OP_SHR_IMM:
4393                 case OP_LSHR_IMM:
4394                         g_assert (amd64_is_imm32 (ins->inst_imm));
4395                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4396                         break;
4397                 case OP_SHR_UN_IMM:
4398                         g_assert (amd64_is_imm32 (ins->inst_imm));
4399                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4400                         break;
4401                 case OP_LSHR_UN_IMM:
4402                         g_assert (amd64_is_imm32 (ins->inst_imm));
4403                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4404                         break;
4405                 case OP_LSHR_UN:
4406                         g_assert (ins->sreg2 == AMD64_RCX);
4407                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4408                         break;
4409                 case OP_SHL_IMM:
4410                 case OP_LSHL_IMM:
4411                         g_assert (amd64_is_imm32 (ins->inst_imm));
4412                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4413                         break;
4414
4415                 case OP_IADDCC:
4416                 case OP_IADD:
4417                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4418                         break;
4419                 case OP_IADC:
4420                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4421                         break;
4422                 case OP_IADD_IMM:
4423                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4424                         break;
4425                 case OP_IADC_IMM:
4426                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4427                         break;
4428                 case OP_ISUBCC:
4429                 case OP_ISUB:
4430                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4431                         break;
4432                 case OP_ISBB:
4433                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4434                         break;
4435                 case OP_ISUB_IMM:
4436                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4437                         break;
4438                 case OP_ISBB_IMM:
4439                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4440                         break;
4441                 case OP_IAND:
4442                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4443                         break;
4444                 case OP_IAND_IMM:
4445                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4446                         break;
4447                 case OP_IOR:
4448                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4449                         break;
4450                 case OP_IOR_IMM:
4451                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4452                         break;
4453                 case OP_IXOR:
4454                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4455                         break;
4456                 case OP_IXOR_IMM:
4457                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4458                         break;
4459                 case OP_INEG:
4460                         amd64_neg_reg_size (code, ins->sreg1, 4);
4461                         break;
4462                 case OP_INOT:
4463                         amd64_not_reg_size (code, ins->sreg1, 4);
4464                         break;
4465                 case OP_ISHL:
4466                         g_assert (ins->sreg2 == AMD64_RCX);
4467                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4468                         break;
4469                 case OP_ISHR:
4470                         g_assert (ins->sreg2 == AMD64_RCX);
4471                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4472                         break;
4473                 case OP_ISHR_IMM:
4474                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4475                         break;
4476                 case OP_ISHR_UN_IMM:
4477                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4478                         break;
4479                 case OP_ISHR_UN:
4480                         g_assert (ins->sreg2 == AMD64_RCX);
4481                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4482                         break;
4483                 case OP_ISHL_IMM:
4484                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4485                         break;
4486                 case OP_IMUL:
4487                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4488                         break;
4489                 case OP_IMUL_OVF:
4490                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4491                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4492                         break;
4493                 case OP_IMUL_OVF_UN:
4494                 case OP_LMUL_OVF_UN: {
4495                         /* the mul operation and the exception check should most likely be split */
4496                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4497                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4498                         /*g_assert (ins->sreg2 == X86_EAX);
4499                         g_assert (ins->dreg == X86_EAX);*/
4500                         if (ins->sreg2 == X86_EAX) {
4501                                 non_eax_reg = ins->sreg1;
4502                         } else if (ins->sreg1 == X86_EAX) {
4503                                 non_eax_reg = ins->sreg2;
4504                         } else {
4505                                 /* no need to save since we're going to store to it anyway */
4506                                 if (ins->dreg != X86_EAX) {
4507                                         saved_eax = TRUE;
4508                                         amd64_push_reg (code, X86_EAX);
4509                                 }
4510                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4511                                 non_eax_reg = ins->sreg2;
4512                         }
4513                         if (ins->dreg == X86_EDX) {
4514                                 if (!saved_eax) {
4515                                         saved_eax = TRUE;
4516                                         amd64_push_reg (code, X86_EAX);
4517                                 }
4518                         } else {
4519                                 saved_edx = TRUE;
4520                                 amd64_push_reg (code, X86_EDX);
4521                         }
4522                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4523                         /* save before the check since pop and mov don't change the flags */
4524                         if (ins->dreg != X86_EAX)
4525                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4526                         if (saved_edx)
4527                                 amd64_pop_reg (code, X86_EDX);
4528                         if (saved_eax)
4529                                 amd64_pop_reg (code, X86_EAX);
4530                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4531                         break;
4532                 }
4533                 case OP_ICOMPARE:
4534                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4535                         break;
4536                 case OP_ICOMPARE_IMM:
4537                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4538                         break;
4539                 case OP_IBEQ:
4540                 case OP_IBLT:
4541                 case OP_IBGT:
4542                 case OP_IBGE:
4543                 case OP_IBLE:
4544                 case OP_LBEQ:
4545                 case OP_LBLT:
4546                 case OP_LBGT:
4547                 case OP_LBGE:
4548                 case OP_LBLE:
4549                 case OP_IBNE_UN:
4550                 case OP_IBLT_UN:
4551                 case OP_IBGT_UN:
4552                 case OP_IBGE_UN:
4553                 case OP_IBLE_UN:
4554                 case OP_LBNE_UN:
4555                 case OP_LBLT_UN:
4556                 case OP_LBGT_UN:
4557                 case OP_LBGE_UN:
4558                 case OP_LBLE_UN:
4559                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4560                         break;
4561
4562                 case OP_CMOV_IEQ:
4563                 case OP_CMOV_IGE:
4564                 case OP_CMOV_IGT:
4565                 case OP_CMOV_ILE:
4566                 case OP_CMOV_ILT:
4567                 case OP_CMOV_INE_UN:
4568                 case OP_CMOV_IGE_UN:
4569                 case OP_CMOV_IGT_UN:
4570                 case OP_CMOV_ILE_UN:
4571                 case OP_CMOV_ILT_UN:
4572                 case OP_CMOV_LEQ:
4573                 case OP_CMOV_LGE:
4574                 case OP_CMOV_LGT:
4575                 case OP_CMOV_LLE:
4576                 case OP_CMOV_LLT:
4577                 case OP_CMOV_LNE_UN:
4578                 case OP_CMOV_LGE_UN:
4579                 case OP_CMOV_LGT_UN:
4580                 case OP_CMOV_LLE_UN:
4581                 case OP_CMOV_LLT_UN:
4582                         g_assert (ins->dreg == ins->sreg1);
4583                         /* This needs to operate on 64 bit values */
4584                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4585                         break;
4586
4587                 case OP_LNOT:
4588                         amd64_not_reg (code, ins->sreg1);
4589                         break;
4590                 case OP_LNEG:
4591                         amd64_neg_reg (code, ins->sreg1);
4592                         break;
4593
4594                 case OP_ICONST:
4595                 case OP_I8CONST:
4596                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4597                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4598                         else
4599                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4600                         break;
4601                 case OP_AOTCONST:
4602                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4603                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4604                         break;
4605                 case OP_JUMP_TABLE:
4606                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4607                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4608                         break;
4609                 case OP_MOVE:
4610                         if (ins->dreg != ins->sreg1)
4611                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4612                         break;
4613                 case OP_AMD64_SET_XMMREG_R4: {
4614                         if (cfg->r4fp) {
4615                                 if (ins->dreg != ins->sreg1)
4616                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4617                         } else {
4618                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4619                         }
4620                         break;
4621                 }
4622                 case OP_AMD64_SET_XMMREG_R8: {
4623                         if (ins->dreg != ins->sreg1)
4624                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4625                         break;
4626                 }
4627                 case OP_TAILCALL: {
4628                         MonoCallInst *call = (MonoCallInst*)ins;
4629                         int i, save_area_offset;
4630
4631                         g_assert (!cfg->method->save_lmf);
4632
4633                         /* Restore callee saved registers */
4634                         save_area_offset = cfg->arch.reg_save_area_offset;
4635                         for (i = 0; i < AMD64_NREG; ++i)
4636                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4637                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4638                                         save_area_offset += 8;
4639                                 }
4640
4641                         if (cfg->arch.omit_fp) {
4642                                 if (cfg->arch.stack_alloc_size)
4643                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4644                                 // FIXME:
4645                                 if (call->stack_usage)
4646                                         NOT_IMPLEMENTED;
4647                         } else {
4648                                 /* Copy arguments on the stack to our argument area */
4649                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4650                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4651                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4652                                 }
4653
4654                                 amd64_leave (code);
4655                         }
4656
4657                         offset = code - cfg->native_code;
4658                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4659                         if (cfg->compile_aot)
4660                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4661                         else
4662                                 amd64_set_reg_template (code, AMD64_R11);
4663                         amd64_jump_reg (code, AMD64_R11);
4664                         ins->flags |= MONO_INST_GC_CALLSITE;
4665                         ins->backend.pc_offset = code - cfg->native_code;
4666                         break;
4667                 }
4668                 case OP_CHECK_THIS:
4669                         /* ensure ins->sreg1 is not NULL */
4670                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4671                         break;
4672                 case OP_ARGLIST: {
4673                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4674                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4675                         break;
4676                 }
4677                 case OP_CALL:
4678                 case OP_FCALL:
4679                 case OP_RCALL:
4680                 case OP_LCALL:
4681                 case OP_VCALL:
4682                 case OP_VCALL2:
4683                 case OP_VOIDCALL:
4684                         call = (MonoCallInst*)ins;
4685                         /*
4686                          * The AMD64 ABI forces callers to know about varargs.
4687                          */
4688                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4689                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4690                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4691                                 /*
4692                                  * Since the unmanaged calling convention doesn't contain a
4693                                  * 'vararg' entry, we have to treat every pinvoke call as a
4694                                  * potential vararg call.
4695                                  */
4696                                 guint32 nregs, i;
4697                                 nregs = 0;
4698                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4699                                         if (call->used_fregs & (1 << i))
4700                                                 nregs ++;
4701                                 if (!nregs)
4702                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4703                                 else
4704                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4705                         }
4706
4707                         if (ins->flags & MONO_INST_HAS_METHOD)
4708                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4709                         else
4710                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4711                         ins->flags |= MONO_INST_GC_CALLSITE;
4712                         ins->backend.pc_offset = code - cfg->native_code;
4713                         code = emit_move_return_value (cfg, ins, code);
4714                         break;
4715                 case OP_FCALL_REG:
4716                 case OP_RCALL_REG:
4717                 case OP_LCALL_REG:
4718                 case OP_VCALL_REG:
4719                 case OP_VCALL2_REG:
4720                 case OP_VOIDCALL_REG:
4721                 case OP_CALL_REG:
4722                         call = (MonoCallInst*)ins;
4723
4724                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4725                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4726                                 ins->sreg1 = AMD64_R11;
4727                         }
4728
4729                         /*
4730                          * The AMD64 ABI forces callers to know about varargs.
4731                          */
4732                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4733                                 if (ins->sreg1 == AMD64_RAX) {
4734                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4735                                         ins->sreg1 = AMD64_R11;
4736                                 }
4737                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4738                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4739                                 /*
4740                                  * Since the unmanaged calling convention doesn't contain a
4741                                  * 'vararg' entry, we have to treat every pinvoke call as a
4742                                  * potential vararg call.
4743                                  */
4744                                 guint32 nregs, i;
4745                                 nregs = 0;
4746                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4747                                         if (call->used_fregs & (1 << i))
4748                                                 nregs ++;
4749                                 if (ins->sreg1 == AMD64_RAX) {
4750                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4751                                         ins->sreg1 = AMD64_R11;
4752                                 }
4753                                 if (!nregs)
4754                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4755                                 else
4756                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4757                         }
4758
4759                         amd64_call_reg (code, ins->sreg1);
4760                         ins->flags |= MONO_INST_GC_CALLSITE;
4761                         ins->backend.pc_offset = code - cfg->native_code;
4762                         code = emit_move_return_value (cfg, ins, code);
4763                         break;
4764                 case OP_FCALL_MEMBASE:
4765                 case OP_RCALL_MEMBASE:
4766                 case OP_LCALL_MEMBASE:
4767                 case OP_VCALL_MEMBASE:
4768                 case OP_VCALL2_MEMBASE:
4769                 case OP_VOIDCALL_MEMBASE:
4770                 case OP_CALL_MEMBASE:
4771                         call = (MonoCallInst*)ins;
4772
4773                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4774                         ins->flags |= MONO_INST_GC_CALLSITE;
4775                         ins->backend.pc_offset = code - cfg->native_code;
4776                         code = emit_move_return_value (cfg, ins, code);
4777                         break;
4778                 case OP_DYN_CALL: {
4779                         int i;
4780                         MonoInst *var = cfg->dyn_call_var;
4781
4782                         g_assert (var->opcode == OP_REGOFFSET);
4783
4784                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4785                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4786                         /* r10 = ftn */
4787                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4788
4789                         /* Save args buffer */
4790                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4791
4792                         /* Set argument registers */
4793                         for (i = 0; i < PARAM_REGS; ++i)
4794                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4795
4796                         /* Make the call */
4797                         amd64_call_reg (code, AMD64_R10);
4798
4799                         ins->flags |= MONO_INST_GC_CALLSITE;
4800                         ins->backend.pc_offset = code - cfg->native_code;
4801
4802                         /* Save result */
4803                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4804                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4805                         break;
4806                 }
4807                 case OP_AMD64_SAVE_SP_TO_LMF: {
4808                         MonoInst *lmf_var = cfg->lmf_var;
4809                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4810                         break;
4811                 }
4812                 case OP_X86_PUSH:
4813                         g_assert_not_reached ();
4814                         amd64_push_reg (code, ins->sreg1);
4815                         break;
4816                 case OP_X86_PUSH_IMM:
4817                         g_assert_not_reached ();
4818                         g_assert (amd64_is_imm32 (ins->inst_imm));
4819                         amd64_push_imm (code, ins->inst_imm);
4820                         break;
4821                 case OP_X86_PUSH_MEMBASE:
4822                         g_assert_not_reached ();
4823                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4824                         break;
4825                 case OP_X86_PUSH_OBJ: {
4826                         int size = ALIGN_TO (ins->inst_imm, 8);
4827
4828                         g_assert_not_reached ();
4829
4830                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4831                         amd64_push_reg (code, AMD64_RDI);
4832                         amd64_push_reg (code, AMD64_RSI);
4833                         amd64_push_reg (code, AMD64_RCX);
4834                         if (ins->inst_offset)
4835                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4836                         else
4837                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4838                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4839                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4840                         amd64_cld (code);
4841                         amd64_prefix (code, X86_REP_PREFIX);
4842                         amd64_movsd (code);
4843                         amd64_pop_reg (code, AMD64_RCX);
4844                         amd64_pop_reg (code, AMD64_RSI);
4845                         amd64_pop_reg (code, AMD64_RDI);
4846                         break;
4847                 }
4848                 case OP_GENERIC_CLASS_INIT: {
4849                         static int byte_offset = -1;
4850                         static guint8 bitmask;
4851                         guint8 *jump;
4852
4853                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4854
4855                         if (byte_offset < 0)
4856                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4857
4858                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4859                         jump = code;
4860                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4861
4862                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4863                         ins->flags |= MONO_INST_GC_CALLSITE;
4864                         ins->backend.pc_offset = code - cfg->native_code;
4865
4866                         x86_patch (jump, code);
4867                         break;
4868                 }
4869
4870                 case OP_X86_LEA:
4871                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4872                         break;
4873                 case OP_X86_LEA_MEMBASE:
4874                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4875                         break;
4876                 case OP_X86_XCHG:
4877                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4878                         break;
4879                 case OP_LOCALLOC:
4880                         /* keep alignment */
4881                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4882                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4883                         code = mono_emit_stack_alloc (cfg, code, ins);
4884                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4885                         if (cfg->param_area)
4886                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4887                         break;
4888                 case OP_LOCALLOC_IMM: {
4889                         guint32 size = ins->inst_imm;
4890                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4891
4892                         if (ins->flags & MONO_INST_INIT) {
4893                                 if (size < 64) {
4894                                         int i;
4895
4896                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4897                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4898
4899                                         for (i = 0; i < size; i += 8)
4900                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4901                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4902                                 } else {
4903                                         amd64_mov_reg_imm (code, ins->dreg, size);
4904                                         ins->sreg1 = ins->dreg;
4905
4906                                         code = mono_emit_stack_alloc (cfg, code, ins);
4907                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4908                                 }
4909                         } else {
4910                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4911                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4912                         }
4913                         if (cfg->param_area)
4914                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4915                         break;
4916                 }
4917                 case OP_THROW: {
4918                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4919                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4920                                              (gpointer)"mono_arch_throw_exception", FALSE);
4921                         ins->flags |= MONO_INST_GC_CALLSITE;
4922                         ins->backend.pc_offset = code - cfg->native_code;
4923                         break;
4924                 }
4925                 case OP_RETHROW: {
4926                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4927                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4928                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4929                         ins->flags |= MONO_INST_GC_CALLSITE;
4930                         ins->backend.pc_offset = code - cfg->native_code;
4931                         break;
4932                 }
4933                 case OP_CALL_HANDLER:
4934                         /* Align stack */
4935                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4936                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4937                         amd64_call_imm (code, 0);
4938                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4939                         /* Restore stack alignment */
4940                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4941                         break;
4942                 case OP_START_HANDLER: {
4943                         /* Even though we're saving RSP, use sizeof */
4944                         /* gpointer because spvar is of type IntPtr */
4945                         /* see: mono_create_spvar_for_region */
4946                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4947                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4948
4949                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4950                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4951                                 cfg->param_area) {
4952                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4953                         }
4954                         break;
4955                 }
4956                 case OP_ENDFINALLY: {
4957                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4958                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4959                         amd64_ret (code);
4960                         break;
4961                 }
4962                 case OP_ENDFILTER: {
4963                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4964                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4965                         /* The local allocator will put the result into RAX */
4966                         amd64_ret (code);
4967                         break;
4968                 }
4969                 case OP_GET_EX_OBJ:
4970                         if (ins->dreg != AMD64_RAX)
4971                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4972                         break;
4973                 case OP_LABEL:
4974                         ins->inst_c0 = code - cfg->native_code;
4975                         break;
4976                 case OP_BR:
4977                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4978                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4979                         //break;
4980                                 if (ins->inst_target_bb->native_offset) {
4981                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4982                                 } else {
4983                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4984                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4985                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4986                                                 x86_jump8 (code, 0);
4987                                         else
4988                                                 x86_jump32 (code, 0);
4989                         }
4990                         break;
4991                 case OP_BR_REG:
4992                         amd64_jump_reg (code, ins->sreg1);
4993                         break;
4994                 case OP_ICNEQ:
4995                 case OP_ICGE:
4996                 case OP_ICLE:
4997                 case OP_ICGE_UN:
4998                 case OP_ICLE_UN:
4999
5000                 case OP_CEQ:
5001                 case OP_LCEQ:
5002                 case OP_ICEQ:
5003                 case OP_CLT:
5004                 case OP_LCLT:
5005                 case OP_ICLT:
5006                 case OP_CGT:
5007                 case OP_ICGT:
5008                 case OP_LCGT:
5009                 case OP_CLT_UN:
5010                 case OP_LCLT_UN:
5011                 case OP_ICLT_UN:
5012                 case OP_CGT_UN:
5013                 case OP_LCGT_UN:
5014                 case OP_ICGT_UN:
5015                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5016                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5017                         break;
5018                 case OP_COND_EXC_EQ:
5019                 case OP_COND_EXC_NE_UN:
5020                 case OP_COND_EXC_LT:
5021                 case OP_COND_EXC_LT_UN:
5022                 case OP_COND_EXC_GT:
5023                 case OP_COND_EXC_GT_UN:
5024                 case OP_COND_EXC_GE:
5025                 case OP_COND_EXC_GE_UN:
5026                 case OP_COND_EXC_LE:
5027                 case OP_COND_EXC_LE_UN:
5028                 case OP_COND_EXC_IEQ:
5029                 case OP_COND_EXC_INE_UN:
5030                 case OP_COND_EXC_ILT:
5031                 case OP_COND_EXC_ILT_UN:
5032                 case OP_COND_EXC_IGT:
5033                 case OP_COND_EXC_IGT_UN:
5034                 case OP_COND_EXC_IGE:
5035                 case OP_COND_EXC_IGE_UN:
5036                 case OP_COND_EXC_ILE:
5037                 case OP_COND_EXC_ILE_UN:
5038                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5039                         break;
5040                 case OP_COND_EXC_OV:
5041                 case OP_COND_EXC_NO:
5042                 case OP_COND_EXC_C:
5043                 case OP_COND_EXC_NC:
5044                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5045                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5046                         break;
5047                 case OP_COND_EXC_IOV:
5048                 case OP_COND_EXC_INO:
5049                 case OP_COND_EXC_IC:
5050                 case OP_COND_EXC_INC:
5051                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5052                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5053                         break;
5054
5055                 /* floating point opcodes */
5056                 case OP_R8CONST: {
5057                         double d = *(double *)ins->inst_p0;
5058
5059                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5060                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5061                         }
5062                         else {
5063                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5064                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5065                         }
5066                         break;
5067                 }
5068                 case OP_R4CONST: {
5069                         float f = *(float *)ins->inst_p0;
5070
5071                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5072                                 if (cfg->r4fp)
5073                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5074                                 else
5075                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5076                         }
5077                         else {
5078                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5079                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5080                                 if (!cfg->r4fp)
5081                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5082                         }
5083                         break;
5084                 }
5085                 case OP_STORER8_MEMBASE_REG:
5086                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5087                         break;
5088                 case OP_LOADR8_MEMBASE:
5089                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5090                         break;
5091                 case OP_STORER4_MEMBASE_REG:
5092                         if (cfg->r4fp) {
5093                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5094                         } else {
5095                                 /* This requires a double->single conversion */
5096                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5097                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5098                         }
5099                         break;
5100                 case OP_LOADR4_MEMBASE:
5101                         if (cfg->r4fp) {
5102                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5103                         } else {
5104                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5105                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5106                         }
5107                         break;
5108                 case OP_ICONV_TO_R4:
5109                         if (cfg->r4fp) {
5110                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5111                         } else {
5112                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5113                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5114                         }
5115                         break;
5116                 case OP_ICONV_TO_R8:
5117                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5118                         break;
5119                 case OP_LCONV_TO_R4:
5120                         if (cfg->r4fp) {
5121                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5122                         } else {
5123                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5124                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5125                         }
5126                         break;
5127                 case OP_LCONV_TO_R8:
5128                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5129                         break;
5130                 case OP_FCONV_TO_R4:
5131                         if (cfg->r4fp) {
5132                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5133                         } else {
5134                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5135                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5136                         }
5137                         break;
5138                 case OP_FCONV_TO_I1:
5139                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5140                         break;
5141                 case OP_FCONV_TO_U1:
5142                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5143                         break;
5144                 case OP_FCONV_TO_I2:
5145                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5146                         break;
5147                 case OP_FCONV_TO_U2:
5148                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5149                         break;
5150                 case OP_FCONV_TO_U4:
5151                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5152                         break;
5153                 case OP_FCONV_TO_I4:
5154                 case OP_FCONV_TO_I:
5155                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5156                         break;
5157                 case OP_FCONV_TO_I8:
5158                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5159                         break;
5160
5161                 case OP_RCONV_TO_I1:
5162                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5163                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5164                         break;
5165                 case OP_RCONV_TO_U1:
5166                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5167                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5168                         break;
5169                 case OP_RCONV_TO_I2:
5170                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5171                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5172                         break;
5173                 case OP_RCONV_TO_U2:
5174                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5175                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5176                         break;
5177                 case OP_RCONV_TO_I4:
5178                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5179                         break;
5180                 case OP_RCONV_TO_U4:
5181                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5182                         break;
5183                 case OP_RCONV_TO_I8:
5184                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5185                         break;
5186                 case OP_RCONV_TO_R8:
5187                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5188                         break;
5189                 case OP_RCONV_TO_R4:
5190                         if (ins->dreg != ins->sreg1)
5191                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5192                         break;
5193
5194                 case OP_LCONV_TO_R_UN: {
5195                         guint8 *br [2];
5196
5197                         /* Based on gcc code */
5198                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5199                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5200
5201                         /* Positive case */
5202                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5203                         br [1] = code; x86_jump8 (code, 0);
5204                         amd64_patch (br [0], code);
5205
5206                         /* Negative case */
5207                         /* Save to the red zone */
5208                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5209                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5210                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5211                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5212                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5213                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5214                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5215                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5216                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5217                         /* Restore */
5218                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5219                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5220                         amd64_patch (br [1], code);
5221                         break;
5222                 }
5223                 case OP_LCONV_TO_OVF_U4:
5224                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5225                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5226                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5227                         break;
5228                 case OP_LCONV_TO_OVF_I4_UN:
5229                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5230                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5231                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5232                         break;
5233                 case OP_FMOVE:
5234                         if (ins->dreg != ins->sreg1)
5235                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5236                         break;
5237                 case OP_RMOVE:
5238                         if (ins->dreg != ins->sreg1)
5239                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5240                         break;
5241                 case OP_MOVE_F_TO_I4:
5242                         if (cfg->r4fp) {
5243                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5244                         } else {
5245                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5246                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5247                         }
5248                         break;
5249                 case OP_MOVE_I4_TO_F:
5250                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5251                         if (!cfg->r4fp)
5252                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5253                         break;
5254                 case OP_MOVE_F_TO_I8:
5255                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5256                         break;
5257                 case OP_MOVE_I8_TO_F:
5258                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5259                         break;
5260                 case OP_FADD:
5261                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5262                         break;
5263                 case OP_FSUB:
5264                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5265                         break;
5266                 case OP_FMUL:
5267                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5268                         break;
5269                 case OP_FDIV:
5270                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5271                         break;
5272                 case OP_FNEG: {
5273                         static double r8_0 = -0.0;
5274
5275                         g_assert (ins->sreg1 == ins->dreg);
5276
5277                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5278                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5279                         break;
5280                 }
5281                 case OP_SIN:
5282                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5283                         break;
5284                 case OP_COS:
5285                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5286                         break;
5287                 case OP_ABS: {
5288                         static guint64 d = 0x7fffffffffffffffUL;
5289
5290                         g_assert (ins->sreg1 == ins->dreg);
5291
5292                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5293                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5294                         break;
5295                 }
5296                 case OP_SQRT:
5297                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5298                         break;
5299
5300                 case OP_RADD:
5301                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5302                         break;
5303                 case OP_RSUB:
5304                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5305                         break;
5306                 case OP_RMUL:
5307                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5308                         break;
5309                 case OP_RDIV:
5310                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5311                         break;
5312                 case OP_RNEG: {
5313                         static float r4_0 = -0.0;
5314
5315                         g_assert (ins->sreg1 == ins->dreg);
5316
5317                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5318                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5319                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5320                         break;
5321                 }
5322
5323                 case OP_IMIN:
5324                         g_assert (cfg->opt & MONO_OPT_CMOV);
5325                         g_assert (ins->dreg == ins->sreg1);
5326                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5327                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5328                         break;
5329                 case OP_IMIN_UN:
5330                         g_assert (cfg->opt & MONO_OPT_CMOV);
5331                         g_assert (ins->dreg == ins->sreg1);
5332                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5333                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5334                         break;
5335                 case OP_IMAX:
5336                         g_assert (cfg->opt & MONO_OPT_CMOV);
5337                         g_assert (ins->dreg == ins->sreg1);
5338                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5339                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5340                         break;
5341                 case OP_IMAX_UN:
5342                         g_assert (cfg->opt & MONO_OPT_CMOV);
5343                         g_assert (ins->dreg == ins->sreg1);
5344                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5345                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5346                         break;
5347                 case OP_LMIN:
5348                         g_assert (cfg->opt & MONO_OPT_CMOV);
5349                         g_assert (ins->dreg == ins->sreg1);
5350                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5351                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5352                         break;
5353                 case OP_LMIN_UN:
5354                         g_assert (cfg->opt & MONO_OPT_CMOV);
5355                         g_assert (ins->dreg == ins->sreg1);
5356                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5357                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5358                         break;
5359                 case OP_LMAX:
5360                         g_assert (cfg->opt & MONO_OPT_CMOV);
5361                         g_assert (ins->dreg == ins->sreg1);
5362                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5363                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5364                         break;
5365                 case OP_LMAX_UN:
5366                         g_assert (cfg->opt & MONO_OPT_CMOV);
5367                         g_assert (ins->dreg == ins->sreg1);
5368                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5369                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5370                         break;
5371                 case OP_X86_FPOP:
5372                         break;
5373                 case OP_FCOMPARE:
5374                         /*
5375                          * The two arguments are swapped because the fbranch instructions
5376                          * depend on this for the non-sse case to work.
5377                          */
5378                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5379                         break;
5380                 case OP_RCOMPARE:
5381                         /*
5382                          * FIXME: Get rid of this.
5383                          * The two arguments are swapped because the fbranch instructions
5384                          * depend on this for the non-sse case to work.
5385                          */
5386                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5387                         break;
5388                 case OP_FCNEQ:
5389                 case OP_FCEQ: {
5390                         /* zeroing the register at the start results in
5391                          * shorter and faster code (we can also remove the widening op)
5392                          */
5393                         guchar *unordered_check;
5394
5395                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5396                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5397                         unordered_check = code;
5398                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5399
5400                         if (ins->opcode == OP_FCEQ) {
5401                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5402                                 amd64_patch (unordered_check, code);
5403                         } else {
5404                                 guchar *jump_to_end;
5405                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5406                                 jump_to_end = code;
5407                                 x86_jump8 (code, 0);
5408                                 amd64_patch (unordered_check, code);
5409                                 amd64_inc_reg (code, ins->dreg);
5410                                 amd64_patch (jump_to_end, code);
5411                         }
5412                         break;
5413                 }
5414                 case OP_FCLT:
5415                 case OP_FCLT_UN: {
5416                         /* zeroing the register at the start results in
5417                          * shorter and faster code (we can also remove the widening op)
5418                          */
5419                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5420                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5421                         if (ins->opcode == OP_FCLT_UN) {
5422                                 guchar *unordered_check = code;
5423                                 guchar *jump_to_end;
5424                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5425                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5426                                 jump_to_end = code;
5427                                 x86_jump8 (code, 0);
5428                                 amd64_patch (unordered_check, code);
5429                                 amd64_inc_reg (code, ins->dreg);
5430                                 amd64_patch (jump_to_end, code);
5431                         } else {
5432                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5433                         }
5434                         break;
5435                 }
5436                 case OP_FCLE: {
5437                         guchar *unordered_check;
5438                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5439                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5440                         unordered_check = code;
5441                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5442                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5443                         amd64_patch (unordered_check, code);
5444                         break;
5445                 }
5446                 case OP_FCGT:
5447                 case OP_FCGT_UN: {
5448                         /* zeroing the register at the start results in
5449                          * shorter and faster code (we can also remove the widening op)
5450                          */
5451                         guchar *unordered_check;
5452
5453                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5454                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5455                         if (ins->opcode == OP_FCGT) {
5456                                 unordered_check = code;
5457                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5458                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5459                                 amd64_patch (unordered_check, code);
5460                         } else {
5461                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5462                         }
5463                         break;
5464                 }
5465                 case OP_FCGE: {
5466                         guchar *unordered_check;
5467                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5468                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5469                         unordered_check = code;
5470                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5471                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5472                         amd64_patch (unordered_check, code);
5473                         break;
5474                 }
5475
5476                 case OP_RCEQ:
5477                 case OP_RCGT:
5478                 case OP_RCLT:
5479                 case OP_RCLT_UN:
5480                 case OP_RCGT_UN: {
5481                         int x86_cond;
5482                         gboolean unordered = FALSE;
5483
5484                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5485                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5486
5487                         switch (ins->opcode) {
5488                         case OP_RCEQ:
5489                                 x86_cond = X86_CC_EQ;
5490                                 break;
5491                         case OP_RCGT:
5492                                 x86_cond = X86_CC_LT;
5493                                 break;
5494                         case OP_RCLT:
5495                                 x86_cond = X86_CC_GT;
5496                                 break;
5497                         case OP_RCLT_UN:
5498                                 x86_cond = X86_CC_GT;
5499                                 unordered = TRUE;
5500                                 break;
5501                         case OP_RCGT_UN:
5502                                 x86_cond = X86_CC_LT;
5503                                 unordered = TRUE;
5504                                 break;
5505                         default:
5506                                 g_assert_not_reached ();
5507                                 break;
5508                         }
5509
5510                         if (unordered) {
5511                                 guchar *unordered_check;
5512                                 guchar *jump_to_end;
5513
5514                                 unordered_check = code;
5515                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5516                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5517                                 jump_to_end = code;
5518                                 x86_jump8 (code, 0);
5519                                 amd64_patch (unordered_check, code);
5520                                 amd64_inc_reg (code, ins->dreg);
5521                                 amd64_patch (jump_to_end, code);
5522                         } else {
5523                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5524                         }
5525                         break;
5526                 }
5527                 case OP_FCLT_MEMBASE:
5528                 case OP_FCGT_MEMBASE:
5529                 case OP_FCLT_UN_MEMBASE:
5530                 case OP_FCGT_UN_MEMBASE:
5531                 case OP_FCEQ_MEMBASE: {
5532                         guchar *unordered_check, *jump_to_end;
5533                         int x86_cond;
5534
5535                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5536                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5537
5538                         switch (ins->opcode) {
5539                         case OP_FCEQ_MEMBASE:
5540                                 x86_cond = X86_CC_EQ;
5541                                 break;
5542                         case OP_FCLT_MEMBASE:
5543                         case OP_FCLT_UN_MEMBASE:
5544                                 x86_cond = X86_CC_LT;
5545                                 break;
5546                         case OP_FCGT_MEMBASE:
5547                         case OP_FCGT_UN_MEMBASE:
5548                                 x86_cond = X86_CC_GT;
5549                                 break;
5550                         default:
5551                                 g_assert_not_reached ();
5552                         }
5553
5554                         unordered_check = code;
5555                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5556                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5557
5558                         switch (ins->opcode) {
5559                         case OP_FCEQ_MEMBASE:
5560                         case OP_FCLT_MEMBASE:
5561                         case OP_FCGT_MEMBASE:
5562                                 amd64_patch (unordered_check, code);
5563                                 break;
5564                         case OP_FCLT_UN_MEMBASE:
5565                         case OP_FCGT_UN_MEMBASE:
5566                                 jump_to_end = code;
5567                                 x86_jump8 (code, 0);
5568                                 amd64_patch (unordered_check, code);
5569                                 amd64_inc_reg (code, ins->dreg);
5570                                 amd64_patch (jump_to_end, code);
5571                                 break;
5572                         default:
5573                                 break;
5574                         }
5575                         break;
5576                 }
5577                 case OP_FBEQ: {
5578                         guchar *jump = code;
5579                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5580                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5581                         amd64_patch (jump, code);
5582                         break;
5583                 }
5584                 case OP_FBNE_UN:
5585                         /* Branch if C013 != 100 */
5586                         /* branch if !ZF or (PF|CF) */
5587                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5588                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5589                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5590                         break;
5591                 case OP_FBLT:
5592                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5593                         break;
5594                 case OP_FBLT_UN:
5595                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5596                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5597                         break;
5598                 case OP_FBGT:
5599                 case OP_FBGT_UN:
5600                         if (ins->opcode == OP_FBGT) {
5601                                 guchar *br1;
5602
5603                                 /* skip branch if C1=1 */
5604                                 br1 = code;
5605                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5606                                 /* branch if (C0 | C3) = 1 */
5607                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5608                                 amd64_patch (br1, code);
5609                                 break;
5610                         } else {
5611                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5612                         }
5613                         break;
5614                 case OP_FBGE: {
5615                         /* Branch if C013 == 100 or 001 */
5616                         guchar *br1;
5617
5618                         /* skip branch if C1=1 */
5619                         br1 = code;
5620                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5621                         /* branch if (C0 | C3) = 1 */
5622                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5623                         amd64_patch (br1, code);
5624                         break;
5625                 }
5626                 case OP_FBGE_UN:
5627                         /* Branch if C013 == 000 */
5628                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5629                         break;
5630                 case OP_FBLE: {
5631                         /* Branch if C013=000 or 100 */
5632                         guchar *br1;
5633
5634                         /* skip branch if C1=1 */
5635                         br1 = code;
5636                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5637                         /* branch if C0=0 */
5638                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5639                         amd64_patch (br1, code);
5640                         break;
5641                 }
5642                 case OP_FBLE_UN:
5643                         /* Branch if C013 != 001 */
5644                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5645                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5646                         break;
5647                 case OP_CKFINITE:
5648                         /* Transfer value to the fp stack */
5649                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5650                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5651                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5652
5653                         amd64_push_reg (code, AMD64_RAX);
5654                         amd64_fxam (code);
5655                         amd64_fnstsw (code);
5656                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5657                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5658                         amd64_pop_reg (code, AMD64_RAX);
5659                         amd64_fstp (code, 0);
5660                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5661                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5662                         break;
5663                 case OP_TLS_GET: {
5664                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5665                         break;
5666                 }
5667                 case OP_TLS_GET_REG:
5668                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5669                         break;
5670                 case OP_TLS_SET: {
5671                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5672                         break;
5673                 }
5674                 case OP_TLS_SET_REG: {
5675                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5676                         break;
5677                 }
5678                 case OP_MEMORY_BARRIER: {
5679                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5680                                 x86_mfence (code);
5681                         break;
5682                 }
5683                 case OP_ATOMIC_ADD_I4:
5684                 case OP_ATOMIC_ADD_I8: {
5685                         int dreg = ins->dreg;
5686                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5687
5688                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5689                                 dreg = AMD64_R11;
5690
5691                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5692                         amd64_prefix (code, X86_LOCK_PREFIX);
5693                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5694                         /* dreg contains the old value, add with sreg2 value */
5695                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5696
5697                         if (ins->dreg != dreg)
5698                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5699
5700                         break;
5701                 }
5702                 case OP_ATOMIC_EXCHANGE_I4:
5703                 case OP_ATOMIC_EXCHANGE_I8: {
5704                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5705
5706                         /* LOCK prefix is implied. */
5707                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5708                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5709                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5710                         break;
5711                 }
5712                 case OP_ATOMIC_CAS_I4:
5713                 case OP_ATOMIC_CAS_I8: {
5714                         guint32 size;
5715
5716                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5717                                 size = 8;
5718                         else
5719                                 size = 4;
5720
5721                         /*
5722                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5723                          * an explanation of how this works.
5724                          */
5725                         g_assert (ins->sreg3 == AMD64_RAX);
5726                         g_assert (ins->sreg1 != AMD64_RAX);
5727                         g_assert (ins->sreg1 != ins->sreg2);
5728
5729                         amd64_prefix (code, X86_LOCK_PREFIX);
5730                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5731
5732                         if (ins->dreg != AMD64_RAX)
5733                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5734                         break;
5735                 }
5736                 case OP_ATOMIC_LOAD_I1: {
5737                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5738                         break;
5739                 }
5740                 case OP_ATOMIC_LOAD_U1: {
5741                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5742                         break;
5743                 }
5744                 case OP_ATOMIC_LOAD_I2: {
5745                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5746                         break;
5747                 }
5748                 case OP_ATOMIC_LOAD_U2: {
5749                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5750                         break;
5751                 }
5752                 case OP_ATOMIC_LOAD_I4: {
5753                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5754                         break;
5755                 }
5756                 case OP_ATOMIC_LOAD_U4:
5757                 case OP_ATOMIC_LOAD_I8:
5758                 case OP_ATOMIC_LOAD_U8: {
5759                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5760                         break;
5761                 }
5762                 case OP_ATOMIC_LOAD_R4: {
5763                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5764                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5765                         break;
5766                 }
5767                 case OP_ATOMIC_LOAD_R8: {
5768                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5769                         break;
5770                 }
5771                 case OP_ATOMIC_STORE_I1:
5772                 case OP_ATOMIC_STORE_U1:
5773                 case OP_ATOMIC_STORE_I2:
5774                 case OP_ATOMIC_STORE_U2:
5775                 case OP_ATOMIC_STORE_I4:
5776                 case OP_ATOMIC_STORE_U4:
5777                 case OP_ATOMIC_STORE_I8:
5778                 case OP_ATOMIC_STORE_U8: {
5779                         int size;
5780
5781                         switch (ins->opcode) {
5782                         case OP_ATOMIC_STORE_I1:
5783                         case OP_ATOMIC_STORE_U1:
5784                                 size = 1;
5785                                 break;
5786                         case OP_ATOMIC_STORE_I2:
5787                         case OP_ATOMIC_STORE_U2:
5788                                 size = 2;
5789                                 break;
5790                         case OP_ATOMIC_STORE_I4:
5791                         case OP_ATOMIC_STORE_U4:
5792                                 size = 4;
5793                                 break;
5794                         case OP_ATOMIC_STORE_I8:
5795                         case OP_ATOMIC_STORE_U8:
5796                                 size = 8;
5797                                 break;
5798                         }
5799
5800                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5801
5802                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5803                                 x86_mfence (code);
5804                         break;
5805                 }
5806                 case OP_ATOMIC_STORE_R4: {
5807                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5808                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5809
5810                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5811                                 x86_mfence (code);
5812                         break;
5813                 }
5814                 case OP_ATOMIC_STORE_R8: {
5815                         x86_nop (code);
5816                         x86_nop (code);
5817                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5818                         x86_nop (code);
5819                         x86_nop (code);
5820
5821                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5822                                 x86_mfence (code);
5823                         break;
5824                 }
5825                 case OP_CARD_TABLE_WBARRIER: {
5826                         int ptr = ins->sreg1;
5827                         int value = ins->sreg2;
5828                         guchar *br = 0;
5829                         int nursery_shift, card_table_shift;
5830                         gpointer card_table_mask;
5831                         size_t nursery_size;
5832
5833                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5834                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5835                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5836
5837                         /*If either point to the stack we can simply avoid the WB. This happens due to
5838                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5839                          */
5840                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5841                                 continue;
5842
5843                         /*
5844                          * We need one register we can clobber, we choose EDX and make sreg1
5845                          * fixed EAX to work around limitations in the local register allocator.
5846                          * sreg2 might get allocated to EDX, but that is not a problem since
5847                          * we use it before clobbering EDX.
5848                          */
5849                         g_assert (ins->sreg1 == AMD64_RAX);
5850
5851                         /*
5852                          * This is the code we produce:
5853                          *
5854                          *   edx = value
5855                          *   edx >>= nursery_shift
5856                          *   cmp edx, (nursery_start >> nursery_shift)
5857                          *   jne done
5858                          *   edx = ptr
5859                          *   edx >>= card_table_shift
5860                          *   edx += cardtable
5861                          *   [edx] = 1
5862                          * done:
5863                          */
5864
5865                         if (mono_gc_card_table_nursery_check ()) {
5866                                 if (value != AMD64_RDX)
5867                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5868                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5869                                 if (shifted_nursery_start >> 31) {
5870                                         /*
5871                                          * The value we need to compare against is 64 bits, so we need
5872                                          * another spare register.  We use RBX, which we save and
5873                                          * restore.
5874                                          */
5875                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5876                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5877                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5878                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5879                                 } else {
5880                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5881                                 }
5882                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5883                         }
5884                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5885                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5886                         if (card_table_mask)
5887                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5888
5889                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5890                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5891
5892                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5893
5894                         if (mono_gc_card_table_nursery_check ())
5895                                 x86_patch (br, code);
5896                         break;
5897                 }
5898 #ifdef MONO_ARCH_SIMD_INTRINSICS
5899                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5900                 case OP_ADDPS:
5901                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5902                         break;
5903                 case OP_DIVPS:
5904                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5905                         break;
5906                 case OP_MULPS:
5907                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5908                         break;
5909                 case OP_SUBPS:
5910                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_MAXPS:
5913                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_MINPS:
5916                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5917                         break;
5918                 case OP_COMPPS:
5919                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5920                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5921                         break;
5922                 case OP_ANDPS:
5923                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5924                         break;
5925                 case OP_ANDNPS:
5926                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5927                         break;
5928                 case OP_ORPS:
5929                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5930                         break;
5931                 case OP_XORPS:
5932                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5933                         break;
5934                 case OP_SQRTPS:
5935                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5936                         break;
5937                 case OP_RSQRTPS:
5938                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5939                         break;
5940                 case OP_RCPPS:
5941                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5942                         break;
5943                 case OP_ADDSUBPS:
5944                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5945                         break;
5946                 case OP_HADDPS:
5947                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5948                         break;
5949                 case OP_HSUBPS:
5950                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_DUPPS_HIGH:
5953                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5954                         break;
5955                 case OP_DUPPS_LOW:
5956                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5957                         break;
5958
5959                 case OP_PSHUFLEW_HIGH:
5960                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5961                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5962                         break;
5963                 case OP_PSHUFLEW_LOW:
5964                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5965                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5966                         break;
5967                 case OP_PSHUFLED:
5968                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5969                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5970                         break;
5971                 case OP_SHUFPS:
5972                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5973                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5974                         break;
5975                 case OP_SHUFPD:
5976                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5977                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5978                         break;
5979
5980                 case OP_ADDPD:
5981                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5982                         break;
5983                 case OP_DIVPD:
5984                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5985                         break;
5986                 case OP_MULPD:
5987                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5988                         break;
5989                 case OP_SUBPD:
5990                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_MAXPD:
5993                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_MINPD:
5996                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_COMPPD:
5999                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6000                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6001                         break;
6002                 case OP_ANDPD:
6003                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6004                         break;
6005                 case OP_ANDNPD:
6006                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6007                         break;
6008                 case OP_ORPD:
6009                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_XORPD:
6012                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_SQRTPD:
6015                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6016                         break;
6017                 case OP_ADDSUBPD:
6018                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020                 case OP_HADDPD:
6021                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6022                         break;
6023                 case OP_HSUBPD:
6024                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6025                         break;
6026                 case OP_DUPPD:
6027                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6028                         break;
6029
6030                 case OP_EXTRACT_MASK:
6031                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6032                         break;
6033
6034                 case OP_PAND:
6035                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_POR:
6038                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_PXOR:
6041                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043
6044                 case OP_PADDB:
6045                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6046                         break;
6047                 case OP_PADDW:
6048                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6049                         break;
6050                 case OP_PADDD:
6051                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053                 case OP_PADDQ:
6054                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056
6057                 case OP_PSUBB:
6058                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6059                         break;
6060                 case OP_PSUBW:
6061                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6062                         break;
6063                 case OP_PSUBD:
6064                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066                 case OP_PSUBQ:
6067                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6068                         break;
6069
6070                 case OP_PMAXB_UN:
6071                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6072                         break;
6073                 case OP_PMAXW_UN:
6074                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6075                         break;
6076                 case OP_PMAXD_UN:
6077                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079
6080                 case OP_PMAXB:
6081                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083                 case OP_PMAXW:
6084                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6085                         break;
6086                 case OP_PMAXD:
6087                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089
6090                 case OP_PAVGB_UN:
6091                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093                 case OP_PAVGW_UN:
6094                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6095                         break;
6096
6097                 case OP_PMINB_UN:
6098                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100                 case OP_PMINW_UN:
6101                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103                 case OP_PMIND_UN:
6104                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106
6107                 case OP_PMINB:
6108                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6109                         break;
6110                 case OP_PMINW:
6111                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6112                         break;
6113                 case OP_PMIND:
6114                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6115                         break;
6116
6117                 case OP_PCMPEQB:
6118                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120                 case OP_PCMPEQW:
6121                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6122                         break;
6123                 case OP_PCMPEQD:
6124                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126                 case OP_PCMPEQQ:
6127                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129
6130                 case OP_PCMPGTB:
6131                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6132                         break;
6133                 case OP_PCMPGTW:
6134                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6135                         break;
6136                 case OP_PCMPGTD:
6137                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6138                         break;
6139                 case OP_PCMPGTQ:
6140                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6141                         break;
6142
6143                 case OP_PSUM_ABS_DIFF:
6144                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6145                         break;
6146
6147                 case OP_UNPACK_LOWB:
6148                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6149                         break;
6150                 case OP_UNPACK_LOWW:
6151                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6152                         break;
6153                 case OP_UNPACK_LOWD:
6154                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6155                         break;
6156                 case OP_UNPACK_LOWQ:
6157                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6158                         break;
6159                 case OP_UNPACK_LOWPS:
6160                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6161                         break;
6162                 case OP_UNPACK_LOWPD:
6163                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6164                         break;
6165
6166                 case OP_UNPACK_HIGHB:
6167                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6168                         break;
6169                 case OP_UNPACK_HIGHW:
6170                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6171                         break;
6172                 case OP_UNPACK_HIGHD:
6173                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6174                         break;
6175                 case OP_UNPACK_HIGHQ:
6176                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6177                         break;
6178                 case OP_UNPACK_HIGHPS:
6179                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6180                         break;
6181                 case OP_UNPACK_HIGHPD:
6182                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6183                         break;
6184
6185                 case OP_PACKW:
6186                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6187                         break;
6188                 case OP_PACKD:
6189                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6190                         break;
6191                 case OP_PACKW_UN:
6192                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194                 case OP_PACKD_UN:
6195                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6196                         break;
6197
6198                 case OP_PADDB_SAT_UN:
6199                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201                 case OP_PSUBB_SAT_UN:
6202                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_PADDW_SAT_UN:
6205                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207                 case OP_PSUBW_SAT_UN:
6208                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6209                         break;
6210
6211                 case OP_PADDB_SAT:
6212                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6213                         break;
6214                 case OP_PSUBB_SAT:
6215                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6216                         break;
6217                 case OP_PADDW_SAT:
6218                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6219                         break;
6220                 case OP_PSUBW_SAT:
6221                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6222                         break;
6223
6224                 case OP_PMULW:
6225                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6226                         break;
6227                 case OP_PMULD:
6228                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6229                         break;
6230                 case OP_PMULQ:
6231                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6232                         break;
6233                 case OP_PMULW_HIGH_UN:
6234                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236                 case OP_PMULW_HIGH:
6237                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239
6240                 case OP_PSHRW:
6241                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6242                         break;
6243                 case OP_PSHRW_REG:
6244                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6245                         break;
6246
6247                 case OP_PSARW:
6248                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6249                         break;
6250                 case OP_PSARW_REG:
6251                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6252                         break;
6253
6254                 case OP_PSHLW:
6255                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6256                         break;
6257                 case OP_PSHLW_REG:
6258                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6259                         break;
6260
6261                 case OP_PSHRD:
6262                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6263                         break;
6264                 case OP_PSHRD_REG:
6265                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6266                         break;
6267
6268                 case OP_PSARD:
6269                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6270                         break;
6271                 case OP_PSARD_REG:
6272                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6273                         break;
6274
6275                 case OP_PSHLD:
6276                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6277                         break;
6278                 case OP_PSHLD_REG:
6279                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6280                         break;
6281
6282                 case OP_PSHRQ:
6283                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6284                         break;
6285                 case OP_PSHRQ_REG:
6286                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6287                         break;
6288
6289                 /*TODO: This is appart of the sse spec but not added
6290                 case OP_PSARQ:
6291                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6292                         break;
6293                 case OP_PSARQ_REG:
6294                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6295                         break;
6296                 */
6297
6298                 case OP_PSHLQ:
6299                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6300                         break;
6301                 case OP_PSHLQ_REG:
6302                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6303                         break;
6304                 case OP_CVTDQ2PD:
6305                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6306                         break;
6307                 case OP_CVTDQ2PS:
6308                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6309                         break;
6310                 case OP_CVTPD2DQ:
6311                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6312                         break;
6313                 case OP_CVTPD2PS:
6314                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6315                         break;
6316                 case OP_CVTPS2DQ:
6317                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6318                         break;
6319                 case OP_CVTPS2PD:
6320                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6321                         break;
6322                 case OP_CVTTPD2DQ:
6323                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6324                         break;
6325                 case OP_CVTTPS2DQ:
6326                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6327                         break;
6328
6329                 case OP_ICONV_TO_X:
6330                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6331                         break;
6332                 case OP_EXTRACT_I4:
6333                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6334                         break;
6335                 case OP_EXTRACT_I8:
6336                         if (ins->inst_c0) {
6337                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6338                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6339                         } else {
6340                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6341                         }
6342                         break;
6343                 case OP_EXTRACT_I1:
6344                 case OP_EXTRACT_U1:
6345                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6346                         if (ins->inst_c0)
6347                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6348                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6349                         break;
6350                 case OP_EXTRACT_I2:
6351                 case OP_EXTRACT_U2:
6352                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6353                         if (ins->inst_c0)
6354                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6355                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6356                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6357                         break;
6358                 case OP_EXTRACT_R8:
6359                         if (ins->inst_c0)
6360                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6361                         else
6362                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6363                         break;
6364                 case OP_INSERT_I2:
6365                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6366                         break;
6367                 case OP_EXTRACTX_U2:
6368                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6369                         break;
6370                 case OP_INSERTX_U1_SLOW:
6371                         /*sreg1 is the extracted ireg (scratch)
6372                         /sreg2 is the to be inserted ireg (scratch)
6373                         /dreg is the xreg to receive the value*/
6374
6375                         /*clear the bits from the extracted word*/
6376                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6377                         /*shift the value to insert if needed*/
6378                         if (ins->inst_c0 & 1)
6379                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6380                         /*join them together*/
6381                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6382                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6383                         break;
6384                 case OP_INSERTX_I4_SLOW:
6385                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6386                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6387                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6388                         break;
6389                 case OP_INSERTX_I8_SLOW:
6390                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6391                         if (ins->inst_c0)
6392                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6393                         else
6394                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6395                         break;
6396
6397                 case OP_INSERTX_R4_SLOW:
6398                         switch (ins->inst_c0) {
6399                         case 0:
6400                                 if (cfg->r4fp)
6401                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6402                                 else
6403                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6404                                 break;
6405                         case 1:
6406                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6407                                 if (cfg->r4fp)
6408                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6409                                 else
6410                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6411                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6412                                 break;
6413                         case 2:
6414                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6415                                 if (cfg->r4fp)
6416                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6417                                 else
6418                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6419                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6420                                 break;
6421                         case 3:
6422                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6423                                 if (cfg->r4fp)
6424                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6425                                 else
6426                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6427                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6428                                 break;
6429                         }
6430                         break;
6431                 case OP_INSERTX_R8_SLOW:
6432                         if (ins->inst_c0)
6433                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6434                         else
6435                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6436                         break;
6437                 case OP_STOREX_MEMBASE_REG:
6438                 case OP_STOREX_MEMBASE:
6439                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6440                         break;
6441                 case OP_LOADX_MEMBASE:
6442                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6443                         break;
6444                 case OP_LOADX_ALIGNED_MEMBASE:
6445                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6446                         break;
6447                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6448                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6449                         break;
6450                 case OP_STOREX_NTA_MEMBASE_REG:
6451                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6452                         break;
6453                 case OP_PREFETCH_MEMBASE:
6454                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6455                         break;
6456
6457                 case OP_XMOVE:
6458                         /*FIXME the peephole pass should have killed this*/
6459                         if (ins->dreg != ins->sreg1)
6460                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6461                         break;
6462                 case OP_XZERO:
6463                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6464                         break;
6465                 case OP_ICONV_TO_R4_RAW:
6466                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6467                         break;
6468
6469                 case OP_FCONV_TO_R8_X:
6470                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6471                         break;
6472
6473                 case OP_XCONV_R8_TO_I4:
6474                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6475                         switch (ins->backend.source_opcode) {
6476                         case OP_FCONV_TO_I1:
6477                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6478                                 break;
6479                         case OP_FCONV_TO_U1:
6480                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6481                                 break;
6482                         case OP_FCONV_TO_I2:
6483                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6484                                 break;
6485                         case OP_FCONV_TO_U2:
6486                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6487                                 break;
6488                         }
6489                         break;
6490
6491                 case OP_EXPAND_I2:
6492                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6493                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6494                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6495                         break;
6496                 case OP_EXPAND_I4:
6497                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6498                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6499                         break;
6500                 case OP_EXPAND_I8:
6501                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6502                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6503                         break;
6504                 case OP_EXPAND_R4:
6505                         if (cfg->r4fp) {
6506                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6507                         } else {
6508                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6509                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6510                         }
6511                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6512                         break;
6513                 case OP_EXPAND_R8:
6514                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6515                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6516                         break;
6517 #endif
6518                 case OP_LIVERANGE_START: {
6519                         if (cfg->verbose_level > 1)
6520                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6521                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6522                         break;
6523                 }
6524                 case OP_LIVERANGE_END: {
6525                         if (cfg->verbose_level > 1)
6526                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6527                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6528                         break;
6529                 }
6530                 case OP_GC_SAFE_POINT: {
6531                         const char *polling_func = NULL;
6532                         int compare_val = 0;
6533                         guint8 *br [1];
6534
6535 #if defined (USE_COOP_GC)
6536                         polling_func = "mono_threads_state_poll";
6537                         compare_val = 1;
6538 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6539                         polling_func = "mono_nacl_gc";
6540                         compare_val = 0xFFFFFFFF;
6541 #endif
6542                         if (!polling_func)
6543                                 break;
6544
6545                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6546                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6547                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6548                         amd64_patch (br[0], code);
6549                         break;
6550                 }
6551
6552                 case OP_GC_LIVENESS_DEF:
6553                 case OP_GC_LIVENESS_USE:
6554                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6555                         ins->backend.pc_offset = code - cfg->native_code;
6556                         break;
6557                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6558                         ins->backend.pc_offset = code - cfg->native_code;
6559                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6560                         break;
6561                 default:
6562                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6563                         g_assert_not_reached ();
6564                 }
6565
6566                 if ((code - cfg->native_code - offset) > max_len) {
6567 #if !defined(__native_client_codegen__)
6568                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6569                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6570                         g_assert_not_reached ();
6571 #endif
6572                 }
6573         }
6574
6575         cfg->code_len = code - cfg->native_code;
6576 }
6577
6578 #endif /* DISABLE_JIT */
6579
6580 void
6581 mono_arch_register_lowlevel_calls (void)
6582 {
6583         /* The signature doesn't matter */
6584         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6585 }
6586
6587 void
6588 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6589 {
6590         unsigned char *ip = ji->ip.i + code;
6591
6592         /*
6593          * Debug code to help track down problems where the target of a near call is
6594          * is not valid.
6595          */
6596         if (amd64_is_near_call (ip)) {
6597                 gint64 disp = (guint8*)target - (guint8*)ip;
6598
6599                 if (!amd64_is_imm32 (disp)) {
6600                         printf ("TYPE: %d\n", ji->type);
6601                         switch (ji->type) {
6602                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6603                                 printf ("V: %s\n", ji->data.name);
6604                                 break;
6605                         case MONO_PATCH_INFO_METHOD_JUMP:
6606                         case MONO_PATCH_INFO_METHOD:
6607                                 printf ("V: %s\n", ji->data.method->name);
6608                                 break;
6609                         default:
6610                                 break;
6611                         }
6612                 }
6613         }
6614
6615         amd64_patch (ip, (gpointer)target);
6616 }
6617
6618 #ifndef DISABLE_JIT
6619
6620 static int
6621 get_max_epilog_size (MonoCompile *cfg)
6622 {
6623         int max_epilog_size = 16;
6624
6625         if (cfg->method->save_lmf)
6626                 max_epilog_size += 256;
6627
6628         if (mono_jit_trace_calls != NULL)
6629                 max_epilog_size += 50;
6630
6631         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6632                 max_epilog_size += 50;
6633
6634         max_epilog_size += (AMD64_NREG * 2);
6635
6636         return max_epilog_size;
6637 }
6638
6639 /*
6640  * This macro is used for testing whenever the unwinder works correctly at every point
6641  * where an async exception can happen.
6642  */
6643 /* This will generate a SIGSEGV at the given point in the code */
6644 #define async_exc_point(code) do { \
6645     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6646          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6647              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6648          cfg->arch.async_point_count ++; \
6649     } \
6650 } while (0)
6651
6652 guint8 *
6653 mono_arch_emit_prolog (MonoCompile *cfg)
6654 {
6655         MonoMethod *method = cfg->method;
6656         MonoBasicBlock *bb;
6657         MonoMethodSignature *sig;
6658         MonoInst *ins;
6659         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6660         guint8 *code;
6661         CallInfo *cinfo;
6662         MonoInst *lmf_var = cfg->lmf_var;
6663         gboolean args_clobbered = FALSE;
6664         gboolean trace = FALSE;
6665 #ifdef __native_client_codegen__
6666         guint alignment_check;
6667 #endif
6668
6669         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6670
6671 #if defined(__default_codegen__)
6672         code = cfg->native_code = g_malloc (cfg->code_size);
6673 #elif defined(__native_client_codegen__)
6674         /* native_code_alloc is not 32-byte aligned, native_code is. */
6675         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6676
6677         /* Align native_code to next nearest kNaclAlignment byte. */
6678         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6679         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6680
6681         code = cfg->native_code;
6682
6683         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6684         g_assert (alignment_check == 0);
6685 #endif
6686
6687         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6688                 trace = TRUE;
6689
6690         /* Amount of stack space allocated by register saving code */
6691         pos = 0;
6692
6693         /* Offset between RSP and the CFA */
6694         cfa_offset = 0;
6695
6696         /*
6697          * The prolog consists of the following parts:
6698          * FP present:
6699          * - push rbp, mov rbp, rsp
6700          * - save callee saved regs using pushes
6701          * - allocate frame
6702          * - save rgctx if needed
6703          * - save lmf if needed
6704          * FP not present:
6705          * - allocate frame
6706          * - save rgctx if needed
6707          * - save lmf if needed
6708          * - save callee saved regs using moves
6709          */
6710
6711         // CFA = sp + 8
6712         cfa_offset = 8;
6713         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6714         // IP saved at CFA - 8
6715         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6716         async_exc_point (code);
6717         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6718
6719         if (!cfg->arch.omit_fp) {
6720                 amd64_push_reg (code, AMD64_RBP);
6721                 cfa_offset += 8;
6722                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6723                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6724                 async_exc_point (code);
6725 #ifdef TARGET_WIN32
6726                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6727 #endif
6728                 /* These are handled automatically by the stack marking code */
6729                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6730
6731                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6732                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6733                 async_exc_point (code);
6734 #ifdef TARGET_WIN32
6735                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6736 #endif
6737         }
6738
6739         /* The param area is always at offset 0 from sp */
6740         /* This needs to be allocated here, since it has to come after the spill area */
6741         if (cfg->param_area) {
6742                 if (cfg->arch.omit_fp)
6743                         // FIXME:
6744                         g_assert_not_reached ();
6745                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6746         }
6747
6748         if (cfg->arch.omit_fp) {
6749                 /*
6750                  * On enter, the stack is misaligned by the pushing of the return
6751                  * address. It is either made aligned by the pushing of %rbp, or by
6752                  * this.
6753                  */
6754                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6755                 if ((alloc_size % 16) == 0) {
6756                         alloc_size += 8;
6757                         /* Mark the padding slot as NOREF */
6758                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6759                 }
6760         } else {
6761                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6762                 if (cfg->stack_offset != alloc_size) {
6763                         /* Mark the padding slot as NOREF */
6764                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6765                 }
6766                 cfg->arch.sp_fp_offset = alloc_size;
6767                 alloc_size -= pos;
6768         }
6769
6770         cfg->arch.stack_alloc_size = alloc_size;
6771
6772         /* Allocate stack frame */
6773         if (alloc_size) {
6774                 /* See mono_emit_stack_alloc */
6775 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6776                 guint32 remaining_size = alloc_size;
6777                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6778                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6779                 guint32 offset = code - cfg->native_code;
6780                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6781                         while (required_code_size >= (cfg->code_size - offset))
6782                                 cfg->code_size *= 2;
6783                         cfg->native_code = mono_realloc_native_code (cfg);
6784                         code = cfg->native_code + offset;
6785                         cfg->stat_code_reallocs++;
6786                 }
6787
6788                 while (remaining_size >= 0x1000) {
6789                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6790                         if (cfg->arch.omit_fp) {
6791                                 cfa_offset += 0x1000;
6792                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6793                         }
6794                         async_exc_point (code);
6795 #ifdef TARGET_WIN32
6796                         if (cfg->arch.omit_fp)
6797                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6798 #endif
6799
6800                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6801                         remaining_size -= 0x1000;
6802                 }
6803                 if (remaining_size) {
6804                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6805                         if (cfg->arch.omit_fp) {
6806                                 cfa_offset += remaining_size;
6807                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6808                                 async_exc_point (code);
6809                         }
6810 #ifdef TARGET_WIN32
6811                         if (cfg->arch.omit_fp)
6812                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6813 #endif
6814                 }
6815 #else
6816                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6817                 if (cfg->arch.omit_fp) {
6818                         cfa_offset += alloc_size;
6819                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6820                         async_exc_point (code);
6821                 }
6822 #endif
6823         }
6824
6825         /* Stack alignment check */
6826 #if 0
6827         {
6828                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6829                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6830                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6831                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6832                 amd64_breakpoint (code);
6833         }
6834 #endif
6835
6836         if (mini_get_debug_options ()->init_stacks) {
6837                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6838
6839                 /* Save registers to the red zone */
6840                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6841                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6842
6843                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6844                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6845                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6846
6847                 amd64_cld (code);
6848 #if defined(__default_codegen__)
6849                 amd64_prefix (code, X86_REP_PREFIX);
6850                 amd64_stosl (code);
6851 #elif defined(__native_client_codegen__)
6852                 /* NaCl stos pseudo-instruction */
6853                 amd64_codegen_pre (code);
6854                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6855                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6856                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6857                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6858                 amd64_prefix (code, X86_REP_PREFIX);
6859                 amd64_stosl (code);
6860                 amd64_codegen_post (code);
6861 #endif /* __native_client_codegen__ */
6862
6863                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6864                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6865         }
6866
6867         /* Save LMF */
6868         if (method->save_lmf)
6869                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6870
6871         /* Save callee saved registers */
6872         if (cfg->arch.omit_fp) {
6873                 save_area_offset = cfg->arch.reg_save_area_offset;
6874                 /* Save caller saved registers after sp is adjusted */
6875                 /* The registers are saved at the bottom of the frame */
6876                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6877         } else {
6878                 /* The registers are saved just below the saved rbp */
6879                 save_area_offset = cfg->arch.reg_save_area_offset;
6880         }
6881
6882         for (i = 0; i < AMD64_NREG; ++i) {
6883                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6884                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6885
6886                         if (cfg->arch.omit_fp) {
6887                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6888                                 /* These are handled automatically by the stack marking code */
6889                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6890                         } else {
6891                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6892                                 // FIXME: GC
6893                         }
6894
6895                         save_area_offset += 8;
6896                         async_exc_point (code);
6897                 }
6898         }
6899
6900         /* store runtime generic context */
6901         if (cfg->rgctx_var) {
6902                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6903                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6904
6905                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6906
6907                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6908                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6909         }
6910
6911         /* compute max_length in order to use short forward jumps */
6912         max_epilog_size = get_max_epilog_size (cfg);
6913         if (cfg->opt & MONO_OPT_BRANCH) {
6914                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6915                         MonoInst *ins;
6916                         int max_length = 0;
6917
6918                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6919                                 max_length += 6;
6920                         /* max alignment for loops */
6921                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6922                                 max_length += LOOP_ALIGNMENT;
6923 #ifdef __native_client_codegen__
6924                         /* max alignment for native client */
6925                         max_length += kNaClAlignment;
6926 #endif
6927
6928                         MONO_BB_FOR_EACH_INS (bb, ins) {
6929 #ifdef __native_client_codegen__
6930                                 {
6931                                         int space_in_block = kNaClAlignment -
6932                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6933                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6934                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6935                                                 max_length += space_in_block;
6936                                         }
6937                                 }
6938 #endif  /*__native_client_codegen__*/
6939                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6940                         }
6941
6942                         /* Take prolog and epilog instrumentation into account */
6943                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6944                                 max_length += max_epilog_size;
6945
6946                         bb->max_length = max_length;
6947                 }
6948         }
6949
6950         sig = mono_method_signature (method);
6951         pos = 0;
6952
6953         cinfo = cfg->arch.cinfo;
6954
6955         if (sig->ret->type != MONO_TYPE_VOID) {
6956                 /* Save volatile arguments to the stack */
6957                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6958                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6959         }
6960
6961         /* Keep this in sync with emit_load_volatile_arguments */
6962         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6963                 ArgInfo *ainfo = cinfo->args + i;
6964
6965                 ins = cfg->args [i];
6966
6967                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6968                         /* Unused arguments */
6969                         continue;
6970
6971                 /* Save volatile arguments to the stack */
6972                 if (ins->opcode != OP_REGVAR) {
6973                         switch (ainfo->storage) {
6974                         case ArgInIReg: {
6975                                 guint32 size = 8;
6976
6977                                 /* FIXME: I1 etc */
6978                                 /*
6979                                 if (stack_offset & 0x1)
6980                                         size = 1;
6981                                 else if (stack_offset & 0x2)
6982                                         size = 2;
6983                                 else if (stack_offset & 0x4)
6984                                         size = 4;
6985                                 else
6986                                         size = 8;
6987                                 */
6988                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6989
6990                                 /*
6991                                  * Save the original location of 'this',
6992                                  * get_generic_info_from_stack_frame () needs this to properly look up
6993                                  * the argument value during the handling of async exceptions.
6994                                  */
6995                                 if (ins == cfg->args [0]) {
6996                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6997                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6998                                 }
6999                                 break;
7000                         }
7001                         case ArgInFloatSSEReg:
7002                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7003                                 break;
7004                         case ArgInDoubleSSEReg:
7005                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7006                                 break;
7007                         case ArgValuetypeInReg:
7008                                 for (quad = 0; quad < 2; quad ++) {
7009                                         switch (ainfo->pair_storage [quad]) {
7010                                         case ArgInIReg:
7011                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7012                                                 break;
7013                                         case ArgInFloatSSEReg:
7014                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7015                                                 break;
7016                                         case ArgInDoubleSSEReg:
7017                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7018                                                 break;
7019                                         case ArgNone:
7020                                                 break;
7021                                         default:
7022                                                 g_assert_not_reached ();
7023                                         }
7024                                 }
7025                                 break;
7026                         case ArgValuetypeAddrInIReg:
7027                                 if (ainfo->pair_storage [0] == ArgInIReg)
7028                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7029                                 break;
7030                         default:
7031                                 break;
7032                         }
7033                 } else {
7034                         /* Argument allocated to (non-volatile) register */
7035                         switch (ainfo->storage) {
7036                         case ArgInIReg:
7037                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7038                                 break;
7039                         case ArgOnStack:
7040                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7041                                 break;
7042                         default:
7043                                 g_assert_not_reached ();
7044                         }
7045
7046                         if (ins == cfg->args [0]) {
7047                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7048                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7049                         }
7050                 }
7051         }
7052
7053         if (cfg->method->save_lmf)
7054                 args_clobbered = TRUE;
7055
7056         if (trace) {
7057                 args_clobbered = TRUE;
7058                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7059         }
7060
7061         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7062                 args_clobbered = TRUE;
7063
7064         /*
7065          * Optimize the common case of the first bblock making a call with the same
7066          * arguments as the method. This works because the arguments are still in their
7067          * original argument registers.
7068          * FIXME: Generalize this
7069          */
7070         if (!args_clobbered) {
7071                 MonoBasicBlock *first_bb = cfg->bb_entry;
7072                 MonoInst *next;
7073                 int filter = FILTER_IL_SEQ_POINT;
7074
7075                 next = mono_bb_first_inst (first_bb, filter);
7076                 if (!next && first_bb->next_bb) {
7077                         first_bb = first_bb->next_bb;
7078                         next = mono_bb_first_inst (first_bb, filter);
7079                 }
7080
7081                 if (first_bb->in_count > 1)
7082                         next = NULL;
7083
7084                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7085                         ArgInfo *ainfo = cinfo->args + i;
7086                         gboolean match = FALSE;
7087
7088                         ins = cfg->args [i];
7089                         if (ins->opcode != OP_REGVAR) {
7090                                 switch (ainfo->storage) {
7091                                 case ArgInIReg: {
7092                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7093                                                 if (next->dreg == ainfo->reg) {
7094                                                         NULLIFY_INS (next);
7095                                                         match = TRUE;
7096                                                 } else {
7097                                                         next->opcode = OP_MOVE;
7098                                                         next->sreg1 = ainfo->reg;
7099                                                         /* Only continue if the instruction doesn't change argument regs */
7100                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7101                                                                 match = TRUE;
7102                                                 }
7103                                         }
7104                                         break;
7105                                 }
7106                                 default:
7107                                         break;
7108                                 }
7109                         } else {
7110                                 /* Argument allocated to (non-volatile) register */
7111                                 switch (ainfo->storage) {
7112                                 case ArgInIReg:
7113                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7114                                                 NULLIFY_INS (next);
7115                                                 match = TRUE;
7116                                         }
7117                                         break;
7118                                 default:
7119                                         break;
7120                                 }
7121                         }
7122
7123                         if (match) {
7124                                 next = mono_inst_next (next, filter);
7125                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7126                                 if (!next)
7127                                         break;
7128                         }
7129                 }
7130         }
7131
7132         if (cfg->gen_sdb_seq_points) {
7133                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7134
7135                 /* Initialize seq_point_info_var */
7136                 if (cfg->compile_aot) {
7137                         /* Initialize the variable from a GOT slot */
7138                         /* Same as OP_AOTCONST */
7139                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7140                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7141                         g_assert (info_var->opcode == OP_REGOFFSET);
7142                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7143                 }
7144
7145                 if (cfg->compile_aot) {
7146                         /* Initialize ss_tramp_var */
7147                         ins = cfg->arch.ss_tramp_var;
7148                         g_assert (ins->opcode == OP_REGOFFSET);
7149
7150                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7151                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7152                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7153                 } else {
7154                         /* Initialize ss_trigger_page_var */
7155                         ins = cfg->arch.ss_trigger_page_var;
7156
7157                         g_assert (ins->opcode == OP_REGOFFSET);
7158
7159                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7160                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7161                 }
7162         }
7163
7164         cfg->code_len = code - cfg->native_code;
7165
7166         g_assert (cfg->code_len < cfg->code_size);
7167
7168         return code;
7169 }
7170
7171 void
7172 mono_arch_emit_epilog (MonoCompile *cfg)
7173 {
7174         MonoMethod *method = cfg->method;
7175         int quad, i;
7176         guint8 *code;
7177         int max_epilog_size;
7178         CallInfo *cinfo;
7179         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7180         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7181
7182         max_epilog_size = get_max_epilog_size (cfg);
7183
7184         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7185                 cfg->code_size *= 2;
7186                 cfg->native_code = mono_realloc_native_code (cfg);
7187                 cfg->stat_code_reallocs++;
7188         }
7189         code = cfg->native_code + cfg->code_len;
7190
7191         cfg->has_unwind_info_for_epilog = TRUE;
7192
7193         /* Mark the start of the epilog */
7194         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7195
7196         /* Save the uwind state which is needed by the out-of-line code */
7197         mono_emit_unwind_op_remember_state (cfg, code);
7198
7199         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7200                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7201
7202         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7203
7204         if (method->save_lmf) {
7205                 /* check if we need to restore protection of the stack after a stack overflow */
7206                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7207                         guint8 *patch;
7208                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7209                         /* we load the value in a separate instruction: this mechanism may be
7210                          * used later as a safer way to do thread interruption
7211                          */
7212                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7213                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7214                         patch = code;
7215                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7216                         /* note that the call trampoline will preserve eax/edx */
7217                         x86_call_reg (code, X86_ECX);
7218                         x86_patch (patch, code);
7219                 } else {
7220                         /* FIXME: maybe save the jit tls in the prolog */
7221                 }
7222                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7223                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7224                 }
7225         }
7226
7227         /* Restore callee saved regs */
7228         for (i = 0; i < AMD64_NREG; ++i) {
7229                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7230                         /* Restore only used_int_regs, not arch.saved_iregs */
7231                         if (cfg->used_int_regs & (1 << i)) {
7232                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7233                                 mono_emit_unwind_op_same_value (cfg, code, i);
7234                                 async_exc_point (code);
7235                         }
7236                         save_area_offset += 8;
7237                 }
7238         }
7239
7240         /* Load returned vtypes into registers if needed */
7241         cinfo = cfg->arch.cinfo;
7242         if (cinfo->ret.storage == ArgValuetypeInReg) {
7243                 ArgInfo *ainfo = &cinfo->ret;
7244                 MonoInst *inst = cfg->ret;
7245
7246                 for (quad = 0; quad < 2; quad ++) {
7247                         switch (ainfo->pair_storage [quad]) {
7248                         case ArgInIReg:
7249                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7250                                 break;
7251                         case ArgInFloatSSEReg:
7252                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7253                                 break;
7254                         case ArgInDoubleSSEReg:
7255                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7256                                 break;
7257                         case ArgNone:
7258                                 break;
7259                         default:
7260                                 g_assert_not_reached ();
7261                         }
7262                 }
7263         }
7264
7265         if (cfg->arch.omit_fp) {
7266                 if (cfg->arch.stack_alloc_size) {
7267                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7268                 }
7269         } else {
7270                 amd64_leave (code);
7271                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7272         }
7273         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7274         async_exc_point (code);
7275         amd64_ret (code);
7276
7277         /* Restore the unwind state to be the same as before the epilog */
7278         mono_emit_unwind_op_restore_state (cfg, code);
7279
7280         cfg->code_len = code - cfg->native_code;
7281
7282         g_assert (cfg->code_len < cfg->code_size);
7283 }
7284
7285 void
7286 mono_arch_emit_exceptions (MonoCompile *cfg)
7287 {
7288         MonoJumpInfo *patch_info;
7289         int nthrows, i;
7290         guint8 *code;
7291         MonoClass *exc_classes [16];
7292         guint8 *exc_throw_start [16], *exc_throw_end [16];
7293         guint32 code_size = 0;
7294
7295         /* Compute needed space */
7296         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7297                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7298                         code_size += 40;
7299                 if (patch_info->type == MONO_PATCH_INFO_R8)
7300                         code_size += 8 + 15; /* sizeof (double) + alignment */
7301                 if (patch_info->type == MONO_PATCH_INFO_R4)
7302                         code_size += 4 + 15; /* sizeof (float) + alignment */
7303                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7304                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7305         }
7306
7307 #ifdef __native_client_codegen__
7308         /* Give us extra room on Native Client.  This could be   */
7309         /* more carefully calculated, but bundle alignment makes */
7310         /* it much trickier, so *2 like other places is good.    */
7311         code_size *= 2;
7312 #endif
7313
7314         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7315                 cfg->code_size *= 2;
7316                 cfg->native_code = mono_realloc_native_code (cfg);
7317                 cfg->stat_code_reallocs++;
7318         }
7319
7320         code = cfg->native_code + cfg->code_len;
7321
7322         /* add code to raise exceptions */
7323         nthrows = 0;
7324         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7325                 switch (patch_info->type) {
7326                 case MONO_PATCH_INFO_EXC: {
7327                         MonoClass *exc_class;
7328                         guint8 *buf, *buf2;
7329                         guint32 throw_ip;
7330
7331                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7332
7333                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7334                         g_assert (exc_class);
7335                         throw_ip = patch_info->ip.i;
7336
7337                         //x86_breakpoint (code);
7338                         /* Find a throw sequence for the same exception class */
7339                         for (i = 0; i < nthrows; ++i)
7340                                 if (exc_classes [i] == exc_class)
7341                                         break;
7342                         if (i < nthrows) {
7343                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7344                                 x86_jump_code (code, exc_throw_start [i]);
7345                                 patch_info->type = MONO_PATCH_INFO_NONE;
7346                         }
7347                         else {
7348                                 buf = code;
7349                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7350                                 buf2 = code;
7351
7352                                 if (nthrows < 16) {
7353                                         exc_classes [nthrows] = exc_class;
7354                                         exc_throw_start [nthrows] = code;
7355                                 }
7356                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7357
7358                                 patch_info->type = MONO_PATCH_INFO_NONE;
7359
7360                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7361
7362                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7363                                 while (buf < buf2)
7364                                         x86_nop (buf);
7365
7366                                 if (nthrows < 16) {
7367                                         exc_throw_end [nthrows] = code;
7368                                         nthrows ++;
7369                                 }
7370                         }
7371                         break;
7372                 }
7373                 default:
7374                         /* do nothing */
7375                         break;
7376                 }
7377                 g_assert(code < cfg->native_code + cfg->code_size);
7378         }
7379
7380         /* Handle relocations with RIP relative addressing */
7381         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7382                 gboolean remove = FALSE;
7383                 guint8 *orig_code = code;
7384
7385                 switch (patch_info->type) {
7386                 case MONO_PATCH_INFO_R8:
7387                 case MONO_PATCH_INFO_R4: {
7388                         guint8 *pos, *patch_pos;
7389                         guint32 target_pos;
7390
7391                         /* The SSE opcodes require a 16 byte alignment */
7392 #if defined(__default_codegen__)
7393                         code = (guint8*)ALIGN_TO (code, 16);
7394 #elif defined(__native_client_codegen__)
7395                         {
7396                                 /* Pad this out with HLT instructions  */
7397                                 /* or we can get garbage bytes emitted */
7398                                 /* which will fail validation          */
7399                                 guint8 *aligned_code;
7400                                 /* extra align to make room for  */
7401                                 /* mov/push below                      */
7402                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7403                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7404                                 /* The technique of hiding data in an  */
7405                                 /* instruction has a problem here: we  */
7406                                 /* need the data aligned to a 16-byte  */
7407                                 /* boundary but the instruction cannot */
7408                                 /* cross the bundle boundary. so only  */
7409                                 /* odd multiples of 16 can be used     */
7410                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7411                                         aligned_code += 16;
7412                                 }
7413                                 while (code < aligned_code) {
7414                                         *(code++) = 0xf4; /* hlt */
7415                                 }
7416                         }
7417 #endif
7418
7419                         pos = cfg->native_code + patch_info->ip.i;
7420                         if (IS_REX (pos [1])) {
7421                                 patch_pos = pos + 5;
7422                                 target_pos = code - pos - 9;
7423                         }
7424                         else {
7425                                 patch_pos = pos + 4;
7426                                 target_pos = code - pos - 8;
7427                         }
7428
7429                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7430 #ifdef __native_client_codegen__
7431                                 /* Hide 64-bit data in a         */
7432                                 /* "mov imm64, r11" instruction. */
7433                                 /* write it before the start of  */
7434                                 /* the data*/
7435                                 *(code-2) = 0x49; /* prefix      */
7436                                 *(code-1) = 0xbb; /* mov X, %r11 */
7437 #endif
7438                                 *(double*)code = *(double*)patch_info->data.target;
7439                                 code += sizeof (double);
7440                         } else {
7441 #ifdef __native_client_codegen__
7442                                 /* Hide 32-bit data in a        */
7443                                 /* "push imm32" instruction.    */
7444                                 *(code-1) = 0x68; /* push */
7445 #endif
7446                                 *(float*)code = *(float*)patch_info->data.target;
7447                                 code += sizeof (float);
7448                         }
7449
7450                         *(guint32*)(patch_pos) = target_pos;
7451
7452                         remove = TRUE;
7453                         break;
7454                 }
7455                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7456                         guint8 *pos;
7457
7458                         if (cfg->compile_aot)
7459                                 continue;
7460
7461                         /*loading is faster against aligned addresses.*/
7462                         code = (guint8*)ALIGN_TO (code, 8);
7463                         memset (orig_code, 0, code - orig_code);
7464
7465                         pos = cfg->native_code + patch_info->ip.i;
7466
7467                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7468                         if (IS_REX (pos [1]))
7469                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7470                         else
7471                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7472
7473                         *(gpointer*)code = (gpointer)patch_info->data.target;
7474                         code += sizeof (gpointer);
7475
7476                         remove = TRUE;
7477                         break;
7478                 }
7479                 default:
7480                         break;
7481                 }
7482
7483                 if (remove) {
7484                         if (patch_info == cfg->patch_info)
7485                                 cfg->patch_info = patch_info->next;
7486                         else {
7487                                 MonoJumpInfo *tmp;
7488
7489                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7490                                         ;
7491                                 tmp->next = patch_info->next;
7492                         }
7493                 }
7494                 g_assert (code < cfg->native_code + cfg->code_size);
7495         }
7496
7497         cfg->code_len = code - cfg->native_code;
7498
7499         g_assert (cfg->code_len < cfg->code_size);
7500
7501 }
7502
7503 #endif /* DISABLE_JIT */
7504
7505 void*
7506 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7507 {
7508         guchar *code = p;
7509         MonoMethodSignature *sig;
7510         MonoInst *inst;
7511         int i, n, stack_area = 0;
7512
7513         /* Keep this in sync with mono_arch_get_argument_info */
7514
7515         if (enable_arguments) {
7516                 /* Allocate a new area on the stack and save arguments there */
7517                 sig = mono_method_signature (cfg->method);
7518
7519                 n = sig->param_count + sig->hasthis;
7520
7521                 stack_area = ALIGN_TO (n * 8, 16);
7522
7523                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7524
7525                 for (i = 0; i < n; ++i) {
7526                         inst = cfg->args [i];
7527
7528                         if (inst->opcode == OP_REGVAR)
7529                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7530                         else {
7531                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7532                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7533                         }
7534                 }
7535         }
7536
7537         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7538         amd64_set_reg_template (code, AMD64_ARG_REG1);
7539         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7540         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7541
7542         if (enable_arguments)
7543                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7544
7545         return code;
7546 }
7547
7548 enum {
7549         SAVE_NONE,
7550         SAVE_STRUCT,
7551         SAVE_EAX,
7552         SAVE_EAX_EDX,
7553         SAVE_XMM
7554 };
7555
7556 void*
7557 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7558 {
7559         guchar *code = p;
7560         int save_mode = SAVE_NONE;
7561         MonoMethod *method = cfg->method;
7562         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7563         int i;
7564
7565         switch (ret_type->type) {
7566         case MONO_TYPE_VOID:
7567                 /* special case string .ctor icall */
7568                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7569                         save_mode = SAVE_EAX;
7570                 else
7571                         save_mode = SAVE_NONE;
7572                 break;
7573         case MONO_TYPE_I8:
7574         case MONO_TYPE_U8:
7575                 save_mode = SAVE_EAX;
7576                 break;
7577         case MONO_TYPE_R4:
7578         case MONO_TYPE_R8:
7579                 save_mode = SAVE_XMM;
7580                 break;
7581         case MONO_TYPE_GENERICINST:
7582                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7583                         save_mode = SAVE_EAX;
7584                         break;
7585                 }
7586                 /* Fall through */
7587         case MONO_TYPE_VALUETYPE:
7588                 save_mode = SAVE_STRUCT;
7589                 break;
7590         default:
7591                 save_mode = SAVE_EAX;
7592                 break;
7593         }
7594
7595         /* Save the result and copy it into the proper argument register */
7596         switch (save_mode) {
7597         case SAVE_EAX:
7598                 amd64_push_reg (code, AMD64_RAX);
7599                 /* Align stack */
7600                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7601                 if (enable_arguments)
7602                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7603                 break;
7604         case SAVE_STRUCT:
7605                 /* FIXME: */
7606                 if (enable_arguments)
7607                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7608                 break;
7609         case SAVE_XMM:
7610                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7611                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7612                 /* Align stack */
7613                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7614                 /*
7615                  * The result is already in the proper argument register so no copying
7616                  * needed.
7617                  */
7618                 break;
7619         case SAVE_NONE:
7620                 break;
7621         default:
7622                 g_assert_not_reached ();
7623         }
7624
7625         /* Set %al since this is a varargs call */
7626         if (save_mode == SAVE_XMM)
7627                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7628         else
7629                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7630
7631         if (preserve_argument_registers) {
7632                 for (i = 0; i < PARAM_REGS; ++i)
7633                         amd64_push_reg (code, param_regs [i]);
7634         }
7635
7636         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7637         amd64_set_reg_template (code, AMD64_ARG_REG1);
7638         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7639
7640         if (preserve_argument_registers) {
7641                 for (i = PARAM_REGS - 1; i >= 0; --i)
7642                         amd64_pop_reg (code, param_regs [i]);
7643         }
7644
7645         /* Restore result */
7646         switch (save_mode) {
7647         case SAVE_EAX:
7648                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7649                 amd64_pop_reg (code, AMD64_RAX);
7650                 break;
7651         case SAVE_STRUCT:
7652                 /* FIXME: */
7653                 break;
7654         case SAVE_XMM:
7655                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7656                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7657                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7658                 break;
7659         case SAVE_NONE:
7660                 break;
7661         default:
7662                 g_assert_not_reached ();
7663         }
7664
7665         return code;
7666 }
7667
7668 void
7669 mono_arch_flush_icache (guint8 *code, gint size)
7670 {
7671         /* Not needed */
7672 }
7673
7674 void
7675 mono_arch_flush_register_windows (void)
7676 {
7677 }
7678
7679 gboolean
7680 mono_arch_is_inst_imm (gint64 imm)
7681 {
7682         return amd64_is_imm32 (imm);
7683 }
7684
7685 /*
7686  * Determine whenever the trap whose info is in SIGINFO is caused by
7687  * integer overflow.
7688  */
7689 gboolean
7690 mono_arch_is_int_overflow (void *sigctx, void *info)
7691 {
7692         MonoContext ctx;
7693         guint8* rip;
7694         int reg;
7695         gint64 value;
7696
7697         mono_sigctx_to_monoctx (sigctx, &ctx);
7698
7699         rip = (guint8*)ctx.gregs [AMD64_RIP];
7700
7701         if (IS_REX (rip [0])) {
7702                 reg = amd64_rex_b (rip [0]);
7703                 rip ++;
7704         }
7705         else
7706                 reg = 0;
7707
7708         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7709                 /* idiv REG */
7710                 reg += x86_modrm_rm (rip [1]);
7711
7712                 value = ctx.gregs [reg];
7713
7714                 if (value == -1)
7715                         return TRUE;
7716         }
7717
7718         return FALSE;
7719 }
7720
7721 guint32
7722 mono_arch_get_patch_offset (guint8 *code)
7723 {
7724         return 3;
7725 }
7726
7727 /**
7728  * mono_breakpoint_clean_code:
7729  *
7730  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7731  * breakpoints in the original code, they are removed in the copy.
7732  *
7733  * Returns TRUE if no sw breakpoint was present.
7734  */
7735 gboolean
7736 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7737 {
7738         /*
7739          * If method_start is non-NULL we need to perform bound checks, since we access memory
7740          * at code - offset we could go before the start of the method and end up in a different
7741          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7742          * instead.
7743          */
7744         if (!method_start || code - offset >= method_start) {
7745                 memcpy (buf, code - offset, size);
7746         } else {
7747                 int diff = code - method_start;
7748                 memset (buf, 0, size);
7749                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7750         }
7751         return TRUE;
7752 }
7753
7754 #if defined(__native_client_codegen__)
7755 /* For membase calls, we want the base register. for Native Client,  */
7756 /* all indirect calls have the following sequence with the given sizes: */
7757 /* mov %eXX,%eXX                                [2-3]   */
7758 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7759 /* and $0xffffffffffffffe0,%r11d                [4]     */
7760 /* add %r15,%r11                                [3]     */
7761 /* callq *%r11                                  [3]     */
7762
7763
7764 /* Determine if code points to a NaCl call-through-register sequence, */
7765 /* (i.e., the last 3 instructions listed above) */
7766 int
7767 is_nacl_call_reg_sequence(guint8* code)
7768 {
7769         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7770                                "\x4d\x03\xdf"     /* add */
7771                                "\x41\xff\xd3";   /* call */
7772         return memcmp(code, sequence, 10) == 0;
7773 }
7774
7775 /* Determine if code points to the first opcode of the mov membase component */
7776 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7777 /* (there could be a REX prefix before the opcode but it is ignored) */
7778 static int
7779 is_nacl_indirect_call_membase_sequence(guint8* code)
7780 {
7781                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7782         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7783                /* and that src reg = dest reg */
7784                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7785                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7786                IS_REX(code[2]) &&
7787                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7788                /* and has dst of r11 and base of r15 */
7789                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7790                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7791 }
7792 #endif /* __native_client_codegen__ */
7793
7794 int
7795 mono_arch_get_this_arg_reg (guint8 *code)
7796 {
7797         return AMD64_ARG_REG1;
7798 }
7799
7800 gpointer
7801 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7802 {
7803         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7804 }
7805
7806 #define MAX_ARCH_DELEGATE_PARAMS 10
7807
7808 static gpointer
7809 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7810 {
7811         guint8 *code, *start;
7812         GSList *unwind_ops = NULL;
7813         int i;
7814
7815         unwind_ops = mono_arch_get_cie_program ();
7816
7817         if (has_target) {
7818                 start = code = mono_global_codeman_reserve (64);
7819
7820                 /* Replace the this argument with the target */
7821                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7822                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7823                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7824
7825                 g_assert ((code - start) < 64);
7826         } else {
7827                 start = code = mono_global_codeman_reserve (64);
7828
7829                 if (param_count == 0) {
7830                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7831                 } else {
7832                         /* We have to shift the arguments left */
7833                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7834                         for (i = 0; i < param_count; ++i) {
7835 #ifdef TARGET_WIN32
7836                                 if (i < 3)
7837                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7838                                 else
7839                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7840 #else
7841                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7842 #endif
7843                         }
7844
7845                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7846                 }
7847                 g_assert ((code - start) < 64);
7848         }
7849
7850         nacl_global_codeman_validate (&start, 64, &code);
7851         mono_arch_flush_icache (start, code - start);
7852
7853         if (has_target) {
7854                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7855         } else {
7856                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7857                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7858                 g_free (name);
7859         }
7860
7861         if (mono_jit_map_is_enabled ()) {
7862                 char *buff;
7863                 if (has_target)
7864                         buff = (char*)"delegate_invoke_has_target";
7865                 else
7866                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7867                 mono_emit_jit_tramp (start, code - start, buff);
7868                 if (!has_target)
7869                         g_free (buff);
7870         }
7871         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7872
7873         return start;
7874 }
7875
7876 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7877
7878 static gpointer
7879 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7880 {
7881         guint8 *code, *start;
7882         int size = 20;
7883         char *tramp_name;
7884         GSList *unwind_ops;
7885
7886         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7887                 return NULL;
7888
7889         start = code = mono_global_codeman_reserve (size);
7890
7891         unwind_ops = mono_arch_get_cie_program ();
7892
7893         /* Replace the this argument with the target */
7894         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7895         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7896
7897         if (load_imt_reg) {
7898                 /* Load the IMT reg */
7899                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7900         }
7901
7902         /* Load the vtable */
7903         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7904         amd64_jump_membase (code, AMD64_RAX, offset);
7905         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7906
7907         if (load_imt_reg)
7908                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7909         else
7910                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7911         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7912         g_free (tramp_name);
7913
7914         return start;
7915 }
7916
7917 /*
7918  * mono_arch_get_delegate_invoke_impls:
7919  *
7920  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7921  * trampolines.
7922  */
7923 GSList*
7924 mono_arch_get_delegate_invoke_impls (void)
7925 {
7926         GSList *res = NULL;
7927         MonoTrampInfo *info;
7928         int i;
7929
7930         get_delegate_invoke_impl (&info, TRUE, 0);
7931         res = g_slist_prepend (res, info);
7932
7933         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7934                 get_delegate_invoke_impl (&info, FALSE, i);
7935                 res = g_slist_prepend (res, info);
7936         }
7937
7938         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7939                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7940                 res = g_slist_prepend (res, info);
7941
7942                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7943                 res = g_slist_prepend (res, info);
7944         }
7945
7946         return res;
7947 }
7948
7949 gpointer
7950 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7951 {
7952         guint8 *code, *start;
7953         int i;
7954
7955         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7956                 return NULL;
7957
7958         /* FIXME: Support more cases */
7959         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7960                 return NULL;
7961
7962         if (has_target) {
7963                 static guint8* cached = NULL;
7964
7965                 if (cached)
7966                         return cached;
7967
7968                 if (mono_aot_only) {
7969                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7970                 } else {
7971                         MonoTrampInfo *info;
7972                         start = get_delegate_invoke_impl (&info, TRUE, 0);
7973                         mono_tramp_info_register (info, NULL);
7974                 }
7975
7976                 mono_memory_barrier ();
7977
7978                 cached = start;
7979         } else {
7980                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7981                 for (i = 0; i < sig->param_count; ++i)
7982                         if (!mono_is_regsize_var (sig->params [i]))
7983                                 return NULL;
7984                 if (sig->param_count > 4)
7985                         return NULL;
7986
7987                 code = cache [sig->param_count];
7988                 if (code)
7989                         return code;
7990
7991                 if (mono_aot_only) {
7992                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7993                         start = mono_aot_get_trampoline (name);
7994                         g_free (name);
7995                 } else {
7996                         MonoTrampInfo *info;
7997                         start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7998                         mono_tramp_info_register (info, NULL);
7999                 }
8000
8001                 mono_memory_barrier ();
8002
8003                 cache [sig->param_count] = start;
8004         }
8005
8006         return start;
8007 }
8008
8009 gpointer
8010 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8011 {
8012         MonoTrampInfo *info;
8013         gpointer code;
8014
8015         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8016         if (code)
8017                 mono_tramp_info_register (info, NULL);
8018         return code;
8019 }
8020
8021 void
8022 mono_arch_finish_init (void)
8023 {
8024 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8025         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8026 #endif
8027 }
8028
8029 void
8030 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8031 {
8032 }
8033
8034 #if defined(__default_codegen__)
8035 #define CMP_SIZE (6 + 1)
8036 #define CMP_REG_REG_SIZE (4 + 1)
8037 #define BR_SMALL_SIZE 2
8038 #define BR_LARGE_SIZE 6
8039 #define MOV_REG_IMM_SIZE 10
8040 #define MOV_REG_IMM_32BIT_SIZE 6
8041 #define JUMP_REG_SIZE (2 + 1)
8042 #elif defined(__native_client_codegen__)
8043 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8044 #define CMP_SIZE ((6 + 1) * 2 - 1)
8045 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8046 #define BR_SMALL_SIZE (2 * 2 - 1)
8047 #define BR_LARGE_SIZE (6 * 2 - 1)
8048 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8049 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8050 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8051 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8052 /* Jump membase's size is large and unpredictable    */
8053 /* in native client, just pad it out a whole bundle. */
8054 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8055 #endif
8056
8057 static int
8058 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8059 {
8060         int i, distance = 0;
8061         for (i = start; i < target; ++i)
8062                 distance += imt_entries [i]->chunk_size;
8063         return distance;
8064 }
8065
8066 /*
8067  * LOCKING: called with the domain lock held
8068  */
8069 gpointer
8070 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8071         gpointer fail_tramp)
8072 {
8073         int i;
8074         int size = 0;
8075         guint8 *code, *start;
8076         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8077         GSList *unwind_ops;
8078
8079         for (i = 0; i < count; ++i) {
8080                 MonoIMTCheckItem *item = imt_entries [i];
8081                 if (item->is_equals) {
8082                         if (item->check_target_idx) {
8083                                 if (!item->compare_done) {
8084                                         if (amd64_is_imm32 (item->key))
8085                                                 item->chunk_size += CMP_SIZE;
8086                                         else
8087                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8088                                 }
8089                                 if (item->has_target_code) {
8090                                         item->chunk_size += MOV_REG_IMM_SIZE;
8091                                 } else {
8092                                         if (vtable_is_32bit)
8093                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8094                                         else
8095                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8096 #ifdef __native_client_codegen__
8097                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8098 #endif
8099                                 }
8100                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8101                         } else {
8102                                 if (fail_tramp) {
8103                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8104                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8105                                 } else {
8106                                         if (vtable_is_32bit)
8107                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8108                                         else
8109                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8110                                         item->chunk_size += JUMP_REG_SIZE;
8111                                         /* with assert below:
8112                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8113                                          */
8114 #ifdef __native_client_codegen__
8115                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8116 #endif
8117                                 }
8118                         }
8119                 } else {
8120                         if (amd64_is_imm32 (item->key))
8121                                 item->chunk_size += CMP_SIZE;
8122                         else
8123                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8124                         item->chunk_size += BR_LARGE_SIZE;
8125                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8126                 }
8127                 size += item->chunk_size;
8128         }
8129 #if defined(__native_client__) && defined(__native_client_codegen__)
8130         /* In Native Client, we don't re-use thunks, allocate from the */
8131         /* normal code manager paths. */
8132         code = mono_domain_code_reserve (domain, size);
8133 #else
8134         if (fail_tramp)
8135                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8136         else
8137                 code = mono_domain_code_reserve (domain, size);
8138 #endif
8139         start = code;
8140
8141         unwind_ops = mono_arch_get_cie_program ();
8142
8143         for (i = 0; i < count; ++i) {
8144                 MonoIMTCheckItem *item = imt_entries [i];
8145                 item->code_target = code;
8146                 if (item->is_equals) {
8147                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8148
8149                         if (item->check_target_idx || fail_case) {
8150                                 if (!item->compare_done || fail_case) {
8151                                         if (amd64_is_imm32 (item->key))
8152                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8153                                         else {
8154                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8155                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8156                                         }
8157                                 }
8158                                 item->jmp_code = code;
8159                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8160                                 if (item->has_target_code) {
8161                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8162                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8163                                 } else {
8164                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8165                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8166                                 }
8167
8168                                 if (fail_case) {
8169                                         amd64_patch (item->jmp_code, code);
8170                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8171                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8172                                         item->jmp_code = NULL;
8173                                 }
8174                         } else {
8175                                 /* enable the commented code to assert on wrong method */
8176 #if 0
8177                                 if (amd64_is_imm32 (item->key))
8178                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8179                                 else {
8180                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8181                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8182                                 }
8183                                 item->jmp_code = code;
8184                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8185                                 /* See the comment below about R10 */
8186                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8187                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8188                                 amd64_patch (item->jmp_code, code);
8189                                 amd64_breakpoint (code);
8190                                 item->jmp_code = NULL;
8191 #else
8192                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8193                                    needs to be preserved.  R10 needs
8194                                    to be preserved for calls which
8195                                    require a runtime generic context,
8196                                    but interface calls don't. */
8197                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8198                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8199 #endif
8200                         }
8201                 } else {
8202                         if (amd64_is_imm32 (item->key))
8203                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8204                         else {
8205                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8206                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8207                         }
8208                         item->jmp_code = code;
8209                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8210                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8211                         else
8212                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8213                 }
8214                 g_assert (code - item->code_target <= item->chunk_size);
8215         }
8216         /* patch the branches to get to the target items */
8217         for (i = 0; i < count; ++i) {
8218                 MonoIMTCheckItem *item = imt_entries [i];
8219                 if (item->jmp_code) {
8220                         if (item->check_target_idx) {
8221                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8222                         }
8223                 }
8224         }
8225
8226         if (!fail_tramp)
8227                 mono_stats.imt_thunks_size += code - start;
8228         g_assert (code - start <= size);
8229
8230         nacl_domain_code_validate(domain, &start, size, &code);
8231         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8232
8233         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8234
8235         return start;
8236 }
8237
8238 MonoMethod*
8239 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8240 {
8241         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8242 }
8243
8244 MonoVTable*
8245 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8246 {
8247         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8248 }
8249
8250 GSList*
8251 mono_arch_get_cie_program (void)
8252 {
8253         GSList *l = NULL;
8254
8255         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8256         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8257
8258         return l;
8259 }
8260
8261 #ifndef DISABLE_JIT
8262
8263 MonoInst*
8264 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8265 {
8266         MonoInst *ins = NULL;
8267         int opcode = 0;
8268
8269         if (cmethod->klass == mono_defaults.math_class) {
8270                 if (strcmp (cmethod->name, "Sin") == 0) {
8271                         opcode = OP_SIN;
8272                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8273                         opcode = OP_COS;
8274                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8275                         opcode = OP_SQRT;
8276                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8277                         opcode = OP_ABS;
8278                 }
8279
8280                 if (opcode && fsig->param_count == 1) {
8281                         MONO_INST_NEW (cfg, ins, opcode);
8282                         ins->type = STACK_R8;
8283                         ins->dreg = mono_alloc_freg (cfg);
8284                         ins->sreg1 = args [0]->dreg;
8285                         MONO_ADD_INS (cfg->cbb, ins);
8286                 }
8287
8288                 opcode = 0;
8289                 if (cfg->opt & MONO_OPT_CMOV) {
8290                         if (strcmp (cmethod->name, "Min") == 0) {
8291                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8292                                         opcode = OP_IMIN;
8293                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8294                                         opcode = OP_IMIN_UN;
8295                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8296                                         opcode = OP_LMIN;
8297                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8298                                         opcode = OP_LMIN_UN;
8299                         } else if (strcmp (cmethod->name, "Max") == 0) {
8300                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8301                                         opcode = OP_IMAX;
8302                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8303                                         opcode = OP_IMAX_UN;
8304                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8305                                         opcode = OP_LMAX;
8306                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8307                                         opcode = OP_LMAX_UN;
8308                         }
8309                 }
8310
8311                 if (opcode && fsig->param_count == 2) {
8312                         MONO_INST_NEW (cfg, ins, opcode);
8313                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8314                         ins->dreg = mono_alloc_ireg (cfg);
8315                         ins->sreg1 = args [0]->dreg;
8316                         ins->sreg2 = args [1]->dreg;
8317                         MONO_ADD_INS (cfg->cbb, ins);
8318                 }
8319
8320 #if 0
8321                 /* OP_FREM is not IEEE compatible */
8322                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8323                         MONO_INST_NEW (cfg, ins, OP_FREM);
8324                         ins->inst_i0 = args [0];
8325                         ins->inst_i1 = args [1];
8326                 }
8327 #endif
8328         }
8329
8330         return ins;
8331 }
8332 #endif
8333
8334 gboolean
8335 mono_arch_print_tree (MonoInst *tree, int arity)
8336 {
8337         return 0;
8338 }
8339
8340 mgreg_t
8341 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8342 {
8343         return ctx->gregs [reg];
8344 }
8345
8346 void
8347 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8348 {
8349         ctx->gregs [reg] = val;
8350 }
8351
8352 gpointer
8353 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8354 {
8355         gpointer *sp, old_value;
8356         char *bp;
8357
8358         /*Load the spvar*/
8359         bp = MONO_CONTEXT_GET_BP (ctx);
8360         sp = *(gpointer*)(bp + clause->exvar_offset);
8361
8362         old_value = *sp;
8363         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8364                 return old_value;
8365
8366         *sp = new_value;
8367
8368         return old_value;
8369 }
8370
8371 /*
8372  * mono_arch_emit_load_aotconst:
8373  *
8374  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8375  * TARGET from the mscorlib GOT in full-aot code.
8376  * On AMD64, the result is placed into R11.
8377  */
8378 guint8*
8379 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8380 {
8381         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8382         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8383
8384         return code;
8385 }
8386
8387 /*
8388  * mono_arch_get_trampolines:
8389  *
8390  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8391  * for AOT.
8392  */
8393 GSList *
8394 mono_arch_get_trampolines (gboolean aot)
8395 {
8396         return mono_amd64_get_exception_trampolines (aot);
8397 }
8398
8399 /* Soft Debug support */
8400 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8401
8402 /*
8403  * mono_arch_set_breakpoint:
8404  *
8405  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8406  * The location should contain code emitted by OP_SEQ_POINT.
8407  */
8408 void
8409 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8410 {
8411         guint8 *code = ip;
8412         guint8 *orig_code = code;
8413
8414         if (ji->from_aot) {
8415                 guint32 native_offset = ip - (guint8*)ji->code_start;
8416                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8417
8418                 g_assert (info->bp_addrs [native_offset] == 0);
8419                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8420         } else {
8421                 /*
8422                  * In production, we will use int3 (has to fix the size in the md
8423                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8424                  * instead.
8425                  */
8426                 g_assert (code [0] == 0x90);
8427                 if (breakpoint_size == 8) {
8428                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8429                 } else {
8430                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8431                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8432                 }
8433
8434                 g_assert (code - orig_code == breakpoint_size);
8435         }
8436 }
8437
8438 /*
8439  * mono_arch_clear_breakpoint:
8440  *
8441  *   Clear the breakpoint at IP.
8442  */
8443 void
8444 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8445 {
8446         guint8 *code = ip;
8447         int i;
8448
8449         if (ji->from_aot) {
8450                 guint32 native_offset = ip - (guint8*)ji->code_start;
8451                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8452
8453                 info->bp_addrs [native_offset] = NULL;
8454         } else {
8455                 for (i = 0; i < breakpoint_size; ++i)
8456                         x86_nop (code);
8457         }
8458 }
8459
8460 gboolean
8461 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8462 {
8463 #ifdef HOST_WIN32
8464         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8465         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8466                 return TRUE;
8467         else
8468                 return FALSE;
8469 #else
8470         siginfo_t* sinfo = (siginfo_t*) info;
8471         /* Sometimes the address is off by 4 */
8472         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8473                 return TRUE;
8474         else
8475                 return FALSE;
8476 #endif
8477 }
8478
8479 /*
8480  * mono_arch_skip_breakpoint:
8481  *
8482  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8483  * we resume, the instruction is not executed again.
8484  */
8485 void
8486 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8487 {
8488         if (ji->from_aot) {
8489                 /* The breakpoint instruction is a call */
8490         } else {
8491                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8492         }
8493 }
8494
8495 /*
8496  * mono_arch_start_single_stepping:
8497  *
8498  *   Start single stepping.
8499  */
8500 void
8501 mono_arch_start_single_stepping (void)
8502 {
8503         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8504         ss_trampoline = mini_get_single_step_trampoline ();
8505 }
8506
8507 /*
8508  * mono_arch_stop_single_stepping:
8509  *
8510  *   Stop single stepping.
8511  */
8512 void
8513 mono_arch_stop_single_stepping (void)
8514 {
8515         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8516         ss_trampoline = NULL;
8517 }
8518
8519 /*
8520  * mono_arch_is_single_step_event:
8521  *
8522  *   Return whenever the machine state in SIGCTX corresponds to a single
8523  * step event.
8524  */
8525 gboolean
8526 mono_arch_is_single_step_event (void *info, void *sigctx)
8527 {
8528 #ifdef HOST_WIN32
8529         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8530         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8531                 return TRUE;
8532         else
8533                 return FALSE;
8534 #else
8535         siginfo_t* sinfo = (siginfo_t*) info;
8536         /* Sometimes the address is off by 4 */
8537         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8538                 return TRUE;
8539         else
8540                 return FALSE;
8541 #endif
8542 }
8543
8544 /*
8545  * mono_arch_skip_single_step:
8546  *
8547  *   Modify CTX so the ip is placed after the single step trigger instruction,
8548  * we resume, the instruction is not executed again.
8549  */
8550 void
8551 mono_arch_skip_single_step (MonoContext *ctx)
8552 {
8553         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8554 }
8555
8556 /*
8557  * mono_arch_create_seq_point_info:
8558  *
8559  *   Return a pointer to a data structure which is used by the sequence
8560  * point implementation in AOTed code.
8561  */
8562 gpointer
8563 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8564 {
8565         SeqPointInfo *info;
8566         MonoJitInfo *ji;
8567
8568         // FIXME: Add a free function
8569
8570         mono_domain_lock (domain);
8571         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8572                                                                 code);
8573         mono_domain_unlock (domain);
8574
8575         if (!info) {
8576                 ji = mono_jit_info_table_find (domain, (char*)code);
8577                 g_assert (ji);
8578
8579                 // FIXME: Optimize the size
8580                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8581
8582                 info->ss_tramp_addr = &ss_trampoline;
8583
8584                 mono_domain_lock (domain);
8585                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8586                                                          code, info);
8587                 mono_domain_unlock (domain);
8588         }
8589
8590         return info;
8591 }
8592
8593 void
8594 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8595 {
8596         ext->lmf.previous_lmf = prev_lmf;
8597         /* Mark that this is a MonoLMFExt */
8598         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8599         ext->lmf.rsp = (gssize)ext;
8600 }
8601
8602 #endif
8603
8604 gboolean
8605 mono_arch_opcode_supported (int opcode)
8606 {
8607         switch (opcode) {
8608         case OP_ATOMIC_ADD_I4:
8609         case OP_ATOMIC_ADD_I8:
8610         case OP_ATOMIC_EXCHANGE_I4:
8611         case OP_ATOMIC_EXCHANGE_I8:
8612         case OP_ATOMIC_CAS_I4:
8613         case OP_ATOMIC_CAS_I8:
8614         case OP_ATOMIC_LOAD_I1:
8615         case OP_ATOMIC_LOAD_I2:
8616         case OP_ATOMIC_LOAD_I4:
8617         case OP_ATOMIC_LOAD_I8:
8618         case OP_ATOMIC_LOAD_U1:
8619         case OP_ATOMIC_LOAD_U2:
8620         case OP_ATOMIC_LOAD_U4:
8621         case OP_ATOMIC_LOAD_U8:
8622         case OP_ATOMIC_LOAD_R4:
8623         case OP_ATOMIC_LOAD_R8:
8624         case OP_ATOMIC_STORE_I1:
8625         case OP_ATOMIC_STORE_I2:
8626         case OP_ATOMIC_STORE_I4:
8627         case OP_ATOMIC_STORE_I8:
8628         case OP_ATOMIC_STORE_U1:
8629         case OP_ATOMIC_STORE_U2:
8630         case OP_ATOMIC_STORE_U4:
8631         case OP_ATOMIC_STORE_U8:
8632         case OP_ATOMIC_STORE_R4:
8633         case OP_ATOMIC_STORE_R8:
8634                 return TRUE;
8635         default:
8636                 return FALSE;
8637         }
8638 }