mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /*
  69  * The code generated for sequence points reads from this location, which is
  70  * made read-only when single stepping is enabled.
  71  */
  72 static gpointer ss_trigger_page;
  73
  74 /* Enabled breakpoints read from this trigger page */
  75 static gpointer bp_trigger_page;
  76
  77 /* The size of the breakpoint sequence */
  78 static int breakpoint_size;
  79
  80 /* The size of the breakpoint instruction causing the actual fault */
  81 static int breakpoint_fault_size;
  82
  83 /* The size of the single step instruction causing the actual fault */
  84 static int single_step_fault_size;
  85
  86 /* The single step trampoline */
  87 static gpointer ss_trampoline;
  88
  89 /* Offset between fp and the first argument in the callee */
  90 #define ARGS_OFFSET 16
  91 #define GP_SCRATCH_REG AMD64_R11
  92
  93 /*
  94  * AMD64 register usage:
  95  * - callee saved registers are used for global register allocation
  96  * - %r11 is used for materializing 64 bit constants in opcodes
  97  * - the rest is used for local allocation
  98  */
  99
 100 /*
 101  * Floating point comparison results:
 102  *                  ZF PF CF
 103  * A > B            0  0  0
 104  * A < B            0  0  1
 105  * A = B            1  0  0
 106  * A > B            0  0  0
 107  * UNORDERED        1  1  1
 108  */
 109
 110 const char*
 111 mono_arch_regname (int reg)
 112 {
 113         switch (reg) {
 114         case AMD64_RAX: return "%rax";
 115         case AMD64_RBX: return "%rbx";
 116         case AMD64_RCX: return "%rcx";
 117         case AMD64_RDX: return "%rdx";
 118         case AMD64_RSP: return "%rsp";
 119         case AMD64_RBP: return "%rbp";
 120         case AMD64_RDI: return "%rdi";
 121         case AMD64_RSI: return "%rsi";
 122         case AMD64_R8: return "%r8";
 123         case AMD64_R9: return "%r9";
 124         case AMD64_R10: return "%r10";
 125         case AMD64_R11: return "%r11";
 126         case AMD64_R12: return "%r12";
 127         case AMD64_R13: return "%r13";
 128         case AMD64_R14: return "%r14";
 129         case AMD64_R15: return "%r15";
 130         }
 131         return "unknown";
 132 }
 133
 134 static const char * packed_xmmregs [] = {
 135         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 136         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 137 };
 138
 139 static const char * single_xmmregs [] = {
 140         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 141         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 142 };
 143
 144 const char*
 145 mono_arch_fregname (int reg)
 146 {
 147         if (reg < AMD64_XMM_NREG)
 148                 return single_xmmregs [reg];
 149         else
 150                 return "unknown";
 151 }
 152
 153 const char *
 154 mono_arch_xregname (int reg)
 155 {
 156         if (reg < AMD64_XMM_NREG)
 157                 return packed_xmmregs [reg];
 158         else
 159                 return "unknown";
 160 }
 161
 162 static gboolean
 163 debug_omit_fp (void)
 164 {
 165 #if 0
 166         return mono_debug_count ();
 167 #else
 168         return TRUE;
 169 #endif
 170 }
 171
 172 static inline gboolean
 173 amd64_is_near_call (guint8 *code)
 174 {
 175         /* Skip REX */
 176         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 177                 code += 1;
 178
 179         return code [0] == 0xe8;
 180 }
 181
 182 static inline gboolean
 183 amd64_use_imm32 (gint64 val)
 184 {
 185         if (mini_get_debug_options()->single_imm_size)
 186                 return FALSE;
 187
 188         return amd64_is_imm32 (val);
 189 }
 190
 191 #ifdef __native_client_codegen__
 192
 193 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 194 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 195 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 196 /* We only want to force bundle alignment for the top level instruction,    */
 197 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 198 static MonoNativeTlsKey nacl_instruction_depth;
 199
 200 static MonoNativeTlsKey nacl_rex_tag;
 201 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 202
 203 void
 204 amd64_nacl_clear_legacy_prefix_tag ()
 205 {
 206         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 207 }
 208
 209 void
 210 amd64_nacl_tag_legacy_prefix (guint8* code)
 211 {
 212         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 213                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 214 }
 215
 216 void
 217 amd64_nacl_tag_rex (guint8* code)
 218 {
 219         mono_native_tls_set_value (nacl_rex_tag, code);
 220 }
 221
 222 guint8*
 223 amd64_nacl_get_legacy_prefix_tag ()
 224 {
 225         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 226 }
 227
 228 guint8*
 229 amd64_nacl_get_rex_tag ()
 230 {
 231         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 232 }
 233
 234 /* Increment the instruction "depth" described above */
 235 void
 236 amd64_nacl_instruction_pre ()
 237 {
 238         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 239         depth++;
 240         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 241 }
 242
 243 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 244 /* alignment if depth == 0 (top level instruction)                          */
 245 /* IN: start, end    pointers to instruction beginning and end              */
 246 /* OUT: start, end   pointers to beginning and end after possible alignment */
 247 /* GLOBALS: nacl_instruction_depth     defined above                        */
 248 void
 249 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 250 {
 251         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 252         depth--;
 253         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 254
 255         g_assert ( depth >= 0 );
 256         if (depth == 0) {
 257                 uintptr_t space_in_block;
 258                 uintptr_t instlen;
 259                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 260                 /* if legacy prefix is present, and if it was emitted before */
 261                 /* the start of the instruction sequence, adjust the start   */
 262                 if (prefix != NULL && prefix < *start) {
 263                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 264                         *start = prefix;
 265                 }
 266                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 267                 instlen = (uintptr_t)(*end - *start);
 268                 /* Only check for instructions which are less than        */
 269                 /* kNaClAlignment. The only instructions that should ever */
 270                 /* be that long are call sequences, which are already     */
 271                 /* padded out to align the return to the next bundle.     */
 272                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 273                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 274                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 275                         const size_t length = (size_t)((*end)-(*start));
 276                         g_assert (length < MAX_NACL_INST_LENGTH);
 277
 278                         memcpy (copy_of_instruction, *start, length);
 279                         *start = mono_arch_nacl_pad (*start, space_in_block);
 280                         memcpy (*start, copy_of_instruction, length);
 281                         *end = *start + length;
 282                 }
 283                 amd64_nacl_clear_legacy_prefix_tag ();
 284                 amd64_nacl_tag_rex (NULL);
 285         }
 286 }
 287
 288 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 289 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 290 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 291 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 292 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 293 /* IN:      code                                                            */
 294 /*             pointer to current instruction stream (in the                */
 295 /*             middle of an instruction, after opcode is emitted)           */
 296 /*          basereg/offset/dreg                                             */
 297 /*             operands of normal membase address                           */
 298 /* OUT:     code                                                            */
 299 /*             pointer to the end of the membase/memindex emit              */
 300 /* GLOBALS: nacl_rex_tag                                                    */
 301 /*             position in instruction stream that rex prefix was emitted   */
 302 /*          nacl_legacy_prefix_tag                                          */
 303 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 304 void
 305 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 306 {
 307         gint8 true_basereg = basereg;
 308
 309         /* Cache these values, they might change  */
 310         /* as new instructions are emitted below. */
 311         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 312         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 313
 314         /* 'basereg' is given masked to 0x7 at this point, so check */
 315         /* the rex prefix to see if this is an extended register.   */
 316         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 317                 true_basereg |= 0x8;
 318         }
 319
 320 #define X86_LEA_OPCODE (0x8D)
 321
 322         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 323                 guint8* old_instruction_start;
 324
 325                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 326                 /* 32-bits of the old base register (new index register)     */
 327                 guint8 buf[32];
 328                 guint8* buf_ptr = buf;
 329                 size_t insert_len;
 330
 331                 g_assert (rex_tag != NULL);
 332
 333                 if (IS_REX(*rex_tag)) {
 334                         /* The old rex.B should be the new rex.X */
 335                         if (*rex_tag & AMD64_REX_B) {
 336                                 *rex_tag |= AMD64_REX_X;
 337                         }
 338                         /* Since our new base is %r15 set rex.B */
 339                         *rex_tag |= AMD64_REX_B;
 340                 } else {
 341                         /* Shift the instruction by one byte  */
 342                         /* so we can insert a rex prefix      */
 343                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 344                         *code += 1;
 345                         /* New rex prefix only needs rex.B for %r15 base */
 346                         *rex_tag = AMD64_REX(AMD64_REX_B);
 347                 }
 348
 349                 if (legacy_prefix_tag) {
 350                         old_instruction_start = legacy_prefix_tag;
 351                 } else {
 352                         old_instruction_start = rex_tag;
 353                 }
 354
 355                 /* Clears the upper 32-bits of the previous base register */
 356                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 357                 insert_len = buf_ptr - buf;
 358
 359                 /* Move the old instruction forward to make */
 360                 /* room for 'mov' stored in 'buf_ptr'       */
 361                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 362                 *code += insert_len;
 363                 memcpy (old_instruction_start, buf, insert_len);
 364
 365                 /* Sandboxed replacement for the normal membase_emit */
 366                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 367
 368         } else {
 369                 /* Normal default behavior, emit membase memory location */
 370                 x86_membase_emit_body (*code, dreg, basereg, offset);
 371         }
 372 }
 373
 374
 375 static inline unsigned char*
 376 amd64_skip_nops (unsigned char* code)
 377 {
 378         guint8 in_nop;
 379         do {
 380                 in_nop = 0;
 381                 if (   code[0] == 0x90) {
 382                         in_nop = 1;
 383                         code += 1;
 384                 }
 385                 if (   code[0] == 0x66 && code[1] == 0x90) {
 386                         in_nop = 1;
 387                         code += 2;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x00) {
 391                         in_nop = 1;
 392                         code += 3;
 393                 }
 394                 if (code[0] == 0x0f && code[1] == 0x1f
 395                  && code[2] == 0x40 && code[3] == 0x00) {
 396                         in_nop = 1;
 397                         code += 4;
 398                 }
 399                 if (code[0] == 0x0f && code[1] == 0x1f
 400                  && code[2] == 0x44 && code[3] == 0x00
 401                  && code[4] == 0x00) {
 402                         in_nop = 1;
 403                         code += 5;
 404                 }
 405                 if (code[0] == 0x66 && code[1] == 0x0f
 406                  && code[2] == 0x1f && code[3] == 0x44
 407                  && code[4] == 0x00 && code[5] == 0x00) {
 408                         in_nop = 1;
 409                         code += 6;
 410                 }
 411                 if (code[0] == 0x0f && code[1] == 0x1f
 412                  && code[2] == 0x80 && code[3] == 0x00
 413                  && code[4] == 0x00 && code[5] == 0x00
 414                  && code[6] == 0x00) {
 415                         in_nop = 1;
 416                         code += 7;
 417                 }
 418                 if (code[0] == 0x0f && code[1] == 0x1f
 419                  && code[2] == 0x84 && code[3] == 0x00
 420                  && code[4] == 0x00 && code[5] == 0x00
 421                  && code[6] == 0x00 && code[7] == 0x00) {
 422                         in_nop = 1;
 423                         code += 8;
 424                 }
 425         } while ( in_nop );
 426         return code;
 427 }
 428
 429 guint8*
 430 mono_arch_nacl_skip_nops (guint8* code)
 431 {
 432   return amd64_skip_nops(code);
 433 }
 434
 435 #endif /*__native_client_codegen__*/
 436
 437 static inline void
 438 amd64_patch (unsigned char* code, gpointer target)
 439 {
 440         guint8 rex = 0;
 441
 442 #ifdef __native_client_codegen__
 443         code = amd64_skip_nops (code);
 444 #endif
 445 #if defined(__native_client_codegen__) && defined(__native_client__)
 446         if (nacl_is_code_address (code)) {
 447                 /* For tail calls, code is patched after being installed */
 448                 /* but not through the normal "patch callsite" method.   */
 449                 unsigned char buf[kNaClAlignment];
 450                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 451                 int ret;
 452                 memcpy (buf, aligned_code, kNaClAlignment);
 453                 /* Patch a temp buffer of bundle size, */
 454                 /* then install to actual location.    */
 455                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 456                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 457                 g_assert (ret == 0);
 458                 return;
 459         }
 460         target = nacl_modify_patch_target (target);
 461 #endif
 462
 463         /* Skip REX */
 464         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 465                 rex = code [0];
 466                 code += 1;
 467         }
 468
 469         if ((code [0] & 0xf8) == 0xb8) {
 470                 /* amd64_set_reg_template */
 471                 *(guint64*)(code + 1) = (guint64)target;
 472         }
 473         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 474                 /* mov 0(%rip), %dreg */
 475                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 476         }
 477         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 478                 /* call *<OFFSET>(%rip) */
 479                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 480         }
 481         else if (code [0] == 0xe8) {
 482                 /* call <DISP> */
 483                 gint64 disp = (guint8*)target - (guint8*)code;
 484                 g_assert (amd64_is_imm32 (disp));
 485                 x86_patch (code, (unsigned char*)target);
 486         }
 487         else
 488                 x86_patch (code, (unsigned char*)target);
 489 }
 490
 491 void
 492 mono_amd64_patch (unsigned char* code, gpointer target)
 493 {
 494         amd64_patch (code, target);
 495 }
 496
 497 typedef enum {
 498         ArgInIReg,
 499         ArgInFloatSSEReg,
 500         ArgInDoubleSSEReg,
 501         ArgOnStack,
 502         ArgValuetypeInReg,
 503         ArgValuetypeAddrInIReg,
 504         ArgNone /* only in pair_storage */
 505 } ArgStorage;
 506
 507 typedef struct {
 508         gint16 offset;
 509         gint8  reg;
 510         ArgStorage storage;
 511
 512         /* Only if storage == ArgValuetypeInReg */
 513         ArgStorage pair_storage [2];
 514         gint8 pair_regs [2];
 515         /* The size of each pair */
 516         int pair_size [2];
 517         int nregs;
 518 } ArgInfo;
 519
 520 typedef struct {
 521         int nargs;
 522         guint32 stack_usage;
 523         guint32 reg_usage;
 524         guint32 freg_usage;
 525         gboolean need_stack_align;
 526         gboolean vtype_retaddr;
 527         /* The index of the vret arg in the argument list */
 528         int vret_arg_index;
 529         ArgInfo ret;
 530         ArgInfo sig_cookie;
 531         ArgInfo args [1];
 532 } CallInfo;
 533
 534 #define DEBUG(a) if (cfg->verbose_level > 1) a
 535
 536 #ifdef TARGET_WIN32
 537 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 538
 539 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 540 #else
 541 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 542
 543  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 544 #endif
 545
 546 static void inline
 547 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 548 {
 549     ainfo->offset = *stack_size;
 550
 551     if (*gr >= PARAM_REGS) {
 552                 ainfo->storage = ArgOnStack;
 553                 /* Since the same stack slot size is used for all arg */
 554                 /*  types, it needs to be big enough to hold them all */
 555                 (*stack_size) += sizeof(mgreg_t);
 556     }
 557     else {
 558                 ainfo->storage = ArgInIReg;
 559                 ainfo->reg = param_regs [*gr];
 560                 (*gr) ++;
 561     }
 562 }
 563
 564 #ifdef TARGET_WIN32
 565 #define FLOAT_PARAM_REGS 4
 566 #else
 567 #define FLOAT_PARAM_REGS 8
 568 #endif
 569
 570 static void inline
 571 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 572 {
 573     ainfo->offset = *stack_size;
 574
 575     if (*gr >= FLOAT_PARAM_REGS) {
 576                 ainfo->storage = ArgOnStack;
 577                 /* Since the same stack slot size is used for both float */
 578                 /*  types, it needs to be big enough to hold them both */
 579                 (*stack_size) += sizeof(mgreg_t);
 580     }
 581     else {
 582                 /* A double register */
 583                 if (is_double)
 584                         ainfo->storage = ArgInDoubleSSEReg;
 585                 else
 586                         ainfo->storage = ArgInFloatSSEReg;
 587                 ainfo->reg = *gr;
 588                 (*gr) += 1;
 589     }
 590 }
 591
 592 typedef enum ArgumentClass {
 593         ARG_CLASS_NO_CLASS,
 594         ARG_CLASS_MEMORY,
 595         ARG_CLASS_INTEGER,
 596         ARG_CLASS_SSE
 597 } ArgumentClass;
 598
 599 static ArgumentClass
 600 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 601 {
 602         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 603         MonoType *ptype;
 604
 605         ptype = mini_get_underlying_type (type);
 606         switch (ptype->type) {
 607         case MONO_TYPE_I1:
 608         case MONO_TYPE_U1:
 609         case MONO_TYPE_I2:
 610         case MONO_TYPE_U2:
 611         case MONO_TYPE_I4:
 612         case MONO_TYPE_U4:
 613         case MONO_TYPE_I:
 614         case MONO_TYPE_U:
 615         case MONO_TYPE_STRING:
 616         case MONO_TYPE_OBJECT:
 617         case MONO_TYPE_CLASS:
 618         case MONO_TYPE_SZARRAY:
 619         case MONO_TYPE_PTR:
 620         case MONO_TYPE_FNPTR:
 621         case MONO_TYPE_ARRAY:
 622         case MONO_TYPE_I8:
 623         case MONO_TYPE_U8:
 624                 class2 = ARG_CLASS_INTEGER;
 625                 break;
 626         case MONO_TYPE_R4:
 627         case MONO_TYPE_R8:
 628 #ifdef TARGET_WIN32
 629                 class2 = ARG_CLASS_INTEGER;
 630 #else
 631                 class2 = ARG_CLASS_SSE;
 632 #endif
 633                 break;
 634
 635         case MONO_TYPE_TYPEDBYREF:
 636                 g_assert_not_reached ();
 637
 638         case MONO_TYPE_GENERICINST:
 639                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 640                         class2 = ARG_CLASS_INTEGER;
 641                         break;
 642                 }
 643                 /* fall through */
 644         case MONO_TYPE_VALUETYPE: {
 645                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 646                 int i;
 647
 648                 for (i = 0; i < info->num_fields; ++i) {
 649                         class2 = class1;
 650                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 651                 }
 652                 break;
 653         }
 654         default:
 655                 g_assert_not_reached ();
 656         }
 657
 658         /* Merge */
 659         if (class1 == class2)
 660                 ;
 661         else if (class1 == ARG_CLASS_NO_CLASS)
 662                 class1 = class2;
 663         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 664                 class1 = ARG_CLASS_MEMORY;
 665         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 666                 class1 = ARG_CLASS_INTEGER;
 667         else
 668                 class1 = ARG_CLASS_SSE;
 669
 670         return class1;
 671 }
 672 #ifdef __native_client_codegen__
 673
 674 /* Default alignment for Native Client is 32-byte. */
 675 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 676
 677 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 678 /* Check that alignment doesn't cross an alignment boundary.             */
 679 guint8*
 680 mono_arch_nacl_pad(guint8 *code, int pad)
 681 {
 682         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 683
 684         if (pad == 0) return code;
 685         /* assertion: alignment cannot cross a block boundary */
 686         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 687                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 688         while (pad >= kMaxPadding) {
 689                 amd64_padding (code, kMaxPadding);
 690                 pad -= kMaxPadding;
 691         }
 692         if (pad != 0) amd64_padding (code, pad);
 693         return code;
 694 }
 695 #endif
 696
 697 static int
 698 count_fields_nested (MonoClass *klass)
 699 {
 700         MonoMarshalType *info;
 701         int i, count;
 702
 703         info = mono_marshal_load_type_info (klass);
 704         g_assert(info);
 705         count = 0;
 706         for (i = 0; i < info->num_fields; ++i) {
 707                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 708                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 709                 else
 710                         count ++;
 711         }
 712         return count;
 713 }
 714
 715 static int
 716 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 717 {
 718         MonoMarshalType *info;
 719         int i;
 720
 721         info = mono_marshal_load_type_info (klass);
 722         g_assert(info);
 723         for (i = 0; i < info->num_fields; ++i) {
 724                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 725                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 726                 } else {
 727                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 728                         fields [index].offset += offset;
 729                         index ++;
 730                 }
 731         }
 732         return index;
 733 }
 734
 735 static void
 736 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 737                            gboolean is_return,
 738                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 739 {
 740         guint32 size, quad, nquads, i, nfields;
 741         /* Keep track of the size used in each quad so we can */
 742         /* use the right size when copying args/return vars.  */
 743         guint32 quadsize [2] = {8, 8};
 744         ArgumentClass args [2];
 745         MonoMarshalType *info = NULL;
 746         MonoMarshalField *fields = NULL;
 747         MonoClass *klass;
 748         gboolean pass_on_stack = FALSE;
 749
 750         klass = mono_class_from_mono_type (type);
 751         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 752 #ifndef TARGET_WIN32
 753         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 754                 /* We pass and return vtypes of size 8 in a register */
 755         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 756                 pass_on_stack = TRUE;
 757         }
 758 #else
 759         if (!sig->pinvoke) {
 760                 pass_on_stack = TRUE;
 761         }
 762 #endif
 763
 764         /* If this struct can't be split up naturally into 8-byte */
 765         /* chunks (registers), pass it on the stack.              */
 766         if (sig->pinvoke && !pass_on_stack) {
 767                 guint32 align;
 768                 guint32 field_size;
 769
 770                 info = mono_marshal_load_type_info (klass);
 771                 g_assert (info);
 772
 773                 /*
 774                  * Collect field information recursively to be able to
 775                  * handle nested structures.
 776                  */
 777                 nfields = count_fields_nested (klass);
 778                 fields = g_new0 (MonoMarshalField, nfields);
 779                 collect_field_info_nested (klass, fields, 0, 0);
 780
 781                 for (i = 0; i < nfields; ++i) {
 782                         field_size = mono_marshal_type_size (fields [i].field->type,
 783                                                            fields [i].mspec,
 784                                                            &align, TRUE, klass->unicode);
 785                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 786                                 pass_on_stack = TRUE;
 787                                 break;
 788                         }
 789                 }
 790         }
 791
 792 #ifndef TARGET_WIN32
 793         if (size == 0) {
 794                 ainfo->storage = ArgValuetypeInReg;
 795                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 796                 return;
 797         }
 798 #endif
 799
 800         if (pass_on_stack) {
 801                 /* Allways pass in memory */
 802                 ainfo->offset = *stack_size;
 803                 *stack_size += ALIGN_TO (size, 8);
 804                 ainfo->storage = ArgOnStack;
 805
 806                 g_free (fields);
 807                 return;
 808         }
 809
 810         /* FIXME: Handle structs smaller than 8 bytes */
 811         //if ((size % 8) != 0)
 812         //      NOT_IMPLEMENTED;
 813
 814         if (size > 8)
 815                 nquads = 2;
 816         else
 817                 nquads = 1;
 818
 819         if (!sig->pinvoke) {
 820                 int n = mono_class_value_size (klass, NULL);
 821
 822                 quadsize [0] = n >= 8 ? 8 : n;
 823                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 824
 825                 /* Always pass in 1 or 2 integer registers */
 826                 args [0] = ARG_CLASS_INTEGER;
 827                 args [1] = ARG_CLASS_INTEGER;
 828                 /* Only the simplest cases are supported */
 829                 if (is_return && nquads != 1) {
 830                         args [0] = ARG_CLASS_MEMORY;
 831                         args [1] = ARG_CLASS_MEMORY;
 832                 }
 833         } else {
 834                 /*
 835                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 836                  * The X87 and SSEUP stuff is left out since there are no such types in
 837                  * the CLR.
 838                  */
 839                 g_assert (info);
 840
 841                 if (!fields) {
 842                         ainfo->storage = ArgValuetypeInReg;
 843                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 844                         return;
 845                 }
 846
 847 #ifndef TARGET_WIN32
 848                 if (info->native_size > 16) {
 849                         ainfo->offset = *stack_size;
 850                         *stack_size += ALIGN_TO (info->native_size, 8);
 851                         ainfo->storage = ArgOnStack;
 852
 853                         g_free (fields);
 854                         return;
 855                 }
 856 #else
 857                 switch (info->native_size) {
 858                 case 1: case 2: case 4: case 8:
 859                         break;
 860                 default:
 861                         if (is_return) {
 862                                 ainfo->storage = ArgOnStack;
 863                                 ainfo->offset = *stack_size;
 864                                 *stack_size += ALIGN_TO (info->native_size, 8);
 865                         }
 866                         else {
 867                                 ainfo->storage = ArgValuetypeAddrInIReg;
 868
 869                                 if (*gr < PARAM_REGS) {
 870                                         ainfo->pair_storage [0] = ArgInIReg;
 871                                         ainfo->pair_regs [0] = param_regs [*gr];
 872                                         (*gr) ++;
 873                                 }
 874                                 else {
 875                                         ainfo->pair_storage [0] = ArgOnStack;
 876                                         ainfo->offset = *stack_size;
 877                                         *stack_size += 8;
 878                                 }
 879                         }
 880
 881                         g_free (fields);
 882                         return;
 883                 }
 884 #endif
 885
 886                 args [0] = ARG_CLASS_NO_CLASS;
 887                 args [1] = ARG_CLASS_NO_CLASS;
 888                 for (quad = 0; quad < nquads; ++quad) {
 889                         int size;
 890                         guint32 align;
 891                         ArgumentClass class1;
 892
 893                         if (nfields == 0)
 894                                 class1 = ARG_CLASS_MEMORY;
 895                         else
 896                                 class1 = ARG_CLASS_NO_CLASS;
 897                         for (i = 0; i < nfields; ++i) {
 898                                 size = mono_marshal_type_size (fields [i].field->type,
 899                                                                                            fields [i].mspec,
 900                                                                                            &align, TRUE, klass->unicode);
 901                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 902                                         /* Unaligned field */
 903                                         NOT_IMPLEMENTED;
 904                                 }
 905
 906                                 /* Skip fields in other quad */
 907                                 if ((quad == 0) && (fields [i].offset >= 8))
 908                                         continue;
 909                                 if ((quad == 1) && (fields [i].offset < 8))
 910                                         continue;
 911
 912                                 /* How far into this quad this data extends.*/
 913                                 /* (8 is size of quad) */
 914                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 915
 916                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 917                         }
 918                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 919                         args [quad] = class1;
 920                 }
 921         }
 922
 923         g_free (fields);
 924
 925         /* Post merger cleanup */
 926         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 927                 args [0] = args [1] = ARG_CLASS_MEMORY;
 928
 929         /* Allocate registers */
 930         {
 931                 int orig_gr = *gr;
 932                 int orig_fr = *fr;
 933
 934                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 935                         quadsize [0] ++;
 936                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 937                         quadsize [1] ++;
 938
 939                 ainfo->storage = ArgValuetypeInReg;
 940                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 941                 g_assert (quadsize [0] <= 8);
 942                 g_assert (quadsize [1] <= 8);
 943                 ainfo->pair_size [0] = quadsize [0];
 944                 ainfo->pair_size [1] = quadsize [1];
 945                 ainfo->nregs = nquads;
 946                 for (quad = 0; quad < nquads; ++quad) {
 947                         switch (args [quad]) {
 948                         case ARG_CLASS_INTEGER:
 949                                 if (*gr >= PARAM_REGS)
 950                                         args [quad] = ARG_CLASS_MEMORY;
 951                                 else {
 952                                         ainfo->pair_storage [quad] = ArgInIReg;
 953                                         if (is_return)
 954                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 955                                         else
 956                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 957                                         (*gr) ++;
 958                                 }
 959                                 break;
 960                         case ARG_CLASS_SSE:
 961                                 if (*fr >= FLOAT_PARAM_REGS)
 962                                         args [quad] = ARG_CLASS_MEMORY;
 963                                 else {
 964                                         if (quadsize[quad] <= 4)
 965                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 966                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 967                                         ainfo->pair_regs [quad] = *fr;
 968                                         (*fr) ++;
 969                                 }
 970                                 break;
 971                         case ARG_CLASS_MEMORY:
 972                                 break;
 973                         default:
 974                                 g_assert_not_reached ();
 975                         }
 976                 }
 977
 978                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 979                         /* Revert possible register assignments */
 980                         *gr = orig_gr;
 981                         *fr = orig_fr;
 982
 983                         ainfo->offset = *stack_size;
 984                         if (sig->pinvoke)
 985                                 *stack_size += ALIGN_TO (info->native_size, 8);
 986                         else
 987                                 *stack_size += nquads * sizeof(mgreg_t);
 988                         ainfo->storage = ArgOnStack;
 989                 }
 990         }
 991 }
 992
 993 /*
 994  * get_call_info:
 995  *
 996  *  Obtain information about a call according to the calling convention.
 997  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 998  * Draft Version 0.23" document for more information.
 999  */
1000 static CallInfo*
1001 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1002 {
1003         guint32 i, gr, fr, pstart;
1004         MonoType *ret_type;
1005         int n = sig->hasthis + sig->param_count;
1006         guint32 stack_size = 0;
1007         CallInfo *cinfo;
1008         gboolean is_pinvoke = sig->pinvoke;
1009
1010         if (mp)
1011                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1012         else
1013                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1014
1015         cinfo->nargs = n;
1016
1017         gr = 0;
1018         fr = 0;
1019
1020 #ifdef TARGET_WIN32
1021         /* Reserve space where the callee can save the argument registers */
1022         stack_size = 4 * sizeof (mgreg_t);
1023 #endif
1024
1025         /* return value */
1026         ret_type = mini_get_underlying_type (sig->ret);
1027         switch (ret_type->type) {
1028         case MONO_TYPE_I1:
1029         case MONO_TYPE_U1:
1030         case MONO_TYPE_I2:
1031         case MONO_TYPE_U2:
1032         case MONO_TYPE_I4:
1033         case MONO_TYPE_U4:
1034         case MONO_TYPE_I:
1035         case MONO_TYPE_U:
1036         case MONO_TYPE_PTR:
1037         case MONO_TYPE_FNPTR:
1038         case MONO_TYPE_CLASS:
1039         case MONO_TYPE_OBJECT:
1040         case MONO_TYPE_SZARRAY:
1041         case MONO_TYPE_ARRAY:
1042         case MONO_TYPE_STRING:
1043                 cinfo->ret.storage = ArgInIReg;
1044                 cinfo->ret.reg = AMD64_RAX;
1045                 break;
1046         case MONO_TYPE_U8:
1047         case MONO_TYPE_I8:
1048                 cinfo->ret.storage = ArgInIReg;
1049                 cinfo->ret.reg = AMD64_RAX;
1050                 break;
1051         case MONO_TYPE_R4:
1052                 cinfo->ret.storage = ArgInFloatSSEReg;
1053                 cinfo->ret.reg = AMD64_XMM0;
1054                 break;
1055         case MONO_TYPE_R8:
1056                 cinfo->ret.storage = ArgInDoubleSSEReg;
1057                 cinfo->ret.reg = AMD64_XMM0;
1058                 break;
1059         case MONO_TYPE_GENERICINST:
1060                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1061                         cinfo->ret.storage = ArgInIReg;
1062                         cinfo->ret.reg = AMD64_RAX;
1063                         break;
1064                 }
1065                 /* fall through */
1066 #if defined( __native_client_codegen__ )
1067         case MONO_TYPE_TYPEDBYREF:
1068 #endif
1069         case MONO_TYPE_VALUETYPE: {
1070                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1071
1072                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1073                 if (cinfo->ret.storage == ArgOnStack) {
1074                         cinfo->vtype_retaddr = TRUE;
1075                         /* The caller passes the address where the value is stored */
1076                 }
1077                 break;
1078         }
1079 #if !defined( __native_client_codegen__ )
1080         case MONO_TYPE_TYPEDBYREF:
1081                 /* Same as a valuetype with size 24 */
1082                 cinfo->vtype_retaddr = TRUE;
1083                 break;
1084 #endif
1085         case MONO_TYPE_VOID:
1086                 break;
1087         default:
1088                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1089         }
1090
1091         pstart = 0;
1092         /*
1093          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1094          * the first argument, allowing 'this' to be always passed in the first arg reg.
1095          * Also do this if the first argument is a reference type, since virtual calls
1096          * are sometimes made using calli without sig->hasthis set, like in the delegate
1097          * invoke wrappers.
1098          */
1099         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1100                 if (sig->hasthis) {
1101                         add_general (&gr, &stack_size, cinfo->args + 0);
1102                 } else {
1103                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1104                         pstart = 1;
1105                 }
1106                 add_general (&gr, &stack_size, &cinfo->ret);
1107                 cinfo->vret_arg_index = 1;
1108         } else {
1109                 /* this */
1110                 if (sig->hasthis)
1111                         add_general (&gr, &stack_size, cinfo->args + 0);
1112
1113                 if (cinfo->vtype_retaddr)
1114                         add_general (&gr, &stack_size, &cinfo->ret);
1115         }
1116
1117         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1118                 gr = PARAM_REGS;
1119                 fr = FLOAT_PARAM_REGS;
1120
1121                 /* Emit the signature cookie just before the implicit arguments */
1122                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1123         }
1124
1125         for (i = pstart; i < sig->param_count; ++i) {
1126                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1127                 MonoType *ptype;
1128
1129 #ifdef TARGET_WIN32
1130                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1131                 if (gr > fr)
1132                         fr = gr;
1133                 else if (fr > gr)
1134                         gr = fr;
1135 #endif
1136
1137                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1138                         /* We allways pass the sig cookie on the stack for simplicity */
1139                         /*
1140                          * Prevent implicit arguments + the sig cookie from being passed
1141                          * in registers.
1142                          */
1143                         gr = PARAM_REGS;
1144                         fr = FLOAT_PARAM_REGS;
1145
1146                         /* Emit the signature cookie just before the implicit arguments */
1147                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1148                 }
1149
1150                 ptype = mini_get_underlying_type (sig->params [i]);
1151                 switch (ptype->type) {
1152                 case MONO_TYPE_I1:
1153                 case MONO_TYPE_U1:
1154                         add_general (&gr, &stack_size, ainfo);
1155                         break;
1156                 case MONO_TYPE_I2:
1157                 case MONO_TYPE_U2:
1158                         add_general (&gr, &stack_size, ainfo);
1159                         break;
1160                 case MONO_TYPE_I4:
1161                 case MONO_TYPE_U4:
1162                         add_general (&gr, &stack_size, ainfo);
1163                         break;
1164                 case MONO_TYPE_I:
1165                 case MONO_TYPE_U:
1166                 case MONO_TYPE_PTR:
1167                 case MONO_TYPE_FNPTR:
1168                 case MONO_TYPE_CLASS:
1169                 case MONO_TYPE_OBJECT:
1170                 case MONO_TYPE_STRING:
1171                 case MONO_TYPE_SZARRAY:
1172                 case MONO_TYPE_ARRAY:
1173                         add_general (&gr, &stack_size, ainfo);
1174                         break;
1175                 case MONO_TYPE_GENERICINST:
1176                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1177                                 add_general (&gr, &stack_size, ainfo);
1178                                 break;
1179                         }
1180                         /* fall through */
1181                 case MONO_TYPE_VALUETYPE:
1182                 case MONO_TYPE_TYPEDBYREF:
1183                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1184                         break;
1185                 case MONO_TYPE_U8:
1186
1187                 case MONO_TYPE_I8:
1188                         add_general (&gr, &stack_size, ainfo);
1189                         break;
1190                 case MONO_TYPE_R4:
1191                         add_float (&fr, &stack_size, ainfo, FALSE);
1192                         break;
1193                 case MONO_TYPE_R8:
1194                         add_float (&fr, &stack_size, ainfo, TRUE);
1195                         break;
1196                 default:
1197                         g_assert_not_reached ();
1198                 }
1199         }
1200
1201         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1202                 gr = PARAM_REGS;
1203                 fr = FLOAT_PARAM_REGS;
1204
1205                 /* Emit the signature cookie just before the implicit arguments */
1206                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1207         }
1208
1209         cinfo->stack_usage = stack_size;
1210         cinfo->reg_usage = gr;
1211         cinfo->freg_usage = fr;
1212         return cinfo;
1213 }
1214
1215 /*
1216  * mono_arch_get_argument_info:
1217  * @csig:  a method signature
1218  * @param_count: the number of parameters to consider
1219  * @arg_info: an array to store the result infos
1220  *
1221  * Gathers information on parameters such as size, alignment and
1222  * padding. arg_info should be large enought to hold param_count + 1 entries.
1223  *
1224  * Returns the size of the argument area on the stack.
1225  */
1226 int
1227 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1228 {
1229         int k;
1230         CallInfo *cinfo = get_call_info (NULL, csig);
1231         guint32 args_size = cinfo->stack_usage;
1232
1233         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1234         if (csig->hasthis) {
1235                 arg_info [0].offset = 0;
1236         }
1237
1238         for (k = 0; k < param_count; k++) {
1239                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1240                 /* FIXME: */
1241                 arg_info [k + 1].size = 0;
1242         }
1243
1244         g_free (cinfo);
1245
1246         return args_size;
1247 }
1248
1249 gboolean
1250 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1251 {
1252         CallInfo *c1, *c2;
1253         gboolean res;
1254         MonoType *callee_ret;
1255
1256         c1 = get_call_info (NULL, caller_sig);
1257         c2 = get_call_info (NULL, callee_sig);
1258         res = c1->stack_usage >= c2->stack_usage;
1259         callee_ret = mini_get_underlying_type (callee_sig->ret);
1260         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1261                 /* An address on the callee's stack is passed as the first argument */
1262                 res = FALSE;
1263
1264         g_free (c1);
1265         g_free (c2);
1266
1267         return res;
1268 }
1269
1270 /*
1271  * Initialize the cpu to execute managed code.
1272  */
1273 void
1274 mono_arch_cpu_init (void)
1275 {
1276 #ifndef _MSC_VER
1277         guint16 fpcw;
1278
1279         /* spec compliance requires running with double precision */
1280         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1281         fpcw &= ~X86_FPCW_PRECC_MASK;
1282         fpcw |= X86_FPCW_PREC_DOUBLE;
1283         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1284         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1285 #else
1286         /* TODO: This is crashing on Win64 right now.
1287         * _control87 (_PC_53, MCW_PC);
1288         */
1289 #endif
1290 }
1291
1292 /*
1293  * Initialize architecture specific code.
1294  */
1295 void
1296 mono_arch_init (void)
1297 {
1298         int flags;
1299
1300         mono_mutex_init_recursive (&mini_arch_mutex);
1301 #if defined(__native_client_codegen__)
1302         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1303         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1304         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1305         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1306 #endif
1307
1308 #ifdef MONO_ARCH_NOMAP32BIT
1309         flags = MONO_MMAP_READ;
1310         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1311         breakpoint_size = 13;
1312         breakpoint_fault_size = 3;
1313 #else
1314         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1315         /* amd64_mov_reg_mem () */
1316         breakpoint_size = 8;
1317         breakpoint_fault_size = 8;
1318 #endif
1319
1320         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1321         single_step_fault_size = 4;
1322
1323         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1324         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1325         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1326
1327         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1328         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1329         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1330         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1331 }
1332
1333 /*
1334  * Cleanup architecture specific code.
1335  */
1336 void
1337 mono_arch_cleanup (void)
1338 {
1339         mono_mutex_destroy (&mini_arch_mutex);
1340 #if defined(__native_client_codegen__)
1341         mono_native_tls_free (nacl_instruction_depth);
1342         mono_native_tls_free (nacl_rex_tag);
1343         mono_native_tls_free (nacl_legacy_prefix_tag);
1344 #endif
1345 }
1346
1347 /*
1348  * This function returns the optimizations supported on this cpu.
1349  */
1350 guint32
1351 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1352 {
1353         guint32 opts = 0;
1354
1355         *exclude_mask = 0;
1356
1357         if (mono_hwcap_x86_has_cmov) {
1358                 opts |= MONO_OPT_CMOV;
1359
1360                 if (mono_hwcap_x86_has_fcmov)
1361                         opts |= MONO_OPT_FCMOV;
1362                 else
1363                         *exclude_mask |= MONO_OPT_FCMOV;
1364         } else {
1365                 *exclude_mask |= MONO_OPT_CMOV;
1366         }
1367
1368         return opts;
1369 }
1370
1371 /*
1372  * This function test for all SSE functions supported.
1373  *
1374  * Returns a bitmask corresponding to all supported versions.
1375  *
1376  */
1377 guint32
1378 mono_arch_cpu_enumerate_simd_versions (void)
1379 {
1380         guint32 sse_opts = 0;
1381
1382         if (mono_hwcap_x86_has_sse1)
1383                 sse_opts |= SIMD_VERSION_SSE1;
1384
1385         if (mono_hwcap_x86_has_sse2)
1386                 sse_opts |= SIMD_VERSION_SSE2;
1387
1388         if (mono_hwcap_x86_has_sse3)
1389                 sse_opts |= SIMD_VERSION_SSE3;
1390
1391         if (mono_hwcap_x86_has_ssse3)
1392                 sse_opts |= SIMD_VERSION_SSSE3;
1393
1394         if (mono_hwcap_x86_has_sse41)
1395                 sse_opts |= SIMD_VERSION_SSE41;
1396
1397         if (mono_hwcap_x86_has_sse42)
1398                 sse_opts |= SIMD_VERSION_SSE42;
1399
1400         if (mono_hwcap_x86_has_sse4a)
1401                 sse_opts |= SIMD_VERSION_SSE4a;
1402
1403         return sse_opts;
1404 }
1405
1406 #ifndef DISABLE_JIT
1407
1408 GList *
1409 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1410 {
1411         GList *vars = NULL;
1412         int i;
1413
1414         for (i = 0; i < cfg->num_varinfo; i++) {
1415                 MonoInst *ins = cfg->varinfo [i];
1416                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1417
1418                 /* unused vars */
1419                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1420                         continue;
1421
1422                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1423                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1424                         continue;
1425
1426                 if (mono_is_regsize_var (ins->inst_vtype)) {
1427                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1428                         g_assert (i == vmv->idx);
1429                         vars = g_list_prepend (vars, vmv);
1430                 }
1431         }
1432
1433         vars = mono_varlist_sort (cfg, vars, 0);
1434
1435         return vars;
1436 }
1437
1438 /**
1439  * mono_arch_compute_omit_fp:
1440  *
1441  *   Determine whenever the frame pointer can be eliminated.
1442  */
1443 static void
1444 mono_arch_compute_omit_fp (MonoCompile *cfg)
1445 {
1446         MonoMethodSignature *sig;
1447         MonoMethodHeader *header;
1448         int i, locals_size;
1449         CallInfo *cinfo;
1450
1451         if (cfg->arch.omit_fp_computed)
1452                 return;
1453
1454         header = cfg->header;
1455
1456         sig = mono_method_signature (cfg->method);
1457
1458         if (!cfg->arch.cinfo)
1459                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1460         cinfo = cfg->arch.cinfo;
1461
1462         /*
1463          * FIXME: Remove some of the restrictions.
1464          */
1465         cfg->arch.omit_fp = TRUE;
1466         cfg->arch.omit_fp_computed = TRUE;
1467
1468 #ifdef __native_client_codegen__
1469         /* NaCl modules may not change the value of RBP, so it cannot be */
1470         /* used as a normal register, but it can be used as a frame pointer*/
1471         cfg->disable_omit_fp = TRUE;
1472         cfg->arch.omit_fp = FALSE;
1473 #endif
1474
1475         if (cfg->disable_omit_fp)
1476                 cfg->arch.omit_fp = FALSE;
1477
1478         if (!debug_omit_fp ())
1479                 cfg->arch.omit_fp = FALSE;
1480         /*
1481         if (cfg->method->save_lmf)
1482                 cfg->arch.omit_fp = FALSE;
1483         */
1484         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1485                 cfg->arch.omit_fp = FALSE;
1486         if (header->num_clauses)
1487                 cfg->arch.omit_fp = FALSE;
1488         if (cfg->param_area)
1489                 cfg->arch.omit_fp = FALSE;
1490         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1491                 cfg->arch.omit_fp = FALSE;
1492         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1493                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1494                 cfg->arch.omit_fp = FALSE;
1495         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1496                 ArgInfo *ainfo = &cinfo->args [i];
1497
1498                 if (ainfo->storage == ArgOnStack) {
1499                         /*
1500                          * The stack offset can only be determined when the frame
1501                          * size is known.
1502                          */
1503                         cfg->arch.omit_fp = FALSE;
1504                 }
1505         }
1506
1507         locals_size = 0;
1508         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1509                 MonoInst *ins = cfg->varinfo [i];
1510                 int ialign;
1511
1512                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1513         }
1514 }
1515
1516 GList *
1517 mono_arch_get_global_int_regs (MonoCompile *cfg)
1518 {
1519         GList *regs = NULL;
1520
1521         mono_arch_compute_omit_fp (cfg);
1522
1523         if (cfg->arch.omit_fp)
1524                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1525
1526         /* We use the callee saved registers for global allocation */
1527         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1528         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1529         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1530         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1531 #ifndef __native_client_codegen__
1532         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1533 #endif
1534 #ifdef TARGET_WIN32
1535         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1536         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1537 #endif
1538
1539         return regs;
1540 }
1541
1542 GList*
1543 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1544 {
1545         GList *regs = NULL;
1546         int i;
1547
1548         /* All XMM registers */
1549         for (i = 0; i < 16; ++i)
1550                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1551
1552         return regs;
1553 }
1554
1555 GList*
1556 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1557 {
1558         static GList *r = NULL;
1559
1560         if (r == NULL) {
1561                 GList *regs = NULL;
1562
1563                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1564                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1565                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1566                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1567                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1568 #ifndef __native_client_codegen__
1569                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1570 #endif
1571
1572                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1573                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1574                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1575                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1576                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1577                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1580
1581                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1582         }
1583
1584         return r;
1585 }
1586
1587 GList*
1588 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1589 {
1590         int i;
1591         static GList *r = NULL;
1592
1593         if (r == NULL) {
1594                 GList *regs = NULL;
1595
1596                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1597                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1598
1599                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1600         }
1601
1602         return r;
1603 }
1604
1605 /*
1606  * mono_arch_regalloc_cost:
1607  *
1608  *  Return the cost, in number of memory references, of the action of
1609  * allocating the variable VMV into a register during global register
1610  * allocation.
1611  */
1612 guint32
1613 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1614 {
1615         MonoInst *ins = cfg->varinfo [vmv->idx];
1616
1617         if (cfg->method->save_lmf)
1618                 /* The register is already saved */
1619                 /* substract 1 for the invisible store in the prolog */
1620                 return (ins->opcode == OP_ARG) ? 0 : 1;
1621         else
1622                 /* push+pop */
1623                 return (ins->opcode == OP_ARG) ? 1 : 2;
1624 }
1625
1626 /*
1627  * mono_arch_fill_argument_info:
1628  *
1629  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1630  * of the method.
1631  */
1632 void
1633 mono_arch_fill_argument_info (MonoCompile *cfg)
1634 {
1635         MonoType *sig_ret;
1636         MonoMethodSignature *sig;
1637         MonoInst *ins;
1638         int i;
1639         CallInfo *cinfo;
1640
1641         sig = mono_method_signature (cfg->method);
1642
1643         cinfo = cfg->arch.cinfo;
1644         sig_ret = mini_get_underlying_type (sig->ret);
1645
1646         /*
1647          * Contrary to mono_arch_allocate_vars (), the information should describe
1648          * where the arguments are at the beginning of the method, not where they can be
1649          * accessed during the execution of the method. The later makes no sense for the
1650          * global register allocator, since a variable can be in more than one location.
1651          */
1652         if (sig_ret->type != MONO_TYPE_VOID) {
1653                 switch (cinfo->ret.storage) {
1654                 case ArgInIReg:
1655                 case ArgInFloatSSEReg:
1656                 case ArgInDoubleSSEReg:
1657                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1658                                 cfg->vret_addr->opcode = OP_REGVAR;
1659                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1660                         }
1661                         else {
1662                                 cfg->ret->opcode = OP_REGVAR;
1663                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1664                         }
1665                         break;
1666                 case ArgValuetypeInReg:
1667                         cfg->ret->opcode = OP_REGOFFSET;
1668                         cfg->ret->inst_basereg = -1;
1669                         cfg->ret->inst_offset = -1;
1670                         break;
1671                 default:
1672                         g_assert_not_reached ();
1673                 }
1674         }
1675
1676         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1677                 ArgInfo *ainfo = &cinfo->args [i];
1678
1679                 ins = cfg->args [i];
1680
1681                 switch (ainfo->storage) {
1682                 case ArgInIReg:
1683                 case ArgInFloatSSEReg:
1684                 case ArgInDoubleSSEReg:
1685                         ins->opcode = OP_REGVAR;
1686                         ins->inst_c0 = ainfo->reg;
1687                         break;
1688                 case ArgOnStack:
1689                         ins->opcode = OP_REGOFFSET;
1690                         ins->inst_basereg = -1;
1691                         ins->inst_offset = -1;
1692                         break;
1693                 case ArgValuetypeInReg:
1694                         /* Dummy */
1695                         ins->opcode = OP_NOP;
1696                         break;
1697                 default:
1698                         g_assert_not_reached ();
1699                 }
1700         }
1701 }
1702
1703 void
1704 mono_arch_allocate_vars (MonoCompile *cfg)
1705 {
1706         MonoType *sig_ret;
1707         MonoMethodSignature *sig;
1708         MonoInst *ins;
1709         int i, offset;
1710         guint32 locals_stack_size, locals_stack_align;
1711         gint32 *offsets;
1712         CallInfo *cinfo;
1713
1714         sig = mono_method_signature (cfg->method);
1715
1716         cinfo = cfg->arch.cinfo;
1717         sig_ret = mini_get_underlying_type (sig->ret);
1718
1719         mono_arch_compute_omit_fp (cfg);
1720
1721         /*
1722          * We use the ABI calling conventions for managed code as well.
1723          * Exception: valuetypes are only sometimes passed or returned in registers.
1724          */
1725
1726         /*
1727          * The stack looks like this:
1728          * <incoming arguments passed on the stack>
1729          * <return value>
1730          * <lmf/caller saved registers>
1731          * <locals>
1732          * <spill area>
1733          * <localloc area>  -> grows dynamically
1734          * <params area>
1735          */
1736
1737         if (cfg->arch.omit_fp) {
1738                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1739                 cfg->frame_reg = AMD64_RSP;
1740                 offset = 0;
1741         } else {
1742                 /* Locals are allocated backwards from %fp */
1743                 cfg->frame_reg = AMD64_RBP;
1744                 offset = 0;
1745         }
1746
1747         cfg->arch.saved_iregs = cfg->used_int_regs;
1748         if (cfg->method->save_lmf)
1749                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1750                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1751
1752         if (cfg->arch.omit_fp)
1753                 cfg->arch.reg_save_area_offset = offset;
1754         /* Reserve space for callee saved registers */
1755         for (i = 0; i < AMD64_NREG; ++i)
1756                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1757                         offset += sizeof(mgreg_t);
1758                 }
1759         if (!cfg->arch.omit_fp)
1760                 cfg->arch.reg_save_area_offset = -offset;
1761
1762         if (sig_ret->type != MONO_TYPE_VOID) {
1763                 switch (cinfo->ret.storage) {
1764                 case ArgInIReg:
1765                 case ArgInFloatSSEReg:
1766                 case ArgInDoubleSSEReg:
1767                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1768                                 /* The register is volatile */
1769                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1770                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1771                                 if (cfg->arch.omit_fp) {
1772                                         cfg->vret_addr->inst_offset = offset;
1773                                         offset += 8;
1774                                 } else {
1775                                         offset += 8;
1776                                         cfg->vret_addr->inst_offset = -offset;
1777                                 }
1778                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1779                                         printf ("vret_addr =");
1780                                         mono_print_ins (cfg->vret_addr);
1781                                 }
1782                         }
1783                         else {
1784                                 cfg->ret->opcode = OP_REGVAR;
1785                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1786                         }
1787                         break;
1788                 case ArgValuetypeInReg:
1789                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1790                         cfg->ret->opcode = OP_REGOFFSET;
1791                         cfg->ret->inst_basereg = cfg->frame_reg;
1792                         if (cfg->arch.omit_fp) {
1793                                 cfg->ret->inst_offset = offset;
1794                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1795                         } else {
1796                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1797                                 cfg->ret->inst_offset = - offset;
1798                         }
1799                         break;
1800                 default:
1801                         g_assert_not_reached ();
1802                 }
1803                 cfg->ret->dreg = cfg->ret->inst_c0;
1804         }
1805
1806         /* Allocate locals */
1807         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1808         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1809                 char *mname = mono_method_full_name (cfg->method, TRUE);
1810                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1811                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1812                 g_free (mname);
1813                 return;
1814         }
1815
1816         if (locals_stack_align) {
1817                 offset += (locals_stack_align - 1);
1818                 offset &= ~(locals_stack_align - 1);
1819         }
1820         if (cfg->arch.omit_fp) {
1821                 cfg->locals_min_stack_offset = offset;
1822                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1823         } else {
1824                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1825                 cfg->locals_max_stack_offset = - offset;
1826         }
1827
1828         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1829                 if (offsets [i] != -1) {
1830                         MonoInst *ins = cfg->varinfo [i];
1831                         ins->opcode = OP_REGOFFSET;
1832                         ins->inst_basereg = cfg->frame_reg;
1833                         if (cfg->arch.omit_fp)
1834                                 ins->inst_offset = (offset + offsets [i]);
1835                         else
1836                                 ins->inst_offset = - (offset + offsets [i]);
1837                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1838                 }
1839         }
1840         offset += locals_stack_size;
1841
1842         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1843                 g_assert (!cfg->arch.omit_fp);
1844                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1845                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1846         }
1847
1848         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1849                 ins = cfg->args [i];
1850                 if (ins->opcode != OP_REGVAR) {
1851                         ArgInfo *ainfo = &cinfo->args [i];
1852                         gboolean inreg = TRUE;
1853
1854                         /* FIXME: Allocate volatile arguments to registers */
1855                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1856                                 inreg = FALSE;
1857
1858                         /*
1859                          * Under AMD64, all registers used to pass arguments to functions
1860                          * are volatile across calls.
1861                          * FIXME: Optimize this.
1862                          */
1863                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1864                                 inreg = FALSE;
1865
1866                         ins->opcode = OP_REGOFFSET;
1867
1868                         switch (ainfo->storage) {
1869                         case ArgInIReg:
1870                         case ArgInFloatSSEReg:
1871                         case ArgInDoubleSSEReg:
1872                                 if (inreg) {
1873                                         ins->opcode = OP_REGVAR;
1874                                         ins->dreg = ainfo->reg;
1875                                 }
1876                                 break;
1877                         case ArgOnStack:
1878                                 g_assert (!cfg->arch.omit_fp);
1879                                 ins->opcode = OP_REGOFFSET;
1880                                 ins->inst_basereg = cfg->frame_reg;
1881                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1882                                 break;
1883                         case ArgValuetypeInReg:
1884                                 break;
1885                         case ArgValuetypeAddrInIReg: {
1886                                 MonoInst *indir;
1887                                 g_assert (!cfg->arch.omit_fp);
1888
1889                                 MONO_INST_NEW (cfg, indir, 0);
1890                                 indir->opcode = OP_REGOFFSET;
1891                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1892                                         indir->inst_basereg = cfg->frame_reg;
1893                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1894                                         offset += (sizeof (gpointer));
1895                                         indir->inst_offset = - offset;
1896                                 }
1897                                 else {
1898                                         indir->inst_basereg = cfg->frame_reg;
1899                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1900                                 }
1901
1902                                 ins->opcode = OP_VTARG_ADDR;
1903                                 ins->inst_left = indir;
1904
1905                                 break;
1906                         }
1907                         default:
1908                                 NOT_IMPLEMENTED;
1909                         }
1910
1911                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1912                                 ins->opcode = OP_REGOFFSET;
1913                                 ins->inst_basereg = cfg->frame_reg;
1914                                 /* These arguments are saved to the stack in the prolog */
1915                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1916                                 if (cfg->arch.omit_fp) {
1917                                         ins->inst_offset = offset;
1918                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1919                                         // Arguments are yet supported by the stack map creation code
1920                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1921                                 } else {
1922                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1923                                         ins->inst_offset = - offset;
1924                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1925                                 }
1926                         }
1927                 }
1928         }
1929
1930         cfg->stack_offset = offset;
1931 }
1932
1933 void
1934 mono_arch_create_vars (MonoCompile *cfg)
1935 {
1936         MonoMethodSignature *sig;
1937         CallInfo *cinfo;
1938         MonoType *sig_ret;
1939
1940         sig = mono_method_signature (cfg->method);
1941
1942         if (!cfg->arch.cinfo)
1943                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1944         cinfo = cfg->arch.cinfo;
1945
1946         if (cinfo->ret.storage == ArgValuetypeInReg)
1947                 cfg->ret_var_is_local = TRUE;
1948
1949         sig_ret = mini_get_underlying_type (sig->ret);
1950         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
1951                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1952                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1953                         printf ("vret_addr = ");
1954                         mono_print_ins (cfg->vret_addr);
1955                 }
1956         }
1957
1958         if (cfg->gen_sdb_seq_points) {
1959                 MonoInst *ins;
1960
1961                 if (cfg->compile_aot) {
1962                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1963                         ins->flags |= MONO_INST_VOLATILE;
1964                         cfg->arch.seq_point_info_var = ins;
1965
1966                         ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1967                         ins->flags |= MONO_INST_VOLATILE;
1968                         cfg->arch.ss_tramp_var = ins;
1969                 }
1970
1971             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1972                 ins->flags |= MONO_INST_VOLATILE;
1973                 cfg->arch.ss_trigger_page_var = ins;
1974         }
1975
1976         if (cfg->method->save_lmf)
1977                 cfg->create_lmf_var = TRUE;
1978
1979         if (cfg->method->save_lmf) {
1980                 cfg->lmf_ir = TRUE;
1981 #if !defined(TARGET_WIN32)
1982                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
1983                         cfg->lmf_ir_mono_lmf = TRUE;
1984 #endif
1985         }
1986 }
1987
1988 static void
1989 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1990 {
1991         MonoInst *ins;
1992
1993         switch (storage) {
1994         case ArgInIReg:
1995                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1996                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1997                 ins->sreg1 = tree->dreg;
1998                 MONO_ADD_INS (cfg->cbb, ins);
1999                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2000                 break;
2001         case ArgInFloatSSEReg:
2002                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2003                 ins->dreg = mono_alloc_freg (cfg);
2004                 ins->sreg1 = tree->dreg;
2005                 MONO_ADD_INS (cfg->cbb, ins);
2006
2007                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2008                 break;
2009         case ArgInDoubleSSEReg:
2010                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2011                 ins->dreg = mono_alloc_freg (cfg);
2012                 ins->sreg1 = tree->dreg;
2013                 MONO_ADD_INS (cfg->cbb, ins);
2014
2015                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2016
2017                 break;
2018         default:
2019                 g_assert_not_reached ();
2020         }
2021 }
2022
2023 static int
2024 arg_storage_to_load_membase (ArgStorage storage)
2025 {
2026         switch (storage) {
2027         case ArgInIReg:
2028 #if defined(__mono_ilp32__)
2029                 return OP_LOADI8_MEMBASE;
2030 #else
2031                 return OP_LOAD_MEMBASE;
2032 #endif
2033         case ArgInDoubleSSEReg:
2034                 return OP_LOADR8_MEMBASE;
2035         case ArgInFloatSSEReg:
2036                 return OP_LOADR4_MEMBASE;
2037         default:
2038                 g_assert_not_reached ();
2039         }
2040
2041         return -1;
2042 }
2043
2044 static void
2045 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2046 {
2047         MonoMethodSignature *tmp_sig;
2048         int sig_reg;
2049
2050         if (call->tail_call)
2051                 NOT_IMPLEMENTED;
2052
2053         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2054
2055         /*
2056          * mono_ArgIterator_Setup assumes the signature cookie is
2057          * passed first and all the arguments which were before it are
2058          * passed on the stack after the signature. So compensate by
2059          * passing a different signature.
2060          */
2061         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2062         tmp_sig->param_count -= call->signature->sentinelpos;
2063         tmp_sig->sentinelpos = 0;
2064         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2065
2066         sig_reg = mono_alloc_ireg (cfg);
2067         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2068
2069         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2070 }
2071
2072 #ifdef ENABLE_LLVM
2073 static inline LLVMArgStorage
2074 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2075 {
2076         switch (storage) {
2077         case ArgInIReg:
2078                 return LLVMArgInIReg;
2079         case ArgNone:
2080                 return LLVMArgNone;
2081         default:
2082                 g_assert_not_reached ();
2083                 return LLVMArgNone;
2084         }
2085 }
2086
2087 LLVMCallInfo*
2088 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2089 {
2090         int i, n;
2091         CallInfo *cinfo;
2092         ArgInfo *ainfo;
2093         int j;
2094         LLVMCallInfo *linfo;
2095         MonoType *t, *sig_ret;
2096
2097         n = sig->param_count + sig->hasthis;
2098         sig_ret = mini_get_underlying_type (sig->ret);
2099
2100         cinfo = get_call_info (cfg->mempool, sig);
2101
2102         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2103
2104         /*
2105          * LLVM always uses the native ABI while we use our own ABI, the
2106          * only difference is the handling of vtypes:
2107          * - we only pass/receive them in registers in some cases, and only
2108          *   in 1 or 2 integer registers.
2109          */
2110         if (cinfo->ret.storage == ArgValuetypeInReg) {
2111                 if (sig->pinvoke) {
2112                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2113                         cfg->disable_llvm = TRUE;
2114                         return linfo;
2115                 }
2116
2117                 linfo->ret.storage = LLVMArgVtypeInReg;
2118                 for (j = 0; j < 2; ++j)
2119                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2120         }
2121
2122         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2123                 /* Vtype returned using a hidden argument */
2124                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2125                 linfo->vret_arg_index = cinfo->vret_arg_index;
2126         }
2127
2128         for (i = 0; i < n; ++i) {
2129                 ainfo = cinfo->args + i;
2130
2131                 if (i >= sig->hasthis)
2132                         t = sig->params [i - sig->hasthis];
2133                 else
2134                         t = &mono_defaults.int_class->byval_arg;
2135
2136                 linfo->args [i].storage = LLVMArgNone;
2137
2138                 switch (ainfo->storage) {
2139                 case ArgInIReg:
2140                         linfo->args [i].storage = LLVMArgInIReg;
2141                         break;
2142                 case ArgInDoubleSSEReg:
2143                 case ArgInFloatSSEReg:
2144                         linfo->args [i].storage = LLVMArgInFPReg;
2145                         break;
2146                 case ArgOnStack:
2147                         if (MONO_TYPE_ISSTRUCT (t)) {
2148                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2149                         } else {
2150                                 linfo->args [i].storage = LLVMArgInIReg;
2151                                 if (!t->byref) {
2152                                         if (t->type == MONO_TYPE_R4)
2153                                                 linfo->args [i].storage = LLVMArgInFPReg;
2154                                         else if (t->type == MONO_TYPE_R8)
2155                                                 linfo->args [i].storage = LLVMArgInFPReg;
2156                                 }
2157                         }
2158                         break;
2159                 case ArgValuetypeInReg:
2160                         if (sig->pinvoke) {
2161                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2162                                 cfg->disable_llvm = TRUE;
2163                                 return linfo;
2164                         }
2165
2166                         linfo->args [i].storage = LLVMArgVtypeInReg;
2167                         for (j = 0; j < 2; ++j)
2168                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2169                         break;
2170                 default:
2171                         cfg->exception_message = g_strdup ("ainfo->storage");
2172                         cfg->disable_llvm = TRUE;
2173                         break;
2174                 }
2175         }
2176
2177         return linfo;
2178 }
2179 #endif
2180
2181 void
2182 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2183 {
2184         MonoInst *arg, *in;
2185         MonoMethodSignature *sig;
2186         MonoType *sig_ret;
2187         int i, n;
2188         CallInfo *cinfo;
2189         ArgInfo *ainfo;
2190
2191         sig = call->signature;
2192         n = sig->param_count + sig->hasthis;
2193
2194         cinfo = get_call_info (cfg->mempool, sig);
2195
2196         sig_ret = sig->ret;
2197
2198         if (COMPILE_LLVM (cfg)) {
2199                 /* We shouldn't be called in the llvm case */
2200                 cfg->disable_llvm = TRUE;
2201                 return;
2202         }
2203
2204         /*
2205          * Emit all arguments which are passed on the stack to prevent register
2206          * allocation problems.
2207          */
2208         for (i = 0; i < n; ++i) {
2209                 MonoType *t;
2210                 ainfo = cinfo->args + i;
2211
2212                 in = call->args [i];
2213
2214                 if (sig->hasthis && i == 0)
2215                         t = &mono_defaults.object_class->byval_arg;
2216                 else
2217                         t = sig->params [i - sig->hasthis];
2218
2219                 t = mini_get_underlying_type (t);
2220                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2221                         if (!t->byref) {
2222                                 if (t->type == MONO_TYPE_R4)
2223                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2224                                 else if (t->type == MONO_TYPE_R8)
2225                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2226                                 else
2227                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2228                         } else {
2229                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2230                         }
2231                         if (cfg->compute_gc_maps) {
2232                                 MonoInst *def;
2233
2234                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2235                         }
2236                 }
2237         }
2238
2239         /*
2240          * Emit all parameters passed in registers in non-reverse order for better readability
2241          * and to help the optimization in emit_prolog ().
2242          */
2243         for (i = 0; i < n; ++i) {
2244                 ainfo = cinfo->args + i;
2245
2246                 in = call->args [i];
2247
2248                 if (ainfo->storage == ArgInIReg)
2249                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2250         }
2251
2252         for (i = n - 1; i >= 0; --i) {
2253                 MonoType *t;
2254
2255                 ainfo = cinfo->args + i;
2256
2257                 in = call->args [i];
2258
2259                 if (sig->hasthis && i == 0)
2260                         t = &mono_defaults.object_class->byval_arg;
2261                 else
2262                         t = sig->params [i - sig->hasthis];
2263                 t = mini_get_underlying_type (t);
2264
2265                 switch (ainfo->storage) {
2266                 case ArgInIReg:
2267                         /* Already done */
2268                         break;
2269                 case ArgInFloatSSEReg:
2270                 case ArgInDoubleSSEReg:
2271                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2272                         break;
2273                 case ArgOnStack:
2274                 case ArgValuetypeInReg:
2275                 case ArgValuetypeAddrInIReg:
2276                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2277                                 MonoInst *call_inst = (MonoInst*)call;
2278                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2279                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2280                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(t))) {
2281                                 guint32 align;
2282                                 guint32 size;
2283
2284                                 if (t->type == MONO_TYPE_TYPEDBYREF) {
2285                                         size = sizeof (MonoTypedRef);
2286                                         align = sizeof (gpointer);
2287                                 }
2288                                 else {
2289                                         if (sig->pinvoke)
2290                                                 size = mono_type_native_stack_size (t, &align);
2291                                         else {
2292                                                 /*
2293                                                  * Other backends use mono_type_stack_size (), but that
2294                                                  * aligns the size to 8, which is larger than the size of
2295                                                  * the source, leading to reads of invalid memory if the
2296                                                  * source is at the end of address space.
2297                                                  */
2298                                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2299                                         }
2300                                 }
2301                                 g_assert (in->klass);
2302
2303                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2304                                         /* Avoid asserts in emit_memcpy () */
2305                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2306                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2307                                         /* Continue normally */
2308                                 }
2309
2310                                 if (size > 0) {
2311                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2312                                         arg->sreg1 = in->dreg;
2313                                         arg->klass = mono_class_from_mono_type (t);
2314                                         arg->backend.size = size;
2315                                         arg->inst_p0 = call;
2316                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2317                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2318
2319                                         MONO_ADD_INS (cfg->cbb, arg);
2320                                 }
2321                         }
2322                         break;
2323                 default:
2324                         g_assert_not_reached ();
2325                 }
2326
2327                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2328                         /* Emit the signature cookie just before the implicit arguments */
2329                         emit_sig_cookie (cfg, call, cinfo);
2330         }
2331
2332         /* Handle the case where there are no implicit arguments */
2333         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2334                 emit_sig_cookie (cfg, call, cinfo);
2335
2336         sig_ret = mini_get_underlying_type (sig->ret);
2337         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2338                 MonoInst *vtarg;
2339
2340                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2341                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2342                                 /*
2343                                  * Tell the JIT to use a more efficient calling convention: call using
2344                                  * OP_CALL, compute the result location after the call, and save the
2345                                  * result there.
2346                                  */
2347                                 call->vret_in_reg = TRUE;
2348                                 /*
2349                                  * Nullify the instruction computing the vret addr to enable
2350                                  * future optimizations.
2351                                  */
2352                                 if (call->vret_var)
2353                                         NULLIFY_INS (call->vret_var);
2354                         } else {
2355                                 if (call->tail_call)
2356                                         NOT_IMPLEMENTED;
2357                                 /*
2358                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2359                                  * the stack. Push the address here, so the call instruction can
2360                                  * access it.
2361                                  */
2362                                 if (!cfg->arch.vret_addr_loc) {
2363                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2364                                         /* Prevent it from being register allocated or optimized away */
2365                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2366                                 }
2367
2368                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2369                         }
2370                 }
2371                 else {
2372                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2373                         vtarg->sreg1 = call->vret_var->dreg;
2374                         vtarg->dreg = mono_alloc_preg (cfg);
2375                         MONO_ADD_INS (cfg->cbb, vtarg);
2376
2377                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2378                 }
2379         }
2380
2381         if (cfg->method->save_lmf) {
2382                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2383                 MONO_ADD_INS (cfg->cbb, arg);
2384         }
2385
2386         call->stack_usage = cinfo->stack_usage;
2387 }
2388
2389 void
2390 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2391 {
2392         MonoInst *arg;
2393         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2394         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2395         int size = ins->backend.size;
2396
2397         if (ainfo->storage == ArgValuetypeInReg) {
2398                 MonoInst *load;
2399                 int part;
2400
2401                 for (part = 0; part < 2; ++part) {
2402                         if (ainfo->pair_storage [part] == ArgNone)
2403                                 continue;
2404
2405                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2406                         load->inst_basereg = src->dreg;
2407                         load->inst_offset = part * sizeof(mgreg_t);
2408
2409                         switch (ainfo->pair_storage [part]) {
2410                         case ArgInIReg:
2411                                 load->dreg = mono_alloc_ireg (cfg);
2412                                 break;
2413                         case ArgInDoubleSSEReg:
2414                         case ArgInFloatSSEReg:
2415                                 load->dreg = mono_alloc_freg (cfg);
2416                                 break;
2417                         default:
2418                                 g_assert_not_reached ();
2419                         }
2420                         MONO_ADD_INS (cfg->cbb, load);
2421
2422                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2423                 }
2424         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2425                 MonoInst *vtaddr, *load;
2426                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2427
2428                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2429                 cfg->has_indirection = TRUE;
2430                 load->inst_p0 = vtaddr;
2431                 vtaddr->flags |= MONO_INST_INDIRECT;
2432                 load->type = STACK_MP;
2433                 load->klass = vtaddr->klass;
2434                 load->dreg = mono_alloc_ireg (cfg);
2435                 MONO_ADD_INS (cfg->cbb, load);
2436                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2437
2438                 if (ainfo->pair_storage [0] == ArgInIReg) {
2439                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2440                         arg->dreg = mono_alloc_ireg (cfg);
2441                         arg->sreg1 = load->dreg;
2442                         arg->inst_imm = 0;
2443                         MONO_ADD_INS (cfg->cbb, arg);
2444                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2445                 } else {
2446                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2447                 }
2448         } else {
2449                 if (size == 8) {
2450                         int dreg = mono_alloc_ireg (cfg);
2451
2452                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2453                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2454                 } else if (size <= 40) {
2455                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2456                 } else {
2457                         // FIXME: Code growth
2458                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2459                 }
2460
2461                 if (cfg->compute_gc_maps) {
2462                         MonoInst *def;
2463                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2464                 }
2465         }
2466 }
2467
2468 void
2469 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2470 {
2471         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2472
2473         if (ret->type == MONO_TYPE_R4) {
2474                 if (COMPILE_LLVM (cfg))
2475                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2476                 else
2477                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2478                 return;
2479         } else if (ret->type == MONO_TYPE_R8) {
2480                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2481                 return;
2482         }
2483
2484         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2485 }
2486
2487 #endif /* DISABLE_JIT */
2488
2489 #define EMIT_COND_BRANCH(ins,cond,sign) \
2490         if (ins->inst_true_bb->native_offset) { \
2491                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2492         } else { \
2493                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2494                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2495             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2496                         x86_branch8 (code, cond, 0, sign); \
2497                 else \
2498                         x86_branch32 (code, cond, 0, sign); \
2499 }
2500
2501 typedef struct {
2502         MonoMethodSignature *sig;
2503         CallInfo *cinfo;
2504 } ArchDynCallInfo;
2505
2506 static gboolean
2507 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2508 {
2509         int i;
2510
2511 #ifdef HOST_WIN32
2512         return FALSE;
2513 #endif
2514
2515         switch (cinfo->ret.storage) {
2516         case ArgNone:
2517         case ArgInIReg:
2518                 break;
2519         case ArgValuetypeInReg: {
2520                 ArgInfo *ainfo = &cinfo->ret;
2521
2522                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2523                         return FALSE;
2524                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2525                         return FALSE;
2526                 break;
2527         }
2528         default:
2529                 return FALSE;
2530         }
2531
2532         for (i = 0; i < cinfo->nargs; ++i) {
2533                 ArgInfo *ainfo = &cinfo->args [i];
2534                 switch (ainfo->storage) {
2535                 case ArgInIReg:
2536                         break;
2537                 case ArgValuetypeInReg:
2538                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2539                                 return FALSE;
2540                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2541                                 return FALSE;
2542                         break;
2543                 default:
2544                         return FALSE;
2545                 }
2546         }
2547
2548         return TRUE;
2549 }
2550
2551 /*
2552  * mono_arch_dyn_call_prepare:
2553  *
2554  *   Return a pointer to an arch-specific structure which contains information
2555  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2556  * supported for SIG.
2557  * This function is equivalent to ffi_prep_cif in libffi.
2558  */
2559 MonoDynCallInfo*
2560 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2561 {
2562         ArchDynCallInfo *info;
2563         CallInfo *cinfo;
2564
2565         cinfo = get_call_info (NULL, sig);
2566
2567         if (!dyn_call_supported (sig, cinfo)) {
2568                 g_free (cinfo);
2569                 return NULL;
2570         }
2571
2572         info = g_new0 (ArchDynCallInfo, 1);
2573         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2574         info->sig = sig;
2575         info->cinfo = cinfo;
2576
2577         return (MonoDynCallInfo*)info;
2578 }
2579
2580 /*
2581  * mono_arch_dyn_call_free:
2582  *
2583  *   Free a MonoDynCallInfo structure.
2584  */
2585 void
2586 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2587 {
2588         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2589
2590         g_free (ainfo->cinfo);
2591         g_free (ainfo);
2592 }
2593
2594 #if !defined(__native_client__)
2595 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2596 #define GREG_TO_PTR(greg) (gpointer)(greg)
2597 #else
2598 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2599 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2600 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2601 #endif
2602
2603 /*
2604  * mono_arch_get_start_dyn_call:
2605  *
2606  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2607  * store the result into BUF.
2608  * ARGS should be an array of pointers pointing to the arguments.
2609  * RET should point to a memory buffer large enought to hold the result of the
2610  * call.
2611  * This function should be as fast as possible, any work which does not depend
2612  * on the actual values of the arguments should be done in
2613  * mono_arch_dyn_call_prepare ().
2614  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2615  * libffi.
2616  */
2617 void
2618 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2619 {
2620         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2621         DynCallArgs *p = (DynCallArgs*)buf;
2622         int arg_index, greg, i, pindex;
2623         MonoMethodSignature *sig = dinfo->sig;
2624
2625         g_assert (buf_len >= sizeof (DynCallArgs));
2626
2627         p->res = 0;
2628         p->ret = ret;
2629
2630         arg_index = 0;
2631         greg = 0;
2632         pindex = 0;
2633
2634         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2635                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2636                 if (!sig->hasthis)
2637                         pindex = 1;
2638         }
2639
2640         if (dinfo->cinfo->vtype_retaddr)
2641                 p->regs [greg ++] = PTR_TO_GREG(ret);
2642
2643         for (i = pindex; i < sig->param_count; i++) {
2644                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2645                 gpointer *arg = args [arg_index ++];
2646
2647                 if (t->byref) {
2648                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2649                         continue;
2650                 }
2651
2652                 switch (t->type) {
2653                 case MONO_TYPE_STRING:
2654                 case MONO_TYPE_CLASS:
2655                 case MONO_TYPE_ARRAY:
2656                 case MONO_TYPE_SZARRAY:
2657                 case MONO_TYPE_OBJECT:
2658                 case MONO_TYPE_PTR:
2659                 case MONO_TYPE_I:
2660                 case MONO_TYPE_U:
2661 #if !defined(__mono_ilp32__)
2662                 case MONO_TYPE_I8:
2663                 case MONO_TYPE_U8:
2664 #endif
2665                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2666                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2667                         break;
2668 #if defined(__mono_ilp32__)
2669                 case MONO_TYPE_I8:
2670                 case MONO_TYPE_U8:
2671                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2672                         p->regs [greg ++] = *(guint64*)(arg);
2673                         break;
2674 #endif
2675                 case MONO_TYPE_U1:
2676                         p->regs [greg ++] = *(guint8*)(arg);
2677                         break;
2678                 case MONO_TYPE_I1:
2679                         p->regs [greg ++] = *(gint8*)(arg);
2680                         break;
2681                 case MONO_TYPE_I2:
2682                         p->regs [greg ++] = *(gint16*)(arg);
2683                         break;
2684                 case MONO_TYPE_U2:
2685                         p->regs [greg ++] = *(guint16*)(arg);
2686                         break;
2687                 case MONO_TYPE_I4:
2688                         p->regs [greg ++] = *(gint32*)(arg);
2689                         break;
2690                 case MONO_TYPE_U4:
2691                         p->regs [greg ++] = *(guint32*)(arg);
2692                         break;
2693                 case MONO_TYPE_GENERICINST:
2694                     if (MONO_TYPE_IS_REFERENCE (t)) {
2695                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2696                                 break;
2697                         } else {
2698                                 /* Fall through */
2699                         }
2700                 case MONO_TYPE_VALUETYPE: {
2701                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2702
2703                         g_assert (ainfo->storage == ArgValuetypeInReg);
2704                         if (ainfo->pair_storage [0] != ArgNone) {
2705                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2706                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2707                         }
2708                         if (ainfo->pair_storage [1] != ArgNone) {
2709                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2710                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2711                         }
2712                         break;
2713                 }
2714                 default:
2715                         g_assert_not_reached ();
2716                 }
2717         }
2718
2719         g_assert (greg <= PARAM_REGS);
2720 }
2721
2722 /*
2723  * mono_arch_finish_dyn_call:
2724  *
2725  *   Store the result of a dyn call into the return value buffer passed to
2726  * start_dyn_call ().
2727  * This function should be as fast as possible, any work which does not depend
2728  * on the actual values of the arguments should be done in
2729  * mono_arch_dyn_call_prepare ().
2730  */
2731 void
2732 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2733 {
2734         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2735         MonoMethodSignature *sig = dinfo->sig;
2736         guint8 *ret = ((DynCallArgs*)buf)->ret;
2737         mgreg_t res = ((DynCallArgs*)buf)->res;
2738         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2739
2740         switch (sig_ret->type) {
2741         case MONO_TYPE_VOID:
2742                 *(gpointer*)ret = NULL;
2743                 break;
2744         case MONO_TYPE_STRING:
2745         case MONO_TYPE_CLASS:
2746         case MONO_TYPE_ARRAY:
2747         case MONO_TYPE_SZARRAY:
2748         case MONO_TYPE_OBJECT:
2749         case MONO_TYPE_I:
2750         case MONO_TYPE_U:
2751         case MONO_TYPE_PTR:
2752                 *(gpointer*)ret = GREG_TO_PTR(res);
2753                 break;
2754         case MONO_TYPE_I1:
2755                 *(gint8*)ret = res;
2756                 break;
2757         case MONO_TYPE_U1:
2758                 *(guint8*)ret = res;
2759                 break;
2760         case MONO_TYPE_I2:
2761                 *(gint16*)ret = res;
2762                 break;
2763         case MONO_TYPE_U2:
2764                 *(guint16*)ret = res;
2765                 break;
2766         case MONO_TYPE_I4:
2767                 *(gint32*)ret = res;
2768                 break;
2769         case MONO_TYPE_U4:
2770                 *(guint32*)ret = res;
2771                 break;
2772         case MONO_TYPE_I8:
2773                 *(gint64*)ret = res;
2774                 break;
2775         case MONO_TYPE_U8:
2776                 *(guint64*)ret = res;
2777                 break;
2778         case MONO_TYPE_GENERICINST:
2779                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2780                         *(gpointer*)ret = GREG_TO_PTR(res);
2781                         break;
2782                 } else {
2783                         /* Fall through */
2784                 }
2785         case MONO_TYPE_VALUETYPE:
2786                 if (dinfo->cinfo->vtype_retaddr) {
2787                         /* Nothing to do */
2788                 } else {
2789                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2790
2791                         g_assert (ainfo->storage == ArgValuetypeInReg);
2792
2793                         if (ainfo->pair_storage [0] != ArgNone) {
2794                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2795                                 ((mgreg_t*)ret)[0] = res;
2796                         }
2797
2798                         g_assert (ainfo->pair_storage [1] == ArgNone);
2799                 }
2800                 break;
2801         default:
2802                 g_assert_not_reached ();
2803         }
2804 }
2805
2806 /* emit an exception if condition is fail */
2807 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2808         do {                                                        \
2809                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2810                 if (tins == NULL) {                                                                             \
2811                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2812                                         MONO_PATCH_INFO_EXC, exc_name);  \
2813                         x86_branch32 (code, cond, 0, signed);               \
2814                 } else {        \
2815                         EMIT_COND_BRANCH (tins, cond, signed);  \
2816                 }                       \
2817         } while (0);
2818
2819 #define EMIT_FPCOMPARE(code) do { \
2820         amd64_fcompp (code); \
2821         amd64_fnstsw (code); \
2822 } while (0);
2823
2824 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2825     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2826         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2827         amd64_ ##op (code); \
2828         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2829         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2830 } while (0);
2831
2832 static guint8*
2833 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2834 {
2835         gboolean no_patch = FALSE;
2836
2837         /*
2838          * FIXME: Add support for thunks
2839          */
2840         {
2841                 gboolean near_call = FALSE;
2842
2843                 /*
2844                  * Indirect calls are expensive so try to make a near call if possible.
2845                  * The caller memory is allocated by the code manager so it is
2846                  * guaranteed to be at a 32 bit offset.
2847                  */
2848
2849                 if (patch_type != MONO_PATCH_INFO_ABS) {
2850                         /* The target is in memory allocated using the code manager */
2851                         near_call = TRUE;
2852
2853                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2854                                 if (((MonoMethod*)data)->klass->image->aot_module)
2855                                         /* The callee might be an AOT method */
2856                                         near_call = FALSE;
2857                                 if (((MonoMethod*)data)->dynamic)
2858                                         /* The target is in malloc-ed memory */
2859                                         near_call = FALSE;
2860                         }
2861
2862                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2863                                 /*
2864                                  * The call might go directly to a native function without
2865                                  * the wrapper.
2866                                  */
2867                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2868                                 if (mi) {
2869                                         gconstpointer target = mono_icall_get_wrapper (mi);
2870                                         if ((((guint64)target) >> 32) != 0)
2871                                                 near_call = FALSE;
2872                                 }
2873                         }
2874                 }
2875                 else {
2876                         MonoJumpInfo *jinfo = NULL;
2877
2878                         if (cfg->abs_patches)
2879                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2880                         if (jinfo) {
2881                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2882                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2883                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2884                                                 near_call = TRUE;
2885                                         no_patch = TRUE;
2886                                 } else {
2887                                         /*
2888                                          * This is not really an optimization, but required because the
2889                                          * generic class init trampolines use R11 to pass the vtable.
2890                                          */
2891                                         near_call = TRUE;
2892                                 }
2893                         } else {
2894                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2895                                 if (info) {
2896                                         if (info->func == info->wrapper) {
2897                                                 /* No wrapper */
2898                                                 if ((((guint64)info->func) >> 32) == 0)
2899                                                         near_call = TRUE;
2900                                         }
2901                                         else {
2902                                                 /* See the comment in mono_codegen () */
2903                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2904                                                         near_call = TRUE;
2905                                         }
2906                                 }
2907                                 else if ((((guint64)data) >> 32) == 0) {
2908                                         near_call = TRUE;
2909                                         no_patch = TRUE;
2910                                 }
2911                         }
2912                 }
2913
2914                 if (cfg->method->dynamic)
2915                         /* These methods are allocated using malloc */
2916                         near_call = FALSE;
2917
2918 #ifdef MONO_ARCH_NOMAP32BIT
2919                 near_call = FALSE;
2920 #endif
2921 #if defined(__native_client__)
2922                 /* Always use near_call == TRUE for Native Client */
2923                 near_call = TRUE;
2924 #endif
2925                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2926                 if (optimize_for_xen)
2927                         near_call = FALSE;
2928
2929                 if (cfg->compile_aot) {
2930                         near_call = TRUE;
2931                         no_patch = TRUE;
2932                 }
2933
2934                 if (near_call) {
2935                         /*
2936                          * Align the call displacement to an address divisible by 4 so it does
2937                          * not span cache lines. This is required for code patching to work on SMP
2938                          * systems.
2939                          */
2940                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2941                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2942                                 amd64_padding (code, pad_size);
2943                         }
2944                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2945                         amd64_call_code (code, 0);
2946                 }
2947                 else {
2948                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2949                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2950                         amd64_call_reg (code, GP_SCRATCH_REG);
2951                 }
2952         }
2953
2954         return code;
2955 }
2956
2957 static inline guint8*
2958 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2959 {
2960 #ifdef TARGET_WIN32
2961         if (win64_adjust_stack)
2962                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2963 #endif
2964         code = emit_call_body (cfg, code, patch_type, data);
2965 #ifdef TARGET_WIN32
2966         if (win64_adjust_stack)
2967                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2968 #endif
2969
2970         return code;
2971 }
2972
2973 static inline int
2974 store_membase_imm_to_store_membase_reg (int opcode)
2975 {
2976         switch (opcode) {
2977         case OP_STORE_MEMBASE_IMM:
2978                 return OP_STORE_MEMBASE_REG;
2979         case OP_STOREI4_MEMBASE_IMM:
2980                 return OP_STOREI4_MEMBASE_REG;
2981         case OP_STOREI8_MEMBASE_IMM:
2982                 return OP_STOREI8_MEMBASE_REG;
2983         }
2984
2985         return -1;
2986 }
2987
2988 #ifndef DISABLE_JIT
2989
2990 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2991
2992 /*
2993  * mono_arch_peephole_pass_1:
2994  *
2995  *   Perform peephole opts which should/can be performed before local regalloc
2996  */
2997 void
2998 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2999 {
3000         MonoInst *ins, *n;
3001
3002         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3003                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3004
3005                 switch (ins->opcode) {
3006                 case OP_ADD_IMM:
3007                 case OP_IADD_IMM:
3008                 case OP_LADD_IMM:
3009                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3010                                 /*
3011                                  * X86_LEA is like ADD, but doesn't have the
3012                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3013                                  * its operand to 64 bit.
3014                                  */
3015                                 ins->opcode = OP_X86_LEA_MEMBASE;
3016                                 ins->inst_basereg = ins->sreg1;
3017                         }
3018                         break;
3019                 case OP_LXOR:
3020                 case OP_IXOR:
3021                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3022                                 MonoInst *ins2;
3023
3024                                 /*
3025                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3026                                  * the latter has length 2-3 instead of 6 (reverse constant
3027                                  * propagation). These instruction sequences are very common
3028                                  * in the initlocals bblock.
3029                                  */
3030                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3031                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3032                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3033                                                 ins2->sreg1 = ins->dreg;
3034                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3035                                                 /* Continue */
3036                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3037                                                 NULLIFY_INS (ins2);
3038                                                 /* Continue */
3039                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3040                                                 /* Continue */
3041                                         } else {
3042                                                 break;
3043                                         }
3044                                 }
3045                         }
3046                         break;
3047                 case OP_COMPARE_IMM:
3048                 case OP_LCOMPARE_IMM:
3049                         /* OP_COMPARE_IMM (reg, 0)
3050                          * -->
3051                          * OP_AMD64_TEST_NULL (reg)
3052                          */
3053                         if (!ins->inst_imm)
3054                                 ins->opcode = OP_AMD64_TEST_NULL;
3055                         break;
3056                 case OP_ICOMPARE_IMM:
3057                         if (!ins->inst_imm)
3058                                 ins->opcode = OP_X86_TEST_NULL;
3059                         break;
3060                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3061                         /*
3062                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3063                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3064                          * -->
3065                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3066                          * OP_COMPARE_IMM reg, imm
3067                          *
3068                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3069                          */
3070                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3071                             ins->inst_basereg == last_ins->inst_destbasereg &&
3072                             ins->inst_offset == last_ins->inst_offset) {
3073                                         ins->opcode = OP_ICOMPARE_IMM;
3074                                         ins->sreg1 = last_ins->sreg1;
3075
3076                                         /* check if we can remove cmp reg,0 with test null */
3077                                         if (!ins->inst_imm)
3078                                                 ins->opcode = OP_X86_TEST_NULL;
3079                                 }
3080
3081                         break;
3082                 }
3083
3084                 mono_peephole_ins (bb, ins);
3085         }
3086 }
3087
3088 void
3089 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3090 {
3091         MonoInst *ins, *n;
3092
3093         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3094                 switch (ins->opcode) {
3095                 case OP_ICONST:
3096                 case OP_I8CONST: {
3097                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3098                         /* reg = 0 -> XOR (reg, reg) */
3099                         /* XOR sets cflags on x86, so we cant do it always */
3100                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3101                                 ins->opcode = OP_LXOR;
3102                                 ins->sreg1 = ins->dreg;
3103                                 ins->sreg2 = ins->dreg;
3104                                 /* Fall through */
3105                         } else {
3106                                 break;
3107                         }
3108                 }
3109                 case OP_LXOR:
3110                         /*
3111                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3112                          * 0 result into 64 bits.
3113                          */
3114                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3115                                 ins->opcode = OP_IXOR;
3116                         }
3117                         /* Fall through */
3118                 case OP_IXOR:
3119                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3120                                 MonoInst *ins2;
3121
3122                                 /*
3123                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3124                                  * the latter has length 2-3 instead of 6 (reverse constant
3125                                  * propagation). These instruction sequences are very common
3126                                  * in the initlocals bblock.
3127                                  */
3128                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3129                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3130                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3131                                                 ins2->sreg1 = ins->dreg;
3132                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3133                                                 /* Continue */
3134                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3135                                                 NULLIFY_INS (ins2);
3136                                                 /* Continue */
3137                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3138                                                 /* Continue */
3139                                         } else {
3140                                                 break;
3141                                         }
3142                                 }
3143                         }
3144                         break;
3145                 case OP_IADD_IMM:
3146                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3147                                 ins->opcode = OP_X86_INC_REG;
3148                         break;
3149                 case OP_ISUB_IMM:
3150                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3151                                 ins->opcode = OP_X86_DEC_REG;
3152                         break;
3153                 }
3154
3155                 mono_peephole_ins (bb, ins);
3156         }
3157 }
3158
3159 #define NEW_INS(cfg,ins,dest,op) do {   \
3160                 MONO_INST_NEW ((cfg), (dest), (op)); \
3161         (dest)->cil_code = (ins)->cil_code; \
3162         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3163         } while (0)
3164
3165 /*
3166  * mono_arch_lowering_pass:
3167  *
3168  *  Converts complex opcodes into simpler ones so that each IR instruction
3169  * corresponds to one machine instruction.
3170  */
3171 void
3172 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3173 {
3174         MonoInst *ins, *n, *temp;
3175
3176         /*
3177          * FIXME: Need to add more instructions, but the current machine
3178          * description can't model some parts of the composite instructions like
3179          * cdq.
3180          */
3181         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3182                 switch (ins->opcode) {
3183                 case OP_DIV_IMM:
3184                 case OP_REM_IMM:
3185                 case OP_IDIV_IMM:
3186                 case OP_IDIV_UN_IMM:
3187                 case OP_IREM_UN_IMM:
3188                 case OP_LREM_IMM:
3189                 case OP_IREM_IMM:
3190                         mono_decompose_op_imm (cfg, bb, ins);
3191                         break;
3192                 case OP_COMPARE_IMM:
3193                 case OP_LCOMPARE_IMM:
3194                         if (!amd64_use_imm32 (ins->inst_imm)) {
3195                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3196                                 temp->inst_c0 = ins->inst_imm;
3197                                 temp->dreg = mono_alloc_ireg (cfg);
3198                                 ins->opcode = OP_COMPARE;
3199                                 ins->sreg2 = temp->dreg;
3200                         }
3201                         break;
3202 #ifndef __mono_ilp32__
3203                 case OP_LOAD_MEMBASE:
3204 #endif
3205                 case OP_LOADI8_MEMBASE:
3206 #ifndef __native_client_codegen__
3207                 /*  Don't generate memindex opcodes (to simplify */
3208                 /*  read sandboxing) */
3209                         if (!amd64_use_imm32 (ins->inst_offset)) {
3210                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3211                                 temp->inst_c0 = ins->inst_offset;
3212                                 temp->dreg = mono_alloc_ireg (cfg);
3213                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3214                                 ins->inst_indexreg = temp->dreg;
3215                         }
3216 #endif
3217                         break;
3218 #ifndef __mono_ilp32__
3219                 case OP_STORE_MEMBASE_IMM:
3220 #endif
3221                 case OP_STOREI8_MEMBASE_IMM:
3222                         if (!amd64_use_imm32 (ins->inst_imm)) {
3223                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3224                                 temp->inst_c0 = ins->inst_imm;
3225                                 temp->dreg = mono_alloc_ireg (cfg);
3226                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3227                                 ins->sreg1 = temp->dreg;
3228                         }
3229                         break;
3230 #ifdef MONO_ARCH_SIMD_INTRINSICS
3231                 case OP_EXPAND_I1: {
3232                                 int temp_reg1 = mono_alloc_ireg (cfg);
3233                                 int temp_reg2 = mono_alloc_ireg (cfg);
3234                                 int original_reg = ins->sreg1;
3235
3236                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3237                                 temp->sreg1 = original_reg;
3238                                 temp->dreg = temp_reg1;
3239
3240                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3241                                 temp->sreg1 = temp_reg1;
3242                                 temp->dreg = temp_reg2;
3243                                 temp->inst_imm = 8;
3244
3245                                 NEW_INS (cfg, ins, temp, OP_LOR);
3246                                 temp->sreg1 = temp->dreg = temp_reg2;
3247                                 temp->sreg2 = temp_reg1;
3248
3249                                 ins->opcode = OP_EXPAND_I2;
3250                                 ins->sreg1 = temp_reg2;
3251                         }
3252                         break;
3253 #endif
3254                 default:
3255                         break;
3256                 }
3257         }
3258
3259         bb->max_vreg = cfg->next_vreg;
3260 }
3261
3262 static const int
3263 branch_cc_table [] = {
3264         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3265         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3266         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3267 };
3268
3269 /* Maps CMP_... constants to X86_CC_... constants */
3270 static const int
3271 cc_table [] = {
3272         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3273         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3274 };
3275
3276 static const int
3277 cc_signed_table [] = {
3278         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3279         FALSE, FALSE, FALSE, FALSE
3280 };
3281
3282 /*#include "cprop.c"*/
3283
3284 static unsigned char*
3285 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3286 {
3287         if (size == 8)
3288                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3289         else
3290                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3291
3292         if (size == 1)
3293                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3294         else if (size == 2)
3295                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3296         return code;
3297 }
3298
3299 static unsigned char*
3300 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3301 {
3302         int sreg = tree->sreg1;
3303         int need_touch = FALSE;
3304
3305 #if defined(TARGET_WIN32)
3306         need_touch = TRUE;
3307 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3308         if (!tree->flags & MONO_INST_INIT)
3309                 need_touch = TRUE;
3310 #endif
3311
3312         if (need_touch) {
3313                 guint8* br[5];
3314
3315                 /*
3316                  * Under Windows:
3317                  * If requested stack size is larger than one page,
3318                  * perform stack-touch operation
3319                  */
3320                 /*
3321                  * Generate stack probe code.
3322                  * Under Windows, it is necessary to allocate one page at a time,
3323                  * "touching" stack after each successful sub-allocation. This is
3324                  * because of the way stack growth is implemented - there is a
3325                  * guard page before the lowest stack page that is currently commited.
3326                  * Stack normally grows sequentially so OS traps access to the
3327                  * guard page and commits more pages when needed.
3328                  */
3329                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3330                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3331
3332                 br[2] = code; /* loop */
3333                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3334                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3335                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3336                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3337                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3338                 amd64_patch (br[3], br[2]);
3339                 amd64_test_reg_reg (code, sreg, sreg);
3340                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3341                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3342
3343                 br[1] = code; x86_jump8 (code, 0);
3344
3345                 amd64_patch (br[0], code);
3346                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3347                 amd64_patch (br[1], code);
3348                 amd64_patch (br[4], code);
3349         }
3350         else
3351                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3352
3353         if (tree->flags & MONO_INST_INIT) {
3354                 int offset = 0;
3355                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3356                         amd64_push_reg (code, AMD64_RAX);
3357                         offset += 8;
3358                 }
3359                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3360                         amd64_push_reg (code, AMD64_RCX);
3361                         offset += 8;
3362                 }
3363                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3364                         amd64_push_reg (code, AMD64_RDI);
3365                         offset += 8;
3366                 }
3367
3368                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3369                 if (sreg != AMD64_RCX)
3370                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3371                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3372
3373                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3374                 if (cfg->param_area)
3375                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3376                 amd64_cld (code);
3377 #if defined(__default_codegen__)
3378                 amd64_prefix (code, X86_REP_PREFIX);
3379                 amd64_stosl (code);
3380 #elif defined(__native_client_codegen__)
3381                 /* NaCl stos pseudo-instruction */
3382                 amd64_codegen_pre(code);
3383                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3384                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3385                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3386                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3387                 amd64_prefix (code, X86_REP_PREFIX);
3388                 amd64_stosl (code);
3389                 amd64_codegen_post(code);
3390 #endif /* __native_client_codegen__ */
3391
3392                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3393                         amd64_pop_reg (code, AMD64_RDI);
3394                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3395                         amd64_pop_reg (code, AMD64_RCX);
3396                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3397                         amd64_pop_reg (code, AMD64_RAX);
3398         }
3399         return code;
3400 }
3401
3402 static guint8*
3403 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3404 {
3405         CallInfo *cinfo;
3406         guint32 quad;
3407
3408         /* Move return value to the target register */
3409         /* FIXME: do this in the local reg allocator */
3410         switch (ins->opcode) {
3411         case OP_CALL:
3412         case OP_CALL_REG:
3413         case OP_CALL_MEMBASE:
3414         case OP_LCALL:
3415         case OP_LCALL_REG:
3416         case OP_LCALL_MEMBASE:
3417                 g_assert (ins->dreg == AMD64_RAX);
3418                 break;
3419         case OP_FCALL:
3420         case OP_FCALL_REG:
3421         case OP_FCALL_MEMBASE: {
3422                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3423                 if (rtype->type == MONO_TYPE_R4) {
3424                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3425                 }
3426                 else {
3427                         if (ins->dreg != AMD64_XMM0)
3428                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3429                 }
3430                 break;
3431         }
3432         case OP_RCALL:
3433         case OP_RCALL_REG:
3434         case OP_RCALL_MEMBASE:
3435                 if (ins->dreg != AMD64_XMM0)
3436                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3437                 break;
3438         case OP_VCALL:
3439         case OP_VCALL_REG:
3440         case OP_VCALL_MEMBASE:
3441         case OP_VCALL2:
3442         case OP_VCALL2_REG:
3443         case OP_VCALL2_MEMBASE:
3444                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3445                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3446                         MonoInst *loc = cfg->arch.vret_addr_loc;
3447
3448                         /* Load the destination address */
3449                         g_assert (loc->opcode == OP_REGOFFSET);
3450                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3451
3452                         for (quad = 0; quad < 2; quad ++) {
3453                                 switch (cinfo->ret.pair_storage [quad]) {
3454                                 case ArgInIReg:
3455                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3456                                         break;
3457                                 case ArgInFloatSSEReg:
3458                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3459                                         break;
3460                                 case ArgInDoubleSSEReg:
3461                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3462                                         break;
3463                                 case ArgNone:
3464                                         break;
3465                                 default:
3466                                         NOT_IMPLEMENTED;
3467                                 }
3468                         }
3469                 }
3470                 break;
3471         }
3472
3473         return code;
3474 }
3475
3476 #endif /* DISABLE_JIT */
3477
3478 #ifdef __APPLE__
3479 static int tls_gs_offset;
3480 #endif
3481
3482 gboolean
3483 mono_amd64_have_tls_get (void)
3484 {
3485 #ifdef TARGET_MACH
3486         static gboolean have_tls_get = FALSE;
3487         static gboolean inited = FALSE;
3488
3489         if (inited)
3490                 return have_tls_get;
3491
3492 #if MONO_HAVE_FAST_TLS
3493         guint8 *ins = (guint8*)pthread_getspecific;
3494
3495         /*
3496          * We're looking for these two instructions:
3497          *
3498          * mov    %gs:[offset](,%rdi,8),%rax
3499          * retq
3500          */
3501         have_tls_get = ins [0] == 0x65 &&
3502                        ins [1] == 0x48 &&
3503                        ins [2] == 0x8b &&
3504                        ins [3] == 0x04 &&
3505                        ins [4] == 0xfd &&
3506                        ins [6] == 0x00 &&
3507                        ins [7] == 0x00 &&
3508                        ins [8] == 0x00 &&
3509                        ins [9] == 0xc3;
3510
3511         tls_gs_offset = ins[5];
3512 #endif
3513
3514         inited = TRUE;
3515
3516         return have_tls_get;
3517 #elif defined(TARGET_ANDROID)
3518         return FALSE;
3519 #else
3520         return TRUE;
3521 #endif
3522 }
3523
3524 int
3525 mono_amd64_get_tls_gs_offset (void)
3526 {
3527 #ifdef TARGET_OSX
3528         return tls_gs_offset;
3529 #else
3530         g_assert_not_reached ();
3531         return -1;
3532 #endif
3533 }
3534
3535 /*
3536  * mono_amd64_emit_tls_get:
3537  * @code: buffer to store code to
3538  * @dreg: hard register where to place the result
3539  * @tls_offset: offset info
3540  *
3541  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3542  * the dreg register the item in the thread local storage identified
3543  * by tls_offset.
3544  *
3545  * Returns: a pointer to the end of the stored code
3546  */
3547 guint8*
3548 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3549 {
3550 #ifdef TARGET_WIN32
3551         if (tls_offset < 64) {
3552                 x86_prefix (code, X86_GS_PREFIX);
3553                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3554         } else {
3555                 guint8 *buf [16];
3556
3557                 g_assert (tls_offset < 0x440);
3558                 /* Load TEB->TlsExpansionSlots */
3559                 x86_prefix (code, X86_GS_PREFIX);
3560                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3561                 amd64_test_reg_reg (code, dreg, dreg);
3562                 buf [0] = code;
3563                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3564                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3565                 amd64_patch (buf [0], code);
3566         }
3567 #elif defined(__APPLE__)
3568         x86_prefix (code, X86_GS_PREFIX);
3569         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3570 #else
3571         if (optimize_for_xen) {
3572                 x86_prefix (code, X86_FS_PREFIX);
3573                 amd64_mov_reg_mem (code, dreg, 0, 8);
3574                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3575         } else {
3576                 x86_prefix (code, X86_FS_PREFIX);
3577                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3578         }
3579 #endif
3580         return code;
3581 }
3582
3583 static guint8*
3584 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3585 {
3586         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3587 #ifdef TARGET_OSX
3588         if (dreg != offset_reg)
3589                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3590         amd64_prefix (code, X86_GS_PREFIX);
3591         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3592 #elif defined(__linux__)
3593         int tmpreg = -1;
3594
3595         if (dreg == offset_reg) {
3596                 /* Use a temporary reg by saving it to the redzone */
3597                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3598                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3599                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3600                 offset_reg = tmpreg;
3601         }
3602         x86_prefix (code, X86_FS_PREFIX);
3603         amd64_mov_reg_mem (code, dreg, 0, 8);
3604         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3605         if (tmpreg != -1)
3606                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3607 #else
3608         g_assert_not_reached ();
3609 #endif
3610         return code;
3611 }
3612
3613 static guint8*
3614 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3615 {
3616 #ifdef TARGET_WIN32
3617         g_assert_not_reached ();
3618 #elif defined(__APPLE__)
3619         x86_prefix (code, X86_GS_PREFIX);
3620         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3621 #else
3622         g_assert (!optimize_for_xen);
3623         x86_prefix (code, X86_FS_PREFIX);
3624         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3625 #endif
3626         return code;
3627 }
3628
3629 static guint8*
3630 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3631 {
3632         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3633 #ifdef TARGET_WIN32
3634         g_assert_not_reached ();
3635 #elif defined(__APPLE__)
3636         x86_prefix (code, X86_GS_PREFIX);
3637         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3638 #else
3639         x86_prefix (code, X86_FS_PREFIX);
3640         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3641 #endif
3642         return code;
3643 }
3644
3645  /*
3646  * mono_arch_translate_tls_offset:
3647  *
3648  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3649  */
3650 int
3651 mono_arch_translate_tls_offset (int offset)
3652 {
3653 #ifdef __APPLE__
3654         return tls_gs_offset + (offset * 8);
3655 #else
3656         return offset;
3657 #endif
3658 }
3659
3660 /*
3661  * emit_setup_lmf:
3662  *
3663  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3664  */
3665 static guint8*
3666 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3667 {
3668         /*
3669          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3670          */
3671         /*
3672          * sp is saved right before calls but we need to save it here too so
3673          * async stack walks would work.
3674          */
3675         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3676         /* Save rbp */
3677         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3678         if (cfg->arch.omit_fp && cfa_offset != -1)
3679                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3680
3681         /* These can't contain refs */
3682         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3683         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3684         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3685         /* These are handled automatically by the stack marking code */
3686         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3687
3688         return code;
3689 }
3690
3691 #define REAL_PRINT_REG(text,reg) \
3692 mono_assert (reg >= 0); \
3693 amd64_push_reg (code, AMD64_RAX); \
3694 amd64_push_reg (code, AMD64_RDX); \
3695 amd64_push_reg (code, AMD64_RCX); \
3696 amd64_push_reg (code, reg); \
3697 amd64_push_imm (code, reg); \
3698 amd64_push_imm (code, text " %d %p\n"); \
3699 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3700 amd64_call_reg (code, AMD64_RAX); \
3701 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3702 amd64_pop_reg (code, AMD64_RCX); \
3703 amd64_pop_reg (code, AMD64_RDX); \
3704 amd64_pop_reg (code, AMD64_RAX);
3705
3706 /* benchmark and set based on cpu */
3707 #define LOOP_ALIGNMENT 8
3708 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3709
3710 #ifndef DISABLE_JIT
3711 void
3712 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3713 {
3714         MonoInst *ins;
3715         MonoCallInst *call;
3716         guint offset;
3717         guint8 *code = cfg->native_code + cfg->code_len;
3718         int max_len;
3719
3720         /* Fix max_offset estimate for each successor bb */
3721         if (cfg->opt & MONO_OPT_BRANCH) {
3722                 int current_offset = cfg->code_len;
3723                 MonoBasicBlock *current_bb;
3724                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3725                         current_bb->max_offset = current_offset;
3726                         current_offset += current_bb->max_length;
3727                 }
3728         }
3729
3730         if (cfg->opt & MONO_OPT_LOOP) {
3731                 int pad, align = LOOP_ALIGNMENT;
3732                 /* set alignment depending on cpu */
3733                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3734                         pad = align - pad;
3735                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3736                         amd64_padding (code, pad);
3737                         cfg->code_len += pad;
3738                         bb->native_offset = cfg->code_len;
3739                 }
3740         }
3741
3742 #if defined(__native_client_codegen__)
3743         /* For Native Client, all indirect call/jump targets must be */
3744         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3745         /* indirectly as well.                                       */
3746         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3747                                       (bb->flags & BB_EXCEPTION_HANDLER);
3748
3749         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3750                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3751                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3752                 cfg->code_len += pad;
3753                 bb->native_offset = cfg->code_len;
3754         }
3755 #endif  /*__native_client_codegen__*/
3756
3757         if (cfg->verbose_level > 2)
3758                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3759
3760         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3761                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3762                 g_assert (!cfg->compile_aot);
3763
3764                 cov->data [bb->dfn].cil_code = bb->cil_code;
3765                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3766                 /* this is not thread save, but good enough */
3767                 amd64_inc_membase (code, AMD64_R11, 0);
3768         }
3769
3770         offset = code - cfg->native_code;
3771
3772         mono_debug_open_block (cfg, bb, offset);
3773
3774     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3775                 x86_breakpoint (code);
3776
3777         MONO_BB_FOR_EACH_INS (bb, ins) {
3778                 offset = code - cfg->native_code;
3779
3780                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3781
3782 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3783
3784                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3785                         cfg->code_size *= 2;
3786                         cfg->native_code = mono_realloc_native_code(cfg);
3787                         code = cfg->native_code + offset;
3788                         cfg->stat_code_reallocs++;
3789                 }
3790
3791                 if (cfg->debug_info)
3792                         mono_debug_record_line_number (cfg, ins, offset);
3793
3794                 switch (ins->opcode) {
3795                 case OP_BIGMUL:
3796                         amd64_mul_reg (code, ins->sreg2, TRUE);
3797                         break;
3798                 case OP_BIGMUL_UN:
3799                         amd64_mul_reg (code, ins->sreg2, FALSE);
3800                         break;
3801                 case OP_X86_SETEQ_MEMBASE:
3802                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3803                         break;
3804                 case OP_STOREI1_MEMBASE_IMM:
3805                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3806                         break;
3807                 case OP_STOREI2_MEMBASE_IMM:
3808                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3809                         break;
3810                 case OP_STOREI4_MEMBASE_IMM:
3811                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3812                         break;
3813                 case OP_STOREI1_MEMBASE_REG:
3814                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3815                         break;
3816                 case OP_STOREI2_MEMBASE_REG:
3817                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3818                         break;
3819                 /* In AMD64 NaCl, pointers are 4 bytes, */
3820                 /*  so STORE_* != STOREI8_*. Likewise below. */
3821                 case OP_STORE_MEMBASE_REG:
3822                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3823                         break;
3824                 case OP_STOREI8_MEMBASE_REG:
3825                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3826                         break;
3827                 case OP_STOREI4_MEMBASE_REG:
3828                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3829                         break;
3830                 case OP_STORE_MEMBASE_IMM:
3831 #ifndef __native_client_codegen__
3832                         /* In NaCl, this could be a PCONST type, which could */
3833                         /* mean a pointer type was copied directly into the  */
3834                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3835                         /* the value would be 0x00000000FFFFFFFF which is    */
3836                         /* not proper for an imm32 unless you cast it.       */
3837                         g_assert (amd64_is_imm32 (ins->inst_imm));
3838 #endif
3839                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3840                         break;
3841                 case OP_STOREI8_MEMBASE_IMM:
3842                         g_assert (amd64_is_imm32 (ins->inst_imm));
3843                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3844                         break;
3845                 case OP_LOAD_MEM:
3846 #ifdef __mono_ilp32__
3847                         /* In ILP32, pointers are 4 bytes, so separate these */
3848                         /* cases, use literal 8 below where we really want 8 */
3849                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3850                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3851                         break;
3852 #endif
3853                 case OP_LOADI8_MEM:
3854                         // FIXME: Decompose this earlier
3855                         if (amd64_use_imm32 (ins->inst_imm))
3856                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3857                         else {
3858                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3859                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3860                         }
3861                         break;
3862                 case OP_LOADI4_MEM:
3863                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3864                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3865                         break;
3866                 case OP_LOADU4_MEM:
3867                         // FIXME: Decompose this earlier
3868                         if (amd64_use_imm32 (ins->inst_imm))
3869                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3870                         else {
3871                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3872                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3873                         }
3874                         break;
3875                 case OP_LOADU1_MEM:
3876                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3877                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3878                         break;
3879                 case OP_LOADU2_MEM:
3880                         /* For NaCl, pointers are 4 bytes, so separate these */
3881                         /* cases, use literal 8 below where we really want 8 */
3882                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3883                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3884                         break;
3885                 case OP_LOAD_MEMBASE:
3886                         g_assert (amd64_is_imm32 (ins->inst_offset));
3887                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3888                         break;
3889                 case OP_LOADI8_MEMBASE:
3890                         /* Use literal 8 instead of sizeof pointer or */
3891                         /* register, we really want 8 for this opcode */
3892                         g_assert (amd64_is_imm32 (ins->inst_offset));
3893                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3894                         break;
3895                 case OP_LOADI4_MEMBASE:
3896                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3897                         break;
3898                 case OP_LOADU4_MEMBASE:
3899                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3900                         break;
3901                 case OP_LOADU1_MEMBASE:
3902                         /* The cpu zero extends the result into 64 bits */
3903                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3904                         break;
3905                 case OP_LOADI1_MEMBASE:
3906                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3907                         break;
3908                 case OP_LOADU2_MEMBASE:
3909                         /* The cpu zero extends the result into 64 bits */
3910                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3911                         break;
3912                 case OP_LOADI2_MEMBASE:
3913                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3914                         break;
3915                 case OP_AMD64_LOADI8_MEMINDEX:
3916                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3917                         break;
3918                 case OP_LCONV_TO_I1:
3919                 case OP_ICONV_TO_I1:
3920                 case OP_SEXT_I1:
3921                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3922                         break;
3923                 case OP_LCONV_TO_I2:
3924                 case OP_ICONV_TO_I2:
3925                 case OP_SEXT_I2:
3926                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3927                         break;
3928                 case OP_LCONV_TO_U1:
3929                 case OP_ICONV_TO_U1:
3930                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3931                         break;
3932                 case OP_LCONV_TO_U2:
3933                 case OP_ICONV_TO_U2:
3934                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3935                         break;
3936                 case OP_ZEXT_I4:
3937                         /* Clean out the upper word */
3938                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3939                         break;
3940                 case OP_SEXT_I4:
3941                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3942                         break;
3943                 case OP_COMPARE:
3944                 case OP_LCOMPARE:
3945                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3946                         break;
3947                 case OP_COMPARE_IMM:
3948 #if defined(__mono_ilp32__)
3949                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3950                         g_assert (amd64_is_imm32 (ins->inst_imm));
3951                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3952                         break;
3953 #endif
3954                 case OP_LCOMPARE_IMM:
3955                         g_assert (amd64_is_imm32 (ins->inst_imm));
3956                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3957                         break;
3958                 case OP_X86_COMPARE_REG_MEMBASE:
3959                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3960                         break;
3961                 case OP_X86_TEST_NULL:
3962                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3963                         break;
3964                 case OP_AMD64_TEST_NULL:
3965                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3966                         break;
3967
3968                 case OP_X86_ADD_REG_MEMBASE:
3969                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3970                         break;
3971                 case OP_X86_SUB_REG_MEMBASE:
3972                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3973                         break;
3974                 case OP_X86_AND_REG_MEMBASE:
3975                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3976                         break;
3977                 case OP_X86_OR_REG_MEMBASE:
3978                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3979                         break;
3980                 case OP_X86_XOR_REG_MEMBASE:
3981                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3982                         break;
3983
3984                 case OP_X86_ADD_MEMBASE_IMM:
3985                         /* FIXME: Make a 64 version too */
3986                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3987                         break;
3988                 case OP_X86_SUB_MEMBASE_IMM:
3989                         g_assert (amd64_is_imm32 (ins->inst_imm));
3990                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3991                         break;
3992                 case OP_X86_AND_MEMBASE_IMM:
3993                         g_assert (amd64_is_imm32 (ins->inst_imm));
3994                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3995                         break;
3996                 case OP_X86_OR_MEMBASE_IMM:
3997                         g_assert (amd64_is_imm32 (ins->inst_imm));
3998                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3999                         break;
4000                 case OP_X86_XOR_MEMBASE_IMM:
4001                         g_assert (amd64_is_imm32 (ins->inst_imm));
4002                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4003                         break;
4004                 case OP_X86_ADD_MEMBASE_REG:
4005                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4006                         break;
4007                 case OP_X86_SUB_MEMBASE_REG:
4008                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4009                         break;
4010                 case OP_X86_AND_MEMBASE_REG:
4011                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4012                         break;
4013                 case OP_X86_OR_MEMBASE_REG:
4014                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4015                         break;
4016                 case OP_X86_XOR_MEMBASE_REG:
4017                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4018                         break;
4019                 case OP_X86_INC_MEMBASE:
4020                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4021                         break;
4022                 case OP_X86_INC_REG:
4023                         amd64_inc_reg_size (code, ins->dreg, 4);
4024                         break;
4025                 case OP_X86_DEC_MEMBASE:
4026                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4027                         break;
4028                 case OP_X86_DEC_REG:
4029                         amd64_dec_reg_size (code, ins->dreg, 4);
4030                         break;
4031                 case OP_X86_MUL_REG_MEMBASE:
4032                 case OP_X86_MUL_MEMBASE_REG:
4033                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4034                         break;
4035                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4036                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4037                         break;
4038                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4039                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4040                         break;
4041                 case OP_AMD64_COMPARE_MEMBASE_REG:
4042                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4043                         break;
4044                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4045                         g_assert (amd64_is_imm32 (ins->inst_imm));
4046                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4047                         break;
4048                 case OP_X86_COMPARE_MEMBASE8_IMM:
4049                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4050                         break;
4051                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4052                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4053                         break;
4054                 case OP_AMD64_COMPARE_REG_MEMBASE:
4055                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4056                         break;
4057
4058                 case OP_AMD64_ADD_REG_MEMBASE:
4059                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4060                         break;
4061                 case OP_AMD64_SUB_REG_MEMBASE:
4062                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4063                         break;
4064                 case OP_AMD64_AND_REG_MEMBASE:
4065                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4066                         break;
4067                 case OP_AMD64_OR_REG_MEMBASE:
4068                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4069                         break;
4070                 case OP_AMD64_XOR_REG_MEMBASE:
4071                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4072                         break;
4073
4074                 case OP_AMD64_ADD_MEMBASE_REG:
4075                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4076                         break;
4077                 case OP_AMD64_SUB_MEMBASE_REG:
4078                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4079                         break;
4080                 case OP_AMD64_AND_MEMBASE_REG:
4081                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4082                         break;
4083                 case OP_AMD64_OR_MEMBASE_REG:
4084                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4085                         break;
4086                 case OP_AMD64_XOR_MEMBASE_REG:
4087                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4088                         break;
4089
4090                 case OP_AMD64_ADD_MEMBASE_IMM:
4091                         g_assert (amd64_is_imm32 (ins->inst_imm));
4092                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4093                         break;
4094                 case OP_AMD64_SUB_MEMBASE_IMM:
4095                         g_assert (amd64_is_imm32 (ins->inst_imm));
4096                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4097                         break;
4098                 case OP_AMD64_AND_MEMBASE_IMM:
4099                         g_assert (amd64_is_imm32 (ins->inst_imm));
4100                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4101                         break;
4102                 case OP_AMD64_OR_MEMBASE_IMM:
4103                         g_assert (amd64_is_imm32 (ins->inst_imm));
4104                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4105                         break;
4106                 case OP_AMD64_XOR_MEMBASE_IMM:
4107                         g_assert (amd64_is_imm32 (ins->inst_imm));
4108                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4109                         break;
4110
4111                 case OP_BREAK:
4112                         amd64_breakpoint (code);
4113                         break;
4114                 case OP_RELAXED_NOP:
4115                         x86_prefix (code, X86_REP_PREFIX);
4116                         x86_nop (code);
4117                         break;
4118                 case OP_HARD_NOP:
4119                         x86_nop (code);
4120                         break;
4121                 case OP_NOP:
4122                 case OP_DUMMY_USE:
4123                 case OP_DUMMY_STORE:
4124                 case OP_DUMMY_ICONST:
4125                 case OP_DUMMY_R8CONST:
4126                 case OP_NOT_REACHED:
4127                 case OP_NOT_NULL:
4128                         break;
4129                 case OP_IL_SEQ_POINT:
4130                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4131                         break;
4132                 case OP_SEQ_POINT: {
4133                         int i;
4134
4135                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4136                                 if (cfg->compile_aot) {
4137                                         MonoInst *var = cfg->arch.ss_tramp_var;
4138                                         guint8 *label;
4139
4140                                         /* Load ss_tramp_var */
4141                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4142                                         /* Load the trampoline address */
4143                                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4144                                         /* Call it if it is non-null */
4145                                         amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4146                                         label = code;
4147                                         amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4148                                         amd64_call_reg (code, AMD64_R11);
4149                                         amd64_patch (label, code);
4150                                 } else {
4151                                         /*
4152                                          * Read from the single stepping trigger page. This will cause a
4153                                          * SIGSEGV when single stepping is enabled.
4154                                          * We do this _before_ the breakpoint, so single stepping after
4155                                          * a breakpoint is hit will step to the next IL offset.
4156                                          */
4157                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
4158
4159                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4160                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4161                                 }
4162                         }
4163
4164                         /*
4165                          * This is the address which is saved in seq points,
4166                          */
4167                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4168
4169                         if (cfg->compile_aot) {
4170                                 guint32 offset = code - cfg->native_code;
4171                                 guint32 val;
4172                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4173                                 guint8 *label;
4174
4175                                 /* Load info var */
4176                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4177                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4178                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4179                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4180                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4181                                 label = code;
4182                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4183                                 /* Call the trampoline */
4184                                 amd64_call_reg (code, AMD64_R11);
4185                                 amd64_patch (label, code);
4186                         } else {
4187                                 /*
4188                                  * A placeholder for a possible breakpoint inserted by
4189                                  * mono_arch_set_breakpoint ().
4190                                  */
4191                                 for (i = 0; i < breakpoint_size; ++i)
4192                                         x86_nop (code);
4193                         }
4194                         /*
4195                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4196                          * to another IL offset.
4197                          */
4198                         x86_nop (code);
4199                         break;
4200                 }
4201                 case OP_ADDCC:
4202                 case OP_LADDCC:
4203                 case OP_LADD:
4204                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4205                         break;
4206                 case OP_ADC:
4207                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4208                         break;
4209                 case OP_ADD_IMM:
4210                 case OP_LADD_IMM:
4211                         g_assert (amd64_is_imm32 (ins->inst_imm));
4212                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4213                         break;
4214                 case OP_ADC_IMM:
4215                         g_assert (amd64_is_imm32 (ins->inst_imm));
4216                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4217                         break;
4218                 case OP_SUBCC:
4219                 case OP_LSUBCC:
4220                 case OP_LSUB:
4221                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4222                         break;
4223                 case OP_SBB:
4224                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4225                         break;
4226                 case OP_SUB_IMM:
4227                 case OP_LSUB_IMM:
4228                         g_assert (amd64_is_imm32 (ins->inst_imm));
4229                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4230                         break;
4231                 case OP_SBB_IMM:
4232                         g_assert (amd64_is_imm32 (ins->inst_imm));
4233                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4234                         break;
4235                 case OP_LAND:
4236                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4237                         break;
4238                 case OP_AND_IMM:
4239                 case OP_LAND_IMM:
4240                         g_assert (amd64_is_imm32 (ins->inst_imm));
4241                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4242                         break;
4243                 case OP_LMUL:
4244                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4245                         break;
4246                 case OP_MUL_IMM:
4247                 case OP_LMUL_IMM:
4248                 case OP_IMUL_IMM: {
4249                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4250
4251                         switch (ins->inst_imm) {
4252                         case 2:
4253                                 /* MOV r1, r2 */
4254                                 /* ADD r1, r1 */
4255                                 if (ins->dreg != ins->sreg1)
4256                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4257                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4258                                 break;
4259                         case 3:
4260                                 /* LEA r1, [r2 + r2*2] */
4261                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4262                                 break;
4263                         case 5:
4264                                 /* LEA r1, [r2 + r2*4] */
4265                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4266                                 break;
4267                         case 6:
4268                                 /* LEA r1, [r2 + r2*2] */
4269                                 /* ADD r1, r1          */
4270                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4271                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4272                                 break;
4273                         case 9:
4274                                 /* LEA r1, [r2 + r2*8] */
4275                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4276                                 break;
4277                         case 10:
4278                                 /* LEA r1, [r2 + r2*4] */
4279                                 /* ADD r1, r1          */
4280                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4281                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4282                                 break;
4283                         case 12:
4284                                 /* LEA r1, [r2 + r2*2] */
4285                                 /* SHL r1, 2           */
4286                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4287                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4288                                 break;
4289                         case 25:
4290                                 /* LEA r1, [r2 + r2*4] */
4291                                 /* LEA r1, [r1 + r1*4] */
4292                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4293                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4294                                 break;
4295                         case 100:
4296                                 /* LEA r1, [r2 + r2*4] */
4297                                 /* SHL r1, 2           */
4298                                 /* LEA r1, [r1 + r1*4] */
4299                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4300                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4301                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4302                                 break;
4303                         default:
4304                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4305                                 break;
4306                         }
4307                         break;
4308                 }
4309                 case OP_LDIV:
4310                 case OP_LREM:
4311 #if defined( __native_client_codegen__ )
4312                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4313                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4314 #endif
4315                         /* Regalloc magic makes the div/rem cases the same */
4316                         if (ins->sreg2 == AMD64_RDX) {
4317                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4318                                 amd64_cdq (code);
4319                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4320                         } else {
4321                                 amd64_cdq (code);
4322                                 amd64_div_reg (code, ins->sreg2, TRUE);
4323                         }
4324                         break;
4325                 case OP_LDIV_UN:
4326                 case OP_LREM_UN:
4327 #if defined( __native_client_codegen__ )
4328                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4329                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4330 #endif
4331                         if (ins->sreg2 == AMD64_RDX) {
4332                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4333                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4334                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4335                         } else {
4336                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4337                                 amd64_div_reg (code, ins->sreg2, FALSE);
4338                         }
4339                         break;
4340                 case OP_IDIV:
4341                 case OP_IREM:
4342 #if defined( __native_client_codegen__ )
4343                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4344                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4345 #endif
4346                         if (ins->sreg2 == AMD64_RDX) {
4347                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4348                                 amd64_cdq_size (code, 4);
4349                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4350                         } else {
4351                                 amd64_cdq_size (code, 4);
4352                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4353                         }
4354                         break;
4355                 case OP_IDIV_UN:
4356                 case OP_IREM_UN:
4357 #if defined( __native_client_codegen__ )
4358                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4359                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4360 #endif
4361                         if (ins->sreg2 == AMD64_RDX) {
4362                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4363                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4364                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4365                         } else {
4366                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4367                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4368                         }
4369                         break;
4370                 case OP_LMUL_OVF:
4371                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4372                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4373                         break;
4374                 case OP_LOR:
4375                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4376                         break;
4377                 case OP_OR_IMM:
4378                 case OP_LOR_IMM:
4379                         g_assert (amd64_is_imm32 (ins->inst_imm));
4380                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4381                         break;
4382                 case OP_LXOR:
4383                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4384                         break;
4385                 case OP_XOR_IMM:
4386                 case OP_LXOR_IMM:
4387                         g_assert (amd64_is_imm32 (ins->inst_imm));
4388                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4389                         break;
4390                 case OP_LSHL:
4391                         g_assert (ins->sreg2 == AMD64_RCX);
4392                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4393                         break;
4394                 case OP_LSHR:
4395                         g_assert (ins->sreg2 == AMD64_RCX);
4396                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4397                         break;
4398                 case OP_SHR_IMM:
4399                 case OP_LSHR_IMM:
4400                         g_assert (amd64_is_imm32 (ins->inst_imm));
4401                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4402                         break;
4403                 case OP_SHR_UN_IMM:
4404                         g_assert (amd64_is_imm32 (ins->inst_imm));
4405                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4406                         break;
4407                 case OP_LSHR_UN_IMM:
4408                         g_assert (amd64_is_imm32 (ins->inst_imm));
4409                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4410                         break;
4411                 case OP_LSHR_UN:
4412                         g_assert (ins->sreg2 == AMD64_RCX);
4413                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4414                         break;
4415                 case OP_SHL_IMM:
4416                 case OP_LSHL_IMM:
4417                         g_assert (amd64_is_imm32 (ins->inst_imm));
4418                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4419                         break;
4420
4421                 case OP_IADDCC:
4422                 case OP_IADD:
4423                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4424                         break;
4425                 case OP_IADC:
4426                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4427                         break;
4428                 case OP_IADD_IMM:
4429                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4430                         break;
4431                 case OP_IADC_IMM:
4432                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4433                         break;
4434                 case OP_ISUBCC:
4435                 case OP_ISUB:
4436                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4437                         break;
4438                 case OP_ISBB:
4439                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4440                         break;
4441                 case OP_ISUB_IMM:
4442                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4443                         break;
4444                 case OP_ISBB_IMM:
4445                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4446                         break;
4447                 case OP_IAND:
4448                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4449                         break;
4450                 case OP_IAND_IMM:
4451                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4452                         break;
4453                 case OP_IOR:
4454                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4455                         break;
4456                 case OP_IOR_IMM:
4457                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4458                         break;
4459                 case OP_IXOR:
4460                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4461                         break;
4462                 case OP_IXOR_IMM:
4463                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4464                         break;
4465                 case OP_INEG:
4466                         amd64_neg_reg_size (code, ins->sreg1, 4);
4467                         break;
4468                 case OP_INOT:
4469                         amd64_not_reg_size (code, ins->sreg1, 4);
4470                         break;
4471                 case OP_ISHL:
4472                         g_assert (ins->sreg2 == AMD64_RCX);
4473                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4474                         break;
4475                 case OP_ISHR:
4476                         g_assert (ins->sreg2 == AMD64_RCX);
4477                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4478                         break;
4479                 case OP_ISHR_IMM:
4480                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4481                         break;
4482                 case OP_ISHR_UN_IMM:
4483                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4484                         break;
4485                 case OP_ISHR_UN:
4486                         g_assert (ins->sreg2 == AMD64_RCX);
4487                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4488                         break;
4489                 case OP_ISHL_IMM:
4490                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4491                         break;
4492                 case OP_IMUL:
4493                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4494                         break;
4495                 case OP_IMUL_OVF:
4496                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4497                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4498                         break;
4499                 case OP_IMUL_OVF_UN:
4500                 case OP_LMUL_OVF_UN: {
4501                         /* the mul operation and the exception check should most likely be split */
4502                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4503                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4504                         /*g_assert (ins->sreg2 == X86_EAX);
4505                         g_assert (ins->dreg == X86_EAX);*/
4506                         if (ins->sreg2 == X86_EAX) {
4507                                 non_eax_reg = ins->sreg1;
4508                         } else if (ins->sreg1 == X86_EAX) {
4509                                 non_eax_reg = ins->sreg2;
4510                         } else {
4511                                 /* no need to save since we're going to store to it anyway */
4512                                 if (ins->dreg != X86_EAX) {
4513                                         saved_eax = TRUE;
4514                                         amd64_push_reg (code, X86_EAX);
4515                                 }
4516                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4517                                 non_eax_reg = ins->sreg2;
4518                         }
4519                         if (ins->dreg == X86_EDX) {
4520                                 if (!saved_eax) {
4521                                         saved_eax = TRUE;
4522                                         amd64_push_reg (code, X86_EAX);
4523                                 }
4524                         } else {
4525                                 saved_edx = TRUE;
4526                                 amd64_push_reg (code, X86_EDX);
4527                         }
4528                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4529                         /* save before the check since pop and mov don't change the flags */
4530                         if (ins->dreg != X86_EAX)
4531                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4532                         if (saved_edx)
4533                                 amd64_pop_reg (code, X86_EDX);
4534                         if (saved_eax)
4535                                 amd64_pop_reg (code, X86_EAX);
4536                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4537                         break;
4538                 }
4539                 case OP_ICOMPARE:
4540                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4541                         break;
4542                 case OP_ICOMPARE_IMM:
4543                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4544                         break;
4545                 case OP_IBEQ:
4546                 case OP_IBLT:
4547                 case OP_IBGT:
4548                 case OP_IBGE:
4549                 case OP_IBLE:
4550                 case OP_LBEQ:
4551                 case OP_LBLT:
4552                 case OP_LBGT:
4553                 case OP_LBGE:
4554                 case OP_LBLE:
4555                 case OP_IBNE_UN:
4556                 case OP_IBLT_UN:
4557                 case OP_IBGT_UN:
4558                 case OP_IBGE_UN:
4559                 case OP_IBLE_UN:
4560                 case OP_LBNE_UN:
4561                 case OP_LBLT_UN:
4562                 case OP_LBGT_UN:
4563                 case OP_LBGE_UN:
4564                 case OP_LBLE_UN:
4565                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4566                         break;
4567
4568                 case OP_CMOV_IEQ:
4569                 case OP_CMOV_IGE:
4570                 case OP_CMOV_IGT:
4571                 case OP_CMOV_ILE:
4572                 case OP_CMOV_ILT:
4573                 case OP_CMOV_INE_UN:
4574                 case OP_CMOV_IGE_UN:
4575                 case OP_CMOV_IGT_UN:
4576                 case OP_CMOV_ILE_UN:
4577                 case OP_CMOV_ILT_UN:
4578                 case OP_CMOV_LEQ:
4579                 case OP_CMOV_LGE:
4580                 case OP_CMOV_LGT:
4581                 case OP_CMOV_LLE:
4582                 case OP_CMOV_LLT:
4583                 case OP_CMOV_LNE_UN:
4584                 case OP_CMOV_LGE_UN:
4585                 case OP_CMOV_LGT_UN:
4586                 case OP_CMOV_LLE_UN:
4587                 case OP_CMOV_LLT_UN:
4588                         g_assert (ins->dreg == ins->sreg1);
4589                         /* This needs to operate on 64 bit values */
4590                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4591                         break;
4592
4593                 case OP_LNOT:
4594                         amd64_not_reg (code, ins->sreg1);
4595                         break;
4596                 case OP_LNEG:
4597                         amd64_neg_reg (code, ins->sreg1);
4598                         break;
4599
4600                 case OP_ICONST:
4601                 case OP_I8CONST:
4602                         if (amd64_use_imm32 (ins->inst_c0))
4603                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4604                         else
4605                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4606                         break;
4607                 case OP_AOTCONST:
4608                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4609                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4610                         break;
4611                 case OP_JUMP_TABLE:
4612                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4613                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4614                         break;
4615                 case OP_MOVE:
4616                         if (ins->dreg != ins->sreg1)
4617                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4618                         break;
4619                 case OP_AMD64_SET_XMMREG_R4: {
4620                         if (cfg->r4fp) {
4621                                 if (ins->dreg != ins->sreg1)
4622                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4623                         } else {
4624                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4625                         }
4626                         break;
4627                 }
4628                 case OP_AMD64_SET_XMMREG_R8: {
4629                         if (ins->dreg != ins->sreg1)
4630                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4631                         break;
4632                 }
4633                 case OP_TAILCALL: {
4634                         MonoCallInst *call = (MonoCallInst*)ins;
4635                         int i, save_area_offset;
4636
4637                         g_assert (!cfg->method->save_lmf);
4638
4639                         /* Restore callee saved registers */
4640                         save_area_offset = cfg->arch.reg_save_area_offset;
4641                         for (i = 0; i < AMD64_NREG; ++i)
4642                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4643                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4644                                         save_area_offset += 8;
4645                                 }
4646
4647                         if (cfg->arch.omit_fp) {
4648                                 if (cfg->arch.stack_alloc_size)
4649                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4650                                 // FIXME:
4651                                 if (call->stack_usage)
4652                                         NOT_IMPLEMENTED;
4653                         } else {
4654                                 /* Copy arguments on the stack to our argument area */
4655                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4656                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4657                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4658                                 }
4659
4660                                 amd64_leave (code);
4661                         }
4662
4663                         offset = code - cfg->native_code;
4664                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4665                         if (cfg->compile_aot)
4666                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4667                         else
4668                                 amd64_set_reg_template (code, AMD64_R11);
4669                         amd64_jump_reg (code, AMD64_R11);
4670                         ins->flags |= MONO_INST_GC_CALLSITE;
4671                         ins->backend.pc_offset = code - cfg->native_code;
4672                         break;
4673                 }
4674                 case OP_CHECK_THIS:
4675                         /* ensure ins->sreg1 is not NULL */
4676                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4677                         break;
4678                 case OP_ARGLIST: {
4679                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4680                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4681                         break;
4682                 }
4683                 case OP_CALL:
4684                 case OP_FCALL:
4685                 case OP_RCALL:
4686                 case OP_LCALL:
4687                 case OP_VCALL:
4688                 case OP_VCALL2:
4689                 case OP_VOIDCALL:
4690                         call = (MonoCallInst*)ins;
4691                         /*
4692                          * The AMD64 ABI forces callers to know about varargs.
4693                          */
4694                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4695                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4696                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4697                                 /*
4698                                  * Since the unmanaged calling convention doesn't contain a
4699                                  * 'vararg' entry, we have to treat every pinvoke call as a
4700                                  * potential vararg call.
4701                                  */
4702                                 guint32 nregs, i;
4703                                 nregs = 0;
4704                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4705                                         if (call->used_fregs & (1 << i))
4706                                                 nregs ++;
4707                                 if (!nregs)
4708                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4709                                 else
4710                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4711                         }
4712
4713                         if (ins->flags & MONO_INST_HAS_METHOD)
4714                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4715                         else
4716                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4717                         ins->flags |= MONO_INST_GC_CALLSITE;
4718                         ins->backend.pc_offset = code - cfg->native_code;
4719                         code = emit_move_return_value (cfg, ins, code);
4720                         break;
4721                 case OP_FCALL_REG:
4722                 case OP_RCALL_REG:
4723                 case OP_LCALL_REG:
4724                 case OP_VCALL_REG:
4725                 case OP_VCALL2_REG:
4726                 case OP_VOIDCALL_REG:
4727                 case OP_CALL_REG:
4728                         call = (MonoCallInst*)ins;
4729
4730                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4731                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4732                                 ins->sreg1 = AMD64_R11;
4733                         }
4734
4735                         /*
4736                          * The AMD64 ABI forces callers to know about varargs.
4737                          */
4738                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4739                                 if (ins->sreg1 == AMD64_RAX) {
4740                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4741                                         ins->sreg1 = AMD64_R11;
4742                                 }
4743                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4744                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4745                                 /*
4746                                  * Since the unmanaged calling convention doesn't contain a
4747                                  * 'vararg' entry, we have to treat every pinvoke call as a
4748                                  * potential vararg call.
4749                                  */
4750                                 guint32 nregs, i;
4751                                 nregs = 0;
4752                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4753                                         if (call->used_fregs & (1 << i))
4754                                                 nregs ++;
4755                                 if (ins->sreg1 == AMD64_RAX) {
4756                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4757                                         ins->sreg1 = AMD64_R11;
4758                                 }
4759                                 if (!nregs)
4760                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4761                                 else
4762                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4763                         }
4764
4765                         amd64_call_reg (code, ins->sreg1);
4766                         ins->flags |= MONO_INST_GC_CALLSITE;
4767                         ins->backend.pc_offset = code - cfg->native_code;
4768                         code = emit_move_return_value (cfg, ins, code);
4769                         break;
4770                 case OP_FCALL_MEMBASE:
4771                 case OP_RCALL_MEMBASE:
4772                 case OP_LCALL_MEMBASE:
4773                 case OP_VCALL_MEMBASE:
4774                 case OP_VCALL2_MEMBASE:
4775                 case OP_VOIDCALL_MEMBASE:
4776                 case OP_CALL_MEMBASE:
4777                         call = (MonoCallInst*)ins;
4778
4779                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4780                         ins->flags |= MONO_INST_GC_CALLSITE;
4781                         ins->backend.pc_offset = code - cfg->native_code;
4782                         code = emit_move_return_value (cfg, ins, code);
4783                         break;
4784                 case OP_DYN_CALL: {
4785                         int i;
4786                         MonoInst *var = cfg->dyn_call_var;
4787
4788                         g_assert (var->opcode == OP_REGOFFSET);
4789
4790                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4791                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4792                         /* r10 = ftn */
4793                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4794
4795                         /* Save args buffer */
4796                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4797
4798                         /* Set argument registers */
4799                         for (i = 0; i < PARAM_REGS; ++i)
4800                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4801
4802                         /* Make the call */
4803                         amd64_call_reg (code, AMD64_R10);
4804
4805                         ins->flags |= MONO_INST_GC_CALLSITE;
4806                         ins->backend.pc_offset = code - cfg->native_code;
4807
4808                         /* Save result */
4809                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4810                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4811                         break;
4812                 }
4813                 case OP_AMD64_SAVE_SP_TO_LMF: {
4814                         MonoInst *lmf_var = cfg->lmf_var;
4815                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4816                         break;
4817                 }
4818                 case OP_X86_PUSH:
4819                         g_assert_not_reached ();
4820                         amd64_push_reg (code, ins->sreg1);
4821                         break;
4822                 case OP_X86_PUSH_IMM:
4823                         g_assert_not_reached ();
4824                         g_assert (amd64_is_imm32 (ins->inst_imm));
4825                         amd64_push_imm (code, ins->inst_imm);
4826                         break;
4827                 case OP_X86_PUSH_MEMBASE:
4828                         g_assert_not_reached ();
4829                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4830                         break;
4831                 case OP_X86_PUSH_OBJ: {
4832                         int size = ALIGN_TO (ins->inst_imm, 8);
4833
4834                         g_assert_not_reached ();
4835
4836                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4837                         amd64_push_reg (code, AMD64_RDI);
4838                         amd64_push_reg (code, AMD64_RSI);
4839                         amd64_push_reg (code, AMD64_RCX);
4840                         if (ins->inst_offset)
4841                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4842                         else
4843                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4844                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4845                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4846                         amd64_cld (code);
4847                         amd64_prefix (code, X86_REP_PREFIX);
4848                         amd64_movsd (code);
4849                         amd64_pop_reg (code, AMD64_RCX);
4850                         amd64_pop_reg (code, AMD64_RSI);
4851                         amd64_pop_reg (code, AMD64_RDI);
4852                         break;
4853                 }
4854                 case OP_GENERIC_CLASS_INIT: {
4855                         static int byte_offset = -1;
4856                         static guint8 bitmask;
4857                         guint8 *jump;
4858
4859                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4860
4861                         if (byte_offset < 0)
4862                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
4863
4864                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
4865                         jump = code;
4866                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4867
4868                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4869                         ins->flags |= MONO_INST_GC_CALLSITE;
4870                         ins->backend.pc_offset = code - cfg->native_code;
4871
4872                         x86_patch (jump, code);
4873                         break;
4874                 }
4875
4876                 case OP_X86_LEA:
4877                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4878                         break;
4879                 case OP_X86_LEA_MEMBASE:
4880                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4881                         break;
4882                 case OP_X86_XCHG:
4883                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4884                         break;
4885                 case OP_LOCALLOC:
4886                         /* keep alignment */
4887                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4888                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4889                         code = mono_emit_stack_alloc (cfg, code, ins);
4890                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4891                         if (cfg->param_area)
4892                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4893                         break;
4894                 case OP_LOCALLOC_IMM: {
4895                         guint32 size = ins->inst_imm;
4896                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4897
4898                         if (ins->flags & MONO_INST_INIT) {
4899                                 if (size < 64) {
4900                                         int i;
4901
4902                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4903                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4904
4905                                         for (i = 0; i < size; i += 8)
4906                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4907                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4908                                 } else {
4909                                         amd64_mov_reg_imm (code, ins->dreg, size);
4910                                         ins->sreg1 = ins->dreg;
4911
4912                                         code = mono_emit_stack_alloc (cfg, code, ins);
4913                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4914                                 }
4915                         } else {
4916                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4917                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4918                         }
4919                         if (cfg->param_area)
4920                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4921                         break;
4922                 }
4923                 case OP_THROW: {
4924                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4925                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4926                                              (gpointer)"mono_arch_throw_exception", FALSE);
4927                         ins->flags |= MONO_INST_GC_CALLSITE;
4928                         ins->backend.pc_offset = code - cfg->native_code;
4929                         break;
4930                 }
4931                 case OP_RETHROW: {
4932                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4933                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4934                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4935                         ins->flags |= MONO_INST_GC_CALLSITE;
4936                         ins->backend.pc_offset = code - cfg->native_code;
4937                         break;
4938                 }
4939                 case OP_CALL_HANDLER:
4940                         /* Align stack */
4941                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4942                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4943                         amd64_call_imm (code, 0);
4944                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4945                         /* Restore stack alignment */
4946                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4947                         break;
4948                 case OP_START_HANDLER: {
4949                         /* Even though we're saving RSP, use sizeof */
4950                         /* gpointer because spvar is of type IntPtr */
4951                         /* see: mono_create_spvar_for_region */
4952                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4953                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4954
4955                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4956                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4957                                 cfg->param_area) {
4958                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4959                         }
4960                         break;
4961                 }
4962                 case OP_ENDFINALLY: {
4963                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4964                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4965                         amd64_ret (code);
4966                         break;
4967                 }
4968                 case OP_ENDFILTER: {
4969                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4970                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4971                         /* The local allocator will put the result into RAX */
4972                         amd64_ret (code);
4973                         break;
4974                 }
4975                 case OP_GET_EX_OBJ:
4976                         if (ins->dreg != AMD64_RAX)
4977                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4978                         break;
4979                 case OP_LABEL:
4980                         ins->inst_c0 = code - cfg->native_code;
4981                         break;
4982                 case OP_BR:
4983                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4984                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4985                         //break;
4986                                 if (ins->inst_target_bb->native_offset) {
4987                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4988                                 } else {
4989                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4990                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4991                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4992                                                 x86_jump8 (code, 0);
4993                                         else
4994                                                 x86_jump32 (code, 0);
4995                         }
4996                         break;
4997                 case OP_BR_REG:
4998                         amd64_jump_reg (code, ins->sreg1);
4999                         break;
5000                 case OP_ICNEQ:
5001                 case OP_ICGE:
5002                 case OP_ICLE:
5003                 case OP_ICGE_UN:
5004                 case OP_ICLE_UN:
5005
5006                 case OP_CEQ:
5007                 case OP_LCEQ:
5008                 case OP_ICEQ:
5009                 case OP_CLT:
5010                 case OP_LCLT:
5011                 case OP_ICLT:
5012                 case OP_CGT:
5013                 case OP_ICGT:
5014                 case OP_LCGT:
5015                 case OP_CLT_UN:
5016                 case OP_LCLT_UN:
5017                 case OP_ICLT_UN:
5018                 case OP_CGT_UN:
5019                 case OP_LCGT_UN:
5020                 case OP_ICGT_UN:
5021                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5022                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5023                         break;
5024                 case OP_COND_EXC_EQ:
5025                 case OP_COND_EXC_NE_UN:
5026                 case OP_COND_EXC_LT:
5027                 case OP_COND_EXC_LT_UN:
5028                 case OP_COND_EXC_GT:
5029                 case OP_COND_EXC_GT_UN:
5030                 case OP_COND_EXC_GE:
5031                 case OP_COND_EXC_GE_UN:
5032                 case OP_COND_EXC_LE:
5033                 case OP_COND_EXC_LE_UN:
5034                 case OP_COND_EXC_IEQ:
5035                 case OP_COND_EXC_INE_UN:
5036                 case OP_COND_EXC_ILT:
5037                 case OP_COND_EXC_ILT_UN:
5038                 case OP_COND_EXC_IGT:
5039                 case OP_COND_EXC_IGT_UN:
5040                 case OP_COND_EXC_IGE:
5041                 case OP_COND_EXC_IGE_UN:
5042                 case OP_COND_EXC_ILE:
5043                 case OP_COND_EXC_ILE_UN:
5044                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5045                         break;
5046                 case OP_COND_EXC_OV:
5047                 case OP_COND_EXC_NO:
5048                 case OP_COND_EXC_C:
5049                 case OP_COND_EXC_NC:
5050                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5051                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5052                         break;
5053                 case OP_COND_EXC_IOV:
5054                 case OP_COND_EXC_INO:
5055                 case OP_COND_EXC_IC:
5056                 case OP_COND_EXC_INC:
5057                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5058                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5059                         break;
5060
5061                 /* floating point opcodes */
5062                 case OP_R8CONST: {
5063                         double d = *(double *)ins->inst_p0;
5064
5065                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5066                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5067                         }
5068                         else {
5069                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5070                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5071                         }
5072                         break;
5073                 }
5074                 case OP_R4CONST: {
5075                         float f = *(float *)ins->inst_p0;
5076
5077                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5078                                 if (cfg->r4fp)
5079                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5080                                 else
5081                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5082                         }
5083                         else {
5084                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5085                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5086                                 if (!cfg->r4fp)
5087                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5088                         }
5089                         break;
5090                 }
5091                 case OP_STORER8_MEMBASE_REG:
5092                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5093                         break;
5094                 case OP_LOADR8_MEMBASE:
5095                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5096                         break;
5097                 case OP_STORER4_MEMBASE_REG:
5098                         if (cfg->r4fp) {
5099                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5100                         } else {
5101                                 /* This requires a double->single conversion */
5102                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5103                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5104                         }
5105                         break;
5106                 case OP_LOADR4_MEMBASE:
5107                         if (cfg->r4fp) {
5108                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5109                         } else {
5110                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5111                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5112                         }
5113                         break;
5114                 case OP_ICONV_TO_R4:
5115                         if (cfg->r4fp) {
5116                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5117                         } else {
5118                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5119                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5120                         }
5121                         break;
5122                 case OP_ICONV_TO_R8:
5123                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5124                         break;
5125                 case OP_LCONV_TO_R4:
5126                         if (cfg->r4fp) {
5127                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5128                         } else {
5129                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5130                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5131                         }
5132                         break;
5133                 case OP_LCONV_TO_R8:
5134                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5135                         break;
5136                 case OP_FCONV_TO_R4:
5137                         if (cfg->r4fp) {
5138                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5139                         } else {
5140                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5141                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5142                         }
5143                         break;
5144                 case OP_FCONV_TO_I1:
5145                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5146                         break;
5147                 case OP_FCONV_TO_U1:
5148                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5149                         break;
5150                 case OP_FCONV_TO_I2:
5151                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5152                         break;
5153                 case OP_FCONV_TO_U2:
5154                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5155                         break;
5156                 case OP_FCONV_TO_U4:
5157                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5158                         break;
5159                 case OP_FCONV_TO_I4:
5160                 case OP_FCONV_TO_I:
5161                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5162                         break;
5163                 case OP_FCONV_TO_I8:
5164                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5165                         break;
5166
5167                 case OP_RCONV_TO_I1:
5168                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5169                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5170                         break;
5171                 case OP_RCONV_TO_U1:
5172                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5173                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5174                         break;
5175                 case OP_RCONV_TO_I2:
5176                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5177                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5178                         break;
5179                 case OP_RCONV_TO_U2:
5180                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5181                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5182                         break;
5183                 case OP_RCONV_TO_I4:
5184                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5185                         break;
5186                 case OP_RCONV_TO_U4:
5187                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5188                         break;
5189                 case OP_RCONV_TO_I8:
5190                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5191                         break;
5192                 case OP_RCONV_TO_R8:
5193                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5194                         break;
5195                 case OP_RCONV_TO_R4:
5196                         if (ins->dreg != ins->sreg1)
5197                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5198                         break;
5199
5200                 case OP_LCONV_TO_R_UN: {
5201                         guint8 *br [2];
5202
5203                         /* Based on gcc code */
5204                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5205                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5206
5207                         /* Positive case */
5208                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5209                         br [1] = code; x86_jump8 (code, 0);
5210                         amd64_patch (br [0], code);
5211
5212                         /* Negative case */
5213                         /* Save to the red zone */
5214                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5215                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5216                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5217                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5218                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5219                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5220                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5221                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5222                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5223                         /* Restore */
5224                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5225                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5226                         amd64_patch (br [1], code);
5227                         break;
5228                 }
5229                 case OP_LCONV_TO_OVF_U4:
5230                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5231                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5232                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5233                         break;
5234                 case OP_LCONV_TO_OVF_I4_UN:
5235                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5236                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5237                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5238                         break;
5239                 case OP_FMOVE:
5240                         if (ins->dreg != ins->sreg1)
5241                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5242                         break;
5243                 case OP_RMOVE:
5244                         if (ins->dreg != ins->sreg1)
5245                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5246                         break;
5247                 case OP_MOVE_F_TO_I4:
5248                         if (cfg->r4fp) {
5249                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5250                         } else {
5251                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5252                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5253                         }
5254                         break;
5255                 case OP_MOVE_I4_TO_F:
5256                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5257                         if (!cfg->r4fp)
5258                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5259                         break;
5260                 case OP_MOVE_F_TO_I8:
5261                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5262                         break;
5263                 case OP_MOVE_I8_TO_F:
5264                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5265                         break;
5266                 case OP_FADD:
5267                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5268                         break;
5269                 case OP_FSUB:
5270                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5271                         break;
5272                 case OP_FMUL:
5273                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5274                         break;
5275                 case OP_FDIV:
5276                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5277                         break;
5278                 case OP_FNEG: {
5279                         static double r8_0 = -0.0;
5280
5281                         g_assert (ins->sreg1 == ins->dreg);
5282
5283                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5284                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5285                         break;
5286                 }
5287                 case OP_SIN:
5288                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5289                         break;
5290                 case OP_COS:
5291                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5292                         break;
5293                 case OP_ABS: {
5294                         static guint64 d = 0x7fffffffffffffffUL;
5295
5296                         g_assert (ins->sreg1 == ins->dreg);
5297
5298                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5299                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5300                         break;
5301                 }
5302                 case OP_SQRT:
5303                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5304                         break;
5305
5306                 case OP_RADD:
5307                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5308                         break;
5309                 case OP_RSUB:
5310                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5311                         break;
5312                 case OP_RMUL:
5313                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5314                         break;
5315                 case OP_RDIV:
5316                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5317                         break;
5318                 case OP_RNEG: {
5319                         static float r4_0 = -0.0;
5320
5321                         g_assert (ins->sreg1 == ins->dreg);
5322
5323                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5324                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5325                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5326                         break;
5327                 }
5328
5329                 case OP_IMIN:
5330                         g_assert (cfg->opt & MONO_OPT_CMOV);
5331                         g_assert (ins->dreg == ins->sreg1);
5332                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5333                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5334                         break;
5335                 case OP_IMIN_UN:
5336                         g_assert (cfg->opt & MONO_OPT_CMOV);
5337                         g_assert (ins->dreg == ins->sreg1);
5338                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5339                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5340                         break;
5341                 case OP_IMAX:
5342                         g_assert (cfg->opt & MONO_OPT_CMOV);
5343                         g_assert (ins->dreg == ins->sreg1);
5344                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5345                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5346                         break;
5347                 case OP_IMAX_UN:
5348                         g_assert (cfg->opt & MONO_OPT_CMOV);
5349                         g_assert (ins->dreg == ins->sreg1);
5350                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5351                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5352                         break;
5353                 case OP_LMIN:
5354                         g_assert (cfg->opt & MONO_OPT_CMOV);
5355                         g_assert (ins->dreg == ins->sreg1);
5356                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5357                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5358                         break;
5359                 case OP_LMIN_UN:
5360                         g_assert (cfg->opt & MONO_OPT_CMOV);
5361                         g_assert (ins->dreg == ins->sreg1);
5362                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5363                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5364                         break;
5365                 case OP_LMAX:
5366                         g_assert (cfg->opt & MONO_OPT_CMOV);
5367                         g_assert (ins->dreg == ins->sreg1);
5368                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5369                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5370                         break;
5371                 case OP_LMAX_UN:
5372                         g_assert (cfg->opt & MONO_OPT_CMOV);
5373                         g_assert (ins->dreg == ins->sreg1);
5374                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5375                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5376                         break;
5377                 case OP_X86_FPOP:
5378                         break;
5379                 case OP_FCOMPARE:
5380                         /*
5381                          * The two arguments are swapped because the fbranch instructions
5382                          * depend on this for the non-sse case to work.
5383                          */
5384                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5385                         break;
5386                 case OP_RCOMPARE:
5387                         /*
5388                          * FIXME: Get rid of this.
5389                          * The two arguments are swapped because the fbranch instructions
5390                          * depend on this for the non-sse case to work.
5391                          */
5392                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5393                         break;
5394                 case OP_FCNEQ:
5395                 case OP_FCEQ: {
5396                         /* zeroing the register at the start results in
5397                          * shorter and faster code (we can also remove the widening op)
5398                          */
5399                         guchar *unordered_check;
5400
5401                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5402                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5403                         unordered_check = code;
5404                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5405
5406                         if (ins->opcode == OP_FCEQ) {
5407                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5408                                 amd64_patch (unordered_check, code);
5409                         } else {
5410                                 guchar *jump_to_end;
5411                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5412                                 jump_to_end = code;
5413                                 x86_jump8 (code, 0);
5414                                 amd64_patch (unordered_check, code);
5415                                 amd64_inc_reg (code, ins->dreg);
5416                                 amd64_patch (jump_to_end, code);
5417                         }
5418                         break;
5419                 }
5420                 case OP_FCLT:
5421                 case OP_FCLT_UN: {
5422                         /* zeroing the register at the start results in
5423                          * shorter and faster code (we can also remove the widening op)
5424                          */
5425                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5426                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5427                         if (ins->opcode == OP_FCLT_UN) {
5428                                 guchar *unordered_check = code;
5429                                 guchar *jump_to_end;
5430                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5431                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5432                                 jump_to_end = code;
5433                                 x86_jump8 (code, 0);
5434                                 amd64_patch (unordered_check, code);
5435                                 amd64_inc_reg (code, ins->dreg);
5436                                 amd64_patch (jump_to_end, code);
5437                         } else {
5438                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5439                         }
5440                         break;
5441                 }
5442                 case OP_FCLE: {
5443                         guchar *unordered_check;
5444                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5445                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5446                         unordered_check = code;
5447                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5448                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5449                         amd64_patch (unordered_check, code);
5450                         break;
5451                 }
5452                 case OP_FCGT:
5453                 case OP_FCGT_UN: {
5454                         /* zeroing the register at the start results in
5455                          * shorter and faster code (we can also remove the widening op)
5456                          */
5457                         guchar *unordered_check;
5458
5459                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5460                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5461                         if (ins->opcode == OP_FCGT) {
5462                                 unordered_check = code;
5463                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5464                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5465                                 amd64_patch (unordered_check, code);
5466                         } else {
5467                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5468                         }
5469                         break;
5470                 }
5471                 case OP_FCGE: {
5472                         guchar *unordered_check;
5473                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5474                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5475                         unordered_check = code;
5476                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5477                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5478                         amd64_patch (unordered_check, code);
5479                         break;
5480                 }
5481
5482                 case OP_RCEQ:
5483                 case OP_RCGT:
5484                 case OP_RCLT:
5485                 case OP_RCLT_UN:
5486                 case OP_RCGT_UN: {
5487                         int x86_cond;
5488                         gboolean unordered = FALSE;
5489
5490                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5491                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5492
5493                         switch (ins->opcode) {
5494                         case OP_RCEQ:
5495                                 x86_cond = X86_CC_EQ;
5496                                 break;
5497                         case OP_RCGT:
5498                                 x86_cond = X86_CC_LT;
5499                                 break;
5500                         case OP_RCLT:
5501                                 x86_cond = X86_CC_GT;
5502                                 break;
5503                         case OP_RCLT_UN:
5504                                 x86_cond = X86_CC_GT;
5505                                 unordered = TRUE;
5506                                 break;
5507                         case OP_RCGT_UN:
5508                                 x86_cond = X86_CC_LT;
5509                                 unordered = TRUE;
5510                                 break;
5511                         default:
5512                                 g_assert_not_reached ();
5513                                 break;
5514                         }
5515
5516                         if (unordered) {
5517                                 guchar *unordered_check;
5518                                 guchar *jump_to_end;
5519
5520                                 unordered_check = code;
5521                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5522                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5523                                 jump_to_end = code;
5524                                 x86_jump8 (code, 0);
5525                                 amd64_patch (unordered_check, code);
5526                                 amd64_inc_reg (code, ins->dreg);
5527                                 amd64_patch (jump_to_end, code);
5528                         } else {
5529                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5530                         }
5531                         break;
5532                 }
5533                 case OP_FCLT_MEMBASE:
5534                 case OP_FCGT_MEMBASE:
5535                 case OP_FCLT_UN_MEMBASE:
5536                 case OP_FCGT_UN_MEMBASE:
5537                 case OP_FCEQ_MEMBASE: {
5538                         guchar *unordered_check, *jump_to_end;
5539                         int x86_cond;
5540
5541                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5542                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5543
5544                         switch (ins->opcode) {
5545                         case OP_FCEQ_MEMBASE:
5546                                 x86_cond = X86_CC_EQ;
5547                                 break;
5548                         case OP_FCLT_MEMBASE:
5549                         case OP_FCLT_UN_MEMBASE:
5550                                 x86_cond = X86_CC_LT;
5551                                 break;
5552                         case OP_FCGT_MEMBASE:
5553                         case OP_FCGT_UN_MEMBASE:
5554                                 x86_cond = X86_CC_GT;
5555                                 break;
5556                         default:
5557                                 g_assert_not_reached ();
5558                         }
5559
5560                         unordered_check = code;
5561                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5562                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5563
5564                         switch (ins->opcode) {
5565                         case OP_FCEQ_MEMBASE:
5566                         case OP_FCLT_MEMBASE:
5567                         case OP_FCGT_MEMBASE:
5568                                 amd64_patch (unordered_check, code);
5569                                 break;
5570                         case OP_FCLT_UN_MEMBASE:
5571                         case OP_FCGT_UN_MEMBASE:
5572                                 jump_to_end = code;
5573                                 x86_jump8 (code, 0);
5574                                 amd64_patch (unordered_check, code);
5575                                 amd64_inc_reg (code, ins->dreg);
5576                                 amd64_patch (jump_to_end, code);
5577                                 break;
5578                         default:
5579                                 break;
5580                         }
5581                         break;
5582                 }
5583                 case OP_FBEQ: {
5584                         guchar *jump = code;
5585                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5586                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5587                         amd64_patch (jump, code);
5588                         break;
5589                 }
5590                 case OP_FBNE_UN:
5591                         /* Branch if C013 != 100 */
5592                         /* branch if !ZF or (PF|CF) */
5593                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5594                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5595                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5596                         break;
5597                 case OP_FBLT:
5598                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5599                         break;
5600                 case OP_FBLT_UN:
5601                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5602                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5603                         break;
5604                 case OP_FBGT:
5605                 case OP_FBGT_UN:
5606                         if (ins->opcode == OP_FBGT) {
5607                                 guchar *br1;
5608
5609                                 /* skip branch if C1=1 */
5610                                 br1 = code;
5611                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5612                                 /* branch if (C0 | C3) = 1 */
5613                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5614                                 amd64_patch (br1, code);
5615                                 break;
5616                         } else {
5617                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5618                         }
5619                         break;
5620                 case OP_FBGE: {
5621                         /* Branch if C013 == 100 or 001 */
5622                         guchar *br1;
5623
5624                         /* skip branch if C1=1 */
5625                         br1 = code;
5626                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5627                         /* branch if (C0 | C3) = 1 */
5628                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5629                         amd64_patch (br1, code);
5630                         break;
5631                 }
5632                 case OP_FBGE_UN:
5633                         /* Branch if C013 == 000 */
5634                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5635                         break;
5636                 case OP_FBLE: {
5637                         /* Branch if C013=000 or 100 */
5638                         guchar *br1;
5639
5640                         /* skip branch if C1=1 */
5641                         br1 = code;
5642                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5643                         /* branch if C0=0 */
5644                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5645                         amd64_patch (br1, code);
5646                         break;
5647                 }
5648                 case OP_FBLE_UN:
5649                         /* Branch if C013 != 001 */
5650                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5651                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5652                         break;
5653                 case OP_CKFINITE:
5654                         /* Transfer value to the fp stack */
5655                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5656                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5657                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5658
5659                         amd64_push_reg (code, AMD64_RAX);
5660                         amd64_fxam (code);
5661                         amd64_fnstsw (code);
5662                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5663                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5664                         amd64_pop_reg (code, AMD64_RAX);
5665                         amd64_fstp (code, 0);
5666                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5667                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5668                         break;
5669                 case OP_TLS_GET: {
5670                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5671                         break;
5672                 }
5673                 case OP_TLS_GET_REG:
5674                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5675                         break;
5676                 case OP_TLS_SET: {
5677                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5678                         break;
5679                 }
5680                 case OP_TLS_SET_REG: {
5681                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5682                         break;
5683                 }
5684                 case OP_MEMORY_BARRIER: {
5685                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5686                                 x86_mfence (code);
5687                         break;
5688                 }
5689                 case OP_ATOMIC_ADD_I4:
5690                 case OP_ATOMIC_ADD_I8: {
5691                         int dreg = ins->dreg;
5692                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5693
5694                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5695                                 dreg = AMD64_R11;
5696
5697                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5698                         amd64_prefix (code, X86_LOCK_PREFIX);
5699                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5700                         /* dreg contains the old value, add with sreg2 value */
5701                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5702
5703                         if (ins->dreg != dreg)
5704                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5705
5706                         break;
5707                 }
5708                 case OP_ATOMIC_EXCHANGE_I4:
5709                 case OP_ATOMIC_EXCHANGE_I8: {
5710                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5711
5712                         /* LOCK prefix is implied. */
5713                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5714                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5715                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5716                         break;
5717                 }
5718                 case OP_ATOMIC_CAS_I4:
5719                 case OP_ATOMIC_CAS_I8: {
5720                         guint32 size;
5721
5722                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5723                                 size = 8;
5724                         else
5725                                 size = 4;
5726
5727                         /*
5728                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5729                          * an explanation of how this works.
5730                          */
5731                         g_assert (ins->sreg3 == AMD64_RAX);
5732                         g_assert (ins->sreg1 != AMD64_RAX);
5733                         g_assert (ins->sreg1 != ins->sreg2);
5734
5735                         amd64_prefix (code, X86_LOCK_PREFIX);
5736                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5737
5738                         if (ins->dreg != AMD64_RAX)
5739                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5740                         break;
5741                 }
5742                 case OP_ATOMIC_LOAD_I1: {
5743                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5744                         break;
5745                 }
5746                 case OP_ATOMIC_LOAD_U1: {
5747                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5748                         break;
5749                 }
5750                 case OP_ATOMIC_LOAD_I2: {
5751                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5752                         break;
5753                 }
5754                 case OP_ATOMIC_LOAD_U2: {
5755                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5756                         break;
5757                 }
5758                 case OP_ATOMIC_LOAD_I4: {
5759                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5760                         break;
5761                 }
5762                 case OP_ATOMIC_LOAD_U4:
5763                 case OP_ATOMIC_LOAD_I8:
5764                 case OP_ATOMIC_LOAD_U8: {
5765                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5766                         break;
5767                 }
5768                 case OP_ATOMIC_LOAD_R4: {
5769                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5770                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5771                         break;
5772                 }
5773                 case OP_ATOMIC_LOAD_R8: {
5774                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5775                         break;
5776                 }
5777                 case OP_ATOMIC_STORE_I1:
5778                 case OP_ATOMIC_STORE_U1:
5779                 case OP_ATOMIC_STORE_I2:
5780                 case OP_ATOMIC_STORE_U2:
5781                 case OP_ATOMIC_STORE_I4:
5782                 case OP_ATOMIC_STORE_U4:
5783                 case OP_ATOMIC_STORE_I8:
5784                 case OP_ATOMIC_STORE_U8: {
5785                         int size;
5786
5787                         switch (ins->opcode) {
5788                         case OP_ATOMIC_STORE_I1:
5789                         case OP_ATOMIC_STORE_U1:
5790                                 size = 1;
5791                                 break;
5792                         case OP_ATOMIC_STORE_I2:
5793                         case OP_ATOMIC_STORE_U2:
5794                                 size = 2;
5795                                 break;
5796                         case OP_ATOMIC_STORE_I4:
5797                         case OP_ATOMIC_STORE_U4:
5798                                 size = 4;
5799                                 break;
5800                         case OP_ATOMIC_STORE_I8:
5801                         case OP_ATOMIC_STORE_U8:
5802                                 size = 8;
5803                                 break;
5804                         }
5805
5806                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5807
5808                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5809                                 x86_mfence (code);
5810                         break;
5811                 }
5812                 case OP_ATOMIC_STORE_R4: {
5813                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5814                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5815
5816                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5817                                 x86_mfence (code);
5818                         break;
5819                 }
5820                 case OP_ATOMIC_STORE_R8: {
5821                         x86_nop (code);
5822                         x86_nop (code);
5823                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5824                         x86_nop (code);
5825                         x86_nop (code);
5826
5827                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5828                                 x86_mfence (code);
5829                         break;
5830                 }
5831                 case OP_CARD_TABLE_WBARRIER: {
5832                         int ptr = ins->sreg1;
5833                         int value = ins->sreg2;
5834                         guchar *br = 0;
5835                         int nursery_shift, card_table_shift;
5836                         gpointer card_table_mask;
5837                         size_t nursery_size;
5838
5839                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5840                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5841                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5842
5843                         /*If either point to the stack we can simply avoid the WB. This happens due to
5844                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5845                          */
5846                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5847                                 continue;
5848
5849                         /*
5850                          * We need one register we can clobber, we choose EDX and make sreg1
5851                          * fixed EAX to work around limitations in the local register allocator.
5852                          * sreg2 might get allocated to EDX, but that is not a problem since
5853                          * we use it before clobbering EDX.
5854                          */
5855                         g_assert (ins->sreg1 == AMD64_RAX);
5856
5857                         /*
5858                          * This is the code we produce:
5859                          *
5860                          *   edx = value
5861                          *   edx >>= nursery_shift
5862                          *   cmp edx, (nursery_start >> nursery_shift)
5863                          *   jne done
5864                          *   edx = ptr
5865                          *   edx >>= card_table_shift
5866                          *   edx += cardtable
5867                          *   [edx] = 1
5868                          * done:
5869                          */
5870
5871                         if (mono_gc_card_table_nursery_check ()) {
5872                                 if (value != AMD64_RDX)
5873                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5874                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5875                                 if (shifted_nursery_start >> 31) {
5876                                         /*
5877                                          * The value we need to compare against is 64 bits, so we need
5878                                          * another spare register.  We use RBX, which we save and
5879                                          * restore.
5880                                          */
5881                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5882                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5883                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5884                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5885                                 } else {
5886                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5887                                 }
5888                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5889                         }
5890                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5891                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5892                         if (card_table_mask)
5893                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5894
5895                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5896                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5897
5898                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5899
5900                         if (mono_gc_card_table_nursery_check ())
5901                                 x86_patch (br, code);
5902                         break;
5903                 }
5904 #ifdef MONO_ARCH_SIMD_INTRINSICS
5905                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5906                 case OP_ADDPS:
5907                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5908                         break;
5909                 case OP_DIVPS:
5910                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5911                         break;
5912                 case OP_MULPS:
5913                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5914                         break;
5915                 case OP_SUBPS:
5916                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5917                         break;
5918                 case OP_MAXPS:
5919                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5920                         break;
5921                 case OP_MINPS:
5922                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5923                         break;
5924                 case OP_COMPPS:
5925                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5926                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5927                         break;
5928                 case OP_ANDPS:
5929                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5930                         break;
5931                 case OP_ANDNPS:
5932                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5933                         break;
5934                 case OP_ORPS:
5935                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5936                         break;
5937                 case OP_XORPS:
5938                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5939                         break;
5940                 case OP_SQRTPS:
5941                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5942                         break;
5943                 case OP_RSQRTPS:
5944                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5945                         break;
5946                 case OP_RCPPS:
5947                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5948                         break;
5949                 case OP_ADDSUBPS:
5950                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5951                         break;
5952                 case OP_HADDPS:
5953                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5954                         break;
5955                 case OP_HSUBPS:
5956                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5957                         break;
5958                 case OP_DUPPS_HIGH:
5959                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5960                         break;
5961                 case OP_DUPPS_LOW:
5962                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5963                         break;
5964
5965                 case OP_PSHUFLEW_HIGH:
5966                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5967                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5968                         break;
5969                 case OP_PSHUFLEW_LOW:
5970                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5971                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5972                         break;
5973                 case OP_PSHUFLED:
5974                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5975                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5976                         break;
5977                 case OP_SHUFPS:
5978                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5979                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5980                         break;
5981                 case OP_SHUFPD:
5982                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5983                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5984                         break;
5985
5986                 case OP_ADDPD:
5987                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5988                         break;
5989                 case OP_DIVPD:
5990                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5991                         break;
5992                 case OP_MULPD:
5993                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5994                         break;
5995                 case OP_SUBPD:
5996                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5997                         break;
5998                 case OP_MAXPD:
5999                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6000                         break;
6001                 case OP_MINPD:
6002                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6003                         break;
6004                 case OP_COMPPD:
6005                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6006                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6007                         break;
6008                 case OP_ANDPD:
6009                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6010                         break;
6011                 case OP_ANDNPD:
6012                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6013                         break;
6014                 case OP_ORPD:
6015                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6016                         break;
6017                 case OP_XORPD:
6018                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020                 case OP_SQRTPD:
6021                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6022                         break;
6023                 case OP_ADDSUBPD:
6024                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6025                         break;
6026                 case OP_HADDPD:
6027                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6028                         break;
6029                 case OP_HSUBPD:
6030                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6031                         break;
6032                 case OP_DUPPD:
6033                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6034                         break;
6035
6036                 case OP_EXTRACT_MASK:
6037                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6038                         break;
6039
6040                 case OP_PAND:
6041                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043                 case OP_POR:
6044                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6045                         break;
6046                 case OP_PXOR:
6047                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049
6050                 case OP_PADDB:
6051                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6052                         break;
6053                 case OP_PADDW:
6054                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6055                         break;
6056                 case OP_PADDD:
6057                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6058                         break;
6059                 case OP_PADDQ:
6060                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062
6063                 case OP_PSUBB:
6064                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6065                         break;
6066                 case OP_PSUBW:
6067                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6068                         break;
6069                 case OP_PSUBD:
6070                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6071                         break;
6072                 case OP_PSUBQ:
6073                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075
6076                 case OP_PMAXB_UN:
6077                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6078                         break;
6079                 case OP_PMAXW_UN:
6080                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6081                         break;
6082                 case OP_PMAXD_UN:
6083                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6084                         break;
6085
6086                 case OP_PMAXB:
6087                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6088                         break;
6089                 case OP_PMAXW:
6090                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6091                         break;
6092                 case OP_PMAXD:
6093                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6094                         break;
6095
6096                 case OP_PAVGB_UN:
6097                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6098                         break;
6099                 case OP_PAVGW_UN:
6100                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6101                         break;
6102
6103                 case OP_PMINB_UN:
6104                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6105                         break;
6106                 case OP_PMINW_UN:
6107                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_PMIND_UN:
6110                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112
6113                 case OP_PMINB:
6114                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6115                         break;
6116                 case OP_PMINW:
6117                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6118                         break;
6119                 case OP_PMIND:
6120                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6121                         break;
6122
6123                 case OP_PCMPEQB:
6124                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6125                         break;
6126                 case OP_PCMPEQW:
6127                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6128                         break;
6129                 case OP_PCMPEQD:
6130                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6131                         break;
6132                 case OP_PCMPEQQ:
6133                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6134                         break;
6135
6136                 case OP_PCMPGTB:
6137                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6138                         break;
6139                 case OP_PCMPGTW:
6140                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6141                         break;
6142                 case OP_PCMPGTD:
6143                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6144                         break;
6145                 case OP_PCMPGTQ:
6146                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6147                         break;
6148
6149                 case OP_PSUM_ABS_DIFF:
6150                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6151                         break;
6152
6153                 case OP_UNPACK_LOWB:
6154                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6155                         break;
6156                 case OP_UNPACK_LOWW:
6157                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6158                         break;
6159                 case OP_UNPACK_LOWD:
6160                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6161                         break;
6162                 case OP_UNPACK_LOWQ:
6163                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6164                         break;
6165                 case OP_UNPACK_LOWPS:
6166                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6167                         break;
6168                 case OP_UNPACK_LOWPD:
6169                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6170                         break;
6171
6172                 case OP_UNPACK_HIGHB:
6173                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6174                         break;
6175                 case OP_UNPACK_HIGHW:
6176                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6177                         break;
6178                 case OP_UNPACK_HIGHD:
6179                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6180                         break;
6181                 case OP_UNPACK_HIGHQ:
6182                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6183                         break;
6184                 case OP_UNPACK_HIGHPS:
6185                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6186                         break;
6187                 case OP_UNPACK_HIGHPD:
6188                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6189                         break;
6190
6191                 case OP_PACKW:
6192                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6193                         break;
6194                 case OP_PACKD:
6195                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6196                         break;
6197                 case OP_PACKW_UN:
6198                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6199                         break;
6200                 case OP_PACKD_UN:
6201                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6202                         break;
6203
6204                 case OP_PADDB_SAT_UN:
6205                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6206                         break;
6207                 case OP_PSUBB_SAT_UN:
6208                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6209                         break;
6210                 case OP_PADDW_SAT_UN:
6211                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6212                         break;
6213                 case OP_PSUBW_SAT_UN:
6214                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6215                         break;
6216
6217                 case OP_PADDB_SAT:
6218                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6219                         break;
6220                 case OP_PSUBB_SAT:
6221                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6222                         break;
6223                 case OP_PADDW_SAT:
6224                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6225                         break;
6226                 case OP_PSUBW_SAT:
6227                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6228                         break;
6229
6230                 case OP_PMULW:
6231                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6232                         break;
6233                 case OP_PMULD:
6234                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6235                         break;
6236                 case OP_PMULQ:
6237                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6238                         break;
6239                 case OP_PMULW_HIGH_UN:
6240                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6241                         break;
6242                 case OP_PMULW_HIGH:
6243                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6244                         break;
6245
6246                 case OP_PSHRW:
6247                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6248                         break;
6249                 case OP_PSHRW_REG:
6250                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6251                         break;
6252
6253                 case OP_PSARW:
6254                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6255                         break;
6256                 case OP_PSARW_REG:
6257                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6258                         break;
6259
6260                 case OP_PSHLW:
6261                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6262                         break;
6263                 case OP_PSHLW_REG:
6264                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6265                         break;
6266
6267                 case OP_PSHRD:
6268                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6269                         break;
6270                 case OP_PSHRD_REG:
6271                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6272                         break;
6273
6274                 case OP_PSARD:
6275                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6276                         break;
6277                 case OP_PSARD_REG:
6278                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6279                         break;
6280
6281                 case OP_PSHLD:
6282                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6283                         break;
6284                 case OP_PSHLD_REG:
6285                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6286                         break;
6287
6288                 case OP_PSHRQ:
6289                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6290                         break;
6291                 case OP_PSHRQ_REG:
6292                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6293                         break;
6294
6295                 /*TODO: This is appart of the sse spec but not added
6296                 case OP_PSARQ:
6297                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6298                         break;
6299                 case OP_PSARQ_REG:
6300                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6301                         break;
6302                 */
6303
6304                 case OP_PSHLQ:
6305                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6306                         break;
6307                 case OP_PSHLQ_REG:
6308                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6309                         break;
6310                 case OP_CVTDQ2PD:
6311                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6312                         break;
6313                 case OP_CVTDQ2PS:
6314                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6315                         break;
6316                 case OP_CVTPD2DQ:
6317                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6318                         break;
6319                 case OP_CVTPD2PS:
6320                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6321                         break;
6322                 case OP_CVTPS2DQ:
6323                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6324                         break;
6325                 case OP_CVTPS2PD:
6326                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6327                         break;
6328                 case OP_CVTTPD2DQ:
6329                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6330                         break;
6331                 case OP_CVTTPS2DQ:
6332                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6333                         break;
6334
6335                 case OP_ICONV_TO_X:
6336                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6337                         break;
6338                 case OP_EXTRACT_I4:
6339                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6340                         break;
6341                 case OP_EXTRACT_I8:
6342                         if (ins->inst_c0) {
6343                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6344                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6345                         } else {
6346                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6347                         }
6348                         break;
6349                 case OP_EXTRACT_I1:
6350                 case OP_EXTRACT_U1:
6351                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6352                         if (ins->inst_c0)
6353                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6354                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6355                         break;
6356                 case OP_EXTRACT_I2:
6357                 case OP_EXTRACT_U2:
6358                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6359                         if (ins->inst_c0)
6360                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6361                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6362                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6363                         break;
6364                 case OP_EXTRACT_R8:
6365                         if (ins->inst_c0)
6366                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6367                         else
6368                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6369                         break;
6370                 case OP_INSERT_I2:
6371                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6372                         break;
6373                 case OP_EXTRACTX_U2:
6374                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6375                         break;
6376                 case OP_INSERTX_U1_SLOW:
6377                         /*sreg1 is the extracted ireg (scratch)
6378                         /sreg2 is the to be inserted ireg (scratch)
6379                         /dreg is the xreg to receive the value*/
6380
6381                         /*clear the bits from the extracted word*/
6382                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6383                         /*shift the value to insert if needed*/
6384                         if (ins->inst_c0 & 1)
6385                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6386                         /*join them together*/
6387                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6388                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6389                         break;
6390                 case OP_INSERTX_I4_SLOW:
6391                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6392                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6393                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6394                         break;
6395                 case OP_INSERTX_I8_SLOW:
6396                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6397                         if (ins->inst_c0)
6398                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6399                         else
6400                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6401                         break;
6402
6403                 case OP_INSERTX_R4_SLOW:
6404                         switch (ins->inst_c0) {
6405                         case 0:
6406                                 if (cfg->r4fp)
6407                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6408                                 else
6409                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6410                                 break;
6411                         case 1:
6412                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6413                                 if (cfg->r4fp)
6414                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6415                                 else
6416                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6417                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6418                                 break;
6419                         case 2:
6420                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6421                                 if (cfg->r4fp)
6422                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6423                                 else
6424                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6425                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6426                                 break;
6427                         case 3:
6428                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6429                                 if (cfg->r4fp)
6430                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6431                                 else
6432                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6433                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6434                                 break;
6435                         }
6436                         break;
6437                 case OP_INSERTX_R8_SLOW:
6438                         if (ins->inst_c0)
6439                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6440                         else
6441                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6442                         break;
6443                 case OP_STOREX_MEMBASE_REG:
6444                 case OP_STOREX_MEMBASE:
6445                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6446                         break;
6447                 case OP_LOADX_MEMBASE:
6448                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6449                         break;
6450                 case OP_LOADX_ALIGNED_MEMBASE:
6451                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6452                         break;
6453                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6454                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6455                         break;
6456                 case OP_STOREX_NTA_MEMBASE_REG:
6457                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6458                         break;
6459                 case OP_PREFETCH_MEMBASE:
6460                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6461                         break;
6462
6463                 case OP_XMOVE:
6464                         /*FIXME the peephole pass should have killed this*/
6465                         if (ins->dreg != ins->sreg1)
6466                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6467                         break;
6468                 case OP_XZERO:
6469                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6470                         break;
6471                 case OP_ICONV_TO_R4_RAW:
6472                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6473                         break;
6474
6475                 case OP_FCONV_TO_R8_X:
6476                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6477                         break;
6478
6479                 case OP_XCONV_R8_TO_I4:
6480                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6481                         switch (ins->backend.source_opcode) {
6482                         case OP_FCONV_TO_I1:
6483                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6484                                 break;
6485                         case OP_FCONV_TO_U1:
6486                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6487                                 break;
6488                         case OP_FCONV_TO_I2:
6489                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6490                                 break;
6491                         case OP_FCONV_TO_U2:
6492                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6493                                 break;
6494                         }
6495                         break;
6496
6497                 case OP_EXPAND_I2:
6498                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6499                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6500                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6501                         break;
6502                 case OP_EXPAND_I4:
6503                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6504                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6505                         break;
6506                 case OP_EXPAND_I8:
6507                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6508                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6509                         break;
6510                 case OP_EXPAND_R4:
6511                         if (cfg->r4fp) {
6512                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6513                         } else {
6514                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6515                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6516                         }
6517                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6518                         break;
6519                 case OP_EXPAND_R8:
6520                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6521                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6522                         break;
6523 #endif
6524                 case OP_LIVERANGE_START: {
6525                         if (cfg->verbose_level > 1)
6526                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6527                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6528                         break;
6529                 }
6530                 case OP_LIVERANGE_END: {
6531                         if (cfg->verbose_level > 1)
6532                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6533                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6534                         break;
6535                 }
6536                 case OP_GC_SAFE_POINT: {
6537                         const char *polling_func = NULL;
6538                         int compare_val = 0;
6539                         guint8 *br [1];
6540
6541 #if defined (USE_COOP_GC)
6542                         polling_func = "mono_threads_state_poll";
6543                         compare_val = 1;
6544 #elif defined(__native_client_codegen__) && defined(__native_client_gc__)
6545                         polling_func = "mono_nacl_gc";
6546                         compare_val = 0xFFFFFFFF;
6547 #endif
6548                         if (!polling_func)
6549                                 break;
6550
6551                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6552                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6553                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6554                         amd64_patch (br[0], code);
6555                         break;
6556                 }
6557
6558                 case OP_GC_LIVENESS_DEF:
6559                 case OP_GC_LIVENESS_USE:
6560                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6561                         ins->backend.pc_offset = code - cfg->native_code;
6562                         break;
6563                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6564                         ins->backend.pc_offset = code - cfg->native_code;
6565                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6566                         break;
6567                 default:
6568                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6569                         g_assert_not_reached ();
6570                 }
6571
6572                 if ((code - cfg->native_code - offset) > max_len) {
6573 #if !defined(__native_client_codegen__)
6574                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6575                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6576                         g_assert_not_reached ();
6577 #endif
6578                 }
6579         }
6580
6581         cfg->code_len = code - cfg->native_code;
6582 }
6583
6584 #endif /* DISABLE_JIT */
6585
6586 void
6587 mono_arch_register_lowlevel_calls (void)
6588 {
6589         /* The signature doesn't matter */
6590         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6591 }
6592
6593 void
6594 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6595 {
6596         unsigned char *ip = ji->ip.i + code;
6597
6598         /*
6599          * Debug code to help track down problems where the target of a near call is
6600          * is not valid.
6601          */
6602         if (amd64_is_near_call (ip)) {
6603                 gint64 disp = (guint8*)target - (guint8*)ip;
6604
6605                 if (!amd64_is_imm32 (disp)) {
6606                         printf ("TYPE: %d\n", ji->type);
6607                         switch (ji->type) {
6608                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6609                                 printf ("V: %s\n", ji->data.name);
6610                                 break;
6611                         case MONO_PATCH_INFO_METHOD_JUMP:
6612                         case MONO_PATCH_INFO_METHOD:
6613                                 printf ("V: %s\n", ji->data.method->name);
6614                                 break;
6615                         default:
6616                                 break;
6617                         }
6618                 }
6619         }
6620
6621         amd64_patch (ip, (gpointer)target);
6622 }
6623
6624 #ifndef DISABLE_JIT
6625
6626 static int
6627 get_max_epilog_size (MonoCompile *cfg)
6628 {
6629         int max_epilog_size = 16;
6630
6631         if (cfg->method->save_lmf)
6632                 max_epilog_size += 256;
6633
6634         if (mono_jit_trace_calls != NULL)
6635                 max_epilog_size += 50;
6636
6637         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6638                 max_epilog_size += 50;
6639
6640         max_epilog_size += (AMD64_NREG * 2);
6641
6642         return max_epilog_size;
6643 }
6644
6645 /*
6646  * This macro is used for testing whenever the unwinder works correctly at every point
6647  * where an async exception can happen.
6648  */
6649 /* This will generate a SIGSEGV at the given point in the code */
6650 #define async_exc_point(code) do { \
6651     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6652          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6653              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6654          cfg->arch.async_point_count ++; \
6655     } \
6656 } while (0)
6657
6658 guint8 *
6659 mono_arch_emit_prolog (MonoCompile *cfg)
6660 {
6661         MonoMethod *method = cfg->method;
6662         MonoBasicBlock *bb;
6663         MonoMethodSignature *sig;
6664         MonoInst *ins;
6665         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6666         guint8 *code;
6667         CallInfo *cinfo;
6668         MonoInst *lmf_var = cfg->lmf_var;
6669         gboolean args_clobbered = FALSE;
6670         gboolean trace = FALSE;
6671 #ifdef __native_client_codegen__
6672         guint alignment_check;
6673 #endif
6674
6675         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6676
6677 #if defined(__default_codegen__)
6678         code = cfg->native_code = g_malloc (cfg->code_size);
6679 #elif defined(__native_client_codegen__)
6680         /* native_code_alloc is not 32-byte aligned, native_code is. */
6681         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6682
6683         /* Align native_code to next nearest kNaclAlignment byte. */
6684         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6685         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6686
6687         code = cfg->native_code;
6688
6689         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6690         g_assert (alignment_check == 0);
6691 #endif
6692
6693         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6694                 trace = TRUE;
6695
6696         /* Amount of stack space allocated by register saving code */
6697         pos = 0;
6698
6699         /* Offset between RSP and the CFA */
6700         cfa_offset = 0;
6701
6702         /*
6703          * The prolog consists of the following parts:
6704          * FP present:
6705          * - push rbp, mov rbp, rsp
6706          * - save callee saved regs using pushes
6707          * - allocate frame
6708          * - save rgctx if needed
6709          * - save lmf if needed
6710          * FP not present:
6711          * - allocate frame
6712          * - save rgctx if needed
6713          * - save lmf if needed
6714          * - save callee saved regs using moves
6715          */
6716
6717         // CFA = sp + 8
6718         cfa_offset = 8;
6719         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6720         // IP saved at CFA - 8
6721         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6722         async_exc_point (code);
6723         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6724
6725         if (!cfg->arch.omit_fp) {
6726                 amd64_push_reg (code, AMD64_RBP);
6727                 cfa_offset += 8;
6728                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6729                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6730                 async_exc_point (code);
6731 #ifdef TARGET_WIN32
6732                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6733 #endif
6734                 /* These are handled automatically by the stack marking code */
6735                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6736
6737                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6738                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6739                 async_exc_point (code);
6740 #ifdef TARGET_WIN32
6741                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6742 #endif
6743         }
6744
6745         /* The param area is always at offset 0 from sp */
6746         /* This needs to be allocated here, since it has to come after the spill area */
6747         if (cfg->param_area) {
6748                 if (cfg->arch.omit_fp)
6749                         // FIXME:
6750                         g_assert_not_reached ();
6751                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6752         }
6753
6754         if (cfg->arch.omit_fp) {
6755                 /*
6756                  * On enter, the stack is misaligned by the pushing of the return
6757                  * address. It is either made aligned by the pushing of %rbp, or by
6758                  * this.
6759                  */
6760                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6761                 if ((alloc_size % 16) == 0) {
6762                         alloc_size += 8;
6763                         /* Mark the padding slot as NOREF */
6764                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6765                 }
6766         } else {
6767                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6768                 if (cfg->stack_offset != alloc_size) {
6769                         /* Mark the padding slot as NOREF */
6770                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6771                 }
6772                 cfg->arch.sp_fp_offset = alloc_size;
6773                 alloc_size -= pos;
6774         }
6775
6776         cfg->arch.stack_alloc_size = alloc_size;
6777
6778         /* Allocate stack frame */
6779         if (alloc_size) {
6780                 /* See mono_emit_stack_alloc */
6781 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6782                 guint32 remaining_size = alloc_size;
6783                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6784                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6785                 guint32 offset = code - cfg->native_code;
6786                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6787                         while (required_code_size >= (cfg->code_size - offset))
6788                                 cfg->code_size *= 2;
6789                         cfg->native_code = mono_realloc_native_code (cfg);
6790                         code = cfg->native_code + offset;
6791                         cfg->stat_code_reallocs++;
6792                 }
6793
6794                 while (remaining_size >= 0x1000) {
6795                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6796                         if (cfg->arch.omit_fp) {
6797                                 cfa_offset += 0x1000;
6798                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6799                         }
6800                         async_exc_point (code);
6801 #ifdef TARGET_WIN32
6802                         if (cfg->arch.omit_fp)
6803                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6804 #endif
6805
6806                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6807                         remaining_size -= 0x1000;
6808                 }
6809                 if (remaining_size) {
6810                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6811                         if (cfg->arch.omit_fp) {
6812                                 cfa_offset += remaining_size;
6813                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6814                                 async_exc_point (code);
6815                         }
6816 #ifdef TARGET_WIN32
6817                         if (cfg->arch.omit_fp)
6818                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6819 #endif
6820                 }
6821 #else
6822                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6823                 if (cfg->arch.omit_fp) {
6824                         cfa_offset += alloc_size;
6825                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6826                         async_exc_point (code);
6827                 }
6828 #endif
6829         }
6830
6831         /* Stack alignment check */
6832 #if 0
6833         {
6834                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6835                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6836                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6837                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6838                 amd64_breakpoint (code);
6839         }
6840 #endif
6841
6842         if (mini_get_debug_options ()->init_stacks) {
6843                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6844
6845                 /* Save registers to the red zone */
6846                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6847                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6848
6849                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6850                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6851                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6852
6853                 amd64_cld (code);
6854 #if defined(__default_codegen__)
6855                 amd64_prefix (code, X86_REP_PREFIX);
6856                 amd64_stosl (code);
6857 #elif defined(__native_client_codegen__)
6858                 /* NaCl stos pseudo-instruction */
6859                 amd64_codegen_pre (code);
6860                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6861                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6862                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6863                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6864                 amd64_prefix (code, X86_REP_PREFIX);
6865                 amd64_stosl (code);
6866                 amd64_codegen_post (code);
6867 #endif /* __native_client_codegen__ */
6868
6869                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6870                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6871         }
6872
6873         /* Save LMF */
6874         if (method->save_lmf)
6875                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6876
6877         /* Save callee saved registers */
6878         if (cfg->arch.omit_fp) {
6879                 save_area_offset = cfg->arch.reg_save_area_offset;
6880                 /* Save caller saved registers after sp is adjusted */
6881                 /* The registers are saved at the bottom of the frame */
6882                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6883         } else {
6884                 /* The registers are saved just below the saved rbp */
6885                 save_area_offset = cfg->arch.reg_save_area_offset;
6886         }
6887
6888         for (i = 0; i < AMD64_NREG; ++i) {
6889                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6890                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6891
6892                         if (cfg->arch.omit_fp) {
6893                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6894                                 /* These are handled automatically by the stack marking code */
6895                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6896                         } else {
6897                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6898                                 // FIXME: GC
6899                         }
6900
6901                         save_area_offset += 8;
6902                         async_exc_point (code);
6903                 }
6904         }
6905
6906         /* store runtime generic context */
6907         if (cfg->rgctx_var) {
6908                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6909                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6910
6911                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6912
6913                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6914                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6915         }
6916
6917         /* compute max_length in order to use short forward jumps */
6918         max_epilog_size = get_max_epilog_size (cfg);
6919         if (cfg->opt & MONO_OPT_BRANCH) {
6920                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6921                         MonoInst *ins;
6922                         int max_length = 0;
6923
6924                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6925                                 max_length += 6;
6926                         /* max alignment for loops */
6927                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6928                                 max_length += LOOP_ALIGNMENT;
6929 #ifdef __native_client_codegen__
6930                         /* max alignment for native client */
6931                         max_length += kNaClAlignment;
6932 #endif
6933
6934                         MONO_BB_FOR_EACH_INS (bb, ins) {
6935 #ifdef __native_client_codegen__
6936                                 {
6937                                         int space_in_block = kNaClAlignment -
6938                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6939                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6940                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6941                                                 max_length += space_in_block;
6942                                         }
6943                                 }
6944 #endif  /*__native_client_codegen__*/
6945                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6946                         }
6947
6948                         /* Take prolog and epilog instrumentation into account */
6949                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6950                                 max_length += max_epilog_size;
6951
6952                         bb->max_length = max_length;
6953                 }
6954         }
6955
6956         sig = mono_method_signature (method);
6957         pos = 0;
6958
6959         cinfo = cfg->arch.cinfo;
6960
6961         if (sig->ret->type != MONO_TYPE_VOID) {
6962                 /* Save volatile arguments to the stack */
6963                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6964                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6965         }
6966
6967         /* Keep this in sync with emit_load_volatile_arguments */
6968         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6969                 ArgInfo *ainfo = cinfo->args + i;
6970
6971                 ins = cfg->args [i];
6972
6973                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6974                         /* Unused arguments */
6975                         continue;
6976
6977                 /* Save volatile arguments to the stack */
6978                 if (ins->opcode != OP_REGVAR) {
6979                         switch (ainfo->storage) {
6980                         case ArgInIReg: {
6981                                 guint32 size = 8;
6982
6983                                 /* FIXME: I1 etc */
6984                                 /*
6985                                 if (stack_offset & 0x1)
6986                                         size = 1;
6987                                 else if (stack_offset & 0x2)
6988                                         size = 2;
6989                                 else if (stack_offset & 0x4)
6990                                         size = 4;
6991                                 else
6992                                         size = 8;
6993                                 */
6994                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6995
6996                                 /*
6997                                  * Save the original location of 'this',
6998                                  * get_generic_info_from_stack_frame () needs this to properly look up
6999                                  * the argument value during the handling of async exceptions.
7000                                  */
7001                                 if (ins == cfg->args [0]) {
7002                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7003                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7004                                 }
7005                                 break;
7006                         }
7007                         case ArgInFloatSSEReg:
7008                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7009                                 break;
7010                         case ArgInDoubleSSEReg:
7011                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7012                                 break;
7013                         case ArgValuetypeInReg:
7014                                 for (quad = 0; quad < 2; quad ++) {
7015                                         switch (ainfo->pair_storage [quad]) {
7016                                         case ArgInIReg:
7017                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7018                                                 break;
7019                                         case ArgInFloatSSEReg:
7020                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7021                                                 break;
7022                                         case ArgInDoubleSSEReg:
7023                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7024                                                 break;
7025                                         case ArgNone:
7026                                                 break;
7027                                         default:
7028                                                 g_assert_not_reached ();
7029                                         }
7030                                 }
7031                                 break;
7032                         case ArgValuetypeAddrInIReg:
7033                                 if (ainfo->pair_storage [0] == ArgInIReg)
7034                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7035                                 break;
7036                         default:
7037                                 break;
7038                         }
7039                 } else {
7040                         /* Argument allocated to (non-volatile) register */
7041                         switch (ainfo->storage) {
7042                         case ArgInIReg:
7043                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7044                                 break;
7045                         case ArgOnStack:
7046                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7047                                 break;
7048                         default:
7049                                 g_assert_not_reached ();
7050                         }
7051
7052                         if (ins == cfg->args [0]) {
7053                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7054                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7055                         }
7056                 }
7057         }
7058
7059         if (cfg->method->save_lmf)
7060                 args_clobbered = TRUE;
7061
7062         if (trace) {
7063                 args_clobbered = TRUE;
7064                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7065         }
7066
7067         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7068                 args_clobbered = TRUE;
7069
7070         /*
7071          * Optimize the common case of the first bblock making a call with the same
7072          * arguments as the method. This works because the arguments are still in their
7073          * original argument registers.
7074          * FIXME: Generalize this
7075          */
7076         if (!args_clobbered) {
7077                 MonoBasicBlock *first_bb = cfg->bb_entry;
7078                 MonoInst *next;
7079                 int filter = FILTER_IL_SEQ_POINT;
7080
7081                 next = mono_bb_first_inst (first_bb, filter);
7082                 if (!next && first_bb->next_bb) {
7083                         first_bb = first_bb->next_bb;
7084                         next = mono_bb_first_inst (first_bb, filter);
7085                 }
7086
7087                 if (first_bb->in_count > 1)
7088                         next = NULL;
7089
7090                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7091                         ArgInfo *ainfo = cinfo->args + i;
7092                         gboolean match = FALSE;
7093
7094                         ins = cfg->args [i];
7095                         if (ins->opcode != OP_REGVAR) {
7096                                 switch (ainfo->storage) {
7097                                 case ArgInIReg: {
7098                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7099                                                 if (next->dreg == ainfo->reg) {
7100                                                         NULLIFY_INS (next);
7101                                                         match = TRUE;
7102                                                 } else {
7103                                                         next->opcode = OP_MOVE;
7104                                                         next->sreg1 = ainfo->reg;
7105                                                         /* Only continue if the instruction doesn't change argument regs */
7106                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7107                                                                 match = TRUE;
7108                                                 }
7109                                         }
7110                                         break;
7111                                 }
7112                                 default:
7113                                         break;
7114                                 }
7115                         } else {
7116                                 /* Argument allocated to (non-volatile) register */
7117                                 switch (ainfo->storage) {
7118                                 case ArgInIReg:
7119                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7120                                                 NULLIFY_INS (next);
7121                                                 match = TRUE;
7122                                         }
7123                                         break;
7124                                 default:
7125                                         break;
7126                                 }
7127                         }
7128
7129                         if (match) {
7130                                 next = mono_inst_next (next, filter);
7131                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7132                                 if (!next)
7133                                         break;
7134                         }
7135                 }
7136         }
7137
7138         if (cfg->gen_sdb_seq_points) {
7139                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7140
7141                 /* Initialize seq_point_info_var */
7142                 if (cfg->compile_aot) {
7143                         /* Initialize the variable from a GOT slot */
7144                         /* Same as OP_AOTCONST */
7145                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7146                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7147                         g_assert (info_var->opcode == OP_REGOFFSET);
7148                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7149                 }
7150
7151                 if (cfg->compile_aot) {
7152                         /* Initialize ss_tramp_var */
7153                         ins = cfg->arch.ss_tramp_var;
7154                         g_assert (ins->opcode == OP_REGOFFSET);
7155
7156                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7157                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7158                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7159                 } else {
7160                         /* Initialize ss_trigger_page_var */
7161                         ins = cfg->arch.ss_trigger_page_var;
7162
7163                         g_assert (ins->opcode == OP_REGOFFSET);
7164
7165                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7166                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7167                 }
7168         }
7169
7170         cfg->code_len = code - cfg->native_code;
7171
7172         g_assert (cfg->code_len < cfg->code_size);
7173
7174         return code;
7175 }
7176
7177 void
7178 mono_arch_emit_epilog (MonoCompile *cfg)
7179 {
7180         MonoMethod *method = cfg->method;
7181         int quad, i;
7182         guint8 *code;
7183         int max_epilog_size;
7184         CallInfo *cinfo;
7185         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7186         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7187
7188         max_epilog_size = get_max_epilog_size (cfg);
7189
7190         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7191                 cfg->code_size *= 2;
7192                 cfg->native_code = mono_realloc_native_code (cfg);
7193                 cfg->stat_code_reallocs++;
7194         }
7195         code = cfg->native_code + cfg->code_len;
7196
7197         cfg->has_unwind_info_for_epilog = TRUE;
7198
7199         /* Mark the start of the epilog */
7200         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7201
7202         /* Save the uwind state which is needed by the out-of-line code */
7203         mono_emit_unwind_op_remember_state (cfg, code);
7204
7205         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7206                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7207
7208         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7209
7210         if (method->save_lmf) {
7211                 /* check if we need to restore protection of the stack after a stack overflow */
7212                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7213                         guint8 *patch;
7214                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7215                         /* we load the value in a separate instruction: this mechanism may be
7216                          * used later as a safer way to do thread interruption
7217                          */
7218                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7219                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7220                         patch = code;
7221                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7222                         /* note that the call trampoline will preserve eax/edx */
7223                         x86_call_reg (code, X86_ECX);
7224                         x86_patch (patch, code);
7225                 } else {
7226                         /* FIXME: maybe save the jit tls in the prolog */
7227                 }
7228                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7229                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7230                 }
7231         }
7232
7233         /* Restore callee saved regs */
7234         for (i = 0; i < AMD64_NREG; ++i) {
7235                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7236                         /* Restore only used_int_regs, not arch.saved_iregs */
7237                         if (cfg->used_int_regs & (1 << i)) {
7238                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7239                                 mono_emit_unwind_op_same_value (cfg, code, i);
7240                                 async_exc_point (code);
7241                         }
7242                         save_area_offset += 8;
7243                 }
7244         }
7245
7246         /* Load returned vtypes into registers if needed */
7247         cinfo = cfg->arch.cinfo;
7248         if (cinfo->ret.storage == ArgValuetypeInReg) {
7249                 ArgInfo *ainfo = &cinfo->ret;
7250                 MonoInst *inst = cfg->ret;
7251
7252                 for (quad = 0; quad < 2; quad ++) {
7253                         switch (ainfo->pair_storage [quad]) {
7254                         case ArgInIReg:
7255                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7256                                 break;
7257                         case ArgInFloatSSEReg:
7258                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7259                                 break;
7260                         case ArgInDoubleSSEReg:
7261                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7262                                 break;
7263                         case ArgNone:
7264                                 break;
7265                         default:
7266                                 g_assert_not_reached ();
7267                         }
7268                 }
7269         }
7270
7271         if (cfg->arch.omit_fp) {
7272                 if (cfg->arch.stack_alloc_size) {
7273                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7274                 }
7275         } else {
7276                 amd64_leave (code);
7277                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7278         }
7279         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7280         async_exc_point (code);
7281         amd64_ret (code);
7282
7283         /* Restore the unwind state to be the same as before the epilog */
7284         mono_emit_unwind_op_restore_state (cfg, code);
7285
7286         cfg->code_len = code - cfg->native_code;
7287
7288         g_assert (cfg->code_len < cfg->code_size);
7289 }
7290
7291 void
7292 mono_arch_emit_exceptions (MonoCompile *cfg)
7293 {
7294         MonoJumpInfo *patch_info;
7295         int nthrows, i;
7296         guint8 *code;
7297         MonoClass *exc_classes [16];
7298         guint8 *exc_throw_start [16], *exc_throw_end [16];
7299         guint32 code_size = 0;
7300
7301         /* Compute needed space */
7302         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7303                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7304                         code_size += 40;
7305                 if (patch_info->type == MONO_PATCH_INFO_R8)
7306                         code_size += 8 + 15; /* sizeof (double) + alignment */
7307                 if (patch_info->type == MONO_PATCH_INFO_R4)
7308                         code_size += 4 + 15; /* sizeof (float) + alignment */
7309                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7310                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7311         }
7312
7313 #ifdef __native_client_codegen__
7314         /* Give us extra room on Native Client.  This could be   */
7315         /* more carefully calculated, but bundle alignment makes */
7316         /* it much trickier, so *2 like other places is good.    */
7317         code_size *= 2;
7318 #endif
7319
7320         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7321                 cfg->code_size *= 2;
7322                 cfg->native_code = mono_realloc_native_code (cfg);
7323                 cfg->stat_code_reallocs++;
7324         }
7325
7326         code = cfg->native_code + cfg->code_len;
7327
7328         /* add code to raise exceptions */
7329         nthrows = 0;
7330         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7331                 switch (patch_info->type) {
7332                 case MONO_PATCH_INFO_EXC: {
7333                         MonoClass *exc_class;
7334                         guint8 *buf, *buf2;
7335                         guint32 throw_ip;
7336
7337                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7338
7339                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7340                         g_assert (exc_class);
7341                         throw_ip = patch_info->ip.i;
7342
7343                         //x86_breakpoint (code);
7344                         /* Find a throw sequence for the same exception class */
7345                         for (i = 0; i < nthrows; ++i)
7346                                 if (exc_classes [i] == exc_class)
7347                                         break;
7348                         if (i < nthrows) {
7349                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7350                                 x86_jump_code (code, exc_throw_start [i]);
7351                                 patch_info->type = MONO_PATCH_INFO_NONE;
7352                         }
7353                         else {
7354                                 buf = code;
7355                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7356                                 buf2 = code;
7357
7358                                 if (nthrows < 16) {
7359                                         exc_classes [nthrows] = exc_class;
7360                                         exc_throw_start [nthrows] = code;
7361                                 }
7362                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7363
7364                                 patch_info->type = MONO_PATCH_INFO_NONE;
7365
7366                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7367
7368                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7369                                 while (buf < buf2)
7370                                         x86_nop (buf);
7371
7372                                 if (nthrows < 16) {
7373                                         exc_throw_end [nthrows] = code;
7374                                         nthrows ++;
7375                                 }
7376                         }
7377                         break;
7378                 }
7379                 default:
7380                         /* do nothing */
7381                         break;
7382                 }
7383                 g_assert(code < cfg->native_code + cfg->code_size);
7384         }
7385
7386         /* Handle relocations with RIP relative addressing */
7387         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7388                 gboolean remove = FALSE;
7389                 guint8 *orig_code = code;
7390
7391                 switch (patch_info->type) {
7392                 case MONO_PATCH_INFO_R8:
7393                 case MONO_PATCH_INFO_R4: {
7394                         guint8 *pos, *patch_pos;
7395                         guint32 target_pos;
7396
7397                         /* The SSE opcodes require a 16 byte alignment */
7398 #if defined(__default_codegen__)
7399                         code = (guint8*)ALIGN_TO (code, 16);
7400 #elif defined(__native_client_codegen__)
7401                         {
7402                                 /* Pad this out with HLT instructions  */
7403                                 /* or we can get garbage bytes emitted */
7404                                 /* which will fail validation          */
7405                                 guint8 *aligned_code;
7406                                 /* extra align to make room for  */
7407                                 /* mov/push below                      */
7408                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7409                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7410                                 /* The technique of hiding data in an  */
7411                                 /* instruction has a problem here: we  */
7412                                 /* need the data aligned to a 16-byte  */
7413                                 /* boundary but the instruction cannot */
7414                                 /* cross the bundle boundary. so only  */
7415                                 /* odd multiples of 16 can be used     */
7416                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7417                                         aligned_code += 16;
7418                                 }
7419                                 while (code < aligned_code) {
7420                                         *(code++) = 0xf4; /* hlt */
7421                                 }
7422                         }
7423 #endif
7424
7425                         pos = cfg->native_code + patch_info->ip.i;
7426                         if (IS_REX (pos [1])) {
7427                                 patch_pos = pos + 5;
7428                                 target_pos = code - pos - 9;
7429                         }
7430                         else {
7431                                 patch_pos = pos + 4;
7432                                 target_pos = code - pos - 8;
7433                         }
7434
7435                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7436 #ifdef __native_client_codegen__
7437                                 /* Hide 64-bit data in a         */
7438                                 /* "mov imm64, r11" instruction. */
7439                                 /* write it before the start of  */
7440                                 /* the data*/
7441                                 *(code-2) = 0x49; /* prefix      */
7442                                 *(code-1) = 0xbb; /* mov X, %r11 */
7443 #endif
7444                                 *(double*)code = *(double*)patch_info->data.target;
7445                                 code += sizeof (double);
7446                         } else {
7447 #ifdef __native_client_codegen__
7448                                 /* Hide 32-bit data in a        */
7449                                 /* "push imm32" instruction.    */
7450                                 *(code-1) = 0x68; /* push */
7451 #endif
7452                                 *(float*)code = *(float*)patch_info->data.target;
7453                                 code += sizeof (float);
7454                         }
7455
7456                         *(guint32*)(patch_pos) = target_pos;
7457
7458                         remove = TRUE;
7459                         break;
7460                 }
7461                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7462                         guint8 *pos;
7463
7464                         if (cfg->compile_aot)
7465                                 continue;
7466
7467                         /*loading is faster against aligned addresses.*/
7468                         code = (guint8*)ALIGN_TO (code, 8);
7469                         memset (orig_code, 0, code - orig_code);
7470
7471                         pos = cfg->native_code + patch_info->ip.i;
7472
7473                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7474                         if (IS_REX (pos [1]))
7475                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7476                         else
7477                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7478
7479                         *(gpointer*)code = (gpointer)patch_info->data.target;
7480                         code += sizeof (gpointer);
7481
7482                         remove = TRUE;
7483                         break;
7484                 }
7485                 default:
7486                         break;
7487                 }
7488
7489                 if (remove) {
7490                         if (patch_info == cfg->patch_info)
7491                                 cfg->patch_info = patch_info->next;
7492                         else {
7493                                 MonoJumpInfo *tmp;
7494
7495                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7496                                         ;
7497                                 tmp->next = patch_info->next;
7498                         }
7499                 }
7500                 g_assert (code < cfg->native_code + cfg->code_size);
7501         }
7502
7503         cfg->code_len = code - cfg->native_code;
7504
7505         g_assert (cfg->code_len < cfg->code_size);
7506
7507 }
7508
7509 #endif /* DISABLE_JIT */
7510
7511 void*
7512 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7513 {
7514         guchar *code = p;
7515         MonoMethodSignature *sig;
7516         MonoInst *inst;
7517         int i, n, stack_area = 0;
7518
7519         /* Keep this in sync with mono_arch_get_argument_info */
7520
7521         if (enable_arguments) {
7522                 /* Allocate a new area on the stack and save arguments there */
7523                 sig = mono_method_signature (cfg->method);
7524
7525                 n = sig->param_count + sig->hasthis;
7526
7527                 stack_area = ALIGN_TO (n * 8, 16);
7528
7529                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7530
7531                 for (i = 0; i < n; ++i) {
7532                         inst = cfg->args [i];
7533
7534                         if (inst->opcode == OP_REGVAR)
7535                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7536                         else {
7537                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7538                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7539                         }
7540                 }
7541         }
7542
7543         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7544         amd64_set_reg_template (code, AMD64_ARG_REG1);
7545         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7546         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7547
7548         if (enable_arguments)
7549                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7550
7551         return code;
7552 }
7553
7554 enum {
7555         SAVE_NONE,
7556         SAVE_STRUCT,
7557         SAVE_EAX,
7558         SAVE_EAX_EDX,
7559         SAVE_XMM
7560 };
7561
7562 void*
7563 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7564 {
7565         guchar *code = p;
7566         int save_mode = SAVE_NONE;
7567         MonoMethod *method = cfg->method;
7568         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7569         int i;
7570
7571         switch (ret_type->type) {
7572         case MONO_TYPE_VOID:
7573                 /* special case string .ctor icall */
7574                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7575                         save_mode = SAVE_EAX;
7576                 else
7577                         save_mode = SAVE_NONE;
7578                 break;
7579         case MONO_TYPE_I8:
7580         case MONO_TYPE_U8:
7581                 save_mode = SAVE_EAX;
7582                 break;
7583         case MONO_TYPE_R4:
7584         case MONO_TYPE_R8:
7585                 save_mode = SAVE_XMM;
7586                 break;
7587         case MONO_TYPE_GENERICINST:
7588                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7589                         save_mode = SAVE_EAX;
7590                         break;
7591                 }
7592                 /* Fall through */
7593         case MONO_TYPE_VALUETYPE:
7594                 save_mode = SAVE_STRUCT;
7595                 break;
7596         default:
7597                 save_mode = SAVE_EAX;
7598                 break;
7599         }
7600
7601         /* Save the result and copy it into the proper argument register */
7602         switch (save_mode) {
7603         case SAVE_EAX:
7604                 amd64_push_reg (code, AMD64_RAX);
7605                 /* Align stack */
7606                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7607                 if (enable_arguments)
7608                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7609                 break;
7610         case SAVE_STRUCT:
7611                 /* FIXME: */
7612                 if (enable_arguments)
7613                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7614                 break;
7615         case SAVE_XMM:
7616                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7617                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7618                 /* Align stack */
7619                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7620                 /*
7621                  * The result is already in the proper argument register so no copying
7622                  * needed.
7623                  */
7624                 break;
7625         case SAVE_NONE:
7626                 break;
7627         default:
7628                 g_assert_not_reached ();
7629         }
7630
7631         /* Set %al since this is a varargs call */
7632         if (save_mode == SAVE_XMM)
7633                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7634         else
7635                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7636
7637         if (preserve_argument_registers) {
7638                 for (i = 0; i < PARAM_REGS; ++i)
7639                         amd64_push_reg (code, param_regs [i]);
7640         }
7641
7642         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7643         amd64_set_reg_template (code, AMD64_ARG_REG1);
7644         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7645
7646         if (preserve_argument_registers) {
7647                 for (i = PARAM_REGS - 1; i >= 0; --i)
7648                         amd64_pop_reg (code, param_regs [i]);
7649         }
7650
7651         /* Restore result */
7652         switch (save_mode) {
7653         case SAVE_EAX:
7654                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7655                 amd64_pop_reg (code, AMD64_RAX);
7656                 break;
7657         case SAVE_STRUCT:
7658                 /* FIXME: */
7659                 break;
7660         case SAVE_XMM:
7661                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7662                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7663                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7664                 break;
7665         case SAVE_NONE:
7666                 break;
7667         default:
7668                 g_assert_not_reached ();
7669         }
7670
7671         return code;
7672 }
7673
7674 void
7675 mono_arch_flush_icache (guint8 *code, gint size)
7676 {
7677         /* Not needed */
7678 }
7679
7680 void
7681 mono_arch_flush_register_windows (void)
7682 {
7683 }
7684
7685 gboolean
7686 mono_arch_is_inst_imm (gint64 imm)
7687 {
7688         return amd64_use_imm32 (imm);
7689 }
7690
7691 /*
7692  * Determine whenever the trap whose info is in SIGINFO is caused by
7693  * integer overflow.
7694  */
7695 gboolean
7696 mono_arch_is_int_overflow (void *sigctx, void *info)
7697 {
7698         MonoContext ctx;
7699         guint8* rip;
7700         int reg;
7701         gint64 value;
7702
7703         mono_sigctx_to_monoctx (sigctx, &ctx);
7704
7705         rip = (guint8*)ctx.gregs [AMD64_RIP];
7706
7707         if (IS_REX (rip [0])) {
7708                 reg = amd64_rex_b (rip [0]);
7709                 rip ++;
7710         }
7711         else
7712                 reg = 0;
7713
7714         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7715                 /* idiv REG */
7716                 reg += x86_modrm_rm (rip [1]);
7717
7718                 value = ctx.gregs [reg];
7719
7720                 if (value == -1)
7721                         return TRUE;
7722         }
7723
7724         return FALSE;
7725 }
7726
7727 guint32
7728 mono_arch_get_patch_offset (guint8 *code)
7729 {
7730         return 3;
7731 }
7732
7733 /**
7734  * mono_breakpoint_clean_code:
7735  *
7736  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7737  * breakpoints in the original code, they are removed in the copy.
7738  *
7739  * Returns TRUE if no sw breakpoint was present.
7740  */
7741 gboolean
7742 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7743 {
7744         /*
7745          * If method_start is non-NULL we need to perform bound checks, since we access memory
7746          * at code - offset we could go before the start of the method and end up in a different
7747          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7748          * instead.
7749          */
7750         if (!method_start || code - offset >= method_start) {
7751                 memcpy (buf, code - offset, size);
7752         } else {
7753                 int diff = code - method_start;
7754                 memset (buf, 0, size);
7755                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7756         }
7757         return TRUE;
7758 }
7759
7760 #if defined(__native_client_codegen__)
7761 /* For membase calls, we want the base register. for Native Client,  */
7762 /* all indirect calls have the following sequence with the given sizes: */
7763 /* mov %eXX,%eXX                                [2-3]   */
7764 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7765 /* and $0xffffffffffffffe0,%r11d                [4]     */
7766 /* add %r15,%r11                                [3]     */
7767 /* callq *%r11                                  [3]     */
7768
7769
7770 /* Determine if code points to a NaCl call-through-register sequence, */
7771 /* (i.e., the last 3 instructions listed above) */
7772 int
7773 is_nacl_call_reg_sequence(guint8* code)
7774 {
7775         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7776                                "\x4d\x03\xdf"     /* add */
7777                                "\x41\xff\xd3";   /* call */
7778         return memcmp(code, sequence, 10) == 0;
7779 }
7780
7781 /* Determine if code points to the first opcode of the mov membase component */
7782 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7783 /* (there could be a REX prefix before the opcode but it is ignored) */
7784 static int
7785 is_nacl_indirect_call_membase_sequence(guint8* code)
7786 {
7787                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7788         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7789                /* and that src reg = dest reg */
7790                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7791                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7792                IS_REX(code[2]) &&
7793                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7794                /* and has dst of r11 and base of r15 */
7795                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7796                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7797 }
7798 #endif /* __native_client_codegen__ */
7799
7800 int
7801 mono_arch_get_this_arg_reg (guint8 *code)
7802 {
7803         return AMD64_ARG_REG1;
7804 }
7805
7806 gpointer
7807 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7808 {
7809         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7810 }
7811
7812 #define MAX_ARCH_DELEGATE_PARAMS 10
7813
7814 static gpointer
7815 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7816 {
7817         guint8 *code, *start;
7818         GSList *unwind_ops = NULL;
7819         int i;
7820
7821         unwind_ops = mono_arch_get_cie_program ();
7822
7823         if (has_target) {
7824                 start = code = mono_global_codeman_reserve (64);
7825
7826                 /* Replace the this argument with the target */
7827                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7828                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7829                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7830
7831                 g_assert ((code - start) < 64);
7832         } else {
7833                 start = code = mono_global_codeman_reserve (64);
7834
7835                 if (param_count == 0) {
7836                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7837                 } else {
7838                         /* We have to shift the arguments left */
7839                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7840                         for (i = 0; i < param_count; ++i) {
7841 #ifdef TARGET_WIN32
7842                                 if (i < 3)
7843                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7844                                 else
7845                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7846 #else
7847                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7848 #endif
7849                         }
7850
7851                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7852                 }
7853                 g_assert ((code - start) < 64);
7854         }
7855
7856         nacl_global_codeman_validate (&start, 64, &code);
7857         mono_arch_flush_icache (start, code - start);
7858
7859         if (has_target) {
7860                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7861         } else {
7862                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7863                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7864                 g_free (name);
7865         }
7866
7867         if (mono_jit_map_is_enabled ()) {
7868                 char *buff;
7869                 if (has_target)
7870                         buff = (char*)"delegate_invoke_has_target";
7871                 else
7872                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7873                 mono_emit_jit_tramp (start, code - start, buff);
7874                 if (!has_target)
7875                         g_free (buff);
7876         }
7877         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7878
7879         return start;
7880 }
7881
7882 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7883
7884 static gpointer
7885 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7886 {
7887         guint8 *code, *start;
7888         int size = 20;
7889         char *tramp_name;
7890         GSList *unwind_ops;
7891
7892         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7893                 return NULL;
7894
7895         start = code = mono_global_codeman_reserve (size);
7896
7897         unwind_ops = mono_arch_get_cie_program ();
7898
7899         /* Replace the this argument with the target */
7900         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7901         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7902
7903         if (load_imt_reg) {
7904                 /* Load the IMT reg */
7905                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7906         }
7907
7908         /* Load the vtable */
7909         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7910         amd64_jump_membase (code, AMD64_RAX, offset);
7911         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7912
7913         if (load_imt_reg)
7914                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
7915         else
7916                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
7917         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7918         g_free (tramp_name);
7919
7920         return start;
7921 }
7922
7923 /*
7924  * mono_arch_get_delegate_invoke_impls:
7925  *
7926  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7927  * trampolines.
7928  */
7929 GSList*
7930 mono_arch_get_delegate_invoke_impls (void)
7931 {
7932         GSList *res = NULL;
7933         MonoTrampInfo *info;
7934         int i;
7935
7936         get_delegate_invoke_impl (&info, TRUE, 0);
7937         res = g_slist_prepend (res, info);
7938
7939         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7940                 get_delegate_invoke_impl (&info, FALSE, i);
7941                 res = g_slist_prepend (res, info);
7942         }
7943
7944         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7945                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7946                 res = g_slist_prepend (res, info);
7947
7948                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7949                 res = g_slist_prepend (res, info);
7950         }
7951
7952         return res;
7953 }
7954
7955 gpointer
7956 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7957 {
7958         guint8 *code, *start;
7959         int i;
7960
7961         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7962                 return NULL;
7963
7964         /* FIXME: Support more cases */
7965         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7966                 return NULL;
7967
7968         if (has_target) {
7969                 static guint8* cached = NULL;
7970
7971                 if (cached)
7972                         return cached;
7973
7974                 if (mono_aot_only) {
7975                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7976                 } else {
7977                         MonoTrampInfo *info;
7978                         start = get_delegate_invoke_impl (&info, TRUE, 0);
7979                         mono_tramp_info_register (info, NULL);
7980                 }
7981
7982                 mono_memory_barrier ();
7983
7984                 cached = start;
7985         } else {
7986                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7987                 for (i = 0; i < sig->param_count; ++i)
7988                         if (!mono_is_regsize_var (sig->params [i]))
7989                                 return NULL;
7990                 if (sig->param_count > 4)
7991                         return NULL;
7992
7993                 code = cache [sig->param_count];
7994                 if (code)
7995                         return code;
7996
7997                 if (mono_aot_only) {
7998                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7999                         start = mono_aot_get_trampoline (name);
8000                         g_free (name);
8001                 } else {
8002                         MonoTrampInfo *info;
8003                         start = get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8004                         mono_tramp_info_register (info, NULL);
8005                 }
8006
8007                 mono_memory_barrier ();
8008
8009                 cache [sig->param_count] = start;
8010         }
8011
8012         return start;
8013 }
8014
8015 gpointer
8016 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8017 {
8018         MonoTrampInfo *info;
8019         gpointer code;
8020
8021         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8022         if (code)
8023                 mono_tramp_info_register (info, NULL);
8024         return code;
8025 }
8026
8027 void
8028 mono_arch_finish_init (void)
8029 {
8030 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8031         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8032 #endif
8033 }
8034
8035 void
8036 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8037 {
8038 }
8039
8040 #if defined(__default_codegen__)
8041 #define CMP_SIZE (6 + 1)
8042 #define CMP_REG_REG_SIZE (4 + 1)
8043 #define BR_SMALL_SIZE 2
8044 #define BR_LARGE_SIZE 6
8045 #define MOV_REG_IMM_SIZE 10
8046 #define MOV_REG_IMM_32BIT_SIZE 6
8047 #define JUMP_REG_SIZE (2 + 1)
8048 #elif defined(__native_client_codegen__)
8049 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8050 #define CMP_SIZE ((6 + 1) * 2 - 1)
8051 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8052 #define BR_SMALL_SIZE (2 * 2 - 1)
8053 #define BR_LARGE_SIZE (6 * 2 - 1)
8054 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8055 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8056 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8057 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8058 /* Jump membase's size is large and unpredictable    */
8059 /* in native client, just pad it out a whole bundle. */
8060 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8061 #endif
8062
8063 static int
8064 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8065 {
8066         int i, distance = 0;
8067         for (i = start; i < target; ++i)
8068                 distance += imt_entries [i]->chunk_size;
8069         return distance;
8070 }
8071
8072 /*
8073  * LOCKING: called with the domain lock held
8074  */
8075 gpointer
8076 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8077         gpointer fail_tramp)
8078 {
8079         int i;
8080         int size = 0;
8081         guint8 *code, *start;
8082         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8083         GSList *unwind_ops;
8084
8085         for (i = 0; i < count; ++i) {
8086                 MonoIMTCheckItem *item = imt_entries [i];
8087                 if (item->is_equals) {
8088                         if (item->check_target_idx) {
8089                                 if (!item->compare_done) {
8090                                         if (amd64_use_imm32 ((gint64)item->key))
8091                                                 item->chunk_size += CMP_SIZE;
8092                                         else
8093                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8094                                 }
8095                                 if (item->has_target_code) {
8096                                         item->chunk_size += MOV_REG_IMM_SIZE;
8097                                 } else {
8098                                         if (vtable_is_32bit)
8099                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8100                                         else
8101                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8102 #ifdef __native_client_codegen__
8103                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8104 #endif
8105                                 }
8106                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8107                         } else {
8108                                 if (fail_tramp) {
8109                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8110                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8111                                 } else {
8112                                         if (vtable_is_32bit)
8113                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8114                                         else
8115                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8116                                         item->chunk_size += JUMP_REG_SIZE;
8117                                         /* with assert below:
8118                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8119                                          */
8120 #ifdef __native_client_codegen__
8121                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8122 #endif
8123                                 }
8124                         }
8125                 } else {
8126                         if (amd64_use_imm32 ((gint64)item->key))
8127                                 item->chunk_size += CMP_SIZE;
8128                         else
8129                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8130                         item->chunk_size += BR_LARGE_SIZE;
8131                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8132                 }
8133                 size += item->chunk_size;
8134         }
8135 #if defined(__native_client__) && defined(__native_client_codegen__)
8136         /* In Native Client, we don't re-use thunks, allocate from the */
8137         /* normal code manager paths. */
8138         code = mono_domain_code_reserve (domain, size);
8139 #else
8140         if (fail_tramp)
8141                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8142         else
8143                 code = mono_domain_code_reserve (domain, size);
8144 #endif
8145         start = code;
8146
8147         unwind_ops = mono_arch_get_cie_program ();
8148
8149         for (i = 0; i < count; ++i) {
8150                 MonoIMTCheckItem *item = imt_entries [i];
8151                 item->code_target = code;
8152                 if (item->is_equals) {
8153                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8154
8155                         if (item->check_target_idx || fail_case) {
8156                                 if (!item->compare_done || fail_case) {
8157                                         if (amd64_use_imm32 ((gint64)item->key))
8158                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8159                                         else {
8160                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8161                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8162                                         }
8163                                 }
8164                                 item->jmp_code = code;
8165                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8166                                 if (item->has_target_code) {
8167                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8168                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8169                                 } else {
8170                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8171                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8172                                 }
8173
8174                                 if (fail_case) {
8175                                         amd64_patch (item->jmp_code, code);
8176                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8177                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8178                                         item->jmp_code = NULL;
8179                                 }
8180                         } else {
8181                                 /* enable the commented code to assert on wrong method */
8182 #if 0
8183                                 if (amd64_is_imm32 (item->key))
8184                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8185                                 else {
8186                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8187                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8188                                 }
8189                                 item->jmp_code = code;
8190                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8191                                 /* See the comment below about R10 */
8192                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8193                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8194                                 amd64_patch (item->jmp_code, code);
8195                                 amd64_breakpoint (code);
8196                                 item->jmp_code = NULL;
8197 #else
8198                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8199                                    needs to be preserved.  R10 needs
8200                                    to be preserved for calls which
8201                                    require a runtime generic context,
8202                                    but interface calls don't. */
8203                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8204                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8205 #endif
8206                         }
8207                 } else {
8208                         if (amd64_use_imm32 ((gint64)item->key))
8209                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8210                         else {
8211                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8212                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8213                         }
8214                         item->jmp_code = code;
8215                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8216                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8217                         else
8218                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8219                 }
8220                 g_assert (code - item->code_target <= item->chunk_size);
8221         }
8222         /* patch the branches to get to the target items */
8223         for (i = 0; i < count; ++i) {
8224                 MonoIMTCheckItem *item = imt_entries [i];
8225                 if (item->jmp_code) {
8226                         if (item->check_target_idx) {
8227                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8228                         }
8229                 }
8230         }
8231
8232         if (!fail_tramp)
8233                 mono_stats.imt_thunks_size += code - start;
8234         g_assert (code - start <= size);
8235
8236         nacl_domain_code_validate(domain, &start, size, &code);
8237         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8238
8239         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8240
8241         return start;
8242 }
8243
8244 MonoMethod*
8245 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8246 {
8247         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8248 }
8249
8250 MonoVTable*
8251 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8252 {
8253         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8254 }
8255
8256 GSList*
8257 mono_arch_get_cie_program (void)
8258 {
8259         GSList *l = NULL;
8260
8261         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8262         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8263
8264         return l;
8265 }
8266
8267 #ifndef DISABLE_JIT
8268
8269 MonoInst*
8270 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8271 {
8272         MonoInst *ins = NULL;
8273         int opcode = 0;
8274
8275         if (cmethod->klass == mono_defaults.math_class) {
8276                 if (strcmp (cmethod->name, "Sin") == 0) {
8277                         opcode = OP_SIN;
8278                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8279                         opcode = OP_COS;
8280                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8281                         opcode = OP_SQRT;
8282                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8283                         opcode = OP_ABS;
8284                 }
8285
8286                 if (opcode && fsig->param_count == 1) {
8287                         MONO_INST_NEW (cfg, ins, opcode);
8288                         ins->type = STACK_R8;
8289                         ins->dreg = mono_alloc_freg (cfg);
8290                         ins->sreg1 = args [0]->dreg;
8291                         MONO_ADD_INS (cfg->cbb, ins);
8292                 }
8293
8294                 opcode = 0;
8295                 if (cfg->opt & MONO_OPT_CMOV) {
8296                         if (strcmp (cmethod->name, "Min") == 0) {
8297                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8298                                         opcode = OP_IMIN;
8299                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8300                                         opcode = OP_IMIN_UN;
8301                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8302                                         opcode = OP_LMIN;
8303                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8304                                         opcode = OP_LMIN_UN;
8305                         } else if (strcmp (cmethod->name, "Max") == 0) {
8306                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8307                                         opcode = OP_IMAX;
8308                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8309                                         opcode = OP_IMAX_UN;
8310                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8311                                         opcode = OP_LMAX;
8312                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8313                                         opcode = OP_LMAX_UN;
8314                         }
8315                 }
8316
8317                 if (opcode && fsig->param_count == 2) {
8318                         MONO_INST_NEW (cfg, ins, opcode);
8319                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8320                         ins->dreg = mono_alloc_ireg (cfg);
8321                         ins->sreg1 = args [0]->dreg;
8322                         ins->sreg2 = args [1]->dreg;
8323                         MONO_ADD_INS (cfg->cbb, ins);
8324                 }
8325
8326 #if 0
8327                 /* OP_FREM is not IEEE compatible */
8328                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8329                         MONO_INST_NEW (cfg, ins, OP_FREM);
8330                         ins->inst_i0 = args [0];
8331                         ins->inst_i1 = args [1];
8332                 }
8333 #endif
8334         }
8335
8336         return ins;
8337 }
8338 #endif
8339
8340 gboolean
8341 mono_arch_print_tree (MonoInst *tree, int arity)
8342 {
8343         return 0;
8344 }
8345
8346 mgreg_t
8347 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8348 {
8349         return ctx->gregs [reg];
8350 }
8351
8352 void
8353 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8354 {
8355         ctx->gregs [reg] = val;
8356 }
8357
8358 gpointer
8359 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8360 {
8361         gpointer *sp, old_value;
8362         char *bp;
8363
8364         /*Load the spvar*/
8365         bp = MONO_CONTEXT_GET_BP (ctx);
8366         sp = *(gpointer*)(bp + clause->exvar_offset);
8367
8368         old_value = *sp;
8369         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8370                 return old_value;
8371
8372         *sp = new_value;
8373
8374         return old_value;
8375 }
8376
8377 /*
8378  * mono_arch_emit_load_aotconst:
8379  *
8380  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8381  * TARGET from the mscorlib GOT in full-aot code.
8382  * On AMD64, the result is placed into R11.
8383  */
8384 guint8*
8385 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8386 {
8387         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8388         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8389
8390         return code;
8391 }
8392
8393 /*
8394  * mono_arch_get_trampolines:
8395  *
8396  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8397  * for AOT.
8398  */
8399 GSList *
8400 mono_arch_get_trampolines (gboolean aot)
8401 {
8402         return mono_amd64_get_exception_trampolines (aot);
8403 }
8404
8405 /* Soft Debug support */
8406 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8407
8408 /*
8409  * mono_arch_set_breakpoint:
8410  *
8411  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8412  * The location should contain code emitted by OP_SEQ_POINT.
8413  */
8414 void
8415 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8416 {
8417         guint8 *code = ip;
8418         guint8 *orig_code = code;
8419
8420         if (ji->from_aot) {
8421                 guint32 native_offset = ip - (guint8*)ji->code_start;
8422                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8423
8424                 g_assert (info->bp_addrs [native_offset] == 0);
8425                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8426         } else {
8427                 /*
8428                  * In production, we will use int3 (has to fix the size in the md
8429                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8430                  * instead.
8431                  */
8432                 g_assert (code [0] == 0x90);
8433                 if (breakpoint_size == 8) {
8434                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8435                 } else {
8436                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8437                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8438                 }
8439
8440                 g_assert (code - orig_code == breakpoint_size);
8441         }
8442 }
8443
8444 /*
8445  * mono_arch_clear_breakpoint:
8446  *
8447  *   Clear the breakpoint at IP.
8448  */
8449 void
8450 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8451 {
8452         guint8 *code = ip;
8453         int i;
8454
8455         if (ji->from_aot) {
8456                 guint32 native_offset = ip - (guint8*)ji->code_start;
8457                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8458
8459                 info->bp_addrs [native_offset] = NULL;
8460         } else {
8461                 for (i = 0; i < breakpoint_size; ++i)
8462                         x86_nop (code);
8463         }
8464 }
8465
8466 gboolean
8467 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8468 {
8469 #ifdef HOST_WIN32
8470         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8471         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8472                 return TRUE;
8473         else
8474                 return FALSE;
8475 #else
8476         siginfo_t* sinfo = (siginfo_t*) info;
8477         /* Sometimes the address is off by 4 */
8478         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8479                 return TRUE;
8480         else
8481                 return FALSE;
8482 #endif
8483 }
8484
8485 /*
8486  * mono_arch_skip_breakpoint:
8487  *
8488  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8489  * we resume, the instruction is not executed again.
8490  */
8491 void
8492 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8493 {
8494         if (ji->from_aot) {
8495                 /* The breakpoint instruction is a call */
8496         } else {
8497                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8498         }
8499 }
8500
8501 /*
8502  * mono_arch_start_single_stepping:
8503  *
8504  *   Start single stepping.
8505  */
8506 void
8507 mono_arch_start_single_stepping (void)
8508 {
8509         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8510         ss_trampoline = mini_get_single_step_trampoline ();
8511 }
8512
8513 /*
8514  * mono_arch_stop_single_stepping:
8515  *
8516  *   Stop single stepping.
8517  */
8518 void
8519 mono_arch_stop_single_stepping (void)
8520 {
8521         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8522         ss_trampoline = NULL;
8523 }
8524
8525 /*
8526  * mono_arch_is_single_step_event:
8527  *
8528  *   Return whenever the machine state in SIGCTX corresponds to a single
8529  * step event.
8530  */
8531 gboolean
8532 mono_arch_is_single_step_event (void *info, void *sigctx)
8533 {
8534 #ifdef HOST_WIN32
8535         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8536         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8537                 return TRUE;
8538         else
8539                 return FALSE;
8540 #else
8541         siginfo_t* sinfo = (siginfo_t*) info;
8542         /* Sometimes the address is off by 4 */
8543         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8544                 return TRUE;
8545         else
8546                 return FALSE;
8547 #endif
8548 }
8549
8550 /*
8551  * mono_arch_skip_single_step:
8552  *
8553  *   Modify CTX so the ip is placed after the single step trigger instruction,
8554  * we resume, the instruction is not executed again.
8555  */
8556 void
8557 mono_arch_skip_single_step (MonoContext *ctx)
8558 {
8559         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8560 }
8561
8562 /*
8563  * mono_arch_create_seq_point_info:
8564  *
8565  *   Return a pointer to a data structure which is used by the sequence
8566  * point implementation in AOTed code.
8567  */
8568 gpointer
8569 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8570 {
8571         SeqPointInfo *info;
8572         MonoJitInfo *ji;
8573
8574         // FIXME: Add a free function
8575
8576         mono_domain_lock (domain);
8577         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8578                                                                 code);
8579         mono_domain_unlock (domain);
8580
8581         if (!info) {
8582                 ji = mono_jit_info_table_find (domain, (char*)code);
8583                 g_assert (ji);
8584
8585                 // FIXME: Optimize the size
8586                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8587
8588                 info->ss_tramp_addr = &ss_trampoline;
8589
8590                 mono_domain_lock (domain);
8591                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8592                                                          code, info);
8593                 mono_domain_unlock (domain);
8594         }
8595
8596         return info;
8597 }
8598
8599 void
8600 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8601 {
8602         ext->lmf.previous_lmf = prev_lmf;
8603         /* Mark that this is a MonoLMFExt */
8604         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8605         ext->lmf.rsp = (gssize)ext;
8606 }
8607
8608 #endif
8609
8610 gboolean
8611 mono_arch_opcode_supported (int opcode)
8612 {
8613         switch (opcode) {
8614         case OP_ATOMIC_ADD_I4:
8615         case OP_ATOMIC_ADD_I8:
8616         case OP_ATOMIC_EXCHANGE_I4:
8617         case OP_ATOMIC_EXCHANGE_I8:
8618         case OP_ATOMIC_CAS_I4:
8619         case OP_ATOMIC_CAS_I8:
8620         case OP_ATOMIC_LOAD_I1:
8621         case OP_ATOMIC_LOAD_I2:
8622         case OP_ATOMIC_LOAD_I4:
8623         case OP_ATOMIC_LOAD_I8:
8624         case OP_ATOMIC_LOAD_U1:
8625         case OP_ATOMIC_LOAD_U2:
8626         case OP_ATOMIC_LOAD_U4:
8627         case OP_ATOMIC_LOAD_U8:
8628         case OP_ATOMIC_LOAD_R4:
8629         case OP_ATOMIC_LOAD_R8:
8630         case OP_ATOMIC_STORE_I1:
8631         case OP_ATOMIC_STORE_I2:
8632         case OP_ATOMIC_STORE_I4:
8633         case OP_ATOMIC_STORE_I8:
8634         case OP_ATOMIC_STORE_U1:
8635         case OP_ATOMIC_STORE_U2:
8636         case OP_ATOMIC_STORE_U4:
8637         case OP_ATOMIC_STORE_U8:
8638         case OP_ATOMIC_STORE_R4:
8639         case OP_ATOMIC_STORE_R8:
8640                 return TRUE;
8641         default:
8642                 return FALSE;
8643         }
8644 }