mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "mini-amd64.h"
  30 #include "inssel.h"
  31 #include "cpu-amd64.h"
  32
  33 static gint lmf_tls_offset = -1;
  34 static gint lmf_addr_tls_offset = -1;
  35 static gint appdomain_tls_offset = -1;
  36 static gint thread_tls_offset = -1;
  37
  38 #ifdef MONO_XEN_OPT
  39 static gboolean optimize_for_xen = TRUE;
  40 #else
  41 #define optimize_for_xen 0
  42 #endif
  43
  44 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  45
  46 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  47
  48 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  49
  50 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  51
  52 #ifdef PLATFORM_WIN32
  53 /* Under windows, the default pinvoke calling convention is stdcall */
  54 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  55 #else
  56 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  57 #endif
  58
  59 /* This mutex protects architecture specific caches */
  60 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  61 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  62 static CRITICAL_SECTION mini_arch_mutex;
  63
  64 MonoBreakpointInfo
  65 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  66
  67 #define ARGS_OFFSET 16
  68 #define GP_SCRATCH_REG AMD64_R11
  69
  70 /*
  71  * AMD64 register usage:
  72  * - callee saved registers are used for global register allocation
  73  * - %r11 is used for materializing 64 bit constants in opcodes
  74  * - the rest is used for local allocation
  75  */
  76
  77 /*
  78  * Floating point comparison results:
  79  *                  ZF PF CF
  80  * A > B            0  0  0
  81  * A < B            0  0  1
  82  * A = B            1  0  0
  83  * A > B            0  0  0
  84  * UNORDERED        1  1  1
  85  */
  86
  87 const char*
  88 mono_arch_regname (int reg)
  89 {
  90         switch (reg) {
  91         case AMD64_RAX: return "%rax";
  92         case AMD64_RBX: return "%rbx";
  93         case AMD64_RCX: return "%rcx";
  94         case AMD64_RDX: return "%rdx";
  95         case AMD64_RSP: return "%rsp";
  96         case AMD64_RBP: return "%rbp";
  97         case AMD64_RDI: return "%rdi";
  98         case AMD64_RSI: return "%rsi";
  99         case AMD64_R8: return "%r8";
 100         case AMD64_R9: return "%r9";
 101         case AMD64_R10: return "%r10";
 102         case AMD64_R11: return "%r11";
 103         case AMD64_R12: return "%r12";
 104         case AMD64_R13: return "%r13";
 105         case AMD64_R14: return "%r14";
 106         case AMD64_R15: return "%r15";
 107         }
 108         return "unknown";
 109 }
 110
 111 static const char * xmmregs [] = {
 112         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 113         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 114 };
 115
 116 const char*
 117 mono_arch_fregname (int reg)
 118 {
 119         if (reg < AMD64_XMM_NREG)
 120                 return xmmregs [reg];
 121         else
 122                 return "unknown";
 123 }
 124
 125 G_GNUC_UNUSED static void
 126 break_count (void)
 127 {
 128 }
 129
 130 G_GNUC_UNUSED static gboolean
 131 debug_count (void)
 132 {
 133         static int count = 0;
 134         count ++;
 135
 136         if (!getenv ("COUNT"))
 137                 return TRUE;
 138
 139         if (count == atoi (getenv ("COUNT"))) {
 140                 break_count ();
 141         }
 142
 143         if (count > atoi (getenv ("COUNT"))) {
 144                 return FALSE;
 145         }
 146
 147         return TRUE;
 148 }
 149
 150 static gboolean
 151 debug_omit_fp (void)
 152 {
 153 #if 0
 154         return debug_count ();
 155 #else
 156         return TRUE;
 157 #endif
 158 }
 159
 160 static inline gboolean
 161 amd64_is_near_call (guint8 *code)
 162 {
 163         /* Skip REX */
 164         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 165                 code += 1;
 166
 167         return code [0] == 0xe8;
 168 }
 169
 170 static inline void
 171 amd64_patch (unsigned char* code, gpointer target)
 172 {
 173         /* Skip REX */
 174         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 175                 code += 1;
 176
 177         if ((code [0] & 0xf8) == 0xb8) {
 178                 /* amd64_set_reg_template */
 179                 *(guint64*)(code + 1) = (guint64)target;
 180         }
 181         else if (code [0] == 0x8b) {
 182                 /* mov 0(%rip), %dreg */
 183                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 184         }
 185         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 186                 /* call *<OFFSET>(%rip) */
 187                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 188         }
 189         else if ((code [0] == 0xe8)) {
 190                 /* call <DISP> */
 191                 gint64 disp = (guint8*)target - (guint8*)code;
 192                 g_assert (amd64_is_imm32 (disp));
 193                 x86_patch (code, (unsigned char*)target);
 194         }
 195         else
 196                 x86_patch (code, (unsigned char*)target);
 197 }
 198
 199 void
 200 mono_amd64_patch (unsigned char* code, gpointer target)
 201 {
 202         amd64_patch (code, target);
 203 }
 204
 205 typedef enum {
 206         ArgInIReg,
 207         ArgInFloatSSEReg,
 208         ArgInDoubleSSEReg,
 209         ArgOnStack,
 210         ArgValuetypeInReg,
 211         ArgNone /* only in pair_storage */
 212 } ArgStorage;
 213
 214 typedef struct {
 215         gint16 offset;
 216         gint8  reg;
 217         ArgStorage storage;
 218
 219         /* Only if storage == ArgValuetypeInReg */
 220         ArgStorage pair_storage [2];
 221         gint8 pair_regs [2];
 222 } ArgInfo;
 223
 224 typedef struct {
 225         int nargs;
 226         guint32 stack_usage;
 227         guint32 reg_usage;
 228         guint32 freg_usage;
 229         gboolean need_stack_align;
 230         ArgInfo ret;
 231         ArgInfo sig_cookie;
 232         ArgInfo args [1];
 233 } CallInfo;
 234
 235 #define DEBUG(a) if (cfg->verbose_level > 1) a
 236
 237 #define NEW_ICONST(cfg,dest,val) do {   \
 238                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 239                 (dest)->opcode = OP_ICONST;     \
 240                 (dest)->inst_c0 = (val);        \
 241                 (dest)->type = STACK_I4;        \
 242         } while (0)
 243
 244 #ifdef PLATFORM_WIN32
 245 #define PARAM_REGS 4
 246
 247 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 248
 249 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 250 #else
 251 #define PARAM_REGS 6
 252
 253 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 254
 255  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 256 #endif
 257
 258 static void inline
 259 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 260 {
 261     ainfo->offset = *stack_size;
 262
 263     if (*gr >= PARAM_REGS) {
 264                 ainfo->storage = ArgOnStack;
 265                 (*stack_size) += sizeof (gpointer);
 266     }
 267     else {
 268                 ainfo->storage = ArgInIReg;
 269                 ainfo->reg = param_regs [*gr];
 270                 (*gr) ++;
 271     }
 272 }
 273
 274 #ifdef PLATFORM_WIN32
 275 #define FLOAT_PARAM_REGS 4
 276 #else
 277 #define FLOAT_PARAM_REGS 8
 278 #endif
 279
 280 static void inline
 281 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 282 {
 283     ainfo->offset = *stack_size;
 284
 285     if (*gr >= FLOAT_PARAM_REGS) {
 286                 ainfo->storage = ArgOnStack;
 287                 (*stack_size) += sizeof (gpointer);
 288     }
 289     else {
 290                 /* A double register */
 291                 if (is_double)
 292                         ainfo->storage = ArgInDoubleSSEReg;
 293                 else
 294                         ainfo->storage = ArgInFloatSSEReg;
 295                 ainfo->reg = *gr;
 296                 (*gr) += 1;
 297     }
 298 }
 299
 300 typedef enum ArgumentClass {
 301         ARG_CLASS_NO_CLASS,
 302         ARG_CLASS_MEMORY,
 303         ARG_CLASS_INTEGER,
 304         ARG_CLASS_SSE
 305 } ArgumentClass;
 306
 307 static ArgumentClass
 308 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 309 {
 310         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 311         MonoType *ptype;
 312
 313         ptype = mono_type_get_underlying_type (type);
 314         switch (ptype->type) {
 315         case MONO_TYPE_BOOLEAN:
 316         case MONO_TYPE_CHAR:
 317         case MONO_TYPE_I1:
 318         case MONO_TYPE_U1:
 319         case MONO_TYPE_I2:
 320         case MONO_TYPE_U2:
 321         case MONO_TYPE_I4:
 322         case MONO_TYPE_U4:
 323         case MONO_TYPE_I:
 324         case MONO_TYPE_U:
 325         case MONO_TYPE_STRING:
 326         case MONO_TYPE_OBJECT:
 327         case MONO_TYPE_CLASS:
 328         case MONO_TYPE_SZARRAY:
 329         case MONO_TYPE_PTR:
 330         case MONO_TYPE_FNPTR:
 331         case MONO_TYPE_ARRAY:
 332         case MONO_TYPE_I8:
 333         case MONO_TYPE_U8:
 334                 class2 = ARG_CLASS_INTEGER;
 335                 break;
 336         case MONO_TYPE_R4:
 337         case MONO_TYPE_R8:
 338                 class2 = ARG_CLASS_SSE;
 339                 break;
 340
 341         case MONO_TYPE_TYPEDBYREF:
 342                 g_assert_not_reached ();
 343
 344         case MONO_TYPE_GENERICINST:
 345                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 346                         class2 = ARG_CLASS_INTEGER;
 347                         break;
 348                 }
 349                 /* fall through */
 350         case MONO_TYPE_VALUETYPE: {
 351                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 352                 int i;
 353
 354                 for (i = 0; i < info->num_fields; ++i) {
 355                         class2 = class1;
 356                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 357                 }
 358                 break;
 359         }
 360         default:
 361                 g_assert_not_reached ();
 362         }
 363
 364         /* Merge */
 365         if (class1 == class2)
 366                 ;
 367         else if (class1 == ARG_CLASS_NO_CLASS)
 368                 class1 = class2;
 369         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 370                 class1 = ARG_CLASS_MEMORY;
 371         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 372                 class1 = ARG_CLASS_INTEGER;
 373         else
 374                 class1 = ARG_CLASS_SSE;
 375
 376         return class1;
 377 }
 378
 379 static void
 380 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 381                gboolean is_return,
 382                guint32 *gr, guint32 *fr, guint32 *stack_size)
 383 {
 384         guint32 size, quad, nquads, i;
 385         ArgumentClass args [2];
 386         MonoMarshalType *info;
 387         MonoClass *klass;
 388
 389         klass = mono_class_from_mono_type (type);
 390         if (sig->pinvoke)
 391                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 392         else
 393                 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
 394
 395         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 396                 /* Allways pass in memory */
 397                 ainfo->offset = *stack_size;
 398                 *stack_size += ALIGN_TO (size, 8);
 399                 ainfo->storage = ArgOnStack;
 400
 401                 return;
 402         }
 403
 404         /* FIXME: Handle structs smaller than 8 bytes */
 405         //if ((size % 8) != 0)
 406         //      NOT_IMPLEMENTED;
 407
 408         if (size > 8)
 409                 nquads = 2;
 410         else
 411                 nquads = 1;
 412
 413         /*
 414          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 415          * The X87 and SSEUP stuff is left out since there are no such types in
 416          * the CLR.
 417          */
 418         info = mono_marshal_load_type_info (klass);
 419         g_assert (info);
 420         if (info->native_size > 16) {
 421                 ainfo->offset = *stack_size;
 422                 *stack_size += ALIGN_TO (info->native_size, 8);
 423                 ainfo->storage = ArgOnStack;
 424
 425                 return;
 426         }
 427
 428         args [0] = ARG_CLASS_NO_CLASS;
 429         args [1] = ARG_CLASS_NO_CLASS;
 430         for (quad = 0; quad < nquads; ++quad) {
 431                 int size;
 432                 guint32 align;
 433                 ArgumentClass class1;
 434
 435                 class1 = ARG_CLASS_NO_CLASS;
 436                 for (i = 0; i < info->num_fields; ++i) {
 437                         size = mono_marshal_type_size (info->fields [i].field->type,
 438                                                                                    info->fields [i].mspec,
 439                                                                                    &align, TRUE, klass->unicode);
 440                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 441                                 /* Unaligned field */
 442                                 NOT_IMPLEMENTED;
 443                         }
 444
 445                         /* Skip fields in other quad */
 446                         if ((quad == 0) && (info->fields [i].offset >= 8))
 447                                 continue;
 448                         if ((quad == 1) && (info->fields [i].offset < 8))
 449                                 continue;
 450
 451                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 452                 }
 453                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 454                 args [quad] = class1;
 455         }
 456
 457         /* Post merger cleanup */
 458         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 459                 args [0] = args [1] = ARG_CLASS_MEMORY;
 460
 461         /* Allocate registers */
 462         {
 463                 int orig_gr = *gr;
 464                 int orig_fr = *fr;
 465
 466                 ainfo->storage = ArgValuetypeInReg;
 467                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 468                 for (quad = 0; quad < nquads; ++quad) {
 469                         switch (args [quad]) {
 470                         case ARG_CLASS_INTEGER:
 471                                 if (*gr >= PARAM_REGS)
 472                                         args [quad] = ARG_CLASS_MEMORY;
 473                                 else {
 474                                         ainfo->pair_storage [quad] = ArgInIReg;
 475                                         if (is_return)
 476                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 477                                         else
 478                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 479                                         (*gr) ++;
 480                                 }
 481                                 break;
 482                         case ARG_CLASS_SSE:
 483                                 if (*fr >= FLOAT_PARAM_REGS)
 484                                         args [quad] = ARG_CLASS_MEMORY;
 485                                 else {
 486                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 487                                         ainfo->pair_regs [quad] = *fr;
 488                                         (*fr) ++;
 489                                 }
 490                                 break;
 491                         case ARG_CLASS_MEMORY:
 492                                 break;
 493                         default:
 494                                 g_assert_not_reached ();
 495                         }
 496                 }
 497
 498                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 499                         /* Revert possible register assignments */
 500                         *gr = orig_gr;
 501                         *fr = orig_fr;
 502
 503                         ainfo->offset = *stack_size;
 504                         *stack_size += ALIGN_TO (info->native_size, 8);
 505                         ainfo->storage = ArgOnStack;
 506                 }
 507         }
 508 }
 509
 510 /*
 511  * get_call_info:
 512  *
 513  *  Obtain information about a call according to the calling convention.
 514  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 515  * Draft Version 0.23" document for more information.
 516  */
 517 static CallInfo*
 518 get_call_info (MonoCompile *cfg, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 519 {
 520         guint32 i, gr, fr;
 521         MonoType *ret_type;
 522         int n = sig->hasthis + sig->param_count;
 523         guint32 stack_size = 0;
 524         CallInfo *cinfo;
 525         MonoGenericSharingContext *gsctx = cfg ? cfg->generic_sharing_context : NULL;
 526
 527         if (mp)
 528                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 529         else
 530                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 531
 532         gr = 0;
 533         fr = 0;
 534
 535         /* return value */
 536         {
 537                 ret_type = mono_type_get_underlying_type (sig->ret);
 538                 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
 539                 switch (ret_type->type) {
 540                 case MONO_TYPE_BOOLEAN:
 541                 case MONO_TYPE_I1:
 542                 case MONO_TYPE_U1:
 543                 case MONO_TYPE_I2:
 544                 case MONO_TYPE_U2:
 545                 case MONO_TYPE_CHAR:
 546                 case MONO_TYPE_I4:
 547                 case MONO_TYPE_U4:
 548                 case MONO_TYPE_I:
 549                 case MONO_TYPE_U:
 550                 case MONO_TYPE_PTR:
 551                 case MONO_TYPE_FNPTR:
 552                 case MONO_TYPE_CLASS:
 553                 case MONO_TYPE_OBJECT:
 554                 case MONO_TYPE_SZARRAY:
 555                 case MONO_TYPE_ARRAY:
 556                 case MONO_TYPE_STRING:
 557                         cinfo->ret.storage = ArgInIReg;
 558                         cinfo->ret.reg = AMD64_RAX;
 559                         break;
 560                 case MONO_TYPE_U8:
 561                 case MONO_TYPE_I8:
 562                         cinfo->ret.storage = ArgInIReg;
 563                         cinfo->ret.reg = AMD64_RAX;
 564                         break;
 565                 case MONO_TYPE_R4:
 566                         cinfo->ret.storage = ArgInFloatSSEReg;
 567                         cinfo->ret.reg = AMD64_XMM0;
 568                         break;
 569                 case MONO_TYPE_R8:
 570                         cinfo->ret.storage = ArgInDoubleSSEReg;
 571                         cinfo->ret.reg = AMD64_XMM0;
 572                         break;
 573                 case MONO_TYPE_GENERICINST:
 574                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 575                                 cinfo->ret.storage = ArgInIReg;
 576                                 cinfo->ret.reg = AMD64_RAX;
 577                                 break;
 578                         }
 579                         /* fall through */
 580                 case MONO_TYPE_VALUETYPE: {
 581                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 582
 583                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 584                         if (cinfo->ret.storage == ArgOnStack)
 585                                 /* The caller passes the address where the value is stored */
 586                                 add_general (&gr, &stack_size, &cinfo->ret);
 587                         break;
 588                 }
 589                 case MONO_TYPE_TYPEDBYREF:
 590                         /* Same as a valuetype with size 24 */
 591                         add_general (&gr, &stack_size, &cinfo->ret);
 592                         ;
 593                         break;
 594                 case MONO_TYPE_VOID:
 595                         break;
 596                 default:
 597                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 598                 }
 599         }
 600
 601         /* this */
 602         if (sig->hasthis)
 603                 add_general (&gr, &stack_size, cinfo->args + 0);
 604
 605         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 606                 gr = PARAM_REGS;
 607                 fr = FLOAT_PARAM_REGS;
 608
 609                 /* Emit the signature cookie just before the implicit arguments */
 610                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 611         }
 612
 613         for (i = 0; i < sig->param_count; ++i) {
 614                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 615                 MonoType *ptype;
 616
 617                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 618                         /* We allways pass the sig cookie on the stack for simplicity */
 619                         /*
 620                          * Prevent implicit arguments + the sig cookie from being passed
 621                          * in registers.
 622                          */
 623                         gr = PARAM_REGS;
 624                         fr = FLOAT_PARAM_REGS;
 625
 626                         /* Emit the signature cookie just before the implicit arguments */
 627                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 628                 }
 629
 630                 if (sig->params [i]->byref) {
 631                         add_general (&gr, &stack_size, ainfo);
 632                         continue;
 633                 }
 634                 ptype = mono_type_get_underlying_type (sig->params [i]);
 635                 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
 636                 switch (ptype->type) {
 637                 case MONO_TYPE_BOOLEAN:
 638                 case MONO_TYPE_I1:
 639                 case MONO_TYPE_U1:
 640                         add_general (&gr, &stack_size, ainfo);
 641                         break;
 642                 case MONO_TYPE_I2:
 643                 case MONO_TYPE_U2:
 644                 case MONO_TYPE_CHAR:
 645                         add_general (&gr, &stack_size, ainfo);
 646                         break;
 647                 case MONO_TYPE_I4:
 648                 case MONO_TYPE_U4:
 649                         add_general (&gr, &stack_size, ainfo);
 650                         break;
 651                 case MONO_TYPE_I:
 652                 case MONO_TYPE_U:
 653                 case MONO_TYPE_PTR:
 654                 case MONO_TYPE_FNPTR:
 655                 case MONO_TYPE_CLASS:
 656                 case MONO_TYPE_OBJECT:
 657                 case MONO_TYPE_STRING:
 658                 case MONO_TYPE_SZARRAY:
 659                 case MONO_TYPE_ARRAY:
 660                         add_general (&gr, &stack_size, ainfo);
 661                         break;
 662                 case MONO_TYPE_GENERICINST:
 663                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 664                                 add_general (&gr, &stack_size, ainfo);
 665                                 break;
 666                         }
 667                         /* fall through */
 668                 case MONO_TYPE_VALUETYPE:
 669                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 670                         break;
 671                 case MONO_TYPE_TYPEDBYREF:
 672                         stack_size += sizeof (MonoTypedRef);
 673                         ainfo->storage = ArgOnStack;
 674                         break;
 675                 case MONO_TYPE_U8:
 676                 case MONO_TYPE_I8:
 677                         add_general (&gr, &stack_size, ainfo);
 678                         break;
 679                 case MONO_TYPE_R4:
 680                         add_float (&fr, &stack_size, ainfo, FALSE);
 681                         break;
 682                 case MONO_TYPE_R8:
 683                         add_float (&fr, &stack_size, ainfo, TRUE);
 684                         break;
 685                 default:
 686                         g_assert_not_reached ();
 687                 }
 688         }
 689
 690         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 691                 gr = PARAM_REGS;
 692                 fr = FLOAT_PARAM_REGS;
 693
 694                 /* Emit the signature cookie just before the implicit arguments */
 695                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 696         }
 697
 698 #ifdef PLATFORM_WIN32
 699         if (stack_size < 32) {
 700                 /* The Win64 ABI requires 32 bits  */
 701                 stack_size = 32;
 702         }
 703 #endif
 704
 705         if (stack_size & 0x8) {
 706                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 707                 cinfo->need_stack_align = TRUE;
 708                 stack_size += 8;
 709         }
 710
 711         cinfo->stack_usage = stack_size;
 712         cinfo->reg_usage = gr;
 713         cinfo->freg_usage = fr;
 714         return cinfo;
 715 }
 716
 717 /*
 718  * mono_arch_get_argument_info:
 719  * @csig:  a method signature
 720  * @param_count: the number of parameters to consider
 721  * @arg_info: an array to store the result infos
 722  *
 723  * Gathers information on parameters such as size, alignment and
 724  * padding. arg_info should be large enought to hold param_count + 1 entries.
 725  *
 726  * Returns the size of the argument area on the stack.
 727  */
 728 int
 729 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 730 {
 731         int k;
 732         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 733         guint32 args_size = cinfo->stack_usage;
 734
 735         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 736         if (csig->hasthis) {
 737                 arg_info [0].offset = 0;
 738         }
 739
 740         for (k = 0; k < param_count; k++) {
 741                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 742                 /* FIXME: */
 743                 arg_info [k + 1].size = 0;
 744         }
 745
 746         g_free (cinfo);
 747
 748         return args_size;
 749 }
 750
 751 static int
 752 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 753 {
 754         __asm__ __volatile__ ("cpuid"
 755                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 756                 : "a" (id));
 757         return 1;
 758 }
 759
 760 /*
 761  * Initialize the cpu to execute managed code.
 762  */
 763 void
 764 mono_arch_cpu_init (void)
 765 {
 766 #ifndef _MSC_VER
 767         guint16 fpcw;
 768
 769         /* spec compliance requires running with double precision */
 770         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 771         fpcw &= ~X86_FPCW_PRECC_MASK;
 772         fpcw |= X86_FPCW_PREC_DOUBLE;
 773         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 774         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 775 #else
 776         _control87 (_PC_53, MCW_PC);
 777 #endif
 778 }
 779
 780 /*
 781  * Initialize architecture specific code.
 782  */
 783 void
 784 mono_arch_init (void)
 785 {
 786         InitializeCriticalSection (&mini_arch_mutex);
 787 }
 788
 789 /*
 790  * Cleanup architecture specific code.
 791  */
 792 void
 793 mono_arch_cleanup (void)
 794 {
 795         DeleteCriticalSection (&mini_arch_mutex);
 796 }
 797
 798 /*
 799  * This function returns the optimizations supported on this cpu.
 800  */
 801 guint32
 802 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 803 {
 804         int eax, ebx, ecx, edx;
 805         guint32 opts = 0;
 806
 807         /* FIXME: AMD64 */
 808
 809         *exclude_mask = 0;
 810         /* Feature Flags function, flags returned in EDX. */
 811         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 812                 if (edx & (1 << 15)) {
 813                         opts |= MONO_OPT_CMOV;
 814                         if (edx & 1)
 815                                 opts |= MONO_OPT_FCMOV;
 816                         else
 817                                 *exclude_mask |= MONO_OPT_FCMOV;
 818                 } else
 819                         *exclude_mask |= MONO_OPT_CMOV;
 820         }
 821         return opts;
 822 }
 823
 824 gboolean
 825 mono_amd64_is_sse2 (void)
 826 {
 827         return use_sse2;
 828 }
 829
 830 GList *
 831 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 832 {
 833         GList *vars = NULL;
 834         int i;
 835
 836         for (i = 0; i < cfg->num_varinfo; i++) {
 837                 MonoInst *ins = cfg->varinfo [i];
 838                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 839
 840                 /* unused vars */
 841                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 842                         continue;
 843
 844                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 845                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 846                         continue;
 847
 848                 if (mono_is_regsize_var (ins->inst_vtype)) {
 849                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 850                         g_assert (i == vmv->idx);
 851                         vars = g_list_prepend (vars, vmv);
 852                 }
 853         }
 854
 855         vars = mono_varlist_sort (cfg, vars, 0);
 856
 857         return vars;
 858 }
 859
 860 /**
 861  * mono_arch_compute_omit_fp:
 862  *
 863  *   Determine whenever the frame pointer can be eliminated.
 864  */
 865 static void
 866 mono_arch_compute_omit_fp (MonoCompile *cfg)
 867 {
 868         MonoMethodSignature *sig;
 869         MonoMethodHeader *header;
 870         int i, locals_size;
 871         CallInfo *cinfo;
 872
 873         if (cfg->arch.omit_fp_computed)
 874                 return;
 875
 876         header = mono_method_get_header (cfg->method);
 877
 878         sig = mono_method_signature (cfg->method);
 879
 880         if (!cfg->arch.cinfo)
 881                 cfg->arch.cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
 882         cinfo = cfg->arch.cinfo;
 883
 884         /*
 885          * FIXME: Remove some of the restrictions.
 886          */
 887         cfg->arch.omit_fp = TRUE;
 888         cfg->arch.omit_fp_computed = TRUE;
 889
 890         /* Temporarily disable this when running in the debugger until we have support
 891          * for this in the debugger. */
 892         if (mono_debug_using_mono_debugger ())
 893                 cfg->arch.omit_fp = FALSE;
 894
 895         if (!debug_omit_fp ())
 896                 cfg->arch.omit_fp = FALSE;
 897         /*
 898         if (cfg->method->save_lmf)
 899                 cfg->arch.omit_fp = FALSE;
 900         */
 901         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 902                 cfg->arch.omit_fp = FALSE;
 903         if (header->num_clauses)
 904                 cfg->arch.omit_fp = FALSE;
 905         if (cfg->param_area)
 906                 cfg->arch.omit_fp = FALSE;
 907         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 908                 cfg->arch.omit_fp = FALSE;
 909         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 910                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 911                 cfg->arch.omit_fp = FALSE;
 912         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 913                 ArgInfo *ainfo = &cinfo->args [i];
 914
 915                 if (ainfo->storage == ArgOnStack) {
 916                         /*
 917                          * The stack offset can only be determined when the frame
 918                          * size is known.
 919                          */
 920                         cfg->arch.omit_fp = FALSE;
 921                 }
 922         }
 923
 924         if (cinfo->ret.storage == ArgValuetypeInReg)
 925                 cfg->arch.omit_fp = FALSE;
 926
 927         locals_size = 0;
 928         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
 929                 MonoInst *ins = cfg->varinfo [i];
 930                 int ialign;
 931
 932                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
 933         }
 934
 935         if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
 936                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 937                 cfg->arch.omit_fp = FALSE;
 938         }
 939 }
 940
 941 GList *
 942 mono_arch_get_global_int_regs (MonoCompile *cfg)
 943 {
 944         GList *regs = NULL;
 945
 946         mono_arch_compute_omit_fp (cfg);
 947
 948         if (cfg->arch.omit_fp)
 949                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 950
 951         /* We use the callee saved registers for global allocation */
 952         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 953         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 954         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 955         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 956         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 957
 958         return regs;
 959 }
 960
 961 /*
 962  * mono_arch_regalloc_cost:
 963  *
 964  *  Return the cost, in number of memory references, of the action of
 965  * allocating the variable VMV into a register during global register
 966  * allocation.
 967  */
 968 guint32
 969 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 970 {
 971         MonoInst *ins = cfg->varinfo [vmv->idx];
 972
 973         if (cfg->method->save_lmf)
 974                 /* The register is already saved */
 975                 /* substract 1 for the invisible store in the prolog */
 976                 return (ins->opcode == OP_ARG) ? 0 : 1;
 977         else
 978                 /* push+pop */
 979                 return (ins->opcode == OP_ARG) ? 1 : 2;
 980 }
 981
 982 void
 983 mono_arch_allocate_vars (MonoCompile *cfg)
 984 {
 985         MonoMethodSignature *sig;
 986         MonoMethodHeader *header;
 987         MonoInst *inst;
 988         int i, offset;
 989         guint32 locals_stack_size, locals_stack_align;
 990         gint32 *offsets;
 991         CallInfo *cinfo;
 992
 993         header = mono_method_get_header (cfg->method);
 994
 995         sig = mono_method_signature (cfg->method);
 996
 997         cinfo = cfg->arch.cinfo;
 998
 999         mono_arch_compute_omit_fp (cfg);
1000
1001         /*
1002          * We use the ABI calling conventions for managed code as well.
1003          * Exception: valuetypes are never passed or returned in registers.
1004          */
1005
1006         if (cfg->arch.omit_fp) {
1007                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1008                 cfg->frame_reg = AMD64_RSP;
1009                 offset = 0;
1010         } else {
1011                 /* Locals are allocated backwards from %fp */
1012                 cfg->frame_reg = AMD64_RBP;
1013                 offset = 0;
1014         }
1015
1016         if (cfg->method->save_lmf) {
1017                 /* Reserve stack space for saving LMF */
1018                 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1019                 g_assert (offset == 0);
1020                 if (cfg->arch.omit_fp) {
1021                         cfg->arch.lmf_offset = offset;
1022                         offset += sizeof (MonoLMF);
1023                 }
1024                 else {
1025                         offset += sizeof (MonoLMF);
1026                         cfg->arch.lmf_offset = -offset;
1027                 }
1028         } else {
1029                 /* Reserve space for caller saved registers */
1030                 for (i = 0; i < AMD64_NREG; ++i)
1031                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1032                                 offset += sizeof (gpointer);
1033                         }
1034         }
1035
1036         if (sig->ret->type != MONO_TYPE_VOID) {
1037                 switch (cinfo->ret.storage) {
1038                 case ArgInIReg:
1039                 case ArgInFloatSSEReg:
1040                 case ArgInDoubleSSEReg:
1041                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1042                                 /* The register is volatile */
1043                                 cfg->vret_addr->opcode = OP_REGOFFSET;
1044                                 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1045                                 if (cfg->arch.omit_fp) {
1046                                         cfg->vret_addr->inst_offset = offset;
1047                                         offset += 8;
1048                                 } else {
1049                                         offset += 8;
1050                                         cfg->vret_addr->inst_offset = -offset;
1051                                 }
1052                                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1053                                         printf ("vret_addr =");
1054                                         mono_print_ins (cfg->vret_addr);
1055                                 }
1056                         }
1057                         else {
1058                                 cfg->ret->opcode = OP_REGVAR;
1059                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1060                         }
1061                         break;
1062                 case ArgValuetypeInReg:
1063                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1064                         g_assert (!cfg->arch.omit_fp);
1065                         offset += 16;
1066                         cfg->ret->opcode = OP_REGOFFSET;
1067                         cfg->ret->inst_basereg = cfg->frame_reg;
1068                         cfg->ret->inst_offset = - offset;
1069                         break;
1070                 default:
1071                         g_assert_not_reached ();
1072                 }
1073                 cfg->ret->dreg = cfg->ret->inst_c0;
1074         }
1075
1076         /* Allocate locals */
1077         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1078         if (locals_stack_align) {
1079                 offset += (locals_stack_align - 1);
1080                 offset &= ~(locals_stack_align - 1);
1081         }
1082         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1083                 if (offsets [i] != -1) {
1084                         MonoInst *inst = cfg->varinfo [i];
1085                         inst->opcode = OP_REGOFFSET;
1086                         inst->inst_basereg = cfg->frame_reg;
1087                         if (cfg->arch.omit_fp)
1088                                 inst->inst_offset = (offset + offsets [i]);
1089                         else
1090                                 inst->inst_offset = - (offset + offsets [i]);
1091                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1092                 }
1093         }
1094         offset += locals_stack_size;
1095
1096         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1097                 g_assert (!cfg->arch.omit_fp);
1098                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1099                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1100         }
1101
1102         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1103                 inst = cfg->args [i];
1104                 if (inst->opcode != OP_REGVAR) {
1105                         ArgInfo *ainfo = &cinfo->args [i];
1106                         gboolean inreg = TRUE;
1107                         MonoType *arg_type;
1108
1109                         if (sig->hasthis && (i == 0))
1110                                 arg_type = &mono_defaults.object_class->byval_arg;
1111                         else
1112                                 arg_type = sig->params [i - sig->hasthis];
1113
1114                         /* FIXME: Allocate volatile arguments to registers */
1115                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1116                                 inreg = FALSE;
1117
1118                         /*
1119                          * Under AMD64, all registers used to pass arguments to functions
1120                          * are volatile across calls.
1121                          * FIXME: Optimize this.
1122                          */
1123                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1124                                 inreg = FALSE;
1125
1126                         inst->opcode = OP_REGOFFSET;
1127
1128                         switch (ainfo->storage) {
1129                         case ArgInIReg:
1130                         case ArgInFloatSSEReg:
1131                         case ArgInDoubleSSEReg:
1132                                 inst->opcode = OP_REGVAR;
1133                                 inst->dreg = ainfo->reg;
1134                                 break;
1135                         case ArgOnStack:
1136                                 g_assert (!cfg->arch.omit_fp);
1137                                 inst->opcode = OP_REGOFFSET;
1138                                 inst->inst_basereg = cfg->frame_reg;
1139                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1140                                 break;
1141                         case ArgValuetypeInReg:
1142                                 break;
1143                         default:
1144                                 NOT_IMPLEMENTED;
1145                         }
1146
1147                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1148                                 inst->opcode = OP_REGOFFSET;
1149                                 inst->inst_basereg = cfg->frame_reg;
1150                                 /* These arguments are saved to the stack in the prolog */
1151                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1152                                 if (cfg->arch.omit_fp) {
1153                                         inst->inst_offset = offset;
1154                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1155                                 } else {
1156                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1157                                         inst->inst_offset = - offset;
1158                                 }
1159                         }
1160                 }
1161         }
1162
1163         cfg->stack_offset = offset;
1164 }
1165
1166 void
1167 mono_arch_create_vars (MonoCompile *cfg)
1168 {
1169         MonoMethodSignature *sig;
1170         CallInfo *cinfo;
1171
1172         sig = mono_method_signature (cfg->method);
1173
1174         if (!cfg->arch.cinfo)
1175                 cfg->arch.cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
1176         cinfo = cfg->arch.cinfo;
1177
1178         if (cinfo->ret.storage == ArgValuetypeInReg)
1179                 cfg->ret_var_is_local = TRUE;
1180
1181         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1182                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1183                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1184                         printf ("vret_addr = ");
1185                         mono_print_ins (cfg->vret_addr);
1186                 }
1187         }
1188 }
1189
1190 static void
1191 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1192 {
1193         switch (storage) {
1194         case ArgInIReg:
1195                 arg->opcode = OP_OUTARG_REG;
1196                 arg->inst_left = tree;
1197                 arg->inst_call = call;
1198                 arg->backend.reg3 = reg;
1199                 break;
1200         case ArgInFloatSSEReg:
1201                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1202                 arg->inst_left = tree;
1203                 arg->inst_call = call;
1204                 arg->backend.reg3 = reg;
1205                 break;
1206         case ArgInDoubleSSEReg:
1207                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1208                 arg->inst_left = tree;
1209                 arg->inst_call = call;
1210                 arg->backend.reg3 = reg;
1211                 break;
1212         default:
1213                 g_assert_not_reached ();
1214         }
1215 }
1216
1217 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1218  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1219  */
1220
1221 static int
1222 arg_storage_to_ldind (ArgStorage storage)
1223 {
1224         switch (storage) {
1225         case ArgInIReg:
1226                 return CEE_LDIND_I;
1227         case ArgInDoubleSSEReg:
1228                 return CEE_LDIND_R8;
1229         case ArgInFloatSSEReg:
1230                 return CEE_LDIND_R4;
1231         default:
1232                 g_assert_not_reached ();
1233         }
1234
1235         return -1;
1236 }
1237
1238 static void
1239 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1240 {
1241         MonoInst *arg;
1242         MonoMethodSignature *tmp_sig;
1243         MonoInst *sig_arg;
1244
1245         /* FIXME: Add support for signature tokens to AOT */
1246         cfg->disable_aot = TRUE;
1247
1248         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1249
1250         /*
1251          * mono_ArgIterator_Setup assumes the signature cookie is
1252          * passed first and all the arguments which were before it are
1253          * passed on the stack after the signature. So compensate by
1254          * passing a different signature.
1255          */
1256         tmp_sig = mono_metadata_signature_dup (call->signature);
1257         tmp_sig->param_count -= call->signature->sentinelpos;
1258         tmp_sig->sentinelpos = 0;
1259         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1260
1261         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1262         sig_arg->inst_p0 = tmp_sig;
1263
1264         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1265         arg->inst_left = sig_arg;
1266         arg->type = STACK_PTR;
1267         MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1268 }
1269
1270 /*
1271  * take the arguments and generate the arch-specific
1272  * instructions to properly call the function in call.
1273  * This includes pushing, moving arguments to the right register
1274  * etc.
1275  * Issue: who does the spilling if needed, and when?
1276  */
1277 MonoCallInst*
1278 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1279         MonoInst *arg, *in;
1280         MonoMethodSignature *sig;
1281         int i, n, stack_size;
1282         CallInfo *cinfo;
1283         ArgInfo *ainfo;
1284
1285         stack_size = 0;
1286
1287         sig = call->signature;
1288         n = sig->param_count + sig->hasthis;
1289
1290         cinfo = get_call_info (cfg, cfg->mempool, sig, sig->pinvoke);
1291
1292         for (i = 0; i < n; ++i) {
1293                 ainfo = cinfo->args + i;
1294
1295                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1296                         /* Emit the signature cookie just before the implicit arguments */
1297                         emit_sig_cookie (cfg, call, cinfo);
1298                 }
1299
1300                 if (is_virtual && i == 0) {
1301                         /* the argument will be attached to the call instruction */
1302                         in = call->args [i];
1303                 } else {
1304                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1305                         in = call->args [i];
1306                         arg->cil_code = in->cil_code;
1307                         arg->inst_left = in;
1308                         arg->type = in->type;
1309                         if (!cinfo->stack_usage)
1310                                 /* Keep the assignments to the arg registers in order if possible */
1311                                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1312                         else
1313                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1314
1315                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1316                                 guint32 align;
1317                                 guint32 size;
1318
1319                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1320                                         size = sizeof (MonoTypedRef);
1321                                         align = sizeof (gpointer);
1322                                 }
1323                                 else
1324                                 if (sig->pinvoke)
1325                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1326                                 else {
1327                                         /*
1328                                          * Other backends use mini_type_stack_size (), but that
1329                                          * aligns the size to 8, which is larger than the size of
1330                                          * the source, leading to reads of invalid memory if the
1331                                          * source is at the end of address space.
1332                                          */
1333                                         size = mono_class_value_size (in->klass, &align);
1334                                 }
1335                                 if (ainfo->storage == ArgValuetypeInReg) {
1336                                         if (ainfo->pair_storage [1] == ArgNone) {
1337                                                 MonoInst *load;
1338
1339                                                 /* Simpler case */
1340
1341                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1342                                                 load->inst_left = in;
1343
1344                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1345                                         }
1346                                         else {
1347                                                 /* Trees can't be shared so make a copy */
1348                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1349                                                 MonoInst *load, *load2, *offset_ins;
1350
1351                                                 /* Reg1 */
1352                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1353                                                 load->ssa_op = MONO_SSA_LOAD;
1354                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1355
1356                                                 NEW_ICONST (cfg, offset_ins, 0);
1357                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1358                                                 load2->inst_left = load;
1359                                                 load2->inst_right = offset_ins;
1360
1361                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1362                                                 load->inst_left = load2;
1363
1364                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1365
1366                                                 /* Reg2 */
1367                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1368                                                 load->ssa_op = MONO_SSA_LOAD;
1369                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1370
1371                                                 NEW_ICONST (cfg, offset_ins, 8);
1372                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1373                                                 load2->inst_left = load;
1374                                                 load2->inst_right = offset_ins;
1375
1376                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1377                                                 load->inst_left = load2;
1378
1379                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1380                                                 arg->cil_code = in->cil_code;
1381                                                 arg->type = in->type;
1382                                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1383
1384                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1385
1386                                                 /* Prepend a copy inst */
1387                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1388                                                 arg->cil_code = in->cil_code;
1389                                                 arg->ssa_op = MONO_SSA_STORE;
1390                                                 arg->inst_left = vtaddr;
1391                                                 arg->inst_right = in;
1392                                                 arg->type = in->type;
1393
1394                                                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1395                                         }
1396                                 }
1397                                 else {
1398                                         arg->opcode = OP_OUTARG_VT;
1399                                         arg->klass = in->klass;
1400                                         arg->backend.is_pinvoke = sig->pinvoke;
1401                                         arg->inst_imm = size;
1402                                 }
1403                         }
1404                         else {
1405                                 switch (ainfo->storage) {
1406                                 case ArgInIReg:
1407                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1408                                         break;
1409                                 case ArgInFloatSSEReg:
1410                                 case ArgInDoubleSSEReg:
1411                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1412                                         break;
1413                                 case ArgOnStack:
1414                                         arg->opcode = OP_OUTARG;
1415                                         if (!sig->params [i - sig->hasthis]->byref) {
1416                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1417                                                         arg->opcode = OP_OUTARG_R4;
1418                                                 else
1419                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1420                                                                 arg->opcode = OP_OUTARG_R8;
1421                                         }
1422                                         break;
1423                                 default:
1424                                         g_assert_not_reached ();
1425                                 }
1426                         }
1427                 }
1428         }
1429
1430         /* Handle the case where there are no implicit arguments */
1431         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1432                 emit_sig_cookie (cfg, call, cinfo);
1433         }
1434
1435         if (cinfo->need_stack_align) {
1436                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1437                 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1438         }
1439
1440         if (cfg->method->save_lmf) {
1441                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1442                 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1443         }
1444
1445         call->stack_usage = cinfo->stack_usage;
1446         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1447         cfg->flags |= MONO_CFG_HAS_CALLS;
1448
1449         return call;
1450 }
1451
1452 #define EMIT_COND_BRANCH(ins,cond,sign) \
1453 if (ins->flags & MONO_INST_BRLABEL) { \
1454         if (ins->inst_i0->inst_c0) { \
1455                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1456         } else { \
1457                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1458                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1459                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1460                         x86_branch8 (code, cond, 0, sign); \
1461                 else \
1462                         x86_branch32 (code, cond, 0, sign); \
1463         } \
1464 } else { \
1465         if (ins->inst_true_bb->native_offset) { \
1466                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1467         } else { \
1468                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1469                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1470                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1471                         x86_branch8 (code, cond, 0, sign); \
1472                 else \
1473                         x86_branch32 (code, cond, 0, sign); \
1474         } \
1475 }
1476
1477 /* emit an exception if condition is fail */
1478 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1479         do {                                                        \
1480                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1481                 if (tins == NULL) {                                                                             \
1482                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1483                                         MONO_PATCH_INFO_EXC, exc_name);  \
1484                         x86_branch32 (code, cond, 0, signed);               \
1485                 } else {        \
1486                         EMIT_COND_BRANCH (tins, cond, signed);  \
1487                 }                       \
1488         } while (0);
1489
1490 #define EMIT_FPCOMPARE(code) do { \
1491         amd64_fcompp (code); \
1492         amd64_fnstsw (code); \
1493 } while (0);
1494
1495 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1496     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1497         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1498         amd64_ ##op (code); \
1499         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1500         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1501 } while (0);
1502
1503 static guint8*
1504 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1505 {
1506         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1507
1508         /*
1509          * FIXME: Add support for thunks
1510          */
1511         {
1512                 gboolean near_call = FALSE;
1513
1514                 /*
1515                  * Indirect calls are expensive so try to make a near call if possible.
1516                  * The caller memory is allocated by the code manager so it is
1517                  * guaranteed to be at a 32 bit offset.
1518                  */
1519
1520                 if (patch_type != MONO_PATCH_INFO_ABS) {
1521                         /* The target is in memory allocated using the code manager */
1522                         near_call = TRUE;
1523
1524                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1525                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1526                                         /* The callee might be an AOT method */
1527                                         near_call = FALSE;
1528                                 if (((MonoMethod*)data)->dynamic)
1529                                         /* The target is in malloc-ed memory */
1530                                         near_call = FALSE;
1531                         }
1532
1533                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1534                                 /*
1535                                  * The call might go directly to a native function without
1536                                  * the wrapper.
1537                                  */
1538                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1539                                 if (mi) {
1540                                         gconstpointer target = mono_icall_get_wrapper (mi);
1541                                         if ((((guint64)target) >> 32) != 0)
1542                                                 near_call = FALSE;
1543                                 }
1544                         }
1545                 }
1546                 else {
1547                         if (mono_find_class_init_trampoline_by_addr (data))
1548                                 near_call = TRUE;
1549                         else {
1550                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1551                                 if (info) {
1552                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1553                                                 strstr (cfg->method->name, info->name)) {
1554                                                 /* A call to the wrapped function */
1555                                                 if ((((guint64)data) >> 32) == 0)
1556                                                         near_call = TRUE;
1557                                         }
1558                                         else if (info->func == info->wrapper) {
1559                                                 /* No wrapper */
1560                                                 if ((((guint64)info->func) >> 32) == 0)
1561                                                         near_call = TRUE;
1562                                         }
1563                                         else {
1564                                                 /* See the comment in mono_codegen () */
1565                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1566                                                         near_call = TRUE;
1567                                         }
1568                                 }
1569                                 else if ((((guint64)data) >> 32) == 0)
1570                                         near_call = TRUE;
1571                         }
1572                 }
1573
1574                 if (cfg->method->dynamic)
1575                         /* These methods are allocated using malloc */
1576                         near_call = FALSE;
1577
1578                 if (cfg->compile_aot)
1579                         near_call = TRUE;
1580
1581 #ifdef MONO_ARCH_NOMAP32BIT
1582                 near_call = FALSE;
1583 #endif
1584
1585                 if (near_call) {
1586                         amd64_call_code (code, 0);
1587                 }
1588                 else {
1589                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1590                         amd64_call_reg (code, GP_SCRATCH_REG);
1591                 }
1592         }
1593
1594         return code;
1595 }
1596
1597 static inline guint8*
1598 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1599 {
1600         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1601
1602         return emit_call_body (cfg, code, patch_type, data);
1603 }
1604
1605 static inline int
1606 store_membase_imm_to_store_membase_reg (int opcode)
1607 {
1608         switch (opcode) {
1609         case OP_STORE_MEMBASE_IMM:
1610                 return OP_STORE_MEMBASE_REG;
1611         case OP_STOREI4_MEMBASE_IMM:
1612                 return OP_STOREI4_MEMBASE_REG;
1613         case OP_STOREI8_MEMBASE_IMM:
1614                 return OP_STOREI8_MEMBASE_REG;
1615         }
1616
1617         return -1;
1618 }
1619
1620 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
1621
1622 /*
1623  * mono_arch_peephole_pass_1:
1624  *
1625  *   Perform peephole opts which should/can be performed before local regalloc
1626  */
1627 void
1628 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1629 {
1630         MonoInst *ins, *n;
1631
1632         MONO_INST_LIST_FOR_EACH_ENTRY_SAFE (ins, n, &bb->ins_list, node) {
1633                 MonoInst *last_ins = mono_inst_list_prev (&ins->node, &bb->ins_list);
1634
1635                 switch (ins->opcode) {
1636                 case OP_ADD_IMM:
1637                 case OP_IADD_IMM:
1638                 case OP_LADD_IMM:
1639                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
1640                                 /*
1641                                  * X86_LEA is like ADD, but doesn't have the
1642                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
1643                                  * its operand to 64 bit.
1644                                  */
1645                                 ins->opcode = OP_X86_LEA_MEMBASE;
1646                                 ins->inst_basereg = ins->sreg1;
1647                                 /* Fall through */
1648                         }
1649                         else
1650                                 break;
1651                 case OP_LXOR:
1652                 case OP_IXOR:
1653                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1654                                 MonoInst *ins2;
1655
1656                                 /*
1657                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1658                                  * the latter has length 2-3 instead of 6 (reverse constant
1659                                  * propagation). These instruction sequences are very common
1660                                  * in the initlocals bblock.
1661                                  */
1662                                 for (ins2 = mono_inst_list_next (&ins->node, &bb->ins_list); ins2;
1663                                                 ins2 = mono_inst_list_next (&ins2->node, &bb->ins_list)) {
1664                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1665                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1666                                                 ins2->sreg1 = ins->dreg;
1667                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1668                                                 /* Continue */
1669                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1670                                                 NULLIFY_INS (ins2);
1671                                                 /* Continue */
1672                                         } else {
1673                                                 break;
1674                                         }
1675                                 }
1676                         }
1677                         break;
1678                 case OP_COMPARE_IMM:
1679                 case OP_LCOMPARE_IMM:
1680                         /* OP_COMPARE_IMM (reg, 0)
1681                          * -->
1682                          * OP_AMD64_TEST_NULL (reg)
1683                          */
1684                         if (!ins->inst_imm)
1685                                 ins->opcode = OP_AMD64_TEST_NULL;
1686                         break;
1687                 case OP_ICOMPARE_IMM:
1688                         if (!ins->inst_imm)
1689                                 ins->opcode = OP_X86_TEST_NULL;
1690                         break;
1691                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1692                         /*
1693                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1694                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1695                          * -->
1696                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1697                          * OP_COMPARE_IMM reg, imm
1698                          *
1699                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1700                          */
1701                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1702                             ins->inst_basereg == last_ins->inst_destbasereg &&
1703                             ins->inst_offset == last_ins->inst_offset) {
1704                                         ins->opcode = OP_ICOMPARE_IMM;
1705                                         ins->sreg1 = last_ins->sreg1;
1706
1707                                         /* check if we can remove cmp reg,0 with test null */
1708                                         if (!ins->inst_imm)
1709                                                 ins->opcode = OP_X86_TEST_NULL;
1710                                 }
1711
1712                         break;
1713                 case OP_LOAD_MEMBASE:
1714                 case OP_LOADI4_MEMBASE:
1715                         /*
1716                          * Note: if reg1 = reg2 the load op is removed
1717                          *
1718                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1719                          * OP_LOAD_MEMBASE offset(basereg), reg2
1720                          * -->
1721                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1722                          * OP_MOVE reg1, reg2
1723                          */
1724                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1725                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1726                             ins->inst_basereg == last_ins->inst_destbasereg &&
1727                             ins->inst_offset == last_ins->inst_offset) {
1728                                 if (ins->dreg == last_ins->sreg1) {
1729                                         MONO_DEL_INS (ins);
1730                                         continue;
1731                                 } else {
1732                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1733                                         ins->opcode = OP_MOVE;
1734                                         ins->sreg1 = last_ins->sreg1;
1735                                 }
1736
1737                         /*
1738                          * Note: reg1 must be different from the basereg in the second load
1739                          * Note: if reg1 = reg2 is equal then second load is removed
1740                          *
1741                          * OP_LOAD_MEMBASE offset(basereg), reg1
1742                          * OP_LOAD_MEMBASE offset(basereg), reg2
1743                          * -->
1744                          * OP_LOAD_MEMBASE offset(basereg), reg1
1745                          * OP_MOVE reg1, reg2
1746                          */
1747                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1748                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1749                               ins->inst_basereg != last_ins->dreg &&
1750                               ins->inst_basereg == last_ins->inst_basereg &&
1751                               ins->inst_offset == last_ins->inst_offset) {
1752
1753                                 if (ins->dreg == last_ins->dreg) {
1754                                         MONO_DEL_INS (ins);
1755                                         continue;
1756                                 } else {
1757                                         ins->opcode = OP_MOVE;
1758                                         ins->sreg1 = last_ins->dreg;
1759                                 }
1760
1761                                 //g_assert_not_reached ();
1762
1763 #if 0
1764                         /*
1765                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1766                          * OP_LOAD_MEMBASE offset(basereg), reg
1767                          * -->
1768                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1769                          * OP_ICONST reg, imm
1770                          */
1771                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1772                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1773                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1774                                    ins->inst_offset == last_ins->inst_offset) {
1775                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1776                                 ins->opcode = OP_ICONST;
1777                                 ins->inst_c0 = last_ins->inst_imm;
1778                                 g_assert_not_reached (); // check this rule
1779 #endif
1780                         }
1781                         break;
1782                 case OP_LOADI1_MEMBASE:
1783                         /*
1784                          * Note: if reg1 = reg2 the load op is removed
1785                          *
1786                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1787                          * OP_LOAD_MEMBASE offset(basereg), reg2
1788                          * -->
1789                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1790                          * OP_MOVE reg1, reg2
1791                          */
1792                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1793                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1794                                         ins->inst_offset == last_ins->inst_offset) {
1795                                 if (ins->dreg == last_ins->sreg1) {
1796                                         MONO_DEL_INS (ins);
1797                                         continue;
1798                                 } else {
1799                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1800                                         ins->opcode = OP_MOVE;
1801                                         ins->sreg1 = last_ins->sreg1;
1802                                 }
1803                         }
1804                         break;
1805                 case OP_LOADI2_MEMBASE:
1806                         /*
1807                          * Note: if reg1 = reg2 the load op is removed
1808                          *
1809                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1810                          * OP_LOAD_MEMBASE offset(basereg), reg2
1811                          * -->
1812                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1813                          * OP_MOVE reg1, reg2
1814                          */
1815                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1816                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1817                                         ins->inst_offset == last_ins->inst_offset) {
1818                                 if (ins->dreg == last_ins->sreg1) {
1819                                         MONO_DEL_INS (ins);
1820                                         continue;
1821                                 } else {
1822                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1823                                         ins->opcode = OP_MOVE;
1824                                         ins->sreg1 = last_ins->sreg1;
1825                                 }
1826                         }
1827                         break;
1828                 case OP_MOVE:
1829                 case OP_FMOVE:
1830                         /*
1831                          * Removes:
1832                          *
1833                          * OP_MOVE reg, reg
1834                          */
1835                         if (ins->dreg == ins->sreg1) {
1836                                 MONO_DEL_INS (ins);
1837                                 continue;
1838                         }
1839                         /*
1840                          * Removes:
1841                          *
1842                          * OP_MOVE sreg, dreg
1843                          * OP_MOVE dreg, sreg
1844                          */
1845                         if (last_ins && last_ins->opcode == OP_MOVE &&
1846                             ins->sreg1 == last_ins->dreg &&
1847                             ins->dreg == last_ins->sreg1) {
1848                                 MONO_DEL_INS (ins);
1849                                 continue;
1850                         }
1851                         break;
1852                 }
1853         }
1854 }
1855
1856 void
1857 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1858 {
1859         MonoInst *ins, *n;
1860
1861         MONO_INST_LIST_FOR_EACH_ENTRY_SAFE (ins, n, &bb->ins_list, node) {
1862                 MonoInst *last_ins = mono_inst_list_prev (&ins->node, &bb->ins_list);
1863
1864                 switch (ins->opcode) {
1865                 case OP_ICONST:
1866                 case OP_I8CONST: {
1867                         MonoInst *next;
1868
1869                         /* reg = 0 -> XOR (reg, reg) */
1870                         /* XOR sets cflags on x86, so we cant do it always */
1871                         next = mono_inst_list_next (&ins->node, &bb->ins_list);
1872                         if (ins->inst_c0 == 0 && (!next ||
1873                                         (next && INST_IGNORES_CFLAGS (next->opcode)))) {
1874                                 ins->opcode = OP_LXOR;
1875                                 ins->sreg1 = ins->dreg;
1876                                 ins->sreg2 = ins->dreg;
1877                                 /* Fall through */
1878                         } else {
1879                                 break;
1880                         }
1881                 }
1882                 case OP_LXOR:
1883                         /*
1884                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
1885                          * 0 result into 64 bits.
1886                          */
1887                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1888                                 ins->opcode = OP_IXOR;
1889                         }
1890                         /* Fall through */
1891                 case OP_IXOR:
1892                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1893                                 MonoInst *ins2;
1894
1895                                 /*
1896                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1897                                  * the latter has length 2-3 instead of 6 (reverse constant
1898                                  * propagation). These instruction sequences are very common
1899                                  * in the initlocals bblock.
1900                                  */
1901                                 for (ins2 = mono_inst_list_next (&ins->node, &bb->ins_list); ins2;
1902                                                 ins2 = mono_inst_list_next (&ins2->node, &bb->ins_list)) {
1903                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1904                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1905                                                 ins2->sreg1 = ins->dreg;
1906                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1907                                                 /* Continue */
1908                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1909                                                 NULLIFY_INS (ins2);
1910                                                 /* Continue */
1911                                         } else {
1912                                                 break;
1913                                         }
1914                                 }
1915                         }
1916                         break;
1917                 case OP_IADD_IMM:
1918                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1919                                 ins->opcode = OP_X86_INC_REG;
1920                         break;
1921                 case OP_ISUB_IMM:
1922                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1923                                 ins->opcode = OP_X86_DEC_REG;
1924                         break;
1925                 case OP_MUL_IMM:
1926                         /* remove unnecessary multiplication with 1 */
1927                         if (ins->inst_imm == 1) {
1928                                 if (ins->dreg != ins->sreg1) {
1929                                         ins->opcode = OP_MOVE;
1930                                 } else {
1931                                         MONO_DEL_INS (ins);
1932                                         continue;
1933                                 }
1934                         }
1935                         break;
1936                 case OP_COMPARE_IMM:
1937                         /* OP_COMPARE_IMM (reg, 0)
1938                          * -->
1939                          * OP_AMD64_TEST_NULL (reg)
1940                          */
1941                         if (!ins->inst_imm)
1942                                 ins->opcode = OP_AMD64_TEST_NULL;
1943                         break;
1944                 case OP_ICOMPARE_IMM:
1945                         if (!ins->inst_imm)
1946                                 ins->opcode = OP_X86_TEST_NULL;
1947                         break;
1948                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1949                         /*
1950                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1951                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1952                          * -->
1953                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1954                          * OP_COMPARE_IMM reg, imm
1955                          *
1956                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1957                          */
1958                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1959                             ins->inst_basereg == last_ins->inst_destbasereg &&
1960                             ins->inst_offset == last_ins->inst_offset) {
1961                                         ins->opcode = OP_ICOMPARE_IMM;
1962                                         ins->sreg1 = last_ins->sreg1;
1963
1964                                         /* check if we can remove cmp reg,0 with test null */
1965                                         if (!ins->inst_imm)
1966                                                 ins->opcode = OP_X86_TEST_NULL;
1967                                 }
1968
1969                         break;
1970                 case OP_LOAD_MEMBASE:
1971                 case OP_LOADI4_MEMBASE:
1972                         /*
1973                          * Note: if reg1 = reg2 the load op is removed
1974                          *
1975                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1976                          * OP_LOAD_MEMBASE offset(basereg), reg2
1977                          * -->
1978                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1979                          * OP_MOVE reg1, reg2
1980                          */
1981                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1982                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1983                             ins->inst_basereg == last_ins->inst_destbasereg &&
1984                             ins->inst_offset == last_ins->inst_offset) {
1985                                 if (ins->dreg == last_ins->sreg1) {
1986                                         MONO_DEL_INS (ins);
1987                                         continue;
1988                                 } else {
1989                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1990                                         ins->opcode = OP_MOVE;
1991                                         ins->sreg1 = last_ins->sreg1;
1992                                 }
1993
1994                         /*
1995                          * Note: reg1 must be different from the basereg in the second load
1996                          * Note: if reg1 = reg2 is equal then second load is removed
1997                          *
1998                          * OP_LOAD_MEMBASE offset(basereg), reg1
1999                          * OP_LOAD_MEMBASE offset(basereg), reg2
2000                          * -->
2001                          * OP_LOAD_MEMBASE offset(basereg), reg1
2002                          * OP_MOVE reg1, reg2
2003                          */
2004                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
2005                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
2006                               ins->inst_basereg != last_ins->dreg &&
2007                               ins->inst_basereg == last_ins->inst_basereg &&
2008                               ins->inst_offset == last_ins->inst_offset) {
2009
2010                                 if (ins->dreg == last_ins->dreg) {
2011                                         MONO_DEL_INS (ins);
2012                                         continue;
2013                                 } else {
2014                                         ins->opcode = OP_MOVE;
2015                                         ins->sreg1 = last_ins->dreg;
2016                                 }
2017
2018                                 //g_assert_not_reached ();
2019
2020 #if 0
2021                         /*
2022                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2023                          * OP_LOAD_MEMBASE offset(basereg), reg
2024                          * -->
2025                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
2026                          * OP_ICONST reg, imm
2027                          */
2028                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
2029                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
2030                                    ins->inst_basereg == last_ins->inst_destbasereg &&
2031                                    ins->inst_offset == last_ins->inst_offset) {
2032                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
2033                                 ins->opcode = OP_ICONST;
2034                                 ins->inst_c0 = last_ins->inst_imm;
2035                                 g_assert_not_reached (); // check this rule
2036 #endif
2037                         }
2038                         break;
2039                 case OP_LOADI1_MEMBASE:
2040                 case OP_LOADU1_MEMBASE:
2041                         /*
2042                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2043                          * OP_LOAD_MEMBASE offset(basereg), reg2
2044                          * -->
2045                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2046                          * CONV_I1/U1 reg1, reg2
2047                          */
2048                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
2049                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2050                                         ins->inst_offset == last_ins->inst_offset) {
2051                                 ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? OP_PCONV_TO_I1 : OP_PCONV_TO_U1;
2052                                 ins->sreg1 = last_ins->sreg1;
2053                         }
2054                         break;
2055                 case OP_LOADI2_MEMBASE:
2056                 case OP_LOADU2_MEMBASE:
2057                         /*
2058                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2059                          * OP_LOAD_MEMBASE offset(basereg), reg2
2060                          * -->
2061                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
2062                          * CONV_I2/U2 reg1, reg2
2063                          */
2064                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
2065                                         ins->inst_basereg == last_ins->inst_destbasereg &&
2066                                         ins->inst_offset == last_ins->inst_offset) {
2067                                 ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? OP_PCONV_TO_I2 : OP_PCONV_TO_U2;
2068                                 ins->sreg1 = last_ins->sreg1;
2069                         }
2070                         break;
2071                 case OP_MOVE:
2072                 case OP_FMOVE:
2073                         /*
2074                          * Removes:
2075                          *
2076                          * OP_MOVE reg, reg
2077                          */
2078                         if (ins->dreg == ins->sreg1) {
2079                                 MONO_DEL_INS (ins);
2080                                 continue;
2081                         }
2082                         /*
2083                          * Removes:
2084                          *
2085                          * OP_MOVE sreg, dreg
2086                          * OP_MOVE dreg, sreg
2087                          */
2088                         if (last_ins && last_ins->opcode == OP_MOVE &&
2089                                         ins->sreg1 == last_ins->dreg &&
2090                                         ins->dreg == last_ins->sreg1) {
2091                                 MONO_DEL_INS (ins);
2092                                 continue;
2093                         }
2094                         break;
2095                 }
2096         }
2097 }
2098
2099 #define NEW_INS(cfg,ins,dest,op) do {                                   \
2100                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
2101                 (dest)->opcode = (op);  \
2102                 MONO_INST_LIST_ADD_TAIL (&(dest)->node, &(ins)->node); \
2103         } while (0)
2104
2105 /*
2106  * mono_arch_lowering_pass:
2107  *
2108  *  Converts complex opcodes into simpler ones so that each IR instruction
2109  * corresponds to one machine instruction.
2110  */
2111 void
2112 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2113 {
2114         MonoInst *ins, *n, *temp;
2115
2116         if (bb->max_vreg > cfg->rs->next_vreg)
2117                 cfg->rs->next_vreg = bb->max_vreg;
2118
2119         /*
2120          * FIXME: Need to add more instructions, but the current machine
2121          * description can't model some parts of the composite instructions like
2122          * cdq.
2123          */
2124         MONO_INST_LIST_FOR_EACH_ENTRY_SAFE (ins, n, &bb->ins_list, node) {
2125                 switch (ins->opcode) {
2126                 case OP_DIV_IMM:
2127                 case OP_REM_IMM:
2128                 case OP_IDIV_IMM:
2129                 case OP_IREM_IMM:
2130                 case OP_IDIV_UN_IMM:
2131                 case OP_IREM_UN_IMM:
2132                         NEW_INS (cfg, ins, temp, OP_ICONST);
2133                         temp->inst_c0 = ins->inst_imm;
2134                         temp->dreg = mono_regstate_next_int (cfg->rs);
2135                         ins->opcode = mono_op_imm_to_op (ins->opcode);
2136                         ins->sreg2 = temp->dreg;
2137                         break;
2138                 case OP_COMPARE_IMM:
2139                 case OP_LCOMPARE_IMM:
2140                         if (!amd64_is_imm32 (ins->inst_imm)) {
2141                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2142                                 temp->inst_c0 = ins->inst_imm;
2143                                 temp->dreg = mono_regstate_next_int (cfg->rs);
2144                                 ins->opcode = OP_COMPARE;
2145                                 ins->sreg2 = temp->dreg;
2146                         }
2147                         break;
2148                 case OP_LOAD_MEMBASE:
2149                 case OP_LOADI8_MEMBASE:
2150                         if (!amd64_is_imm32 (ins->inst_offset)) {
2151                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2152                                 temp->inst_c0 = ins->inst_offset;
2153                                 temp->dreg = mono_regstate_next_int (cfg->rs);
2154                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2155                                 ins->inst_indexreg = temp->dreg;
2156                         }
2157                         break;
2158                 case OP_STORE_MEMBASE_IMM:
2159                 case OP_STOREI8_MEMBASE_IMM:
2160                         if (!amd64_is_imm32 (ins->inst_imm)) {
2161                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2162                                 temp->inst_c0 = ins->inst_imm;
2163                                 temp->dreg = mono_regstate_next_int (cfg->rs);
2164                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2165                                 ins->sreg1 = temp->dreg;
2166                         }
2167                         break;
2168                 default:
2169                         break;
2170                 }
2171         }
2172
2173         bb->max_vreg = cfg->rs->next_vreg;
2174 }
2175
2176 static const int
2177 branch_cc_table [] = {
2178         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2179         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2180         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2181 };
2182
2183 /* Maps CMP_... constants to X86_CC_... constants */
2184 static const int
2185 cc_table [] = {
2186         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2187         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2188 };
2189
2190 static const int
2191 cc_signed_table [] = {
2192         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2193         FALSE, FALSE, FALSE, FALSE
2194 };
2195
2196 /*#include "cprop.c"*/
2197
2198 static unsigned char*
2199 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2200 {
2201         if (use_sse2) {
2202                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2203         }
2204         else {
2205                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
2206                 x86_fnstcw_membase(code, AMD64_RSP, 0);
2207                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
2208                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2209                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
2210                 amd64_fldcw_membase (code, AMD64_RSP, 2);
2211                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
2212                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
2213                 amd64_pop_reg (code, dreg);
2214                 amd64_fldcw_membase (code, AMD64_RSP, 0);
2215                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
2216         }
2217
2218         if (size == 1)
2219                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2220         else if (size == 2)
2221                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2222         return code;
2223 }
2224
2225 static unsigned char*
2226 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2227 {
2228         int sreg = tree->sreg1;
2229         int need_touch = FALSE;
2230
2231 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2232         if (!tree->flags & MONO_INST_INIT)
2233                 need_touch = TRUE;
2234 #endif
2235
2236         if (need_touch) {
2237                 guint8* br[5];
2238
2239                 /*
2240                  * Under Windows:
2241                  * If requested stack size is larger than one page,
2242                  * perform stack-touch operation
2243                  */
2244                 /*
2245                  * Generate stack probe code.
2246                  * Under Windows, it is necessary to allocate one page at a time,
2247                  * "touching" stack after each successful sub-allocation. This is
2248                  * because of the way stack growth is implemented - there is a
2249                  * guard page before the lowest stack page that is currently commited.
2250                  * Stack normally grows sequentially so OS traps access to the
2251                  * guard page and commits more pages when needed.
2252                  */
2253                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2254                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2255
2256                 br[2] = code; /* loop */
2257                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2258                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2259                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2260                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2261                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2262                 amd64_patch (br[3], br[2]);
2263                 amd64_test_reg_reg (code, sreg, sreg);
2264                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2265                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2266
2267                 br[1] = code; x86_jump8 (code, 0);
2268
2269                 amd64_patch (br[0], code);
2270                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2271                 amd64_patch (br[1], code);
2272                 amd64_patch (br[4], code);
2273         }
2274         else
2275                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2276
2277         if (tree->flags & MONO_INST_INIT) {
2278                 int offset = 0;
2279                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2280                         amd64_push_reg (code, AMD64_RAX);
2281                         offset += 8;
2282                 }
2283                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2284                         amd64_push_reg (code, AMD64_RCX);
2285                         offset += 8;
2286                 }
2287                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2288                         amd64_push_reg (code, AMD64_RDI);
2289                         offset += 8;
2290                 }
2291
2292                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2293                 if (sreg != AMD64_RCX)
2294                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2295                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2296
2297                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2298                 amd64_cld (code);
2299                 amd64_prefix (code, X86_REP_PREFIX);
2300                 amd64_stosl (code);
2301
2302                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2303                         amd64_pop_reg (code, AMD64_RDI);
2304                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2305                         amd64_pop_reg (code, AMD64_RCX);
2306                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2307                         amd64_pop_reg (code, AMD64_RAX);
2308         }
2309         return code;
2310 }
2311
2312 static guint8*
2313 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2314 {
2315         CallInfo *cinfo;
2316         guint32 quad;
2317
2318         /* Move return value to the target register */
2319         /* FIXME: do this in the local reg allocator */
2320         switch (ins->opcode) {
2321         case OP_CALL:
2322         case OP_CALL_REG:
2323         case OP_CALL_MEMBASE:
2324         case OP_LCALL:
2325         case OP_LCALL_REG:
2326         case OP_LCALL_MEMBASE:
2327                 g_assert (ins->dreg == AMD64_RAX);
2328                 break;
2329         case OP_FCALL:
2330         case OP_FCALL_REG:
2331         case OP_FCALL_MEMBASE:
2332                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2333                         if (use_sse2)
2334                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2335                         else {
2336                                 /* FIXME: optimize this */
2337                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2338                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2339                         }
2340                 }
2341                 else {
2342                         if (use_sse2) {
2343                                 if (ins->dreg != AMD64_XMM0)
2344                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2345                         }
2346                         else {
2347                                 /* FIXME: optimize this */
2348                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2349                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2350                         }
2351                 }
2352                 break;
2353         case OP_VCALL:
2354         case OP_VCALL_REG:
2355         case OP_VCALL_MEMBASE:
2356                 cinfo = get_call_info (cfg, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2357                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2358                         /* Pop the destination address from the stack */
2359                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2360                         amd64_pop_reg (code, AMD64_RCX);
2361
2362                         for (quad = 0; quad < 2; quad ++) {
2363                                 switch (cinfo->ret.pair_storage [quad]) {
2364                                 case ArgInIReg:
2365                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2366                                         break;
2367                                 case ArgInFloatSSEReg:
2368                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2369                                         break;
2370                                 case ArgInDoubleSSEReg:
2371                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2372                                         break;
2373                                 case ArgNone:
2374                                         break;
2375                                 default:
2376                                         NOT_IMPLEMENTED;
2377                                 }
2378                         }
2379                 }
2380                 break;
2381         }
2382
2383         return code;
2384 }
2385
2386 /*
2387  * emit_tls_get:
2388  * @code: buffer to store code to
2389  * @dreg: hard register where to place the result
2390  * @tls_offset: offset info
2391  *
2392  * emit_tls_get emits in @code the native code that puts in the dreg register
2393  * the item in the thread local storage identified by tls_offset.
2394  *
2395  * Returns: a pointer to the end of the stored code
2396  */
2397 static guint8*
2398 emit_tls_get (guint8* code, int dreg, int tls_offset)
2399 {
2400         if (optimize_for_xen) {
2401                 x86_prefix (code, X86_FS_PREFIX);
2402                 amd64_mov_reg_mem (code, dreg, 0, 8);
2403                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2404         } else {
2405                 x86_prefix (code, X86_FS_PREFIX);
2406                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2407         }
2408         return code;
2409 }
2410
2411 /*
2412  * emit_load_volatile_arguments:
2413  *
2414  *  Load volatile arguments from the stack to the original input registers.
2415  * Required before a tail call.
2416  */
2417 static guint8*
2418 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2419 {
2420         MonoMethod *method = cfg->method;
2421         MonoMethodSignature *sig;
2422         MonoInst *inst;
2423         CallInfo *cinfo;
2424         guint32 i;
2425
2426         /* FIXME: Generate intermediate code instead */
2427
2428         sig = mono_method_signature (method);
2429
2430         cinfo = cfg->arch.cinfo;
2431
2432         /* This is the opposite of the code in emit_prolog */
2433
2434         if (sig->ret->type != MONO_TYPE_VOID) {
2435                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2436                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2437         }
2438
2439         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2440                 ArgInfo *ainfo = cinfo->args + i;
2441                 MonoType *arg_type;
2442                 inst = cfg->args [i];
2443
2444                 if (sig->hasthis && (i == 0))
2445                         arg_type = &mono_defaults.object_class->byval_arg;
2446                 else
2447                         arg_type = sig->params [i - sig->hasthis];
2448
2449                 if (inst->opcode != OP_REGVAR) {
2450                         switch (ainfo->storage) {
2451                         case ArgInIReg: {
2452                                 guint32 size = 8;
2453
2454                                 /* FIXME: I1 etc */
2455                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2456                                 break;
2457                         }
2458                         case ArgInFloatSSEReg:
2459                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2460                                 break;
2461                         case ArgInDoubleSSEReg:
2462                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2463                                 break;
2464                         default:
2465                                 break;
2466                         }
2467                 }
2468                 else {
2469                         g_assert (ainfo->storage == ArgInIReg);
2470
2471                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2472                 }
2473         }
2474
2475         return code;
2476 }
2477
2478 #define REAL_PRINT_REG(text,reg) \
2479 mono_assert (reg >= 0); \
2480 amd64_push_reg (code, AMD64_RAX); \
2481 amd64_push_reg (code, AMD64_RDX); \
2482 amd64_push_reg (code, AMD64_RCX); \
2483 amd64_push_reg (code, reg); \
2484 amd64_push_imm (code, reg); \
2485 amd64_push_imm (code, text " %d %p\n"); \
2486 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2487 amd64_call_reg (code, AMD64_RAX); \
2488 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2489 amd64_pop_reg (code, AMD64_RCX); \
2490 amd64_pop_reg (code, AMD64_RDX); \
2491 amd64_pop_reg (code, AMD64_RAX);
2492
2493 /* benchmark and set based on cpu */
2494 #define LOOP_ALIGNMENT 8
2495 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2496
2497 void
2498 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2499 {
2500         MonoInst *ins;
2501         MonoCallInst *call;
2502         guint offset;
2503         guint8 *code = cfg->native_code + cfg->code_len;
2504         guint last_offset = 0;
2505         int max_len, cpos;
2506
2507         if (cfg->opt & MONO_OPT_LOOP) {
2508                 int pad, align = LOOP_ALIGNMENT;
2509                 /* set alignment depending on cpu */
2510                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2511                         pad = align - pad;
2512                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2513                         amd64_padding (code, pad);
2514                         cfg->code_len += pad;
2515                         bb->native_offset = cfg->code_len;
2516                 }
2517         }
2518
2519         if (cfg->verbose_level > 2)
2520                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2521
2522         cpos = bb->max_offset;
2523
2524         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2525                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2526                 g_assert (!cfg->compile_aot);
2527                 cpos += 6;
2528
2529                 cov->data [bb->dfn].cil_code = bb->cil_code;
2530                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2531                 /* this is not thread save, but good enough */
2532                 amd64_inc_membase (code, AMD64_R11, 0);
2533         }
2534
2535         offset = code - cfg->native_code;
2536
2537         mono_debug_open_block (cfg, bb, offset);
2538
2539         MONO_BB_FOR_EACH_INS (bb, ins) {
2540                 offset = code - cfg->native_code;
2541
2542                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2543
2544                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2545                         cfg->code_size *= 2;
2546                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2547                         code = cfg->native_code + offset;
2548                         mono_jit_stats.code_reallocs++;
2549                 }
2550
2551                 if (cfg->debug_info)
2552                         mono_debug_record_line_number (cfg, ins, offset);
2553
2554                 switch (ins->opcode) {
2555                 case OP_BIGMUL:
2556                         amd64_mul_reg (code, ins->sreg2, TRUE);
2557                         break;
2558                 case OP_BIGMUL_UN:
2559                         amd64_mul_reg (code, ins->sreg2, FALSE);
2560                         break;
2561                 case OP_X86_SETEQ_MEMBASE:
2562                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2563                         break;
2564                 case OP_STOREI1_MEMBASE_IMM:
2565                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2566                         break;
2567                 case OP_STOREI2_MEMBASE_IMM:
2568                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2569                         break;
2570                 case OP_STOREI4_MEMBASE_IMM:
2571                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2572                         break;
2573                 case OP_STOREI1_MEMBASE_REG:
2574                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2575                         break;
2576                 case OP_STOREI2_MEMBASE_REG:
2577                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2578                         break;
2579                 case OP_STORE_MEMBASE_REG:
2580                 case OP_STOREI8_MEMBASE_REG:
2581                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2582                         break;
2583                 case OP_STOREI4_MEMBASE_REG:
2584                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2585                         break;
2586                 case OP_STORE_MEMBASE_IMM:
2587                 case OP_STOREI8_MEMBASE_IMM:
2588                         g_assert (amd64_is_imm32 (ins->inst_imm));
2589                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2590                         break;
2591                 case OP_LOAD_MEM:
2592                 case OP_LOADI8_MEM:
2593                         // FIXME: Decompose this earlier
2594                         if (amd64_is_imm32 (ins->inst_imm))
2595                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2596                         else {
2597                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2598                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2599                         }
2600                         break;
2601                 case OP_LOADI4_MEM:
2602                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2603                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2604                         break;
2605                 case OP_LOADU4_MEM:
2606                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2607                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2608                         break;
2609                 case OP_LOADU1_MEM:
2610                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2611                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2612                         break;
2613                 case OP_LOADU2_MEM:
2614                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2615                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2616                         break;
2617                 case OP_LOAD_MEMBASE:
2618                 case OP_LOADI8_MEMBASE:
2619                         g_assert (amd64_is_imm32 (ins->inst_offset));
2620                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2621                         break;
2622                 case OP_LOADI4_MEMBASE:
2623                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2624                         break;
2625                 case OP_LOADU4_MEMBASE:
2626                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2627                         break;
2628                 case OP_LOADU1_MEMBASE:
2629                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2630                         break;
2631                 case OP_LOADI1_MEMBASE:
2632                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2633                         break;
2634                 case OP_LOADU2_MEMBASE:
2635                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2636                         break;
2637                 case OP_LOADI2_MEMBASE:
2638                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2639                         break;
2640                 case OP_AMD64_LOADI8_MEMINDEX:
2641                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2642                         break;
2643                 case OP_LCONV_TO_I1:
2644                 case OP_ICONV_TO_I1:
2645                 case OP_SEXT_I1:
2646                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2647                         break;
2648                 case OP_LCONV_TO_I2:
2649                 case OP_ICONV_TO_I2:
2650                 case OP_SEXT_I2:
2651                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2652                         break;
2653                 case OP_LCONV_TO_U1:
2654                 case OP_ICONV_TO_U1:
2655                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2656                         break;
2657                 case OP_LCONV_TO_U2:
2658                 case OP_ICONV_TO_U2:
2659                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2660                         break;
2661                 case OP_ZEXT_I4:
2662                         /* Clean out the upper word */
2663                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2664                         break;
2665                 case OP_SEXT_I4:
2666                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2667                         break;
2668                 case OP_COMPARE:
2669                 case OP_LCOMPARE:
2670                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2671                         break;
2672                 case OP_COMPARE_IMM:
2673                 case OP_LCOMPARE_IMM:
2674                         g_assert (amd64_is_imm32 (ins->inst_imm));
2675                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2676                         break;
2677                 case OP_X86_COMPARE_REG_MEMBASE:
2678                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2679                         break;
2680                 case OP_X86_TEST_NULL:
2681                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2682                         break;
2683                 case OP_AMD64_TEST_NULL:
2684                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2685                         break;
2686
2687                 case OP_X86_ADD_REG_MEMBASE:
2688                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2689                         break;
2690                 case OP_X86_SUB_REG_MEMBASE:
2691                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2692                         break;
2693                 case OP_X86_AND_REG_MEMBASE:
2694                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2695                         break;
2696                 case OP_X86_OR_REG_MEMBASE:
2697                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2698                         break;
2699                 case OP_X86_XOR_REG_MEMBASE:
2700                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2701                         break;
2702
2703                 case OP_X86_ADD_MEMBASE_IMM:
2704                         /* FIXME: Make a 64 version too */
2705                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2706                         break;
2707                 case OP_X86_SUB_MEMBASE_IMM:
2708                         g_assert (amd64_is_imm32 (ins->inst_imm));
2709                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2710                         break;
2711                 case OP_X86_AND_MEMBASE_IMM:
2712                         g_assert (amd64_is_imm32 (ins->inst_imm));
2713                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2714                         break;
2715                 case OP_X86_OR_MEMBASE_IMM:
2716                         g_assert (amd64_is_imm32 (ins->inst_imm));
2717                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2718                         break;
2719                 case OP_X86_XOR_MEMBASE_IMM:
2720                         g_assert (amd64_is_imm32 (ins->inst_imm));
2721                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2722                         break;
2723                 case OP_X86_ADD_MEMBASE_REG:
2724                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2725                         break;
2726                 case OP_X86_SUB_MEMBASE_REG:
2727                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2728                         break;
2729                 case OP_X86_AND_MEMBASE_REG:
2730                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2731                         break;
2732                 case OP_X86_OR_MEMBASE_REG:
2733                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2734                         break;
2735                 case OP_X86_XOR_MEMBASE_REG:
2736                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2737                         break;
2738                 case OP_X86_INC_MEMBASE:
2739                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2740                         break;
2741                 case OP_X86_INC_REG:
2742                         amd64_inc_reg_size (code, ins->dreg, 4);
2743                         break;
2744                 case OP_X86_DEC_MEMBASE:
2745                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2746                         break;
2747                 case OP_X86_DEC_REG:
2748                         amd64_dec_reg_size (code, ins->dreg, 4);
2749                         break;
2750                 case OP_X86_MUL_REG_MEMBASE:
2751                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2752                         break;
2753                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2754                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2755                         break;
2756                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2757                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2758                         break;
2759                 case OP_AMD64_COMPARE_MEMBASE_REG:
2760                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2761                         break;
2762                 case OP_AMD64_COMPARE_MEMBASE_IMM:
2763                         g_assert (amd64_is_imm32 (ins->inst_imm));
2764                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2765                         break;
2766                 case OP_X86_COMPARE_MEMBASE8_IMM:
2767                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2768                         break;
2769                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2770                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2771                         break;
2772                 case OP_AMD64_COMPARE_REG_MEMBASE:
2773                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2774                         break;
2775
2776                 case OP_AMD64_ADD_REG_MEMBASE:
2777                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2778                         break;
2779                 case OP_AMD64_SUB_REG_MEMBASE:
2780                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2781                         break;
2782                 case OP_AMD64_AND_REG_MEMBASE:
2783                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2784                         break;
2785                 case OP_AMD64_OR_REG_MEMBASE:
2786                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2787                         break;
2788                 case OP_AMD64_XOR_REG_MEMBASE:
2789                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2790                         break;
2791
2792                 case OP_AMD64_ADD_MEMBASE_REG:
2793                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2794                         break;
2795                 case OP_AMD64_SUB_MEMBASE_REG:
2796                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2797                         break;
2798                 case OP_AMD64_AND_MEMBASE_REG:
2799                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2800                         break;
2801                 case OP_AMD64_OR_MEMBASE_REG:
2802                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2803                         break;
2804                 case OP_AMD64_XOR_MEMBASE_REG:
2805                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2806                         break;
2807
2808                 case OP_AMD64_ADD_MEMBASE_IMM:
2809                         g_assert (amd64_is_imm32 (ins->inst_imm));
2810                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2811                         break;
2812                 case OP_AMD64_SUB_MEMBASE_IMM:
2813                         g_assert (amd64_is_imm32 (ins->inst_imm));
2814                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2815                         break;
2816                 case OP_AMD64_AND_MEMBASE_IMM:
2817                         g_assert (amd64_is_imm32 (ins->inst_imm));
2818                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2819                         break;
2820                 case OP_AMD64_OR_MEMBASE_IMM:
2821                         g_assert (amd64_is_imm32 (ins->inst_imm));
2822                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2823                         break;
2824                 case OP_AMD64_XOR_MEMBASE_IMM:
2825                         g_assert (amd64_is_imm32 (ins->inst_imm));
2826                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2827                         break;
2828
2829                 case OP_BREAK:
2830                         amd64_breakpoint (code);
2831                         break;
2832                 case OP_NOP:
2833                 case OP_DUMMY_USE:
2834                 case OP_DUMMY_STORE:
2835                 case OP_NOT_REACHED:
2836                 case OP_NOT_NULL:
2837                         break;
2838                 case OP_ADDCC:
2839                 case OP_LADD:
2840                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2841                         break;
2842                 case OP_ADC:
2843                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2844                         break;
2845                 case OP_ADD_IMM:
2846                 case OP_LADD_IMM:
2847                         g_assert (amd64_is_imm32 (ins->inst_imm));
2848                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2849                         break;
2850                 case OP_ADC_IMM:
2851                         g_assert (amd64_is_imm32 (ins->inst_imm));
2852                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2853                         break;
2854                 case OP_SUBCC:
2855                 case OP_LSUB:
2856                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2857                         break;
2858                 case OP_SBB:
2859                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2860                         break;
2861                 case OP_SUB_IMM:
2862                 case OP_LSUB_IMM:
2863                         g_assert (amd64_is_imm32 (ins->inst_imm));
2864                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2865                         break;
2866                 case OP_SBB_IMM:
2867                         g_assert (amd64_is_imm32 (ins->inst_imm));
2868                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2869                         break;
2870                 case OP_LAND:
2871                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2872                         break;
2873                 case OP_AND_IMM:
2874                 case OP_LAND_IMM:
2875                         g_assert (amd64_is_imm32 (ins->inst_imm));
2876                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2877                         break;
2878                 case OP_LMUL:
2879                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2880                         break;
2881                 case OP_MUL_IMM:
2882                 case OP_LMUL_IMM:
2883                 case OP_IMUL_IMM: {
2884                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2885
2886                         switch (ins->inst_imm) {
2887                         case 2:
2888                                 /* MOV r1, r2 */
2889                                 /* ADD r1, r1 */
2890                                 if (ins->dreg != ins->sreg1)
2891                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2892                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2893                                 break;
2894                         case 3:
2895                                 /* LEA r1, [r2 + r2*2] */
2896                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2897                                 break;
2898                         case 5:
2899                                 /* LEA r1, [r2 + r2*4] */
2900                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2901                                 break;
2902                         case 6:
2903                                 /* LEA r1, [r2 + r2*2] */
2904                                 /* ADD r1, r1          */
2905                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2906                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2907                                 break;
2908                         case 9:
2909                                 /* LEA r1, [r2 + r2*8] */
2910                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2911                                 break;
2912                         case 10:
2913                                 /* LEA r1, [r2 + r2*4] */
2914                                 /* ADD r1, r1          */
2915                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2916                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2917                                 break;
2918                         case 12:
2919                                 /* LEA r1, [r2 + r2*2] */
2920                                 /* SHL r1, 2           */
2921                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2922                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2923                                 break;
2924                         case 25:
2925                                 /* LEA r1, [r2 + r2*4] */
2926                                 /* LEA r1, [r1 + r1*4] */
2927                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2928                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2929                                 break;
2930                         case 100:
2931                                 /* LEA r1, [r2 + r2*4] */
2932                                 /* SHL r1, 2           */
2933                                 /* LEA r1, [r1 + r1*4] */
2934                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2935                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2936                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2937                                 break;
2938                         default:
2939                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2940                                 break;
2941                         }
2942                         break;
2943                 }
2944                 case OP_LDIV:
2945                 case OP_LREM:
2946                         /* Regalloc magic makes the div/rem cases the same */
2947                         if (ins->sreg2 == AMD64_RDX) {
2948                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2949                                 amd64_cdq (code);
2950                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
2951                         } else {
2952                                 amd64_cdq (code);
2953                                 amd64_div_reg (code, ins->sreg2, TRUE);
2954                         }
2955                         break;
2956                 case OP_LDIV_UN:
2957                 case OP_LREM_UN:
2958                         if (ins->sreg2 == AMD64_RDX) {
2959                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2960                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2961                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
2962                         } else {
2963                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2964                                 amd64_div_reg (code, ins->sreg2, FALSE);
2965                         }
2966                         break;
2967                 case OP_IDIV:
2968                 case OP_IREM:
2969                         if (ins->sreg2 == AMD64_RDX) {
2970                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2971                                 amd64_cdq_size (code, 4);
2972                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
2973                         } else {
2974                                 amd64_cdq_size (code, 4);
2975                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2976                         }
2977                         break;
2978                 case OP_IDIV_UN:
2979                 case OP_IREM_UN:
2980                         if (ins->sreg2 == AMD64_RDX) {
2981                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2982                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2983                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
2984                         } else {
2985                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2986                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2987                         }
2988                         break;
2989                 case OP_LMUL_OVF:
2990                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2991                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2992                         break;
2993                 case OP_LOR:
2994                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2995                         break;
2996                 case OP_OR_IMM:
2997                 case OP_LOR_IMM:
2998                         g_assert (amd64_is_imm32 (ins->inst_imm));
2999                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3000                         break;
3001                 case OP_LXOR:
3002                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3003                         break;
3004                 case OP_XOR_IMM:
3005                 case OP_LXOR_IMM:
3006                         g_assert (amd64_is_imm32 (ins->inst_imm));
3007                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3008                         break;
3009                 case OP_LSHL:
3010                         g_assert (ins->sreg2 == AMD64_RCX);
3011                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3012                         break;
3013                 case OP_LSHR:
3014                         g_assert (ins->sreg2 == AMD64_RCX);
3015                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3016                         break;
3017                 case OP_SHR_IMM:
3018                         g_assert (amd64_is_imm32 (ins->inst_imm));
3019                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3020                         break;
3021                 case OP_LSHR_IMM:
3022                         g_assert (amd64_is_imm32 (ins->inst_imm));
3023                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3024                         break;
3025                 case OP_SHR_UN_IMM:
3026                         g_assert (amd64_is_imm32 (ins->inst_imm));
3027                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3028                         break;
3029                 case OP_LSHR_UN_IMM:
3030                         g_assert (amd64_is_imm32 (ins->inst_imm));
3031                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3032                         break;
3033                 case OP_LSHR_UN:
3034                         g_assert (ins->sreg2 == AMD64_RCX);
3035                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3036                         break;
3037                 case OP_SHL_IMM:
3038                         g_assert (amd64_is_imm32 (ins->inst_imm));
3039                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3040                         break;
3041                 case OP_LSHL_IMM:
3042                         g_assert (amd64_is_imm32 (ins->inst_imm));
3043                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3044                         break;
3045
3046                 case OP_IADDCC:
3047                 case OP_IADD:
3048                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3049                         break;
3050                 case OP_IADC:
3051                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3052                         break;
3053                 case OP_IADD_IMM:
3054                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3055                         break;
3056                 case OP_IADC_IMM:
3057                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3058                         break;
3059                 case OP_ISUBCC:
3060                 case OP_ISUB:
3061                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3062                         break;
3063                 case OP_ISBB:
3064                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3065                         break;
3066                 case OP_ISUB_IMM:
3067                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3068                         break;
3069                 case OP_ISBB_IMM:
3070                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3071                         break;
3072                 case OP_IAND:
3073                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3074                         break;
3075                 case OP_IAND_IMM:
3076                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3077                         break;
3078                 case OP_IOR:
3079                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3080                         break;
3081                 case OP_IOR_IMM:
3082                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3083                         break;
3084                 case OP_IXOR:
3085                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3086                         break;
3087                 case OP_IXOR_IMM:
3088                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3089                         break;
3090                 case OP_INEG:
3091                         amd64_neg_reg_size (code, ins->sreg1, 4);
3092                         break;
3093                 case OP_INOT:
3094                         amd64_not_reg_size (code, ins->sreg1, 4);
3095                         break;
3096                 case OP_ISHL:
3097                         g_assert (ins->sreg2 == AMD64_RCX);
3098                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3099                         break;
3100                 case OP_ISHR:
3101                         g_assert (ins->sreg2 == AMD64_RCX);
3102                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3103                         break;
3104                 case OP_ISHR_IMM:
3105                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3106                         break;
3107                 case OP_ISHR_UN_IMM:
3108                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3109                         break;
3110                 case OP_ISHR_UN:
3111                         g_assert (ins->sreg2 == AMD64_RCX);
3112                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3113                         break;
3114                 case OP_ISHL_IMM:
3115                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3116                         break;
3117                 case OP_IMUL:
3118                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3119                         break;
3120                 case OP_IMUL_OVF:
3121                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3122                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3123                         break;
3124                 case OP_IMUL_OVF_UN:
3125                 case OP_LMUL_OVF_UN: {
3126                         /* the mul operation and the exception check should most likely be split */
3127                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3128                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3129                         /*g_assert (ins->sreg2 == X86_EAX);
3130                         g_assert (ins->dreg == X86_EAX);*/
3131                         if (ins->sreg2 == X86_EAX) {
3132                                 non_eax_reg = ins->sreg1;
3133                         } else if (ins->sreg1 == X86_EAX) {
3134                                 non_eax_reg = ins->sreg2;
3135                         } else {
3136                                 /* no need to save since we're going to store to it anyway */
3137                                 if (ins->dreg != X86_EAX) {
3138                                         saved_eax = TRUE;
3139                                         amd64_push_reg (code, X86_EAX);
3140                                 }
3141                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3142                                 non_eax_reg = ins->sreg2;
3143                         }
3144                         if (ins->dreg == X86_EDX) {
3145                                 if (!saved_eax) {
3146                                         saved_eax = TRUE;
3147                                         amd64_push_reg (code, X86_EAX);
3148                                 }
3149                         } else {
3150                                 saved_edx = TRUE;
3151                                 amd64_push_reg (code, X86_EDX);
3152                         }
3153                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3154                         /* save before the check since pop and mov don't change the flags */
3155                         if (ins->dreg != X86_EAX)
3156                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3157                         if (saved_edx)
3158                                 amd64_pop_reg (code, X86_EDX);
3159                         if (saved_eax)
3160                                 amd64_pop_reg (code, X86_EAX);
3161                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3162                         break;
3163                 }
3164                 case OP_ICOMPARE:
3165                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3166                         break;
3167                 case OP_ICOMPARE_IMM:
3168                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3169                         break;
3170                 case OP_IBEQ:
3171                 case OP_IBLT:
3172                 case OP_IBGT:
3173                 case OP_IBGE:
3174                 case OP_IBLE:
3175                 case OP_LBEQ:
3176                 case OP_LBLT:
3177                 case OP_LBGT:
3178                 case OP_LBGE:
3179                 case OP_LBLE:
3180                 case OP_IBNE_UN:
3181                 case OP_IBLT_UN:
3182                 case OP_IBGT_UN:
3183                 case OP_IBGE_UN:
3184                 case OP_IBLE_UN:
3185                 case OP_LBNE_UN:
3186                 case OP_LBLT_UN:
3187                 case OP_LBGT_UN:
3188                 case OP_LBGE_UN:
3189                 case OP_LBLE_UN:
3190                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3191                         break;
3192
3193                 case OP_LNOT:
3194                         amd64_not_reg (code, ins->sreg1);
3195                         break;
3196                 case OP_LNEG:
3197                         amd64_neg_reg (code, ins->sreg1);
3198                         break;
3199
3200                 case OP_ICONST:
3201                 case OP_I8CONST:
3202                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3203                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3204                         else
3205                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3206                         break;
3207                 case OP_AOTCONST:
3208                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3209                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3210                         break;
3211                 case OP_MOVE:
3212                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3213                         break;
3214                 case OP_AMD64_SET_XMMREG_R4: {
3215                         if (use_sse2) {
3216                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3217                         }
3218                         else {
3219                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
3220                                 /* ins->dreg is set to -1 by the reg allocator */
3221                                 amd64_movss_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
3222                         }
3223                         break;
3224                 }
3225                 case OP_AMD64_SET_XMMREG_R8: {
3226                         if (use_sse2) {
3227                                 if (ins->dreg != ins->sreg1)
3228                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3229                         }
3230                         else {
3231                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
3232                                 /* ins->dreg is set to -1 by the reg allocator */
3233                                 amd64_movsd_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
3234                         }
3235                         break;
3236                 }
3237                 case OP_JMP: {
3238                         /*
3239                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3240                          * Keep in sync with the code in emit_epilog.
3241                          */
3242                         int pos = 0, i;
3243
3244                         /* FIXME: no tracing support... */
3245                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3246                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3247
3248                         g_assert (!cfg->method->save_lmf);
3249
3250                         code = emit_load_volatile_arguments (cfg, code);
3251
3252                         if (cfg->arch.omit_fp) {
3253                                 guint32 save_offset = 0;
3254                                 /* Pop callee-saved registers */
3255                                 for (i = 0; i < AMD64_NREG; ++i)
3256                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3257                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3258                                                 save_offset += 8;
3259                                         }
3260                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3261                         }
3262                         else {
3263                                 for (i = 0; i < AMD64_NREG; ++i)
3264                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3265                                                 pos -= sizeof (gpointer);
3266
3267                                 if (pos)
3268                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3269
3270                                 /* Pop registers in reverse order */
3271                                 for (i = AMD64_NREG - 1; i > 0; --i)
3272                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3273                                                 amd64_pop_reg (code, i);
3274                                         }
3275
3276                                 amd64_leave (code);
3277                         }
3278
3279                         offset = code - cfg->native_code;
3280                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3281                         if (cfg->compile_aot)
3282                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3283                         else
3284                                 amd64_set_reg_template (code, AMD64_R11);
3285                         amd64_jump_reg (code, AMD64_R11);
3286                         break;
3287                 }
3288                 case OP_CHECK_THIS:
3289                         /* ensure ins->sreg1 is not NULL */
3290                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3291                         break;
3292                 case OP_ARGLIST: {
3293                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3294                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3295                         break;
3296                 }
3297                 case OP_FCALL:
3298                 case OP_LCALL:
3299                 case OP_VCALL:
3300                 case OP_VOIDCALL:
3301                 case OP_CALL:
3302                         call = (MonoCallInst*)ins;
3303                         /*
3304                          * The AMD64 ABI forces callers to know about varargs.
3305                          */
3306                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3307                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3308                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3309                                 /*
3310                                  * Since the unmanaged calling convention doesn't contain a
3311                                  * 'vararg' entry, we have to treat every pinvoke call as a
3312                                  * potential vararg call.
3313                                  */
3314                                 guint32 nregs, i;
3315                                 nregs = 0;
3316                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3317                                         if (call->used_fregs & (1 << i))
3318                                                 nregs ++;
3319                                 if (!nregs)
3320                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3321                                 else
3322                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3323                         }
3324
3325                         if (ins->flags & MONO_INST_HAS_METHOD)
3326                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3327                         else
3328                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3329                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3330                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3331                         code = emit_move_return_value (cfg, ins, code);
3332                         break;
3333                 case OP_FCALL_REG:
3334                 case OP_LCALL_REG:
3335                 case OP_VCALL_REG:
3336                 case OP_VOIDCALL_REG:
3337                 case OP_CALL_REG:
3338                         call = (MonoCallInst*)ins;
3339
3340                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3341                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3342                                 ins->sreg1 = AMD64_R11;
3343                         }
3344
3345                         /*
3346                          * The AMD64 ABI forces callers to know about varargs.
3347                          */
3348                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3349                                 if (ins->sreg1 == AMD64_RAX) {
3350                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3351                                         ins->sreg1 = AMD64_R11;
3352                                 }
3353                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3354                         }
3355                         amd64_call_reg (code, ins->sreg1);
3356                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3357                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3358                         code = emit_move_return_value (cfg, ins, code);
3359                         break;
3360                 case OP_FCALL_MEMBASE:
3361                 case OP_LCALL_MEMBASE:
3362                 case OP_VCALL_MEMBASE:
3363                 case OP_VOIDCALL_MEMBASE:
3364                 case OP_CALL_MEMBASE:
3365                         call = (MonoCallInst*)ins;
3366
3367                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3368                                 /*
3369                                  * Can't use R11 because it is clobbered by the trampoline
3370                                  * code, and the reg value is needed by get_vcall_slot_addr.
3371                                  */
3372                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3373                                 ins->sreg1 = AMD64_RAX;
3374                         }
3375
3376                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3377                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3378                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3379                         code = emit_move_return_value (cfg, ins, code);
3380                         break;
3381                 case OP_AMD64_SAVE_SP_TO_LMF:
3382                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3383                         break;
3384                 case OP_OUTARG:
3385                 case OP_X86_PUSH:
3386                         amd64_push_reg (code, ins->sreg1);
3387                         break;
3388                 case OP_X86_PUSH_IMM:
3389                         g_assert (amd64_is_imm32 (ins->inst_imm));
3390                         amd64_push_imm (code, ins->inst_imm);
3391                         break;
3392                 case OP_X86_PUSH_MEMBASE:
3393                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3394                         break;
3395                 case OP_X86_PUSH_OBJ:
3396                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3397                         amd64_push_reg (code, AMD64_RDI);
3398                         amd64_push_reg (code, AMD64_RSI);
3399                         amd64_push_reg (code, AMD64_RCX);
3400                         if (ins->inst_offset)
3401                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3402                         else
3403                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3404                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3405                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3406                         amd64_cld (code);
3407                         amd64_prefix (code, X86_REP_PREFIX);
3408                         amd64_movsd (code);
3409                         amd64_pop_reg (code, AMD64_RCX);
3410                         amd64_pop_reg (code, AMD64_RSI);
3411                         amd64_pop_reg (code, AMD64_RDI);
3412                         break;
3413                 case OP_X86_LEA:
3414                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3415                         break;
3416                 case OP_X86_LEA_MEMBASE:
3417                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3418                         break;
3419                 case OP_X86_XCHG:
3420                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3421                         break;
3422                 case OP_LOCALLOC:
3423                         /* keep alignment */
3424                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3425                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3426                         code = mono_emit_stack_alloc (code, ins);
3427                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3428                         break;
3429                 case OP_LOCALLOC_IMM: {
3430                         guint32 size = ins->inst_imm;
3431                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3432
3433                         if (ins->flags & MONO_INST_INIT) {
3434                                 /* FIXME: Optimize this */
3435                                 amd64_mov_reg_imm (code, ins->dreg, size);
3436                                 ins->sreg1 = ins->dreg;
3437
3438                                 code = mono_emit_stack_alloc (code, ins);
3439                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3440                         } else {
3441                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3442                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3443                         }
3444                         break;
3445                 }
3446                 case OP_THROW: {
3447                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3448                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3449                                              (gpointer)"mono_arch_throw_exception");
3450                         break;
3451                 }
3452                 case OP_RETHROW: {
3453                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3454                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3455                                              (gpointer)"mono_arch_rethrow_exception");
3456                         break;
3457                 }
3458                 case OP_CALL_HANDLER:
3459                         /* Align stack */
3460                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3461                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3462                         amd64_call_imm (code, 0);
3463                         /* Restore stack alignment */
3464                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3465                         break;
3466                 case OP_START_HANDLER: {
3467                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3468                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3469                         break;
3470                 }
3471                 case OP_ENDFINALLY: {
3472                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3473                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3474                         amd64_ret (code);
3475                         break;
3476                 }
3477                 case OP_ENDFILTER: {
3478                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3479                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3480                         /* The local allocator will put the result into RAX */
3481                         amd64_ret (code);
3482                         break;
3483                 }
3484
3485                 case OP_LABEL:
3486                         ins->inst_c0 = code - cfg->native_code;
3487                         break;
3488                 case OP_BR:
3489                         if (ins->flags & MONO_INST_BRLABEL) {
3490                                 if (ins->inst_i0->inst_c0) {
3491                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3492                                 } else {
3493                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3494                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3495                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3496                                                 x86_jump8 (code, 0);
3497                                         else
3498                                                 x86_jump32 (code, 0);
3499                                 }
3500                         } else {
3501                                 if (ins->inst_target_bb->native_offset) {
3502                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3503                                 } else {
3504                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3505                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3506                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3507                                                 x86_jump8 (code, 0);
3508                                         else
3509                                                 x86_jump32 (code, 0);
3510                                 }
3511                         }
3512                         break;
3513                 case OP_BR_REG:
3514                         amd64_jump_reg (code, ins->sreg1);
3515                         break;
3516                 case OP_CEQ:
3517                 case OP_LCEQ:
3518                 case OP_ICEQ:
3519                 case OP_CLT:
3520                 case OP_LCLT:
3521                 case OP_ICLT:
3522                 case OP_CGT:
3523                 case OP_ICGT:
3524                 case OP_LCGT:
3525                 case OP_CLT_UN:
3526                 case OP_LCLT_UN:
3527                 case OP_ICLT_UN:
3528                 case OP_CGT_UN:
3529                 case OP_LCGT_UN:
3530                 case OP_ICGT_UN:
3531                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3532                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3533                         break;
3534                 case OP_COND_EXC_EQ:
3535                 case OP_COND_EXC_NE_UN:
3536                 case OP_COND_EXC_LT:
3537                 case OP_COND_EXC_LT_UN:
3538                 case OP_COND_EXC_GT:
3539                 case OP_COND_EXC_GT_UN:
3540                 case OP_COND_EXC_GE:
3541                 case OP_COND_EXC_GE_UN:
3542                 case OP_COND_EXC_LE:
3543                 case OP_COND_EXC_LE_UN:
3544                 case OP_COND_EXC_IEQ:
3545                 case OP_COND_EXC_INE_UN:
3546                 case OP_COND_EXC_ILT:
3547                 case OP_COND_EXC_ILT_UN:
3548                 case OP_COND_EXC_IGT:
3549                 case OP_COND_EXC_IGT_UN:
3550                 case OP_COND_EXC_IGE:
3551                 case OP_COND_EXC_IGE_UN:
3552                 case OP_COND_EXC_ILE:
3553                 case OP_COND_EXC_ILE_UN:
3554                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3555                         break;
3556                 case OP_COND_EXC_OV:
3557                 case OP_COND_EXC_NO:
3558                 case OP_COND_EXC_C:
3559                 case OP_COND_EXC_NC:
3560                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3561                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3562                         break;
3563                 case OP_COND_EXC_IOV:
3564                 case OP_COND_EXC_INO:
3565                 case OP_COND_EXC_IC:
3566                 case OP_COND_EXC_INC:
3567                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3568                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3569                         break;
3570
3571                 /* floating point opcodes */
3572                 case OP_R8CONST: {
3573                         double d = *(double *)ins->inst_p0;
3574
3575                         if (use_sse2) {
3576                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3577                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3578                                 }
3579                                 else {
3580                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3581                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3582                                 }
3583                         }
3584                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3585                                 amd64_fldz (code);
3586                         } else if (d == 1.0) {
3587                                 x86_fld1 (code);
3588                         } else {
3589                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3590                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3591                         }
3592                         break;
3593                 }
3594                 case OP_R4CONST: {
3595                         float f = *(float *)ins->inst_p0;
3596
3597                         if (use_sse2) {
3598                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3599                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3600                                 }
3601                                 else {
3602                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3603                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3604                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3605                                 }
3606                         }
3607                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3608                                 amd64_fldz (code);
3609                         } else if (f == 1.0) {
3610                                 x86_fld1 (code);
3611                         } else {
3612                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3613                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3614                         }
3615                         break;
3616                 }
3617                 case OP_STORER8_MEMBASE_REG:
3618                         if (use_sse2)
3619                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3620                         else
3621                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3622                         break;
3623                 case OP_LOADR8_SPILL_MEMBASE:
3624                         if (use_sse2)
3625                                 g_assert_not_reached ();
3626                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3627                         amd64_fxch (code, 1);
3628                         break;
3629                 case OP_LOADR8_MEMBASE:
3630                         if (use_sse2)
3631                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3632                         else
3633                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3634                         break;
3635                 case OP_STORER4_MEMBASE_REG:
3636                         if (use_sse2) {
3637                                 /* This requires a double->single conversion */
3638                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3639                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3640                         }
3641                         else
3642                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3643                         break;
3644                 case OP_LOADR4_MEMBASE:
3645                         if (use_sse2) {
3646                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3647                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3648                         }
3649                         else
3650                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3651                         break;
3652                 case OP_ICONV_TO_R4: /* FIXME: change precision */
3653                 case OP_ICONV_TO_R8:
3654                         if (use_sse2)
3655                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3656                         else {
3657                                 amd64_push_reg (code, ins->sreg1);
3658                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3659                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3660                         }
3661                         break;
3662                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3663                 case OP_LCONV_TO_R8:
3664                         if (use_sse2)
3665                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3666                         else {
3667                                 amd64_push_reg (code, ins->sreg1);
3668                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3669                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3670                         }
3671                         break;
3672                 case OP_X86_FP_LOAD_I8:
3673                         if (use_sse2)
3674                                 g_assert_not_reached ();
3675                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3676                         break;
3677                 case OP_X86_FP_LOAD_I4:
3678                         if (use_sse2)
3679                                 g_assert_not_reached ();
3680                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3681                         break;
3682                 case OP_FCONV_TO_R4:
3683                         /* FIXME: nothing to do ?? */
3684                         break;
3685                 case OP_FCONV_TO_I1:
3686                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3687                         break;
3688                 case OP_FCONV_TO_U1:
3689                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3690                         break;
3691                 case OP_FCONV_TO_I2:
3692                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3693                         break;
3694                 case OP_FCONV_TO_U2:
3695                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3696                         break;
3697                 case OP_FCONV_TO_U4:
3698                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3699                         break;
3700                 case OP_FCONV_TO_I4:
3701                 case OP_FCONV_TO_I:
3702                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3703                         break;
3704                 case OP_FCONV_TO_I8:
3705                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3706                         break;
3707                 case OP_LCONV_TO_R_UN: {
3708                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3709                         guint8 *br [2];
3710
3711                         if (use_sse2) {
3712                                 /* Based on gcc code */
3713                                 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3714                                 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3715
3716                                 /* Positive case */
3717                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3718                                 br [1] = code; x86_jump8 (code, 0);
3719                                 amd64_patch (br [0], code);
3720
3721                                 /* Negative case */
3722                                 /* Save to the red zone */
3723                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3724                                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3725                                 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3726                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3727                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3728                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3729                                 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3730                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3731                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3732                                 /* Restore */
3733                                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3734                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3735                                 amd64_patch (br [1], code);
3736
3737                                 break;
3738                         }
3739
3740                         /* load 64bit integer to FP stack */
3741                         amd64_push_imm (code, 0);
3742                         amd64_push_reg (code, ins->sreg2);
3743                         amd64_push_reg (code, ins->sreg1);
3744                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3745                         /* store as 80bit FP value */
3746                         x86_fst80_membase (code, AMD64_RSP, 0);
3747
3748                         /* test if lreg is negative */
3749                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3750                         br [0] = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3751
3752                         /* add correction constant mn */
3753                         x86_fld80_mem (code, (gssize)mn);
3754                         x86_fld80_membase (code, AMD64_RSP, 0);
3755                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3756                         x86_fst80_membase (code, AMD64_RSP, 0);
3757
3758                         amd64_patch (br [0], code);
3759
3760                         x86_fld80_membase (code, AMD64_RSP, 0);
3761                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3762
3763                         break;
3764                 }
3765                 case OP_LCONV_TO_OVF_U4:
3766                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3767                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3768                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3769                         break;
3770                 case OP_LCONV_TO_OVF_I4_UN:
3771                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3772                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3773                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3774                         break;
3775                 case OP_FMOVE:
3776                         if (use_sse2 && (ins->dreg != ins->sreg1))
3777                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3778                         break;
3779                 case OP_FADD:
3780                         if (use_sse2)
3781                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3782                         else
3783                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3784                         break;
3785                 case OP_FSUB:
3786                         if (use_sse2)
3787                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3788                         else
3789                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3790                         break;
3791                 case OP_FMUL:
3792                         if (use_sse2)
3793                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3794                         else
3795                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3796                         break;
3797                 case OP_FDIV:
3798                         if (use_sse2)
3799                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3800                         else
3801                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3802                         break;
3803                 case OP_FNEG:
3804                         if (use_sse2) {
3805                                 static double r8_0 = -0.0;
3806
3807                                 g_assert (ins->sreg1 == ins->dreg);
3808
3809                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3810                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3811                         }
3812                         else
3813                                 amd64_fchs (code);
3814                         break;
3815                 case OP_SIN:
3816                         if (use_sse2) {
3817                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3818                         }
3819                         else {
3820                                 amd64_fsin (code);
3821                                 amd64_fldz (code);
3822                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3823                         }
3824                         break;
3825                 case OP_COS:
3826                         if (use_sse2) {
3827                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3828                         }
3829                         else {
3830                                 amd64_fcos (code);
3831                                 amd64_fldz (code);
3832                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3833                         }
3834                         break;
3835                 case OP_ABS:
3836                         if (use_sse2) {
3837                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3838                         }
3839                         else
3840                                 amd64_fabs (code);
3841                         break;
3842                 case OP_TAN: {
3843                         /*
3844                          * it really doesn't make sense to inline all this code,
3845                          * it's here just to show that things may not be as simple
3846                          * as they appear.
3847                          */
3848                         guchar *check_pos, *end_tan, *pop_jump;
3849                         if (use_sse2)
3850                                 g_assert_not_reached ();
3851                         amd64_push_reg (code, AMD64_RAX);
3852                         amd64_fptan (code);
3853                         amd64_fnstsw (code);
3854                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3855                         check_pos = code;
3856                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3857                         amd64_fstp (code, 0); /* pop the 1.0 */
3858                         end_tan = code;
3859                         x86_jump8 (code, 0);
3860                         amd64_fldpi (code);
3861                         amd64_fp_op (code, X86_FADD, 0);
3862                         amd64_fxch (code, 1);
3863                         x86_fprem1 (code);
3864                         amd64_fstsw (code);
3865                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3866                         pop_jump = code;
3867                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3868                         amd64_fstp (code, 1);
3869                         amd64_fptan (code);
3870                         amd64_patch (pop_jump, code);
3871                         amd64_fstp (code, 0); /* pop the 1.0 */
3872                         amd64_patch (check_pos, code);
3873                         amd64_patch (end_tan, code);
3874                         amd64_fldz (code);
3875                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3876                         amd64_pop_reg (code, AMD64_RAX);
3877                         break;
3878                 }
3879                 case OP_ATAN:
3880                         if (use_sse2)
3881                                 g_assert_not_reached ();
3882                         x86_fld1 (code);
3883                         amd64_fpatan (code);
3884                         amd64_fldz (code);
3885                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3886                         break;
3887                 case OP_SQRT:
3888                         if (use_sse2) {
3889                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3890                         }
3891                         else
3892                                 amd64_fsqrt (code);
3893                         break;
3894                 case OP_IMIN:
3895                         g_assert (cfg->opt & MONO_OPT_CMOV);
3896                         g_assert (ins->dreg == ins->sreg1);
3897                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3898                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3899                         break;
3900                 case OP_IMAX:
3901                         g_assert (cfg->opt & MONO_OPT_CMOV);
3902                         g_assert (ins->dreg == ins->sreg1);
3903                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3904                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3905                         break;
3906                 case OP_LMIN:
3907                         g_assert (cfg->opt & MONO_OPT_CMOV);
3908                         g_assert (ins->dreg == ins->sreg1);
3909                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3910                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3911                         break;
3912                 case OP_LMAX:
3913                         g_assert (cfg->opt & MONO_OPT_CMOV);
3914                         g_assert (ins->dreg == ins->sreg1);
3915                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3916                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3917                         break;
3918                 case OP_X86_FPOP:
3919                         if (!use_sse2)
3920                                 amd64_fstp (code, 0);
3921                         break;
3922                 case OP_FREM: {
3923                         guint8 *l1, *l2;
3924
3925                         if (use_sse2)
3926                                 g_assert_not_reached ();
3927                         amd64_push_reg (code, AMD64_RAX);
3928                         /* we need to exchange ST(0) with ST(1) */
3929                         amd64_fxch (code, 1);
3930
3931                         /* this requires a loop, because fprem somtimes
3932                          * returns a partial remainder */
3933                         l1 = code;
3934                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3935                         /* x86_fprem1 (code); */
3936                         amd64_fprem (code);
3937                         amd64_fnstsw (code);
3938                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3939                         l2 = code + 2;
3940                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3941
3942                         /* pop result */
3943                         amd64_fstp (code, 1);
3944
3945                         amd64_pop_reg (code, AMD64_RAX);
3946                         break;
3947                 }
3948                 case OP_FCOMPARE:
3949                         if (use_sse2) {
3950                                 /*
3951                                  * The two arguments are swapped because the fbranch instructions
3952                                  * depend on this for the non-sse case to work.
3953                                  */
3954                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3955                                 break;
3956                         }
3957                         if (cfg->opt & MONO_OPT_FCMOV) {
3958                                 amd64_fcomip (code, 1);
3959                                 amd64_fstp (code, 0);
3960                                 break;
3961                         }
3962                         /* this overwrites EAX */
3963                         EMIT_FPCOMPARE(code);
3964                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3965                         break;
3966                 case OP_FCEQ:
3967                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3968                                 /* zeroing the register at the start results in
3969                                  * shorter and faster code (we can also remove the widening op)
3970                                  */
3971                                 guchar *unordered_check;
3972                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3973
3974                                 if (use_sse2)
3975                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3976                                 else {
3977                                         amd64_fcomip (code, 1);
3978                                         amd64_fstp (code, 0);
3979                                 }
3980                                 unordered_check = code;
3981                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3982                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3983                                 amd64_patch (unordered_check, code);
3984                                 break;
3985                         }
3986                         if (ins->dreg != AMD64_RAX)
3987                                 amd64_push_reg (code, AMD64_RAX);
3988
3989                         EMIT_FPCOMPARE(code);
3990                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3991                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3992                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3993                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3994
3995                         if (ins->dreg != AMD64_RAX)
3996                                 amd64_pop_reg (code, AMD64_RAX);
3997                         break;
3998                 case OP_FCLT:
3999                 case OP_FCLT_UN:
4000                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4001                                 /* zeroing the register at the start results in
4002                                  * shorter and faster code (we can also remove the widening op)
4003                                  */
4004                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4005                                 if (use_sse2)
4006                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4007                                 else {
4008                                         amd64_fcomip (code, 1);
4009                                         amd64_fstp (code, 0);
4010                                 }
4011                                 if (ins->opcode == OP_FCLT_UN) {
4012                                         guchar *unordered_check = code;
4013                                         guchar *jump_to_end;
4014                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4015                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4016                                         jump_to_end = code;
4017                                         x86_jump8 (code, 0);
4018                                         amd64_patch (unordered_check, code);
4019                                         amd64_inc_reg (code, ins->dreg);
4020                                         amd64_patch (jump_to_end, code);
4021                                 } else {
4022                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4023                                 }
4024                                 break;
4025                         }
4026                         if (ins->dreg != AMD64_RAX)
4027                                 amd64_push_reg (code, AMD64_RAX);
4028
4029                         EMIT_FPCOMPARE(code);
4030                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
4031                         if (ins->opcode == OP_FCLT_UN) {
4032                                 guchar *is_not_zero_check, *end_jump;
4033                                 is_not_zero_check = code;
4034                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4035                                 end_jump = code;
4036                                 x86_jump8 (code, 0);
4037                                 amd64_patch (is_not_zero_check, code);
4038                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4039
4040                                 amd64_patch (end_jump, code);
4041                         }
4042                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4043                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4044
4045                         if (ins->dreg != AMD64_RAX)
4046                                 amd64_pop_reg (code, AMD64_RAX);
4047                         break;
4048                 case OP_FCGT:
4049                 case OP_FCGT_UN:
4050                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4051                                 /* zeroing the register at the start results in
4052                                  * shorter and faster code (we can also remove the widening op)
4053                                  */
4054                                 guchar *unordered_check;
4055                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4056                                 if (use_sse2)
4057                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4058                                 else {
4059                                         amd64_fcomip (code, 1);
4060                                         amd64_fstp (code, 0);
4061                                 }
4062                                 if (ins->opcode == OP_FCGT) {
4063                                         unordered_check = code;
4064                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4065                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4066                                         amd64_patch (unordered_check, code);
4067                                 } else {
4068                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4069                                 }
4070                                 break;
4071                         }
4072                         if (ins->dreg != AMD64_RAX)
4073                                 amd64_push_reg (code, AMD64_RAX);
4074
4075                         EMIT_FPCOMPARE(code);
4076                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
4077                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4078                         if (ins->opcode == OP_FCGT_UN) {
4079                                 guchar *is_not_zero_check, *end_jump;
4080                                 is_not_zero_check = code;
4081                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4082                                 end_jump = code;
4083                                 x86_jump8 (code, 0);
4084                                 amd64_patch (is_not_zero_check, code);
4085                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4086
4087                                 amd64_patch (end_jump, code);
4088                         }
4089                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4090                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4091
4092                         if (ins->dreg != AMD64_RAX)
4093                                 amd64_pop_reg (code, AMD64_RAX);
4094                         break;
4095                 case OP_FCLT_MEMBASE:
4096                 case OP_FCGT_MEMBASE:
4097                 case OP_FCLT_UN_MEMBASE:
4098                 case OP_FCGT_UN_MEMBASE:
4099                 case OP_FCEQ_MEMBASE: {
4100                         guchar *unordered_check, *jump_to_end;
4101                         int x86_cond;
4102                         g_assert (use_sse2);
4103
4104                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4105                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4106
4107                         switch (ins->opcode) {
4108                         case OP_FCEQ_MEMBASE:
4109                                 x86_cond = X86_CC_EQ;
4110                                 break;
4111                         case OP_FCLT_MEMBASE:
4112                         case OP_FCLT_UN_MEMBASE:
4113                                 x86_cond = X86_CC_LT;
4114                                 break;
4115                         case OP_FCGT_MEMBASE:
4116                         case OP_FCGT_UN_MEMBASE:
4117                                 x86_cond = X86_CC_GT;
4118                                 break;
4119                         default:
4120                                 g_assert_not_reached ();
4121                         }
4122
4123                         unordered_check = code;
4124                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4125                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4126
4127                         switch (ins->opcode) {
4128                         case OP_FCEQ_MEMBASE:
4129                         case OP_FCLT_MEMBASE:
4130                         case OP_FCGT_MEMBASE:
4131                                 amd64_patch (unordered_check, code);
4132                                 break;
4133                         case OP_FCLT_UN_MEMBASE:
4134                         case OP_FCGT_UN_MEMBASE:
4135                                 jump_to_end = code;
4136                                 x86_jump8 (code, 0);
4137                                 amd64_patch (unordered_check, code);
4138                                 amd64_inc_reg (code, ins->dreg);
4139                                 amd64_patch (jump_to_end, code);
4140                                 break;
4141                         default:
4142                                 break;
4143                         }
4144                         break;
4145                 }
4146                 case OP_FBEQ:
4147                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4148                                 guchar *jump = code;
4149                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
4150                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4151                                 amd64_patch (jump, code);
4152                                 break;
4153                         }
4154                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
4155                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4156                         break;
4157                 case OP_FBNE_UN:
4158                         /* Branch if C013 != 100 */
4159                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4160                                 /* branch if !ZF or (PF|CF) */
4161                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4162                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4163                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4164                                 break;
4165                         }
4166                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
4167                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4168                         break;
4169                 case OP_FBLT:
4170                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4171                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4172                                 break;
4173                         }
4174                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4175                         break;
4176                 case OP_FBLT_UN:
4177                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4178                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4179                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4180                                 break;
4181                         }
4182                         if (ins->opcode == OP_FBLT_UN) {
4183                                 guchar *is_not_zero_check, *end_jump;
4184                                 is_not_zero_check = code;
4185                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4186                                 end_jump = code;
4187                                 x86_jump8 (code, 0);
4188                                 amd64_patch (is_not_zero_check, code);
4189                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4190
4191                                 amd64_patch (end_jump, code);
4192                         }
4193                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4194                         break;
4195                 case OP_FBGT:
4196                 case OP_FBGT_UN:
4197                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4198                                 if (ins->opcode == OP_FBGT) {
4199                                         guchar *br1;
4200
4201                                         /* skip branch if C1=1 */
4202                                         br1 = code;
4203                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4204                                         /* branch if (C0 | C3) = 1 */
4205                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4206                                         amd64_patch (br1, code);
4207                                         break;
4208                                 } else {
4209                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4210                                 }
4211                                 break;
4212                         }
4213                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4214                         if (ins->opcode == OP_FBGT_UN) {
4215                                 guchar *is_not_zero_check, *end_jump;
4216                                 is_not_zero_check = code;
4217                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4218                                 end_jump = code;
4219                                 x86_jump8 (code, 0);
4220                                 amd64_patch (is_not_zero_check, code);
4221                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4222
4223                                 amd64_patch (end_jump, code);
4224                         }
4225                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4226                         break;
4227                 case OP_FBGE:
4228                         /* Branch if C013 == 100 or 001 */
4229                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4230                                 guchar *br1;
4231
4232                                 /* skip branch if C1=1 */
4233                                 br1 = code;
4234                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4235                                 /* branch if (C0 | C3) = 1 */
4236                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4237                                 amd64_patch (br1, code);
4238                                 break;
4239                         }
4240                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4241                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4242                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
4243                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4244                         break;
4245                 case OP_FBGE_UN:
4246                         /* Branch if C013 == 000 */
4247                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4248                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4249                                 break;
4250                         }
4251                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4252                         break;
4253                 case OP_FBLE:
4254                         /* Branch if C013=000 or 100 */
4255                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4256                                 guchar *br1;
4257
4258                                 /* skip branch if C1=1 */
4259                                 br1 = code;
4260                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4261                                 /* branch if C0=0 */
4262                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4263                                 amd64_patch (br1, code);
4264                                 break;
4265                         }
4266                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
4267                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4268                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4269                         break;
4270                 case OP_FBLE_UN:
4271                         /* Branch if C013 != 001 */
4272                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4273                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4274                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4275                                 break;
4276                         }
4277                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4278                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4279                         break;
4280                 case OP_CKFINITE:
4281                         if (use_sse2) {
4282                                 /* Transfer value to the fp stack */
4283                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4284                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4285                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4286                         }
4287                         amd64_push_reg (code, AMD64_RAX);
4288                         amd64_fxam (code);
4289                         amd64_fnstsw (code);
4290                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4291                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4292                         amd64_pop_reg (code, AMD64_RAX);
4293                         if (use_sse2) {
4294                                 amd64_fstp (code, 0);
4295                         }
4296                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4297                         if (use_sse2)
4298                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4299                         break;
4300                 case OP_TLS_GET: {
4301                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4302                         break;
4303                 }
4304                 case OP_MEMORY_BARRIER: {
4305                         /* Not needed on amd64 */
4306                         break;
4307                 }
4308                 case OP_ATOMIC_ADD_I4:
4309                 case OP_ATOMIC_ADD_I8: {
4310                         int dreg = ins->dreg;
4311                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4312
4313                         if (dreg == ins->inst_basereg)
4314                                 dreg = AMD64_R11;
4315
4316                         if (dreg != ins->sreg2)
4317                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4318
4319                         x86_prefix (code, X86_LOCK_PREFIX);
4320                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4321
4322                         if (dreg != ins->dreg)
4323                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4324
4325                         break;
4326                 }
4327                 case OP_ATOMIC_ADD_NEW_I4:
4328                 case OP_ATOMIC_ADD_NEW_I8: {
4329                         int dreg = ins->dreg;
4330                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4331
4332                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4333                                 dreg = AMD64_R11;
4334
4335                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4336                         amd64_prefix (code, X86_LOCK_PREFIX);
4337                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4338                         /* dreg contains the old value, add with sreg2 value */
4339                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4340
4341                         if (ins->dreg != dreg)
4342                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4343
4344                         break;
4345                 }
4346                 case OP_ATOMIC_EXCHANGE_I4:
4347                 case OP_ATOMIC_EXCHANGE_I8: {
4348                         guchar *br[2];
4349                         int sreg2 = ins->sreg2;
4350                         int breg = ins->inst_basereg;
4351                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
4352
4353                         /*
4354                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
4355                          * an explanation of how this works.
4356                          */
4357
4358                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4359                          * hack to overcome limits in x86 reg allocator
4360                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4361                          */
4362                         /* The pushes invalidate rsp */
4363                         if ((breg == AMD64_RAX) || (breg == AMD64_RSP)) {
4364                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4365                                 breg = AMD64_R11;
4366                         }
4367
4368                         if (ins->dreg != AMD64_RAX)
4369                                 amd64_push_reg (code, AMD64_RAX);
4370
4371                         /* We need the EAX reg for the cmpxchg */
4372                         if (ins->sreg2 == AMD64_RAX) {
4373                                 amd64_push_reg (code, AMD64_RDX);
4374                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4375                                 sreg2 = AMD64_RDX;
4376                         }
4377
4378                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4379
4380                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4381                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4382                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4383                         amd64_patch (br [1], br [0]);
4384
4385                         if (ins->dreg != AMD64_RAX) {
4386                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4387                                 amd64_pop_reg (code, AMD64_RAX);
4388                         }
4389
4390                         if (ins->sreg2 != sreg2)
4391                                 amd64_pop_reg (code, AMD64_RDX);
4392
4393                         break;
4394                 }
4395                 default:
4396                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4397                         g_assert_not_reached ();
4398                 }
4399
4400                 if ((code - cfg->native_code - offset) > max_len) {
4401                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4402                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4403                         g_assert_not_reached ();
4404                 }
4405
4406                 cpos += max_len;
4407
4408                 last_offset = offset;
4409         }
4410
4411         cfg->code_len = code - cfg->native_code;
4412 }
4413
4414 void
4415 mono_arch_register_lowlevel_calls (void)
4416 {
4417 }
4418
4419 void
4420 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4421 {
4422         MonoJumpInfo *patch_info;
4423         gboolean compile_aot = !run_cctors;
4424
4425         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4426                 unsigned char *ip = patch_info->ip.i + code;
4427                 unsigned char *target;
4428
4429                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4430
4431                 if (compile_aot) {
4432                         switch (patch_info->type) {
4433                         case MONO_PATCH_INFO_BB:
4434                         case MONO_PATCH_INFO_LABEL:
4435                                 break;
4436                         default:
4437                                 /* No need to patch these */
4438                                 continue;
4439                         }
4440                 }
4441
4442                 switch (patch_info->type) {
4443                 case MONO_PATCH_INFO_NONE:
4444                         continue;
4445                 case MONO_PATCH_INFO_METHOD_REL:
4446                 case MONO_PATCH_INFO_R8:
4447                 case MONO_PATCH_INFO_R4:
4448                         g_assert_not_reached ();
4449                         continue;
4450                 case MONO_PATCH_INFO_BB:
4451                         break;
4452                 default:
4453                         break;
4454                 }
4455
4456                 /*
4457                  * Debug code to help track down problems where the target of a near call is
4458                  * is not valid.
4459                  */
4460                 if (amd64_is_near_call (ip)) {
4461                         gint64 disp = (guint8*)target - (guint8*)ip;
4462
4463                         if (!amd64_is_imm32 (disp)) {
4464                                 printf ("TYPE: %d\n", patch_info->type);
4465                                 switch (patch_info->type) {
4466                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4467                                         printf ("V: %s\n", patch_info->data.name);
4468                                         break;
4469                                 case MONO_PATCH_INFO_METHOD_JUMP:
4470                                 case MONO_PATCH_INFO_METHOD:
4471                                         printf ("V: %s\n", patch_info->data.method->name);
4472                                         break;
4473                                 default:
4474                                         break;
4475                                 }
4476                         }
4477                 }
4478
4479                 amd64_patch (ip, (gpointer)target);
4480         }
4481 }
4482
4483 /*
4484  * This macro is used for testing whenever the unwinder works correctly at every point
4485  * where an async exception can happen.
4486  */
4487 /* This will generate a SIGSEGV at the given point in the code */
4488 #define async_exc_point(code) do { \
4489     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4490          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4491              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4492          cfg->arch.async_point_count ++; \
4493     } \
4494 } while (0)
4495
4496 guint8 *
4497 mono_arch_emit_prolog (MonoCompile *cfg)
4498 {
4499         MonoMethod *method = cfg->method;
4500         MonoBasicBlock *bb;
4501         MonoMethodSignature *sig;
4502         MonoInst *ins;
4503         int alloc_size, pos, max_offset, i, quad;
4504         guint8 *code;
4505         CallInfo *cinfo;
4506         gint32 lmf_offset = cfg->arch.lmf_offset;
4507         gboolean args_clobbered = FALSE;
4508         gboolean trace = FALSE;
4509
4510         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4511
4512         code = cfg->native_code = g_malloc (cfg->code_size);
4513
4514         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4515                 trace = TRUE;
4516
4517         /* Amount of stack space allocated by register saving code */
4518         pos = 0;
4519
4520         /*
4521          * The prolog consists of the following parts:
4522          * FP present:
4523          * - push rbp, mov rbp, rsp
4524          * - save callee saved regs using pushes
4525          * - allocate frame
4526          * - save lmf if needed
4527          * FP not present:
4528          * - allocate frame
4529          * - save lmf if needed
4530          * - save callee saved regs using moves
4531          */
4532
4533         async_exc_point (code);
4534
4535         if (!cfg->arch.omit_fp) {
4536                 amd64_push_reg (code, AMD64_RBP);
4537                 async_exc_point (code);
4538                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4539                 async_exc_point (code);
4540         }
4541
4542         /* Save callee saved registers */
4543         if (!cfg->arch.omit_fp && !method->save_lmf) {
4544                 for (i = 0; i < AMD64_NREG; ++i)
4545                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4546                                 amd64_push_reg (code, i);
4547                                 pos += sizeof (gpointer);
4548                                 async_exc_point (code);
4549                         }
4550         }
4551
4552         if (cfg->arch.omit_fp) {
4553                 /*
4554                  * On enter, the stack is misaligned by the the pushing of the return
4555                  * address. It is either made aligned by the pushing of %rbp, or by
4556                  * this.
4557                  */
4558                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4559                 if ((alloc_size % 16) == 0)
4560                         alloc_size += 8;
4561         } else {
4562                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4563
4564                 alloc_size -= pos;
4565         }
4566
4567         cfg->arch.stack_alloc_size = alloc_size;
4568
4569         /* Allocate stack frame */
4570         if (alloc_size) {
4571                 /* See mono_emit_stack_alloc */
4572 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4573                 guint32 remaining_size = alloc_size;
4574                 while (remaining_size >= 0x1000) {
4575                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4576                         async_exc_point (code);
4577                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4578                         remaining_size -= 0x1000;
4579                 }
4580                 if (remaining_size) {
4581                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4582                         async_exc_point (code);
4583                 }
4584 #else
4585                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4586                 async_exc_point (code);
4587 #endif
4588         }
4589
4590         /* Stack alignment check */
4591 #if 0
4592         {
4593                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4594                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4595                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4596                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4597                 amd64_breakpoint (code);
4598         }
4599 #endif
4600
4601         /* Save LMF */
4602         if (method->save_lmf) {
4603                 /*
4604                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4605                  */
4606                 /* sp is saved right before calls */
4607                 /* Skip method (only needed for trampoline LMF frames) */
4608                 /* Save callee saved regs */
4609                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4610                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4611                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4612                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4613                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4614                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4615         }
4616
4617         /* Save callee saved registers */
4618         if (cfg->arch.omit_fp && !method->save_lmf) {
4619                 gint32 save_area_offset = 0;
4620
4621                 /* Save caller saved registers after sp is adjusted */
4622                 /* The registers are saved at the bottom of the frame */
4623                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4624                 for (i = 0; i < AMD64_NREG; ++i)
4625                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4626                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4627                                 save_area_offset += 8;
4628                                 async_exc_point (code);
4629                         }
4630         }
4631
4632         /* compute max_offset in order to use short forward jumps */
4633         max_offset = 0;
4634         if (cfg->opt & MONO_OPT_BRANCH) {
4635                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4636                         bb->max_offset = max_offset;
4637
4638                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4639                                 max_offset += 6;
4640                         /* max alignment for loops */
4641                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4642                                 max_offset += LOOP_ALIGNMENT;
4643
4644                         MONO_BB_FOR_EACH_INS (bb, ins) {
4645                                 if (ins->opcode == OP_LABEL)
4646                                         ins->inst_c1 = max_offset;
4647
4648                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4649                         }
4650                 }
4651         }
4652
4653         sig = mono_method_signature (method);
4654         pos = 0;
4655
4656         cinfo = cfg->arch.cinfo;
4657
4658         if (sig->ret->type != MONO_TYPE_VOID) {
4659                 /* Save volatile arguments to the stack */
4660                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4661                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4662         }
4663
4664         /* Keep this in sync with emit_load_volatile_arguments */
4665         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4666                 ArgInfo *ainfo = cinfo->args + i;
4667                 gint32 stack_offset;
4668                 MonoType *arg_type;
4669
4670                 ins = cfg->args [i];
4671
4672                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4673                         /* Unused arguments */
4674                         continue;
4675
4676                 if (sig->hasthis && (i == 0))
4677                         arg_type = &mono_defaults.object_class->byval_arg;
4678                 else
4679                         arg_type = sig->params [i - sig->hasthis];
4680
4681                 stack_offset = ainfo->offset + ARGS_OFFSET;
4682
4683                 /* Save volatile arguments to the stack */
4684                 if (ins->opcode != OP_REGVAR) {
4685                         switch (ainfo->storage) {
4686                         case ArgInIReg: {
4687                                 guint32 size = 8;
4688
4689                                 /* FIXME: I1 etc */
4690                                 /*
4691                                 if (stack_offset & 0x1)
4692                                         size = 1;
4693                                 else if (stack_offset & 0x2)
4694                                         size = 2;
4695                                 else if (stack_offset & 0x4)
4696                                         size = 4;
4697                                 else
4698                                         size = 8;
4699                                 */
4700                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4701                                 break;
4702                         }
4703                         case ArgInFloatSSEReg:
4704                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4705                                 break;
4706                         case ArgInDoubleSSEReg:
4707                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4708                                 break;
4709                         case ArgValuetypeInReg:
4710                                 for (quad = 0; quad < 2; quad ++) {
4711                                         switch (ainfo->pair_storage [quad]) {
4712                                         case ArgInIReg:
4713                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4714                                                 break;
4715                                         case ArgInFloatSSEReg:
4716                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4717                                                 break;
4718                                         case ArgInDoubleSSEReg:
4719                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4720                                                 break;
4721                                         case ArgNone:
4722                                                 break;
4723                                         default:
4724                                                 g_assert_not_reached ();
4725                                         }
4726                                 }
4727                                 break;
4728                         default:
4729                                 break;
4730                         }
4731                 } else {
4732                         /* Argument allocated to (non-volatile) register */
4733                         switch (ainfo->storage) {
4734                         case ArgInIReg:
4735                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4736                                 break;
4737                         case ArgOnStack:
4738                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4739                                 break;
4740                         default:
4741                                 g_assert_not_reached ();
4742                         }
4743                 }
4744         }
4745
4746         /* Might need to attach the thread to the JIT  or change the domain for the callback */
4747         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4748                 guint64 domain = (guint64)cfg->domain;
4749
4750                 args_clobbered = TRUE;
4751
4752                 /*
4753                  * The call might clobber argument registers, but they are already
4754                  * saved to the stack/global regs.
4755                  */
4756                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4757                         guint8 *buf, *no_domain_branch;
4758
4759                         code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4760                         if ((domain >> 32) == 0)
4761                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4762                         else
4763                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4764                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4765                         no_domain_branch = code;
4766                         x86_branch8 (code, X86_CC_NE, 0, 0);
4767                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4768                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4769                         buf = code;
4770                         x86_branch8 (code, X86_CC_NE, 0, 0);
4771                         amd64_patch (no_domain_branch, code);
4772                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4773                         amd64_patch (buf, code);
4774                 } else {
4775                         g_assert (!cfg->compile_aot);
4776                         if ((domain >> 32) == 0)
4777                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4778                         else
4779                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4780                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4781                 }
4782         }
4783
4784         if (method->save_lmf) {
4785                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4786                         /*
4787                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4788                          * through the mono_lmf_addr TLS variable.
4789                          */
4790                         /* %rax = previous_lmf */
4791                         x86_prefix (code, X86_FS_PREFIX);
4792                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4793
4794                         /* Save previous_lmf */
4795                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4796                         /* Set new lmf */
4797                         if (lmf_offset == 0) {
4798                                 x86_prefix (code, X86_FS_PREFIX);
4799                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4800                         } else {
4801                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4802                                 x86_prefix (code, X86_FS_PREFIX);
4803                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4804                         }
4805                 } else {
4806                         if (lmf_addr_tls_offset != -1) {
4807                                 /* Load lmf quicky using the FS register */
4808                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4809                         }
4810                         else {
4811                                 /*
4812                                  * The call might clobber argument registers, but they are already
4813                                  * saved to the stack/global regs.
4814                                  */
4815                                 args_clobbered = TRUE;
4816                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4817                                                                   (gpointer)"mono_get_lmf_addr");
4818                         }
4819
4820                         /* Save lmf_addr */
4821                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4822                         /* Save previous_lmf */
4823                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4824                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4825                         /* Set new lmf */
4826                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4827                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4828                 }
4829         }
4830
4831         if (trace) {
4832                 args_clobbered = TRUE;
4833                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4834         }
4835
4836         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4837                 args_clobbered = TRUE;
4838
4839         /*
4840          * Optimize the common case of the first bblock making a call with the same
4841          * arguments as the method. This works because the arguments are still in their
4842          * original argument registers.
4843          * FIXME: Generalize this
4844          */
4845         if (!args_clobbered) {
4846                 MonoBasicBlock *first_bb = cfg->bb_entry;
4847                 MonoInst *next;
4848
4849                 next = mono_inst_list_first (&first_bb->ins_list);
4850                 if (!next && first_bb->next_bb) {
4851                         first_bb = first_bb->next_bb;
4852                         next = mono_inst_list_first (&first_bb->ins_list);
4853                 }
4854
4855                 if (first_bb->in_count > 1)
4856                         next = NULL;
4857
4858                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4859                         ArgInfo *ainfo = cinfo->args + i;
4860                         gboolean match = FALSE;
4861
4862                         ins = cfg->args [i];
4863                         if (ins->opcode != OP_REGVAR) {
4864                                 switch (ainfo->storage) {
4865                                 case ArgInIReg: {
4866                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4867                                                 if (next->dreg == ainfo->reg) {
4868                                                         NULLIFY_INS (next);
4869                                                         match = TRUE;
4870                                                 } else {
4871                                                         next->opcode = OP_MOVE;
4872                                                         next->sreg1 = ainfo->reg;
4873                                                         /* Only continue if the instruction doesn't change argument regs */
4874                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4875                                                                 match = TRUE;
4876                                                 }
4877                                         }
4878                                         break;
4879                                 }
4880                                 default:
4881                                         break;
4882                                 }
4883                         } else {
4884                                 /* Argument allocated to (non-volatile) register */
4885                                 switch (ainfo->storage) {
4886                                 case ArgInIReg:
4887                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4888                                                 NULLIFY_INS (next);
4889                                                 match = TRUE;
4890                                         }
4891                                         break;
4892                                 default:
4893                                         break;
4894                                 }
4895                         }
4896
4897                         if (!match)
4898                                 break;
4899                         next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4900                 }
4901         }
4902
4903         cfg->code_len = code - cfg->native_code;
4904
4905         g_assert (cfg->code_len < cfg->code_size);
4906
4907         return code;
4908 }
4909
4910 void
4911 mono_arch_emit_epilog (MonoCompile *cfg)
4912 {
4913         MonoMethod *method = cfg->method;
4914         int quad, pos, i;
4915         guint8 *code;
4916         int max_epilog_size = 16;
4917         CallInfo *cinfo;
4918         gint32 lmf_offset = cfg->arch.lmf_offset;
4919
4920         if (cfg->method->save_lmf)
4921                 max_epilog_size += 256;
4922
4923         if (mono_jit_trace_calls != NULL)
4924                 max_epilog_size += 50;
4925
4926         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4927                 max_epilog_size += 50;
4928
4929         max_epilog_size += (AMD64_NREG * 2);
4930
4931         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4932                 cfg->code_size *= 2;
4933                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4934                 mono_jit_stats.code_reallocs++;
4935         }
4936
4937         code = cfg->native_code + cfg->code_len;
4938
4939         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4940                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4941
4942         /* the code restoring the registers must be kept in sync with OP_JMP */
4943         pos = 0;
4944
4945         if (method->save_lmf) {
4946                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4947                         /*
4948                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4949                          * through the mono_lmf_addr TLS variable.
4950                          */
4951                         /* reg = previous_lmf */
4952                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4953                         x86_prefix (code, X86_FS_PREFIX);
4954                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4955                 } else {
4956                         /* Restore previous lmf */
4957                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4958                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4959                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4960                 }
4961
4962                 /* Restore caller saved regs */
4963                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4964                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
4965                 }
4966                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4967                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4968                 }
4969                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4970                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4971                 }
4972                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4973                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4974                 }
4975                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4976                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4977                 }
4978                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4979                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4980                 }
4981         } else {
4982
4983                 if (cfg->arch.omit_fp) {
4984                         gint32 save_area_offset = 0;
4985
4986                         for (i = 0; i < AMD64_NREG; ++i)
4987                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4988                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4989                                         save_area_offset += 8;
4990                                 }
4991                 }
4992                 else {
4993                         for (i = 0; i < AMD64_NREG; ++i)
4994                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4995                                         pos -= sizeof (gpointer);
4996
4997                         if (pos) {
4998                                 if (pos == - sizeof (gpointer)) {
4999                                         /* Only one register, so avoid lea */
5000                                         for (i = AMD64_NREG - 1; i > 0; --i)
5001                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5002                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5003                                                 }
5004                                 }
5005                                 else {
5006                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5007
5008                                         /* Pop registers in reverse order */
5009                                         for (i = AMD64_NREG - 1; i > 0; --i)
5010                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5011                                                         amd64_pop_reg (code, i);
5012                                                 }
5013                                 }
5014                         }
5015                 }
5016         }
5017
5018         /* Load returned vtypes into registers if needed */
5019         cinfo = cfg->arch.cinfo;
5020         if (cinfo->ret.storage == ArgValuetypeInReg) {
5021                 ArgInfo *ainfo = &cinfo->ret;
5022                 MonoInst *inst = cfg->ret;
5023
5024                 for (quad = 0; quad < 2; quad ++) {
5025                         switch (ainfo->pair_storage [quad]) {
5026                         case ArgInIReg:
5027                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5028                                 break;
5029                         case ArgInFloatSSEReg:
5030                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5031                                 break;
5032                         case ArgInDoubleSSEReg:
5033                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5034                                 break;
5035                         case ArgNone:
5036                                 break;
5037                         default:
5038                                 g_assert_not_reached ();
5039                         }
5040                 }
5041         }
5042
5043         if (cfg->arch.omit_fp) {
5044                 if (cfg->arch.stack_alloc_size)
5045                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5046         } else {
5047                 amd64_leave (code);
5048         }
5049         async_exc_point (code);
5050         amd64_ret (code);
5051
5052         cfg->code_len = code - cfg->native_code;
5053
5054         g_assert (cfg->code_len < cfg->code_size);
5055
5056         if (cfg->arch.omit_fp) {
5057                 /*
5058                  * Encode the stack size into used_int_regs so the exception handler
5059                  * can access it.
5060                  */
5061                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5062                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5063         }
5064 }
5065
5066 void
5067 mono_arch_emit_exceptions (MonoCompile *cfg)
5068 {
5069         MonoJumpInfo *patch_info;
5070         int nthrows, i;
5071         guint8 *code;
5072         MonoClass *exc_classes [16];
5073         guint8 *exc_throw_start [16], *exc_throw_end [16];
5074         guint32 code_size = 0;
5075
5076         /* Compute needed space */
5077         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5078                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5079                         code_size += 40;
5080                 if (patch_info->type == MONO_PATCH_INFO_R8)
5081                         code_size += 8 + 15; /* sizeof (double) + alignment */
5082                 if (patch_info->type == MONO_PATCH_INFO_R4)
5083                         code_size += 4 + 15; /* sizeof (float) + alignment */
5084         }
5085
5086         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5087                 cfg->code_size *= 2;
5088                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5089                 mono_jit_stats.code_reallocs++;
5090         }
5091
5092         code = cfg->native_code + cfg->code_len;
5093
5094         /* add code to raise exceptions */
5095         nthrows = 0;
5096         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5097                 switch (patch_info->type) {
5098                 case MONO_PATCH_INFO_EXC: {
5099                         MonoClass *exc_class;
5100                         guint8 *buf, *buf2;
5101                         guint32 throw_ip;
5102
5103                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5104
5105                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5106                         g_assert (exc_class);
5107                         throw_ip = patch_info->ip.i;
5108
5109                         //x86_breakpoint (code);
5110                         /* Find a throw sequence for the same exception class */
5111                         for (i = 0; i < nthrows; ++i)
5112                                 if (exc_classes [i] == exc_class)
5113                                         break;
5114                         if (i < nthrows) {
5115                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5116                                 x86_jump_code (code, exc_throw_start [i]);
5117                                 patch_info->type = MONO_PATCH_INFO_NONE;
5118                         }
5119                         else {
5120                                 buf = code;
5121                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5122                                 buf2 = code;
5123
5124                                 if (nthrows < 16) {
5125                                         exc_classes [nthrows] = exc_class;
5126                                         exc_throw_start [nthrows] = code;
5127                                 }
5128                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5129                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
5130                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5131                                 patch_info->ip.i = code - cfg->native_code;
5132
5133                                 code = emit_call_body (cfg, code, patch_info->type, patch_info->data.name);
5134
5135                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5136                                 while (buf < buf2)
5137                                         x86_nop (buf);
5138
5139                                 if (nthrows < 16) {
5140                                         exc_throw_end [nthrows] = code;
5141                                         nthrows ++;
5142                                 }
5143                         }
5144                         break;
5145                 }
5146                 default:
5147                         /* do nothing */
5148                         break;
5149                 }
5150         }
5151
5152         /* Handle relocations with RIP relative addressing */
5153         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5154                 gboolean remove = FALSE;
5155
5156                 switch (patch_info->type) {
5157                 case MONO_PATCH_INFO_R8:
5158                 case MONO_PATCH_INFO_R4: {
5159                         guint8 *pos;
5160
5161                         if (use_sse2) {
5162                                 /* The SSE opcodes require a 16 byte alignment */
5163                                 code = (guint8*)ALIGN_TO (code, 16);
5164                         } else {
5165                                 code = (guint8*)ALIGN_TO (code, 8);
5166                         }
5167
5168                         pos = cfg->native_code + patch_info->ip.i;
5169
5170
5171                         if (use_sse2) {
5172                                 if (IS_REX (pos [1]))
5173                                         *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5174                                 else
5175                                         *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5176                         } else {
5177                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
5178                         }
5179
5180                         if (patch_info->type == MONO_PATCH_INFO_R8) {
5181                                 *(double*)code = *(double*)patch_info->data.target;
5182                                 code += sizeof (double);
5183                         } else {
5184                                 *(float*)code = *(float*)patch_info->data.target;
5185                                 code += sizeof (float);
5186                         }
5187
5188                         remove = TRUE;
5189                         break;
5190                 }
5191                 default:
5192                         break;
5193                 }
5194
5195                 if (remove) {
5196                         if (patch_info == cfg->patch_info)
5197                                 cfg->patch_info = patch_info->next;
5198                         else {
5199                                 MonoJumpInfo *tmp;
5200
5201                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5202                                         ;
5203                                 tmp->next = patch_info->next;
5204                         }
5205                 }
5206         }
5207
5208         cfg->code_len = code - cfg->native_code;
5209
5210         g_assert (cfg->code_len < cfg->code_size);
5211
5212 }
5213
5214 void*
5215 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5216 {
5217         guchar *code = p;
5218         CallInfo *cinfo = NULL;
5219         MonoMethodSignature *sig;
5220         MonoInst *inst;
5221         int i, n, stack_area = 0;
5222
5223         /* Keep this in sync with mono_arch_get_argument_info */
5224
5225         if (enable_arguments) {
5226                 /* Allocate a new area on the stack and save arguments there */
5227                 sig = mono_method_signature (cfg->method);
5228
5229                 cinfo = get_call_info (cfg, cfg->mempool, sig, FALSE);
5230
5231                 n = sig->param_count + sig->hasthis;
5232
5233                 stack_area = ALIGN_TO (n * 8, 16);
5234
5235                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5236
5237                 for (i = 0; i < n; ++i) {
5238                         inst = cfg->args [i];
5239
5240                         if (inst->opcode == OP_REGVAR)
5241                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5242                         else {
5243                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5244                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5245                         }
5246                 }
5247         }
5248
5249         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5250         amd64_set_reg_template (code, AMD64_ARG_REG1);
5251         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5252         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
5253
5254         if (enable_arguments)
5255                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5256
5257         return code;
5258 }
5259
5260 enum {
5261         SAVE_NONE,
5262         SAVE_STRUCT,
5263         SAVE_EAX,
5264         SAVE_EAX_EDX,
5265         SAVE_XMM
5266 };
5267
5268 void*
5269 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5270 {
5271         guchar *code = p;
5272         int save_mode = SAVE_NONE;
5273         MonoMethod *method = cfg->method;
5274         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
5275
5276         switch (rtype) {
5277         case MONO_TYPE_VOID:
5278                 /* special case string .ctor icall */
5279                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5280                         save_mode = SAVE_EAX;
5281                 else
5282                         save_mode = SAVE_NONE;
5283                 break;
5284         case MONO_TYPE_I8:
5285         case MONO_TYPE_U8:
5286                 save_mode = SAVE_EAX;
5287                 break;
5288         case MONO_TYPE_R4:
5289         case MONO_TYPE_R8:
5290                 save_mode = SAVE_XMM;
5291                 break;
5292         case MONO_TYPE_GENERICINST:
5293                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5294                         save_mode = SAVE_EAX;
5295                         break;
5296                 }
5297                 /* Fall through */
5298         case MONO_TYPE_VALUETYPE:
5299                 save_mode = SAVE_STRUCT;
5300                 break;
5301         default:
5302                 save_mode = SAVE_EAX;
5303                 break;
5304         }
5305
5306         /* Save the result and copy it into the proper argument register */
5307         switch (save_mode) {
5308         case SAVE_EAX:
5309                 amd64_push_reg (code, AMD64_RAX);
5310                 /* Align stack */
5311                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5312                 if (enable_arguments)
5313                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5314                 break;
5315         case SAVE_STRUCT:
5316                 /* FIXME: */
5317                 if (enable_arguments)
5318                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5319                 break;
5320         case SAVE_XMM:
5321                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5322                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5323                 /* Align stack */
5324                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5325                 /*
5326                  * The result is already in the proper argument register so no copying
5327                  * needed.
5328                  */
5329                 break;
5330         case SAVE_NONE:
5331                 break;
5332         default:
5333                 g_assert_not_reached ();
5334         }
5335
5336         /* Set %al since this is a varargs call */
5337         if (save_mode == SAVE_XMM)
5338                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5339         else
5340                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5341
5342         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5343         amd64_set_reg_template (code, AMD64_ARG_REG1);
5344         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
5345
5346         /* Restore result */
5347         switch (save_mode) {
5348         case SAVE_EAX:
5349                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5350                 amd64_pop_reg (code, AMD64_RAX);
5351                 break;
5352         case SAVE_STRUCT:
5353                 /* FIXME: */
5354                 break;
5355         case SAVE_XMM:
5356                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5357                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5358                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5359                 break;
5360         case SAVE_NONE:
5361                 break;
5362         default:
5363                 g_assert_not_reached ();
5364         }
5365
5366         return code;
5367 }
5368
5369 void
5370 mono_arch_flush_icache (guint8 *code, gint size)
5371 {
5372         /* Not needed */
5373 }
5374
5375 void
5376 mono_arch_flush_register_windows (void)
5377 {
5378 }
5379
5380 gboolean
5381 mono_arch_is_inst_imm (gint64 imm)
5382 {
5383         return amd64_is_imm32 (imm);
5384 }
5385
5386 /*
5387  * Determine whenever the trap whose info is in SIGINFO is caused by
5388  * integer overflow.
5389  */
5390 gboolean
5391 mono_arch_is_int_overflow (void *sigctx, void *info)
5392 {
5393         MonoContext ctx;
5394         guint8* rip;
5395         int reg;
5396         gint64 value;
5397
5398         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5399
5400         rip = (guint8*)ctx.rip;
5401
5402         if (IS_REX (rip [0])) {
5403                 reg = amd64_rex_b (rip [0]);
5404                 rip ++;
5405         }
5406         else
5407                 reg = 0;
5408
5409         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5410                 /* idiv REG */
5411                 reg += x86_modrm_rm (rip [1]);
5412
5413                 switch (reg) {
5414                 case AMD64_RAX:
5415                         value = ctx.rax;
5416                         break;
5417                 case AMD64_RBX:
5418                         value = ctx.rbx;
5419                         break;
5420                 case AMD64_RCX:
5421                         value = ctx.rcx;
5422                         break;
5423                 case AMD64_RDX:
5424                         value = ctx.rdx;
5425                         break;
5426                 case AMD64_RBP:
5427                         value = ctx.rbp;
5428                         break;
5429                 case AMD64_RSP:
5430                         value = ctx.rsp;
5431                         break;
5432                 case AMD64_RSI:
5433                         value = ctx.rsi;
5434                         break;
5435                 case AMD64_RDI:
5436                         value = ctx.rdi;
5437                         break;
5438                 case AMD64_R12:
5439                         value = ctx.r12;
5440                         break;
5441                 case AMD64_R13:
5442                         value = ctx.r13;
5443                         break;
5444                 case AMD64_R14:
5445                         value = ctx.r14;
5446                         break;
5447                 case AMD64_R15:
5448                         value = ctx.r15;
5449                         break;
5450                 default:
5451                         g_assert_not_reached ();
5452                         reg = -1;
5453                 }
5454
5455                 if (value == -1)
5456                         return TRUE;
5457         }
5458
5459         return FALSE;
5460 }
5461
5462 guint32
5463 mono_arch_get_patch_offset (guint8 *code)
5464 {
5465         return 3;
5466 }
5467
5468 gboolean
5469 mono_breakpoint_clean_code (guint8 *code, guint8 *buf, int size)
5470 {
5471         int i;
5472         gboolean can_write = TRUE;
5473         memcpy (buf, code, size);
5474         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5475                 int idx = mono_breakpoint_info_index [i];
5476                 guint8 *ptr;
5477                 if (idx < 1)
5478                         continue;
5479                 ptr = mono_breakpoint_info [idx].address;
5480                 if (ptr >= code && ptr < code + size) {
5481                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5482                         can_write = FALSE;
5483                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5484                         buf [ptr - code] = saved_byte;
5485                 }
5486         }
5487         return can_write;
5488 }
5489
5490 gpointer
5491 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5492 {
5493         guint8 buf [10];
5494         guint32 reg;
5495         gint32 disp;
5496         guint8 rex = 0;
5497
5498         mono_breakpoint_clean_code (code - 10, buf, sizeof (buf));
5499         code = buf + 10;
5500
5501         *displacement = 0;
5502
5503         /* go to the start of the call instruction
5504          *
5505          * address_byte = (m << 6) | (o << 3) | reg
5506          * call opcode: 0xff address_byte displacement
5507          * 0xff m=1,o=2 imm8
5508          * 0xff m=2,o=2 imm32
5509          */
5510         code -= 7;
5511
5512         /*
5513          * A given byte sequence can match more than case here, so we have to be
5514          * really careful about the ordering of the cases. Longer sequences
5515          * come first.
5516          */
5517 #ifdef MONO_ARCH_HAVE_IMT
5518         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5519                 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5520                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11d
5521                  * ff 50 fc                call   *0xfffffffc(%rax)
5522                  */
5523                 reg = amd64_modrm_rm (code [5]);
5524                 disp = (signed char)code [6];
5525                 /* R10 is clobbered by the IMT thunk code */
5526                 g_assert (reg != AMD64_R10);
5527         }
5528 #else
5529         if (0) {
5530         }
5531 #endif
5532         else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5533                         /*
5534                          * This is a interface call
5535                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
5536                          * ff 10                  callq  *(%rax)
5537                          */
5538                 if (IS_REX (code [4]))
5539                         rex = code [4];
5540                 reg = amd64_modrm_rm (code [6]);
5541                 disp = 0;
5542                 /* R10 is clobbered by the IMT thunk code */
5543                 g_assert (reg != AMD64_R10);
5544         } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5545                 /* call OFFSET(%rip) */
5546                 disp = *(guint32*)(code + 3);
5547                 return (gpointer*)(code + disp + 7);
5548         }
5549         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5550                 /* call *[reg+disp32] */
5551                 if (IS_REX (code [0]))
5552                         rex = code [0];
5553                 reg = amd64_modrm_rm (code [2]);
5554                 disp = *(gint32*)(code + 3);
5555                 /* R10 is clobbered by the IMT thunk code */
5556                 g_assert (reg != AMD64_R10);
5557         }
5558         else if (code [2] == 0xe8) {
5559                 /* call <ADDR> */
5560                 return NULL;
5561         }
5562         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5563                 /* call *%reg */
5564                 return NULL;
5565         }
5566         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5567                 /* call *[reg+disp8] */
5568                 if (IS_REX (code [3]))
5569                         rex = code [3];
5570                 reg = amd64_modrm_rm (code [5]);
5571                 disp = *(gint8*)(code + 6);
5572                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5573         }
5574         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5575                         /*
5576                          * This is a interface call: should check the above code can't catch it earlier
5577                          * 8b 40 30   mov    0x30(%eax),%eax
5578                          * ff 10      call   *(%eax)
5579                          */
5580                 if (IS_REX (code [4]))
5581                         rex = code [4];
5582                 reg = amd64_modrm_rm (code [6]);
5583                 disp = 0;
5584         }
5585         else
5586                 g_assert_not_reached ();
5587
5588         reg += amd64_rex_b (rex);
5589
5590         /* R11 is clobbered by the trampoline code */
5591         g_assert (reg != AMD64_R11);
5592
5593         *displacement = disp;
5594         return regs [reg];
5595 }
5596
5597 gpointer*
5598 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5599 {
5600         gpointer vt;
5601         int displacement;
5602         vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5603         if (!vt)
5604                 return NULL;
5605         return (gpointer*)((char*)vt + displacement);
5606 }
5607
5608 gpointer
5609 mono_arch_get_this_arg_from_call (MonoMethodSignature *sig, gssize *regs, guint8 *code)
5610 {
5611         if (MONO_TYPE_ISSTRUCT (sig->ret))
5612                 return (gpointer)regs [AMD64_ARG_REG2];
5613         else
5614                 return (gpointer)regs [AMD64_ARG_REG1];
5615 }
5616
5617 #define MAX_ARCH_DELEGATE_PARAMS 10
5618
5619 gpointer
5620 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5621 {
5622         guint8 *code, *start;
5623         int i;
5624
5625         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5626                 return NULL;
5627
5628         /* FIXME: Support more cases */
5629         if (MONO_TYPE_ISSTRUCT (sig->ret))
5630                 return NULL;
5631
5632         if (has_target) {
5633                 static guint8* cached = NULL;
5634                 mono_mini_arch_lock ();
5635                 if (cached) {
5636                         mono_mini_arch_unlock ();
5637                         return cached;
5638                 }
5639
5640                 start = code = mono_global_codeman_reserve (64);
5641
5642                 /* Replace the this argument with the target */
5643                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5644                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5645                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5646
5647                 g_assert ((code - start) < 64);
5648
5649                 cached = start;
5650                 mono_debug_add_delegate_trampoline (start, code - start);
5651                 mono_mini_arch_unlock ();
5652         } else {
5653                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5654                 for (i = 0; i < sig->param_count; ++i)
5655                         if (!mono_is_regsize_var (sig->params [i]))
5656                                 return NULL;
5657                 if (sig->param_count > 4)
5658                         return NULL;
5659
5660                 mono_mini_arch_lock ();
5661                 code = cache [sig->param_count];
5662                 if (code) {
5663                         mono_mini_arch_unlock ();
5664                         return code;
5665                 }
5666
5667                 start = code = mono_global_codeman_reserve (64);
5668
5669                 if (sig->param_count == 0) {
5670                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5671                 } else {
5672                         /* We have to shift the arguments left */
5673                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5674                         for (i = 0; i < sig->param_count; ++i)
5675                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5676
5677                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5678                 }
5679                 g_assert ((code - start) < 64);
5680
5681                 cache [sig->param_count] = start;
5682
5683                 mono_debug_add_delegate_trampoline (start, code - start);
5684                 mono_mini_arch_unlock ();
5685         }
5686
5687         return start;
5688 }
5689
5690 /*
5691  * Support for fast access to the thread-local lmf structure using the GS
5692  * segment register on NPTL + kernel 2.6.x.
5693  */
5694
5695 static gboolean tls_offset_inited = FALSE;
5696
5697 void
5698 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5699 {
5700         if (!tls_offset_inited) {
5701                 tls_offset_inited = TRUE;
5702 #ifdef MONO_XEN_OPT
5703                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5704 #endif
5705                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5706                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5707                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5708                 thread_tls_offset = mono_thread_get_tls_offset ();
5709         }
5710 }
5711
5712 void
5713 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5714 {
5715 }
5716
5717 void
5718 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5719 {
5720         MonoCallInst *call = (MonoCallInst*)inst;
5721         CallInfo * cinfo = get_call_info (cfg, cfg->mempool, inst->signature, FALSE);
5722
5723         if (vt_reg != -1) {
5724                 MonoInst *vtarg;
5725
5726                 if (cinfo->ret.storage == ArgValuetypeInReg) {
5727                         /*
5728                          * The valuetype is in RAX:RDX after the call, need to be copied to
5729                          * the stack. Push the address here, so the call instruction can
5730                          * access it.
5731                          */
5732                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5733                         vtarg->sreg1 = vt_reg;
5734                         mono_bblock_add_inst (cfg->cbb, vtarg);
5735
5736                         /* Align stack */
5737                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5738                 }
5739                 else {
5740                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
5741                         vtarg->sreg1 = vt_reg;
5742                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
5743                         mono_bblock_add_inst (cfg->cbb, vtarg);
5744
5745                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
5746                 }
5747         }
5748
5749         /* add the this argument */
5750         if (this_reg != -1) {
5751                 MonoInst *this;
5752                 MONO_INST_NEW (cfg, this, OP_MOVE);
5753                 this->type = this_type;
5754                 this->sreg1 = this_reg;
5755                 this->dreg = mono_regstate_next_int (cfg->rs);
5756                 mono_bblock_add_inst (cfg->cbb, this);
5757
5758                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
5759         }
5760 }
5761
5762 #ifdef MONO_ARCH_HAVE_IMT
5763
5764 #define CMP_SIZE (6 + 1)
5765 #define CMP_REG_REG_SIZE (4 + 1)
5766 #define BR_SMALL_SIZE 2
5767 #define BR_LARGE_SIZE 6
5768 #define MOV_REG_IMM_SIZE 10
5769 #define MOV_REG_IMM_32BIT_SIZE 6
5770 #define JUMP_REG_SIZE (2 + 1)
5771
5772 static int
5773 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5774 {
5775         int i, distance = 0;
5776         for (i = start; i < target; ++i)
5777                 distance += imt_entries [i]->chunk_size;
5778         return distance;
5779 }
5780
5781 /*
5782  * LOCKING: called with the domain lock held
5783  */
5784 gpointer
5785 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count)
5786 {
5787         int i;
5788         int size = 0;
5789         guint8 *code, *start;
5790         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5791
5792         for (i = 0; i < count; ++i) {
5793                 MonoIMTCheckItem *item = imt_entries [i];
5794                 if (item->is_equals) {
5795                         if (item->check_target_idx) {
5796                                 if (!item->compare_done) {
5797                                         if (amd64_is_imm32 (item->method))
5798                                                 item->chunk_size += CMP_SIZE;
5799                                         else
5800                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5801                                 }
5802                                 if (vtable_is_32bit)
5803                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5804                                 else
5805                                         item->chunk_size += MOV_REG_IMM_SIZE;
5806                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5807                         } else {
5808                                 if (vtable_is_32bit)
5809                                         item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5810                                 else
5811                                         item->chunk_size += MOV_REG_IMM_SIZE;
5812                                 item->chunk_size += JUMP_REG_SIZE;
5813                                 /* with assert below:
5814                                  * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5815                                  */
5816                         }
5817                 } else {
5818                         if (amd64_is_imm32 (item->method))
5819                                 item->chunk_size += CMP_SIZE;
5820                         else
5821                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5822                         item->chunk_size += BR_LARGE_SIZE;
5823                         imt_entries [item->check_target_idx]->compare_done = TRUE;
5824                 }
5825                 size += item->chunk_size;
5826         }
5827         code = mono_code_manager_reserve (domain->code_mp, size);
5828         start = code;
5829         for (i = 0; i < count; ++i) {
5830                 MonoIMTCheckItem *item = imt_entries [i];
5831                 item->code_target = code;
5832                 if (item->is_equals) {
5833                         if (item->check_target_idx) {
5834                                 if (!item->compare_done) {
5835                                         if (amd64_is_imm32 (item->method))
5836                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5837                                         else {
5838                                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
5839                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5840                                         }
5841                                 }
5842                                 item->jmp_code = code;
5843                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5844                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->vtable_slot]));
5845                                 amd64_jump_membase (code, AMD64_R11, 0);
5846                         } else {
5847                                 /* enable the commented code to assert on wrong method */
5848 #if 0
5849                                 if (amd64_is_imm32 (item->method))
5850                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5851                                 else {
5852                                         amd64_mov_reg_imm (code, AMD64_R10, item->method);
5853                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5854                                 }
5855                                 item->jmp_code = code;
5856                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5857                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->vtable_slot]));
5858                                 amd64_jump_membase (code, AMD64_R11, 0);
5859                                 amd64_patch (item->jmp_code, code);
5860                                 amd64_breakpoint (code);
5861                                 item->jmp_code = NULL;
5862 #else
5863                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->vtable_slot]));
5864                                 amd64_jump_membase (code, AMD64_R11, 0);
5865 #endif
5866                         }
5867                 } else {
5868                         if (amd64_is_imm32 (item->method))
5869                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5870                         else {
5871                                 amd64_mov_reg_imm (code, AMD64_R10, item->method);
5872                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5873                         }
5874                         item->jmp_code = code;
5875                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5876                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5877                         else
5878                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5879                 }
5880                 g_assert (code - item->code_target <= item->chunk_size);
5881         }
5882         /* patch the branches to get to the target items */
5883         for (i = 0; i < count; ++i) {
5884                 MonoIMTCheckItem *item = imt_entries [i];
5885                 if (item->jmp_code) {
5886                         if (item->check_target_idx) {
5887                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5888                         }
5889                 }
5890         }
5891
5892         mono_stats.imt_thunks_size += code - start;
5893         g_assert (code - start <= size);
5894
5895         return start;
5896 }
5897
5898 MonoMethod*
5899 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
5900 {
5901         /*
5902          * R11 is clobbered by the trampoline code, so we have to retrieve the method
5903          * from the code.
5904          * 41 bb c0 f7 89 00     mov    $0x89f7c0,%r11d
5905          * ff 90 68 ff ff ff     callq  *0xffffffffffffff68(%rax)
5906          */
5907         /* Similar to get_vcall_slot_addr () */
5908
5909         /* Find the start of the call instruction */
5910         code -= 7;
5911         if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5912                 /* IMT-based interface calls
5913                  * 41 bb 14 f8 28 08       mov    $0x828f814,%r11
5914                  * ff 50 fc                call   *0xfffffffc(%rax)
5915                  */
5916                 code += 4;
5917         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5918                 /* call *[reg+disp32] */
5919                 code += 1;
5920         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5921                 /* call *[reg+disp8] */
5922                 code += 4;
5923         } else
5924                 g_assert_not_reached ();
5925
5926         /* Find the start of the mov instruction */
5927         code -= 10;
5928         if (code [0] == 0x49 && code [1] == 0xbb) {
5929                 return (MonoMethod*)*(gssize*)(code + 2);
5930         } else if (code [3] == 0x4d && code [4] == 0x8b && code [5] == 0x1d) {
5931                 /* mov    <OFFSET>(%rip),%r11 */
5932                 return (MonoMethod*)*(gssize*)(code + 10 + *(guint32*)(code + 6));
5933         } else if (code [4] == 0x41 && code [5] == 0xbb) {
5934                 return (MonoMethod*)(gssize)*(guint32*)(code + 6);
5935         } else {
5936                 int i;
5937
5938                 printf ("Unknown call sequence: ");
5939                 for (i = -10; i < 20; ++i)
5940                         printf ("%x ", code [i]);
5941                 g_assert_not_reached ();
5942                 return NULL;
5943         }
5944 }
5945
5946 MonoObject*
5947 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method)
5948 {
5949         return mono_arch_get_this_arg_from_call (mono_method_signature (method), (gssize*)regs, NULL);
5950 }
5951 #endif
5952
5953 MonoInst*
5954 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5955 {
5956         MonoInst *ins = NULL;
5957
5958         if (cmethod->klass == mono_defaults.math_class) {
5959                 if (strcmp (cmethod->name, "Sin") == 0) {
5960                         MONO_INST_NEW (cfg, ins, OP_SIN);
5961                         ins->inst_i0 = args [0];
5962                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5963                         MONO_INST_NEW (cfg, ins, OP_COS);
5964                         ins->inst_i0 = args [0];
5965                 } else if (strcmp (cmethod->name, "Tan") == 0) {
5966                         if (use_sse2)
5967                                 return ins;
5968                         MONO_INST_NEW (cfg, ins, OP_TAN);
5969                         ins->inst_i0 = args [0];
5970                 } else if (strcmp (cmethod->name, "Atan") == 0) {
5971                         if (use_sse2)
5972                                 return ins;
5973                         MONO_INST_NEW (cfg, ins, OP_ATAN);
5974                         ins->inst_i0 = args [0];
5975                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5976                         MONO_INST_NEW (cfg, ins, OP_SQRT);
5977                         ins->inst_i0 = args [0];
5978                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5979                         MONO_INST_NEW (cfg, ins, OP_ABS);
5980                         ins->inst_i0 = args [0];
5981                 }
5982
5983                 if (cfg->opt & MONO_OPT_CMOV) {
5984                         int opcode = 0;
5985
5986                         if (strcmp (cmethod->name, "Min") == 0) {
5987                                 if (fsig->params [0]->type == MONO_TYPE_I4)
5988                                         opcode = OP_IMIN;
5989                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
5990                                         opcode = OP_LMIN;
5991                         } else if (strcmp (cmethod->name, "Max") == 0) {
5992                                 if (fsig->params [0]->type == MONO_TYPE_I4)
5993                                         opcode = OP_IMAX;
5994                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
5995                                         opcode = OP_LMAX;
5996                         }
5997
5998                         if (opcode) {
5999                                 MONO_INST_NEW (cfg, ins, opcode);
6000                                 ins->inst_i0 = args [0];
6001                                 ins->inst_i1 = args [1];
6002                         }
6003                 }
6004
6005 #if 0
6006                 /* OP_FREM is not IEEE compatible */
6007                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6008                         MONO_INST_NEW (cfg, ins, OP_FREM);
6009                         ins->inst_i0 = args [0];
6010                         ins->inst_i1 = args [1];
6011                 }
6012 #endif
6013         } else if(cmethod->klass->image == mono_defaults.corlib &&
6014                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
6015                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
6016                 /*
6017                  * Can't implement CompareExchange methods this way since they have
6018                  * three arguments.
6019                  */
6020         }
6021
6022         return ins;
6023 }
6024
6025 gboolean
6026 mono_arch_print_tree (MonoInst *tree, int arity)
6027 {
6028         return 0;
6029 }
6030
6031 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6032 {
6033         MonoInst* ins;
6034
6035         if (appdomain_tls_offset == -1)
6036                 return NULL;
6037
6038         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6039         ins->inst_offset = appdomain_tls_offset;
6040         return ins;
6041 }
6042
6043 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6044 {
6045         MonoInst* ins;
6046
6047         if (thread_tls_offset == -1)
6048                 return NULL;
6049
6050         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6051         ins->inst_offset = thread_tls_offset;
6052         return ins;
6053 }