mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27 #include <mono/utils/mono-mmap.h>
  28
  29 #include "trace.h"
  30 #include "ir-emit.h"
  31 #include "mini-amd64.h"
  32 #include "cpu-amd64.h"
  33 #include "debugger-agent.h"
  34
  35 /*
  36  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  37  * method-to-ir.c.
  38  */
  39 #define MONO_ARCH_IMT_REG AMD64_R11
  40
  41 static gint lmf_tls_offset = -1;
  42 static gint lmf_addr_tls_offset = -1;
  43 static gint appdomain_tls_offset = -1;
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef HOST_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* This mutex protects architecture specific caches */
  65 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  66 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  67 static CRITICAL_SECTION mini_arch_mutex;
  68
  69 MonoBreakpointInfo
  70 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  71
  72 /*
  73  * The code generated for sequence points reads from this location, which is
  74  * made read-only when single stepping is enabled.
  75  */
  76 static gpointer ss_trigger_page;
  77
  78 /* Enabled breakpoints read from this trigger page */
  79 static gpointer bp_trigger_page;
  80
  81 /* The size of the breakpoint sequence */
  82 static int breakpoint_size;
  83
  84 /* The size of the breakpoint instruction causing the actual fault */
  85 static int breakpoint_fault_size;
  86
  87 /* The size of the single step instruction causing the actual fault */
  88 static int single_step_fault_size;
  89
  90 #ifdef HOST_WIN32
  91 /* On Win64 always reserve first 32 bytes for first four arguments */
  92 #define ARGS_OFFSET 48
  93 #else
  94 #define ARGS_OFFSET 16
  95 #endif
  96 #define GP_SCRATCH_REG AMD64_R11
  97
  98 /*
  99  * AMD64 register usage:
 100  * - callee saved registers are used for global register allocation
 101  * - %r11 is used for materializing 64 bit constants in opcodes
 102  * - the rest is used for local allocation
 103  */
 104
 105 /*
 106  * Floating point comparison results:
 107  *                  ZF PF CF
 108  * A > B            0  0  0
 109  * A < B            0  0  1
 110  * A = B            1  0  0
 111  * A > B            0  0  0
 112  * UNORDERED        1  1  1
 113  */
 114
 115 const char*
 116 mono_arch_regname (int reg)
 117 {
 118         switch (reg) {
 119         case AMD64_RAX: return "%rax";
 120         case AMD64_RBX: return "%rbx";
 121         case AMD64_RCX: return "%rcx";
 122         case AMD64_RDX: return "%rdx";
 123         case AMD64_RSP: return "%rsp";
 124         case AMD64_RBP: return "%rbp";
 125         case AMD64_RDI: return "%rdi";
 126         case AMD64_RSI: return "%rsi";
 127         case AMD64_R8: return "%r8";
 128         case AMD64_R9: return "%r9";
 129         case AMD64_R10: return "%r10";
 130         case AMD64_R11: return "%r11";
 131         case AMD64_R12: return "%r12";
 132         case AMD64_R13: return "%r13";
 133         case AMD64_R14: return "%r14";
 134         case AMD64_R15: return "%r15";
 135         }
 136         return "unknown";
 137 }
 138
 139 static const char * packed_xmmregs [] = {
 140         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 141         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 142 };
 143
 144 static const char * single_xmmregs [] = {
 145         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 146         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 147 };
 148
 149 const char*
 150 mono_arch_fregname (int reg)
 151 {
 152         if (reg < AMD64_XMM_NREG)
 153                 return single_xmmregs [reg];
 154         else
 155                 return "unknown";
 156 }
 157
 158 const char *
 159 mono_arch_xregname (int reg)
 160 {
 161         if (reg < AMD64_XMM_NREG)
 162                 return packed_xmmregs [reg];
 163         else
 164                 return "unknown";
 165 }
 166
 167 G_GNUC_UNUSED static void
 168 break_count (void)
 169 {
 170 }
 171
 172 G_GNUC_UNUSED static gboolean
 173 debug_count (void)
 174 {
 175         static int count = 0;
 176         count ++;
 177
 178         if (!getenv ("COUNT"))
 179                 return TRUE;
 180
 181         if (count == atoi (getenv ("COUNT"))) {
 182                 break_count ();
 183         }
 184
 185         if (count > atoi (getenv ("COUNT"))) {
 186                 return FALSE;
 187         }
 188
 189         return TRUE;
 190 }
 191
 192 static gboolean
 193 debug_omit_fp (void)
 194 {
 195 #if 0
 196         return debug_count ();
 197 #else
 198         return TRUE;
 199 #endif
 200 }
 201
 202 static inline gboolean
 203 amd64_is_near_call (guint8 *code)
 204 {
 205         /* Skip REX */
 206         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 207                 code += 1;
 208
 209         return code [0] == 0xe8;
 210 }
 211
 212 static inline void
 213 amd64_patch (unsigned char* code, gpointer target)
 214 {
 215         guint8 rex = 0;
 216
 217         /* Skip REX */
 218         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 219                 rex = code [0];
 220                 code += 1;
 221         }
 222
 223         if ((code [0] & 0xf8) == 0xb8) {
 224                 /* amd64_set_reg_template */
 225                 *(guint64*)(code + 1) = (guint64)target;
 226         }
 227         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 228                 /* mov 0(%rip), %dreg */
 229                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 230         }
 231         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 232                 /* call *<OFFSET>(%rip) */
 233                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 234         }
 235         else if ((code [0] == 0xe8)) {
 236                 /* call <DISP> */
 237                 gint64 disp = (guint8*)target - (guint8*)code;
 238                 g_assert (amd64_is_imm32 (disp));
 239                 x86_patch (code, (unsigned char*)target);
 240         }
 241         else
 242                 x86_patch (code, (unsigned char*)target);
 243 }
 244
 245 void
 246 mono_amd64_patch (unsigned char* code, gpointer target)
 247 {
 248         amd64_patch (code, target);
 249 }
 250
 251 typedef enum {
 252         ArgInIReg,
 253         ArgInFloatSSEReg,
 254         ArgInDoubleSSEReg,
 255         ArgOnStack,
 256         ArgValuetypeInReg,
 257         ArgValuetypeAddrInIReg,
 258         ArgNone /* only in pair_storage */
 259 } ArgStorage;
 260
 261 typedef struct {
 262         gint16 offset;
 263         gint8  reg;
 264         ArgStorage storage;
 265
 266         /* Only if storage == ArgValuetypeInReg */
 267         ArgStorage pair_storage [2];
 268         gint8 pair_regs [2];
 269 } ArgInfo;
 270
 271 typedef struct {
 272         int nargs;
 273         guint32 stack_usage;
 274         guint32 reg_usage;
 275         guint32 freg_usage;
 276         gboolean need_stack_align;
 277         gboolean vtype_retaddr;
 278         ArgInfo ret;
 279         ArgInfo sig_cookie;
 280         ArgInfo args [1];
 281 } CallInfo;
 282
 283 #define DEBUG(a) if (cfg->verbose_level > 1) a
 284
 285 #ifdef HOST_WIN32
 286 #define PARAM_REGS 4
 287
 288 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 289
 290 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 291 #else
 292 #define PARAM_REGS 6
 293
 294 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 295
 296  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 297 #endif
 298
 299 static void inline
 300 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 301 {
 302     ainfo->offset = *stack_size;
 303
 304     if (*gr >= PARAM_REGS) {
 305                 ainfo->storage = ArgOnStack;
 306                 (*stack_size) += sizeof (gpointer);
 307     }
 308     else {
 309                 ainfo->storage = ArgInIReg;
 310                 ainfo->reg = param_regs [*gr];
 311                 (*gr) ++;
 312     }
 313 }
 314
 315 #ifdef HOST_WIN32
 316 #define FLOAT_PARAM_REGS 4
 317 #else
 318 #define FLOAT_PARAM_REGS 8
 319 #endif
 320
 321 static void inline
 322 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 323 {
 324     ainfo->offset = *stack_size;
 325
 326     if (*gr >= FLOAT_PARAM_REGS) {
 327                 ainfo->storage = ArgOnStack;
 328                 (*stack_size) += sizeof (gpointer);
 329     }
 330     else {
 331                 /* A double register */
 332                 if (is_double)
 333                         ainfo->storage = ArgInDoubleSSEReg;
 334                 else
 335                         ainfo->storage = ArgInFloatSSEReg;
 336                 ainfo->reg = *gr;
 337                 (*gr) += 1;
 338     }
 339 }
 340
 341 typedef enum ArgumentClass {
 342         ARG_CLASS_NO_CLASS,
 343         ARG_CLASS_MEMORY,
 344         ARG_CLASS_INTEGER,
 345         ARG_CLASS_SSE
 346 } ArgumentClass;
 347
 348 static ArgumentClass
 349 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 350 {
 351         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 352         MonoType *ptype;
 353
 354         ptype = mini_type_get_underlying_type (NULL, type);
 355         switch (ptype->type) {
 356         case MONO_TYPE_BOOLEAN:
 357         case MONO_TYPE_CHAR:
 358         case MONO_TYPE_I1:
 359         case MONO_TYPE_U1:
 360         case MONO_TYPE_I2:
 361         case MONO_TYPE_U2:
 362         case MONO_TYPE_I4:
 363         case MONO_TYPE_U4:
 364         case MONO_TYPE_I:
 365         case MONO_TYPE_U:
 366         case MONO_TYPE_STRING:
 367         case MONO_TYPE_OBJECT:
 368         case MONO_TYPE_CLASS:
 369         case MONO_TYPE_SZARRAY:
 370         case MONO_TYPE_PTR:
 371         case MONO_TYPE_FNPTR:
 372         case MONO_TYPE_ARRAY:
 373         case MONO_TYPE_I8:
 374         case MONO_TYPE_U8:
 375                 class2 = ARG_CLASS_INTEGER;
 376                 break;
 377         case MONO_TYPE_R4:
 378         case MONO_TYPE_R8:
 379 #ifdef HOST_WIN32
 380                 class2 = ARG_CLASS_INTEGER;
 381 #else
 382                 class2 = ARG_CLASS_SSE;
 383 #endif
 384                 break;
 385
 386         case MONO_TYPE_TYPEDBYREF:
 387                 g_assert_not_reached ();
 388
 389         case MONO_TYPE_GENERICINST:
 390                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 391                         class2 = ARG_CLASS_INTEGER;
 392                         break;
 393                 }
 394                 /* fall through */
 395         case MONO_TYPE_VALUETYPE: {
 396                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 397                 int i;
 398
 399                 for (i = 0; i < info->num_fields; ++i) {
 400                         class2 = class1;
 401                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 402                 }
 403                 break;
 404         }
 405         default:
 406                 g_assert_not_reached ();
 407         }
 408
 409         /* Merge */
 410         if (class1 == class2)
 411                 ;
 412         else if (class1 == ARG_CLASS_NO_CLASS)
 413                 class1 = class2;
 414         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 415                 class1 = ARG_CLASS_MEMORY;
 416         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 417                 class1 = ARG_CLASS_INTEGER;
 418         else
 419                 class1 = ARG_CLASS_SSE;
 420
 421         return class1;
 422 }
 423
 424 static void
 425 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 426                            gboolean is_return,
 427                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 428 {
 429         guint32 size, quad, nquads, i;
 430         ArgumentClass args [2];
 431         MonoMarshalType *info = NULL;
 432         MonoClass *klass;
 433         MonoGenericSharingContext tmp_gsctx;
 434         gboolean pass_on_stack = FALSE;
 435
 436         /*
 437          * The gsctx currently contains no data, it is only used for checking whenever
 438          * open types are allowed, some callers like mono_arch_get_argument_info ()
 439          * don't pass it to us, so work around that.
 440          */
 441         if (!gsctx)
 442                 gsctx = &tmp_gsctx;
 443
 444         klass = mono_class_from_mono_type (type);
 445         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 446 #ifndef HOST_WIN32
 447         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 448                 /* We pass and return vtypes of size 8 in a register */
 449         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 450                 pass_on_stack = TRUE;
 451         }
 452 #else
 453         if (!sig->pinvoke) {
 454                 pass_on_stack = TRUE;
 455         }
 456 #endif
 457
 458         if (pass_on_stack) {
 459                 /* Allways pass in memory */
 460                 ainfo->offset = *stack_size;
 461                 *stack_size += ALIGN_TO (size, 8);
 462                 ainfo->storage = ArgOnStack;
 463
 464                 return;
 465         }
 466
 467         /* FIXME: Handle structs smaller than 8 bytes */
 468         //if ((size % 8) != 0)
 469         //      NOT_IMPLEMENTED;
 470
 471         if (size > 8)
 472                 nquads = 2;
 473         else
 474                 nquads = 1;
 475
 476         if (!sig->pinvoke) {
 477                 /* Always pass in 1 or 2 integer registers */
 478                 args [0] = ARG_CLASS_INTEGER;
 479                 args [1] = ARG_CLASS_INTEGER;
 480                 /* Only the simplest cases are supported */
 481                 if (is_return && nquads != 1) {
 482                         args [0] = ARG_CLASS_MEMORY;
 483                         args [1] = ARG_CLASS_MEMORY;
 484                 }
 485         } else {
 486                 /*
 487                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 488                  * The X87 and SSEUP stuff is left out since there are no such types in
 489                  * the CLR.
 490                  */
 491                 info = mono_marshal_load_type_info (klass);
 492                 g_assert (info);
 493
 494 #ifndef HOST_WIN32
 495                 if (info->native_size > 16) {
 496                         ainfo->offset = *stack_size;
 497                         *stack_size += ALIGN_TO (info->native_size, 8);
 498                         ainfo->storage = ArgOnStack;
 499
 500                         return;
 501                 }
 502 #else
 503                 switch (info->native_size) {
 504                 case 1: case 2: case 4: case 8:
 505                         break;
 506                 default:
 507                         if (is_return) {
 508                                 ainfo->storage = ArgOnStack;
 509                                 ainfo->offset = *stack_size;
 510                                 *stack_size += ALIGN_TO (info->native_size, 8);
 511                         }
 512                         else {
 513                                 ainfo->storage = ArgValuetypeAddrInIReg;
 514
 515                                 if (*gr < PARAM_REGS) {
 516                                         ainfo->pair_storage [0] = ArgInIReg;
 517                                         ainfo->pair_regs [0] = param_regs [*gr];
 518                                         (*gr) ++;
 519                                 }
 520                                 else {
 521                                         ainfo->pair_storage [0] = ArgOnStack;
 522                                         ainfo->offset = *stack_size;
 523                                         *stack_size += 8;
 524                                 }
 525                         }
 526
 527                         return;
 528                 }
 529 #endif
 530
 531                 args [0] = ARG_CLASS_NO_CLASS;
 532                 args [1] = ARG_CLASS_NO_CLASS;
 533                 for (quad = 0; quad < nquads; ++quad) {
 534                         int size;
 535                         guint32 align;
 536                         ArgumentClass class1;
 537
 538                         if (info->num_fields == 0)
 539                                 class1 = ARG_CLASS_MEMORY;
 540                         else
 541                                 class1 = ARG_CLASS_NO_CLASS;
 542                         for (i = 0; i < info->num_fields; ++i) {
 543                                 size = mono_marshal_type_size (info->fields [i].field->type,
 544                                                                                            info->fields [i].mspec,
 545                                                                                            &align, TRUE, klass->unicode);
 546                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 547                                         /* Unaligned field */
 548                                         NOT_IMPLEMENTED;
 549                                 }
 550
 551                                 /* Skip fields in other quad */
 552                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 553                                         continue;
 554                                 if ((quad == 1) && (info->fields [i].offset < 8))
 555                                         continue;
 556
 557                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 558                         }
 559                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 560                         args [quad] = class1;
 561                 }
 562         }
 563
 564         /* Post merger cleanup */
 565         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 566                 args [0] = args [1] = ARG_CLASS_MEMORY;
 567
 568         /* Allocate registers */
 569         {
 570                 int orig_gr = *gr;
 571                 int orig_fr = *fr;
 572
 573                 ainfo->storage = ArgValuetypeInReg;
 574                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 575                 for (quad = 0; quad < nquads; ++quad) {
 576                         switch (args [quad]) {
 577                         case ARG_CLASS_INTEGER:
 578                                 if (*gr >= PARAM_REGS)
 579                                         args [quad] = ARG_CLASS_MEMORY;
 580                                 else {
 581                                         ainfo->pair_storage [quad] = ArgInIReg;
 582                                         if (is_return)
 583                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 584                                         else
 585                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 586                                         (*gr) ++;
 587                                 }
 588                                 break;
 589                         case ARG_CLASS_SSE:
 590                                 if (*fr >= FLOAT_PARAM_REGS)
 591                                         args [quad] = ARG_CLASS_MEMORY;
 592                                 else {
 593                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 594                                         ainfo->pair_regs [quad] = *fr;
 595                                         (*fr) ++;
 596                                 }
 597                                 break;
 598                         case ARG_CLASS_MEMORY:
 599                                 break;
 600                         default:
 601                                 g_assert_not_reached ();
 602                         }
 603                 }
 604
 605                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 606                         /* Revert possible register assignments */
 607                         *gr = orig_gr;
 608                         *fr = orig_fr;
 609
 610                         ainfo->offset = *stack_size;
 611                         if (sig->pinvoke)
 612                                 *stack_size += ALIGN_TO (info->native_size, 8);
 613                         else
 614                                 *stack_size += nquads * sizeof (gpointer);
 615                         ainfo->storage = ArgOnStack;
 616                 }
 617         }
 618 }
 619
 620 /*
 621  * get_call_info:
 622  *
 623  *  Obtain information about a call according to the calling convention.
 624  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 625  * Draft Version 0.23" document for more information.
 626  */
 627 static CallInfo*
 628 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 629 {
 630         guint32 i, gr, fr;
 631         MonoType *ret_type;
 632         int n = sig->hasthis + sig->param_count;
 633         guint32 stack_size = 0;
 634         CallInfo *cinfo;
 635
 636         if (mp)
 637                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 638         else
 639                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 640
 641         cinfo->nargs = n;
 642
 643         gr = 0;
 644         fr = 0;
 645
 646         /* return value */
 647         {
 648                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 649                 switch (ret_type->type) {
 650                 case MONO_TYPE_BOOLEAN:
 651                 case MONO_TYPE_I1:
 652                 case MONO_TYPE_U1:
 653                 case MONO_TYPE_I2:
 654                 case MONO_TYPE_U2:
 655                 case MONO_TYPE_CHAR:
 656                 case MONO_TYPE_I4:
 657                 case MONO_TYPE_U4:
 658                 case MONO_TYPE_I:
 659                 case MONO_TYPE_U:
 660                 case MONO_TYPE_PTR:
 661                 case MONO_TYPE_FNPTR:
 662                 case MONO_TYPE_CLASS:
 663                 case MONO_TYPE_OBJECT:
 664                 case MONO_TYPE_SZARRAY:
 665                 case MONO_TYPE_ARRAY:
 666                 case MONO_TYPE_STRING:
 667                         cinfo->ret.storage = ArgInIReg;
 668                         cinfo->ret.reg = AMD64_RAX;
 669                         break;
 670                 case MONO_TYPE_U8:
 671                 case MONO_TYPE_I8:
 672                         cinfo->ret.storage = ArgInIReg;
 673                         cinfo->ret.reg = AMD64_RAX;
 674                         break;
 675                 case MONO_TYPE_R4:
 676                         cinfo->ret.storage = ArgInFloatSSEReg;
 677                         cinfo->ret.reg = AMD64_XMM0;
 678                         break;
 679                 case MONO_TYPE_R8:
 680                         cinfo->ret.storage = ArgInDoubleSSEReg;
 681                         cinfo->ret.reg = AMD64_XMM0;
 682                         break;
 683                 case MONO_TYPE_GENERICINST:
 684                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 685                                 cinfo->ret.storage = ArgInIReg;
 686                                 cinfo->ret.reg = AMD64_RAX;
 687                                 break;
 688                         }
 689                         /* fall through */
 690                 case MONO_TYPE_VALUETYPE: {
 691                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 692
 693                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 694                         if (cinfo->ret.storage == ArgOnStack) {
 695                                 cinfo->vtype_retaddr = TRUE;
 696                                 /* The caller passes the address where the value is stored */
 697                                 add_general (&gr, &stack_size, &cinfo->ret);
 698                         }
 699                         break;
 700                 }
 701                 case MONO_TYPE_TYPEDBYREF:
 702                         /* Same as a valuetype with size 24 */
 703                         add_general (&gr, &stack_size, &cinfo->ret);
 704                         ;
 705                         break;
 706                 case MONO_TYPE_VOID:
 707                         break;
 708                 default:
 709                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 710                 }
 711         }
 712
 713         /* this */
 714         if (sig->hasthis)
 715                 add_general (&gr, &stack_size, cinfo->args + 0);
 716
 717         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 718                 gr = PARAM_REGS;
 719                 fr = FLOAT_PARAM_REGS;
 720
 721                 /* Emit the signature cookie just before the implicit arguments */
 722                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 723         }
 724
 725         for (i = 0; i < sig->param_count; ++i) {
 726                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 727                 MonoType *ptype;
 728
 729 #ifdef HOST_WIN32
 730                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 731                 if (gr > fr)
 732                         fr = gr;
 733                 else if (fr > gr)
 734                         gr = fr;
 735 #endif
 736
 737                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 738                         /* We allways pass the sig cookie on the stack for simplicity */
 739                         /*
 740                          * Prevent implicit arguments + the sig cookie from being passed
 741                          * in registers.
 742                          */
 743                         gr = PARAM_REGS;
 744                         fr = FLOAT_PARAM_REGS;
 745
 746                         /* Emit the signature cookie just before the implicit arguments */
 747                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 748                 }
 749
 750                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 751                 switch (ptype->type) {
 752                 case MONO_TYPE_BOOLEAN:
 753                 case MONO_TYPE_I1:
 754                 case MONO_TYPE_U1:
 755                         add_general (&gr, &stack_size, ainfo);
 756                         break;
 757                 case MONO_TYPE_I2:
 758                 case MONO_TYPE_U2:
 759                 case MONO_TYPE_CHAR:
 760                         add_general (&gr, &stack_size, ainfo);
 761                         break;
 762                 case MONO_TYPE_I4:
 763                 case MONO_TYPE_U4:
 764                         add_general (&gr, &stack_size, ainfo);
 765                         break;
 766                 case MONO_TYPE_I:
 767                 case MONO_TYPE_U:
 768                 case MONO_TYPE_PTR:
 769                 case MONO_TYPE_FNPTR:
 770                 case MONO_TYPE_CLASS:
 771                 case MONO_TYPE_OBJECT:
 772                 case MONO_TYPE_STRING:
 773                 case MONO_TYPE_SZARRAY:
 774                 case MONO_TYPE_ARRAY:
 775                         add_general (&gr, &stack_size, ainfo);
 776                         break;
 777                 case MONO_TYPE_GENERICINST:
 778                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 779                                 add_general (&gr, &stack_size, ainfo);
 780                                 break;
 781                         }
 782                         /* fall through */
 783                 case MONO_TYPE_VALUETYPE:
 784                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 785                         break;
 786                 case MONO_TYPE_TYPEDBYREF:
 787 #ifdef HOST_WIN32
 788                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 789 #else
 790                         stack_size += sizeof (MonoTypedRef);
 791                         ainfo->storage = ArgOnStack;
 792 #endif
 793                         break;
 794                 case MONO_TYPE_U8:
 795                 case MONO_TYPE_I8:
 796                         add_general (&gr, &stack_size, ainfo);
 797                         break;
 798                 case MONO_TYPE_R4:
 799                         add_float (&fr, &stack_size, ainfo, FALSE);
 800                         break;
 801                 case MONO_TYPE_R8:
 802                         add_float (&fr, &stack_size, ainfo, TRUE);
 803                         break;
 804                 default:
 805                         g_assert_not_reached ();
 806                 }
 807         }
 808
 809         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 810                 gr = PARAM_REGS;
 811                 fr = FLOAT_PARAM_REGS;
 812
 813                 /* Emit the signature cookie just before the implicit arguments */
 814                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 815         }
 816
 817 #ifdef HOST_WIN32
 818         // There always is 32 bytes reserved on the stack when calling on Winx64
 819         stack_size += 0x20;
 820 #endif
 821
 822         if (stack_size & 0x8) {
 823                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 824                 cinfo->need_stack_align = TRUE;
 825                 stack_size += 8;
 826         }
 827
 828         cinfo->stack_usage = stack_size;
 829         cinfo->reg_usage = gr;
 830         cinfo->freg_usage = fr;
 831         return cinfo;
 832 }
 833
 834 /*
 835  * mono_arch_get_argument_info:
 836  * @csig:  a method signature
 837  * @param_count: the number of parameters to consider
 838  * @arg_info: an array to store the result infos
 839  *
 840  * Gathers information on parameters such as size, alignment and
 841  * padding. arg_info should be large enought to hold param_count + 1 entries.
 842  *
 843  * Returns the size of the argument area on the stack.
 844  */
 845 int
 846 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 847 {
 848         int k;
 849         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 850         guint32 args_size = cinfo->stack_usage;
 851
 852         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 853         if (csig->hasthis) {
 854                 arg_info [0].offset = 0;
 855         }
 856
 857         for (k = 0; k < param_count; k++) {
 858                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 859                 /* FIXME: */
 860                 arg_info [k + 1].size = 0;
 861         }
 862
 863         g_free (cinfo);
 864
 865         return args_size;
 866 }
 867
 868 static int
 869 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 870 {
 871 #ifndef _MSC_VER
 872         __asm__ __volatile__ ("cpuid"
 873                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 874                 : "a" (id));
 875 #else
 876         int info[4];
 877         __cpuid(info, id);
 878         *p_eax = info[0];
 879         *p_ebx = info[1];
 880         *p_ecx = info[2];
 881         *p_edx = info[3];
 882 #endif
 883         return 1;
 884 }
 885
 886 /*
 887  * Initialize the cpu to execute managed code.
 888  */
 889 void
 890 mono_arch_cpu_init (void)
 891 {
 892 #ifndef _MSC_VER
 893         guint16 fpcw;
 894
 895         /* spec compliance requires running with double precision */
 896         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 897         fpcw &= ~X86_FPCW_PRECC_MASK;
 898         fpcw |= X86_FPCW_PREC_DOUBLE;
 899         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 900         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 901 #else
 902         /* TODO: This is crashing on Win64 right now.
 903         * _control87 (_PC_53, MCW_PC);
 904         */
 905 #endif
 906 }
 907
 908 /*
 909  * Initialize architecture specific code.
 910  */
 911 void
 912 mono_arch_init (void)
 913 {
 914         int flags;
 915
 916         InitializeCriticalSection (&mini_arch_mutex);
 917
 918 #ifdef MONO_ARCH_NOMAP32BIT
 919         flags = MONO_MMAP_READ;
 920         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
 921         breakpoint_size = 13;
 922         breakpoint_fault_size = 3;
 923         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
 924         single_step_fault_size = 5;
 925 #else
 926         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
 927         /* amd64_mov_reg_mem () */
 928         breakpoint_size = 8;
 929         breakpoint_fault_size = 8;
 930         single_step_fault_size = 8;
 931 #endif
 932
 933         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 934         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 935         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 936
 937         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
 938         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
 939         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
 940 }
 941
 942 /*
 943  * Cleanup architecture specific code.
 944  */
 945 void
 946 mono_arch_cleanup (void)
 947 {
 948         DeleteCriticalSection (&mini_arch_mutex);
 949 }
 950
 951 /*
 952  * This function returns the optimizations supported on this cpu.
 953  */
 954 guint32
 955 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 956 {
 957         int eax, ebx, ecx, edx;
 958         guint32 opts = 0;
 959
 960         /* FIXME: AMD64 */
 961
 962         *exclude_mask = 0;
 963         /* Feature Flags function, flags returned in EDX. */
 964         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 965                 if (edx & (1 << 15)) {
 966                         opts |= MONO_OPT_CMOV;
 967                         if (edx & 1)
 968                                 opts |= MONO_OPT_FCMOV;
 969                         else
 970                                 *exclude_mask |= MONO_OPT_FCMOV;
 971                 } else
 972                         *exclude_mask |= MONO_OPT_CMOV;
 973         }
 974
 975         return opts;
 976 }
 977
 978 /*
 979  * This function test for all SSE functions supported.
 980  *
 981  * Returns a bitmask corresponding to all supported versions.
 982  *
 983  */
 984 guint32
 985 mono_arch_cpu_enumerate_simd_versions (void)
 986 {
 987         int eax, ebx, ecx, edx;
 988         guint32 sse_opts = 0;
 989
 990         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 991                 if (edx & (1 << 25))
 992                         sse_opts |= SIMD_VERSION_SSE1;
 993                 if (edx & (1 << 26))
 994                         sse_opts |= SIMD_VERSION_SSE2;
 995                 if (ecx & (1 << 0))
 996                         sse_opts |= SIMD_VERSION_SSE3;
 997                 if (ecx & (1 << 9))
 998                         sse_opts |= SIMD_VERSION_SSSE3;
 999                 if (ecx & (1 << 19))
1000                         sse_opts |= SIMD_VERSION_SSE41;
1001                 if (ecx & (1 << 20))
1002                         sse_opts |= SIMD_VERSION_SSE42;
1003         }
1004
1005         /* Yes, all this needs to be done to check for sse4a.
1006            See: "Amd: CPUID Specification"
1007          */
1008         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1009                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1010                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1011                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1012                         if (ecx & (1 << 6))
1013                                 sse_opts |= SIMD_VERSION_SSE4a;
1014                 }
1015         }
1016
1017         return sse_opts;
1018 }
1019
1020 #ifndef DISABLE_JIT
1021
1022 GList *
1023 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1024 {
1025         GList *vars = NULL;
1026         int i;
1027
1028         for (i = 0; i < cfg->num_varinfo; i++) {
1029                 MonoInst *ins = cfg->varinfo [i];
1030                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1031
1032                 /* unused vars */
1033                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1034                         continue;
1035
1036                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1037                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1038                         continue;
1039
1040                 if (mono_is_regsize_var (ins->inst_vtype)) {
1041                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1042                         g_assert (i == vmv->idx);
1043                         vars = g_list_prepend (vars, vmv);
1044                 }
1045         }
1046
1047         vars = mono_varlist_sort (cfg, vars, 0);
1048
1049         return vars;
1050 }
1051
1052 /**
1053  * mono_arch_compute_omit_fp:
1054  *
1055  *   Determine whenever the frame pointer can be eliminated.
1056  */
1057 static void
1058 mono_arch_compute_omit_fp (MonoCompile *cfg)
1059 {
1060         MonoMethodSignature *sig;
1061         MonoMethodHeader *header;
1062         int i, locals_size;
1063         CallInfo *cinfo;
1064
1065         if (cfg->arch.omit_fp_computed)
1066                 return;
1067
1068         header = cfg->header;
1069
1070         sig = mono_method_signature (cfg->method);
1071
1072         if (!cfg->arch.cinfo)
1073                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1074         cinfo = cfg->arch.cinfo;
1075
1076         /*
1077          * FIXME: Remove some of the restrictions.
1078          */
1079         cfg->arch.omit_fp = TRUE;
1080         cfg->arch.omit_fp_computed = TRUE;
1081
1082         if (cfg->disable_omit_fp)
1083                 cfg->arch.omit_fp = FALSE;
1084
1085         if (!debug_omit_fp ())
1086                 cfg->arch.omit_fp = FALSE;
1087         /*
1088         if (cfg->method->save_lmf)
1089                 cfg->arch.omit_fp = FALSE;
1090         */
1091         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1092                 cfg->arch.omit_fp = FALSE;
1093         if (header->num_clauses)
1094                 cfg->arch.omit_fp = FALSE;
1095         if (cfg->param_area)
1096                 cfg->arch.omit_fp = FALSE;
1097         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1098                 cfg->arch.omit_fp = FALSE;
1099         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1100                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1101                 cfg->arch.omit_fp = FALSE;
1102         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1103                 ArgInfo *ainfo = &cinfo->args [i];
1104
1105                 if (ainfo->storage == ArgOnStack) {
1106                         /*
1107                          * The stack offset can only be determined when the frame
1108                          * size is known.
1109                          */
1110                         cfg->arch.omit_fp = FALSE;
1111                 }
1112         }
1113
1114         locals_size = 0;
1115         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1116                 MonoInst *ins = cfg->varinfo [i];
1117                 int ialign;
1118
1119                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1120         }
1121 }
1122
1123 GList *
1124 mono_arch_get_global_int_regs (MonoCompile *cfg)
1125 {
1126         GList *regs = NULL;
1127
1128         mono_arch_compute_omit_fp (cfg);
1129
1130         if (cfg->globalra) {
1131                 if (cfg->arch.omit_fp)
1132                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1133
1134                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1135                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1136                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1137                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1138                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1139
1140                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1141                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1142                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1143                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1144                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1145                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1146                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1147                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1148         } else {
1149                 if (cfg->arch.omit_fp)
1150                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1151
1152                 /* We use the callee saved registers for global allocation */
1153                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1154                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1155                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1156                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1157                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1158 #ifdef HOST_WIN32
1159                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1160                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1161 #endif
1162         }
1163
1164         return regs;
1165 }
1166
1167 GList*
1168 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1169 {
1170         GList *regs = NULL;
1171         int i;
1172
1173         /* All XMM registers */
1174         for (i = 0; i < 16; ++i)
1175                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1176
1177         return regs;
1178 }
1179
1180 GList*
1181 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1182 {
1183         static GList *r = NULL;
1184
1185         if (r == NULL) {
1186                 GList *regs = NULL;
1187
1188                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1189                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1190                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1191                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1192                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1193                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1194
1195                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1196                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1197                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1198                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1199                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1200                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1201                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1202                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1203
1204                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1205         }
1206
1207         return r;
1208 }
1209
1210 GList*
1211 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1212 {
1213         int i;
1214         static GList *r = NULL;
1215
1216         if (r == NULL) {
1217                 GList *regs = NULL;
1218
1219                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1220                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1221
1222                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1223         }
1224
1225         return r;
1226 }
1227
1228 /*
1229  * mono_arch_regalloc_cost:
1230  *
1231  *  Return the cost, in number of memory references, of the action of
1232  * allocating the variable VMV into a register during global register
1233  * allocation.
1234  */
1235 guint32
1236 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1237 {
1238         MonoInst *ins = cfg->varinfo [vmv->idx];
1239
1240         if (cfg->method->save_lmf)
1241                 /* The register is already saved */
1242                 /* substract 1 for the invisible store in the prolog */
1243                 return (ins->opcode == OP_ARG) ? 0 : 1;
1244         else
1245                 /* push+pop */
1246                 return (ins->opcode == OP_ARG) ? 1 : 2;
1247 }
1248
1249 /*
1250  * mono_arch_fill_argument_info:
1251  *
1252  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1253  * of the method.
1254  */
1255 void
1256 mono_arch_fill_argument_info (MonoCompile *cfg)
1257 {
1258         MonoMethodSignature *sig;
1259         MonoMethodHeader *header;
1260         MonoInst *ins;
1261         int i;
1262         CallInfo *cinfo;
1263
1264         header = cfg->header;
1265
1266         sig = mono_method_signature (cfg->method);
1267
1268         cinfo = cfg->arch.cinfo;
1269
1270         /*
1271          * Contrary to mono_arch_allocate_vars (), the information should describe
1272          * where the arguments are at the beginning of the method, not where they can be
1273          * accessed during the execution of the method. The later makes no sense for the
1274          * global register allocator, since a variable can be in more than one location.
1275          */
1276         if (sig->ret->type != MONO_TYPE_VOID) {
1277                 switch (cinfo->ret.storage) {
1278                 case ArgInIReg:
1279                 case ArgInFloatSSEReg:
1280                 case ArgInDoubleSSEReg:
1281                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1282                                 cfg->vret_addr->opcode = OP_REGVAR;
1283                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1284                         }
1285                         else {
1286                                 cfg->ret->opcode = OP_REGVAR;
1287                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1288                         }
1289                         break;
1290                 case ArgValuetypeInReg:
1291                         cfg->ret->opcode = OP_REGOFFSET;
1292                         cfg->ret->inst_basereg = -1;
1293                         cfg->ret->inst_offset = -1;
1294                         break;
1295                 default:
1296                         g_assert_not_reached ();
1297                 }
1298         }
1299
1300         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1301                 ArgInfo *ainfo = &cinfo->args [i];
1302                 MonoType *arg_type;
1303
1304                 ins = cfg->args [i];
1305
1306                 if (sig->hasthis && (i == 0))
1307                         arg_type = &mono_defaults.object_class->byval_arg;
1308                 else
1309                         arg_type = sig->params [i - sig->hasthis];
1310
1311                 switch (ainfo->storage) {
1312                 case ArgInIReg:
1313                 case ArgInFloatSSEReg:
1314                 case ArgInDoubleSSEReg:
1315                         ins->opcode = OP_REGVAR;
1316                         ins->inst_c0 = ainfo->reg;
1317                         break;
1318                 case ArgOnStack:
1319                         ins->opcode = OP_REGOFFSET;
1320                         ins->inst_basereg = -1;
1321                         ins->inst_offset = -1;
1322                         break;
1323                 case ArgValuetypeInReg:
1324                         /* Dummy */
1325                         ins->opcode = OP_NOP;
1326                         break;
1327                 default:
1328                         g_assert_not_reached ();
1329                 }
1330         }
1331 }
1332
1333 void
1334 mono_arch_allocate_vars (MonoCompile *cfg)
1335 {
1336         MonoMethodSignature *sig;
1337         MonoMethodHeader *header;
1338         MonoInst *ins;
1339         int i, offset;
1340         guint32 locals_stack_size, locals_stack_align;
1341         gint32 *offsets;
1342         CallInfo *cinfo;
1343
1344         header = cfg->header;
1345
1346         sig = mono_method_signature (cfg->method);
1347
1348         cinfo = cfg->arch.cinfo;
1349
1350         mono_arch_compute_omit_fp (cfg);
1351
1352         /*
1353          * We use the ABI calling conventions for managed code as well.
1354          * Exception: valuetypes are only sometimes passed or returned in registers.
1355          */
1356
1357         /*
1358          * The stack looks like this:
1359          * <incoming arguments passed on the stack>
1360          * <return value>
1361          * <lmf/caller saved registers>
1362          * <locals>
1363          * <spill area>
1364          * <localloc area>  -> grows dynamically
1365          * <params area>
1366          */
1367
1368         if (cfg->arch.omit_fp) {
1369                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1370                 cfg->frame_reg = AMD64_RSP;
1371                 offset = 0;
1372         } else {
1373                 /* Locals are allocated backwards from %fp */
1374                 cfg->frame_reg = AMD64_RBP;
1375                 offset = 0;
1376         }
1377
1378         if (cfg->method->save_lmf) {
1379                 /* Reserve stack space for saving LMF */
1380                 if (cfg->arch.omit_fp) {
1381                         cfg->arch.lmf_offset = offset;
1382                         offset += sizeof (MonoLMF);
1383                 }
1384                 else {
1385                         offset += sizeof (MonoLMF);
1386                         cfg->arch.lmf_offset = -offset;
1387                 }
1388         } else {
1389                 if (cfg->arch.omit_fp)
1390                         cfg->arch.reg_save_area_offset = offset;
1391                 /* Reserve space for caller saved registers */
1392                 for (i = 0; i < AMD64_NREG; ++i)
1393                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1394                                 offset += sizeof (gpointer);
1395                         }
1396         }
1397
1398         if (sig->ret->type != MONO_TYPE_VOID) {
1399                 switch (cinfo->ret.storage) {
1400                 case ArgInIReg:
1401                 case ArgInFloatSSEReg:
1402                 case ArgInDoubleSSEReg:
1403                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1404                                 if (cfg->globalra) {
1405                                         cfg->vret_addr->opcode = OP_REGVAR;
1406                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1407                                 } else {
1408                                         /* The register is volatile */
1409                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1410                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1411                                         if (cfg->arch.omit_fp) {
1412                                                 cfg->vret_addr->inst_offset = offset;
1413                                                 offset += 8;
1414                                         } else {
1415                                                 offset += 8;
1416                                                 cfg->vret_addr->inst_offset = -offset;
1417                                         }
1418                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1419                                                 printf ("vret_addr =");
1420                                                 mono_print_ins (cfg->vret_addr);
1421                                         }
1422                                 }
1423                         }
1424                         else {
1425                                 cfg->ret->opcode = OP_REGVAR;
1426                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1427                         }
1428                         break;
1429                 case ArgValuetypeInReg:
1430                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1431                         cfg->ret->opcode = OP_REGOFFSET;
1432                         cfg->ret->inst_basereg = cfg->frame_reg;
1433                         if (cfg->arch.omit_fp) {
1434                                 cfg->ret->inst_offset = offset;
1435                                 offset += 16;
1436                         } else {
1437                                 offset += 16;
1438                                 cfg->ret->inst_offset = - offset;
1439                         }
1440                         break;
1441                 default:
1442                         g_assert_not_reached ();
1443                 }
1444                 if (!cfg->globalra)
1445                         cfg->ret->dreg = cfg->ret->inst_c0;
1446         }
1447
1448         /* Allocate locals */
1449         if (!cfg->globalra) {
1450                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1451                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1452                         char *mname = mono_method_full_name (cfg->method, TRUE);
1453                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1454                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1455                         g_free (mname);
1456                         return;
1457                 }
1458
1459                 if (locals_stack_align) {
1460                         offset += (locals_stack_align - 1);
1461                         offset &= ~(locals_stack_align - 1);
1462                 }
1463                 if (cfg->arch.omit_fp) {
1464                         cfg->locals_min_stack_offset = offset;
1465                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1466                 } else {
1467                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1468                         cfg->locals_max_stack_offset = - offset;
1469                 }
1470
1471                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1472                         if (offsets [i] != -1) {
1473                                 MonoInst *ins = cfg->varinfo [i];
1474                                 ins->opcode = OP_REGOFFSET;
1475                                 ins->inst_basereg = cfg->frame_reg;
1476                                 if (cfg->arch.omit_fp)
1477                                         ins->inst_offset = (offset + offsets [i]);
1478                                 else
1479                                         ins->inst_offset = - (offset + offsets [i]);
1480                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1481                         }
1482                 }
1483                 offset += locals_stack_size;
1484         }
1485
1486         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1487                 g_assert (!cfg->arch.omit_fp);
1488                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1489                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1490         }
1491
1492         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1493                 ins = cfg->args [i];
1494                 if (ins->opcode != OP_REGVAR) {
1495                         ArgInfo *ainfo = &cinfo->args [i];
1496                         gboolean inreg = TRUE;
1497                         MonoType *arg_type;
1498
1499                         if (sig->hasthis && (i == 0))
1500                                 arg_type = &mono_defaults.object_class->byval_arg;
1501                         else
1502                                 arg_type = sig->params [i - sig->hasthis];
1503
1504                         if (cfg->globalra) {
1505                                 /* The new allocator needs info about the original locations of the arguments */
1506                                 switch (ainfo->storage) {
1507                                 case ArgInIReg:
1508                                 case ArgInFloatSSEReg:
1509                                 case ArgInDoubleSSEReg:
1510                                         ins->opcode = OP_REGVAR;
1511                                         ins->inst_c0 = ainfo->reg;
1512                                         break;
1513                                 case ArgOnStack:
1514                                         g_assert (!cfg->arch.omit_fp);
1515                                         ins->opcode = OP_REGOFFSET;
1516                                         ins->inst_basereg = cfg->frame_reg;
1517                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1518                                         break;
1519                                 case ArgValuetypeInReg:
1520                                         ins->opcode = OP_REGOFFSET;
1521                                         ins->inst_basereg = cfg->frame_reg;
1522                                         /* These arguments are saved to the stack in the prolog */
1523                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1524                                         if (cfg->arch.omit_fp) {
1525                                                 ins->inst_offset = offset;
1526                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1527                                         } else {
1528                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1529                                                 ins->inst_offset = - offset;
1530                                         }
1531                                         break;
1532                                 default:
1533                                         g_assert_not_reached ();
1534                                 }
1535
1536                                 continue;
1537                         }
1538
1539                         /* FIXME: Allocate volatile arguments to registers */
1540                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1541                                 inreg = FALSE;
1542
1543                         /*
1544                          * Under AMD64, all registers used to pass arguments to functions
1545                          * are volatile across calls.
1546                          * FIXME: Optimize this.
1547                          */
1548                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1549                                 inreg = FALSE;
1550
1551                         ins->opcode = OP_REGOFFSET;
1552
1553                         switch (ainfo->storage) {
1554                         case ArgInIReg:
1555                         case ArgInFloatSSEReg:
1556                         case ArgInDoubleSSEReg:
1557                                 if (inreg) {
1558                                         ins->opcode = OP_REGVAR;
1559                                         ins->dreg = ainfo->reg;
1560                                 }
1561                                 break;
1562                         case ArgOnStack:
1563                                 g_assert (!cfg->arch.omit_fp);
1564                                 ins->opcode = OP_REGOFFSET;
1565                                 ins->inst_basereg = cfg->frame_reg;
1566                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1567                                 break;
1568                         case ArgValuetypeInReg:
1569                                 break;
1570                         case ArgValuetypeAddrInIReg: {
1571                                 MonoInst *indir;
1572                                 g_assert (!cfg->arch.omit_fp);
1573
1574                                 MONO_INST_NEW (cfg, indir, 0);
1575                                 indir->opcode = OP_REGOFFSET;
1576                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1577                                         indir->inst_basereg = cfg->frame_reg;
1578                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1579                                         offset += (sizeof (gpointer));
1580                                         indir->inst_offset = - offset;
1581                                 }
1582                                 else {
1583                                         indir->inst_basereg = cfg->frame_reg;
1584                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1585                                 }
1586
1587                                 ins->opcode = OP_VTARG_ADDR;
1588                                 ins->inst_left = indir;
1589
1590                                 break;
1591                         }
1592                         default:
1593                                 NOT_IMPLEMENTED;
1594                         }
1595
1596                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1597                                 ins->opcode = OP_REGOFFSET;
1598                                 ins->inst_basereg = cfg->frame_reg;
1599                                 /* These arguments are saved to the stack in the prolog */
1600                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1601                                 if (cfg->arch.omit_fp) {
1602                                         ins->inst_offset = offset;
1603                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1604                                         // Arguments are yet supported by the stack map creation code
1605                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1606                                 } else {
1607                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1608                                         ins->inst_offset = - offset;
1609                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1610                                 }
1611                         }
1612                 }
1613         }
1614
1615         cfg->stack_offset = offset;
1616 }
1617
1618 void
1619 mono_arch_create_vars (MonoCompile *cfg)
1620 {
1621         MonoMethodSignature *sig;
1622         CallInfo *cinfo;
1623
1624         sig = mono_method_signature (cfg->method);
1625
1626         if (!cfg->arch.cinfo)
1627                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1628         cinfo = cfg->arch.cinfo;
1629
1630         if (cinfo->ret.storage == ArgValuetypeInReg)
1631                 cfg->ret_var_is_local = TRUE;
1632
1633         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1634                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1635                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1636                         printf ("vret_addr = ");
1637                         mono_print_ins (cfg->vret_addr);
1638                 }
1639         }
1640
1641         if (cfg->gen_seq_points) {
1642                 MonoInst *ins;
1643
1644             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1645                 ins->flags |= MONO_INST_VOLATILE;
1646                 cfg->arch.ss_trigger_page_var = ins;
1647         }
1648
1649 #ifdef MONO_AMD64_NO_PUSHES
1650         /*
1651          * When this is set, we pass arguments on the stack by moves, and by allocating
1652          * a bigger stack frame, instead of pushes.
1653          * Pushes complicate exception handling because the arguments on the stack have
1654          * to be popped each time a frame is unwound. They also make fp elimination
1655          * impossible.
1656          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1657          * on a new frame which doesn't include a param area.
1658          */
1659         cfg->arch.no_pushes = TRUE;
1660 #endif
1661 }
1662
1663 static void
1664 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1665 {
1666         MonoInst *ins;
1667
1668         switch (storage) {
1669         case ArgInIReg:
1670                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1671                 ins->dreg = mono_alloc_ireg (cfg);
1672                 ins->sreg1 = tree->dreg;
1673                 MONO_ADD_INS (cfg->cbb, ins);
1674                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1675                 break;
1676         case ArgInFloatSSEReg:
1677                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1678                 ins->dreg = mono_alloc_freg (cfg);
1679                 ins->sreg1 = tree->dreg;
1680                 MONO_ADD_INS (cfg->cbb, ins);
1681
1682                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1683                 break;
1684         case ArgInDoubleSSEReg:
1685                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1686                 ins->dreg = mono_alloc_freg (cfg);
1687                 ins->sreg1 = tree->dreg;
1688                 MONO_ADD_INS (cfg->cbb, ins);
1689
1690                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1691
1692                 break;
1693         default:
1694                 g_assert_not_reached ();
1695         }
1696 }
1697
1698 static int
1699 arg_storage_to_load_membase (ArgStorage storage)
1700 {
1701         switch (storage) {
1702         case ArgInIReg:
1703                 return OP_LOAD_MEMBASE;
1704         case ArgInDoubleSSEReg:
1705                 return OP_LOADR8_MEMBASE;
1706         case ArgInFloatSSEReg:
1707                 return OP_LOADR4_MEMBASE;
1708         default:
1709                 g_assert_not_reached ();
1710         }
1711
1712         return -1;
1713 }
1714
1715 static void
1716 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1717 {
1718         MonoInst *arg;
1719         MonoMethodSignature *tmp_sig;
1720         MonoInst *sig_arg;
1721
1722         if (call->tail_call)
1723                 NOT_IMPLEMENTED;
1724
1725         /* FIXME: Add support for signature tokens to AOT */
1726         cfg->disable_aot = TRUE;
1727
1728         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1729
1730         /*
1731          * mono_ArgIterator_Setup assumes the signature cookie is
1732          * passed first and all the arguments which were before it are
1733          * passed on the stack after the signature. So compensate by
1734          * passing a different signature.
1735          */
1736         tmp_sig = mono_metadata_signature_dup (call->signature);
1737         tmp_sig->param_count -= call->signature->sentinelpos;
1738         tmp_sig->sentinelpos = 0;
1739         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1740
1741         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1742         sig_arg->dreg = mono_alloc_ireg (cfg);
1743         sig_arg->inst_p0 = tmp_sig;
1744         MONO_ADD_INS (cfg->cbb, sig_arg);
1745
1746         if (cfg->arch.no_pushes) {
1747                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1748         } else {
1749                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1750                 arg->sreg1 = sig_arg->dreg;
1751                 MONO_ADD_INS (cfg->cbb, arg);
1752         }
1753 }
1754
1755 static inline LLVMArgStorage
1756 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1757 {
1758         switch (storage) {
1759         case ArgInIReg:
1760                 return LLVMArgInIReg;
1761         case ArgNone:
1762                 return LLVMArgNone;
1763         default:
1764                 g_assert_not_reached ();
1765                 return LLVMArgNone;
1766         }
1767 }
1768
1769 #ifdef ENABLE_LLVM
1770 LLVMCallInfo*
1771 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1772 {
1773         int i, n;
1774         CallInfo *cinfo;
1775         ArgInfo *ainfo;
1776         int j;
1777         LLVMCallInfo *linfo;
1778         MonoType *t;
1779
1780         n = sig->param_count + sig->hasthis;
1781
1782         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1783
1784         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1785
1786         /*
1787          * LLVM always uses the native ABI while we use our own ABI, the
1788          * only difference is the handling of vtypes:
1789          * - we only pass/receive them in registers in some cases, and only
1790          *   in 1 or 2 integer registers.
1791          */
1792         if (cinfo->ret.storage == ArgValuetypeInReg) {
1793                 if (sig->pinvoke) {
1794                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1795                         cfg->disable_llvm = TRUE;
1796                         return linfo;
1797                 }
1798
1799                 linfo->ret.storage = LLVMArgVtypeInReg;
1800                 for (j = 0; j < 2; ++j)
1801                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1802         }
1803
1804         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1805                 /* Vtype returned using a hidden argument */
1806                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1807         }
1808
1809         for (i = 0; i < n; ++i) {
1810                 ainfo = cinfo->args + i;
1811
1812                 if (i >= sig->hasthis)
1813                         t = sig->params [i - sig->hasthis];
1814                 else
1815                         t = &mono_defaults.int_class->byval_arg;
1816
1817                 linfo->args [i].storage = LLVMArgNone;
1818
1819                 switch (ainfo->storage) {
1820                 case ArgInIReg:
1821                         linfo->args [i].storage = LLVMArgInIReg;
1822                         break;
1823                 case ArgInDoubleSSEReg:
1824                 case ArgInFloatSSEReg:
1825                         linfo->args [i].storage = LLVMArgInFPReg;
1826                         break;
1827                 case ArgOnStack:
1828                         if (MONO_TYPE_ISSTRUCT (t)) {
1829                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1830                         } else {
1831                                 linfo->args [i].storage = LLVMArgInIReg;
1832                                 if (!t->byref) {
1833                                         if (t->type == MONO_TYPE_R4)
1834                                                 linfo->args [i].storage = LLVMArgInFPReg;
1835                                         else if (t->type == MONO_TYPE_R8)
1836                                                 linfo->args [i].storage = LLVMArgInFPReg;
1837                                 }
1838                         }
1839                         break;
1840                 case ArgValuetypeInReg:
1841                         if (sig->pinvoke) {
1842                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1843                                 cfg->disable_llvm = TRUE;
1844                                 return linfo;
1845                         }
1846
1847                         linfo->args [i].storage = LLVMArgVtypeInReg;
1848                         for (j = 0; j < 2; ++j)
1849                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1850                         break;
1851                 default:
1852                         cfg->exception_message = g_strdup ("ainfo->storage");
1853                         cfg->disable_llvm = TRUE;
1854                         break;
1855                 }
1856         }
1857
1858         return linfo;
1859 }
1860 #endif
1861
1862 void
1863 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1864 {
1865         MonoInst *arg, *in;
1866         MonoMethodSignature *sig;
1867         int i, n, stack_size;
1868         CallInfo *cinfo;
1869         ArgInfo *ainfo;
1870
1871         stack_size = 0;
1872
1873         sig = call->signature;
1874         n = sig->param_count + sig->hasthis;
1875
1876         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1877
1878         if (COMPILE_LLVM (cfg)) {
1879                 /* We shouldn't be called in the llvm case */
1880                 cfg->disable_llvm = TRUE;
1881                 return;
1882         }
1883
1884         if (cinfo->need_stack_align) {
1885                 if (!cfg->arch.no_pushes)
1886                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1887         }
1888
1889         /*
1890          * Emit all arguments which are passed on the stack to prevent register
1891          * allocation problems.
1892          */
1893         if (cfg->arch.no_pushes) {
1894                 for (i = 0; i < n; ++i) {
1895                         MonoType *t;
1896                         ainfo = cinfo->args + i;
1897
1898                         in = call->args [i];
1899
1900                         if (sig->hasthis && i == 0)
1901                                 t = &mono_defaults.object_class->byval_arg;
1902                         else
1903                                 t = sig->params [i - sig->hasthis];
1904
1905                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1906                                 if (!t->byref) {
1907                                         if (t->type == MONO_TYPE_R4)
1908                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1909                                         else if (t->type == MONO_TYPE_R8)
1910                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1911                                         else
1912                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1913                                 } else {
1914                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1915                                 }
1916                         }
1917                 }
1918         }
1919
1920         /*
1921          * Emit all parameters passed in registers in non-reverse order for better readability
1922          * and to help the optimization in emit_prolog ().
1923          */
1924         for (i = 0; i < n; ++i) {
1925                 ainfo = cinfo->args + i;
1926
1927                 in = call->args [i];
1928
1929                 if (ainfo->storage == ArgInIReg)
1930                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1931         }
1932
1933         for (i = n - 1; i >= 0; --i) {
1934                 ainfo = cinfo->args + i;
1935
1936                 in = call->args [i];
1937
1938                 switch (ainfo->storage) {
1939                 case ArgInIReg:
1940                         /* Already done */
1941                         break;
1942                 case ArgInFloatSSEReg:
1943                 case ArgInDoubleSSEReg:
1944                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1945                         break;
1946                 case ArgOnStack:
1947                 case ArgValuetypeInReg:
1948                 case ArgValuetypeAddrInIReg:
1949                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1950                                 MonoInst *call_inst = (MonoInst*)call;
1951                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1952                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1953                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1954                                 guint32 align;
1955                                 guint32 size;
1956
1957                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1958                                         size = sizeof (MonoTypedRef);
1959                                         align = sizeof (gpointer);
1960                                 }
1961                                 else {
1962                                         if (sig->pinvoke)
1963                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1964                                         else {
1965                                                 /*
1966                                                  * Other backends use mono_type_stack_size (), but that
1967                                                  * aligns the size to 8, which is larger than the size of
1968                                                  * the source, leading to reads of invalid memory if the
1969                                                  * source is at the end of address space.
1970                                                  */
1971                                                 size = mono_class_value_size (in->klass, &align);
1972                                         }
1973                                 }
1974                                 g_assert (in->klass);
1975
1976                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
1977                                         /* Avoid asserts in emit_memcpy () */
1978                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1979                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
1980                                         /* Continue normally */
1981                                 }
1982
1983                                 if (size > 0) {
1984                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1985                                         arg->sreg1 = in->dreg;
1986                                         arg->klass = in->klass;
1987                                         arg->backend.size = size;
1988                                         arg->inst_p0 = call;
1989                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1990                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1991
1992                                         MONO_ADD_INS (cfg->cbb, arg);
1993                                 }
1994                         } else {
1995                                 if (cfg->arch.no_pushes) {
1996                                         /* Already done */
1997                                 } else {
1998                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1999                                         arg->sreg1 = in->dreg;
2000                                         if (!sig->params [i - sig->hasthis]->byref) {
2001                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2002                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2003                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2004                                                         arg->inst_destbasereg = X86_ESP;
2005                                                         arg->inst_offset = 0;
2006                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2007                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2008                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2009                                                         arg->inst_destbasereg = X86_ESP;
2010                                                         arg->inst_offset = 0;
2011                                                 }
2012                                         }
2013                                         MONO_ADD_INS (cfg->cbb, arg);
2014                                 }
2015                         }
2016                         break;
2017                 default:
2018                         g_assert_not_reached ();
2019                 }
2020
2021                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2022                         /* Emit the signature cookie just before the implicit arguments */
2023                         emit_sig_cookie (cfg, call, cinfo);
2024         }
2025
2026         /* Handle the case where there are no implicit arguments */
2027         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2028                 emit_sig_cookie (cfg, call, cinfo);
2029
2030         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2031                 MonoInst *vtarg;
2032
2033                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2034                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2035                                 /*
2036                                  * Tell the JIT to use a more efficient calling convention: call using
2037                                  * OP_CALL, compute the result location after the call, and save the
2038                                  * result there.
2039                                  */
2040                                 call->vret_in_reg = TRUE;
2041                                 /*
2042                                  * Nullify the instruction computing the vret addr to enable
2043                                  * future optimizations.
2044                                  */
2045                                 if (call->vret_var)
2046                                         NULLIFY_INS (call->vret_var);
2047                         } else {
2048                                 if (call->tail_call)
2049                                         NOT_IMPLEMENTED;
2050                                 /*
2051                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2052                                  * the stack. Push the address here, so the call instruction can
2053                                  * access it.
2054                                  */
2055                                 if (!cfg->arch.vret_addr_loc) {
2056                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2057                                         /* Prevent it from being register allocated or optimized away */
2058                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2059                                 }
2060
2061                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2062                         }
2063                 }
2064                 else {
2065                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2066                         vtarg->sreg1 = call->vret_var->dreg;
2067                         vtarg->dreg = mono_alloc_preg (cfg);
2068                         MONO_ADD_INS (cfg->cbb, vtarg);
2069
2070                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2071                 }
2072         }
2073
2074 #ifdef HOST_WIN32
2075         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2076                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2077         }
2078 #endif
2079
2080         if (cfg->method->save_lmf) {
2081                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2082                 MONO_ADD_INS (cfg->cbb, arg);
2083         }
2084
2085         call->stack_usage = cinfo->stack_usage;
2086 }
2087
2088 void
2089 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2090 {
2091         MonoInst *arg;
2092         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2093         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2094         int size = ins->backend.size;
2095
2096         if (ainfo->storage == ArgValuetypeInReg) {
2097                 MonoInst *load;
2098                 int part;
2099
2100                 for (part = 0; part < 2; ++part) {
2101                         if (ainfo->pair_storage [part] == ArgNone)
2102                                 continue;
2103
2104                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2105                         load->inst_basereg = src->dreg;
2106                         load->inst_offset = part * sizeof (gpointer);
2107
2108                         switch (ainfo->pair_storage [part]) {
2109                         case ArgInIReg:
2110                                 load->dreg = mono_alloc_ireg (cfg);
2111                                 break;
2112                         case ArgInDoubleSSEReg:
2113                         case ArgInFloatSSEReg:
2114                                 load->dreg = mono_alloc_freg (cfg);
2115                                 break;
2116                         default:
2117                                 g_assert_not_reached ();
2118                         }
2119                         MONO_ADD_INS (cfg->cbb, load);
2120
2121                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2122                 }
2123         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2124                 MonoInst *vtaddr, *load;
2125                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2126
2127                 g_assert (!cfg->arch.no_pushes);
2128
2129                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2130                 load->inst_p0 = vtaddr;
2131                 vtaddr->flags |= MONO_INST_INDIRECT;
2132                 load->type = STACK_MP;
2133                 load->klass = vtaddr->klass;
2134                 load->dreg = mono_alloc_ireg (cfg);
2135                 MONO_ADD_INS (cfg->cbb, load);
2136                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2137
2138                 if (ainfo->pair_storage [0] == ArgInIReg) {
2139                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2140                         arg->dreg = mono_alloc_ireg (cfg);
2141                         arg->sreg1 = load->dreg;
2142                         arg->inst_imm = 0;
2143                         MONO_ADD_INS (cfg->cbb, arg);
2144                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2145                 } else {
2146                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2147                         arg->sreg1 = load->dreg;
2148                         MONO_ADD_INS (cfg->cbb, arg);
2149                 }
2150         } else {
2151                 if (size == 8) {
2152                         if (cfg->arch.no_pushes) {
2153                                 int dreg = mono_alloc_ireg (cfg);
2154
2155                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2156                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2157                         } else {
2158                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2159                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2160                                 arg->inst_basereg = src->dreg;
2161                                 arg->inst_offset = 0;
2162                                 MONO_ADD_INS (cfg->cbb, arg);
2163                         }
2164                 } else if (size <= 40) {
2165                         if (cfg->arch.no_pushes) {
2166                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2167                         } else {
2168                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2169                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2170                         }
2171                 } else {
2172                         if (cfg->arch.no_pushes) {
2173                                 // FIXME: Code growth
2174                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2175                         } else {
2176                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2177                                 arg->inst_basereg = src->dreg;
2178                                 arg->inst_offset = 0;
2179                                 arg->inst_imm = size;
2180                                 MONO_ADD_INS (cfg->cbb, arg);
2181                         }
2182                 }
2183         }
2184 }
2185
2186 void
2187 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2188 {
2189         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2190
2191         if (ret->type == MONO_TYPE_R4) {
2192                 if (COMPILE_LLVM (cfg))
2193                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2194                 else
2195                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2196                 return;
2197         } else if (ret->type == MONO_TYPE_R8) {
2198                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2199                 return;
2200         }
2201
2202         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2203 }
2204
2205 #endif /* DISABLE_JIT */
2206
2207 #define EMIT_COND_BRANCH(ins,cond,sign) \
2208         if (ins->inst_true_bb->native_offset) { \
2209                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2210         } else { \
2211                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2212                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2213             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2214                         x86_branch8 (code, cond, 0, sign); \
2215                 else \
2216                         x86_branch32 (code, cond, 0, sign); \
2217 }
2218
2219 typedef struct {
2220         MonoMethodSignature *sig;
2221         CallInfo *cinfo;
2222 } ArchDynCallInfo;
2223
2224 typedef struct {
2225         mgreg_t regs [PARAM_REGS];
2226         mgreg_t res;
2227         guint8 *ret;
2228 } DynCallArgs;
2229
2230 static gboolean
2231 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2232 {
2233         int i;
2234
2235 #ifdef HOST_WIN32
2236         return FALSE;
2237 #endif
2238
2239         switch (cinfo->ret.storage) {
2240         case ArgNone:
2241         case ArgInIReg:
2242                 break;
2243         case ArgValuetypeInReg: {
2244                 ArgInfo *ainfo = &cinfo->ret;
2245
2246                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2247                         return FALSE;
2248                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2249                         return FALSE;
2250                 break;
2251         }
2252         default:
2253                 return FALSE;
2254         }
2255
2256         for (i = 0; i < cinfo->nargs; ++i) {
2257                 ArgInfo *ainfo = &cinfo->args [i];
2258                 switch (ainfo->storage) {
2259                 case ArgInIReg:
2260                         break;
2261                 case ArgValuetypeInReg:
2262                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2263                                 return FALSE;
2264                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2265                                 return FALSE;
2266                         break;
2267                 default:
2268                         return FALSE;
2269                 }
2270         }
2271
2272         return TRUE;
2273 }
2274
2275 /*
2276  * mono_arch_dyn_call_prepare:
2277  *
2278  *   Return a pointer to an arch-specific structure which contains information
2279  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2280  * supported for SIG.
2281  * This function is equivalent to ffi_prep_cif in libffi.
2282  */
2283 MonoDynCallInfo*
2284 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2285 {
2286         ArchDynCallInfo *info;
2287         CallInfo *cinfo;
2288
2289         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2290
2291         if (!dyn_call_supported (sig, cinfo)) {
2292                 g_free (cinfo);
2293                 return NULL;
2294         }
2295
2296         info = g_new0 (ArchDynCallInfo, 1);
2297         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2298         info->sig = sig;
2299         info->cinfo = cinfo;
2300
2301         return (MonoDynCallInfo*)info;
2302 }
2303
2304 /*
2305  * mono_arch_dyn_call_free:
2306  *
2307  *   Free a MonoDynCallInfo structure.
2308  */
2309 void
2310 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2311 {
2312         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2313
2314         g_free (ainfo->cinfo);
2315         g_free (ainfo);
2316 }
2317
2318 /*
2319  * mono_arch_get_start_dyn_call:
2320  *
2321  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2322  * store the result into BUF.
2323  * ARGS should be an array of pointers pointing to the arguments.
2324  * RET should point to a memory buffer large enought to hold the result of the
2325  * call.
2326  * This function should be as fast as possible, any work which does not depend
2327  * on the actual values of the arguments should be done in
2328  * mono_arch_dyn_call_prepare ().
2329  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2330  * libffi.
2331  */
2332 void
2333 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2334 {
2335         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2336         DynCallArgs *p = (DynCallArgs*)buf;
2337         int arg_index, greg, i;
2338         MonoMethodSignature *sig = dinfo->sig;
2339
2340         g_assert (buf_len >= sizeof (DynCallArgs));
2341
2342         p->res = 0;
2343         p->ret = ret;
2344
2345         arg_index = 0;
2346         greg = 0;
2347
2348         if (dinfo->cinfo->vtype_retaddr)
2349                 p->regs [greg ++] = (mgreg_t)ret;
2350
2351         if (sig->hasthis) {
2352                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2353         }
2354
2355         for (i = 0; i < sig->param_count; i++) {
2356                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2357                 gpointer *arg = args [arg_index ++];
2358
2359                 if (t->byref) {
2360                         p->regs [greg ++] = (mgreg_t)*(arg);
2361                         continue;
2362                 }
2363
2364                 switch (t->type) {
2365                 case MONO_TYPE_STRING:
2366                 case MONO_TYPE_CLASS:
2367                 case MONO_TYPE_ARRAY:
2368                 case MONO_TYPE_SZARRAY:
2369                 case MONO_TYPE_OBJECT:
2370                 case MONO_TYPE_PTR:
2371                 case MONO_TYPE_I:
2372                 case MONO_TYPE_U:
2373                 case MONO_TYPE_I8:
2374                 case MONO_TYPE_U8:
2375                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2376                         p->regs [greg ++] = (mgreg_t)*(arg);
2377                         break;
2378                 case MONO_TYPE_BOOLEAN:
2379                 case MONO_TYPE_U1:
2380                         p->regs [greg ++] = *(guint8*)(arg);
2381                         break;
2382                 case MONO_TYPE_I1:
2383                         p->regs [greg ++] = *(gint8*)(arg);
2384                         break;
2385                 case MONO_TYPE_I2:
2386                         p->regs [greg ++] = *(gint16*)(arg);
2387                         break;
2388                 case MONO_TYPE_U2:
2389                 case MONO_TYPE_CHAR:
2390                         p->regs [greg ++] = *(guint16*)(arg);
2391                         break;
2392                 case MONO_TYPE_I4:
2393                         p->regs [greg ++] = *(gint32*)(arg);
2394                         break;
2395                 case MONO_TYPE_U4:
2396                         p->regs [greg ++] = *(guint32*)(arg);
2397                         break;
2398                 case MONO_TYPE_GENERICINST:
2399                     if (MONO_TYPE_IS_REFERENCE (t)) {
2400                                 p->regs [greg ++] = (mgreg_t)*(arg);
2401                                 break;
2402                         } else {
2403                                 /* Fall through */
2404                         }
2405                 case MONO_TYPE_VALUETYPE: {
2406                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2407
2408                         g_assert (ainfo->storage == ArgValuetypeInReg);
2409                         if (ainfo->pair_storage [0] != ArgNone) {
2410                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2411                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2412                         }
2413                         if (ainfo->pair_storage [1] != ArgNone) {
2414                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2415                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2416                         }
2417                         break;
2418                 }
2419                 default:
2420                         g_assert_not_reached ();
2421                 }
2422         }
2423
2424         g_assert (greg <= PARAM_REGS);
2425 }
2426
2427 /*
2428  * mono_arch_finish_dyn_call:
2429  *
2430  *   Store the result of a dyn call into the return value buffer passed to
2431  * start_dyn_call ().
2432  * This function should be as fast as possible, any work which does not depend
2433  * on the actual values of the arguments should be done in
2434  * mono_arch_dyn_call_prepare ().
2435  */
2436 void
2437 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2438 {
2439         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2440         MonoMethodSignature *sig = dinfo->sig;
2441         guint8 *ret = ((DynCallArgs*)buf)->ret;
2442         mgreg_t res = ((DynCallArgs*)buf)->res;
2443
2444         switch (mono_type_get_underlying_type (sig->ret)->type) {
2445         case MONO_TYPE_VOID:
2446                 *(gpointer*)ret = NULL;
2447                 break;
2448         case MONO_TYPE_STRING:
2449         case MONO_TYPE_CLASS:
2450         case MONO_TYPE_ARRAY:
2451         case MONO_TYPE_SZARRAY:
2452         case MONO_TYPE_OBJECT:
2453         case MONO_TYPE_I:
2454         case MONO_TYPE_U:
2455         case MONO_TYPE_PTR:
2456                 *(gpointer*)ret = (gpointer)res;
2457                 break;
2458         case MONO_TYPE_I1:
2459                 *(gint8*)ret = res;
2460                 break;
2461         case MONO_TYPE_U1:
2462         case MONO_TYPE_BOOLEAN:
2463                 *(guint8*)ret = res;
2464                 break;
2465         case MONO_TYPE_I2:
2466                 *(gint16*)ret = res;
2467                 break;
2468         case MONO_TYPE_U2:
2469         case MONO_TYPE_CHAR:
2470                 *(guint16*)ret = res;
2471                 break;
2472         case MONO_TYPE_I4:
2473                 *(gint32*)ret = res;
2474                 break;
2475         case MONO_TYPE_U4:
2476                 *(guint32*)ret = res;
2477                 break;
2478         case MONO_TYPE_I8:
2479                 *(gint64*)ret = res;
2480                 break;
2481         case MONO_TYPE_U8:
2482                 *(guint64*)ret = res;
2483                 break;
2484         case MONO_TYPE_GENERICINST:
2485                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2486                         *(gpointer*)ret = (gpointer)res;
2487                         break;
2488                 } else {
2489                         /* Fall through */
2490                 }
2491         case MONO_TYPE_VALUETYPE:
2492                 if (dinfo->cinfo->vtype_retaddr) {
2493                         /* Nothing to do */
2494                 } else {
2495                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2496
2497                         g_assert (ainfo->storage == ArgValuetypeInReg);
2498
2499                         if (ainfo->pair_storage [0] != ArgNone) {
2500                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2501                                 ((mgreg_t*)ret)[0] = res;
2502                         }
2503
2504                         g_assert (ainfo->pair_storage [1] == ArgNone);
2505                 }
2506                 break;
2507         default:
2508                 g_assert_not_reached ();
2509         }
2510 }
2511
2512 /* emit an exception if condition is fail */
2513 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2514         do {                                                        \
2515                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2516                 if (tins == NULL) {                                                                             \
2517                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2518                                         MONO_PATCH_INFO_EXC, exc_name);  \
2519                         x86_branch32 (code, cond, 0, signed);               \
2520                 } else {        \
2521                         EMIT_COND_BRANCH (tins, cond, signed);  \
2522                 }                       \
2523         } while (0);
2524
2525 #define EMIT_FPCOMPARE(code) do { \
2526         amd64_fcompp (code); \
2527         amd64_fnstsw (code); \
2528 } while (0);
2529
2530 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2531     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2532         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2533         amd64_ ##op (code); \
2534         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2535         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2536 } while (0);
2537
2538 static guint8*
2539 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2540 {
2541         gboolean no_patch = FALSE;
2542
2543         /*
2544          * FIXME: Add support for thunks
2545          */
2546         {
2547                 gboolean near_call = FALSE;
2548
2549                 /*
2550                  * Indirect calls are expensive so try to make a near call if possible.
2551                  * The caller memory is allocated by the code manager so it is
2552                  * guaranteed to be at a 32 bit offset.
2553                  */
2554
2555                 if (patch_type != MONO_PATCH_INFO_ABS) {
2556                         /* The target is in memory allocated using the code manager */
2557                         near_call = TRUE;
2558
2559                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2560                                 if (((MonoMethod*)data)->klass->image->aot_module)
2561                                         /* The callee might be an AOT method */
2562                                         near_call = FALSE;
2563                                 if (((MonoMethod*)data)->dynamic)
2564                                         /* The target is in malloc-ed memory */
2565                                         near_call = FALSE;
2566                         }
2567
2568                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2569                                 /*
2570                                  * The call might go directly to a native function without
2571                                  * the wrapper.
2572                                  */
2573                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2574                                 if (mi) {
2575                                         gconstpointer target = mono_icall_get_wrapper (mi);
2576                                         if ((((guint64)target) >> 32) != 0)
2577                                                 near_call = FALSE;
2578                                 }
2579                         }
2580                 }
2581                 else {
2582                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2583                                 /*
2584                                  * This is not really an optimization, but required because the
2585                                  * generic class init trampolines use R11 to pass the vtable.
2586                                  */
2587                                 near_call = TRUE;
2588                         } else {
2589                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2590                                 if (info) {
2591                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2592                                                 strstr (cfg->method->name, info->name)) {
2593                                                 /* A call to the wrapped function */
2594                                                 if ((((guint64)data) >> 32) == 0)
2595                                                         near_call = TRUE;
2596                                                 no_patch = TRUE;
2597                                         }
2598                                         else if (info->func == info->wrapper) {
2599                                                 /* No wrapper */
2600                                                 if ((((guint64)info->func) >> 32) == 0)
2601                                                         near_call = TRUE;
2602                                         }
2603                                         else {
2604                                                 /* See the comment in mono_codegen () */
2605                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2606                                                         near_call = TRUE;
2607                                         }
2608                                 }
2609                                 else if ((((guint64)data) >> 32) == 0) {
2610                                         near_call = TRUE;
2611                                         no_patch = TRUE;
2612                                 }
2613                         }
2614                 }
2615
2616                 if (cfg->method->dynamic)
2617                         /* These methods are allocated using malloc */
2618                         near_call = FALSE;
2619
2620 #ifdef MONO_ARCH_NOMAP32BIT
2621                 near_call = FALSE;
2622 #endif
2623
2624                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2625                 if (optimize_for_xen)
2626                         near_call = FALSE;
2627
2628                 if (cfg->compile_aot) {
2629                         near_call = TRUE;
2630                         no_patch = TRUE;
2631                 }
2632
2633                 if (near_call) {
2634                         /*
2635                          * Align the call displacement to an address divisible by 4 so it does
2636                          * not span cache lines. This is required for code patching to work on SMP
2637                          * systems.
2638                          */
2639                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2640                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2641                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2642                         amd64_call_code (code, 0);
2643                 }
2644                 else {
2645                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2646                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2647                         amd64_call_reg (code, GP_SCRATCH_REG);
2648                 }
2649         }
2650
2651         return code;
2652 }
2653
2654 static inline guint8*
2655 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2656 {
2657 #ifdef HOST_WIN32
2658         if (win64_adjust_stack)
2659                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2660 #endif
2661         code = emit_call_body (cfg, code, patch_type, data);
2662 #ifdef HOST_WIN32
2663         if (win64_adjust_stack)
2664                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2665 #endif
2666
2667         return code;
2668 }
2669
2670 static inline int
2671 store_membase_imm_to_store_membase_reg (int opcode)
2672 {
2673         switch (opcode) {
2674         case OP_STORE_MEMBASE_IMM:
2675                 return OP_STORE_MEMBASE_REG;
2676         case OP_STOREI4_MEMBASE_IMM:
2677                 return OP_STOREI4_MEMBASE_REG;
2678         case OP_STOREI8_MEMBASE_IMM:
2679                 return OP_STOREI8_MEMBASE_REG;
2680         }
2681
2682         return -1;
2683 }
2684
2685 #ifndef DISABLE_JIT
2686
2687 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2688
2689 /*
2690  * mono_arch_peephole_pass_1:
2691  *
2692  *   Perform peephole opts which should/can be performed before local regalloc
2693  */
2694 void
2695 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2696 {
2697         MonoInst *ins, *n;
2698
2699         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2700                 MonoInst *last_ins = ins->prev;
2701
2702                 switch (ins->opcode) {
2703                 case OP_ADD_IMM:
2704                 case OP_IADD_IMM:
2705                 case OP_LADD_IMM:
2706                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2707                                 /*
2708                                  * X86_LEA is like ADD, but doesn't have the
2709                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2710                                  * its operand to 64 bit.
2711                                  */
2712                                 ins->opcode = OP_X86_LEA_MEMBASE;
2713                                 ins->inst_basereg = ins->sreg1;
2714                         }
2715                         break;
2716                 case OP_LXOR:
2717                 case OP_IXOR:
2718                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2719                                 MonoInst *ins2;
2720
2721                                 /*
2722                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2723                                  * the latter has length 2-3 instead of 6 (reverse constant
2724                                  * propagation). These instruction sequences are very common
2725                                  * in the initlocals bblock.
2726                                  */
2727                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2728                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2729                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2730                                                 ins2->sreg1 = ins->dreg;
2731                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2732                                                 /* Continue */
2733                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2734                                                 NULLIFY_INS (ins2);
2735                                                 /* Continue */
2736                                         } else {
2737                                                 break;
2738                                         }
2739                                 }
2740                         }
2741                         break;
2742                 case OP_COMPARE_IMM:
2743                 case OP_LCOMPARE_IMM:
2744                         /* OP_COMPARE_IMM (reg, 0)
2745                          * -->
2746                          * OP_AMD64_TEST_NULL (reg)
2747                          */
2748                         if (!ins->inst_imm)
2749                                 ins->opcode = OP_AMD64_TEST_NULL;
2750                         break;
2751                 case OP_ICOMPARE_IMM:
2752                         if (!ins->inst_imm)
2753                                 ins->opcode = OP_X86_TEST_NULL;
2754                         break;
2755                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2756                         /*
2757                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2758                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2759                          * -->
2760                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2761                          * OP_COMPARE_IMM reg, imm
2762                          *
2763                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2764                          */
2765                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2766                             ins->inst_basereg == last_ins->inst_destbasereg &&
2767                             ins->inst_offset == last_ins->inst_offset) {
2768                                         ins->opcode = OP_ICOMPARE_IMM;
2769                                         ins->sreg1 = last_ins->sreg1;
2770
2771                                         /* check if we can remove cmp reg,0 with test null */
2772                                         if (!ins->inst_imm)
2773                                                 ins->opcode = OP_X86_TEST_NULL;
2774                                 }
2775
2776                         break;
2777                 }
2778
2779                 mono_peephole_ins (bb, ins);
2780         }
2781 }
2782
2783 void
2784 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2785 {
2786         MonoInst *ins, *n;
2787
2788         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2789                 switch (ins->opcode) {
2790                 case OP_ICONST:
2791                 case OP_I8CONST: {
2792                         /* reg = 0 -> XOR (reg, reg) */
2793                         /* XOR sets cflags on x86, so we cant do it always */
2794                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2795                                 ins->opcode = OP_LXOR;
2796                                 ins->sreg1 = ins->dreg;
2797                                 ins->sreg2 = ins->dreg;
2798                                 /* Fall through */
2799                         } else {
2800                                 break;
2801                         }
2802                 }
2803                 case OP_LXOR:
2804                         /*
2805                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2806                          * 0 result into 64 bits.
2807                          */
2808                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2809                                 ins->opcode = OP_IXOR;
2810                         }
2811                         /* Fall through */
2812                 case OP_IXOR:
2813                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2814                                 MonoInst *ins2;
2815
2816                                 /*
2817                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2818                                  * the latter has length 2-3 instead of 6 (reverse constant
2819                                  * propagation). These instruction sequences are very common
2820                                  * in the initlocals bblock.
2821                                  */
2822                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2823                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2824                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2825                                                 ins2->sreg1 = ins->dreg;
2826                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2827                                                 /* Continue */
2828                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2829                                                 NULLIFY_INS (ins2);
2830                                                 /* Continue */
2831                                         } else {
2832                                                 break;
2833                                         }
2834                                 }
2835                         }
2836                         break;
2837                 case OP_IADD_IMM:
2838                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2839                                 ins->opcode = OP_X86_INC_REG;
2840                         break;
2841                 case OP_ISUB_IMM:
2842                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2843                                 ins->opcode = OP_X86_DEC_REG;
2844                         break;
2845                 }
2846
2847                 mono_peephole_ins (bb, ins);
2848         }
2849 }
2850
2851 #define NEW_INS(cfg,ins,dest,op) do {   \
2852                 MONO_INST_NEW ((cfg), (dest), (op)); \
2853         (dest)->cil_code = (ins)->cil_code; \
2854         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2855         } while (0)
2856
2857 /*
2858  * mono_arch_lowering_pass:
2859  *
2860  *  Converts complex opcodes into simpler ones so that each IR instruction
2861  * corresponds to one machine instruction.
2862  */
2863 void
2864 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2865 {
2866         MonoInst *ins, *n, *temp;
2867
2868         /*
2869          * FIXME: Need to add more instructions, but the current machine
2870          * description can't model some parts of the composite instructions like
2871          * cdq.
2872          */
2873         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2874                 switch (ins->opcode) {
2875                 case OP_DIV_IMM:
2876                 case OP_REM_IMM:
2877                 case OP_IDIV_IMM:
2878                 case OP_IDIV_UN_IMM:
2879                 case OP_IREM_UN_IMM:
2880                         mono_decompose_op_imm (cfg, bb, ins);
2881                         break;
2882                 case OP_IREM_IMM:
2883                         /* Keep the opcode if we can implement it efficiently */
2884                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2885                                 mono_decompose_op_imm (cfg, bb, ins);
2886                         break;
2887                 case OP_COMPARE_IMM:
2888                 case OP_LCOMPARE_IMM:
2889                         if (!amd64_is_imm32 (ins->inst_imm)) {
2890                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2891                                 temp->inst_c0 = ins->inst_imm;
2892                                 temp->dreg = mono_alloc_ireg (cfg);
2893                                 ins->opcode = OP_COMPARE;
2894                                 ins->sreg2 = temp->dreg;
2895                         }
2896                         break;
2897                 case OP_LOAD_MEMBASE:
2898                 case OP_LOADI8_MEMBASE:
2899                         if (!amd64_is_imm32 (ins->inst_offset)) {
2900                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2901                                 temp->inst_c0 = ins->inst_offset;
2902                                 temp->dreg = mono_alloc_ireg (cfg);
2903                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2904                                 ins->inst_indexreg = temp->dreg;
2905                         }
2906                         break;
2907                 case OP_STORE_MEMBASE_IMM:
2908                 case OP_STOREI8_MEMBASE_IMM:
2909                         if (!amd64_is_imm32 (ins->inst_imm)) {
2910                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2911                                 temp->inst_c0 = ins->inst_imm;
2912                                 temp->dreg = mono_alloc_ireg (cfg);
2913                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2914                                 ins->sreg1 = temp->dreg;
2915                         }
2916                         break;
2917 #ifdef MONO_ARCH_SIMD_INTRINSICS
2918                 case OP_EXPAND_I1: {
2919                                 int temp_reg1 = mono_alloc_ireg (cfg);
2920                                 int temp_reg2 = mono_alloc_ireg (cfg);
2921                                 int original_reg = ins->sreg1;
2922
2923                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2924                                 temp->sreg1 = original_reg;
2925                                 temp->dreg = temp_reg1;
2926
2927                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2928                                 temp->sreg1 = temp_reg1;
2929                                 temp->dreg = temp_reg2;
2930                                 temp->inst_imm = 8;
2931
2932                                 NEW_INS (cfg, ins, temp, OP_LOR);
2933                                 temp->sreg1 = temp->dreg = temp_reg2;
2934                                 temp->sreg2 = temp_reg1;
2935
2936                                 ins->opcode = OP_EXPAND_I2;
2937                                 ins->sreg1 = temp_reg2;
2938                         }
2939                         break;
2940 #endif
2941                 default:
2942                         break;
2943                 }
2944         }
2945
2946         bb->max_vreg = cfg->next_vreg;
2947 }
2948
2949 static const int
2950 branch_cc_table [] = {
2951         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2952         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2953         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2954 };
2955
2956 /* Maps CMP_... constants to X86_CC_... constants */
2957 static const int
2958 cc_table [] = {
2959         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2960         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2961 };
2962
2963 static const int
2964 cc_signed_table [] = {
2965         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2966         FALSE, FALSE, FALSE, FALSE
2967 };
2968
2969 /*#include "cprop.c"*/
2970
2971 static unsigned char*
2972 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2973 {
2974         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2975
2976         if (size == 1)
2977                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2978         else if (size == 2)
2979                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2980         return code;
2981 }
2982
2983 static unsigned char*
2984 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2985 {
2986         int sreg = tree->sreg1;
2987         int need_touch = FALSE;
2988
2989 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2990         if (!tree->flags & MONO_INST_INIT)
2991                 need_touch = TRUE;
2992 #endif
2993
2994         if (need_touch) {
2995                 guint8* br[5];
2996
2997                 /*
2998                  * Under Windows:
2999                  * If requested stack size is larger than one page,
3000                  * perform stack-touch operation
3001                  */
3002                 /*
3003                  * Generate stack probe code.
3004                  * Under Windows, it is necessary to allocate one page at a time,
3005                  * "touching" stack after each successful sub-allocation. This is
3006                  * because of the way stack growth is implemented - there is a
3007                  * guard page before the lowest stack page that is currently commited.
3008                  * Stack normally grows sequentially so OS traps access to the
3009                  * guard page and commits more pages when needed.
3010                  */
3011                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3012                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3013
3014                 br[2] = code; /* loop */
3015                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3016                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3017                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3018                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3019                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3020                 amd64_patch (br[3], br[2]);
3021                 amd64_test_reg_reg (code, sreg, sreg);
3022                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3023                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3024
3025                 br[1] = code; x86_jump8 (code, 0);
3026
3027                 amd64_patch (br[0], code);
3028                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3029                 amd64_patch (br[1], code);
3030                 amd64_patch (br[4], code);
3031         }
3032         else
3033                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3034
3035         if (tree->flags & MONO_INST_INIT) {
3036                 int offset = 0;
3037                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3038                         amd64_push_reg (code, AMD64_RAX);
3039                         offset += 8;
3040                 }
3041                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3042                         amd64_push_reg (code, AMD64_RCX);
3043                         offset += 8;
3044                 }
3045                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3046                         amd64_push_reg (code, AMD64_RDI);
3047                         offset += 8;
3048                 }
3049
3050                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3051                 if (sreg != AMD64_RCX)
3052                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3053                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3054
3055                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3056                 if (cfg->param_area && cfg->arch.no_pushes)
3057                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3058                 amd64_cld (code);
3059                 amd64_prefix (code, X86_REP_PREFIX);
3060                 amd64_stosl (code);
3061
3062                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3063                         amd64_pop_reg (code, AMD64_RDI);
3064                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3065                         amd64_pop_reg (code, AMD64_RCX);
3066                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3067                         amd64_pop_reg (code, AMD64_RAX);
3068         }
3069         return code;
3070 }
3071
3072 static guint8*
3073 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3074 {
3075         CallInfo *cinfo;
3076         guint32 quad;
3077
3078         /* Move return value to the target register */
3079         /* FIXME: do this in the local reg allocator */
3080         switch (ins->opcode) {
3081         case OP_CALL:
3082         case OP_CALL_REG:
3083         case OP_CALL_MEMBASE:
3084         case OP_LCALL:
3085         case OP_LCALL_REG:
3086         case OP_LCALL_MEMBASE:
3087                 g_assert (ins->dreg == AMD64_RAX);
3088                 break;
3089         case OP_FCALL:
3090         case OP_FCALL_REG:
3091         case OP_FCALL_MEMBASE:
3092                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3093                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3094                 }
3095                 else {
3096                         if (ins->dreg != AMD64_XMM0)
3097                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3098                 }
3099                 break;
3100         case OP_VCALL:
3101         case OP_VCALL_REG:
3102         case OP_VCALL_MEMBASE:
3103         case OP_VCALL2:
3104         case OP_VCALL2_REG:
3105         case OP_VCALL2_MEMBASE:
3106                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3107                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3108                         MonoInst *loc = cfg->arch.vret_addr_loc;
3109
3110                         /* Load the destination address */
3111                         g_assert (loc->opcode == OP_REGOFFSET);
3112                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3113
3114                         for (quad = 0; quad < 2; quad ++) {
3115                                 switch (cinfo->ret.pair_storage [quad]) {
3116                                 case ArgInIReg:
3117                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3118                                         break;
3119                                 case ArgInFloatSSEReg:
3120                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3121                                         break;
3122                                 case ArgInDoubleSSEReg:
3123                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3124                                         break;
3125                                 case ArgNone:
3126                                         break;
3127                                 default:
3128                                         NOT_IMPLEMENTED;
3129                                 }
3130                         }
3131                 }
3132                 break;
3133         }
3134
3135         return code;
3136 }
3137
3138 #endif /* DISABLE_JIT */
3139
3140 /*
3141  * mono_amd64_emit_tls_get:
3142  * @code: buffer to store code to
3143  * @dreg: hard register where to place the result
3144  * @tls_offset: offset info
3145  *
3146  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3147  * the dreg register the item in the thread local storage identified
3148  * by tls_offset.
3149  *
3150  * Returns: a pointer to the end of the stored code
3151  */
3152 guint8*
3153 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3154 {
3155 #ifdef HOST_WIN32
3156         g_assert (tls_offset < 64);
3157         x86_prefix (code, X86_GS_PREFIX);
3158         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3159 #else
3160         if (optimize_for_xen) {
3161                 x86_prefix (code, X86_FS_PREFIX);
3162                 amd64_mov_reg_mem (code, dreg, 0, 8);
3163                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3164         } else {
3165                 x86_prefix (code, X86_FS_PREFIX);
3166                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3167         }
3168 #endif
3169         return code;
3170 }
3171
3172 #define REAL_PRINT_REG(text,reg) \
3173 mono_assert (reg >= 0); \
3174 amd64_push_reg (code, AMD64_RAX); \
3175 amd64_push_reg (code, AMD64_RDX); \
3176 amd64_push_reg (code, AMD64_RCX); \
3177 amd64_push_reg (code, reg); \
3178 amd64_push_imm (code, reg); \
3179 amd64_push_imm (code, text " %d %p\n"); \
3180 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3181 amd64_call_reg (code, AMD64_RAX); \
3182 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3183 amd64_pop_reg (code, AMD64_RCX); \
3184 amd64_pop_reg (code, AMD64_RDX); \
3185 amd64_pop_reg (code, AMD64_RAX);
3186
3187 /* benchmark and set based on cpu */
3188 #define LOOP_ALIGNMENT 8
3189 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3190
3191 #ifndef DISABLE_JIT
3192
3193 void
3194 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3195 {
3196         MonoInst *ins;
3197         MonoCallInst *call;
3198         guint offset;
3199         guint8 *code = cfg->native_code + cfg->code_len;
3200         MonoInst *last_ins = NULL;
3201         guint last_offset = 0;
3202         int max_len;
3203
3204         /* Fix max_offset estimate for each successor bb */
3205         if (cfg->opt & MONO_OPT_BRANCH) {
3206                 int current_offset = cfg->code_len;
3207                 MonoBasicBlock *current_bb;
3208                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3209                         current_bb->max_offset = current_offset;
3210                         current_offset += current_bb->max_length;
3211                 }
3212         }
3213
3214         if (cfg->opt & MONO_OPT_LOOP) {
3215                 int pad, align = LOOP_ALIGNMENT;
3216                 /* set alignment depending on cpu */
3217                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3218                         pad = align - pad;
3219                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3220                         amd64_padding (code, pad);
3221                         cfg->code_len += pad;
3222                         bb->native_offset = cfg->code_len;
3223                 }
3224         }
3225
3226         if (cfg->verbose_level > 2)
3227                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3228
3229         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3230                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3231                 g_assert (!cfg->compile_aot);
3232
3233                 cov->data [bb->dfn].cil_code = bb->cil_code;
3234                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3235                 /* this is not thread save, but good enough */
3236                 amd64_inc_membase (code, AMD64_R11, 0);
3237         }
3238
3239         offset = code - cfg->native_code;
3240
3241         mono_debug_open_block (cfg, bb, offset);
3242
3243     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3244                 x86_breakpoint (code);
3245
3246         MONO_BB_FOR_EACH_INS (bb, ins) {
3247                 offset = code - cfg->native_code;
3248
3249                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3250
3251                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3252                         cfg->code_size *= 2;
3253                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3254                         code = cfg->native_code + offset;
3255                         mono_jit_stats.code_reallocs++;
3256                 }
3257
3258                 if (cfg->debug_info)
3259                         mono_debug_record_line_number (cfg, ins, offset);
3260
3261                 switch (ins->opcode) {
3262                 case OP_BIGMUL:
3263                         amd64_mul_reg (code, ins->sreg2, TRUE);
3264                         break;
3265                 case OP_BIGMUL_UN:
3266                         amd64_mul_reg (code, ins->sreg2, FALSE);
3267                         break;
3268                 case OP_X86_SETEQ_MEMBASE:
3269                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3270                         break;
3271                 case OP_STOREI1_MEMBASE_IMM:
3272                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3273                         break;
3274                 case OP_STOREI2_MEMBASE_IMM:
3275                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3276                         break;
3277                 case OP_STOREI4_MEMBASE_IMM:
3278                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3279                         break;
3280                 case OP_STOREI1_MEMBASE_REG:
3281                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3282                         break;
3283                 case OP_STOREI2_MEMBASE_REG:
3284                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3285                         break;
3286                 case OP_STORE_MEMBASE_REG:
3287                 case OP_STOREI8_MEMBASE_REG:
3288                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3289                         break;
3290                 case OP_STOREI4_MEMBASE_REG:
3291                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3292                         break;
3293                 case OP_STORE_MEMBASE_IMM:
3294                 case OP_STOREI8_MEMBASE_IMM:
3295                         g_assert (amd64_is_imm32 (ins->inst_imm));
3296                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3297                         break;
3298                 case OP_LOAD_MEM:
3299                 case OP_LOADI8_MEM:
3300                         // FIXME: Decompose this earlier
3301                         if (amd64_is_imm32 (ins->inst_imm))
3302                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3303                         else {
3304                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3305                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3306                         }
3307                         break;
3308                 case OP_LOADI4_MEM:
3309                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3310                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3311                         break;
3312                 case OP_LOADU4_MEM:
3313                         // FIXME: Decompose this earlier
3314                         if (amd64_is_imm32 (ins->inst_imm))
3315                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3316                         else {
3317                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3318                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3319                         }
3320                         break;
3321                 case OP_LOADU1_MEM:
3322                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3323                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3324                         break;
3325                 case OP_LOADU2_MEM:
3326                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3327                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3328                         break;
3329                 case OP_LOAD_MEMBASE:
3330                 case OP_LOADI8_MEMBASE:
3331                         g_assert (amd64_is_imm32 (ins->inst_offset));
3332                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3333                         break;
3334                 case OP_LOADI4_MEMBASE:
3335                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3336                         break;
3337                 case OP_LOADU4_MEMBASE:
3338                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3339                         break;
3340                 case OP_LOADU1_MEMBASE:
3341                         /* The cpu zero extends the result into 64 bits */
3342                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3343                         break;
3344                 case OP_LOADI1_MEMBASE:
3345                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3346                         break;
3347                 case OP_LOADU2_MEMBASE:
3348                         /* The cpu zero extends the result into 64 bits */
3349                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3350                         break;
3351                 case OP_LOADI2_MEMBASE:
3352                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3353                         break;
3354                 case OP_AMD64_LOADI8_MEMINDEX:
3355                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3356                         break;
3357                 case OP_LCONV_TO_I1:
3358                 case OP_ICONV_TO_I1:
3359                 case OP_SEXT_I1:
3360                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3361                         break;
3362                 case OP_LCONV_TO_I2:
3363                 case OP_ICONV_TO_I2:
3364                 case OP_SEXT_I2:
3365                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3366                         break;
3367                 case OP_LCONV_TO_U1:
3368                 case OP_ICONV_TO_U1:
3369                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3370                         break;
3371                 case OP_LCONV_TO_U2:
3372                 case OP_ICONV_TO_U2:
3373                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3374                         break;
3375                 case OP_ZEXT_I4:
3376                         /* Clean out the upper word */
3377                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3378                         break;
3379                 case OP_SEXT_I4:
3380                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3381                         break;
3382                 case OP_COMPARE:
3383                 case OP_LCOMPARE:
3384                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3385                         break;
3386                 case OP_COMPARE_IMM:
3387                 case OP_LCOMPARE_IMM:
3388                         g_assert (amd64_is_imm32 (ins->inst_imm));
3389                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3390                         break;
3391                 case OP_X86_COMPARE_REG_MEMBASE:
3392                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3393                         break;
3394                 case OP_X86_TEST_NULL:
3395                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3396                         break;
3397                 case OP_AMD64_TEST_NULL:
3398                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3399                         break;
3400
3401                 case OP_X86_ADD_REG_MEMBASE:
3402                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3403                         break;
3404                 case OP_X86_SUB_REG_MEMBASE:
3405                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3406                         break;
3407                 case OP_X86_AND_REG_MEMBASE:
3408                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3409                         break;
3410                 case OP_X86_OR_REG_MEMBASE:
3411                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3412                         break;
3413                 case OP_X86_XOR_REG_MEMBASE:
3414                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3415                         break;
3416
3417                 case OP_X86_ADD_MEMBASE_IMM:
3418                         /* FIXME: Make a 64 version too */
3419                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3420                         break;
3421                 case OP_X86_SUB_MEMBASE_IMM:
3422                         g_assert (amd64_is_imm32 (ins->inst_imm));
3423                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3424                         break;
3425                 case OP_X86_AND_MEMBASE_IMM:
3426                         g_assert (amd64_is_imm32 (ins->inst_imm));
3427                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3428                         break;
3429                 case OP_X86_OR_MEMBASE_IMM:
3430                         g_assert (amd64_is_imm32 (ins->inst_imm));
3431                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3432                         break;
3433                 case OP_X86_XOR_MEMBASE_IMM:
3434                         g_assert (amd64_is_imm32 (ins->inst_imm));
3435                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3436                         break;
3437                 case OP_X86_ADD_MEMBASE_REG:
3438                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3439                         break;
3440                 case OP_X86_SUB_MEMBASE_REG:
3441                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3442                         break;
3443                 case OP_X86_AND_MEMBASE_REG:
3444                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3445                         break;
3446                 case OP_X86_OR_MEMBASE_REG:
3447                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3448                         break;
3449                 case OP_X86_XOR_MEMBASE_REG:
3450                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3451                         break;
3452                 case OP_X86_INC_MEMBASE:
3453                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3454                         break;
3455                 case OP_X86_INC_REG:
3456                         amd64_inc_reg_size (code, ins->dreg, 4);
3457                         break;
3458                 case OP_X86_DEC_MEMBASE:
3459                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3460                         break;
3461                 case OP_X86_DEC_REG:
3462                         amd64_dec_reg_size (code, ins->dreg, 4);
3463                         break;
3464                 case OP_X86_MUL_REG_MEMBASE:
3465                 case OP_X86_MUL_MEMBASE_REG:
3466                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3467                         break;
3468                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3469                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3470                         break;
3471                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3472                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3473                         break;
3474                 case OP_AMD64_COMPARE_MEMBASE_REG:
3475                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3476                         break;
3477                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3478                         g_assert (amd64_is_imm32 (ins->inst_imm));
3479                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3480                         break;
3481                 case OP_X86_COMPARE_MEMBASE8_IMM:
3482                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3483                         break;
3484                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3485                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3486                         break;
3487                 case OP_AMD64_COMPARE_REG_MEMBASE:
3488                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3489                         break;
3490
3491                 case OP_AMD64_ADD_REG_MEMBASE:
3492                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3493                         break;
3494                 case OP_AMD64_SUB_REG_MEMBASE:
3495                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3496                         break;
3497                 case OP_AMD64_AND_REG_MEMBASE:
3498                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3499                         break;
3500                 case OP_AMD64_OR_REG_MEMBASE:
3501                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3502                         break;
3503                 case OP_AMD64_XOR_REG_MEMBASE:
3504                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3505                         break;
3506
3507                 case OP_AMD64_ADD_MEMBASE_REG:
3508                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3509                         break;
3510                 case OP_AMD64_SUB_MEMBASE_REG:
3511                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3512                         break;
3513                 case OP_AMD64_AND_MEMBASE_REG:
3514                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3515                         break;
3516                 case OP_AMD64_OR_MEMBASE_REG:
3517                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3518                         break;
3519                 case OP_AMD64_XOR_MEMBASE_REG:
3520                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3521                         break;
3522
3523                 case OP_AMD64_ADD_MEMBASE_IMM:
3524                         g_assert (amd64_is_imm32 (ins->inst_imm));
3525                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3526                         break;
3527                 case OP_AMD64_SUB_MEMBASE_IMM:
3528                         g_assert (amd64_is_imm32 (ins->inst_imm));
3529                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3530                         break;
3531                 case OP_AMD64_AND_MEMBASE_IMM:
3532                         g_assert (amd64_is_imm32 (ins->inst_imm));
3533                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3534                         break;
3535                 case OP_AMD64_OR_MEMBASE_IMM:
3536                         g_assert (amd64_is_imm32 (ins->inst_imm));
3537                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3538                         break;
3539                 case OP_AMD64_XOR_MEMBASE_IMM:
3540                         g_assert (amd64_is_imm32 (ins->inst_imm));
3541                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3542                         break;
3543
3544                 case OP_BREAK:
3545                         amd64_breakpoint (code);
3546                         break;
3547                 case OP_RELAXED_NOP:
3548                         x86_prefix (code, X86_REP_PREFIX);
3549                         x86_nop (code);
3550                         break;
3551                 case OP_HARD_NOP:
3552                         x86_nop (code);
3553                         break;
3554                 case OP_NOP:
3555                 case OP_DUMMY_USE:
3556                 case OP_DUMMY_STORE:
3557                 case OP_NOT_REACHED:
3558                 case OP_NOT_NULL:
3559                         break;
3560                 case OP_SEQ_POINT: {
3561                         int i;
3562
3563                         if (cfg->compile_aot)
3564                                 NOT_IMPLEMENTED;
3565
3566                         /*
3567                          * Read from the single stepping trigger page. This will cause a
3568                          * SIGSEGV when single stepping is enabled.
3569                          * We do this _before_ the breakpoint, so single stepping after
3570                          * a breakpoint is hit will step to the next IL offset.
3571                          */
3572                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3573                                 if (((guint64)ss_trigger_page >> 32) == 0)
3574                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3575                                 else {
3576                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
3577
3578                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3579                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3580                                 }
3581                         }
3582
3583                         /*
3584                          * This is the address which is saved in seq points,
3585                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3586                          * from the address of the instruction causing the fault.
3587                          */
3588                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3589
3590                         /*
3591                          * A placeholder for a possible breakpoint inserted by
3592                          * mono_arch_set_breakpoint ().
3593                          */
3594                         for (i = 0; i < breakpoint_size; ++i)
3595                                 x86_nop (code);
3596                         break;
3597                 }
3598                 case OP_ADDCC:
3599                 case OP_LADD:
3600                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3601                         break;
3602                 case OP_ADC:
3603                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3604                         break;
3605                 case OP_ADD_IMM:
3606                 case OP_LADD_IMM:
3607                         g_assert (amd64_is_imm32 (ins->inst_imm));
3608                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3609                         break;
3610                 case OP_ADC_IMM:
3611                         g_assert (amd64_is_imm32 (ins->inst_imm));
3612                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3613                         break;
3614                 case OP_SUBCC:
3615                 case OP_LSUB:
3616                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3617                         break;
3618                 case OP_SBB:
3619                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3620                         break;
3621                 case OP_SUB_IMM:
3622                 case OP_LSUB_IMM:
3623                         g_assert (amd64_is_imm32 (ins->inst_imm));
3624                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3625                         break;
3626                 case OP_SBB_IMM:
3627                         g_assert (amd64_is_imm32 (ins->inst_imm));
3628                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3629                         break;
3630                 case OP_LAND:
3631                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3632                         break;
3633                 case OP_AND_IMM:
3634                 case OP_LAND_IMM:
3635                         g_assert (amd64_is_imm32 (ins->inst_imm));
3636                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3637                         break;
3638                 case OP_LMUL:
3639                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3640                         break;
3641                 case OP_MUL_IMM:
3642                 case OP_LMUL_IMM:
3643                 case OP_IMUL_IMM: {
3644                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3645
3646                         switch (ins->inst_imm) {
3647                         case 2:
3648                                 /* MOV r1, r2 */
3649                                 /* ADD r1, r1 */
3650                                 if (ins->dreg != ins->sreg1)
3651                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3652                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3653                                 break;
3654                         case 3:
3655                                 /* LEA r1, [r2 + r2*2] */
3656                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3657                                 break;
3658                         case 5:
3659                                 /* LEA r1, [r2 + r2*4] */
3660                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3661                                 break;
3662                         case 6:
3663                                 /* LEA r1, [r2 + r2*2] */
3664                                 /* ADD r1, r1          */
3665                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3666                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3667                                 break;
3668                         case 9:
3669                                 /* LEA r1, [r2 + r2*8] */
3670                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3671                                 break;
3672                         case 10:
3673                                 /* LEA r1, [r2 + r2*4] */
3674                                 /* ADD r1, r1          */
3675                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3676                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3677                                 break;
3678                         case 12:
3679                                 /* LEA r1, [r2 + r2*2] */
3680                                 /* SHL r1, 2           */
3681                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3682                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3683                                 break;
3684                         case 25:
3685                                 /* LEA r1, [r2 + r2*4] */
3686                                 /* LEA r1, [r1 + r1*4] */
3687                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3688                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3689                                 break;
3690                         case 100:
3691                                 /* LEA r1, [r2 + r2*4] */
3692                                 /* SHL r1, 2           */
3693                                 /* LEA r1, [r1 + r1*4] */
3694                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3695                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3696                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3697                                 break;
3698                         default:
3699                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3700                                 break;
3701                         }
3702                         break;
3703                 }
3704                 case OP_LDIV:
3705                 case OP_LREM:
3706                         /* Regalloc magic makes the div/rem cases the same */
3707                         if (ins->sreg2 == AMD64_RDX) {
3708                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3709                                 amd64_cdq (code);
3710                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3711                         } else {
3712                                 amd64_cdq (code);
3713                                 amd64_div_reg (code, ins->sreg2, TRUE);
3714                         }
3715                         break;
3716                 case OP_LDIV_UN:
3717                 case OP_LREM_UN:
3718                         if (ins->sreg2 == AMD64_RDX) {
3719                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3720                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3721                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3722                         } else {
3723                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3724                                 amd64_div_reg (code, ins->sreg2, FALSE);
3725                         }
3726                         break;
3727                 case OP_IDIV:
3728                 case OP_IREM:
3729                         if (ins->sreg2 == AMD64_RDX) {
3730                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3731                                 amd64_cdq_size (code, 4);
3732                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3733                         } else {
3734                                 amd64_cdq_size (code, 4);
3735                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3736                         }
3737                         break;
3738                 case OP_IDIV_UN:
3739                 case OP_IREM_UN:
3740                         if (ins->sreg2 == AMD64_RDX) {
3741                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3742                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3743                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3744                         } else {
3745                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3746                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3747                         }
3748                         break;
3749                 case OP_IREM_IMM: {
3750                         int power = mono_is_power_of_two (ins->inst_imm);
3751
3752                         g_assert (ins->sreg1 == X86_EAX);
3753                         g_assert (ins->dreg == X86_EAX);
3754                         g_assert (power >= 0);
3755
3756                         if (power == 0) {
3757                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3758                                 break;
3759                         }
3760
3761                         /* Based on gcc code */
3762
3763                         /* Add compensation for negative dividents */
3764                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3765                         if (power > 1)
3766                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3767                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3768                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3769                         /* Compute remainder */
3770                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3771                         /* Remove compensation */
3772                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3773                         break;
3774                 }
3775                 case OP_LMUL_OVF:
3776                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3777                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3778                         break;
3779                 case OP_LOR:
3780                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3781                         break;
3782                 case OP_OR_IMM:
3783                 case OP_LOR_IMM:
3784                         g_assert (amd64_is_imm32 (ins->inst_imm));
3785                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3786                         break;
3787                 case OP_LXOR:
3788                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3789                         break;
3790                 case OP_XOR_IMM:
3791                 case OP_LXOR_IMM:
3792                         g_assert (amd64_is_imm32 (ins->inst_imm));
3793                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3794                         break;
3795                 case OP_LSHL:
3796                         g_assert (ins->sreg2 == AMD64_RCX);
3797                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3798                         break;
3799                 case OP_LSHR:
3800                         g_assert (ins->sreg2 == AMD64_RCX);
3801                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3802                         break;
3803                 case OP_SHR_IMM:
3804                         g_assert (amd64_is_imm32 (ins->inst_imm));
3805                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3806                         break;
3807                 case OP_LSHR_IMM:
3808                         g_assert (amd64_is_imm32 (ins->inst_imm));
3809                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3810                         break;
3811                 case OP_SHR_UN_IMM:
3812                         g_assert (amd64_is_imm32 (ins->inst_imm));
3813                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3814                         break;
3815                 case OP_LSHR_UN_IMM:
3816                         g_assert (amd64_is_imm32 (ins->inst_imm));
3817                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3818                         break;
3819                 case OP_LSHR_UN:
3820                         g_assert (ins->sreg2 == AMD64_RCX);
3821                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3822                         break;
3823                 case OP_SHL_IMM:
3824                         g_assert (amd64_is_imm32 (ins->inst_imm));
3825                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3826                         break;
3827                 case OP_LSHL_IMM:
3828                         g_assert (amd64_is_imm32 (ins->inst_imm));
3829                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3830                         break;
3831
3832                 case OP_IADDCC:
3833                 case OP_IADD:
3834                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3835                         break;
3836                 case OP_IADC:
3837                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3838                         break;
3839                 case OP_IADD_IMM:
3840                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3841                         break;
3842                 case OP_IADC_IMM:
3843                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3844                         break;
3845                 case OP_ISUBCC:
3846                 case OP_ISUB:
3847                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3848                         break;
3849                 case OP_ISBB:
3850                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3851                         break;
3852                 case OP_ISUB_IMM:
3853                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3854                         break;
3855                 case OP_ISBB_IMM:
3856                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3857                         break;
3858                 case OP_IAND:
3859                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3860                         break;
3861                 case OP_IAND_IMM:
3862                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3863                         break;
3864                 case OP_IOR:
3865                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3866                         break;
3867                 case OP_IOR_IMM:
3868                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3869                         break;
3870                 case OP_IXOR:
3871                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3872                         break;
3873                 case OP_IXOR_IMM:
3874                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3875                         break;
3876                 case OP_INEG:
3877                         amd64_neg_reg_size (code, ins->sreg1, 4);
3878                         break;
3879                 case OP_INOT:
3880                         amd64_not_reg_size (code, ins->sreg1, 4);
3881                         break;
3882                 case OP_ISHL:
3883                         g_assert (ins->sreg2 == AMD64_RCX);
3884                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3885                         break;
3886                 case OP_ISHR:
3887                         g_assert (ins->sreg2 == AMD64_RCX);
3888                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3889                         break;
3890                 case OP_ISHR_IMM:
3891                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3892                         break;
3893                 case OP_ISHR_UN_IMM:
3894                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3895                         break;
3896                 case OP_ISHR_UN:
3897                         g_assert (ins->sreg2 == AMD64_RCX);
3898                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3899                         break;
3900                 case OP_ISHL_IMM:
3901                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3902                         break;
3903                 case OP_IMUL:
3904                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3905                         break;
3906                 case OP_IMUL_OVF:
3907                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3908                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3909                         break;
3910                 case OP_IMUL_OVF_UN:
3911                 case OP_LMUL_OVF_UN: {
3912                         /* the mul operation and the exception check should most likely be split */
3913                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3914                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3915                         /*g_assert (ins->sreg2 == X86_EAX);
3916                         g_assert (ins->dreg == X86_EAX);*/
3917                         if (ins->sreg2 == X86_EAX) {
3918                                 non_eax_reg = ins->sreg1;
3919                         } else if (ins->sreg1 == X86_EAX) {
3920                                 non_eax_reg = ins->sreg2;
3921                         } else {
3922                                 /* no need to save since we're going to store to it anyway */
3923                                 if (ins->dreg != X86_EAX) {
3924                                         saved_eax = TRUE;
3925                                         amd64_push_reg (code, X86_EAX);
3926                                 }
3927                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3928                                 non_eax_reg = ins->sreg2;
3929                         }
3930                         if (ins->dreg == X86_EDX) {
3931                                 if (!saved_eax) {
3932                                         saved_eax = TRUE;
3933                                         amd64_push_reg (code, X86_EAX);
3934                                 }
3935                         } else {
3936                                 saved_edx = TRUE;
3937                                 amd64_push_reg (code, X86_EDX);
3938                         }
3939                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3940                         /* save before the check since pop and mov don't change the flags */
3941                         if (ins->dreg != X86_EAX)
3942                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3943                         if (saved_edx)
3944                                 amd64_pop_reg (code, X86_EDX);
3945                         if (saved_eax)
3946                                 amd64_pop_reg (code, X86_EAX);
3947                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3948                         break;
3949                 }
3950                 case OP_ICOMPARE:
3951                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3952                         break;
3953                 case OP_ICOMPARE_IMM:
3954                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3955                         break;
3956                 case OP_IBEQ:
3957                 case OP_IBLT:
3958                 case OP_IBGT:
3959                 case OP_IBGE:
3960                 case OP_IBLE:
3961                 case OP_LBEQ:
3962                 case OP_LBLT:
3963                 case OP_LBGT:
3964                 case OP_LBGE:
3965                 case OP_LBLE:
3966                 case OP_IBNE_UN:
3967                 case OP_IBLT_UN:
3968                 case OP_IBGT_UN:
3969                 case OP_IBGE_UN:
3970                 case OP_IBLE_UN:
3971                 case OP_LBNE_UN:
3972                 case OP_LBLT_UN:
3973                 case OP_LBGT_UN:
3974                 case OP_LBGE_UN:
3975                 case OP_LBLE_UN:
3976                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3977                         break;
3978
3979                 case OP_CMOV_IEQ:
3980                 case OP_CMOV_IGE:
3981                 case OP_CMOV_IGT:
3982                 case OP_CMOV_ILE:
3983                 case OP_CMOV_ILT:
3984                 case OP_CMOV_INE_UN:
3985                 case OP_CMOV_IGE_UN:
3986                 case OP_CMOV_IGT_UN:
3987                 case OP_CMOV_ILE_UN:
3988                 case OP_CMOV_ILT_UN:
3989                 case OP_CMOV_LEQ:
3990                 case OP_CMOV_LGE:
3991                 case OP_CMOV_LGT:
3992                 case OP_CMOV_LLE:
3993                 case OP_CMOV_LLT:
3994                 case OP_CMOV_LNE_UN:
3995                 case OP_CMOV_LGE_UN:
3996                 case OP_CMOV_LGT_UN:
3997                 case OP_CMOV_LLE_UN:
3998                 case OP_CMOV_LLT_UN:
3999                         g_assert (ins->dreg == ins->sreg1);
4000                         /* This needs to operate on 64 bit values */
4001                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4002                         break;
4003
4004                 case OP_LNOT:
4005                         amd64_not_reg (code, ins->sreg1);
4006                         break;
4007                 case OP_LNEG:
4008                         amd64_neg_reg (code, ins->sreg1);
4009                         break;
4010
4011                 case OP_ICONST:
4012                 case OP_I8CONST:
4013                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4014                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4015                         else
4016                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4017                         break;
4018                 case OP_AOTCONST:
4019                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4020                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4021                         break;
4022                 case OP_JUMP_TABLE:
4023                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4024                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4025                         break;
4026                 case OP_MOVE:
4027                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4028                         break;
4029                 case OP_AMD64_SET_XMMREG_R4: {
4030                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4031                         break;
4032                 }
4033                 case OP_AMD64_SET_XMMREG_R8: {
4034                         if (ins->dreg != ins->sreg1)
4035                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4036                         break;
4037                 }
4038                 case OP_TAILCALL: {
4039                         /*
4040                          * Note: this 'frame destruction' logic is useful for tail calls, too.
4041                          * Keep in sync with the code in emit_epilog.
4042                          */
4043                         int pos = 0, i;
4044
4045                         /* FIXME: no tracing support... */
4046                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4047                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4048
4049                         g_assert (!cfg->method->save_lmf);
4050
4051                         if (cfg->arch.omit_fp) {
4052                                 guint32 save_offset = 0;
4053                                 /* Pop callee-saved registers */
4054                                 for (i = 0; i < AMD64_NREG; ++i)
4055                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4056                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4057                                                 save_offset += 8;
4058                                         }
4059                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4060                         }
4061                         else {
4062                                 for (i = 0; i < AMD64_NREG; ++i)
4063                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4064                                                 pos -= sizeof (gpointer);
4065
4066                                 if (pos)
4067                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4068
4069                                 /* Pop registers in reverse order */
4070                                 for (i = AMD64_NREG - 1; i > 0; --i)
4071                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4072                                                 amd64_pop_reg (code, i);
4073                                         }
4074
4075                                 amd64_leave (code);
4076                         }
4077
4078                         offset = code - cfg->native_code;
4079                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4080                         if (cfg->compile_aot)
4081                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4082                         else
4083                                 amd64_set_reg_template (code, AMD64_R11);
4084                         amd64_jump_reg (code, AMD64_R11);
4085                         break;
4086                 }
4087                 case OP_CHECK_THIS:
4088                         /* ensure ins->sreg1 is not NULL */
4089                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4090                         break;
4091                 case OP_ARGLIST: {
4092                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4093                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4094                         break;
4095                 }
4096                 case OP_CALL:
4097                 case OP_FCALL:
4098                 case OP_LCALL:
4099                 case OP_VCALL:
4100                 case OP_VCALL2:
4101                 case OP_VOIDCALL:
4102                         call = (MonoCallInst*)ins;
4103                         /*
4104                          * The AMD64 ABI forces callers to know about varargs.
4105                          */
4106                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4107                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4108                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4109                                 /*
4110                                  * Since the unmanaged calling convention doesn't contain a
4111                                  * 'vararg' entry, we have to treat every pinvoke call as a
4112                                  * potential vararg call.
4113                                  */
4114                                 guint32 nregs, i;
4115                                 nregs = 0;
4116                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4117                                         if (call->used_fregs & (1 << i))
4118                                                 nregs ++;
4119                                 if (!nregs)
4120                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4121                                 else
4122                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4123                         }
4124
4125                         if (ins->flags & MONO_INST_HAS_METHOD)
4126                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4127                         else
4128                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4129                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4130                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4131                         code = emit_move_return_value (cfg, ins, code);
4132                         break;
4133                 case OP_FCALL_REG:
4134                 case OP_LCALL_REG:
4135                 case OP_VCALL_REG:
4136                 case OP_VCALL2_REG:
4137                 case OP_VOIDCALL_REG:
4138                 case OP_CALL_REG:
4139                         call = (MonoCallInst*)ins;
4140
4141                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4142                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4143                                 ins->sreg1 = AMD64_R11;
4144                         }
4145
4146                         /*
4147                          * The AMD64 ABI forces callers to know about varargs.
4148                          */
4149                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4150                                 if (ins->sreg1 == AMD64_RAX) {
4151                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4152                                         ins->sreg1 = AMD64_R11;
4153                                 }
4154                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4155                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4156                                 /*
4157                                  * Since the unmanaged calling convention doesn't contain a
4158                                  * 'vararg' entry, we have to treat every pinvoke call as a
4159                                  * potential vararg call.
4160                                  */
4161                                 guint32 nregs, i;
4162                                 nregs = 0;
4163                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4164                                         if (call->used_fregs & (1 << i))
4165                                                 nregs ++;
4166                                 if (ins->sreg1 == AMD64_RAX) {
4167                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4168                                         ins->sreg1 = AMD64_R11;
4169                                 }
4170                                 if (!nregs)
4171                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4172                                 else
4173                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4174                         }
4175
4176                         amd64_call_reg (code, ins->sreg1);
4177                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4178                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4179                         code = emit_move_return_value (cfg, ins, code);
4180                         break;
4181                 case OP_FCALL_MEMBASE:
4182                 case OP_LCALL_MEMBASE:
4183                 case OP_VCALL_MEMBASE:
4184                 case OP_VCALL2_MEMBASE:
4185                 case OP_VOIDCALL_MEMBASE:
4186                 case OP_CALL_MEMBASE:
4187                         call = (MonoCallInst*)ins;
4188
4189                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4190                                 /*
4191                                  * Can't use R11 because it is clobbered by the trampoline
4192                                  * code, and the reg value is needed by get_vcall_slot_addr.
4193                                  */
4194                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4195                                 ins->sreg1 = AMD64_RAX;
4196                         }
4197
4198                         /*
4199                          * Emit a few nops to simplify get_vcall_slot ().
4200                          */
4201                         amd64_nop (code);
4202                         amd64_nop (code);
4203                         amd64_nop (code);
4204
4205                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4206                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4207                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4208                         code = emit_move_return_value (cfg, ins, code);
4209                         break;
4210                 case OP_DYN_CALL: {
4211                         int i;
4212                         MonoInst *var = cfg->dyn_call_var;
4213
4214                         g_assert (var->opcode == OP_REGOFFSET);
4215
4216                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4217                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4218                         /* r10 = ftn */
4219                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4220
4221                         /* Save args buffer */
4222                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4223
4224                         /* Set argument registers */
4225                         for (i = 0; i < PARAM_REGS; ++i)
4226                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4227
4228                         /* Make the call */
4229                         amd64_call_reg (code, AMD64_R10);
4230
4231                         /* Save result */
4232                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4233                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4234                         break;
4235                 }
4236                 case OP_AMD64_SAVE_SP_TO_LMF:
4237                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4238                         break;
4239                 case OP_X86_PUSH:
4240                         g_assert (!cfg->arch.no_pushes);
4241                         amd64_push_reg (code, ins->sreg1);
4242                         break;
4243                 case OP_X86_PUSH_IMM:
4244                         g_assert (!cfg->arch.no_pushes);
4245                         g_assert (amd64_is_imm32 (ins->inst_imm));
4246                         amd64_push_imm (code, ins->inst_imm);
4247                         break;
4248                 case OP_X86_PUSH_MEMBASE:
4249                         g_assert (!cfg->arch.no_pushes);
4250                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4251                         break;
4252                 case OP_X86_PUSH_OBJ: {
4253                         int size = ALIGN_TO (ins->inst_imm, 8);
4254
4255                         g_assert (!cfg->arch.no_pushes);
4256
4257                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4258                         amd64_push_reg (code, AMD64_RDI);
4259                         amd64_push_reg (code, AMD64_RSI);
4260                         amd64_push_reg (code, AMD64_RCX);
4261                         if (ins->inst_offset)
4262                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4263                         else
4264                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4265                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4266                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4267                         amd64_cld (code);
4268                         amd64_prefix (code, X86_REP_PREFIX);
4269                         amd64_movsd (code);
4270                         amd64_pop_reg (code, AMD64_RCX);
4271                         amd64_pop_reg (code, AMD64_RSI);
4272                         amd64_pop_reg (code, AMD64_RDI);
4273                         break;
4274                 }
4275                 case OP_X86_LEA:
4276                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4277                         break;
4278                 case OP_X86_LEA_MEMBASE:
4279                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4280                         break;
4281                 case OP_X86_XCHG:
4282                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4283                         break;
4284                 case OP_LOCALLOC:
4285                         /* keep alignment */
4286                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4287                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4288                         code = mono_emit_stack_alloc (cfg, code, ins);
4289                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4290                         if (cfg->param_area && cfg->arch.no_pushes)
4291                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4292                         break;
4293                 case OP_LOCALLOC_IMM: {
4294                         guint32 size = ins->inst_imm;
4295                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4296
4297                         if (ins->flags & MONO_INST_INIT) {
4298                                 if (size < 64) {
4299                                         int i;
4300
4301                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4302                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4303
4304                                         for (i = 0; i < size; i += 8)
4305                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4306                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4307                                 } else {
4308                                         amd64_mov_reg_imm (code, ins->dreg, size);
4309                                         ins->sreg1 = ins->dreg;
4310
4311                                         code = mono_emit_stack_alloc (cfg, code, ins);
4312                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4313                                 }
4314                         } else {
4315                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4316                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4317                         }
4318                         if (cfg->param_area && cfg->arch.no_pushes)
4319                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4320                         break;
4321                 }
4322                 case OP_THROW: {
4323                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4324                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4325                                              (gpointer)"mono_arch_throw_exception", FALSE);
4326                         break;
4327                 }
4328                 case OP_RETHROW: {
4329                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4330                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4331                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4332                         break;
4333                 }
4334                 case OP_CALL_HANDLER:
4335                         /* Align stack */
4336                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4337                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4338                         amd64_call_imm (code, 0);
4339                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4340                         /* Restore stack alignment */
4341                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4342                         break;
4343                 case OP_START_HANDLER: {
4344                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4345                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4346
4347                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4348                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4349                                 cfg->param_area && cfg->arch.no_pushes) {
4350                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4351                         }
4352                         break;
4353                 }
4354                 case OP_ENDFINALLY: {
4355                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4356                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4357                         amd64_ret (code);
4358                         break;
4359                 }
4360                 case OP_ENDFILTER: {
4361                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4362                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4363                         /* The local allocator will put the result into RAX */
4364                         amd64_ret (code);
4365                         break;
4366                 }
4367
4368                 case OP_LABEL:
4369                         ins->inst_c0 = code - cfg->native_code;
4370                         break;
4371                 case OP_BR:
4372                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4373                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4374                         //break;
4375                                 if (ins->inst_target_bb->native_offset) {
4376                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4377                                 } else {
4378                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4379                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4380                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4381                                                 x86_jump8 (code, 0);
4382                                         else
4383                                                 x86_jump32 (code, 0);
4384                         }
4385                         break;
4386                 case OP_BR_REG:
4387                         amd64_jump_reg (code, ins->sreg1);
4388                         break;
4389                 case OP_CEQ:
4390                 case OP_LCEQ:
4391                 case OP_ICEQ:
4392                 case OP_CLT:
4393                 case OP_LCLT:
4394                 case OP_ICLT:
4395                 case OP_CGT:
4396                 case OP_ICGT:
4397                 case OP_LCGT:
4398                 case OP_CLT_UN:
4399                 case OP_LCLT_UN:
4400                 case OP_ICLT_UN:
4401                 case OP_CGT_UN:
4402                 case OP_LCGT_UN:
4403                 case OP_ICGT_UN:
4404                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4405                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4406                         break;
4407                 case OP_COND_EXC_EQ:
4408                 case OP_COND_EXC_NE_UN:
4409                 case OP_COND_EXC_LT:
4410                 case OP_COND_EXC_LT_UN:
4411                 case OP_COND_EXC_GT:
4412                 case OP_COND_EXC_GT_UN:
4413                 case OP_COND_EXC_GE:
4414                 case OP_COND_EXC_GE_UN:
4415                 case OP_COND_EXC_LE:
4416                 case OP_COND_EXC_LE_UN:
4417                 case OP_COND_EXC_IEQ:
4418                 case OP_COND_EXC_INE_UN:
4419                 case OP_COND_EXC_ILT:
4420                 case OP_COND_EXC_ILT_UN:
4421                 case OP_COND_EXC_IGT:
4422                 case OP_COND_EXC_IGT_UN:
4423                 case OP_COND_EXC_IGE:
4424                 case OP_COND_EXC_IGE_UN:
4425                 case OP_COND_EXC_ILE:
4426                 case OP_COND_EXC_ILE_UN:
4427                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4428                         break;
4429                 case OP_COND_EXC_OV:
4430                 case OP_COND_EXC_NO:
4431                 case OP_COND_EXC_C:
4432                 case OP_COND_EXC_NC:
4433                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4434                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4435                         break;
4436                 case OP_COND_EXC_IOV:
4437                 case OP_COND_EXC_INO:
4438                 case OP_COND_EXC_IC:
4439                 case OP_COND_EXC_INC:
4440                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4441                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4442                         break;
4443
4444                 /* floating point opcodes */
4445                 case OP_R8CONST: {
4446                         double d = *(double *)ins->inst_p0;
4447
4448                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4449                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4450                         }
4451                         else {
4452                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4453                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4454                         }
4455                         break;
4456                 }
4457                 case OP_R4CONST: {
4458                         float f = *(float *)ins->inst_p0;
4459
4460                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4461                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4462                         }
4463                         else {
4464                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4465                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4466                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4467                         }
4468                         break;
4469                 }
4470                 case OP_STORER8_MEMBASE_REG:
4471                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4472                         break;
4473                 case OP_LOADR8_MEMBASE:
4474                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4475                         break;
4476                 case OP_STORER4_MEMBASE_REG:
4477                         /* This requires a double->single conversion */
4478                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4479                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4480                         break;
4481                 case OP_LOADR4_MEMBASE:
4482                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4483                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4484                         break;
4485                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4486                 case OP_ICONV_TO_R8:
4487                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4488                         break;
4489                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4490                 case OP_LCONV_TO_R8:
4491                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4492                         break;
4493                 case OP_FCONV_TO_R4:
4494                         /* FIXME: nothing to do ?? */
4495                         break;
4496                 case OP_FCONV_TO_I1:
4497                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4498                         break;
4499                 case OP_FCONV_TO_U1:
4500                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4501                         break;
4502                 case OP_FCONV_TO_I2:
4503                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4504                         break;
4505                 case OP_FCONV_TO_U2:
4506                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4507                         break;
4508                 case OP_FCONV_TO_U4:
4509                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4510                         break;
4511                 case OP_FCONV_TO_I4:
4512                 case OP_FCONV_TO_I:
4513                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4514                         break;
4515                 case OP_FCONV_TO_I8:
4516                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4517                         break;
4518                 case OP_LCONV_TO_R_UN: {
4519                         guint8 *br [2];
4520
4521                         /* Based on gcc code */
4522                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4523                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4524
4525                         /* Positive case */
4526                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4527                         br [1] = code; x86_jump8 (code, 0);
4528                         amd64_patch (br [0], code);
4529
4530                         /* Negative case */
4531                         /* Save to the red zone */
4532                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4533                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4534                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4535                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4536                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4537                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4538                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4539                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4540                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4541                         /* Restore */
4542                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4543                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4544                         amd64_patch (br [1], code);
4545                         break;
4546                 }
4547                 case OP_LCONV_TO_OVF_U4:
4548                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4549                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4550                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4551                         break;
4552                 case OP_LCONV_TO_OVF_I4_UN:
4553                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4554                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4555                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4556                         break;
4557                 case OP_FMOVE:
4558                         if (ins->dreg != ins->sreg1)
4559                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4560                         break;
4561                 case OP_FADD:
4562                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4563                         break;
4564                 case OP_FSUB:
4565                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4566                         break;
4567                 case OP_FMUL:
4568                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4569                         break;
4570                 case OP_FDIV:
4571                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4572                         break;
4573                 case OP_FNEG: {
4574                         static double r8_0 = -0.0;
4575
4576                         g_assert (ins->sreg1 == ins->dreg);
4577
4578                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4579                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4580                         break;
4581                 }
4582                 case OP_SIN:
4583                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4584                         break;
4585                 case OP_COS:
4586                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4587                         break;
4588                 case OP_ABS: {
4589                         static guint64 d = 0x7fffffffffffffffUL;
4590
4591                         g_assert (ins->sreg1 == ins->dreg);
4592
4593                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4594                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4595                         break;
4596                 }
4597                 case OP_SQRT:
4598                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4599                         break;
4600                 case OP_IMIN:
4601                         g_assert (cfg->opt & MONO_OPT_CMOV);
4602                         g_assert (ins->dreg == ins->sreg1);
4603                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4604                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4605                         break;
4606                 case OP_IMIN_UN:
4607                         g_assert (cfg->opt & MONO_OPT_CMOV);
4608                         g_assert (ins->dreg == ins->sreg1);
4609                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4610                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4611                         break;
4612                 case OP_IMAX:
4613                         g_assert (cfg->opt & MONO_OPT_CMOV);
4614                         g_assert (ins->dreg == ins->sreg1);
4615                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4616                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4617                         break;
4618                 case OP_IMAX_UN:
4619                         g_assert (cfg->opt & MONO_OPT_CMOV);
4620                         g_assert (ins->dreg == ins->sreg1);
4621                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4622                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4623                         break;
4624                 case OP_LMIN:
4625                         g_assert (cfg->opt & MONO_OPT_CMOV);
4626                         g_assert (ins->dreg == ins->sreg1);
4627                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4628                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4629                         break;
4630                 case OP_LMIN_UN:
4631                         g_assert (cfg->opt & MONO_OPT_CMOV);
4632                         g_assert (ins->dreg == ins->sreg1);
4633                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4634                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4635                         break;
4636                 case OP_LMAX:
4637                         g_assert (cfg->opt & MONO_OPT_CMOV);
4638                         g_assert (ins->dreg == ins->sreg1);
4639                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4640                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4641                         break;
4642                 case OP_LMAX_UN:
4643                         g_assert (cfg->opt & MONO_OPT_CMOV);
4644                         g_assert (ins->dreg == ins->sreg1);
4645                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4646                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4647                         break;
4648                 case OP_X86_FPOP:
4649                         break;
4650                 case OP_FCOMPARE:
4651                         /*
4652                          * The two arguments are swapped because the fbranch instructions
4653                          * depend on this for the non-sse case to work.
4654                          */
4655                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4656                         break;
4657                 case OP_FCEQ: {
4658                         /* zeroing the register at the start results in
4659                          * shorter and faster code (we can also remove the widening op)
4660                          */
4661                         guchar *unordered_check;
4662                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4663                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4664                         unordered_check = code;
4665                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4666                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4667                         amd64_patch (unordered_check, code);
4668                         break;
4669                 }
4670                 case OP_FCLT:
4671                 case OP_FCLT_UN:
4672                         /* zeroing the register at the start results in
4673                          * shorter and faster code (we can also remove the widening op)
4674                          */
4675                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4676                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4677                         if (ins->opcode == OP_FCLT_UN) {
4678                                 guchar *unordered_check = code;
4679                                 guchar *jump_to_end;
4680                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4681                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4682                                 jump_to_end = code;
4683                                 x86_jump8 (code, 0);
4684                                 amd64_patch (unordered_check, code);
4685                                 amd64_inc_reg (code, ins->dreg);
4686                                 amd64_patch (jump_to_end, code);
4687                         } else {
4688                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4689                         }
4690                         break;
4691                 case OP_FCGT:
4692                 case OP_FCGT_UN: {
4693                         /* zeroing the register at the start results in
4694                          * shorter and faster code (we can also remove the widening op)
4695                          */
4696                         guchar *unordered_check;
4697                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4698                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4699                         if (ins->opcode == OP_FCGT) {
4700                                 unordered_check = code;
4701                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4702                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4703                                 amd64_patch (unordered_check, code);
4704                         } else {
4705                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4706                         }
4707                         break;
4708                 }
4709                 case OP_FCLT_MEMBASE:
4710                 case OP_FCGT_MEMBASE:
4711                 case OP_FCLT_UN_MEMBASE:
4712                 case OP_FCGT_UN_MEMBASE:
4713                 case OP_FCEQ_MEMBASE: {
4714                         guchar *unordered_check, *jump_to_end;
4715                         int x86_cond;
4716
4717                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4718                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4719
4720                         switch (ins->opcode) {
4721                         case OP_FCEQ_MEMBASE:
4722                                 x86_cond = X86_CC_EQ;
4723                                 break;
4724                         case OP_FCLT_MEMBASE:
4725                         case OP_FCLT_UN_MEMBASE:
4726                                 x86_cond = X86_CC_LT;
4727                                 break;
4728                         case OP_FCGT_MEMBASE:
4729                         case OP_FCGT_UN_MEMBASE:
4730                                 x86_cond = X86_CC_GT;
4731                                 break;
4732                         default:
4733                                 g_assert_not_reached ();
4734                         }
4735
4736                         unordered_check = code;
4737                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4738                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4739
4740                         switch (ins->opcode) {
4741                         case OP_FCEQ_MEMBASE:
4742                         case OP_FCLT_MEMBASE:
4743                         case OP_FCGT_MEMBASE:
4744                                 amd64_patch (unordered_check, code);
4745                                 break;
4746                         case OP_FCLT_UN_MEMBASE:
4747                         case OP_FCGT_UN_MEMBASE:
4748                                 jump_to_end = code;
4749                                 x86_jump8 (code, 0);
4750                                 amd64_patch (unordered_check, code);
4751                                 amd64_inc_reg (code, ins->dreg);
4752                                 amd64_patch (jump_to_end, code);
4753                                 break;
4754                         default:
4755                                 break;
4756                         }
4757                         break;
4758                 }
4759                 case OP_FBEQ: {
4760                         guchar *jump = code;
4761                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4762                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4763                         amd64_patch (jump, code);
4764                         break;
4765                 }
4766                 case OP_FBNE_UN:
4767                         /* Branch if C013 != 100 */
4768                         /* branch if !ZF or (PF|CF) */
4769                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4770                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4771                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4772                         break;
4773                 case OP_FBLT:
4774                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4775                         break;
4776                 case OP_FBLT_UN:
4777                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4778                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4779                         break;
4780                 case OP_FBGT:
4781                 case OP_FBGT_UN:
4782                         if (ins->opcode == OP_FBGT) {
4783                                 guchar *br1;
4784
4785                                 /* skip branch if C1=1 */
4786                                 br1 = code;
4787                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4788                                 /* branch if (C0 | C3) = 1 */
4789                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4790                                 amd64_patch (br1, code);
4791                                 break;
4792                         } else {
4793                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4794                         }
4795                         break;
4796                 case OP_FBGE: {
4797                         /* Branch if C013 == 100 or 001 */
4798                         guchar *br1;
4799
4800                         /* skip branch if C1=1 */
4801                         br1 = code;
4802                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4803                         /* branch if (C0 | C3) = 1 */
4804                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4805                         amd64_patch (br1, code);
4806                         break;
4807                 }
4808                 case OP_FBGE_UN:
4809                         /* Branch if C013 == 000 */
4810                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4811                         break;
4812                 case OP_FBLE: {
4813                         /* Branch if C013=000 or 100 */
4814                         guchar *br1;
4815
4816                         /* skip branch if C1=1 */
4817                         br1 = code;
4818                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4819                         /* branch if C0=0 */
4820                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4821                         amd64_patch (br1, code);
4822                         break;
4823                 }
4824                 case OP_FBLE_UN:
4825                         /* Branch if C013 != 001 */
4826                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4827                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4828                         break;
4829                 case OP_CKFINITE:
4830                         /* Transfer value to the fp stack */
4831                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4832                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4833                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4834
4835                         amd64_push_reg (code, AMD64_RAX);
4836                         amd64_fxam (code);
4837                         amd64_fnstsw (code);
4838                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4839                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4840                         amd64_pop_reg (code, AMD64_RAX);
4841                         amd64_fstp (code, 0);
4842                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4843                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4844                         break;
4845                 case OP_TLS_GET: {
4846                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4847                         break;
4848                 }
4849                 case OP_MEMORY_BARRIER: {
4850                         /* Not needed on amd64 */
4851                         break;
4852                 }
4853                 case OP_ATOMIC_ADD_I4:
4854                 case OP_ATOMIC_ADD_I8: {
4855                         int dreg = ins->dreg;
4856                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4857
4858                         if (dreg == ins->inst_basereg)
4859                                 dreg = AMD64_R11;
4860
4861                         if (dreg != ins->sreg2)
4862                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4863
4864                         x86_prefix (code, X86_LOCK_PREFIX);
4865                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4866
4867                         if (dreg != ins->dreg)
4868                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4869
4870                         break;
4871                 }
4872                 case OP_ATOMIC_ADD_NEW_I4:
4873                 case OP_ATOMIC_ADD_NEW_I8: {
4874                         int dreg = ins->dreg;
4875                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4876
4877                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4878                                 dreg = AMD64_R11;
4879
4880                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4881                         amd64_prefix (code, X86_LOCK_PREFIX);
4882                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4883                         /* dreg contains the old value, add with sreg2 value */
4884                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4885
4886                         if (ins->dreg != dreg)
4887                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4888
4889                         break;
4890                 }
4891                 case OP_ATOMIC_EXCHANGE_I4:
4892                 case OP_ATOMIC_EXCHANGE_I8: {
4893                         guchar *br[2];
4894                         int sreg2 = ins->sreg2;
4895                         int breg = ins->inst_basereg;
4896                         guint32 size;
4897                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4898
4899                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4900                                 size = 8;
4901                         else
4902                                 size = 4;
4903
4904                         /*
4905                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4906                          * an explanation of how this works.
4907                          */
4908
4909                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4910                          * hack to overcome limits in x86 reg allocator
4911                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4912                          */
4913                         g_assert (ins->dreg == AMD64_RAX);
4914
4915                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4916                                 /* Highly unlikely, but possible */
4917                                 need_push = TRUE;
4918
4919                         /* The pushes invalidate rsp */
4920                         if ((breg == AMD64_RAX) || need_push) {
4921                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4922                                 breg = AMD64_R11;
4923                         }
4924
4925                         /* We need the EAX reg for the comparand */
4926                         if (ins->sreg2 == AMD64_RAX) {
4927                                 if (breg != AMD64_R11) {
4928                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4929                                         sreg2 = AMD64_R11;
4930                                 } else {
4931                                         g_assert (need_push);
4932                                         amd64_push_reg (code, AMD64_RDX);
4933                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4934                                         sreg2 = AMD64_RDX;
4935                                         rdx_pushed = TRUE;
4936                                 }
4937                         }
4938
4939                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4940
4941                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4942                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4943                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4944                         amd64_patch (br [1], br [0]);
4945
4946                         if (rdx_pushed)
4947                                 amd64_pop_reg (code, AMD64_RDX);
4948
4949                         break;
4950                 }
4951                 case OP_ATOMIC_CAS_I4:
4952                 case OP_ATOMIC_CAS_I8: {
4953                         guint32 size;
4954
4955                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4956                                 size = 8;
4957                         else
4958                                 size = 4;
4959
4960                         /*
4961                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4962                          * an explanation of how this works.
4963                          */
4964                         g_assert (ins->sreg3 == AMD64_RAX);
4965                         g_assert (ins->sreg1 != AMD64_RAX);
4966                         g_assert (ins->sreg1 != ins->sreg2);
4967
4968                         amd64_prefix (code, X86_LOCK_PREFIX);
4969                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4970
4971                         if (ins->dreg != AMD64_RAX)
4972                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4973                         break;
4974                 }
4975 #ifdef MONO_ARCH_SIMD_INTRINSICS
4976                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4977                 case OP_ADDPS:
4978                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4979                         break;
4980                 case OP_DIVPS:
4981                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4982                         break;
4983                 case OP_MULPS:
4984                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4985                         break;
4986                 case OP_SUBPS:
4987                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4988                         break;
4989                 case OP_MAXPS:
4990                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4991                         break;
4992                 case OP_MINPS:
4993                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4994                         break;
4995                 case OP_COMPPS:
4996                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4997                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4998                         break;
4999                 case OP_ANDPS:
5000                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5001                         break;
5002                 case OP_ANDNPS:
5003                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5004                         break;
5005                 case OP_ORPS:
5006                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5007                         break;
5008                 case OP_XORPS:
5009                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5010                         break;
5011                 case OP_SQRTPS:
5012                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5013                         break;
5014                 case OP_RSQRTPS:
5015                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5016                         break;
5017                 case OP_RCPPS:
5018                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5019                         break;
5020                 case OP_ADDSUBPS:
5021                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5022                         break;
5023                 case OP_HADDPS:
5024                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5025                         break;
5026                 case OP_HSUBPS:
5027                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5028                         break;
5029                 case OP_DUPPS_HIGH:
5030                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5031                         break;
5032                 case OP_DUPPS_LOW:
5033                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5034                         break;
5035
5036                 case OP_PSHUFLEW_HIGH:
5037                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5038                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5039                         break;
5040                 case OP_PSHUFLEW_LOW:
5041                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5042                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5043                         break;
5044                 case OP_PSHUFLED:
5045                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5046                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5047                         break;
5048
5049                 case OP_ADDPD:
5050                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5051                         break;
5052                 case OP_DIVPD:
5053                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5054                         break;
5055                 case OP_MULPD:
5056                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5057                         break;
5058                 case OP_SUBPD:
5059                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5060                         break;
5061                 case OP_MAXPD:
5062                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5063                         break;
5064                 case OP_MINPD:
5065                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5066                         break;
5067                 case OP_COMPPD:
5068                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5069                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5070                         break;
5071                 case OP_ANDPD:
5072                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5073                         break;
5074                 case OP_ANDNPD:
5075                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5076                         break;
5077                 case OP_ORPD:
5078                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5079                         break;
5080                 case OP_XORPD:
5081                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5082                         break;
5083                 case OP_SQRTPD:
5084                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5085                         break;
5086                 case OP_ADDSUBPD:
5087                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5088                         break;
5089                 case OP_HADDPD:
5090                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5091                         break;
5092                 case OP_HSUBPD:
5093                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5094                         break;
5095                 case OP_DUPPD:
5096                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5097                         break;
5098
5099                 case OP_EXTRACT_MASK:
5100                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5101                         break;
5102
5103                 case OP_PAND:
5104                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5105                         break;
5106                 case OP_POR:
5107                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5108                         break;
5109                 case OP_PXOR:
5110                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5111                         break;
5112
5113                 case OP_PADDB:
5114                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5115                         break;
5116                 case OP_PADDW:
5117                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5118                         break;
5119                 case OP_PADDD:
5120                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5121                         break;
5122                 case OP_PADDQ:
5123                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5124                         break;
5125
5126                 case OP_PSUBB:
5127                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5128                         break;
5129                 case OP_PSUBW:
5130                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5131                         break;
5132                 case OP_PSUBD:
5133                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5134                         break;
5135                 case OP_PSUBQ:
5136                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5137                         break;
5138
5139                 case OP_PMAXB_UN:
5140                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5141                         break;
5142                 case OP_PMAXW_UN:
5143                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5144                         break;
5145                 case OP_PMAXD_UN:
5146                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5147                         break;
5148
5149                 case OP_PMAXB:
5150                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5151                         break;
5152                 case OP_PMAXW:
5153                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5154                         break;
5155                 case OP_PMAXD:
5156                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5157                         break;
5158
5159                 case OP_PAVGB_UN:
5160                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5161                         break;
5162                 case OP_PAVGW_UN:
5163                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5164                         break;
5165
5166                 case OP_PMINB_UN:
5167                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5168                         break;
5169                 case OP_PMINW_UN:
5170                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5171                         break;
5172                 case OP_PMIND_UN:
5173                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5174                         break;
5175
5176                 case OP_PMINB:
5177                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5178                         break;
5179                 case OP_PMINW:
5180                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5181                         break;
5182                 case OP_PMIND:
5183                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5184                         break;
5185
5186                 case OP_PCMPEQB:
5187                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5188                         break;
5189                 case OP_PCMPEQW:
5190                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5191                         break;
5192                 case OP_PCMPEQD:
5193                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5194                         break;
5195                 case OP_PCMPEQQ:
5196                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5197                         break;
5198
5199                 case OP_PCMPGTB:
5200                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5201                         break;
5202                 case OP_PCMPGTW:
5203                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5204                         break;
5205                 case OP_PCMPGTD:
5206                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5207                         break;
5208                 case OP_PCMPGTQ:
5209                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5210                         break;
5211
5212                 case OP_PSUM_ABS_DIFF:
5213                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5214                         break;
5215
5216                 case OP_UNPACK_LOWB:
5217                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5218                         break;
5219                 case OP_UNPACK_LOWW:
5220                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5221                         break;
5222                 case OP_UNPACK_LOWD:
5223                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5224                         break;
5225                 case OP_UNPACK_LOWQ:
5226                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5227                         break;
5228                 case OP_UNPACK_LOWPS:
5229                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5230                         break;
5231                 case OP_UNPACK_LOWPD:
5232                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5233                         break;
5234
5235                 case OP_UNPACK_HIGHB:
5236                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5237                         break;
5238                 case OP_UNPACK_HIGHW:
5239                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5240                         break;
5241                 case OP_UNPACK_HIGHD:
5242                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5243                         break;
5244                 case OP_UNPACK_HIGHQ:
5245                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5246                         break;
5247                 case OP_UNPACK_HIGHPS:
5248                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5249                         break;
5250                 case OP_UNPACK_HIGHPD:
5251                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5252                         break;
5253
5254                 case OP_PACKW:
5255                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5256                         break;
5257                 case OP_PACKD:
5258                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5259                         break;
5260                 case OP_PACKW_UN:
5261                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5262                         break;
5263                 case OP_PACKD_UN:
5264                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5265                         break;
5266
5267                 case OP_PADDB_SAT_UN:
5268                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5269                         break;
5270                 case OP_PSUBB_SAT_UN:
5271                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5272                         break;
5273                 case OP_PADDW_SAT_UN:
5274                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5275                         break;
5276                 case OP_PSUBW_SAT_UN:
5277                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5278                         break;
5279
5280                 case OP_PADDB_SAT:
5281                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5282                         break;
5283                 case OP_PSUBB_SAT:
5284                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5285                         break;
5286                 case OP_PADDW_SAT:
5287                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5288                         break;
5289                 case OP_PSUBW_SAT:
5290                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5291                         break;
5292
5293                 case OP_PMULW:
5294                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5295                         break;
5296                 case OP_PMULD:
5297                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5298                         break;
5299                 case OP_PMULQ:
5300                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5301                         break;
5302                 case OP_PMULW_HIGH_UN:
5303                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5304                         break;
5305                 case OP_PMULW_HIGH:
5306                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5307                         break;
5308
5309                 case OP_PSHRW:
5310                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5311                         break;
5312                 case OP_PSHRW_REG:
5313                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5314                         break;
5315
5316                 case OP_PSARW:
5317                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5318                         break;
5319                 case OP_PSARW_REG:
5320                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5321                         break;
5322
5323                 case OP_PSHLW:
5324                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5325                         break;
5326                 case OP_PSHLW_REG:
5327                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5328                         break;
5329
5330                 case OP_PSHRD:
5331                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5332                         break;
5333                 case OP_PSHRD_REG:
5334                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5335                         break;
5336
5337                 case OP_PSARD:
5338                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5339                         break;
5340                 case OP_PSARD_REG:
5341                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5342                         break;
5343
5344                 case OP_PSHLD:
5345                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5346                         break;
5347                 case OP_PSHLD_REG:
5348                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5349                         break;
5350
5351                 case OP_PSHRQ:
5352                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5353                         break;
5354                 case OP_PSHRQ_REG:
5355                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5356                         break;
5357
5358                 /*TODO: This is appart of the sse spec but not added
5359                 case OP_PSARQ:
5360                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5361                         break;
5362                 case OP_PSARQ_REG:
5363                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5364                         break;
5365                 */
5366
5367                 case OP_PSHLQ:
5368                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5369                         break;
5370                 case OP_PSHLQ_REG:
5371                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5372                         break;
5373
5374                 case OP_ICONV_TO_X:
5375                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5376                         break;
5377                 case OP_EXTRACT_I4:
5378                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5379                         break;
5380                 case OP_EXTRACT_I8:
5381                         if (ins->inst_c0) {
5382                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5383                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5384                         } else {
5385                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5386                         }
5387                         break;
5388                 case OP_EXTRACT_I1:
5389                 case OP_EXTRACT_U1:
5390                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5391                         if (ins->inst_c0)
5392                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5393                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5394                         break;
5395                 case OP_EXTRACT_I2:
5396                 case OP_EXTRACT_U2:
5397                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5398                         if (ins->inst_c0)
5399                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5400                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5401                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5402                         break;
5403                 case OP_EXTRACT_R8:
5404                         if (ins->inst_c0)
5405                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5406                         else
5407                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5408                         break;
5409                 case OP_INSERT_I2:
5410                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5411                         break;
5412                 case OP_EXTRACTX_U2:
5413                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5414                         break;
5415                 case OP_INSERTX_U1_SLOW:
5416                         /*sreg1 is the extracted ireg (scratch)
5417                         /sreg2 is the to be inserted ireg (scratch)
5418                         /dreg is the xreg to receive the value*/
5419
5420                         /*clear the bits from the extracted word*/
5421                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5422                         /*shift the value to insert if needed*/
5423                         if (ins->inst_c0 & 1)
5424                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5425                         /*join them together*/
5426                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5427                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5428                         break;
5429                 case OP_INSERTX_I4_SLOW:
5430                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5431                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5432                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5433                         break;
5434                 case OP_INSERTX_I8_SLOW:
5435                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5436                         if (ins->inst_c0)
5437                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5438                         else
5439                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5440                         break;
5441
5442                 case OP_INSERTX_R4_SLOW:
5443                         switch (ins->inst_c0) {
5444                         case 0:
5445                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5446                                 break;
5447                         case 1:
5448                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5449                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5450                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5451                                 break;
5452                         case 2:
5453                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5454                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5455                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5456                                 break;
5457                         case 3:
5458                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5459                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5460                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5461                                 break;
5462                         }
5463                         break;
5464                 case OP_INSERTX_R8_SLOW:
5465                         if (ins->inst_c0)
5466                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5467                         else
5468                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5469                         break;
5470                 case OP_STOREX_MEMBASE_REG:
5471                 case OP_STOREX_MEMBASE:
5472                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5473                         break;
5474                 case OP_LOADX_MEMBASE:
5475                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5476                         break;
5477                 case OP_LOADX_ALIGNED_MEMBASE:
5478                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5479                         break;
5480                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5481                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5482                         break;
5483                 case OP_STOREX_NTA_MEMBASE_REG:
5484                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5485                         break;
5486                 case OP_PREFETCH_MEMBASE:
5487                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5488                         break;
5489
5490                 case OP_XMOVE:
5491                         /*FIXME the peephole pass should have killed this*/
5492                         if (ins->dreg != ins->sreg1)
5493                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5494                         break;
5495                 case OP_XZERO:
5496                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5497                         break;
5498                 case OP_ICONV_TO_R8_RAW:
5499                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5500                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5501                         break;
5502
5503                 case OP_FCONV_TO_R8_X:
5504                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5505                         break;
5506
5507                 case OP_XCONV_R8_TO_I4:
5508                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5509                         switch (ins->backend.source_opcode) {
5510                         case OP_FCONV_TO_I1:
5511                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5512                                 break;
5513                         case OP_FCONV_TO_U1:
5514                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5515                                 break;
5516                         case OP_FCONV_TO_I2:
5517                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5518                                 break;
5519                         case OP_FCONV_TO_U2:
5520                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5521                                 break;
5522                         }
5523                         break;
5524
5525                 case OP_EXPAND_I2:
5526                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5527                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5528                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5529                         break;
5530                 case OP_EXPAND_I4:
5531                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5532                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5533                         break;
5534                 case OP_EXPAND_I8:
5535                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5536                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5537                         break;
5538                 case OP_EXPAND_R4:
5539                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5540                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5541                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5542                         break;
5543                 case OP_EXPAND_R8:
5544                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5545                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5546                         break;
5547 #endif
5548                 case OP_LIVERANGE_START: {
5549                         if (cfg->verbose_level > 1)
5550                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5551                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5552                         break;
5553                 }
5554                 case OP_LIVERANGE_END: {
5555                         if (cfg->verbose_level > 1)
5556                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5557                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5558                         break;
5559                 }
5560                 default:
5561                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5562                         g_assert_not_reached ();
5563                 }
5564
5565                 if ((code - cfg->native_code - offset) > max_len) {
5566                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5567                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5568                         g_assert_not_reached ();
5569                 }
5570
5571                 last_ins = ins;
5572                 last_offset = offset;
5573         }
5574
5575         cfg->code_len = code - cfg->native_code;
5576 }
5577
5578 #endif /* DISABLE_JIT */
5579
5580 void
5581 mono_arch_register_lowlevel_calls (void)
5582 {
5583         /* The signature doesn't matter */
5584         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5585 }
5586
5587 void
5588 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5589 {
5590         MonoJumpInfo *patch_info;
5591         gboolean compile_aot = !run_cctors;
5592
5593         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5594                 unsigned char *ip = patch_info->ip.i + code;
5595                 unsigned char *target;
5596
5597                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5598
5599                 if (compile_aot) {
5600                         switch (patch_info->type) {
5601                         case MONO_PATCH_INFO_BB:
5602                         case MONO_PATCH_INFO_LABEL:
5603                                 break;
5604                         default:
5605                                 /* No need to patch these */
5606                                 continue;
5607                         }
5608                 }
5609
5610                 switch (patch_info->type) {
5611                 case MONO_PATCH_INFO_NONE:
5612                         continue;
5613                 case MONO_PATCH_INFO_METHOD_REL:
5614                 case MONO_PATCH_INFO_R8:
5615                 case MONO_PATCH_INFO_R4:
5616                         g_assert_not_reached ();
5617                         continue;
5618                 case MONO_PATCH_INFO_BB:
5619                         break;
5620                 default:
5621                         break;
5622                 }
5623
5624                 /*
5625                  * Debug code to help track down problems where the target of a near call is
5626                  * is not valid.
5627                  */
5628                 if (amd64_is_near_call (ip)) {
5629                         gint64 disp = (guint8*)target - (guint8*)ip;
5630
5631                         if (!amd64_is_imm32 (disp)) {
5632                                 printf ("TYPE: %d\n", patch_info->type);
5633                                 switch (patch_info->type) {
5634                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5635                                         printf ("V: %s\n", patch_info->data.name);
5636                                         break;
5637                                 case MONO_PATCH_INFO_METHOD_JUMP:
5638                                 case MONO_PATCH_INFO_METHOD:
5639                                         printf ("V: %s\n", patch_info->data.method->name);
5640                                         break;
5641                                 default:
5642                                         break;
5643                                 }
5644                         }
5645                 }
5646
5647                 amd64_patch (ip, (gpointer)target);
5648         }
5649 }
5650
5651 #ifndef DISABLE_JIT
5652
5653 static int
5654 get_max_epilog_size (MonoCompile *cfg)
5655 {
5656         int max_epilog_size = 16;
5657
5658         if (cfg->method->save_lmf)
5659                 max_epilog_size += 256;
5660
5661         if (mono_jit_trace_calls != NULL)
5662                 max_epilog_size += 50;
5663
5664         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5665                 max_epilog_size += 50;
5666
5667         max_epilog_size += (AMD64_NREG * 2);
5668
5669         return max_epilog_size;
5670 }
5671
5672 /*
5673  * This macro is used for testing whenever the unwinder works correctly at every point
5674  * where an async exception can happen.
5675  */
5676 /* This will generate a SIGSEGV at the given point in the code */
5677 #define async_exc_point(code) do { \
5678     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5679          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5680              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5681          cfg->arch.async_point_count ++; \
5682     } \
5683 } while (0)
5684
5685 guint8 *
5686 mono_arch_emit_prolog (MonoCompile *cfg)
5687 {
5688         MonoMethod *method = cfg->method;
5689         MonoBasicBlock *bb;
5690         MonoMethodSignature *sig;
5691         MonoInst *ins;
5692         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5693         guint8 *code;
5694         CallInfo *cinfo;
5695         gint32 lmf_offset = cfg->arch.lmf_offset;
5696         gboolean args_clobbered = FALSE;
5697         gboolean trace = FALSE;
5698
5699         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
5700
5701         code = cfg->native_code = g_malloc (cfg->code_size);
5702
5703         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5704                 trace = TRUE;
5705
5706         /* Amount of stack space allocated by register saving code */
5707         pos = 0;
5708
5709         /* Offset between RSP and the CFA */
5710         cfa_offset = 0;
5711
5712         /*
5713          * The prolog consists of the following parts:
5714          * FP present:
5715          * - push rbp, mov rbp, rsp
5716          * - save callee saved regs using pushes
5717          * - allocate frame
5718          * - save rgctx if needed
5719          * - save lmf if needed
5720          * FP not present:
5721          * - allocate frame
5722          * - save rgctx if needed
5723          * - save lmf if needed
5724          * - save callee saved regs using moves
5725          */
5726
5727         // CFA = sp + 8
5728         cfa_offset = 8;
5729         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5730         // IP saved at CFA - 8
5731         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5732         async_exc_point (code);
5733
5734         if (!cfg->arch.omit_fp) {
5735                 amd64_push_reg (code, AMD64_RBP);
5736                 cfa_offset += 8;
5737                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5738                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5739                 async_exc_point (code);
5740 #ifdef HOST_WIN32
5741                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5742 #endif
5743
5744                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5745                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5746                 async_exc_point (code);
5747 #ifdef HOST_WIN32
5748                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5749 #endif
5750         }
5751
5752         /* Save callee saved registers */
5753         if (!cfg->arch.omit_fp && !method->save_lmf) {
5754                 int offset = cfa_offset;
5755
5756                 for (i = 0; i < AMD64_NREG; ++i)
5757                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5758                                 amd64_push_reg (code, i);
5759                                 pos += sizeof (gpointer);
5760                                 offset += 8;
5761                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5762                                 async_exc_point (code);
5763                         }
5764         }
5765
5766         /* The param area is always at offset 0 from sp */
5767         /* This needs to be allocated here, since it has to come after the spill area */
5768         if (cfg->arch.no_pushes && cfg->param_area) {
5769                 if (cfg->arch.omit_fp)
5770                         // FIXME:
5771                         g_assert_not_reached ();
5772                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5773         }
5774
5775         if (cfg->arch.omit_fp) {
5776                 /*
5777                  * On enter, the stack is misaligned by the the pushing of the return
5778                  * address. It is either made aligned by the pushing of %rbp, or by
5779                  * this.
5780                  */
5781                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5782                 if ((alloc_size % 16) == 0)
5783                         alloc_size += 8;
5784         } else {
5785                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5786
5787                 alloc_size -= pos;
5788         }
5789
5790         cfg->arch.stack_alloc_size = alloc_size;
5791
5792         /* Allocate stack frame */
5793         if (alloc_size) {
5794                 /* See mono_emit_stack_alloc */
5795 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5796                 guint32 remaining_size = alloc_size;
5797                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5798                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5799                 guint32 offset = code - cfg->native_code;
5800                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5801                         while (required_code_size >= (cfg->code_size - offset))
5802                                 cfg->code_size *= 2;
5803                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5804                         code = cfg->native_code + offset;
5805                         mono_jit_stats.code_reallocs++;
5806                 }
5807
5808                 while (remaining_size >= 0x1000) {
5809                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5810                         if (cfg->arch.omit_fp) {
5811                                 cfa_offset += 0x1000;
5812                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5813                         }
5814                         async_exc_point (code);
5815 #ifdef HOST_WIN32
5816                         if (cfg->arch.omit_fp)
5817                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5818 #endif
5819
5820                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5821                         remaining_size -= 0x1000;
5822                 }
5823                 if (remaining_size) {
5824                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5825                         if (cfg->arch.omit_fp) {
5826                                 cfa_offset += remaining_size;
5827                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5828                                 async_exc_point (code);
5829                         }
5830 #ifdef HOST_WIN32
5831                         if (cfg->arch.omit_fp)
5832                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5833 #endif
5834                 }
5835 #else
5836                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5837                 if (cfg->arch.omit_fp) {
5838                         cfa_offset += alloc_size;
5839                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5840                         async_exc_point (code);
5841                 }
5842 #endif
5843         }
5844
5845         /* Stack alignment check */
5846 #if 0
5847         {
5848                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5849                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5850                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5851                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5852                 amd64_breakpoint (code);
5853         }
5854 #endif
5855
5856 #ifndef TARGET_WIN32
5857         if (mini_get_debug_options ()->init_stacks) {
5858                 /* Fill the stack frame with a dummy value to force deterministic behavior */
5859
5860                 /* Save registers to the red zone */
5861                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5862                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5863
5864                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5865                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5866                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5867
5868                 amd64_cld (code);
5869                 amd64_prefix (code, X86_REP_PREFIX);
5870                 amd64_stosl (code);
5871
5872                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5873                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5874         }
5875 #endif
5876
5877         /* Save LMF */
5878         if (method->save_lmf) {
5879                 /*
5880                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5881                  */
5882                 /*
5883                  * sp is saved right before calls but we need to save it here too so
5884                  * async stack walks would work.
5885                  */
5886                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5887                 /* Skip method (only needed for trampoline LMF frames) */
5888                 /* Save callee saved regs */
5889                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5890                         int offset;
5891
5892                         switch (i) {
5893                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5894                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5895                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5896                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5897                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5898                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5899 #ifdef HOST_WIN32
5900                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5901                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5902 #endif
5903                         default:
5904                                 offset = -1;
5905                                 break;
5906                         }
5907
5908                         if (offset != -1) {
5909                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5910                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5911                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5912                         }
5913                 }
5914         }
5915
5916         /* Save callee saved registers */
5917         if (cfg->arch.omit_fp && !method->save_lmf) {
5918                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5919
5920                 /* Save caller saved registers after sp is adjusted */
5921                 /* The registers are saved at the bottom of the frame */
5922                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5923                 for (i = 0; i < AMD64_NREG; ++i)
5924                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5925                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5926                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5927                                 save_area_offset += 8;
5928                                 async_exc_point (code);
5929                         }
5930         }
5931
5932         /* store runtime generic context */
5933         if (cfg->rgctx_var) {
5934                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5935                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5936
5937                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5938         }
5939
5940         /* compute max_length in order to use short forward jumps */
5941         max_epilog_size = get_max_epilog_size (cfg);
5942         if (cfg->opt & MONO_OPT_BRANCH) {
5943                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5944                         MonoInst *ins;
5945                         int max_length = 0;
5946
5947                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5948                                 max_length += 6;
5949                         /* max alignment for loops */
5950                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5951                                 max_length += LOOP_ALIGNMENT;
5952
5953                         MONO_BB_FOR_EACH_INS (bb, ins) {
5954                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5955                         }
5956
5957                         /* Take prolog and epilog instrumentation into account */
5958                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5959                                 max_length += max_epilog_size;
5960
5961                         bb->max_length = max_length;
5962                 }
5963         }
5964
5965         sig = mono_method_signature (method);
5966         pos = 0;
5967
5968         cinfo = cfg->arch.cinfo;
5969
5970         if (sig->ret->type != MONO_TYPE_VOID) {
5971                 /* Save volatile arguments to the stack */
5972                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5973                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5974         }
5975
5976         /* Keep this in sync with emit_load_volatile_arguments */
5977         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5978                 ArgInfo *ainfo = cinfo->args + i;
5979                 gint32 stack_offset;
5980                 MonoType *arg_type;
5981
5982                 ins = cfg->args [i];
5983
5984                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5985                         /* Unused arguments */
5986                         continue;
5987
5988                 if (sig->hasthis && (i == 0))
5989                         arg_type = &mono_defaults.object_class->byval_arg;
5990                 else
5991                         arg_type = sig->params [i - sig->hasthis];
5992
5993                 stack_offset = ainfo->offset + ARGS_OFFSET;
5994
5995                 if (cfg->globalra) {
5996                         /* All the other moves are done by the register allocator */
5997                         switch (ainfo->storage) {
5998                         case ArgInFloatSSEReg:
5999                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6000                                 break;
6001                         case ArgValuetypeInReg:
6002                                 for (quad = 0; quad < 2; quad ++) {
6003                                         switch (ainfo->pair_storage [quad]) {
6004                                         case ArgInIReg:
6005                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6006                                                 break;
6007                                         case ArgInFloatSSEReg:
6008                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6009                                                 break;
6010                                         case ArgInDoubleSSEReg:
6011                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6012                                                 break;
6013                                         case ArgNone:
6014                                                 break;
6015                                         default:
6016                                                 g_assert_not_reached ();
6017                                         }
6018                                 }
6019                                 break;
6020                         default:
6021                                 break;
6022                         }
6023
6024                         continue;
6025                 }
6026
6027                 /* Save volatile arguments to the stack */
6028                 if (ins->opcode != OP_REGVAR) {
6029                         switch (ainfo->storage) {
6030                         case ArgInIReg: {
6031                                 guint32 size = 8;
6032
6033                                 /* FIXME: I1 etc */
6034                                 /*
6035                                 if (stack_offset & 0x1)
6036                                         size = 1;
6037                                 else if (stack_offset & 0x2)
6038                                         size = 2;
6039                                 else if (stack_offset & 0x4)
6040                                         size = 4;
6041                                 else
6042                                         size = 8;
6043                                 */
6044                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6045                                 break;
6046                         }
6047                         case ArgInFloatSSEReg:
6048                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6049                                 break;
6050                         case ArgInDoubleSSEReg:
6051                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6052                                 break;
6053                         case ArgValuetypeInReg:
6054                                 for (quad = 0; quad < 2; quad ++) {
6055                                         switch (ainfo->pair_storage [quad]) {
6056                                         case ArgInIReg:
6057                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6058                                                 break;
6059                                         case ArgInFloatSSEReg:
6060                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6061                                                 break;
6062                                         case ArgInDoubleSSEReg:
6063                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6064                                                 break;
6065                                         case ArgNone:
6066                                                 break;
6067                                         default:
6068                                                 g_assert_not_reached ();
6069                                         }
6070                                 }
6071                                 break;
6072                         case ArgValuetypeAddrInIReg:
6073                                 if (ainfo->pair_storage [0] == ArgInIReg)
6074                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6075                                 break;
6076                         default:
6077                                 break;
6078                         }
6079                 } else {
6080                         /* Argument allocated to (non-volatile) register */
6081                         switch (ainfo->storage) {
6082                         case ArgInIReg:
6083                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6084                                 break;
6085                         case ArgOnStack:
6086                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6087                                 break;
6088                         default:
6089                                 g_assert_not_reached ();
6090                         }
6091                 }
6092         }
6093
6094         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6095         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6096                 guint64 domain = (guint64)cfg->domain;
6097
6098                 args_clobbered = TRUE;
6099
6100                 /*
6101                  * The call might clobber argument registers, but they are already
6102                  * saved to the stack/global regs.
6103                  */
6104                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6105                         guint8 *buf, *no_domain_branch;
6106
6107                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6108                         if (cfg->compile_aot) {
6109                                 /* AOT code is only used in the root domain */
6110                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6111                         } else {
6112                                 if ((domain >> 32) == 0)
6113                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6114                                 else
6115                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6116                         }
6117                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6118                         no_domain_branch = code;
6119                         x86_branch8 (code, X86_CC_NE, 0, 0);
6120                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6121                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6122                         buf = code;
6123                         x86_branch8 (code, X86_CC_NE, 0, 0);
6124                         amd64_patch (no_domain_branch, code);
6125                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6126                                           (gpointer)"mono_jit_thread_attach", TRUE);
6127                         amd64_patch (buf, code);
6128 #ifdef HOST_WIN32
6129                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6130                         /* FIXME: Add a separate key for LMF to avoid this */
6131                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6132 #endif
6133                 } else {
6134                         g_assert (!cfg->compile_aot);
6135                         if (cfg->compile_aot) {
6136                                 /* AOT code is only used in the root domain */
6137                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6138                         } else {
6139                                 if ((domain >> 32) == 0)
6140                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6141                                 else
6142                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6143                         }
6144                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6145                                           (gpointer)"mono_jit_thread_attach", TRUE);
6146                 }
6147         }
6148
6149         if (method->save_lmf) {
6150                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6151                         /*
6152                          * Optimized version which uses the mono_lmf TLS variable instead of
6153                          * indirection through the mono_lmf_addr TLS variable.
6154                          */
6155                         /* %rax = previous_lmf */
6156                         x86_prefix (code, X86_FS_PREFIX);
6157                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6158
6159                         /* Save previous_lmf */
6160                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6161                         /* Set new lmf */
6162                         if (lmf_offset == 0) {
6163                                 x86_prefix (code, X86_FS_PREFIX);
6164                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6165                         } else {
6166                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6167                                 x86_prefix (code, X86_FS_PREFIX);
6168                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6169                         }
6170                 } else {
6171                         if (lmf_addr_tls_offset != -1) {
6172                                 /* Load lmf quicky using the FS register */
6173                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6174 #ifdef HOST_WIN32
6175                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6176                                 /* FIXME: Add a separate key for LMF to avoid this */
6177                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6178 #endif
6179                         }
6180                         else {
6181                                 /*
6182                                  * The call might clobber argument registers, but they are already
6183                                  * saved to the stack/global regs.
6184                                  */
6185                                 args_clobbered = TRUE;
6186                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6187                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6188                         }
6189
6190                         /* Save lmf_addr */
6191                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6192                         /* Save previous_lmf */
6193                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6194                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6195                         /* Set new lmf */
6196                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6197                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6198                 }
6199         }
6200
6201         if (trace) {
6202                 args_clobbered = TRUE;
6203                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6204         }
6205
6206         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6207                 args_clobbered = TRUE;
6208
6209         /*
6210          * Optimize the common case of the first bblock making a call with the same
6211          * arguments as the method. This works because the arguments are still in their
6212          * original argument registers.
6213          * FIXME: Generalize this
6214          */
6215         if (!args_clobbered) {
6216                 MonoBasicBlock *first_bb = cfg->bb_entry;
6217                 MonoInst *next;
6218
6219                 next = mono_bb_first_ins (first_bb);
6220                 if (!next && first_bb->next_bb) {
6221                         first_bb = first_bb->next_bb;
6222                         next = mono_bb_first_ins (first_bb);
6223                 }
6224
6225                 if (first_bb->in_count > 1)
6226                         next = NULL;
6227
6228                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6229                         ArgInfo *ainfo = cinfo->args + i;
6230                         gboolean match = FALSE;
6231
6232                         ins = cfg->args [i];
6233                         if (ins->opcode != OP_REGVAR) {
6234                                 switch (ainfo->storage) {
6235                                 case ArgInIReg: {
6236                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6237                                                 if (next->dreg == ainfo->reg) {
6238                                                         NULLIFY_INS (next);
6239                                                         match = TRUE;
6240                                                 } else {
6241                                                         next->opcode = OP_MOVE;
6242                                                         next->sreg1 = ainfo->reg;
6243                                                         /* Only continue if the instruction doesn't change argument regs */
6244                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6245                                                                 match = TRUE;
6246                                                 }
6247                                         }
6248                                         break;
6249                                 }
6250                                 default:
6251                                         break;
6252                                 }
6253                         } else {
6254                                 /* Argument allocated to (non-volatile) register */
6255                                 switch (ainfo->storage) {
6256                                 case ArgInIReg:
6257                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6258                                                 NULLIFY_INS (next);
6259                                                 match = TRUE;
6260                                         }
6261                                         break;
6262                                 default:
6263                                         break;
6264                                 }
6265                         }
6266
6267                         if (match) {
6268                                 next = next->next;
6269                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6270                                 if (!next)
6271                                         break;
6272                         }
6273                 }
6274         }
6275
6276         /* Initialize ss_trigger_page_var */
6277         if (cfg->arch.ss_trigger_page_var) {
6278                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6279
6280                 g_assert (!cfg->compile_aot);
6281                 g_assert (var->opcode == OP_REGOFFSET);
6282
6283                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6284                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6285         }
6286
6287         cfg->code_len = code - cfg->native_code;
6288
6289         g_assert (cfg->code_len < cfg->code_size);
6290
6291         return code;
6292 }
6293
6294 void
6295 mono_arch_emit_epilog (MonoCompile *cfg)
6296 {
6297         MonoMethod *method = cfg->method;
6298         int quad, pos, i;
6299         guint8 *code;
6300         int max_epilog_size;
6301         CallInfo *cinfo;
6302         gint32 lmf_offset = cfg->arch.lmf_offset;
6303
6304         max_epilog_size = get_max_epilog_size (cfg);
6305
6306         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6307                 cfg->code_size *= 2;
6308                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6309                 mono_jit_stats.code_reallocs++;
6310         }
6311
6312         code = cfg->native_code + cfg->code_len;
6313
6314         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6315                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6316
6317         /* the code restoring the registers must be kept in sync with OP_JMP */
6318         pos = 0;
6319
6320         if (method->save_lmf) {
6321                 /* check if we need to restore protection of the stack after a stack overflow */
6322                 if (mono_get_jit_tls_offset () != -1) {
6323                         guint8 *patch;
6324                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6325                         /* we load the value in a separate instruction: this mechanism may be
6326                          * used later as a safer way to do thread interruption
6327                          */
6328                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6329                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6330                         patch = code;
6331                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6332                         /* note that the call trampoline will preserve eax/edx */
6333                         x86_call_reg (code, X86_ECX);
6334                         x86_patch (patch, code);
6335                 } else {
6336                         /* FIXME: maybe save the jit tls in the prolog */
6337                 }
6338                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6339                         /*
6340                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6341                          * through the mono_lmf_addr TLS variable.
6342                          */
6343                         /* reg = previous_lmf */
6344                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6345                         x86_prefix (code, X86_FS_PREFIX);
6346                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6347                 } else {
6348                         /* Restore previous lmf */
6349                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6350                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6351                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6352                 }
6353
6354                 /* Restore caller saved regs */
6355                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6356                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6357                 }
6358                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6359                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6360                 }
6361                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6362                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6363                 }
6364                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6365                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6366                 }
6367                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6368                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6369                 }
6370                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6371                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6372                 }
6373 #ifdef HOST_WIN32
6374                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6375                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6376                 }
6377                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6378                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6379                 }
6380 #endif
6381         } else {
6382
6383                 if (cfg->arch.omit_fp) {
6384                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6385
6386                         for (i = 0; i < AMD64_NREG; ++i)
6387                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6388                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6389                                         save_area_offset += 8;
6390                                 }
6391                 }
6392                 else {
6393                         for (i = 0; i < AMD64_NREG; ++i)
6394                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6395                                         pos -= sizeof (gpointer);
6396
6397                         if (pos) {
6398                                 if (pos == - sizeof (gpointer)) {
6399                                         /* Only one register, so avoid lea */
6400                                         for (i = AMD64_NREG - 1; i > 0; --i)
6401                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6402                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6403                                                 }
6404                                 }
6405                                 else {
6406                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6407
6408                                         /* Pop registers in reverse order */
6409                                         for (i = AMD64_NREG - 1; i > 0; --i)
6410                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6411                                                         amd64_pop_reg (code, i);
6412                                                 }
6413                                 }
6414                         }
6415                 }
6416         }
6417
6418         /* Load returned vtypes into registers if needed */
6419         cinfo = cfg->arch.cinfo;
6420         if (cinfo->ret.storage == ArgValuetypeInReg) {
6421                 ArgInfo *ainfo = &cinfo->ret;
6422                 MonoInst *inst = cfg->ret;
6423
6424                 for (quad = 0; quad < 2; quad ++) {
6425                         switch (ainfo->pair_storage [quad]) {
6426                         case ArgInIReg:
6427                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6428                                 break;
6429                         case ArgInFloatSSEReg:
6430                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6431                                 break;
6432                         case ArgInDoubleSSEReg:
6433                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6434                                 break;
6435                         case ArgNone:
6436                                 break;
6437                         default:
6438                                 g_assert_not_reached ();
6439                         }
6440                 }
6441         }
6442
6443         if (cfg->arch.omit_fp) {
6444                 if (cfg->arch.stack_alloc_size)
6445                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6446         } else {
6447                 amd64_leave (code);
6448         }
6449         async_exc_point (code);
6450         amd64_ret (code);
6451
6452         cfg->code_len = code - cfg->native_code;
6453
6454         g_assert (cfg->code_len < cfg->code_size);
6455 }
6456
6457 void
6458 mono_arch_emit_exceptions (MonoCompile *cfg)
6459 {
6460         MonoJumpInfo *patch_info;
6461         int nthrows, i;
6462         guint8 *code;
6463         MonoClass *exc_classes [16];
6464         guint8 *exc_throw_start [16], *exc_throw_end [16];
6465         guint32 code_size = 0;
6466
6467         /* Compute needed space */
6468         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6469                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6470                         code_size += 40;
6471                 if (patch_info->type == MONO_PATCH_INFO_R8)
6472                         code_size += 8 + 15; /* sizeof (double) + alignment */
6473                 if (patch_info->type == MONO_PATCH_INFO_R4)
6474                         code_size += 4 + 15; /* sizeof (float) + alignment */
6475         }
6476
6477         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6478                 cfg->code_size *= 2;
6479                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6480                 mono_jit_stats.code_reallocs++;
6481         }
6482
6483         code = cfg->native_code + cfg->code_len;
6484
6485         /* add code to raise exceptions */
6486         nthrows = 0;
6487         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6488                 switch (patch_info->type) {
6489                 case MONO_PATCH_INFO_EXC: {
6490                         MonoClass *exc_class;
6491                         guint8 *buf, *buf2;
6492                         guint32 throw_ip;
6493
6494                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6495
6496                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6497                         g_assert (exc_class);
6498                         throw_ip = patch_info->ip.i;
6499
6500                         //x86_breakpoint (code);
6501                         /* Find a throw sequence for the same exception class */
6502                         for (i = 0; i < nthrows; ++i)
6503                                 if (exc_classes [i] == exc_class)
6504                                         break;
6505                         if (i < nthrows) {
6506                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6507                                 x86_jump_code (code, exc_throw_start [i]);
6508                                 patch_info->type = MONO_PATCH_INFO_NONE;
6509                         }
6510                         else {
6511                                 buf = code;
6512                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6513                                 buf2 = code;
6514
6515                                 if (nthrows < 16) {
6516                                         exc_classes [nthrows] = exc_class;
6517                                         exc_throw_start [nthrows] = code;
6518                                 }
6519                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6520
6521                                 patch_info->type = MONO_PATCH_INFO_NONE;
6522
6523                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6524
6525                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6526                                 while (buf < buf2)
6527                                         x86_nop (buf);
6528
6529                                 if (nthrows < 16) {
6530                                         exc_throw_end [nthrows] = code;
6531                                         nthrows ++;
6532                                 }
6533                         }
6534                         break;
6535                 }
6536                 default:
6537                         /* do nothing */
6538                         break;
6539                 }
6540         }
6541
6542         /* Handle relocations with RIP relative addressing */
6543         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6544                 gboolean remove = FALSE;
6545
6546                 switch (patch_info->type) {
6547                 case MONO_PATCH_INFO_R8:
6548                 case MONO_PATCH_INFO_R4: {
6549                         guint8 *pos;
6550
6551                         /* The SSE opcodes require a 16 byte alignment */
6552                         code = (guint8*)ALIGN_TO (code, 16);
6553
6554                         pos = cfg->native_code + patch_info->ip.i;
6555
6556                         if (IS_REX (pos [1]))
6557                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6558                         else
6559                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6560
6561                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6562                                 *(double*)code = *(double*)patch_info->data.target;
6563                                 code += sizeof (double);
6564                         } else {
6565                                 *(float*)code = *(float*)patch_info->data.target;
6566                                 code += sizeof (float);
6567                         }
6568
6569                         remove = TRUE;
6570                         break;
6571                 }
6572                 default:
6573                         break;
6574                 }
6575
6576                 if (remove) {
6577                         if (patch_info == cfg->patch_info)
6578                                 cfg->patch_info = patch_info->next;
6579                         else {
6580                                 MonoJumpInfo *tmp;
6581
6582                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6583                                         ;
6584                                 tmp->next = patch_info->next;
6585                         }
6586                 }
6587         }
6588
6589         cfg->code_len = code - cfg->native_code;
6590
6591         g_assert (cfg->code_len < cfg->code_size);
6592
6593 }
6594
6595 #endif /* DISABLE_JIT */
6596
6597 void*
6598 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6599 {
6600         guchar *code = p;
6601         CallInfo *cinfo = NULL;
6602         MonoMethodSignature *sig;
6603         MonoInst *inst;
6604         int i, n, stack_area = 0;
6605
6606         /* Keep this in sync with mono_arch_get_argument_info */
6607
6608         if (enable_arguments) {
6609                 /* Allocate a new area on the stack and save arguments there */
6610                 sig = mono_method_signature (cfg->method);
6611
6612                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6613
6614                 n = sig->param_count + sig->hasthis;
6615
6616                 stack_area = ALIGN_TO (n * 8, 16);
6617
6618                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6619
6620                 for (i = 0; i < n; ++i) {
6621                         inst = cfg->args [i];
6622
6623                         if (inst->opcode == OP_REGVAR)
6624                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6625                         else {
6626                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6627                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6628                         }
6629                 }
6630         }
6631
6632         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6633         amd64_set_reg_template (code, AMD64_ARG_REG1);
6634         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6635         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6636
6637         if (enable_arguments)
6638                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6639
6640         return code;
6641 }
6642
6643 enum {
6644         SAVE_NONE,
6645         SAVE_STRUCT,
6646         SAVE_EAX,
6647         SAVE_EAX_EDX,
6648         SAVE_XMM
6649 };
6650
6651 void*
6652 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6653 {
6654         guchar *code = p;
6655         int save_mode = SAVE_NONE;
6656         MonoMethod *method = cfg->method;
6657         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6658
6659         switch (ret_type->type) {
6660         case MONO_TYPE_VOID:
6661                 /* special case string .ctor icall */
6662                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6663                         save_mode = SAVE_EAX;
6664                 else
6665                         save_mode = SAVE_NONE;
6666                 break;
6667         case MONO_TYPE_I8:
6668         case MONO_TYPE_U8:
6669                 save_mode = SAVE_EAX;
6670                 break;
6671         case MONO_TYPE_R4:
6672         case MONO_TYPE_R8:
6673                 save_mode = SAVE_XMM;
6674                 break;
6675         case MONO_TYPE_GENERICINST:
6676                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6677                         save_mode = SAVE_EAX;
6678                         break;
6679                 }
6680                 /* Fall through */
6681         case MONO_TYPE_VALUETYPE:
6682                 save_mode = SAVE_STRUCT;
6683                 break;
6684         default:
6685                 save_mode = SAVE_EAX;
6686                 break;
6687         }
6688
6689         /* Save the result and copy it into the proper argument register */
6690         switch (save_mode) {
6691         case SAVE_EAX:
6692                 amd64_push_reg (code, AMD64_RAX);
6693                 /* Align stack */
6694                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6695                 if (enable_arguments)
6696                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6697                 break;
6698         case SAVE_STRUCT:
6699                 /* FIXME: */
6700                 if (enable_arguments)
6701                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6702                 break;
6703         case SAVE_XMM:
6704                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6705                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6706                 /* Align stack */
6707                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6708                 /*
6709                  * The result is already in the proper argument register so no copying
6710                  * needed.
6711                  */
6712                 break;
6713         case SAVE_NONE:
6714                 break;
6715         default:
6716                 g_assert_not_reached ();
6717         }
6718
6719         /* Set %al since this is a varargs call */
6720         if (save_mode == SAVE_XMM)
6721                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6722         else
6723                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6724
6725         if (preserve_argument_registers) {
6726                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6727                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6728         }
6729
6730         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6731         amd64_set_reg_template (code, AMD64_ARG_REG1);
6732         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6733
6734         if (preserve_argument_registers) {
6735                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6736                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6737         }
6738
6739         /* Restore result */
6740         switch (save_mode) {
6741         case SAVE_EAX:
6742                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6743                 amd64_pop_reg (code, AMD64_RAX);
6744                 break;
6745         case SAVE_STRUCT:
6746                 /* FIXME: */
6747                 break;
6748         case SAVE_XMM:
6749                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6750                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6751                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6752                 break;
6753         case SAVE_NONE:
6754                 break;
6755         default:
6756                 g_assert_not_reached ();
6757         }
6758
6759         return code;
6760 }
6761
6762 void
6763 mono_arch_flush_icache (guint8 *code, gint size)
6764 {
6765         /* Not needed */
6766 }
6767
6768 void
6769 mono_arch_flush_register_windows (void)
6770 {
6771 }
6772
6773 gboolean
6774 mono_arch_is_inst_imm (gint64 imm)
6775 {
6776         return amd64_is_imm32 (imm);
6777 }
6778
6779 /*
6780  * Determine whenever the trap whose info is in SIGINFO is caused by
6781  * integer overflow.
6782  */
6783 gboolean
6784 mono_arch_is_int_overflow (void *sigctx, void *info)
6785 {
6786         MonoContext ctx;
6787         guint8* rip;
6788         int reg;
6789         gint64 value;
6790
6791         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6792
6793         rip = (guint8*)ctx.rip;
6794
6795         if (IS_REX (rip [0])) {
6796                 reg = amd64_rex_b (rip [0]);
6797                 rip ++;
6798         }
6799         else
6800                 reg = 0;
6801
6802         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6803                 /* idiv REG */
6804                 reg += x86_modrm_rm (rip [1]);
6805
6806                 switch (reg) {
6807                 case AMD64_RAX:
6808                         value = ctx.rax;
6809                         break;
6810                 case AMD64_RBX:
6811                         value = ctx.rbx;
6812                         break;
6813                 case AMD64_RCX:
6814                         value = ctx.rcx;
6815                         break;
6816                 case AMD64_RDX:
6817                         value = ctx.rdx;
6818                         break;
6819                 case AMD64_RBP:
6820                         value = ctx.rbp;
6821                         break;
6822                 case AMD64_RSP:
6823                         value = ctx.rsp;
6824                         break;
6825                 case AMD64_RSI:
6826                         value = ctx.rsi;
6827                         break;
6828                 case AMD64_RDI:
6829                         value = ctx.rdi;
6830                         break;
6831                 case AMD64_R12:
6832                         value = ctx.r12;
6833                         break;
6834                 case AMD64_R13:
6835                         value = ctx.r13;
6836                         break;
6837                 case AMD64_R14:
6838                         value = ctx.r14;
6839                         break;
6840                 case AMD64_R15:
6841                         value = ctx.r15;
6842                         break;
6843                 default:
6844                         g_assert_not_reached ();
6845                         reg = -1;
6846                 }
6847
6848                 if (value == -1)
6849                         return TRUE;
6850         }
6851
6852         return FALSE;
6853 }
6854
6855 guint32
6856 mono_arch_get_patch_offset (guint8 *code)
6857 {
6858         return 3;
6859 }
6860
6861 /**
6862  * mono_breakpoint_clean_code:
6863  *
6864  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6865  * breakpoints in the original code, they are removed in the copy.
6866  *
6867  * Returns TRUE if no sw breakpoint was present.
6868  */
6869 gboolean
6870 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6871 {
6872         int i;
6873         gboolean can_write = TRUE;
6874         /*
6875          * If method_start is non-NULL we need to perform bound checks, since we access memory
6876          * at code - offset we could go before the start of the method and end up in a different
6877          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6878          * instead.
6879          */
6880         if (!method_start || code - offset >= method_start) {
6881                 memcpy (buf, code - offset, size);
6882         } else {
6883                 int diff = code - method_start;
6884                 memset (buf, 0, size);
6885                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6886         }
6887         code -= offset;
6888         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6889                 int idx = mono_breakpoint_info_index [i];
6890                 guint8 *ptr;
6891                 if (idx < 1)
6892                         continue;
6893                 ptr = mono_breakpoint_info [idx].address;
6894                 if (ptr >= code && ptr < code + size) {
6895                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6896                         can_write = FALSE;
6897                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6898                         buf [ptr - code] = saved_byte;
6899                 }
6900         }
6901         return can_write;
6902 }
6903
6904 gpointer
6905 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6906 {
6907         guint8 buf [10];
6908         guint32 reg;
6909         gint32 disp;
6910         guint8 rex = 0;
6911         MonoJitInfo *ji = NULL;
6912
6913 #ifdef ENABLE_LLVM
6914         /* code - 9 might be before the start of the method */
6915         /* FIXME: Avoid this expensive call somehow */
6916         ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6917 #endif
6918
6919         mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6920         code = buf + 9;
6921
6922         *displacement = 0;
6923
6924         code -= 7;
6925
6926         /*
6927          * A given byte sequence can match more than case here, so we have to be
6928          * really careful about the ordering of the cases. Longer sequences
6929          * come first.
6930          * There are two types of calls:
6931          * - direct calls: 0xff address_byte 8/32 bits displacement
6932          * - indirect calls: nop nop nop <call>
6933          * The nops make sure we don't confuse the instruction preceeding an indirect
6934          * call with a direct call.
6935          */
6936         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6937                 /* call OFFSET(%rip) */
6938                 disp = *(guint32*)(code + 3);
6939                 return (gpointer*)(code + disp + 7);
6940         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6941                 /* call *[reg+disp32] using indexed addressing */
6942                 /* The LLVM JIT emits this, and we emit it too for %r12 */
6943                 if (IS_REX (code [-1])) {
6944                         rex = code [-1];
6945                         g_assert (amd64_rex_x (rex) == 0);
6946                 }
6947                 reg = amd64_sib_base (code [2]);
6948                 disp = *(gint32*)(code + 3);
6949         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6950                 /* call *[reg+disp32] */
6951                 if (IS_REX (code [0]))
6952                         rex = code [0];
6953                 reg = amd64_modrm_rm (code [2]);
6954                 disp = *(gint32*)(code + 3);
6955                 /* R10 is clobbered by the IMT thunk code */
6956                 g_assert (reg != AMD64_R10);
6957         } else if (code [2] == 0xe8) {
6958                 /* call <ADDR> */
6959                 return NULL;
6960         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6961                 /* call *[r12+disp8] using indexed addressing */
6962                 if (IS_REX (code [2]))
6963                         rex = code [2];
6964                 reg = amd64_sib_base (code [5]);
6965                 disp = *(gint8*)(code + 6);
6966         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6967                 /* call *%reg */
6968                 return NULL;
6969         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6970                 /* call *[reg+disp8] */
6971                 if (IS_REX (code [3]))
6972                         rex = code [3];
6973                 reg = amd64_modrm_rm (code [5]);
6974                 disp = *(gint8*)(code + 6);
6975                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6976         }
6977         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6978                 /* call *%reg */
6979                 if (IS_REX (code [4]))
6980                         rex = code [4];
6981                 reg = amd64_modrm_rm (code [6]);
6982                 disp = 0;
6983         }
6984         else
6985                 g_assert_not_reached ();
6986
6987         reg += amd64_rex_b (rex);
6988
6989         /* R11 is clobbered by the trampoline code */
6990         g_assert (reg != AMD64_R11);
6991
6992         *displacement = disp;
6993         return (gpointer)regs [reg];
6994 }
6995
6996 int
6997 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6998 {
6999         int this_reg = AMD64_ARG_REG1;
7000
7001         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
7002                 CallInfo *cinfo;
7003
7004                 if (!gsctx && code)
7005                         gsctx = mono_get_generic_context_from_code (code);
7006
7007                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
7008
7009                 if (cinfo->ret.storage != ArgValuetypeInReg)
7010                         this_reg = AMD64_ARG_REG2;
7011                 g_free (cinfo);
7012         }
7013
7014         return this_reg;
7015 }
7016
7017 gpointer
7018 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
7019 {
7020         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
7021 }
7022
7023 #define MAX_ARCH_DELEGATE_PARAMS 10
7024
7025 static gpointer
7026 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7027 {
7028         guint8 *code, *start;
7029         int i;
7030
7031         if (has_target) {
7032                 start = code = mono_global_codeman_reserve (64);
7033
7034                 /* Replace the this argument with the target */
7035                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7036                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
7037                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7038
7039                 g_assert ((code - start) < 64);
7040         } else {
7041                 start = code = mono_global_codeman_reserve (64);
7042
7043                 if (param_count == 0) {
7044                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7045                 } else {
7046                         /* We have to shift the arguments left */
7047                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7048                         for (i = 0; i < param_count; ++i) {
7049 #ifdef HOST_WIN32
7050                                 if (i < 3)
7051                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7052                                 else
7053                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7054 #else
7055                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7056 #endif
7057                         }
7058
7059                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
7060                 }
7061                 g_assert ((code - start) < 64);
7062         }
7063
7064         mono_debug_add_delegate_trampoline (start, code - start);
7065
7066         if (code_len)
7067                 *code_len = code - start;
7068
7069         return start;
7070 }
7071
7072 /*
7073  * mono_arch_get_delegate_invoke_impls:
7074  *
7075  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7076  * trampolines.
7077  */
7078 GSList*
7079 mono_arch_get_delegate_invoke_impls (void)
7080 {
7081         GSList *res = NULL;
7082         guint8 *code;
7083         guint32 code_len;
7084         int i;
7085
7086         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7087         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7088
7089         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7090                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7091                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7092         }
7093
7094         return res;
7095 }
7096
7097 gpointer
7098 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7099 {
7100         guint8 *code, *start;
7101         int i;
7102
7103         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7104                 return NULL;
7105
7106         /* FIXME: Support more cases */
7107         if (MONO_TYPE_ISSTRUCT (sig->ret))
7108                 return NULL;
7109
7110         if (has_target) {
7111                 static guint8* cached = NULL;
7112
7113                 if (cached)
7114                         return cached;
7115
7116                 if (mono_aot_only)
7117                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7118                 else
7119                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7120
7121                 mono_memory_barrier ();
7122
7123                 cached = start;
7124         } else {
7125                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7126                 for (i = 0; i < sig->param_count; ++i)
7127                         if (!mono_is_regsize_var (sig->params [i]))
7128                                 return NULL;
7129                 if (sig->param_count > 4)
7130                         return NULL;
7131
7132                 code = cache [sig->param_count];
7133                 if (code)
7134                         return code;
7135
7136                 if (mono_aot_only) {
7137                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7138                         start = mono_aot_get_trampoline (name);
7139                         g_free (name);
7140                 } else {
7141                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7142                 }
7143
7144                 mono_memory_barrier ();
7145
7146                 cache [sig->param_count] = start;
7147         }
7148
7149         return start;
7150 }
7151
7152 /*
7153  * Support for fast access to the thread-local lmf structure using the GS
7154  * segment register on NPTL + kernel 2.6.x.
7155  */
7156
7157 static gboolean tls_offset_inited = FALSE;
7158
7159 void
7160 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7161 {
7162         if (!tls_offset_inited) {
7163 #ifdef HOST_WIN32
7164                 /*
7165                  * We need to init this multiple times, since when we are first called, the key might not
7166                  * be initialized yet.
7167                  */
7168                 appdomain_tls_offset = mono_domain_get_tls_key ();
7169                 lmf_tls_offset = mono_get_jit_tls_key ();
7170                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7171
7172                 /* Only 64 tls entries can be accessed using inline code */
7173                 if (appdomain_tls_offset >= 64)
7174                         appdomain_tls_offset = -1;
7175                 if (lmf_tls_offset >= 64)
7176                         lmf_tls_offset = -1;
7177 #else
7178                 tls_offset_inited = TRUE;
7179 #ifdef MONO_XEN_OPT
7180                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7181 #endif
7182                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7183                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7184                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7185 #endif
7186         }
7187 }
7188
7189 void
7190 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7191 {
7192 }
7193
7194 #ifdef MONO_ARCH_HAVE_IMT
7195
7196 #define CMP_SIZE (6 + 1)
7197 #define CMP_REG_REG_SIZE (4 + 1)
7198 #define BR_SMALL_SIZE 2
7199 #define BR_LARGE_SIZE 6
7200 #define MOV_REG_IMM_SIZE 10
7201 #define MOV_REG_IMM_32BIT_SIZE 6
7202 #define JUMP_REG_SIZE (2 + 1)
7203
7204 static int
7205 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7206 {
7207         int i, distance = 0;
7208         for (i = start; i < target; ++i)
7209                 distance += imt_entries [i]->chunk_size;
7210         return distance;
7211 }
7212
7213 /*
7214  * LOCKING: called with the domain lock held
7215  */
7216 gpointer
7217 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7218         gpointer fail_tramp)
7219 {
7220         int i;
7221         int size = 0;
7222         guint8 *code, *start;
7223         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7224
7225         for (i = 0; i < count; ++i) {
7226                 MonoIMTCheckItem *item = imt_entries [i];
7227                 if (item->is_equals) {
7228                         if (item->check_target_idx) {
7229                                 if (!item->compare_done) {
7230                                         if (amd64_is_imm32 (item->key))
7231                                                 item->chunk_size += CMP_SIZE;
7232                                         else
7233                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7234                                 }
7235                                 if (item->has_target_code) {
7236                                         item->chunk_size += MOV_REG_IMM_SIZE;
7237                                 } else {
7238                                         if (vtable_is_32bit)
7239                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7240                                         else
7241                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7242                                 }
7243                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7244                         } else {
7245                                 if (fail_tramp) {
7246                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7247                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7248                                 } else {
7249                                         if (vtable_is_32bit)
7250                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7251                                         else
7252                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7253                                         item->chunk_size += JUMP_REG_SIZE;
7254                                         /* with assert below:
7255                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7256                                          */
7257                                 }
7258                         }
7259                 } else {
7260                         if (amd64_is_imm32 (item->key))
7261                                 item->chunk_size += CMP_SIZE;
7262                         else
7263                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7264                         item->chunk_size += BR_LARGE_SIZE;
7265                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7266                 }
7267                 size += item->chunk_size;
7268         }
7269         if (fail_tramp)
7270                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7271         else
7272                 code = mono_domain_code_reserve (domain, size);
7273         start = code;
7274         for (i = 0; i < count; ++i) {
7275                 MonoIMTCheckItem *item = imt_entries [i];
7276                 item->code_target = code;
7277                 if (item->is_equals) {
7278                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7279
7280                         if (item->check_target_idx || fail_case) {
7281                                 if (!item->compare_done || fail_case) {
7282                                         if (amd64_is_imm32 (item->key))
7283                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7284                                         else {
7285                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7286                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7287                                         }
7288                                 }
7289                                 item->jmp_code = code;
7290                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7291                                 /* See the comment below about R10 */
7292                                 if (item->has_target_code) {
7293                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7294                                         amd64_jump_reg (code, AMD64_R10);
7295                                 } else {
7296                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7297                                         amd64_jump_membase (code, AMD64_R10, 0);
7298                                 }
7299
7300                                 if (fail_case) {
7301                                         amd64_patch (item->jmp_code, code);
7302                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7303                                         amd64_jump_reg (code, AMD64_R10);
7304                                         item->jmp_code = NULL;
7305                                 }
7306                         } else {
7307                                 /* enable the commented code to assert on wrong method */
7308 #if 0
7309                                 if (amd64_is_imm32 (item->key))
7310                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7311                                 else {
7312                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
7313                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7314                                 }
7315                                 item->jmp_code = code;
7316                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7317                                 /* See the comment below about R10 */
7318                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7319                                 amd64_jump_membase (code, AMD64_R10, 0);
7320                                 amd64_patch (item->jmp_code, code);
7321                                 amd64_breakpoint (code);
7322                                 item->jmp_code = NULL;
7323 #else
7324                                 /* We're using R10 here because R11
7325                                    needs to be preserved.  R10 needs
7326                                    to be preserved for calls which
7327                                    require a runtime generic context,
7328                                    but interface calls don't. */
7329                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7330                                 amd64_jump_membase (code, AMD64_R10, 0);
7331 #endif
7332                         }
7333                 } else {
7334                         if (amd64_is_imm32 (item->key))
7335                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7336                         else {
7337                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7338                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7339                         }
7340                         item->jmp_code = code;
7341                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7342                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7343                         else
7344                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7345                 }
7346                 g_assert (code - item->code_target <= item->chunk_size);
7347         }
7348         /* patch the branches to get to the target items */
7349         for (i = 0; i < count; ++i) {
7350                 MonoIMTCheckItem *item = imt_entries [i];
7351                 if (item->jmp_code) {
7352                         if (item->check_target_idx) {
7353                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7354                         }
7355                 }
7356         }
7357
7358         if (!fail_tramp)
7359                 mono_stats.imt_thunks_size += code - start;
7360         g_assert (code - start <= size);
7361
7362         return start;
7363 }
7364
7365 MonoMethod*
7366 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7367 {
7368         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7369 }
7370 #endif
7371
7372 MonoVTable*
7373 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7374 {
7375         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7376 }
7377
7378 GSList*
7379 mono_arch_get_cie_program (void)
7380 {
7381         GSList *l = NULL;
7382
7383         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7384         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7385
7386         return l;
7387 }
7388
7389 MonoInst*
7390 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7391 {
7392         MonoInst *ins = NULL;
7393         int opcode = 0;
7394
7395         if (cmethod->klass == mono_defaults.math_class) {
7396                 if (strcmp (cmethod->name, "Sin") == 0) {
7397                         opcode = OP_SIN;
7398                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7399                         opcode = OP_COS;
7400                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7401                         opcode = OP_SQRT;
7402                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7403                         opcode = OP_ABS;
7404                 }
7405
7406                 if (opcode) {
7407                         MONO_INST_NEW (cfg, ins, opcode);
7408                         ins->type = STACK_R8;
7409                         ins->dreg = mono_alloc_freg (cfg);
7410                         ins->sreg1 = args [0]->dreg;
7411                         MONO_ADD_INS (cfg->cbb, ins);
7412                 }
7413
7414                 opcode = 0;
7415                 if (cfg->opt & MONO_OPT_CMOV) {
7416                         if (strcmp (cmethod->name, "Min") == 0) {
7417                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7418                                         opcode = OP_IMIN;
7419                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7420                                         opcode = OP_IMIN_UN;
7421                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7422                                         opcode = OP_LMIN;
7423                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7424                                         opcode = OP_LMIN_UN;
7425                         } else if (strcmp (cmethod->name, "Max") == 0) {
7426                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7427                                         opcode = OP_IMAX;
7428                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7429                                         opcode = OP_IMAX_UN;
7430                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7431                                         opcode = OP_LMAX;
7432                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7433                                         opcode = OP_LMAX_UN;
7434                         }
7435                 }
7436
7437                 if (opcode) {
7438                         MONO_INST_NEW (cfg, ins, opcode);
7439                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7440                         ins->dreg = mono_alloc_ireg (cfg);
7441                         ins->sreg1 = args [0]->dreg;
7442                         ins->sreg2 = args [1]->dreg;
7443                         MONO_ADD_INS (cfg->cbb, ins);
7444                 }
7445
7446 #if 0
7447                 /* OP_FREM is not IEEE compatible */
7448                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7449                         MONO_INST_NEW (cfg, ins, OP_FREM);
7450                         ins->inst_i0 = args [0];
7451                         ins->inst_i1 = args [1];
7452                 }
7453 #endif
7454         }
7455
7456         /*
7457          * Can't implement CompareExchange methods this way since they have
7458          * three arguments.
7459          */
7460
7461         return ins;
7462 }
7463
7464 gboolean
7465 mono_arch_print_tree (MonoInst *tree, int arity)
7466 {
7467         return 0;
7468 }
7469
7470 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7471 {
7472         MonoInst* ins;
7473
7474         if (appdomain_tls_offset == -1)
7475                 return NULL;
7476
7477         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7478         ins->inst_offset = appdomain_tls_offset;
7479         return ins;
7480 }
7481
7482 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7483
7484 gpointer
7485 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7486 {
7487         switch (reg) {
7488         case AMD64_RCX: return (gpointer)ctx->rcx;
7489         case AMD64_RDX: return (gpointer)ctx->rdx;
7490         case AMD64_RBX: return (gpointer)ctx->rbx;
7491         case AMD64_RBP: return (gpointer)ctx->rbp;
7492         case AMD64_RSP: return (gpointer)ctx->rsp;
7493         default:
7494                 if (reg < 8)
7495                         return _CTX_REG (ctx, rax, reg);
7496                 else if (reg >= 12)
7497                         return _CTX_REG (ctx, r12, reg - 12);
7498                 else
7499                         g_assert_not_reached ();
7500         }
7501 }
7502
7503 /* Soft Debug support */
7504 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7505
7506 /*
7507  * mono_arch_set_breakpoint:
7508  *
7509  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7510  * The location should contain code emitted by OP_SEQ_POINT.
7511  */
7512 void
7513 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7514 {
7515         guint8 *code = ip;
7516         guint8 *orig_code = code;
7517
7518         /*
7519          * In production, we will use int3 (has to fix the size in the md
7520          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7521          * instead.
7522          */
7523         g_assert (code [0] == 0x90);
7524         if (breakpoint_size == 8) {
7525                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7526         } else {
7527                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7528                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7529         }
7530
7531         g_assert (code - orig_code == breakpoint_size);
7532 }
7533
7534 /*
7535  * mono_arch_clear_breakpoint:
7536  *
7537  *   Clear the breakpoint at IP.
7538  */
7539 void
7540 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7541 {
7542         guint8 *code = ip;
7543         int i;
7544
7545         for (i = 0; i < breakpoint_size; ++i)
7546                 x86_nop (code);
7547 }
7548
7549 gboolean
7550 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7551 {
7552 #ifdef HOST_WIN32
7553         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7554         return FALSE;
7555 #else
7556         siginfo_t* sinfo = (siginfo_t*) info;
7557         /* Sometimes the address is off by 4 */
7558         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7559                 return TRUE;
7560         else
7561                 return FALSE;
7562 #endif
7563 }
7564
7565 /*
7566  * mono_arch_get_ip_for_breakpoint:
7567  *
7568  *   Convert the ip in CTX to the address where a breakpoint was placed.
7569  */
7570 guint8*
7571 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7572 {
7573         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7574
7575         /* ip points to the instruction causing the fault */
7576         ip -= (breakpoint_size - breakpoint_fault_size);
7577
7578         return ip;
7579 }
7580
7581 /*
7582  * mono_arch_skip_breakpoint:
7583  *
7584  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7585  * we resume, the instruction is not executed again.
7586  */
7587 void
7588 mono_arch_skip_breakpoint (MonoContext *ctx)
7589 {
7590         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7591 }
7592
7593 /*
7594  * mono_arch_start_single_stepping:
7595  *
7596  *   Start single stepping.
7597  */
7598 void
7599 mono_arch_start_single_stepping (void)
7600 {
7601         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7602 }
7603
7604 /*
7605  * mono_arch_stop_single_stepping:
7606  *
7607  *   Stop single stepping.
7608  */
7609 void
7610 mono_arch_stop_single_stepping (void)
7611 {
7612         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7613 }
7614
7615 /*
7616  * mono_arch_is_single_step_event:
7617  *
7618  *   Return whenever the machine state in SIGCTX corresponds to a single
7619  * step event.
7620  */
7621 gboolean
7622 mono_arch_is_single_step_event (void *info, void *sigctx)
7623 {
7624 #ifdef HOST_WIN32
7625         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7626         return FALSE;
7627 #else
7628         siginfo_t* sinfo = (siginfo_t*) info;
7629         /* Sometimes the address is off by 4 */
7630         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7631                 return TRUE;
7632         else
7633                 return FALSE;
7634 #endif
7635 }
7636
7637 /*
7638  * mono_arch_get_ip_for_single_step:
7639  *
7640  *   Convert the ip in CTX to the address stored in seq_points.
7641  */
7642 guint8*
7643 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7644 {
7645         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7646
7647         ip += single_step_fault_size;
7648
7649         return ip;
7650 }
7651
7652 /*
7653  * mono_arch_skip_single_step:
7654  *
7655  *   Modify CTX so the ip is placed after the single step trigger instruction,
7656  * we resume, the instruction is not executed again.
7657  */
7658 void
7659 mono_arch_skip_single_step (MonoContext *ctx)
7660 {
7661         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7662 }
7663
7664 /*
7665  * mono_arch_create_seq_point_info:
7666  *
7667  *   Return a pointer to a data structure which is used by the sequence
7668  * point implementation in AOTed code.
7669  */
7670 gpointer
7671 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7672 {
7673         NOT_IMPLEMENTED;
7674         return NULL;
7675 }
7676
7677 #endif