mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internal.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35
  36 #include "trace.h"
  37 #include "ir-emit.h"
  38 #include "mini-amd64.h"
  39 #include "cpu-amd64.h"
  40 #include "debugger-agent.h"
  41 #include "mini-gc.h"
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef HOST_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() mono_mutex_lock (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() mono_mutex_unlock (&mini_arch_mutex)
  65 static mono_mutex_t mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 /*
  71  * The code generated for sequence points reads from this location, which is
  72  * made read-only when single stepping is enabled.
  73  */
  74 static gpointer ss_trigger_page;
  75
  76 /* Enabled breakpoints read from this trigger page */
  77 static gpointer bp_trigger_page;
  78
  79 /* The size of the breakpoint sequence */
  80 static int breakpoint_size;
  81
  82 /* The size of the breakpoint instruction causing the actual fault */
  83 static int breakpoint_fault_size;
  84
  85 /* The size of the single step instruction causing the actual fault */
  86 static int single_step_fault_size;
  87
  88 /* Offset between fp and the first argument in the callee */
  89 #define ARGS_OFFSET 16
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 static gboolean
 162 debug_omit_fp (void)
 163 {
 164 #if 0
 165         return mono_debug_count ();
 166 #else
 167         return TRUE;
 168 #endif
 169 }
 170
 171 static inline gboolean
 172 amd64_is_near_call (guint8 *code)
 173 {
 174         /* Skip REX */
 175         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 176                 code += 1;
 177
 178         return code [0] == 0xe8;
 179 }
 180
 181 #ifdef __native_client_codegen__
 182
 183 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 184 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 185 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 186 /* We only want to force bundle alignment for the top level instruction,    */
 187 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 188 static MonoNativeTlsKey nacl_instruction_depth;
 189
 190 static MonoNativeTlsKey nacl_rex_tag;
 191 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 192
 193 void
 194 amd64_nacl_clear_legacy_prefix_tag ()
 195 {
 196         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 197 }
 198
 199 void
 200 amd64_nacl_tag_legacy_prefix (guint8* code)
 201 {
 202         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 203                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 204 }
 205
 206 void
 207 amd64_nacl_tag_rex (guint8* code)
 208 {
 209         mono_native_tls_set_value (nacl_rex_tag, code);
 210 }
 211
 212 guint8*
 213 amd64_nacl_get_legacy_prefix_tag ()
 214 {
 215         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 216 }
 217
 218 guint8*
 219 amd64_nacl_get_rex_tag ()
 220 {
 221         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 222 }
 223
 224 /* Increment the instruction "depth" described above */
 225 void
 226 amd64_nacl_instruction_pre ()
 227 {
 228         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 229         depth++;
 230         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 231 }
 232
 233 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 234 /* alignment if depth == 0 (top level instruction)                          */
 235 /* IN: start, end    pointers to instruction beginning and end              */
 236 /* OUT: start, end   pointers to beginning and end after possible alignment */
 237 /* GLOBALS: nacl_instruction_depth     defined above                        */
 238 void
 239 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 240 {
 241         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 242         depth--;
 243         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 244
 245         g_assert ( depth >= 0 );
 246         if (depth == 0) {
 247                 uintptr_t space_in_block;
 248                 uintptr_t instlen;
 249                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 250                 /* if legacy prefix is present, and if it was emitted before */
 251                 /* the start of the instruction sequence, adjust the start   */
 252                 if (prefix != NULL && prefix < *start) {
 253                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 254                         *start = prefix;
 255                 }
 256                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 257                 instlen = (uintptr_t)(*end - *start);
 258                 /* Only check for instructions which are less than        */
 259                 /* kNaClAlignment. The only instructions that should ever */
 260                 /* be that long are call sequences, which are already     */
 261                 /* padded out to align the return to the next bundle.     */
 262                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 263                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 264                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 265                         const size_t length = (size_t)((*end)-(*start));
 266                         g_assert (length < MAX_NACL_INST_LENGTH);
 267
 268                         memcpy (copy_of_instruction, *start, length);
 269                         *start = mono_arch_nacl_pad (*start, space_in_block);
 270                         memcpy (*start, copy_of_instruction, length);
 271                         *end = *start + length;
 272                 }
 273                 amd64_nacl_clear_legacy_prefix_tag ();
 274                 amd64_nacl_tag_rex (NULL);
 275         }
 276 }
 277
 278 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 279 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 280 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 281 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 282 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 283 /* IN:      code                                                            */
 284 /*             pointer to current instruction stream (in the                */
 285 /*             middle of an instruction, after opcode is emitted)           */
 286 /*          basereg/offset/dreg                                             */
 287 /*             operands of normal membase address                           */
 288 /* OUT:     code                                                            */
 289 /*             pointer to the end of the membase/memindex emit              */
 290 /* GLOBALS: nacl_rex_tag                                                    */
 291 /*             position in instruction stream that rex prefix was emitted   */
 292 /*          nacl_legacy_prefix_tag                                          */
 293 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 294 void
 295 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 296 {
 297         gint8 true_basereg = basereg;
 298
 299         /* Cache these values, they might change  */
 300         /* as new instructions are emitted below. */
 301         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 302         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 303
 304         /* 'basereg' is given masked to 0x7 at this point, so check */
 305         /* the rex prefix to see if this is an extended register.   */
 306         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 307                 true_basereg |= 0x8;
 308         }
 309
 310 #define X86_LEA_OPCODE (0x8D)
 311
 312         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 313                 guint8* old_instruction_start;
 314
 315                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 316                 /* 32-bits of the old base register (new index register)     */
 317                 guint8 buf[32];
 318                 guint8* buf_ptr = buf;
 319                 size_t insert_len;
 320
 321                 g_assert (rex_tag != NULL);
 322
 323                 if (IS_REX(*rex_tag)) {
 324                         /* The old rex.B should be the new rex.X */
 325                         if (*rex_tag & AMD64_REX_B) {
 326                                 *rex_tag |= AMD64_REX_X;
 327                         }
 328                         /* Since our new base is %r15 set rex.B */
 329                         *rex_tag |= AMD64_REX_B;
 330                 } else {
 331                         /* Shift the instruction by one byte  */
 332                         /* so we can insert a rex prefix      */
 333                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 334                         *code += 1;
 335                         /* New rex prefix only needs rex.B for %r15 base */
 336                         *rex_tag = AMD64_REX(AMD64_REX_B);
 337                 }
 338
 339                 if (legacy_prefix_tag) {
 340                         old_instruction_start = legacy_prefix_tag;
 341                 } else {
 342                         old_instruction_start = rex_tag;
 343                 }
 344
 345                 /* Clears the upper 32-bits of the previous base register */
 346                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 347                 insert_len = buf_ptr - buf;
 348
 349                 /* Move the old instruction forward to make */
 350                 /* room for 'mov' stored in 'buf_ptr'       */
 351                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 352                 *code += insert_len;
 353                 memcpy (old_instruction_start, buf, insert_len);
 354
 355                 /* Sandboxed replacement for the normal membase_emit */
 356                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 357
 358         } else {
 359                 /* Normal default behavior, emit membase memory location */
 360                 x86_membase_emit_body (*code, dreg, basereg, offset);
 361         }
 362 }
 363
 364
 365 static inline unsigned char*
 366 amd64_skip_nops (unsigned char* code)
 367 {
 368         guint8 in_nop;
 369         do {
 370                 in_nop = 0;
 371                 if (   code[0] == 0x90) {
 372                         in_nop = 1;
 373                         code += 1;
 374                 }
 375                 if (   code[0] == 0x66 && code[1] == 0x90) {
 376                         in_nop = 1;
 377                         code += 2;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x00) {
 381                         in_nop = 1;
 382                         code += 3;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x40 && code[3] == 0x00) {
 386                         in_nop = 1;
 387                         code += 4;
 388                 }
 389                 if (code[0] == 0x0f && code[1] == 0x1f
 390                  && code[2] == 0x44 && code[3] == 0x00
 391                  && code[4] == 0x00) {
 392                         in_nop = 1;
 393                         code += 5;
 394                 }
 395                 if (code[0] == 0x66 && code[1] == 0x0f
 396                  && code[2] == 0x1f && code[3] == 0x44
 397                  && code[4] == 0x00 && code[5] == 0x00) {
 398                         in_nop = 1;
 399                         code += 6;
 400                 }
 401                 if (code[0] == 0x0f && code[1] == 0x1f
 402                  && code[2] == 0x80 && code[3] == 0x00
 403                  && code[4] == 0x00 && code[5] == 0x00
 404                  && code[6] == 0x00) {
 405                         in_nop = 1;
 406                         code += 7;
 407                 }
 408                 if (code[0] == 0x0f && code[1] == 0x1f
 409                  && code[2] == 0x84 && code[3] == 0x00
 410                  && code[4] == 0x00 && code[5] == 0x00
 411                  && code[6] == 0x00 && code[7] == 0x00) {
 412                         in_nop = 1;
 413                         code += 8;
 414                 }
 415         } while ( in_nop );
 416         return code;
 417 }
 418
 419 guint8*
 420 mono_arch_nacl_skip_nops (guint8* code)
 421 {
 422   return amd64_skip_nops(code);
 423 }
 424
 425 #endif /*__native_client_codegen__*/
 426
 427 static inline void
 428 amd64_patch (unsigned char* code, gpointer target)
 429 {
 430         guint8 rex = 0;
 431
 432 #ifdef __native_client_codegen__
 433         code = amd64_skip_nops (code);
 434 #endif
 435 #if defined(__native_client_codegen__) && defined(__native_client__)
 436         if (nacl_is_code_address (code)) {
 437                 /* For tail calls, code is patched after being installed */
 438                 /* but not through the normal "patch callsite" method.   */
 439                 unsigned char buf[kNaClAlignment];
 440                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 441                 int ret;
 442                 memcpy (buf, aligned_code, kNaClAlignment);
 443                 /* Patch a temp buffer of bundle size, */
 444                 /* then install to actual location.    */
 445                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 446                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 447                 g_assert (ret == 0);
 448                 return;
 449         }
 450         target = nacl_modify_patch_target (target);
 451 #endif
 452
 453         /* Skip REX */
 454         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 455                 rex = code [0];
 456                 code += 1;
 457         }
 458
 459         if ((code [0] & 0xf8) == 0xb8) {
 460                 /* amd64_set_reg_template */
 461                 *(guint64*)(code + 1) = (guint64)target;
 462         }
 463         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 464                 /* mov 0(%rip), %dreg */
 465                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 466         }
 467         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 468                 /* call *<OFFSET>(%rip) */
 469                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 470         }
 471         else if (code [0] == 0xe8) {
 472                 /* call <DISP> */
 473                 gint64 disp = (guint8*)target - (guint8*)code;
 474                 g_assert (amd64_is_imm32 (disp));
 475                 x86_patch (code, (unsigned char*)target);
 476         }
 477         else
 478                 x86_patch (code, (unsigned char*)target);
 479 }
 480
 481 void
 482 mono_amd64_patch (unsigned char* code, gpointer target)
 483 {
 484         amd64_patch (code, target);
 485 }
 486
 487 typedef enum {
 488         ArgInIReg,
 489         ArgInFloatSSEReg,
 490         ArgInDoubleSSEReg,
 491         ArgOnStack,
 492         ArgValuetypeInReg,
 493         ArgValuetypeAddrInIReg,
 494         ArgNone /* only in pair_storage */
 495 } ArgStorage;
 496
 497 typedef struct {
 498         gint16 offset;
 499         gint8  reg;
 500         ArgStorage storage;
 501
 502         /* Only if storage == ArgValuetypeInReg */
 503         ArgStorage pair_storage [2];
 504         gint8 pair_regs [2];
 505         /* The size of each pair */
 506         int pair_size [2];
 507         int nregs;
 508 } ArgInfo;
 509
 510 typedef struct {
 511         int nargs;
 512         guint32 stack_usage;
 513         guint32 reg_usage;
 514         guint32 freg_usage;
 515         gboolean need_stack_align;
 516         gboolean vtype_retaddr;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 #ifdef HOST_WIN32
 527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 528
 529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 530 #else
 531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 532
 533  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #endif
 535
 536 static void inline
 537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 538 {
 539     ainfo->offset = *stack_size;
 540
 541     if (*gr >= PARAM_REGS) {
 542                 ainfo->storage = ArgOnStack;
 543                 /* Since the same stack slot size is used for all arg */
 544                 /*  types, it needs to be big enough to hold them all */
 545                 (*stack_size) += sizeof(mgreg_t);
 546     }
 547     else {
 548                 ainfo->storage = ArgInIReg;
 549                 ainfo->reg = param_regs [*gr];
 550                 (*gr) ++;
 551     }
 552 }
 553
 554 #ifdef HOST_WIN32
 555 #define FLOAT_PARAM_REGS 4
 556 #else
 557 #define FLOAT_PARAM_REGS 8
 558 #endif
 559
 560 static void inline
 561 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 562 {
 563     ainfo->offset = *stack_size;
 564
 565     if (*gr >= FLOAT_PARAM_REGS) {
 566                 ainfo->storage = ArgOnStack;
 567                 /* Since the same stack slot size is used for both float */
 568                 /*  types, it needs to be big enough to hold them both */
 569                 (*stack_size) += sizeof(mgreg_t);
 570     }
 571     else {
 572                 /* A double register */
 573                 if (is_double)
 574                         ainfo->storage = ArgInDoubleSSEReg;
 575                 else
 576                         ainfo->storage = ArgInFloatSSEReg;
 577                 ainfo->reg = *gr;
 578                 (*gr) += 1;
 579     }
 580 }
 581
 582 typedef enum ArgumentClass {
 583         ARG_CLASS_NO_CLASS,
 584         ARG_CLASS_MEMORY,
 585         ARG_CLASS_INTEGER,
 586         ARG_CLASS_SSE
 587 } ArgumentClass;
 588
 589 static ArgumentClass
 590 merge_argument_class_from_type (MonoGenericSharingContext *gsctx, MonoType *type, ArgumentClass class1)
 591 {
 592         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 593         MonoType *ptype;
 594
 595         ptype = mini_type_get_underlying_type (gsctx, type);
 596         switch (ptype->type) {
 597         case MONO_TYPE_BOOLEAN:
 598         case MONO_TYPE_CHAR:
 599         case MONO_TYPE_I1:
 600         case MONO_TYPE_U1:
 601         case MONO_TYPE_I2:
 602         case MONO_TYPE_U2:
 603         case MONO_TYPE_I4:
 604         case MONO_TYPE_U4:
 605         case MONO_TYPE_I:
 606         case MONO_TYPE_U:
 607         case MONO_TYPE_STRING:
 608         case MONO_TYPE_OBJECT:
 609         case MONO_TYPE_CLASS:
 610         case MONO_TYPE_SZARRAY:
 611         case MONO_TYPE_PTR:
 612         case MONO_TYPE_FNPTR:
 613         case MONO_TYPE_ARRAY:
 614         case MONO_TYPE_I8:
 615         case MONO_TYPE_U8:
 616                 class2 = ARG_CLASS_INTEGER;
 617                 break;
 618         case MONO_TYPE_R4:
 619         case MONO_TYPE_R8:
 620 #ifdef HOST_WIN32
 621                 class2 = ARG_CLASS_INTEGER;
 622 #else
 623                 class2 = ARG_CLASS_SSE;
 624 #endif
 625                 break;
 626
 627         case MONO_TYPE_TYPEDBYREF:
 628                 g_assert_not_reached ();
 629
 630         case MONO_TYPE_GENERICINST:
 631                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 632                         class2 = ARG_CLASS_INTEGER;
 633                         break;
 634                 }
 635                 /* fall through */
 636         case MONO_TYPE_VALUETYPE: {
 637                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 638                 int i;
 639
 640                 for (i = 0; i < info->num_fields; ++i) {
 641                         class2 = class1;
 642                         class2 = merge_argument_class_from_type (gsctx, info->fields [i].field->type, class2);
 643                 }
 644                 break;
 645         }
 646         default:
 647                 g_assert_not_reached ();
 648         }
 649
 650         /* Merge */
 651         if (class1 == class2)
 652                 ;
 653         else if (class1 == ARG_CLASS_NO_CLASS)
 654                 class1 = class2;
 655         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 656                 class1 = ARG_CLASS_MEMORY;
 657         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 658                 class1 = ARG_CLASS_INTEGER;
 659         else
 660                 class1 = ARG_CLASS_SSE;
 661
 662         return class1;
 663 }
 664 #ifdef __native_client_codegen__
 665
 666 /* Default alignment for Native Client is 32-byte. */
 667 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 668
 669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 670 /* Check that alignment doesn't cross an alignment boundary.             */
 671 guint8*
 672 mono_arch_nacl_pad(guint8 *code, int pad)
 673 {
 674         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 675
 676         if (pad == 0) return code;
 677         /* assertion: alignment cannot cross a block boundary */
 678         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 679                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 680         while (pad >= kMaxPadding) {
 681                 amd64_padding (code, kMaxPadding);
 682                 pad -= kMaxPadding;
 683         }
 684         if (pad != 0) amd64_padding (code, pad);
 685         return code;
 686 }
 687 #endif
 688
 689 static int
 690 count_fields_nested (MonoClass *klass)
 691 {
 692         MonoMarshalType *info;
 693         int i, count;
 694
 695         info = mono_marshal_load_type_info (klass);
 696         g_assert(info);
 697         count = 0;
 698         for (i = 0; i < info->num_fields; ++i) {
 699                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 700                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 701                 else
 702                         count ++;
 703         }
 704         return count;
 705 }
 706
 707 static int
 708 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 709 {
 710         MonoMarshalType *info;
 711         int i;
 712
 713         info = mono_marshal_load_type_info (klass);
 714         g_assert(info);
 715         for (i = 0; i < info->num_fields; ++i) {
 716                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 717                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 718                 } else {
 719                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 720                         fields [index].offset += offset;
 721                         index ++;
 722                 }
 723         }
 724         return index;
 725 }
 726
 727 static void
 728 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 729                            gboolean is_return,
 730                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 731 {
 732         guint32 size, quad, nquads, i, nfields;
 733         /* Keep track of the size used in each quad so we can */
 734         /* use the right size when copying args/return vars.  */
 735         guint32 quadsize [2] = {8, 8};
 736         ArgumentClass args [2];
 737         MonoMarshalType *info = NULL;
 738         MonoMarshalField *fields = NULL;
 739         MonoClass *klass;
 740         MonoGenericSharingContext tmp_gsctx;
 741         gboolean pass_on_stack = FALSE;
 742
 743         /*
 744          * The gsctx currently contains no data, it is only used for checking whenever
 745          * open types are allowed, some callers like mono_arch_get_argument_info ()
 746          * don't pass it to us, so work around that.
 747          */
 748         if (!gsctx)
 749                 gsctx = &tmp_gsctx;
 750
 751         klass = mono_class_from_mono_type (type);
 752         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 753 #ifndef HOST_WIN32
 754         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 755                 /* We pass and return vtypes of size 8 in a register */
 756         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 757                 pass_on_stack = TRUE;
 758         }
 759 #else
 760         if (!sig->pinvoke) {
 761                 pass_on_stack = TRUE;
 762         }
 763 #endif
 764
 765         /* If this struct can't be split up naturally into 8-byte */
 766         /* chunks (registers), pass it on the stack.              */
 767         if (sig->pinvoke && !pass_on_stack) {
 768                 guint32 align;
 769                 guint32 field_size;
 770
 771                 info = mono_marshal_load_type_info (klass);
 772                 g_assert (info);
 773
 774                 /*
 775                  * Collect field information recursively to be able to
 776                  * handle nested structures.
 777                  */
 778                 nfields = count_fields_nested (klass);
 779                 fields = g_new0 (MonoMarshalField, nfields);
 780                 collect_field_info_nested (klass, fields, 0, 0);
 781
 782                 for (i = 0; i < nfields; ++i) {
 783                         field_size = mono_marshal_type_size (fields [i].field->type,
 784                                                            fields [i].mspec,
 785                                                            &align, TRUE, klass->unicode);
 786                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 787                                 pass_on_stack = TRUE;
 788                                 break;
 789                         }
 790                 }
 791         }
 792
 793         if (pass_on_stack) {
 794                 /* Allways pass in memory */
 795                 ainfo->offset = *stack_size;
 796                 *stack_size += ALIGN_TO (size, 8);
 797                 ainfo->storage = ArgOnStack;
 798
 799                 g_free (fields);
 800                 return;
 801         }
 802
 803         /* FIXME: Handle structs smaller than 8 bytes */
 804         //if ((size % 8) != 0)
 805         //      NOT_IMPLEMENTED;
 806
 807         if (size > 8)
 808                 nquads = 2;
 809         else
 810                 nquads = 1;
 811
 812         if (!sig->pinvoke) {
 813                 int n = mono_class_value_size (klass, NULL);
 814
 815                 quadsize [0] = n >= 8 ? 8 : n;
 816                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 817
 818                 /* Always pass in 1 or 2 integer registers */
 819                 args [0] = ARG_CLASS_INTEGER;
 820                 args [1] = ARG_CLASS_INTEGER;
 821                 /* Only the simplest cases are supported */
 822                 if (is_return && nquads != 1) {
 823                         args [0] = ARG_CLASS_MEMORY;
 824                         args [1] = ARG_CLASS_MEMORY;
 825                 }
 826         } else {
 827                 /*
 828                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 829                  * The X87 and SSEUP stuff is left out since there are no such types in
 830                  * the CLR.
 831                  */
 832                 g_assert (info);
 833                 g_assert (fields);
 834
 835 #ifndef HOST_WIN32
 836                 if (info->native_size > 16) {
 837                         ainfo->offset = *stack_size;
 838                         *stack_size += ALIGN_TO (info->native_size, 8);
 839                         ainfo->storage = ArgOnStack;
 840
 841                         g_free (fields);
 842                         return;
 843                 }
 844 #else
 845                 switch (info->native_size) {
 846                 case 1: case 2: case 4: case 8:
 847                         break;
 848                 default:
 849                         if (is_return) {
 850                                 ainfo->storage = ArgOnStack;
 851                                 ainfo->offset = *stack_size;
 852                                 *stack_size += ALIGN_TO (info->native_size, 8);
 853                         }
 854                         else {
 855                                 ainfo->storage = ArgValuetypeAddrInIReg;
 856
 857                                 if (*gr < PARAM_REGS) {
 858                                         ainfo->pair_storage [0] = ArgInIReg;
 859                                         ainfo->pair_regs [0] = param_regs [*gr];
 860                                         (*gr) ++;
 861                                 }
 862                                 else {
 863                                         ainfo->pair_storage [0] = ArgOnStack;
 864                                         ainfo->offset = *stack_size;
 865                                         *stack_size += 8;
 866                                 }
 867                         }
 868
 869                         g_free (fields);
 870                         return;
 871                 }
 872 #endif
 873
 874                 args [0] = ARG_CLASS_NO_CLASS;
 875                 args [1] = ARG_CLASS_NO_CLASS;
 876                 for (quad = 0; quad < nquads; ++quad) {
 877                         int size;
 878                         guint32 align;
 879                         ArgumentClass class1;
 880
 881                         if (nfields == 0)
 882                                 class1 = ARG_CLASS_MEMORY;
 883                         else
 884                                 class1 = ARG_CLASS_NO_CLASS;
 885                         for (i = 0; i < nfields; ++i) {
 886                                 size = mono_marshal_type_size (fields [i].field->type,
 887                                                                                            fields [i].mspec,
 888                                                                                            &align, TRUE, klass->unicode);
 889                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
 890                                         /* Unaligned field */
 891                                         NOT_IMPLEMENTED;
 892                                 }
 893
 894                                 /* Skip fields in other quad */
 895                                 if ((quad == 0) && (fields [i].offset >= 8))
 896                                         continue;
 897                                 if ((quad == 1) && (fields [i].offset < 8))
 898                                         continue;
 899
 900                                 /* How far into this quad this data extends.*/
 901                                 /* (8 is size of quad) */
 902                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
 903
 904                                 class1 = merge_argument_class_from_type (gsctx, fields [i].field->type, class1);
 905                         }
 906                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 907                         args [quad] = class1;
 908                 }
 909         }
 910
 911         g_free (fields);
 912
 913         /* Post merger cleanup */
 914         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 915                 args [0] = args [1] = ARG_CLASS_MEMORY;
 916
 917         /* Allocate registers */
 918         {
 919                 int orig_gr = *gr;
 920                 int orig_fr = *fr;
 921
 922                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 923                         quadsize [0] ++;
 924                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 925                         quadsize [1] ++;
 926
 927                 ainfo->storage = ArgValuetypeInReg;
 928                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 929                 g_assert (quadsize [0] <= 8);
 930                 g_assert (quadsize [1] <= 8);
 931                 ainfo->pair_size [0] = quadsize [0];
 932                 ainfo->pair_size [1] = quadsize [1];
 933                 ainfo->nregs = nquads;
 934                 for (quad = 0; quad < nquads; ++quad) {
 935                         switch (args [quad]) {
 936                         case ARG_CLASS_INTEGER:
 937                                 if (*gr >= PARAM_REGS)
 938                                         args [quad] = ARG_CLASS_MEMORY;
 939                                 else {
 940                                         ainfo->pair_storage [quad] = ArgInIReg;
 941                                         if (is_return)
 942                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 943                                         else
 944                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 945                                         (*gr) ++;
 946                                 }
 947                                 break;
 948                         case ARG_CLASS_SSE:
 949                                 if (*fr >= FLOAT_PARAM_REGS)
 950                                         args [quad] = ARG_CLASS_MEMORY;
 951                                 else {
 952                                         if (quadsize[quad] <= 4)
 953                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 954                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 955                                         ainfo->pair_regs [quad] = *fr;
 956                                         (*fr) ++;
 957                                 }
 958                                 break;
 959                         case ARG_CLASS_MEMORY:
 960                                 break;
 961                         default:
 962                                 g_assert_not_reached ();
 963                         }
 964                 }
 965
 966                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 967                         /* Revert possible register assignments */
 968                         *gr = orig_gr;
 969                         *fr = orig_fr;
 970
 971                         ainfo->offset = *stack_size;
 972                         if (sig->pinvoke)
 973                                 *stack_size += ALIGN_TO (info->native_size, 8);
 974                         else
 975                                 *stack_size += nquads * sizeof(mgreg_t);
 976                         ainfo->storage = ArgOnStack;
 977                 }
 978         }
 979 }
 980
 981 /*
 982  * get_call_info:
 983  *
 984  *  Obtain information about a call according to the calling convention.
 985  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 986  * Draft Version 0.23" document for more information.
 987  */
 988 static CallInfo*
 989 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig)
 990 {
 991         guint32 i, gr, fr, pstart;
 992         MonoType *ret_type;
 993         int n = sig->hasthis + sig->param_count;
 994         guint32 stack_size = 0;
 995         CallInfo *cinfo;
 996         gboolean is_pinvoke = sig->pinvoke;
 997
 998         if (mp)
 999                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1000         else
1001                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1002
1003         cinfo->nargs = n;
1004
1005         gr = 0;
1006         fr = 0;
1007
1008 #ifdef HOST_WIN32
1009         /* Reserve space where the callee can save the argument registers */
1010         stack_size = 4 * sizeof (mgreg_t);
1011 #endif
1012
1013         /* return value */
1014         {
1015                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
1016                 switch (ret_type->type) {
1017                 case MONO_TYPE_BOOLEAN:
1018                 case MONO_TYPE_I1:
1019                 case MONO_TYPE_U1:
1020                 case MONO_TYPE_I2:
1021                 case MONO_TYPE_U2:
1022                 case MONO_TYPE_CHAR:
1023                 case MONO_TYPE_I4:
1024                 case MONO_TYPE_U4:
1025                 case MONO_TYPE_I:
1026                 case MONO_TYPE_U:
1027                 case MONO_TYPE_PTR:
1028                 case MONO_TYPE_FNPTR:
1029                 case MONO_TYPE_CLASS:
1030                 case MONO_TYPE_OBJECT:
1031                 case MONO_TYPE_SZARRAY:
1032                 case MONO_TYPE_ARRAY:
1033                 case MONO_TYPE_STRING:
1034                         cinfo->ret.storage = ArgInIReg;
1035                         cinfo->ret.reg = AMD64_RAX;
1036                         break;
1037                 case MONO_TYPE_U8:
1038                 case MONO_TYPE_I8:
1039                         cinfo->ret.storage = ArgInIReg;
1040                         cinfo->ret.reg = AMD64_RAX;
1041                         break;
1042                 case MONO_TYPE_R4:
1043                         cinfo->ret.storage = ArgInFloatSSEReg;
1044                         cinfo->ret.reg = AMD64_XMM0;
1045                         break;
1046                 case MONO_TYPE_R8:
1047                         cinfo->ret.storage = ArgInDoubleSSEReg;
1048                         cinfo->ret.reg = AMD64_XMM0;
1049                         break;
1050                 case MONO_TYPE_GENERICINST:
1051                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1052                                 cinfo->ret.storage = ArgInIReg;
1053                                 cinfo->ret.reg = AMD64_RAX;
1054                                 break;
1055                         }
1056                         /* fall through */
1057 #if defined( __native_client_codegen__ )
1058                 case MONO_TYPE_TYPEDBYREF:
1059 #endif
1060                 case MONO_TYPE_VALUETYPE: {
1061                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1062
1063                         add_valuetype (gsctx, sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1064                         if (cinfo->ret.storage == ArgOnStack) {
1065                                 cinfo->vtype_retaddr = TRUE;
1066                                 /* The caller passes the address where the value is stored */
1067                         }
1068                         break;
1069                 }
1070 #if !defined( __native_client_codegen__ )
1071                 case MONO_TYPE_TYPEDBYREF:
1072                         /* Same as a valuetype with size 24 */
1073                         cinfo->vtype_retaddr = TRUE;
1074                         break;
1075 #endif
1076                 case MONO_TYPE_VOID:
1077                         break;
1078                 default:
1079                         g_error ("Can't handle as return value 0x%x", ret_type->type);
1080                 }
1081         }
1082
1083         pstart = 0;
1084         /*
1085          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1086          * the first argument, allowing 'this' to be always passed in the first arg reg.
1087          * Also do this if the first argument is a reference type, since virtual calls
1088          * are sometimes made using calli without sig->hasthis set, like in the delegate
1089          * invoke wrappers.
1090          */
1091         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
1092                 if (sig->hasthis) {
1093                         add_general (&gr, &stack_size, cinfo->args + 0);
1094                 } else {
1095                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1096                         pstart = 1;
1097                 }
1098                 add_general (&gr, &stack_size, &cinfo->ret);
1099                 cinfo->vret_arg_index = 1;
1100         } else {
1101                 /* this */
1102                 if (sig->hasthis)
1103                         add_general (&gr, &stack_size, cinfo->args + 0);
1104
1105                 if (cinfo->vtype_retaddr)
1106                         add_general (&gr, &stack_size, &cinfo->ret);
1107         }
1108
1109         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1110                 gr = PARAM_REGS;
1111                 fr = FLOAT_PARAM_REGS;
1112
1113                 /* Emit the signature cookie just before the implicit arguments */
1114                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1115         }
1116
1117         for (i = pstart; i < sig->param_count; ++i) {
1118                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1119                 MonoType *ptype;
1120
1121 #ifdef HOST_WIN32
1122                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1123                 if (gr > fr)
1124                         fr = gr;
1125                 else if (fr > gr)
1126                         gr = fr;
1127 #endif
1128
1129                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1130                         /* We allways pass the sig cookie on the stack for simplicity */
1131                         /*
1132                          * Prevent implicit arguments + the sig cookie from being passed
1133                          * in registers.
1134                          */
1135                         gr = PARAM_REGS;
1136                         fr = FLOAT_PARAM_REGS;
1137
1138                         /* Emit the signature cookie just before the implicit arguments */
1139                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1140                 }
1141
1142                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
1143                 switch (ptype->type) {
1144                 case MONO_TYPE_BOOLEAN:
1145                 case MONO_TYPE_I1:
1146                 case MONO_TYPE_U1:
1147                         add_general (&gr, &stack_size, ainfo);
1148                         break;
1149                 case MONO_TYPE_I2:
1150                 case MONO_TYPE_U2:
1151                 case MONO_TYPE_CHAR:
1152                         add_general (&gr, &stack_size, ainfo);
1153                         break;
1154                 case MONO_TYPE_I4:
1155                 case MONO_TYPE_U4:
1156                         add_general (&gr, &stack_size, ainfo);
1157                         break;
1158                 case MONO_TYPE_I:
1159                 case MONO_TYPE_U:
1160                 case MONO_TYPE_PTR:
1161                 case MONO_TYPE_FNPTR:
1162                 case MONO_TYPE_CLASS:
1163                 case MONO_TYPE_OBJECT:
1164                 case MONO_TYPE_STRING:
1165                 case MONO_TYPE_SZARRAY:
1166                 case MONO_TYPE_ARRAY:
1167                         add_general (&gr, &stack_size, ainfo);
1168                         break;
1169                 case MONO_TYPE_GENERICINST:
1170                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1171                                 add_general (&gr, &stack_size, ainfo);
1172                                 break;
1173                         }
1174                         /* fall through */
1175                 case MONO_TYPE_VALUETYPE:
1176                 case MONO_TYPE_TYPEDBYREF:
1177                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1178                         break;
1179                 case MONO_TYPE_U8:
1180
1181                 case MONO_TYPE_I8:
1182                         add_general (&gr, &stack_size, ainfo);
1183                         break;
1184                 case MONO_TYPE_R4:
1185                         add_float (&fr, &stack_size, ainfo, FALSE);
1186                         break;
1187                 case MONO_TYPE_R8:
1188                         add_float (&fr, &stack_size, ainfo, TRUE);
1189                         break;
1190                 default:
1191                         g_assert_not_reached ();
1192                 }
1193         }
1194
1195         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1196                 gr = PARAM_REGS;
1197                 fr = FLOAT_PARAM_REGS;
1198
1199                 /* Emit the signature cookie just before the implicit arguments */
1200                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1201         }
1202
1203         cinfo->stack_usage = stack_size;
1204         cinfo->reg_usage = gr;
1205         cinfo->freg_usage = fr;
1206         return cinfo;
1207 }
1208
1209 /*
1210  * mono_arch_get_argument_info:
1211  * @csig:  a method signature
1212  * @param_count: the number of parameters to consider
1213  * @arg_info: an array to store the result infos
1214  *
1215  * Gathers information on parameters such as size, alignment and
1216  * padding. arg_info should be large enought to hold param_count + 1 entries.
1217  *
1218  * Returns the size of the argument area on the stack.
1219  */
1220 int
1221 mono_arch_get_argument_info (MonoGenericSharingContext *gsctx, MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1222 {
1223         int k;
1224         CallInfo *cinfo = get_call_info (NULL, NULL, csig);
1225         guint32 args_size = cinfo->stack_usage;
1226
1227         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1228         if (csig->hasthis) {
1229                 arg_info [0].offset = 0;
1230         }
1231
1232         for (k = 0; k < param_count; k++) {
1233                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1234                 /* FIXME: */
1235                 arg_info [k + 1].size = 0;
1236         }
1237
1238         g_free (cinfo);
1239
1240         return args_size;
1241 }
1242
1243 gboolean
1244 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1245 {
1246         CallInfo *c1, *c2;
1247         gboolean res;
1248         MonoType *callee_ret;
1249
1250         c1 = get_call_info (NULL, NULL, caller_sig);
1251         c2 = get_call_info (NULL, NULL, callee_sig);
1252         res = c1->stack_usage >= c2->stack_usage;
1253         callee_ret = mini_get_underlying_type (cfg, callee_sig->ret);
1254         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1255                 /* An address on the callee's stack is passed as the first argument */
1256                 res = FALSE;
1257
1258         g_free (c1);
1259         g_free (c2);
1260
1261         return res;
1262 }
1263
1264 /*
1265  * Initialize the cpu to execute managed code.
1266  */
1267 void
1268 mono_arch_cpu_init (void)
1269 {
1270 #ifndef _MSC_VER
1271         guint16 fpcw;
1272
1273         /* spec compliance requires running with double precision */
1274         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1275         fpcw &= ~X86_FPCW_PRECC_MASK;
1276         fpcw |= X86_FPCW_PREC_DOUBLE;
1277         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1278         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1279 #else
1280         /* TODO: This is crashing on Win64 right now.
1281         * _control87 (_PC_53, MCW_PC);
1282         */
1283 #endif
1284 }
1285
1286 /*
1287  * Initialize architecture specific code.
1288  */
1289 void
1290 mono_arch_init (void)
1291 {
1292         int flags;
1293
1294         mono_mutex_init_recursive (&mini_arch_mutex);
1295 #if defined(__native_client_codegen__)
1296         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1297         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1298         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1299         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1300 #endif
1301
1302 #ifdef MONO_ARCH_NOMAP32BIT
1303         flags = MONO_MMAP_READ;
1304         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
1305         breakpoint_size = 13;
1306         breakpoint_fault_size = 3;
1307 #else
1308         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
1309         /* amd64_mov_reg_mem () */
1310         breakpoint_size = 8;
1311         breakpoint_fault_size = 8;
1312 #endif
1313
1314         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
1315         single_step_fault_size = 4;
1316
1317         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1318         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
1319         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
1320
1321         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1322         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1323         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1324 }
1325
1326 /*
1327  * Cleanup architecture specific code.
1328  */
1329 void
1330 mono_arch_cleanup (void)
1331 {
1332         mono_mutex_destroy (&mini_arch_mutex);
1333 #if defined(__native_client_codegen__)
1334         mono_native_tls_free (nacl_instruction_depth);
1335         mono_native_tls_free (nacl_rex_tag);
1336         mono_native_tls_free (nacl_legacy_prefix_tag);
1337 #endif
1338 }
1339
1340 /*
1341  * This function returns the optimizations supported on this cpu.
1342  */
1343 guint32
1344 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1345 {
1346         guint32 opts = 0;
1347
1348         *exclude_mask = 0;
1349
1350         if (mono_hwcap_x86_has_cmov) {
1351                 opts |= MONO_OPT_CMOV;
1352
1353                 if (mono_hwcap_x86_has_fcmov)
1354                         opts |= MONO_OPT_FCMOV;
1355                 else
1356                         *exclude_mask |= MONO_OPT_FCMOV;
1357         } else {
1358                 *exclude_mask |= MONO_OPT_CMOV;
1359         }
1360
1361         return opts;
1362 }
1363
1364 /*
1365  * This function test for all SSE functions supported.
1366  *
1367  * Returns a bitmask corresponding to all supported versions.
1368  *
1369  */
1370 guint32
1371 mono_arch_cpu_enumerate_simd_versions (void)
1372 {
1373         guint32 sse_opts = 0;
1374
1375         if (mono_hwcap_x86_has_sse1)
1376                 sse_opts |= SIMD_VERSION_SSE1;
1377
1378         if (mono_hwcap_x86_has_sse2)
1379                 sse_opts |= SIMD_VERSION_SSE2;
1380
1381         if (mono_hwcap_x86_has_sse3)
1382                 sse_opts |= SIMD_VERSION_SSE3;
1383
1384         if (mono_hwcap_x86_has_ssse3)
1385                 sse_opts |= SIMD_VERSION_SSSE3;
1386
1387         if (mono_hwcap_x86_has_sse41)
1388                 sse_opts |= SIMD_VERSION_SSE41;
1389
1390         if (mono_hwcap_x86_has_sse42)
1391                 sse_opts |= SIMD_VERSION_SSE42;
1392
1393         if (mono_hwcap_x86_has_sse4a)
1394                 sse_opts |= SIMD_VERSION_SSE4a;
1395
1396         return sse_opts;
1397 }
1398
1399 #ifndef DISABLE_JIT
1400
1401 GList *
1402 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1403 {
1404         GList *vars = NULL;
1405         int i;
1406
1407         for (i = 0; i < cfg->num_varinfo; i++) {
1408                 MonoInst *ins = cfg->varinfo [i];
1409                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1410
1411                 /* unused vars */
1412                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1413                         continue;
1414
1415                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1416                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1417                         continue;
1418
1419                 if (mono_is_regsize_var (ins->inst_vtype)) {
1420                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1421                         g_assert (i == vmv->idx);
1422                         vars = g_list_prepend (vars, vmv);
1423                 }
1424         }
1425
1426         vars = mono_varlist_sort (cfg, vars, 0);
1427
1428         return vars;
1429 }
1430
1431 /**
1432  * mono_arch_compute_omit_fp:
1433  *
1434  *   Determine whenever the frame pointer can be eliminated.
1435  */
1436 static void
1437 mono_arch_compute_omit_fp (MonoCompile *cfg)
1438 {
1439         MonoMethodSignature *sig;
1440         MonoMethodHeader *header;
1441         int i, locals_size;
1442         CallInfo *cinfo;
1443
1444         if (cfg->arch.omit_fp_computed)
1445                 return;
1446
1447         header = cfg->header;
1448
1449         sig = mono_method_signature (cfg->method);
1450
1451         if (!cfg->arch.cinfo)
1452                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
1453         cinfo = cfg->arch.cinfo;
1454
1455         /*
1456          * FIXME: Remove some of the restrictions.
1457          */
1458         cfg->arch.omit_fp = TRUE;
1459         cfg->arch.omit_fp_computed = TRUE;
1460
1461 #ifdef __native_client_codegen__
1462         /* NaCl modules may not change the value of RBP, so it cannot be */
1463         /* used as a normal register, but it can be used as a frame pointer*/
1464         cfg->disable_omit_fp = TRUE;
1465         cfg->arch.omit_fp = FALSE;
1466 #endif
1467
1468         if (cfg->disable_omit_fp)
1469                 cfg->arch.omit_fp = FALSE;
1470
1471         if (!debug_omit_fp ())
1472                 cfg->arch.omit_fp = FALSE;
1473         /*
1474         if (cfg->method->save_lmf)
1475                 cfg->arch.omit_fp = FALSE;
1476         */
1477         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1478                 cfg->arch.omit_fp = FALSE;
1479         if (header->num_clauses)
1480                 cfg->arch.omit_fp = FALSE;
1481         if (cfg->param_area)
1482                 cfg->arch.omit_fp = FALSE;
1483         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1484                 cfg->arch.omit_fp = FALSE;
1485         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1486                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1487                 cfg->arch.omit_fp = FALSE;
1488         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1489                 ArgInfo *ainfo = &cinfo->args [i];
1490
1491                 if (ainfo->storage == ArgOnStack) {
1492                         /*
1493                          * The stack offset can only be determined when the frame
1494                          * size is known.
1495                          */
1496                         cfg->arch.omit_fp = FALSE;
1497                 }
1498         }
1499
1500         locals_size = 0;
1501         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1502                 MonoInst *ins = cfg->varinfo [i];
1503                 int ialign;
1504
1505                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1506         }
1507 }
1508
1509 GList *
1510 mono_arch_get_global_int_regs (MonoCompile *cfg)
1511 {
1512         GList *regs = NULL;
1513
1514         mono_arch_compute_omit_fp (cfg);
1515
1516         if (cfg->globalra) {
1517                 if (cfg->arch.omit_fp)
1518                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1519
1520                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1521                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1522                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1523                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1524 #ifndef __native_client_codegen__
1525                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1526 #endif
1527
1528                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1529                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1530                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1531                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1532                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1533                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1534                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1535                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1536         } else {
1537                 if (cfg->arch.omit_fp)
1538                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1539
1540                 /* We use the callee saved registers for global allocation */
1541                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1542                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1543                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1544                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1545 #ifndef __native_client_codegen__
1546                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1547 #endif
1548 #ifdef HOST_WIN32
1549                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1550                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1551 #endif
1552         }
1553
1554         return regs;
1555 }
1556
1557 GList*
1558 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1559 {
1560         GList *regs = NULL;
1561         int i;
1562
1563         /* All XMM registers */
1564         for (i = 0; i < 16; ++i)
1565                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1566
1567         return regs;
1568 }
1569
1570 GList*
1571 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1572 {
1573         static GList *r = NULL;
1574
1575         if (r == NULL) {
1576                 GList *regs = NULL;
1577
1578                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1579                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1580                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1581                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1582                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1583 #ifndef __native_client_codegen__
1584                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1585 #endif
1586
1587                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1588                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1589                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1590                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1591                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1592                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1593                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1594                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1595
1596                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1597         }
1598
1599         return r;
1600 }
1601
1602 GList*
1603 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1604 {
1605         int i;
1606         static GList *r = NULL;
1607
1608         if (r == NULL) {
1609                 GList *regs = NULL;
1610
1611                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1612                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1613
1614                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1615         }
1616
1617         return r;
1618 }
1619
1620 /*
1621  * mono_arch_regalloc_cost:
1622  *
1623  *  Return the cost, in number of memory references, of the action of
1624  * allocating the variable VMV into a register during global register
1625  * allocation.
1626  */
1627 guint32
1628 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1629 {
1630         MonoInst *ins = cfg->varinfo [vmv->idx];
1631
1632         if (cfg->method->save_lmf)
1633                 /* The register is already saved */
1634                 /* substract 1 for the invisible store in the prolog */
1635                 return (ins->opcode == OP_ARG) ? 0 : 1;
1636         else
1637                 /* push+pop */
1638                 return (ins->opcode == OP_ARG) ? 1 : 2;
1639 }
1640
1641 /*
1642  * mono_arch_fill_argument_info:
1643  *
1644  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1645  * of the method.
1646  */
1647 void
1648 mono_arch_fill_argument_info (MonoCompile *cfg)
1649 {
1650         MonoType *sig_ret;
1651         MonoMethodSignature *sig;
1652         MonoInst *ins;
1653         int i;
1654         CallInfo *cinfo;
1655
1656         sig = mono_method_signature (cfg->method);
1657
1658         cinfo = cfg->arch.cinfo;
1659         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1660
1661         /*
1662          * Contrary to mono_arch_allocate_vars (), the information should describe
1663          * where the arguments are at the beginning of the method, not where they can be
1664          * accessed during the execution of the method. The later makes no sense for the
1665          * global register allocator, since a variable can be in more than one location.
1666          */
1667         if (sig_ret->type != MONO_TYPE_VOID) {
1668                 switch (cinfo->ret.storage) {
1669                 case ArgInIReg:
1670                 case ArgInFloatSSEReg:
1671                 case ArgInDoubleSSEReg:
1672                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1673                                 cfg->vret_addr->opcode = OP_REGVAR;
1674                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1675                         }
1676                         else {
1677                                 cfg->ret->opcode = OP_REGVAR;
1678                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1679                         }
1680                         break;
1681                 case ArgValuetypeInReg:
1682                         cfg->ret->opcode = OP_REGOFFSET;
1683                         cfg->ret->inst_basereg = -1;
1684                         cfg->ret->inst_offset = -1;
1685                         break;
1686                 default:
1687                         g_assert_not_reached ();
1688                 }
1689         }
1690
1691         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1692                 ArgInfo *ainfo = &cinfo->args [i];
1693
1694                 ins = cfg->args [i];
1695
1696                 switch (ainfo->storage) {
1697                 case ArgInIReg:
1698                 case ArgInFloatSSEReg:
1699                 case ArgInDoubleSSEReg:
1700                         ins->opcode = OP_REGVAR;
1701                         ins->inst_c0 = ainfo->reg;
1702                         break;
1703                 case ArgOnStack:
1704                         ins->opcode = OP_REGOFFSET;
1705                         ins->inst_basereg = -1;
1706                         ins->inst_offset = -1;
1707                         break;
1708                 case ArgValuetypeInReg:
1709                         /* Dummy */
1710                         ins->opcode = OP_NOP;
1711                         break;
1712                 default:
1713                         g_assert_not_reached ();
1714                 }
1715         }
1716 }
1717
1718 void
1719 mono_arch_allocate_vars (MonoCompile *cfg)
1720 {
1721         MonoType *sig_ret;
1722         MonoMethodSignature *sig;
1723         MonoInst *ins;
1724         int i, offset;
1725         guint32 locals_stack_size, locals_stack_align;
1726         gint32 *offsets;
1727         CallInfo *cinfo;
1728
1729         sig = mono_method_signature (cfg->method);
1730
1731         cinfo = cfg->arch.cinfo;
1732         sig_ret = mini_get_underlying_type (cfg, sig->ret);
1733
1734         mono_arch_compute_omit_fp (cfg);
1735
1736         /*
1737          * We use the ABI calling conventions for managed code as well.
1738          * Exception: valuetypes are only sometimes passed or returned in registers.
1739          */
1740
1741         /*
1742          * The stack looks like this:
1743          * <incoming arguments passed on the stack>
1744          * <return value>
1745          * <lmf/caller saved registers>
1746          * <locals>
1747          * <spill area>
1748          * <localloc area>  -> grows dynamically
1749          * <params area>
1750          */
1751
1752         if (cfg->arch.omit_fp) {
1753                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1754                 cfg->frame_reg = AMD64_RSP;
1755                 offset = 0;
1756         } else {
1757                 /* Locals are allocated backwards from %fp */
1758                 cfg->frame_reg = AMD64_RBP;
1759                 offset = 0;
1760         }
1761
1762         cfg->arch.saved_iregs = cfg->used_int_regs;
1763         if (cfg->method->save_lmf)
1764                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1765                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1766
1767         if (cfg->arch.omit_fp)
1768                 cfg->arch.reg_save_area_offset = offset;
1769         /* Reserve space for callee saved registers */
1770         for (i = 0; i < AMD64_NREG; ++i)
1771                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1772                         offset += sizeof(mgreg_t);
1773                 }
1774         if (!cfg->arch.omit_fp)
1775                 cfg->arch.reg_save_area_offset = -offset;
1776
1777         if (sig_ret->type != MONO_TYPE_VOID) {
1778                 switch (cinfo->ret.storage) {
1779                 case ArgInIReg:
1780                 case ArgInFloatSSEReg:
1781                 case ArgInDoubleSSEReg:
1782                         if ((MONO_TYPE_ISSTRUCT (sig_ret) && !mono_class_from_mono_type (sig_ret)->enumtype) || ((sig_ret->type == MONO_TYPE_TYPEDBYREF) && cinfo->vtype_retaddr)) {
1783                                 if (cfg->globalra) {
1784                                         cfg->vret_addr->opcode = OP_REGVAR;
1785                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1786                                 } else {
1787                                         /* The register is volatile */
1788                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1789                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1790                                         if (cfg->arch.omit_fp) {
1791                                                 cfg->vret_addr->inst_offset = offset;
1792                                                 offset += 8;
1793                                         } else {
1794                                                 offset += 8;
1795                                                 cfg->vret_addr->inst_offset = -offset;
1796                                         }
1797                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1798                                                 printf ("vret_addr =");
1799                                                 mono_print_ins (cfg->vret_addr);
1800                                         }
1801                                 }
1802                         }
1803                         else {
1804                                 cfg->ret->opcode = OP_REGVAR;
1805                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1806                         }
1807                         break;
1808                 case ArgValuetypeInReg:
1809                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1810                         cfg->ret->opcode = OP_REGOFFSET;
1811                         cfg->ret->inst_basereg = cfg->frame_reg;
1812                         if (cfg->arch.omit_fp) {
1813                                 cfg->ret->inst_offset = offset;
1814                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1815                         } else {
1816                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1817                                 cfg->ret->inst_offset = - offset;
1818                         }
1819                         break;
1820                 default:
1821                         g_assert_not_reached ();
1822                 }
1823                 if (!cfg->globalra)
1824                         cfg->ret->dreg = cfg->ret->inst_c0;
1825         }
1826
1827         /* Allocate locals */
1828         if (!cfg->globalra) {
1829                 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1830                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1831                         char *mname = mono_method_full_name (cfg->method, TRUE);
1832                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1833                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1834                         g_free (mname);
1835                         return;
1836                 }
1837
1838                 if (locals_stack_align) {
1839                         offset += (locals_stack_align - 1);
1840                         offset &= ~(locals_stack_align - 1);
1841                 }
1842                 if (cfg->arch.omit_fp) {
1843                         cfg->locals_min_stack_offset = offset;
1844                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1845                 } else {
1846                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1847                         cfg->locals_max_stack_offset = - offset;
1848                 }
1849
1850                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1851                         if (offsets [i] != -1) {
1852                                 MonoInst *ins = cfg->varinfo [i];
1853                                 ins->opcode = OP_REGOFFSET;
1854                                 ins->inst_basereg = cfg->frame_reg;
1855                                 if (cfg->arch.omit_fp)
1856                                         ins->inst_offset = (offset + offsets [i]);
1857                                 else
1858                                         ins->inst_offset = - (offset + offsets [i]);
1859                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1860                         }
1861                 }
1862                 offset += locals_stack_size;
1863         }
1864
1865         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1866                 g_assert (!cfg->arch.omit_fp);
1867                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1868                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1869         }
1870
1871         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1872                 ins = cfg->args [i];
1873                 if (ins->opcode != OP_REGVAR) {
1874                         ArgInfo *ainfo = &cinfo->args [i];
1875                         gboolean inreg = TRUE;
1876
1877                         if (cfg->globalra) {
1878                                 /* The new allocator needs info about the original locations of the arguments */
1879                                 switch (ainfo->storage) {
1880                                 case ArgInIReg:
1881                                 case ArgInFloatSSEReg:
1882                                 case ArgInDoubleSSEReg:
1883                                         ins->opcode = OP_REGVAR;
1884                                         ins->inst_c0 = ainfo->reg;
1885                                         break;
1886                                 case ArgOnStack:
1887                                         g_assert (!cfg->arch.omit_fp);
1888                                         ins->opcode = OP_REGOFFSET;
1889                                         ins->inst_basereg = cfg->frame_reg;
1890                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1891                                         break;
1892                                 case ArgValuetypeInReg:
1893                                         ins->opcode = OP_REGOFFSET;
1894                                         ins->inst_basereg = cfg->frame_reg;
1895                                         /* These arguments are saved to the stack in the prolog */
1896                                         offset = ALIGN_TO (offset, sizeof(mgreg_t));
1897                                         if (cfg->arch.omit_fp) {
1898                                                 ins->inst_offset = offset;
1899                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1900                                         } else {
1901                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1902                                                 ins->inst_offset = - offset;
1903                                         }
1904                                         break;
1905                                 default:
1906                                         g_assert_not_reached ();
1907                                 }
1908
1909                                 continue;
1910                         }
1911
1912                         /* FIXME: Allocate volatile arguments to registers */
1913                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1914                                 inreg = FALSE;
1915
1916                         /*
1917                          * Under AMD64, all registers used to pass arguments to functions
1918                          * are volatile across calls.
1919                          * FIXME: Optimize this.
1920                          */
1921                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1922                                 inreg = FALSE;
1923
1924                         ins->opcode = OP_REGOFFSET;
1925
1926                         switch (ainfo->storage) {
1927                         case ArgInIReg:
1928                         case ArgInFloatSSEReg:
1929                         case ArgInDoubleSSEReg:
1930                                 if (inreg) {
1931                                         ins->opcode = OP_REGVAR;
1932                                         ins->dreg = ainfo->reg;
1933                                 }
1934                                 break;
1935                         case ArgOnStack:
1936                                 g_assert (!cfg->arch.omit_fp);
1937                                 ins->opcode = OP_REGOFFSET;
1938                                 ins->inst_basereg = cfg->frame_reg;
1939                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1940                                 break;
1941                         case ArgValuetypeInReg:
1942                                 break;
1943                         case ArgValuetypeAddrInIReg: {
1944                                 MonoInst *indir;
1945                                 g_assert (!cfg->arch.omit_fp);
1946
1947                                 MONO_INST_NEW (cfg, indir, 0);
1948                                 indir->opcode = OP_REGOFFSET;
1949                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1950                                         indir->inst_basereg = cfg->frame_reg;
1951                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1952                                         offset += (sizeof (gpointer));
1953                                         indir->inst_offset = - offset;
1954                                 }
1955                                 else {
1956                                         indir->inst_basereg = cfg->frame_reg;
1957                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1958                                 }
1959
1960                                 ins->opcode = OP_VTARG_ADDR;
1961                                 ins->inst_left = indir;
1962
1963                                 break;
1964                         }
1965                         default:
1966                                 NOT_IMPLEMENTED;
1967                         }
1968
1969                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1970                                 ins->opcode = OP_REGOFFSET;
1971                                 ins->inst_basereg = cfg->frame_reg;
1972                                 /* These arguments are saved to the stack in the prolog */
1973                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1974                                 if (cfg->arch.omit_fp) {
1975                                         ins->inst_offset = offset;
1976                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1977                                         // Arguments are yet supported by the stack map creation code
1978                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1979                                 } else {
1980                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1981                                         ins->inst_offset = - offset;
1982                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1983                                 }
1984                         }
1985                 }
1986         }
1987
1988         cfg->stack_offset = offset;
1989 }
1990
1991 void
1992 mono_arch_create_vars (MonoCompile *cfg)
1993 {
1994         MonoMethodSignature *sig;
1995         CallInfo *cinfo;
1996         MonoType *sig_ret;
1997
1998         sig = mono_method_signature (cfg->method);
1999
2000         if (!cfg->arch.cinfo)
2001                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2002         cinfo = cfg->arch.cinfo;
2003
2004         if (cinfo->ret.storage == ArgValuetypeInReg)
2005                 cfg->ret_var_is_local = TRUE;
2006
2007         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2008         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig_ret)) {
2009                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2010                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2011                         printf ("vret_addr = ");
2012                         mono_print_ins (cfg->vret_addr);
2013                 }
2014         }
2015
2016         if (cfg->gen_seq_points_debug_data) {
2017                 MonoInst *ins;
2018
2019                 if (cfg->compile_aot) {
2020                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2021                         ins->flags |= MONO_INST_VOLATILE;
2022                         cfg->arch.seq_point_info_var = ins;
2023                 }
2024
2025             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2026                 ins->flags |= MONO_INST_VOLATILE;
2027                 cfg->arch.ss_trigger_page_var = ins;
2028         }
2029
2030         if (cfg->method->save_lmf)
2031                 cfg->create_lmf_var = TRUE;
2032
2033         if (cfg->method->save_lmf) {
2034                 cfg->lmf_ir = TRUE;
2035 #if !defined(HOST_WIN32)
2036                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2037                         cfg->lmf_ir_mono_lmf = TRUE;
2038 #endif
2039         }
2040 }
2041
2042 static void
2043 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2044 {
2045         MonoInst *ins;
2046
2047         switch (storage) {
2048         case ArgInIReg:
2049                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2050                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2051                 ins->sreg1 = tree->dreg;
2052                 MONO_ADD_INS (cfg->cbb, ins);
2053                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2054                 break;
2055         case ArgInFloatSSEReg:
2056                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2057                 ins->dreg = mono_alloc_freg (cfg);
2058                 ins->sreg1 = tree->dreg;
2059                 MONO_ADD_INS (cfg->cbb, ins);
2060
2061                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2062                 break;
2063         case ArgInDoubleSSEReg:
2064                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2065                 ins->dreg = mono_alloc_freg (cfg);
2066                 ins->sreg1 = tree->dreg;
2067                 MONO_ADD_INS (cfg->cbb, ins);
2068
2069                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2070
2071                 break;
2072         default:
2073                 g_assert_not_reached ();
2074         }
2075 }
2076
2077 static int
2078 arg_storage_to_load_membase (ArgStorage storage)
2079 {
2080         switch (storage) {
2081         case ArgInIReg:
2082 #if defined(__mono_ilp32__)
2083                 return OP_LOADI8_MEMBASE;
2084 #else
2085                 return OP_LOAD_MEMBASE;
2086 #endif
2087         case ArgInDoubleSSEReg:
2088                 return OP_LOADR8_MEMBASE;
2089         case ArgInFloatSSEReg:
2090                 return OP_LOADR4_MEMBASE;
2091         default:
2092                 g_assert_not_reached ();
2093         }
2094
2095         return -1;
2096 }
2097
2098 static void
2099 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2100 {
2101         MonoMethodSignature *tmp_sig;
2102         int sig_reg;
2103
2104         if (call->tail_call)
2105                 NOT_IMPLEMENTED;
2106
2107         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2108
2109         /*
2110          * mono_ArgIterator_Setup assumes the signature cookie is
2111          * passed first and all the arguments which were before it are
2112          * passed on the stack after the signature. So compensate by
2113          * passing a different signature.
2114          */
2115         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2116         tmp_sig->param_count -= call->signature->sentinelpos;
2117         tmp_sig->sentinelpos = 0;
2118         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2119
2120         sig_reg = mono_alloc_ireg (cfg);
2121         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2122
2123         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2124 }
2125
2126 #ifdef ENABLE_LLVM
2127 static inline LLVMArgStorage
2128 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2129 {
2130         switch (storage) {
2131         case ArgInIReg:
2132                 return LLVMArgInIReg;
2133         case ArgNone:
2134                 return LLVMArgNone;
2135         default:
2136                 g_assert_not_reached ();
2137                 return LLVMArgNone;
2138         }
2139 }
2140
2141 LLVMCallInfo*
2142 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2143 {
2144         int i, n;
2145         CallInfo *cinfo;
2146         ArgInfo *ainfo;
2147         int j;
2148         LLVMCallInfo *linfo;
2149         MonoType *t, *sig_ret;
2150
2151         n = sig->param_count + sig->hasthis;
2152         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2153
2154         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2155
2156         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2157
2158         /*
2159          * LLVM always uses the native ABI while we use our own ABI, the
2160          * only difference is the handling of vtypes:
2161          * - we only pass/receive them in registers in some cases, and only
2162          *   in 1 or 2 integer registers.
2163          */
2164         if (cinfo->ret.storage == ArgValuetypeInReg) {
2165                 if (sig->pinvoke) {
2166                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2167                         cfg->disable_llvm = TRUE;
2168                         return linfo;
2169                 }
2170
2171                 linfo->ret.storage = LLVMArgVtypeInReg;
2172                 for (j = 0; j < 2; ++j)
2173                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2174         }
2175
2176         if (MONO_TYPE_ISSTRUCT (sig_ret) && cinfo->ret.storage == ArgInIReg) {
2177                 /* Vtype returned using a hidden argument */
2178                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2179                 linfo->vret_arg_index = cinfo->vret_arg_index;
2180         }
2181
2182         for (i = 0; i < n; ++i) {
2183                 ainfo = cinfo->args + i;
2184
2185                 if (i >= sig->hasthis)
2186                         t = sig->params [i - sig->hasthis];
2187                 else
2188                         t = &mono_defaults.int_class->byval_arg;
2189
2190                 linfo->args [i].storage = LLVMArgNone;
2191
2192                 switch (ainfo->storage) {
2193                 case ArgInIReg:
2194                         linfo->args [i].storage = LLVMArgInIReg;
2195                         break;
2196                 case ArgInDoubleSSEReg:
2197                 case ArgInFloatSSEReg:
2198                         linfo->args [i].storage = LLVMArgInFPReg;
2199                         break;
2200                 case ArgOnStack:
2201                         if (MONO_TYPE_ISSTRUCT (t)) {
2202                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2203                         } else {
2204                                 linfo->args [i].storage = LLVMArgInIReg;
2205                                 if (!t->byref) {
2206                                         if (t->type == MONO_TYPE_R4)
2207                                                 linfo->args [i].storage = LLVMArgInFPReg;
2208                                         else if (t->type == MONO_TYPE_R8)
2209                                                 linfo->args [i].storage = LLVMArgInFPReg;
2210                                 }
2211                         }
2212                         break;
2213                 case ArgValuetypeInReg:
2214                         if (sig->pinvoke) {
2215                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2216                                 cfg->disable_llvm = TRUE;
2217                                 return linfo;
2218                         }
2219
2220                         linfo->args [i].storage = LLVMArgVtypeInReg;
2221                         for (j = 0; j < 2; ++j)
2222                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2223                         break;
2224                 default:
2225                         cfg->exception_message = g_strdup ("ainfo->storage");
2226                         cfg->disable_llvm = TRUE;
2227                         break;
2228                 }
2229         }
2230
2231         return linfo;
2232 }
2233 #endif
2234
2235 void
2236 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2237 {
2238         MonoInst *arg, *in;
2239         MonoMethodSignature *sig;
2240         MonoType *sig_ret;
2241         int i, n;
2242         CallInfo *cinfo;
2243         ArgInfo *ainfo;
2244
2245         sig = call->signature;
2246         n = sig->param_count + sig->hasthis;
2247
2248         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig);
2249
2250         sig_ret = sig->ret;
2251
2252         if (COMPILE_LLVM (cfg)) {
2253                 /* We shouldn't be called in the llvm case */
2254                 cfg->disable_llvm = TRUE;
2255                 return;
2256         }
2257
2258         /*
2259          * Emit all arguments which are passed on the stack to prevent register
2260          * allocation problems.
2261          */
2262         for (i = 0; i < n; ++i) {
2263                 MonoType *t;
2264                 ainfo = cinfo->args + i;
2265
2266                 in = call->args [i];
2267
2268                 if (sig->hasthis && i == 0)
2269                         t = &mono_defaults.object_class->byval_arg;
2270                 else
2271                         t = sig->params [i - sig->hasthis];
2272
2273                 t = mini_get_underlying_type (cfg, t);
2274                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2275                         if (!t->byref) {
2276                                 if (t->type == MONO_TYPE_R4)
2277                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2278                                 else if (t->type == MONO_TYPE_R8)
2279                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2280                                 else
2281                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2282                         } else {
2283                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2284                         }
2285                         if (cfg->compute_gc_maps) {
2286                                 MonoInst *def;
2287
2288                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2289                         }
2290                 }
2291         }
2292
2293         /*
2294          * Emit all parameters passed in registers in non-reverse order for better readability
2295          * and to help the optimization in emit_prolog ().
2296          */
2297         for (i = 0; i < n; ++i) {
2298                 ainfo = cinfo->args + i;
2299
2300                 in = call->args [i];
2301
2302                 if (ainfo->storage == ArgInIReg)
2303                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2304         }
2305
2306         for (i = n - 1; i >= 0; --i) {
2307                 ainfo = cinfo->args + i;
2308
2309                 in = call->args [i];
2310
2311                 switch (ainfo->storage) {
2312                 case ArgInIReg:
2313                         /* Already done */
2314                         break;
2315                 case ArgInFloatSSEReg:
2316                 case ArgInDoubleSSEReg:
2317                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2318                         break;
2319                 case ArgOnStack:
2320                 case ArgValuetypeInReg:
2321                 case ArgValuetypeAddrInIReg:
2322                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2323                                 MonoInst *call_inst = (MonoInst*)call;
2324                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2325                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2326                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
2327                                 guint32 align;
2328                                 guint32 size;
2329
2330                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
2331                                         size = sizeof (MonoTypedRef);
2332                                         align = sizeof (gpointer);
2333                                 }
2334                                 else {
2335                                         if (sig->pinvoke)
2336                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2337                                         else {
2338                                                 /*
2339                                                  * Other backends use mono_type_stack_size (), but that
2340                                                  * aligns the size to 8, which is larger than the size of
2341                                                  * the source, leading to reads of invalid memory if the
2342                                                  * source is at the end of address space.
2343                                                  */
2344                                                 size = mono_class_value_size (in->klass, &align);
2345                                         }
2346                                 }
2347                                 g_assert (in->klass);
2348
2349                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
2350                                         /* Avoid asserts in emit_memcpy () */
2351                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2352                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2353                                         /* Continue normally */
2354                                 }
2355
2356                                 if (size > 0) {
2357                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2358                                         arg->sreg1 = in->dreg;
2359                                         arg->klass = in->klass;
2360                                         arg->backend.size = size;
2361                                         arg->inst_p0 = call;
2362                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2363                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2364
2365                                         MONO_ADD_INS (cfg->cbb, arg);
2366                                 }
2367                         }
2368                         break;
2369                 default:
2370                         g_assert_not_reached ();
2371                 }
2372
2373                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2374                         /* Emit the signature cookie just before the implicit arguments */
2375                         emit_sig_cookie (cfg, call, cinfo);
2376         }
2377
2378         /* Handle the case where there are no implicit arguments */
2379         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2380                 emit_sig_cookie (cfg, call, cinfo);
2381
2382         sig_ret = mini_get_underlying_type (cfg, sig->ret);
2383         if (sig_ret && MONO_TYPE_ISSTRUCT (sig_ret)) {
2384                 MonoInst *vtarg;
2385
2386                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2387                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2388                                 /*
2389                                  * Tell the JIT to use a more efficient calling convention: call using
2390                                  * OP_CALL, compute the result location after the call, and save the
2391                                  * result there.
2392                                  */
2393                                 call->vret_in_reg = TRUE;
2394                                 /*
2395                                  * Nullify the instruction computing the vret addr to enable
2396                                  * future optimizations.
2397                                  */
2398                                 if (call->vret_var)
2399                                         NULLIFY_INS (call->vret_var);
2400                         } else {
2401                                 if (call->tail_call)
2402                                         NOT_IMPLEMENTED;
2403                                 /*
2404                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2405                                  * the stack. Push the address here, so the call instruction can
2406                                  * access it.
2407                                  */
2408                                 if (!cfg->arch.vret_addr_loc) {
2409                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2410                                         /* Prevent it from being register allocated or optimized away */
2411                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2412                                 }
2413
2414                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2415                         }
2416                 }
2417                 else {
2418                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2419                         vtarg->sreg1 = call->vret_var->dreg;
2420                         vtarg->dreg = mono_alloc_preg (cfg);
2421                         MONO_ADD_INS (cfg->cbb, vtarg);
2422
2423                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2424                 }
2425         }
2426
2427         if (cfg->method->save_lmf) {
2428                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2429                 MONO_ADD_INS (cfg->cbb, arg);
2430         }
2431
2432         call->stack_usage = cinfo->stack_usage;
2433 }
2434
2435 void
2436 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2437 {
2438         MonoInst *arg;
2439         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2440         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2441         int size = ins->backend.size;
2442
2443         if (ainfo->storage == ArgValuetypeInReg) {
2444                 MonoInst *load;
2445                 int part;
2446
2447                 for (part = 0; part < 2; ++part) {
2448                         if (ainfo->pair_storage [part] == ArgNone)
2449                                 continue;
2450
2451                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2452                         load->inst_basereg = src->dreg;
2453                         load->inst_offset = part * sizeof(mgreg_t);
2454
2455                         switch (ainfo->pair_storage [part]) {
2456                         case ArgInIReg:
2457                                 load->dreg = mono_alloc_ireg (cfg);
2458                                 break;
2459                         case ArgInDoubleSSEReg:
2460                         case ArgInFloatSSEReg:
2461                                 load->dreg = mono_alloc_freg (cfg);
2462                                 break;
2463                         default:
2464                                 g_assert_not_reached ();
2465                         }
2466                         MONO_ADD_INS (cfg->cbb, load);
2467
2468                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2469                 }
2470         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2471                 MonoInst *vtaddr, *load;
2472                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2473
2474                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2475                 cfg->has_indirection = TRUE;
2476                 load->inst_p0 = vtaddr;
2477                 vtaddr->flags |= MONO_INST_INDIRECT;
2478                 load->type = STACK_MP;
2479                 load->klass = vtaddr->klass;
2480                 load->dreg = mono_alloc_ireg (cfg);
2481                 MONO_ADD_INS (cfg->cbb, load);
2482                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2483
2484                 if (ainfo->pair_storage [0] == ArgInIReg) {
2485                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2486                         arg->dreg = mono_alloc_ireg (cfg);
2487                         arg->sreg1 = load->dreg;
2488                         arg->inst_imm = 0;
2489                         MONO_ADD_INS (cfg->cbb, arg);
2490                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2491                 } else {
2492                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2493                 }
2494         } else {
2495                 if (size == 8) {
2496                         int dreg = mono_alloc_ireg (cfg);
2497
2498                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2499                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2500                 } else if (size <= 40) {
2501                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2502                 } else {
2503                         // FIXME: Code growth
2504                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2505                 }
2506
2507                 if (cfg->compute_gc_maps) {
2508                         MonoInst *def;
2509                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2510                 }
2511         }
2512 }
2513
2514 void
2515 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2516 {
2517         MonoType *ret = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
2518
2519         if (ret->type == MONO_TYPE_R4) {
2520                 if (COMPILE_LLVM (cfg))
2521                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2522                 else
2523                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2524                 return;
2525         } else if (ret->type == MONO_TYPE_R8) {
2526                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2527                 return;
2528         }
2529
2530         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2531 }
2532
2533 #endif /* DISABLE_JIT */
2534
2535 #define EMIT_COND_BRANCH(ins,cond,sign) \
2536         if (ins->inst_true_bb->native_offset) { \
2537                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2538         } else { \
2539                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2540                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2541             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2542                         x86_branch8 (code, cond, 0, sign); \
2543                 else \
2544                         x86_branch32 (code, cond, 0, sign); \
2545 }
2546
2547 typedef struct {
2548         MonoMethodSignature *sig;
2549         CallInfo *cinfo;
2550 } ArchDynCallInfo;
2551
2552 static gboolean
2553 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2554 {
2555         int i;
2556
2557 #ifdef HOST_WIN32
2558         return FALSE;
2559 #endif
2560
2561         switch (cinfo->ret.storage) {
2562         case ArgNone:
2563         case ArgInIReg:
2564                 break;
2565         case ArgValuetypeInReg: {
2566                 ArgInfo *ainfo = &cinfo->ret;
2567
2568                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2569                         return FALSE;
2570                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2571                         return FALSE;
2572                 break;
2573         }
2574         default:
2575                 return FALSE;
2576         }
2577
2578         for (i = 0; i < cinfo->nargs; ++i) {
2579                 ArgInfo *ainfo = &cinfo->args [i];
2580                 switch (ainfo->storage) {
2581                 case ArgInIReg:
2582                         break;
2583                 case ArgValuetypeInReg:
2584                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2585                                 return FALSE;
2586                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2587                                 return FALSE;
2588                         break;
2589                 default:
2590                         return FALSE;
2591                 }
2592         }
2593
2594         return TRUE;
2595 }
2596
2597 /*
2598  * mono_arch_dyn_call_prepare:
2599  *
2600  *   Return a pointer to an arch-specific structure which contains information
2601  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2602  * supported for SIG.
2603  * This function is equivalent to ffi_prep_cif in libffi.
2604  */
2605 MonoDynCallInfo*
2606 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2607 {
2608         ArchDynCallInfo *info;
2609         CallInfo *cinfo;
2610
2611         cinfo = get_call_info (NULL, NULL, sig);
2612
2613         if (!dyn_call_supported (sig, cinfo)) {
2614                 g_free (cinfo);
2615                 return NULL;
2616         }
2617
2618         info = g_new0 (ArchDynCallInfo, 1);
2619         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2620         info->sig = sig;
2621         info->cinfo = cinfo;
2622
2623         return (MonoDynCallInfo*)info;
2624 }
2625
2626 /*
2627  * mono_arch_dyn_call_free:
2628  *
2629  *   Free a MonoDynCallInfo structure.
2630  */
2631 void
2632 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2633 {
2634         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2635
2636         g_free (ainfo->cinfo);
2637         g_free (ainfo);
2638 }
2639
2640 #if !defined(__native_client__)
2641 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2642 #define GREG_TO_PTR(greg) (gpointer)(greg)
2643 #else
2644 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2645 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2646 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2647 #endif
2648
2649 /*
2650  * mono_arch_get_start_dyn_call:
2651  *
2652  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2653  * store the result into BUF.
2654  * ARGS should be an array of pointers pointing to the arguments.
2655  * RET should point to a memory buffer large enought to hold the result of the
2656  * call.
2657  * This function should be as fast as possible, any work which does not depend
2658  * on the actual values of the arguments should be done in
2659  * mono_arch_dyn_call_prepare ().
2660  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2661  * libffi.
2662  */
2663 void
2664 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2665 {
2666         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2667         DynCallArgs *p = (DynCallArgs*)buf;
2668         int arg_index, greg, i, pindex;
2669         MonoMethodSignature *sig = dinfo->sig;
2670
2671         g_assert (buf_len >= sizeof (DynCallArgs));
2672
2673         p->res = 0;
2674         p->ret = ret;
2675
2676         arg_index = 0;
2677         greg = 0;
2678         pindex = 0;
2679
2680         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2681                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2682                 if (!sig->hasthis)
2683                         pindex = 1;
2684         }
2685
2686         if (dinfo->cinfo->vtype_retaddr)
2687                 p->regs [greg ++] = PTR_TO_GREG(ret);
2688
2689         for (i = pindex; i < sig->param_count; i++) {
2690                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2691                 gpointer *arg = args [arg_index ++];
2692
2693                 if (t->byref) {
2694                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2695                         continue;
2696                 }
2697
2698                 switch (t->type) {
2699                 case MONO_TYPE_STRING:
2700                 case MONO_TYPE_CLASS:
2701                 case MONO_TYPE_ARRAY:
2702                 case MONO_TYPE_SZARRAY:
2703                 case MONO_TYPE_OBJECT:
2704                 case MONO_TYPE_PTR:
2705                 case MONO_TYPE_I:
2706                 case MONO_TYPE_U:
2707 #if !defined(__mono_ilp32__)
2708                 case MONO_TYPE_I8:
2709                 case MONO_TYPE_U8:
2710 #endif
2711                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2712                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2713                         break;
2714 #if defined(__mono_ilp32__)
2715                 case MONO_TYPE_I8:
2716                 case MONO_TYPE_U8:
2717                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2718                         p->regs [greg ++] = *(guint64*)(arg);
2719                         break;
2720 #endif
2721                 case MONO_TYPE_BOOLEAN:
2722                 case MONO_TYPE_U1:
2723                         p->regs [greg ++] = *(guint8*)(arg);
2724                         break;
2725                 case MONO_TYPE_I1:
2726                         p->regs [greg ++] = *(gint8*)(arg);
2727                         break;
2728                 case MONO_TYPE_I2:
2729                         p->regs [greg ++] = *(gint16*)(arg);
2730                         break;
2731                 case MONO_TYPE_U2:
2732                 case MONO_TYPE_CHAR:
2733                         p->regs [greg ++] = *(guint16*)(arg);
2734                         break;
2735                 case MONO_TYPE_I4:
2736                         p->regs [greg ++] = *(gint32*)(arg);
2737                         break;
2738                 case MONO_TYPE_U4:
2739                         p->regs [greg ++] = *(guint32*)(arg);
2740                         break;
2741                 case MONO_TYPE_GENERICINST:
2742                     if (MONO_TYPE_IS_REFERENCE (t)) {
2743                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2744                                 break;
2745                         } else {
2746                                 /* Fall through */
2747                         }
2748                 case MONO_TYPE_VALUETYPE: {
2749                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2750
2751                         g_assert (ainfo->storage == ArgValuetypeInReg);
2752                         if (ainfo->pair_storage [0] != ArgNone) {
2753                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2754                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2755                         }
2756                         if (ainfo->pair_storage [1] != ArgNone) {
2757                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2758                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2759                         }
2760                         break;
2761                 }
2762                 default:
2763                         g_assert_not_reached ();
2764                 }
2765         }
2766
2767         g_assert (greg <= PARAM_REGS);
2768 }
2769
2770 /*
2771  * mono_arch_finish_dyn_call:
2772  *
2773  *   Store the result of a dyn call into the return value buffer passed to
2774  * start_dyn_call ().
2775  * This function should be as fast as possible, any work which does not depend
2776  * on the actual values of the arguments should be done in
2777  * mono_arch_dyn_call_prepare ().
2778  */
2779 void
2780 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2781 {
2782         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2783         MonoMethodSignature *sig = dinfo->sig;
2784         guint8 *ret = ((DynCallArgs*)buf)->ret;
2785         mgreg_t res = ((DynCallArgs*)buf)->res;
2786         MonoType *sig_ret = mono_type_get_underlying_type (sig->ret);
2787
2788         switch (sig_ret->type) {
2789         case MONO_TYPE_VOID:
2790                 *(gpointer*)ret = NULL;
2791                 break;
2792         case MONO_TYPE_STRING:
2793         case MONO_TYPE_CLASS:
2794         case MONO_TYPE_ARRAY:
2795         case MONO_TYPE_SZARRAY:
2796         case MONO_TYPE_OBJECT:
2797         case MONO_TYPE_I:
2798         case MONO_TYPE_U:
2799         case MONO_TYPE_PTR:
2800                 *(gpointer*)ret = GREG_TO_PTR(res);
2801                 break;
2802         case MONO_TYPE_I1:
2803                 *(gint8*)ret = res;
2804                 break;
2805         case MONO_TYPE_U1:
2806         case MONO_TYPE_BOOLEAN:
2807                 *(guint8*)ret = res;
2808                 break;
2809         case MONO_TYPE_I2:
2810                 *(gint16*)ret = res;
2811                 break;
2812         case MONO_TYPE_U2:
2813         case MONO_TYPE_CHAR:
2814                 *(guint16*)ret = res;
2815                 break;
2816         case MONO_TYPE_I4:
2817                 *(gint32*)ret = res;
2818                 break;
2819         case MONO_TYPE_U4:
2820                 *(guint32*)ret = res;
2821                 break;
2822         case MONO_TYPE_I8:
2823                 *(gint64*)ret = res;
2824                 break;
2825         case MONO_TYPE_U8:
2826                 *(guint64*)ret = res;
2827                 break;
2828         case MONO_TYPE_GENERICINST:
2829                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2830                         *(gpointer*)ret = GREG_TO_PTR(res);
2831                         break;
2832                 } else {
2833                         /* Fall through */
2834                 }
2835         case MONO_TYPE_VALUETYPE:
2836                 if (dinfo->cinfo->vtype_retaddr) {
2837                         /* Nothing to do */
2838                 } else {
2839                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2840
2841                         g_assert (ainfo->storage == ArgValuetypeInReg);
2842
2843                         if (ainfo->pair_storage [0] != ArgNone) {
2844                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2845                                 ((mgreg_t*)ret)[0] = res;
2846                         }
2847
2848                         g_assert (ainfo->pair_storage [1] == ArgNone);
2849                 }
2850                 break;
2851         default:
2852                 g_assert_not_reached ();
2853         }
2854 }
2855
2856 /* emit an exception if condition is fail */
2857 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2858         do {                                                        \
2859                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2860                 if (tins == NULL) {                                                                             \
2861                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2862                                         MONO_PATCH_INFO_EXC, exc_name);  \
2863                         x86_branch32 (code, cond, 0, signed);               \
2864                 } else {        \
2865                         EMIT_COND_BRANCH (tins, cond, signed);  \
2866                 }                       \
2867         } while (0);
2868
2869 #define EMIT_FPCOMPARE(code) do { \
2870         amd64_fcompp (code); \
2871         amd64_fnstsw (code); \
2872 } while (0);
2873
2874 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2875     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2876         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2877         amd64_ ##op (code); \
2878         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2879         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2880 } while (0);
2881
2882 static guint8*
2883 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2884 {
2885         gboolean no_patch = FALSE;
2886
2887         /*
2888          * FIXME: Add support for thunks
2889          */
2890         {
2891                 gboolean near_call = FALSE;
2892
2893                 /*
2894                  * Indirect calls are expensive so try to make a near call if possible.
2895                  * The caller memory is allocated by the code manager so it is
2896                  * guaranteed to be at a 32 bit offset.
2897                  */
2898
2899                 if (patch_type != MONO_PATCH_INFO_ABS) {
2900                         /* The target is in memory allocated using the code manager */
2901                         near_call = TRUE;
2902
2903                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2904                                 if (((MonoMethod*)data)->klass->image->aot_module)
2905                                         /* The callee might be an AOT method */
2906                                         near_call = FALSE;
2907                                 if (((MonoMethod*)data)->dynamic)
2908                                         /* The target is in malloc-ed memory */
2909                                         near_call = FALSE;
2910                         }
2911
2912                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2913                                 /*
2914                                  * The call might go directly to a native function without
2915                                  * the wrapper.
2916                                  */
2917                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2918                                 if (mi) {
2919                                         gconstpointer target = mono_icall_get_wrapper (mi);
2920                                         if ((((guint64)target) >> 32) != 0)
2921                                                 near_call = FALSE;
2922                                 }
2923                         }
2924                 }
2925                 else {
2926                         MonoJumpInfo *jinfo = NULL;
2927
2928                         if (cfg->abs_patches)
2929                                 jinfo = g_hash_table_lookup (cfg->abs_patches, data);
2930                         if (jinfo) {
2931                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2932                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2933                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2934                                                 near_call = TRUE;
2935                                         no_patch = TRUE;
2936                                 } else {
2937                                         /*
2938                                          * This is not really an optimization, but required because the
2939                                          * generic class init trampolines use R11 to pass the vtable.
2940                                          */
2941                                         near_call = TRUE;
2942                                 }
2943                         } else {
2944                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2945                                 if (info) {
2946                                         if (info->func == info->wrapper) {
2947                                                 /* No wrapper */
2948                                                 if ((((guint64)info->func) >> 32) == 0)
2949                                                         near_call = TRUE;
2950                                         }
2951                                         else {
2952                                                 /* See the comment in mono_codegen () */
2953                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2954                                                         near_call = TRUE;
2955                                         }
2956                                 }
2957                                 else if ((((guint64)data) >> 32) == 0) {
2958                                         near_call = TRUE;
2959                                         no_patch = TRUE;
2960                                 }
2961                         }
2962                 }
2963
2964                 if (cfg->method->dynamic)
2965                         /* These methods are allocated using malloc */
2966                         near_call = FALSE;
2967
2968 #ifdef MONO_ARCH_NOMAP32BIT
2969                 near_call = FALSE;
2970 #endif
2971 #if defined(__native_client__)
2972                 /* Always use near_call == TRUE for Native Client */
2973                 near_call = TRUE;
2974 #endif
2975                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2976                 if (optimize_for_xen)
2977                         near_call = FALSE;
2978
2979                 if (cfg->compile_aot) {
2980                         near_call = TRUE;
2981                         no_patch = TRUE;
2982                 }
2983
2984                 if (near_call) {
2985                         /*
2986                          * Align the call displacement to an address divisible by 4 so it does
2987                          * not span cache lines. This is required for code patching to work on SMP
2988                          * systems.
2989                          */
2990                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2991                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2992                                 amd64_padding (code, pad_size);
2993                         }
2994                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2995                         amd64_call_code (code, 0);
2996                 }
2997                 else {
2998                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2999                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3000                         amd64_call_reg (code, GP_SCRATCH_REG);
3001                 }
3002         }
3003
3004         return code;
3005 }
3006
3007 static inline guint8*
3008 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
3009 {
3010 #ifdef HOST_WIN32
3011         if (win64_adjust_stack)
3012                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3013 #endif
3014         code = emit_call_body (cfg, code, patch_type, data);
3015 #ifdef HOST_WIN32
3016         if (win64_adjust_stack)
3017                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3018 #endif
3019
3020         return code;
3021 }
3022
3023 static inline int
3024 store_membase_imm_to_store_membase_reg (int opcode)
3025 {
3026         switch (opcode) {
3027         case OP_STORE_MEMBASE_IMM:
3028                 return OP_STORE_MEMBASE_REG;
3029         case OP_STOREI4_MEMBASE_IMM:
3030                 return OP_STOREI4_MEMBASE_REG;
3031         case OP_STOREI8_MEMBASE_IMM:
3032                 return OP_STOREI8_MEMBASE_REG;
3033         }
3034
3035         return -1;
3036 }
3037
3038 #ifndef DISABLE_JIT
3039
3040 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3041
3042 /*
3043  * mono_arch_peephole_pass_1:
3044  *
3045  *   Perform peephole opts which should/can be performed before local regalloc
3046  */
3047 void
3048 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3049 {
3050         MonoInst *ins, *n;
3051
3052         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3053                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3054
3055                 switch (ins->opcode) {
3056                 case OP_ADD_IMM:
3057                 case OP_IADD_IMM:
3058                 case OP_LADD_IMM:
3059                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3060                                 /*
3061                                  * X86_LEA is like ADD, but doesn't have the
3062                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3063                                  * its operand to 64 bit.
3064                                  */
3065                                 ins->opcode = OP_X86_LEA_MEMBASE;
3066                                 ins->inst_basereg = ins->sreg1;
3067                         }
3068                         break;
3069                 case OP_LXOR:
3070                 case OP_IXOR:
3071                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3072                                 MonoInst *ins2;
3073
3074                                 /*
3075                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3076                                  * the latter has length 2-3 instead of 6 (reverse constant
3077                                  * propagation). These instruction sequences are very common
3078                                  * in the initlocals bblock.
3079                                  */
3080                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3081                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3082                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3083                                                 ins2->sreg1 = ins->dreg;
3084                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3085                                                 /* Continue */
3086                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3087                                                 NULLIFY_INS (ins2);
3088                                                 /* Continue */
3089                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3090                                                 /* Continue */
3091                                         } else {
3092                                                 break;
3093                                         }
3094                                 }
3095                         }
3096                         break;
3097                 case OP_COMPARE_IMM:
3098                 case OP_LCOMPARE_IMM:
3099                         /* OP_COMPARE_IMM (reg, 0)
3100                          * -->
3101                          * OP_AMD64_TEST_NULL (reg)
3102                          */
3103                         if (!ins->inst_imm)
3104                                 ins->opcode = OP_AMD64_TEST_NULL;
3105                         break;
3106                 case OP_ICOMPARE_IMM:
3107                         if (!ins->inst_imm)
3108                                 ins->opcode = OP_X86_TEST_NULL;
3109                         break;
3110                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3111                         /*
3112                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3113                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3114                          * -->
3115                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3116                          * OP_COMPARE_IMM reg, imm
3117                          *
3118                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3119                          */
3120                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3121                             ins->inst_basereg == last_ins->inst_destbasereg &&
3122                             ins->inst_offset == last_ins->inst_offset) {
3123                                         ins->opcode = OP_ICOMPARE_IMM;
3124                                         ins->sreg1 = last_ins->sreg1;
3125
3126                                         /* check if we can remove cmp reg,0 with test null */
3127                                         if (!ins->inst_imm)
3128                                                 ins->opcode = OP_X86_TEST_NULL;
3129                                 }
3130
3131                         break;
3132                 }
3133
3134                 mono_peephole_ins (bb, ins);
3135         }
3136 }
3137
3138 void
3139 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3140 {
3141         MonoInst *ins, *n;
3142
3143         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3144                 switch (ins->opcode) {
3145                 case OP_ICONST:
3146                 case OP_I8CONST: {
3147                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3148                         /* reg = 0 -> XOR (reg, reg) */
3149                         /* XOR sets cflags on x86, so we cant do it always */
3150                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3151                                 ins->opcode = OP_LXOR;
3152                                 ins->sreg1 = ins->dreg;
3153                                 ins->sreg2 = ins->dreg;
3154                                 /* Fall through */
3155                         } else {
3156                                 break;
3157                         }
3158                 }
3159                 case OP_LXOR:
3160                         /*
3161                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3162                          * 0 result into 64 bits.
3163                          */
3164                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3165                                 ins->opcode = OP_IXOR;
3166                         }
3167                         /* Fall through */
3168                 case OP_IXOR:
3169                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3170                                 MonoInst *ins2;
3171
3172                                 /*
3173                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3174                                  * the latter has length 2-3 instead of 6 (reverse constant
3175                                  * propagation). These instruction sequences are very common
3176                                  * in the initlocals bblock.
3177                                  */
3178                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3179                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3180                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3181                                                 ins2->sreg1 = ins->dreg;
3182                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3183                                                 /* Continue */
3184                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3185                                                 NULLIFY_INS (ins2);
3186                                                 /* Continue */
3187                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3188                                                 /* Continue */
3189                                         } else {
3190                                                 break;
3191                                         }
3192                                 }
3193                         }
3194                         break;
3195                 case OP_IADD_IMM:
3196                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3197                                 ins->opcode = OP_X86_INC_REG;
3198                         break;
3199                 case OP_ISUB_IMM:
3200                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3201                                 ins->opcode = OP_X86_DEC_REG;
3202                         break;
3203                 }
3204
3205                 mono_peephole_ins (bb, ins);
3206         }
3207 }
3208
3209 #define NEW_INS(cfg,ins,dest,op) do {   \
3210                 MONO_INST_NEW ((cfg), (dest), (op)); \
3211         (dest)->cil_code = (ins)->cil_code; \
3212         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3213         } while (0)
3214
3215 /*
3216  * mono_arch_lowering_pass:
3217  *
3218  *  Converts complex opcodes into simpler ones so that each IR instruction
3219  * corresponds to one machine instruction.
3220  */
3221 void
3222 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3223 {
3224         MonoInst *ins, *n, *temp;
3225
3226         /*
3227          * FIXME: Need to add more instructions, but the current machine
3228          * description can't model some parts of the composite instructions like
3229          * cdq.
3230          */
3231         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3232                 switch (ins->opcode) {
3233                 case OP_DIV_IMM:
3234                 case OP_REM_IMM:
3235                 case OP_IDIV_IMM:
3236                 case OP_IDIV_UN_IMM:
3237                 case OP_IREM_UN_IMM:
3238                 case OP_LREM_IMM:
3239                 case OP_IREM_IMM:
3240                         mono_decompose_op_imm (cfg, bb, ins);
3241                         break;
3242                 case OP_COMPARE_IMM:
3243                 case OP_LCOMPARE_IMM:
3244                         if (!amd64_is_imm32 (ins->inst_imm)) {
3245                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3246                                 temp->inst_c0 = ins->inst_imm;
3247                                 temp->dreg = mono_alloc_ireg (cfg);
3248                                 ins->opcode = OP_COMPARE;
3249                                 ins->sreg2 = temp->dreg;
3250                         }
3251                         break;
3252 #ifndef __mono_ilp32__
3253                 case OP_LOAD_MEMBASE:
3254 #endif
3255                 case OP_LOADI8_MEMBASE:
3256 #ifndef __native_client_codegen__
3257                 /*  Don't generate memindex opcodes (to simplify */
3258                 /*  read sandboxing) */
3259                         if (!amd64_is_imm32 (ins->inst_offset)) {
3260                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3261                                 temp->inst_c0 = ins->inst_offset;
3262                                 temp->dreg = mono_alloc_ireg (cfg);
3263                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3264                                 ins->inst_indexreg = temp->dreg;
3265                         }
3266 #endif
3267                         break;
3268 #ifndef __mono_ilp32__
3269                 case OP_STORE_MEMBASE_IMM:
3270 #endif
3271                 case OP_STOREI8_MEMBASE_IMM:
3272                         if (!amd64_is_imm32 (ins->inst_imm)) {
3273                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3274                                 temp->inst_c0 = ins->inst_imm;
3275                                 temp->dreg = mono_alloc_ireg (cfg);
3276                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3277                                 ins->sreg1 = temp->dreg;
3278                         }
3279                         break;
3280 #ifdef MONO_ARCH_SIMD_INTRINSICS
3281                 case OP_EXPAND_I1: {
3282                                 int temp_reg1 = mono_alloc_ireg (cfg);
3283                                 int temp_reg2 = mono_alloc_ireg (cfg);
3284                                 int original_reg = ins->sreg1;
3285
3286                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3287                                 temp->sreg1 = original_reg;
3288                                 temp->dreg = temp_reg1;
3289
3290                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3291                                 temp->sreg1 = temp_reg1;
3292                                 temp->dreg = temp_reg2;
3293                                 temp->inst_imm = 8;
3294
3295                                 NEW_INS (cfg, ins, temp, OP_LOR);
3296                                 temp->sreg1 = temp->dreg = temp_reg2;
3297                                 temp->sreg2 = temp_reg1;
3298
3299                                 ins->opcode = OP_EXPAND_I2;
3300                                 ins->sreg1 = temp_reg2;
3301                         }
3302                         break;
3303 #endif
3304                 default:
3305                         break;
3306                 }
3307         }
3308
3309         bb->max_vreg = cfg->next_vreg;
3310 }
3311
3312 static const int
3313 branch_cc_table [] = {
3314         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3315         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3316         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3317 };
3318
3319 /* Maps CMP_... constants to X86_CC_... constants */
3320 static const int
3321 cc_table [] = {
3322         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3323         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3324 };
3325
3326 static const int
3327 cc_signed_table [] = {
3328         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3329         FALSE, FALSE, FALSE, FALSE
3330 };
3331
3332 /*#include "cprop.c"*/
3333
3334 static unsigned char*
3335 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3336 {
3337         if (size == 8)
3338                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3339         else
3340                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3341
3342         if (size == 1)
3343                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3344         else if (size == 2)
3345                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3346         return code;
3347 }
3348
3349 static unsigned char*
3350 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3351 {
3352         int sreg = tree->sreg1;
3353         int need_touch = FALSE;
3354
3355 #if defined(HOST_WIN32)
3356         need_touch = TRUE;
3357 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3358         if (!tree->flags & MONO_INST_INIT)
3359                 need_touch = TRUE;
3360 #endif
3361
3362         if (need_touch) {
3363                 guint8* br[5];
3364
3365                 /*
3366                  * Under Windows:
3367                  * If requested stack size is larger than one page,
3368                  * perform stack-touch operation
3369                  */
3370                 /*
3371                  * Generate stack probe code.
3372                  * Under Windows, it is necessary to allocate one page at a time,
3373                  * "touching" stack after each successful sub-allocation. This is
3374                  * because of the way stack growth is implemented - there is a
3375                  * guard page before the lowest stack page that is currently commited.
3376                  * Stack normally grows sequentially so OS traps access to the
3377                  * guard page and commits more pages when needed.
3378                  */
3379                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3380                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3381
3382                 br[2] = code; /* loop */
3383                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3384                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3385                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3386                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3387                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3388                 amd64_patch (br[3], br[2]);
3389                 amd64_test_reg_reg (code, sreg, sreg);
3390                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3391                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3392
3393                 br[1] = code; x86_jump8 (code, 0);
3394
3395                 amd64_patch (br[0], code);
3396                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3397                 amd64_patch (br[1], code);
3398                 amd64_patch (br[4], code);
3399         }
3400         else
3401                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3402
3403         if (tree->flags & MONO_INST_INIT) {
3404                 int offset = 0;
3405                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3406                         amd64_push_reg (code, AMD64_RAX);
3407                         offset += 8;
3408                 }
3409                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3410                         amd64_push_reg (code, AMD64_RCX);
3411                         offset += 8;
3412                 }
3413                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3414                         amd64_push_reg (code, AMD64_RDI);
3415                         offset += 8;
3416                 }
3417
3418                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3419                 if (sreg != AMD64_RCX)
3420                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3421                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3422
3423                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3424                 if (cfg->param_area)
3425                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3426                 amd64_cld (code);
3427 #if defined(__default_codegen__)
3428                 amd64_prefix (code, X86_REP_PREFIX);
3429                 amd64_stosl (code);
3430 #elif defined(__native_client_codegen__)
3431                 /* NaCl stos pseudo-instruction */
3432                 amd64_codegen_pre(code);
3433                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3434                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3435                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3436                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3437                 amd64_prefix (code, X86_REP_PREFIX);
3438                 amd64_stosl (code);
3439                 amd64_codegen_post(code);
3440 #endif /* __native_client_codegen__ */
3441
3442                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3443                         amd64_pop_reg (code, AMD64_RDI);
3444                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3445                         amd64_pop_reg (code, AMD64_RCX);
3446                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3447                         amd64_pop_reg (code, AMD64_RAX);
3448         }
3449         return code;
3450 }
3451
3452 static guint8*
3453 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3454 {
3455         CallInfo *cinfo;
3456         guint32 quad;
3457
3458         /* Move return value to the target register */
3459         /* FIXME: do this in the local reg allocator */
3460         switch (ins->opcode) {
3461         case OP_CALL:
3462         case OP_CALL_REG:
3463         case OP_CALL_MEMBASE:
3464         case OP_LCALL:
3465         case OP_LCALL_REG:
3466         case OP_LCALL_MEMBASE:
3467                 g_assert (ins->dreg == AMD64_RAX);
3468                 break;
3469         case OP_FCALL:
3470         case OP_FCALL_REG:
3471         case OP_FCALL_MEMBASE: {
3472                 MonoType *rtype = mini_get_underlying_type (cfg, ((MonoCallInst*)ins)->signature->ret);
3473                 if (rtype->type == MONO_TYPE_R4) {
3474                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3475                 }
3476                 else {
3477                         if (ins->dreg != AMD64_XMM0)
3478                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3479                 }
3480                 break;
3481         }
3482         case OP_RCALL:
3483         case OP_RCALL_REG:
3484         case OP_RCALL_MEMBASE:
3485                 if (ins->dreg != AMD64_XMM0)
3486                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3487                 break;
3488         case OP_VCALL:
3489         case OP_VCALL_REG:
3490         case OP_VCALL_MEMBASE:
3491         case OP_VCALL2:
3492         case OP_VCALL2_REG:
3493         case OP_VCALL2_MEMBASE:
3494                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature);
3495                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3496                         MonoInst *loc = cfg->arch.vret_addr_loc;
3497
3498                         /* Load the destination address */
3499                         g_assert (loc->opcode == OP_REGOFFSET);
3500                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3501
3502                         for (quad = 0; quad < 2; quad ++) {
3503                                 switch (cinfo->ret.pair_storage [quad]) {
3504                                 case ArgInIReg:
3505                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3506                                         break;
3507                                 case ArgInFloatSSEReg:
3508                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3509                                         break;
3510                                 case ArgInDoubleSSEReg:
3511                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3512                                         break;
3513                                 case ArgNone:
3514                                         break;
3515                                 default:
3516                                         NOT_IMPLEMENTED;
3517                                 }
3518                         }
3519                 }
3520                 break;
3521         }
3522
3523         return code;
3524 }
3525
3526 #endif /* DISABLE_JIT */
3527
3528 #ifdef __APPLE__
3529 static int tls_gs_offset;
3530 #endif
3531
3532 gboolean
3533 mono_amd64_have_tls_get (void)
3534 {
3535 #ifdef TARGET_MACH
3536         static gboolean have_tls_get = FALSE;
3537         static gboolean inited = FALSE;
3538         guint8 *ins;
3539
3540         if (inited)
3541                 return have_tls_get;
3542
3543         ins = (guint8*)pthread_getspecific;
3544
3545         /*
3546          * We're looking for these two instructions:
3547          *
3548          * mov    %gs:[offset](,%rdi,8),%rax
3549          * retq
3550          */
3551         have_tls_get = ins [0] == 0x65 &&
3552                        ins [1] == 0x48 &&
3553                        ins [2] == 0x8b &&
3554                        ins [3] == 0x04 &&
3555                        ins [4] == 0xfd &&
3556                        ins [6] == 0x00 &&
3557                        ins [7] == 0x00 &&
3558                        ins [8] == 0x00 &&
3559                        ins [9] == 0xc3;
3560
3561         inited = TRUE;
3562
3563         tls_gs_offset = ins[5];
3564
3565         return have_tls_get;
3566 #elif defined(TARGET_ANDROID)
3567         return FALSE;
3568 #else
3569         return TRUE;
3570 #endif
3571 }
3572
3573 int
3574 mono_amd64_get_tls_gs_offset (void)
3575 {
3576 #ifdef TARGET_OSX
3577         return tls_gs_offset;
3578 #else
3579         g_assert_not_reached ();
3580         return -1;
3581 #endif
3582 }
3583
3584 /*
3585  * mono_amd64_emit_tls_get:
3586  * @code: buffer to store code to
3587  * @dreg: hard register where to place the result
3588  * @tls_offset: offset info
3589  *
3590  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3591  * the dreg register the item in the thread local storage identified
3592  * by tls_offset.
3593  *
3594  * Returns: a pointer to the end of the stored code
3595  */
3596 guint8*
3597 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3598 {
3599 #ifdef HOST_WIN32
3600         if (tls_offset < 64) {
3601                 x86_prefix (code, X86_GS_PREFIX);
3602                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3603         } else {
3604                 guint8 *buf [16];
3605
3606                 g_assert (tls_offset < 0x440);
3607                 /* Load TEB->TlsExpansionSlots */
3608                 x86_prefix (code, X86_GS_PREFIX);
3609                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3610                 amd64_test_reg_reg (code, dreg, dreg);
3611                 buf [0] = code;
3612                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3613                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3614                 amd64_patch (buf [0], code);
3615         }
3616 #elif defined(__APPLE__)
3617         x86_prefix (code, X86_GS_PREFIX);
3618         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3619 #else
3620         if (optimize_for_xen) {
3621                 x86_prefix (code, X86_FS_PREFIX);
3622                 amd64_mov_reg_mem (code, dreg, 0, 8);
3623                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3624         } else {
3625                 x86_prefix (code, X86_FS_PREFIX);
3626                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3627         }
3628 #endif
3629         return code;
3630 }
3631
3632 static guint8*
3633 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3634 {
3635         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3636 #ifdef TARGET_OSX
3637         if (dreg != offset_reg)
3638                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3639         amd64_prefix (code, X86_GS_PREFIX);
3640         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3641 #elif defined(__linux__)
3642         int tmpreg = -1;
3643
3644         if (dreg == offset_reg) {
3645                 /* Use a temporary reg by saving it to the redzone */
3646                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3647                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3648                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3649                 offset_reg = tmpreg;
3650         }
3651         x86_prefix (code, X86_FS_PREFIX);
3652         amd64_mov_reg_mem (code, dreg, 0, 8);
3653         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3654         if (tmpreg != -1)
3655                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3656 #else
3657         g_assert_not_reached ();
3658 #endif
3659         return code;
3660 }
3661
3662 static guint8*
3663 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3664 {
3665 #ifdef HOST_WIN32
3666         g_assert_not_reached ();
3667 #elif defined(__APPLE__)
3668         x86_prefix (code, X86_GS_PREFIX);
3669         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3670 #else
3671         g_assert (!optimize_for_xen);
3672         x86_prefix (code, X86_FS_PREFIX);
3673         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3674 #endif
3675         return code;
3676 }
3677
3678 static guint8*
3679 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3680 {
3681         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3682 #ifdef HOST_WIN32
3683         g_assert_not_reached ();
3684 #elif defined(__APPLE__)
3685         x86_prefix (code, X86_GS_PREFIX);
3686         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3687 #else
3688         x86_prefix (code, X86_FS_PREFIX);
3689         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3690 #endif
3691         return code;
3692 }
3693
3694  /*
3695  * mono_arch_translate_tls_offset:
3696  *
3697  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3698  */
3699 int
3700 mono_arch_translate_tls_offset (int offset)
3701 {
3702 #ifdef __APPLE__
3703         return tls_gs_offset + (offset * 8);
3704 #else
3705         return offset;
3706 #endif
3707 }
3708
3709 /*
3710  * emit_setup_lmf:
3711  *
3712  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3713  */
3714 static guint8*
3715 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3716 {
3717         /*
3718          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3719          */
3720         /*
3721          * sp is saved right before calls but we need to save it here too so
3722          * async stack walks would work.
3723          */
3724         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3725         /* Save rbp */
3726         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3727         if (cfg->arch.omit_fp && cfa_offset != -1)
3728                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3729
3730         /* These can't contain refs */
3731         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3732         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3733         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3734         /* These are handled automatically by the stack marking code */
3735         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3736
3737         return code;
3738 }
3739
3740 #define REAL_PRINT_REG(text,reg) \
3741 mono_assert (reg >= 0); \
3742 amd64_push_reg (code, AMD64_RAX); \
3743 amd64_push_reg (code, AMD64_RDX); \
3744 amd64_push_reg (code, AMD64_RCX); \
3745 amd64_push_reg (code, reg); \
3746 amd64_push_imm (code, reg); \
3747 amd64_push_imm (code, text " %d %p\n"); \
3748 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3749 amd64_call_reg (code, AMD64_RAX); \
3750 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3751 amd64_pop_reg (code, AMD64_RCX); \
3752 amd64_pop_reg (code, AMD64_RDX); \
3753 amd64_pop_reg (code, AMD64_RAX);
3754
3755 /* benchmark and set based on cpu */
3756 #define LOOP_ALIGNMENT 8
3757 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3758
3759 #ifndef DISABLE_JIT
3760 void
3761 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3762 {
3763         MonoInst *ins;
3764         MonoCallInst *call;
3765         guint offset;
3766         guint8 *code = cfg->native_code + cfg->code_len;
3767         int max_len;
3768
3769         /* Fix max_offset estimate for each successor bb */
3770         if (cfg->opt & MONO_OPT_BRANCH) {
3771                 int current_offset = cfg->code_len;
3772                 MonoBasicBlock *current_bb;
3773                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3774                         current_bb->max_offset = current_offset;
3775                         current_offset += current_bb->max_length;
3776                 }
3777         }
3778
3779         if (cfg->opt & MONO_OPT_LOOP) {
3780                 int pad, align = LOOP_ALIGNMENT;
3781                 /* set alignment depending on cpu */
3782                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3783                         pad = align - pad;
3784                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3785                         amd64_padding (code, pad);
3786                         cfg->code_len += pad;
3787                         bb->native_offset = cfg->code_len;
3788                 }
3789         }
3790
3791 #if defined(__native_client_codegen__)
3792         /* For Native Client, all indirect call/jump targets must be */
3793         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3794         /* indirectly as well.                                       */
3795         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3796                                       (bb->flags & BB_EXCEPTION_HANDLER);
3797
3798         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3799                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3800                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3801                 cfg->code_len += pad;
3802                 bb->native_offset = cfg->code_len;
3803         }
3804 #endif  /*__native_client_codegen__*/
3805
3806         if (cfg->verbose_level > 2)
3807                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3808
3809         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3810                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3811                 g_assert (!cfg->compile_aot);
3812
3813                 cov->data [bb->dfn].cil_code = bb->cil_code;
3814                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3815                 /* this is not thread save, but good enough */
3816                 amd64_inc_membase (code, AMD64_R11, 0);
3817         }
3818
3819         offset = code - cfg->native_code;
3820
3821         mono_debug_open_block (cfg, bb, offset);
3822
3823     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3824                 x86_breakpoint (code);
3825
3826         MONO_BB_FOR_EACH_INS (bb, ins) {
3827                 offset = code - cfg->native_code;
3828
3829                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3830
3831 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3832
3833                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3834                         cfg->code_size *= 2;
3835                         cfg->native_code = mono_realloc_native_code(cfg);
3836                         code = cfg->native_code + offset;
3837                         cfg->stat_code_reallocs++;
3838                 }
3839
3840                 if (cfg->debug_info)
3841                         mono_debug_record_line_number (cfg, ins, offset);
3842
3843                 switch (ins->opcode) {
3844                 case OP_BIGMUL:
3845                         amd64_mul_reg (code, ins->sreg2, TRUE);
3846                         break;
3847                 case OP_BIGMUL_UN:
3848                         amd64_mul_reg (code, ins->sreg2, FALSE);
3849                         break;
3850                 case OP_X86_SETEQ_MEMBASE:
3851                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3852                         break;
3853                 case OP_STOREI1_MEMBASE_IMM:
3854                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3855                         break;
3856                 case OP_STOREI2_MEMBASE_IMM:
3857                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3858                         break;
3859                 case OP_STOREI4_MEMBASE_IMM:
3860                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3861                         break;
3862                 case OP_STOREI1_MEMBASE_REG:
3863                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3864                         break;
3865                 case OP_STOREI2_MEMBASE_REG:
3866                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3867                         break;
3868                 /* In AMD64 NaCl, pointers are 4 bytes, */
3869                 /*  so STORE_* != STOREI8_*. Likewise below. */
3870                 case OP_STORE_MEMBASE_REG:
3871                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3872                         break;
3873                 case OP_STOREI8_MEMBASE_REG:
3874                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3875                         break;
3876                 case OP_STOREI4_MEMBASE_REG:
3877                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3878                         break;
3879                 case OP_STORE_MEMBASE_IMM:
3880 #ifndef __native_client_codegen__
3881                         /* In NaCl, this could be a PCONST type, which could */
3882                         /* mean a pointer type was copied directly into the  */
3883                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3884                         /* the value would be 0x00000000FFFFFFFF which is    */
3885                         /* not proper for an imm32 unless you cast it.       */
3886                         g_assert (amd64_is_imm32 (ins->inst_imm));
3887 #endif
3888                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3889                         break;
3890                 case OP_STOREI8_MEMBASE_IMM:
3891                         g_assert (amd64_is_imm32 (ins->inst_imm));
3892                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3893                         break;
3894                 case OP_LOAD_MEM:
3895 #ifdef __mono_ilp32__
3896                         /* In ILP32, pointers are 4 bytes, so separate these */
3897                         /* cases, use literal 8 below where we really want 8 */
3898                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3899                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3900                         break;
3901 #endif
3902                 case OP_LOADI8_MEM:
3903                         // FIXME: Decompose this earlier
3904                         if (amd64_is_imm32 (ins->inst_imm))
3905                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3906                         else {
3907                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3908                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3909                         }
3910                         break;
3911                 case OP_LOADI4_MEM:
3912                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3913                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3914                         break;
3915                 case OP_LOADU4_MEM:
3916                         // FIXME: Decompose this earlier
3917                         if (amd64_is_imm32 (ins->inst_imm))
3918                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3919                         else {
3920                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3921                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3922                         }
3923                         break;
3924                 case OP_LOADU1_MEM:
3925                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3926                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3927                         break;
3928                 case OP_LOADU2_MEM:
3929                         /* For NaCl, pointers are 4 bytes, so separate these */
3930                         /* cases, use literal 8 below where we really want 8 */
3931                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3932                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3933                         break;
3934                 case OP_LOAD_MEMBASE:
3935                         g_assert (amd64_is_imm32 (ins->inst_offset));
3936                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3937                         break;
3938                 case OP_LOADI8_MEMBASE:
3939                         /* Use literal 8 instead of sizeof pointer or */
3940                         /* register, we really want 8 for this opcode */
3941                         g_assert (amd64_is_imm32 (ins->inst_offset));
3942                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3943                         break;
3944                 case OP_LOADI4_MEMBASE:
3945                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3946                         break;
3947                 case OP_LOADU4_MEMBASE:
3948                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3949                         break;
3950                 case OP_LOADU1_MEMBASE:
3951                         /* The cpu zero extends the result into 64 bits */
3952                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3953                         break;
3954                 case OP_LOADI1_MEMBASE:
3955                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3956                         break;
3957                 case OP_LOADU2_MEMBASE:
3958                         /* The cpu zero extends the result into 64 bits */
3959                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3960                         break;
3961                 case OP_LOADI2_MEMBASE:
3962                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3963                         break;
3964                 case OP_AMD64_LOADI8_MEMINDEX:
3965                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3966                         break;
3967                 case OP_LCONV_TO_I1:
3968                 case OP_ICONV_TO_I1:
3969                 case OP_SEXT_I1:
3970                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3971                         break;
3972                 case OP_LCONV_TO_I2:
3973                 case OP_ICONV_TO_I2:
3974                 case OP_SEXT_I2:
3975                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3976                         break;
3977                 case OP_LCONV_TO_U1:
3978                 case OP_ICONV_TO_U1:
3979                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3980                         break;
3981                 case OP_LCONV_TO_U2:
3982                 case OP_ICONV_TO_U2:
3983                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3984                         break;
3985                 case OP_ZEXT_I4:
3986                         /* Clean out the upper word */
3987                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3988                         break;
3989                 case OP_SEXT_I4:
3990                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3991                         break;
3992                 case OP_COMPARE:
3993                 case OP_LCOMPARE:
3994                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3995                         break;
3996                 case OP_COMPARE_IMM:
3997 #if defined(__mono_ilp32__)
3998                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3999                         g_assert (amd64_is_imm32 (ins->inst_imm));
4000                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4001                         break;
4002 #endif
4003                 case OP_LCOMPARE_IMM:
4004                         g_assert (amd64_is_imm32 (ins->inst_imm));
4005                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4006                         break;
4007                 case OP_X86_COMPARE_REG_MEMBASE:
4008                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4009                         break;
4010                 case OP_X86_TEST_NULL:
4011                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4012                         break;
4013                 case OP_AMD64_TEST_NULL:
4014                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4015                         break;
4016
4017                 case OP_X86_ADD_REG_MEMBASE:
4018                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4019                         break;
4020                 case OP_X86_SUB_REG_MEMBASE:
4021                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4022                         break;
4023                 case OP_X86_AND_REG_MEMBASE:
4024                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4025                         break;
4026                 case OP_X86_OR_REG_MEMBASE:
4027                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4028                         break;
4029                 case OP_X86_XOR_REG_MEMBASE:
4030                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4031                         break;
4032
4033                 case OP_X86_ADD_MEMBASE_IMM:
4034                         /* FIXME: Make a 64 version too */
4035                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4036                         break;
4037                 case OP_X86_SUB_MEMBASE_IMM:
4038                         g_assert (amd64_is_imm32 (ins->inst_imm));
4039                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4040                         break;
4041                 case OP_X86_AND_MEMBASE_IMM:
4042                         g_assert (amd64_is_imm32 (ins->inst_imm));
4043                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4044                         break;
4045                 case OP_X86_OR_MEMBASE_IMM:
4046                         g_assert (amd64_is_imm32 (ins->inst_imm));
4047                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4048                         break;
4049                 case OP_X86_XOR_MEMBASE_IMM:
4050                         g_assert (amd64_is_imm32 (ins->inst_imm));
4051                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4052                         break;
4053                 case OP_X86_ADD_MEMBASE_REG:
4054                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4055                         break;
4056                 case OP_X86_SUB_MEMBASE_REG:
4057                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4058                         break;
4059                 case OP_X86_AND_MEMBASE_REG:
4060                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4061                         break;
4062                 case OP_X86_OR_MEMBASE_REG:
4063                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4064                         break;
4065                 case OP_X86_XOR_MEMBASE_REG:
4066                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4067                         break;
4068                 case OP_X86_INC_MEMBASE:
4069                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4070                         break;
4071                 case OP_X86_INC_REG:
4072                         amd64_inc_reg_size (code, ins->dreg, 4);
4073                         break;
4074                 case OP_X86_DEC_MEMBASE:
4075                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4076                         break;
4077                 case OP_X86_DEC_REG:
4078                         amd64_dec_reg_size (code, ins->dreg, 4);
4079                         break;
4080                 case OP_X86_MUL_REG_MEMBASE:
4081                 case OP_X86_MUL_MEMBASE_REG:
4082                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4083                         break;
4084                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4085                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4086                         break;
4087                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4088                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4089                         break;
4090                 case OP_AMD64_COMPARE_MEMBASE_REG:
4091                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4092                         break;
4093                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4094                         g_assert (amd64_is_imm32 (ins->inst_imm));
4095                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4096                         break;
4097                 case OP_X86_COMPARE_MEMBASE8_IMM:
4098                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4099                         break;
4100                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4101                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4102                         break;
4103                 case OP_AMD64_COMPARE_REG_MEMBASE:
4104                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4105                         break;
4106
4107                 case OP_AMD64_ADD_REG_MEMBASE:
4108                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4109                         break;
4110                 case OP_AMD64_SUB_REG_MEMBASE:
4111                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4112                         break;
4113                 case OP_AMD64_AND_REG_MEMBASE:
4114                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4115                         break;
4116                 case OP_AMD64_OR_REG_MEMBASE:
4117                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4118                         break;
4119                 case OP_AMD64_XOR_REG_MEMBASE:
4120                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4121                         break;
4122
4123                 case OP_AMD64_ADD_MEMBASE_REG:
4124                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4125                         break;
4126                 case OP_AMD64_SUB_MEMBASE_REG:
4127                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4128                         break;
4129                 case OP_AMD64_AND_MEMBASE_REG:
4130                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4131                         break;
4132                 case OP_AMD64_OR_MEMBASE_REG:
4133                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4134                         break;
4135                 case OP_AMD64_XOR_MEMBASE_REG:
4136                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4137                         break;
4138
4139                 case OP_AMD64_ADD_MEMBASE_IMM:
4140                         g_assert (amd64_is_imm32 (ins->inst_imm));
4141                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4142                         break;
4143                 case OP_AMD64_SUB_MEMBASE_IMM:
4144                         g_assert (amd64_is_imm32 (ins->inst_imm));
4145                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4146                         break;
4147                 case OP_AMD64_AND_MEMBASE_IMM:
4148                         g_assert (amd64_is_imm32 (ins->inst_imm));
4149                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4150                         break;
4151                 case OP_AMD64_OR_MEMBASE_IMM:
4152                         g_assert (amd64_is_imm32 (ins->inst_imm));
4153                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4154                         break;
4155                 case OP_AMD64_XOR_MEMBASE_IMM:
4156                         g_assert (amd64_is_imm32 (ins->inst_imm));
4157                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4158                         break;
4159
4160                 case OP_BREAK:
4161                         amd64_breakpoint (code);
4162                         break;
4163                 case OP_RELAXED_NOP:
4164                         x86_prefix (code, X86_REP_PREFIX);
4165                         x86_nop (code);
4166                         break;
4167                 case OP_HARD_NOP:
4168                         x86_nop (code);
4169                         break;
4170                 case OP_NOP:
4171                 case OP_DUMMY_USE:
4172                 case OP_DUMMY_STORE:
4173                 case OP_DUMMY_ICONST:
4174                 case OP_DUMMY_R8CONST:
4175                 case OP_NOT_REACHED:
4176                 case OP_NOT_NULL:
4177                         break;
4178                 case OP_IL_SEQ_POINT:
4179                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4180                         break;
4181                 case OP_SEQ_POINT: {
4182                         int i;
4183
4184                         /*
4185                          * Read from the single stepping trigger page. This will cause a
4186                          * SIGSEGV when single stepping is enabled.
4187                          * We do this _before_ the breakpoint, so single stepping after
4188                          * a breakpoint is hit will step to the next IL offset.
4189                          */
4190                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4191                                 MonoInst *var = cfg->arch.ss_trigger_page_var;
4192
4193                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4194                                 amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
4195                         }
4196
4197                         /*
4198                          * This is the address which is saved in seq points,
4199                          */
4200                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4201
4202                         if (cfg->compile_aot) {
4203                                 guint32 offset = code - cfg->native_code;
4204                                 guint32 val;
4205                                 MonoInst *info_var = cfg->arch.seq_point_info_var;
4206
4207                                 /* Load info var */
4208                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4209                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4210                                 /* Load the info->bp_addrs [offset], which is either a valid address or the address of a trigger page */
4211                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4212                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4213                         } else {
4214                                 /*
4215                                  * A placeholder for a possible breakpoint inserted by
4216                                  * mono_arch_set_breakpoint ().
4217                                  */
4218                                 for (i = 0; i < breakpoint_size; ++i)
4219                                         x86_nop (code);
4220                         }
4221                         /*
4222                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4223                          * to another IL offset.
4224                          */
4225                         x86_nop (code);
4226                         break;
4227                 }
4228                 case OP_ADDCC:
4229                 case OP_LADDCC:
4230                 case OP_LADD:
4231                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4232                         break;
4233                 case OP_ADC:
4234                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4235                         break;
4236                 case OP_ADD_IMM:
4237                 case OP_LADD_IMM:
4238                         g_assert (amd64_is_imm32 (ins->inst_imm));
4239                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4240                         break;
4241                 case OP_ADC_IMM:
4242                         g_assert (amd64_is_imm32 (ins->inst_imm));
4243                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4244                         break;
4245                 case OP_SUBCC:
4246                 case OP_LSUBCC:
4247                 case OP_LSUB:
4248                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4249                         break;
4250                 case OP_SBB:
4251                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4252                         break;
4253                 case OP_SUB_IMM:
4254                 case OP_LSUB_IMM:
4255                         g_assert (amd64_is_imm32 (ins->inst_imm));
4256                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4257                         break;
4258                 case OP_SBB_IMM:
4259                         g_assert (amd64_is_imm32 (ins->inst_imm));
4260                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4261                         break;
4262                 case OP_LAND:
4263                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4264                         break;
4265                 case OP_AND_IMM:
4266                 case OP_LAND_IMM:
4267                         g_assert (amd64_is_imm32 (ins->inst_imm));
4268                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4269                         break;
4270                 case OP_LMUL:
4271                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4272                         break;
4273                 case OP_MUL_IMM:
4274                 case OP_LMUL_IMM:
4275                 case OP_IMUL_IMM: {
4276                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4277
4278                         switch (ins->inst_imm) {
4279                         case 2:
4280                                 /* MOV r1, r2 */
4281                                 /* ADD r1, r1 */
4282                                 if (ins->dreg != ins->sreg1)
4283                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4284                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4285                                 break;
4286                         case 3:
4287                                 /* LEA r1, [r2 + r2*2] */
4288                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4289                                 break;
4290                         case 5:
4291                                 /* LEA r1, [r2 + r2*4] */
4292                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4293                                 break;
4294                         case 6:
4295                                 /* LEA r1, [r2 + r2*2] */
4296                                 /* ADD r1, r1          */
4297                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4298                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4299                                 break;
4300                         case 9:
4301                                 /* LEA r1, [r2 + r2*8] */
4302                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4303                                 break;
4304                         case 10:
4305                                 /* LEA r1, [r2 + r2*4] */
4306                                 /* ADD r1, r1          */
4307                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4308                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4309                                 break;
4310                         case 12:
4311                                 /* LEA r1, [r2 + r2*2] */
4312                                 /* SHL r1, 2           */
4313                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4314                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4315                                 break;
4316                         case 25:
4317                                 /* LEA r1, [r2 + r2*4] */
4318                                 /* LEA r1, [r1 + r1*4] */
4319                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4320                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4321                                 break;
4322                         case 100:
4323                                 /* LEA r1, [r2 + r2*4] */
4324                                 /* SHL r1, 2           */
4325                                 /* LEA r1, [r1 + r1*4] */
4326                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4327                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4328                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4329                                 break;
4330                         default:
4331                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4332                                 break;
4333                         }
4334                         break;
4335                 }
4336                 case OP_LDIV:
4337                 case OP_LREM:
4338 #if defined( __native_client_codegen__ )
4339                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4340                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4341 #endif
4342                         /* Regalloc magic makes the div/rem cases the same */
4343                         if (ins->sreg2 == AMD64_RDX) {
4344                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4345                                 amd64_cdq (code);
4346                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4347                         } else {
4348                                 amd64_cdq (code);
4349                                 amd64_div_reg (code, ins->sreg2, TRUE);
4350                         }
4351                         break;
4352                 case OP_LDIV_UN:
4353                 case OP_LREM_UN:
4354 #if defined( __native_client_codegen__ )
4355                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4356                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4357 #endif
4358                         if (ins->sreg2 == AMD64_RDX) {
4359                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4360                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4361                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4362                         } else {
4363                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4364                                 amd64_div_reg (code, ins->sreg2, FALSE);
4365                         }
4366                         break;
4367                 case OP_IDIV:
4368                 case OP_IREM:
4369 #if defined( __native_client_codegen__ )
4370                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4371                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4372 #endif
4373                         if (ins->sreg2 == AMD64_RDX) {
4374                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4375                                 amd64_cdq_size (code, 4);
4376                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4377                         } else {
4378                                 amd64_cdq_size (code, 4);
4379                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4380                         }
4381                         break;
4382                 case OP_IDIV_UN:
4383                 case OP_IREM_UN:
4384 #if defined( __native_client_codegen__ )
4385                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4386                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4387 #endif
4388                         if (ins->sreg2 == AMD64_RDX) {
4389                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4390                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4391                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4392                         } else {
4393                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4394                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4395                         }
4396                         break;
4397                 case OP_LMUL_OVF:
4398                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4399                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4400                         break;
4401                 case OP_LOR:
4402                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4403                         break;
4404                 case OP_OR_IMM:
4405                 case OP_LOR_IMM:
4406                         g_assert (amd64_is_imm32 (ins->inst_imm));
4407                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4408                         break;
4409                 case OP_LXOR:
4410                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4411                         break;
4412                 case OP_XOR_IMM:
4413                 case OP_LXOR_IMM:
4414                         g_assert (amd64_is_imm32 (ins->inst_imm));
4415                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4416                         break;
4417                 case OP_LSHL:
4418                         g_assert (ins->sreg2 == AMD64_RCX);
4419                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4420                         break;
4421                 case OP_LSHR:
4422                         g_assert (ins->sreg2 == AMD64_RCX);
4423                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4424                         break;
4425                 case OP_SHR_IMM:
4426                         g_assert (amd64_is_imm32 (ins->inst_imm));
4427                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4428                         break;
4429                 case OP_LSHR_IMM:
4430                         g_assert (amd64_is_imm32 (ins->inst_imm));
4431                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4432                         break;
4433                 case OP_SHR_UN_IMM:
4434                         g_assert (amd64_is_imm32 (ins->inst_imm));
4435                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4436                         break;
4437                 case OP_LSHR_UN_IMM:
4438                         g_assert (amd64_is_imm32 (ins->inst_imm));
4439                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4440                         break;
4441                 case OP_LSHR_UN:
4442                         g_assert (ins->sreg2 == AMD64_RCX);
4443                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4444                         break;
4445                 case OP_SHL_IMM:
4446                         g_assert (amd64_is_imm32 (ins->inst_imm));
4447                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4448                         break;
4449                 case OP_LSHL_IMM:
4450                         g_assert (amd64_is_imm32 (ins->inst_imm));
4451                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4452                         break;
4453
4454                 case OP_IADDCC:
4455                 case OP_IADD:
4456                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4457                         break;
4458                 case OP_IADC:
4459                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4460                         break;
4461                 case OP_IADD_IMM:
4462                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4463                         break;
4464                 case OP_IADC_IMM:
4465                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4466                         break;
4467                 case OP_ISUBCC:
4468                 case OP_ISUB:
4469                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4470                         break;
4471                 case OP_ISBB:
4472                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4473                         break;
4474                 case OP_ISUB_IMM:
4475                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4476                         break;
4477                 case OP_ISBB_IMM:
4478                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4479                         break;
4480                 case OP_IAND:
4481                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4482                         break;
4483                 case OP_IAND_IMM:
4484                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4485                         break;
4486                 case OP_IOR:
4487                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4488                         break;
4489                 case OP_IOR_IMM:
4490                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4491                         break;
4492                 case OP_IXOR:
4493                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4494                         break;
4495                 case OP_IXOR_IMM:
4496                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4497                         break;
4498                 case OP_INEG:
4499                         amd64_neg_reg_size (code, ins->sreg1, 4);
4500                         break;
4501                 case OP_INOT:
4502                         amd64_not_reg_size (code, ins->sreg1, 4);
4503                         break;
4504                 case OP_ISHL:
4505                         g_assert (ins->sreg2 == AMD64_RCX);
4506                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4507                         break;
4508                 case OP_ISHR:
4509                         g_assert (ins->sreg2 == AMD64_RCX);
4510                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4511                         break;
4512                 case OP_ISHR_IMM:
4513                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4514                         break;
4515                 case OP_ISHR_UN_IMM:
4516                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4517                         break;
4518                 case OP_ISHR_UN:
4519                         g_assert (ins->sreg2 == AMD64_RCX);
4520                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4521                         break;
4522                 case OP_ISHL_IMM:
4523                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4524                         break;
4525                 case OP_IMUL:
4526                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4527                         break;
4528                 case OP_IMUL_OVF:
4529                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4530                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4531                         break;
4532                 case OP_IMUL_OVF_UN:
4533                 case OP_LMUL_OVF_UN: {
4534                         /* the mul operation and the exception check should most likely be split */
4535                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4536                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4537                         /*g_assert (ins->sreg2 == X86_EAX);
4538                         g_assert (ins->dreg == X86_EAX);*/
4539                         if (ins->sreg2 == X86_EAX) {
4540                                 non_eax_reg = ins->sreg1;
4541                         } else if (ins->sreg1 == X86_EAX) {
4542                                 non_eax_reg = ins->sreg2;
4543                         } else {
4544                                 /* no need to save since we're going to store to it anyway */
4545                                 if (ins->dreg != X86_EAX) {
4546                                         saved_eax = TRUE;
4547                                         amd64_push_reg (code, X86_EAX);
4548                                 }
4549                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4550                                 non_eax_reg = ins->sreg2;
4551                         }
4552                         if (ins->dreg == X86_EDX) {
4553                                 if (!saved_eax) {
4554                                         saved_eax = TRUE;
4555                                         amd64_push_reg (code, X86_EAX);
4556                                 }
4557                         } else {
4558                                 saved_edx = TRUE;
4559                                 amd64_push_reg (code, X86_EDX);
4560                         }
4561                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4562                         /* save before the check since pop and mov don't change the flags */
4563                         if (ins->dreg != X86_EAX)
4564                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4565                         if (saved_edx)
4566                                 amd64_pop_reg (code, X86_EDX);
4567                         if (saved_eax)
4568                                 amd64_pop_reg (code, X86_EAX);
4569                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4570                         break;
4571                 }
4572                 case OP_ICOMPARE:
4573                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4574                         break;
4575                 case OP_ICOMPARE_IMM:
4576                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4577                         break;
4578                 case OP_IBEQ:
4579                 case OP_IBLT:
4580                 case OP_IBGT:
4581                 case OP_IBGE:
4582                 case OP_IBLE:
4583                 case OP_LBEQ:
4584                 case OP_LBLT:
4585                 case OP_LBGT:
4586                 case OP_LBGE:
4587                 case OP_LBLE:
4588                 case OP_IBNE_UN:
4589                 case OP_IBLT_UN:
4590                 case OP_IBGT_UN:
4591                 case OP_IBGE_UN:
4592                 case OP_IBLE_UN:
4593                 case OP_LBNE_UN:
4594                 case OP_LBLT_UN:
4595                 case OP_LBGT_UN:
4596                 case OP_LBGE_UN:
4597                 case OP_LBLE_UN:
4598                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4599                         break;
4600
4601                 case OP_CMOV_IEQ:
4602                 case OP_CMOV_IGE:
4603                 case OP_CMOV_IGT:
4604                 case OP_CMOV_ILE:
4605                 case OP_CMOV_ILT:
4606                 case OP_CMOV_INE_UN:
4607                 case OP_CMOV_IGE_UN:
4608                 case OP_CMOV_IGT_UN:
4609                 case OP_CMOV_ILE_UN:
4610                 case OP_CMOV_ILT_UN:
4611                 case OP_CMOV_LEQ:
4612                 case OP_CMOV_LGE:
4613                 case OP_CMOV_LGT:
4614                 case OP_CMOV_LLE:
4615                 case OP_CMOV_LLT:
4616                 case OP_CMOV_LNE_UN:
4617                 case OP_CMOV_LGE_UN:
4618                 case OP_CMOV_LGT_UN:
4619                 case OP_CMOV_LLE_UN:
4620                 case OP_CMOV_LLT_UN:
4621                         g_assert (ins->dreg == ins->sreg1);
4622                         /* This needs to operate on 64 bit values */
4623                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4624                         break;
4625
4626                 case OP_LNOT:
4627                         amd64_not_reg (code, ins->sreg1);
4628                         break;
4629                 case OP_LNEG:
4630                         amd64_neg_reg (code, ins->sreg1);
4631                         break;
4632
4633                 case OP_ICONST:
4634                 case OP_I8CONST:
4635                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4636                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4637                         else
4638                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4639                         break;
4640                 case OP_AOTCONST:
4641                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4642                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4643                         break;
4644                 case OP_JUMP_TABLE:
4645                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4646                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4647                         break;
4648                 case OP_MOVE:
4649                         if (ins->dreg != ins->sreg1)
4650                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4651                         break;
4652                 case OP_AMD64_SET_XMMREG_R4: {
4653                         if (cfg->r4fp) {
4654                                 if (ins->dreg != ins->sreg1)
4655                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4656                         } else {
4657                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4658                         }
4659                         break;
4660                 }
4661                 case OP_AMD64_SET_XMMREG_R8: {
4662                         if (ins->dreg != ins->sreg1)
4663                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4664                         break;
4665                 }
4666                 case OP_TAILCALL: {
4667                         MonoCallInst *call = (MonoCallInst*)ins;
4668                         int i, save_area_offset;
4669
4670                         g_assert (!cfg->method->save_lmf);
4671
4672                         /* Restore callee saved registers */
4673                         save_area_offset = cfg->arch.reg_save_area_offset;
4674                         for (i = 0; i < AMD64_NREG; ++i)
4675                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4676                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4677                                         save_area_offset += 8;
4678                                 }
4679
4680                         if (cfg->arch.omit_fp) {
4681                                 if (cfg->arch.stack_alloc_size)
4682                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4683                                 // FIXME:
4684                                 if (call->stack_usage)
4685                                         NOT_IMPLEMENTED;
4686                         } else {
4687                                 /* Copy arguments on the stack to our argument area */
4688                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4689                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4690                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4691                                 }
4692
4693                                 amd64_leave (code);
4694                         }
4695
4696                         offset = code - cfg->native_code;
4697                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4698                         if (cfg->compile_aot)
4699                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4700                         else
4701                                 amd64_set_reg_template (code, AMD64_R11);
4702                         amd64_jump_reg (code, AMD64_R11);
4703                         ins->flags |= MONO_INST_GC_CALLSITE;
4704                         ins->backend.pc_offset = code - cfg->native_code;
4705                         break;
4706                 }
4707                 case OP_CHECK_THIS:
4708                         /* ensure ins->sreg1 is not NULL */
4709                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4710                         break;
4711                 case OP_ARGLIST: {
4712                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4713                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4714                         break;
4715                 }
4716                 case OP_CALL:
4717                 case OP_FCALL:
4718                 case OP_RCALL:
4719                 case OP_LCALL:
4720                 case OP_VCALL:
4721                 case OP_VCALL2:
4722                 case OP_VOIDCALL:
4723                         call = (MonoCallInst*)ins;
4724                         /*
4725                          * The AMD64 ABI forces callers to know about varargs.
4726                          */
4727                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4728                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4729                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4730                                 /*
4731                                  * Since the unmanaged calling convention doesn't contain a
4732                                  * 'vararg' entry, we have to treat every pinvoke call as a
4733                                  * potential vararg call.
4734                                  */
4735                                 guint32 nregs, i;
4736                                 nregs = 0;
4737                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4738                                         if (call->used_fregs & (1 << i))
4739                                                 nregs ++;
4740                                 if (!nregs)
4741                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4742                                 else
4743                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4744                         }
4745
4746                         if (ins->flags & MONO_INST_HAS_METHOD)
4747                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4748                         else
4749                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4750                         ins->flags |= MONO_INST_GC_CALLSITE;
4751                         ins->backend.pc_offset = code - cfg->native_code;
4752                         code = emit_move_return_value (cfg, ins, code);
4753                         break;
4754                 case OP_FCALL_REG:
4755                 case OP_RCALL_REG:
4756                 case OP_LCALL_REG:
4757                 case OP_VCALL_REG:
4758                 case OP_VCALL2_REG:
4759                 case OP_VOIDCALL_REG:
4760                 case OP_CALL_REG:
4761                         call = (MonoCallInst*)ins;
4762
4763                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4764                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4765                                 ins->sreg1 = AMD64_R11;
4766                         }
4767
4768                         /*
4769                          * The AMD64 ABI forces callers to know about varargs.
4770                          */
4771                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4772                                 if (ins->sreg1 == AMD64_RAX) {
4773                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4774                                         ins->sreg1 = AMD64_R11;
4775                                 }
4776                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4777                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4778                                 /*
4779                                  * Since the unmanaged calling convention doesn't contain a
4780                                  * 'vararg' entry, we have to treat every pinvoke call as a
4781                                  * potential vararg call.
4782                                  */
4783                                 guint32 nregs, i;
4784                                 nregs = 0;
4785                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4786                                         if (call->used_fregs & (1 << i))
4787                                                 nregs ++;
4788                                 if (ins->sreg1 == AMD64_RAX) {
4789                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4790                                         ins->sreg1 = AMD64_R11;
4791                                 }
4792                                 if (!nregs)
4793                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4794                                 else
4795                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4796                         }
4797
4798                         amd64_call_reg (code, ins->sreg1);
4799                         ins->flags |= MONO_INST_GC_CALLSITE;
4800                         ins->backend.pc_offset = code - cfg->native_code;
4801                         code = emit_move_return_value (cfg, ins, code);
4802                         break;
4803                 case OP_FCALL_MEMBASE:
4804                 case OP_RCALL_MEMBASE:
4805                 case OP_LCALL_MEMBASE:
4806                 case OP_VCALL_MEMBASE:
4807                 case OP_VCALL2_MEMBASE:
4808                 case OP_VOIDCALL_MEMBASE:
4809                 case OP_CALL_MEMBASE:
4810                         call = (MonoCallInst*)ins;
4811
4812                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4813                         ins->flags |= MONO_INST_GC_CALLSITE;
4814                         ins->backend.pc_offset = code - cfg->native_code;
4815                         code = emit_move_return_value (cfg, ins, code);
4816                         break;
4817                 case OP_DYN_CALL: {
4818                         int i;
4819                         MonoInst *var = cfg->dyn_call_var;
4820
4821                         g_assert (var->opcode == OP_REGOFFSET);
4822
4823                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4824                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4825                         /* r10 = ftn */
4826                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4827
4828                         /* Save args buffer */
4829                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4830
4831                         /* Set argument registers */
4832                         for (i = 0; i < PARAM_REGS; ++i)
4833                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4834
4835                         /* Make the call */
4836                         amd64_call_reg (code, AMD64_R10);
4837
4838                         ins->flags |= MONO_INST_GC_CALLSITE;
4839                         ins->backend.pc_offset = code - cfg->native_code;
4840
4841                         /* Save result */
4842                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4843                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4844                         break;
4845                 }
4846                 case OP_AMD64_SAVE_SP_TO_LMF: {
4847                         MonoInst *lmf_var = cfg->lmf_var;
4848                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4849                         break;
4850                 }
4851                 case OP_X86_PUSH:
4852                         g_assert_not_reached ();
4853                         amd64_push_reg (code, ins->sreg1);
4854                         break;
4855                 case OP_X86_PUSH_IMM:
4856                         g_assert_not_reached ();
4857                         g_assert (amd64_is_imm32 (ins->inst_imm));
4858                         amd64_push_imm (code, ins->inst_imm);
4859                         break;
4860                 case OP_X86_PUSH_MEMBASE:
4861                         g_assert_not_reached ();
4862                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4863                         break;
4864                 case OP_X86_PUSH_OBJ: {
4865                         int size = ALIGN_TO (ins->inst_imm, 8);
4866
4867                         g_assert_not_reached ();
4868
4869                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4870                         amd64_push_reg (code, AMD64_RDI);
4871                         amd64_push_reg (code, AMD64_RSI);
4872                         amd64_push_reg (code, AMD64_RCX);
4873                         if (ins->inst_offset)
4874                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4875                         else
4876                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4877                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4878                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4879                         amd64_cld (code);
4880                         amd64_prefix (code, X86_REP_PREFIX);
4881                         amd64_movsd (code);
4882                         amd64_pop_reg (code, AMD64_RCX);
4883                         amd64_pop_reg (code, AMD64_RSI);
4884                         amd64_pop_reg (code, AMD64_RDI);
4885                         break;
4886                 }
4887                 case OP_X86_LEA:
4888                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4889                         break;
4890                 case OP_X86_LEA_MEMBASE:
4891                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4892                         break;
4893                 case OP_X86_XCHG:
4894                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4895                         break;
4896                 case OP_LOCALLOC:
4897                         /* keep alignment */
4898                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4899                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4900                         code = mono_emit_stack_alloc (cfg, code, ins);
4901                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4902                         if (cfg->param_area)
4903                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4904                         break;
4905                 case OP_LOCALLOC_IMM: {
4906                         guint32 size = ins->inst_imm;
4907                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4908
4909                         if (ins->flags & MONO_INST_INIT) {
4910                                 if (size < 64) {
4911                                         int i;
4912
4913                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4914                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4915
4916                                         for (i = 0; i < size; i += 8)
4917                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4918                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4919                                 } else {
4920                                         amd64_mov_reg_imm (code, ins->dreg, size);
4921                                         ins->sreg1 = ins->dreg;
4922
4923                                         code = mono_emit_stack_alloc (cfg, code, ins);
4924                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4925                                 }
4926                         } else {
4927                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4928                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4929                         }
4930                         if (cfg->param_area)
4931                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4932                         break;
4933                 }
4934                 case OP_THROW: {
4935                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4936                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4937                                              (gpointer)"mono_arch_throw_exception", FALSE);
4938                         ins->flags |= MONO_INST_GC_CALLSITE;
4939                         ins->backend.pc_offset = code - cfg->native_code;
4940                         break;
4941                 }
4942                 case OP_RETHROW: {
4943                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4944                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4945                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4946                         ins->flags |= MONO_INST_GC_CALLSITE;
4947                         ins->backend.pc_offset = code - cfg->native_code;
4948                         break;
4949                 }
4950                 case OP_CALL_HANDLER:
4951                         /* Align stack */
4952                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4953                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4954                         amd64_call_imm (code, 0);
4955                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4956                         /* Restore stack alignment */
4957                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4958                         break;
4959                 case OP_START_HANDLER: {
4960                         /* Even though we're saving RSP, use sizeof */
4961                         /* gpointer because spvar is of type IntPtr */
4962                         /* see: mono_create_spvar_for_region */
4963                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4964                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4965
4966                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4967                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4968                                 cfg->param_area) {
4969                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4970                         }
4971                         break;
4972                 }
4973                 case OP_ENDFINALLY: {
4974                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4975                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4976                         amd64_ret (code);
4977                         break;
4978                 }
4979                 case OP_ENDFILTER: {
4980                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4981                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4982                         /* The local allocator will put the result into RAX */
4983                         amd64_ret (code);
4984                         break;
4985                 }
4986
4987                 case OP_LABEL:
4988                         ins->inst_c0 = code - cfg->native_code;
4989                         break;
4990                 case OP_BR:
4991                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4992                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4993                         //break;
4994                                 if (ins->inst_target_bb->native_offset) {
4995                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4996                                 } else {
4997                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4998                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4999                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5000                                                 x86_jump8 (code, 0);
5001                                         else
5002                                                 x86_jump32 (code, 0);
5003                         }
5004                         break;
5005                 case OP_BR_REG:
5006                         amd64_jump_reg (code, ins->sreg1);
5007                         break;
5008                 case OP_ICNEQ:
5009                 case OP_ICGE:
5010                 case OP_ICLE:
5011                 case OP_ICGE_UN:
5012                 case OP_ICLE_UN:
5013
5014                 case OP_CEQ:
5015                 case OP_LCEQ:
5016                 case OP_ICEQ:
5017                 case OP_CLT:
5018                 case OP_LCLT:
5019                 case OP_ICLT:
5020                 case OP_CGT:
5021                 case OP_ICGT:
5022                 case OP_LCGT:
5023                 case OP_CLT_UN:
5024                 case OP_LCLT_UN:
5025                 case OP_ICLT_UN:
5026                 case OP_CGT_UN:
5027                 case OP_LCGT_UN:
5028                 case OP_ICGT_UN:
5029                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5030                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5031                         break;
5032                 case OP_COND_EXC_EQ:
5033                 case OP_COND_EXC_NE_UN:
5034                 case OP_COND_EXC_LT:
5035                 case OP_COND_EXC_LT_UN:
5036                 case OP_COND_EXC_GT:
5037                 case OP_COND_EXC_GT_UN:
5038                 case OP_COND_EXC_GE:
5039                 case OP_COND_EXC_GE_UN:
5040                 case OP_COND_EXC_LE:
5041                 case OP_COND_EXC_LE_UN:
5042                 case OP_COND_EXC_IEQ:
5043                 case OP_COND_EXC_INE_UN:
5044                 case OP_COND_EXC_ILT:
5045                 case OP_COND_EXC_ILT_UN:
5046                 case OP_COND_EXC_IGT:
5047                 case OP_COND_EXC_IGT_UN:
5048                 case OP_COND_EXC_IGE:
5049                 case OP_COND_EXC_IGE_UN:
5050                 case OP_COND_EXC_ILE:
5051                 case OP_COND_EXC_ILE_UN:
5052                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
5053                         break;
5054                 case OP_COND_EXC_OV:
5055                 case OP_COND_EXC_NO:
5056                 case OP_COND_EXC_C:
5057                 case OP_COND_EXC_NC:
5058                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5059                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
5060                         break;
5061                 case OP_COND_EXC_IOV:
5062                 case OP_COND_EXC_INO:
5063                 case OP_COND_EXC_IC:
5064                 case OP_COND_EXC_INC:
5065                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5066                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
5067                         break;
5068
5069                 /* floating point opcodes */
5070                 case OP_R8CONST: {
5071                         double d = *(double *)ins->inst_p0;
5072
5073                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5074                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5075                         }
5076                         else {
5077                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5078                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5079                         }
5080                         break;
5081                 }
5082                 case OP_R4CONST: {
5083                         float f = *(float *)ins->inst_p0;
5084
5085                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5086                                 if (cfg->r4fp)
5087                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5088                                 else
5089                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5090                         }
5091                         else {
5092                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5093                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5094                                 if (!cfg->r4fp)
5095                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5096                         }
5097                         break;
5098                 }
5099                 case OP_STORER8_MEMBASE_REG:
5100                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5101                         break;
5102                 case OP_LOADR8_MEMBASE:
5103                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5104                         break;
5105                 case OP_STORER4_MEMBASE_REG:
5106                         if (cfg->r4fp) {
5107                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5108                         } else {
5109                                 /* This requires a double->single conversion */
5110                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5111                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5112                         }
5113                         break;
5114                 case OP_LOADR4_MEMBASE:
5115                         if (cfg->r4fp) {
5116                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5117                         } else {
5118                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5119                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5120                         }
5121                         break;
5122                 case OP_ICONV_TO_R4:
5123                         if (cfg->r4fp) {
5124                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5125                         } else {
5126                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5127                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5128                         }
5129                         break;
5130                 case OP_ICONV_TO_R8:
5131                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5132                         break;
5133                 case OP_LCONV_TO_R4:
5134                         if (cfg->r4fp) {
5135                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5136                         } else {
5137                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5138                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5139                         }
5140                         break;
5141                 case OP_LCONV_TO_R8:
5142                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5143                         break;
5144                 case OP_FCONV_TO_R4:
5145                         if (cfg->r4fp) {
5146                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5147                         } else {
5148                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5149                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5150                         }
5151                         break;
5152                 case OP_FCONV_TO_I1:
5153                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5154                         break;
5155                 case OP_FCONV_TO_U1:
5156                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5157                         break;
5158                 case OP_FCONV_TO_I2:
5159                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5160                         break;
5161                 case OP_FCONV_TO_U2:
5162                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5163                         break;
5164                 case OP_FCONV_TO_U4:
5165                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5166                         break;
5167                 case OP_FCONV_TO_I4:
5168                 case OP_FCONV_TO_I:
5169                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5170                         break;
5171                 case OP_FCONV_TO_I8:
5172                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5173                         break;
5174
5175                 case OP_RCONV_TO_I1:
5176                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5177                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5178                         break;
5179                 case OP_RCONV_TO_U1:
5180                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5181                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5182                         break;
5183                 case OP_RCONV_TO_I2:
5184                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5185                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5186                         break;
5187                 case OP_RCONV_TO_U2:
5188                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5189                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5190                         break;
5191                 case OP_RCONV_TO_I4:
5192                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5193                         break;
5194                 case OP_RCONV_TO_U4:
5195                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5196                         break;
5197                 case OP_RCONV_TO_I8:
5198                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5199                         break;
5200                 case OP_RCONV_TO_R8:
5201                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5202                         break;
5203                 case OP_RCONV_TO_R4:
5204                         if (ins->dreg != ins->sreg1)
5205                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5206                         break;
5207
5208                 case OP_LCONV_TO_R_UN: {
5209                         guint8 *br [2];
5210
5211                         /* Based on gcc code */
5212                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5213                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5214
5215                         /* Positive case */
5216                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5217                         br [1] = code; x86_jump8 (code, 0);
5218                         amd64_patch (br [0], code);
5219
5220                         /* Negative case */
5221                         /* Save to the red zone */
5222                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5223                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5224                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5225                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5226                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5227                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5228                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5229                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5230                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5231                         /* Restore */
5232                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5233                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5234                         amd64_patch (br [1], code);
5235                         break;
5236                 }
5237                 case OP_LCONV_TO_OVF_U4:
5238                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5239                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5240                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5241                         break;
5242                 case OP_LCONV_TO_OVF_I4_UN:
5243                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5244                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5245                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5246                         break;
5247                 case OP_FMOVE:
5248                         if (ins->dreg != ins->sreg1)
5249                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5250                         break;
5251                 case OP_RMOVE:
5252                         if (ins->dreg != ins->sreg1)
5253                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5254                         break;
5255                 case OP_MOVE_F_TO_I4:
5256                         if (cfg->r4fp) {
5257                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5258                         } else {
5259                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5260                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5261                         }
5262                         break;
5263                 case OP_MOVE_I4_TO_F:
5264                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5265                         if (!cfg->r4fp)
5266                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5267                         break;
5268                 case OP_MOVE_F_TO_I8:
5269                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5270                         break;
5271                 case OP_MOVE_I8_TO_F:
5272                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5273                         break;
5274                 case OP_FADD:
5275                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5276                         break;
5277                 case OP_FSUB:
5278                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5279                         break;
5280                 case OP_FMUL:
5281                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5282                         break;
5283                 case OP_FDIV:
5284                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5285                         break;
5286                 case OP_FNEG: {
5287                         static double r8_0 = -0.0;
5288
5289                         g_assert (ins->sreg1 == ins->dreg);
5290
5291                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5292                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5293                         break;
5294                 }
5295                 case OP_SIN:
5296                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5297                         break;
5298                 case OP_COS:
5299                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5300                         break;
5301                 case OP_ABS: {
5302                         static guint64 d = 0x7fffffffffffffffUL;
5303
5304                         g_assert (ins->sreg1 == ins->dreg);
5305
5306                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5307                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5308                         break;
5309                 }
5310                 case OP_SQRT:
5311                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5312                         break;
5313
5314                 case OP_RADD:
5315                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5316                         break;
5317                 case OP_RSUB:
5318                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5319                         break;
5320                 case OP_RMUL:
5321                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5322                         break;
5323                 case OP_RDIV:
5324                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5325                         break;
5326                 case OP_RNEG: {
5327                         static float r4_0 = -0.0;
5328
5329                         g_assert (ins->sreg1 == ins->dreg);
5330
5331                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5332                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5333                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5334                         break;
5335                 }
5336
5337                 case OP_IMIN:
5338                         g_assert (cfg->opt & MONO_OPT_CMOV);
5339                         g_assert (ins->dreg == ins->sreg1);
5340                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5341                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5342                         break;
5343                 case OP_IMIN_UN:
5344                         g_assert (cfg->opt & MONO_OPT_CMOV);
5345                         g_assert (ins->dreg == ins->sreg1);
5346                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5347                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5348                         break;
5349                 case OP_IMAX:
5350                         g_assert (cfg->opt & MONO_OPT_CMOV);
5351                         g_assert (ins->dreg == ins->sreg1);
5352                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5353                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5354                         break;
5355                 case OP_IMAX_UN:
5356                         g_assert (cfg->opt & MONO_OPT_CMOV);
5357                         g_assert (ins->dreg == ins->sreg1);
5358                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5359                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5360                         break;
5361                 case OP_LMIN:
5362                         g_assert (cfg->opt & MONO_OPT_CMOV);
5363                         g_assert (ins->dreg == ins->sreg1);
5364                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5365                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5366                         break;
5367                 case OP_LMIN_UN:
5368                         g_assert (cfg->opt & MONO_OPT_CMOV);
5369                         g_assert (ins->dreg == ins->sreg1);
5370                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5371                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5372                         break;
5373                 case OP_LMAX:
5374                         g_assert (cfg->opt & MONO_OPT_CMOV);
5375                         g_assert (ins->dreg == ins->sreg1);
5376                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5377                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5378                         break;
5379                 case OP_LMAX_UN:
5380                         g_assert (cfg->opt & MONO_OPT_CMOV);
5381                         g_assert (ins->dreg == ins->sreg1);
5382                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5383                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5384                         break;
5385                 case OP_X86_FPOP:
5386                         break;
5387                 case OP_FCOMPARE:
5388                         /*
5389                          * The two arguments are swapped because the fbranch instructions
5390                          * depend on this for the non-sse case to work.
5391                          */
5392                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5393                         break;
5394                 case OP_RCOMPARE:
5395                         /*
5396                          * FIXME: Get rid of this.
5397                          * The two arguments are swapped because the fbranch instructions
5398                          * depend on this for the non-sse case to work.
5399                          */
5400                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5401                         break;
5402                 case OP_FCNEQ:
5403                 case OP_FCEQ: {
5404                         /* zeroing the register at the start results in
5405                          * shorter and faster code (we can also remove the widening op)
5406                          */
5407                         guchar *unordered_check;
5408
5409                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5410                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5411                         unordered_check = code;
5412                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5413
5414                         if (ins->opcode == OP_FCEQ) {
5415                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5416                                 amd64_patch (unordered_check, code);
5417                         } else {
5418                                 guchar *jump_to_end;
5419                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5420                                 jump_to_end = code;
5421                                 x86_jump8 (code, 0);
5422                                 amd64_patch (unordered_check, code);
5423                                 amd64_inc_reg (code, ins->dreg);
5424                                 amd64_patch (jump_to_end, code);
5425                         }
5426                         break;
5427                 }
5428                 case OP_FCLT:
5429                 case OP_FCLT_UN: {
5430                         /* zeroing the register at the start results in
5431                          * shorter and faster code (we can also remove the widening op)
5432                          */
5433                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5434                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5435                         if (ins->opcode == OP_FCLT_UN) {
5436                                 guchar *unordered_check = code;
5437                                 guchar *jump_to_end;
5438                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5439                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5440                                 jump_to_end = code;
5441                                 x86_jump8 (code, 0);
5442                                 amd64_patch (unordered_check, code);
5443                                 amd64_inc_reg (code, ins->dreg);
5444                                 amd64_patch (jump_to_end, code);
5445                         } else {
5446                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5447                         }
5448                         break;
5449                 }
5450                 case OP_FCLE: {
5451                         guchar *unordered_check;
5452                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5453                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5454                         unordered_check = code;
5455                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5456                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5457                         amd64_patch (unordered_check, code);
5458                         break;
5459                 }
5460                 case OP_FCGT:
5461                 case OP_FCGT_UN: {
5462                         /* zeroing the register at the start results in
5463                          * shorter and faster code (we can also remove the widening op)
5464                          */
5465                         guchar *unordered_check;
5466
5467                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5468                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5469                         if (ins->opcode == OP_FCGT) {
5470                                 unordered_check = code;
5471                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5472                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5473                                 amd64_patch (unordered_check, code);
5474                         } else {
5475                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5476                         }
5477                         break;
5478                 }
5479                 case OP_FCGE: {
5480                         guchar *unordered_check;
5481                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5482                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5483                         unordered_check = code;
5484                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5485                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5486                         amd64_patch (unordered_check, code);
5487                         break;
5488                 }
5489
5490                 case OP_RCEQ:
5491                 case OP_RCGT:
5492                 case OP_RCLT:
5493                 case OP_RCLT_UN:
5494                 case OP_RCGT_UN: {
5495                         int x86_cond;
5496                         gboolean unordered = FALSE;
5497
5498                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5499                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5500
5501                         switch (ins->opcode) {
5502                         case OP_RCEQ:
5503                                 x86_cond = X86_CC_EQ;
5504                                 break;
5505                         case OP_RCGT:
5506                                 x86_cond = X86_CC_LT;
5507                                 break;
5508                         case OP_RCLT:
5509                                 x86_cond = X86_CC_GT;
5510                                 break;
5511                         case OP_RCLT_UN:
5512                                 x86_cond = X86_CC_GT;
5513                                 unordered = TRUE;
5514                                 break;
5515                         case OP_RCGT_UN:
5516                                 x86_cond = X86_CC_LT;
5517                                 unordered = TRUE;
5518                                 break;
5519                         default:
5520                                 g_assert_not_reached ();
5521                                 break;
5522                         }
5523
5524                         if (unordered) {
5525                                 guchar *unordered_check;
5526                                 guchar *jump_to_end;
5527
5528                                 unordered_check = code;
5529                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5530                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5531                                 jump_to_end = code;
5532                                 x86_jump8 (code, 0);
5533                                 amd64_patch (unordered_check, code);
5534                                 amd64_inc_reg (code, ins->dreg);
5535                                 amd64_patch (jump_to_end, code);
5536                         } else {
5537                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5538                         }
5539                         break;
5540                 }
5541                 case OP_FCLT_MEMBASE:
5542                 case OP_FCGT_MEMBASE:
5543                 case OP_FCLT_UN_MEMBASE:
5544                 case OP_FCGT_UN_MEMBASE:
5545                 case OP_FCEQ_MEMBASE: {
5546                         guchar *unordered_check, *jump_to_end;
5547                         int x86_cond;
5548
5549                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5550                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5551
5552                         switch (ins->opcode) {
5553                         case OP_FCEQ_MEMBASE:
5554                                 x86_cond = X86_CC_EQ;
5555                                 break;
5556                         case OP_FCLT_MEMBASE:
5557                         case OP_FCLT_UN_MEMBASE:
5558                                 x86_cond = X86_CC_LT;
5559                                 break;
5560                         case OP_FCGT_MEMBASE:
5561                         case OP_FCGT_UN_MEMBASE:
5562                                 x86_cond = X86_CC_GT;
5563                                 break;
5564                         default:
5565                                 g_assert_not_reached ();
5566                         }
5567
5568                         unordered_check = code;
5569                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5570                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5571
5572                         switch (ins->opcode) {
5573                         case OP_FCEQ_MEMBASE:
5574                         case OP_FCLT_MEMBASE:
5575                         case OP_FCGT_MEMBASE:
5576                                 amd64_patch (unordered_check, code);
5577                                 break;
5578                         case OP_FCLT_UN_MEMBASE:
5579                         case OP_FCGT_UN_MEMBASE:
5580                                 jump_to_end = code;
5581                                 x86_jump8 (code, 0);
5582                                 amd64_patch (unordered_check, code);
5583                                 amd64_inc_reg (code, ins->dreg);
5584                                 amd64_patch (jump_to_end, code);
5585                                 break;
5586                         default:
5587                                 break;
5588                         }
5589                         break;
5590                 }
5591                 case OP_FBEQ: {
5592                         guchar *jump = code;
5593                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5594                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5595                         amd64_patch (jump, code);
5596                         break;
5597                 }
5598                 case OP_FBNE_UN:
5599                         /* Branch if C013 != 100 */
5600                         /* branch if !ZF or (PF|CF) */
5601                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5602                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5603                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5604                         break;
5605                 case OP_FBLT:
5606                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5607                         break;
5608                 case OP_FBLT_UN:
5609                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5610                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5611                         break;
5612                 case OP_FBGT:
5613                 case OP_FBGT_UN:
5614                         if (ins->opcode == OP_FBGT) {
5615                                 guchar *br1;
5616
5617                                 /* skip branch if C1=1 */
5618                                 br1 = code;
5619                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5620                                 /* branch if (C0 | C3) = 1 */
5621                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5622                                 amd64_patch (br1, code);
5623                                 break;
5624                         } else {
5625                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5626                         }
5627                         break;
5628                 case OP_FBGE: {
5629                         /* Branch if C013 == 100 or 001 */
5630                         guchar *br1;
5631
5632                         /* skip branch if C1=1 */
5633                         br1 = code;
5634                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5635                         /* branch if (C0 | C3) = 1 */
5636                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5637                         amd64_patch (br1, code);
5638                         break;
5639                 }
5640                 case OP_FBGE_UN:
5641                         /* Branch if C013 == 000 */
5642                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5643                         break;
5644                 case OP_FBLE: {
5645                         /* Branch if C013=000 or 100 */
5646                         guchar *br1;
5647
5648                         /* skip branch if C1=1 */
5649                         br1 = code;
5650                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5651                         /* branch if C0=0 */
5652                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5653                         amd64_patch (br1, code);
5654                         break;
5655                 }
5656                 case OP_FBLE_UN:
5657                         /* Branch if C013 != 001 */
5658                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5659                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5660                         break;
5661                 case OP_CKFINITE:
5662                         /* Transfer value to the fp stack */
5663                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5664                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5665                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5666
5667                         amd64_push_reg (code, AMD64_RAX);
5668                         amd64_fxam (code);
5669                         amd64_fnstsw (code);
5670                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5671                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5672                         amd64_pop_reg (code, AMD64_RAX);
5673                         amd64_fstp (code, 0);
5674                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5675                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5676                         break;
5677                 case OP_TLS_GET: {
5678                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5679                         break;
5680                 }
5681                 case OP_TLS_GET_REG:
5682                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5683                         break;
5684                 case OP_TLS_SET: {
5685                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5686                         break;
5687                 }
5688                 case OP_TLS_SET_REG: {
5689                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5690                         break;
5691                 }
5692                 case OP_MEMORY_BARRIER: {
5693                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5694                                 x86_mfence (code);
5695                         break;
5696                 }
5697                 case OP_ATOMIC_ADD_I4:
5698                 case OP_ATOMIC_ADD_I8: {
5699                         int dreg = ins->dreg;
5700                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5701
5702                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5703                                 dreg = AMD64_R11;
5704
5705                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5706                         amd64_prefix (code, X86_LOCK_PREFIX);
5707                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5708                         /* dreg contains the old value, add with sreg2 value */
5709                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5710
5711                         if (ins->dreg != dreg)
5712                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5713
5714                         break;
5715                 }
5716                 case OP_ATOMIC_EXCHANGE_I4:
5717                 case OP_ATOMIC_EXCHANGE_I8: {
5718                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5719
5720                         /* LOCK prefix is implied. */
5721                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5722                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5723                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5724                         break;
5725                 }
5726                 case OP_ATOMIC_CAS_I4:
5727                 case OP_ATOMIC_CAS_I8: {
5728                         guint32 size;
5729
5730                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5731                                 size = 8;
5732                         else
5733                                 size = 4;
5734
5735                         /*
5736                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5737                          * an explanation of how this works.
5738                          */
5739                         g_assert (ins->sreg3 == AMD64_RAX);
5740                         g_assert (ins->sreg1 != AMD64_RAX);
5741                         g_assert (ins->sreg1 != ins->sreg2);
5742
5743                         amd64_prefix (code, X86_LOCK_PREFIX);
5744                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5745
5746                         if (ins->dreg != AMD64_RAX)
5747                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5748                         break;
5749                 }
5750                 case OP_ATOMIC_LOAD_I1: {
5751                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5752                         break;
5753                 }
5754                 case OP_ATOMIC_LOAD_U1: {
5755                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5756                         break;
5757                 }
5758                 case OP_ATOMIC_LOAD_I2: {
5759                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5760                         break;
5761                 }
5762                 case OP_ATOMIC_LOAD_U2: {
5763                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5764                         break;
5765                 }
5766                 case OP_ATOMIC_LOAD_I4: {
5767                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5768                         break;
5769                 }
5770                 case OP_ATOMIC_LOAD_U4:
5771                 case OP_ATOMIC_LOAD_I8:
5772                 case OP_ATOMIC_LOAD_U8: {
5773                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5774                         break;
5775                 }
5776                 case OP_ATOMIC_LOAD_R4: {
5777                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5778                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5779                         break;
5780                 }
5781                 case OP_ATOMIC_LOAD_R8: {
5782                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5783                         break;
5784                 }
5785                 case OP_ATOMIC_STORE_I1:
5786                 case OP_ATOMIC_STORE_U1:
5787                 case OP_ATOMIC_STORE_I2:
5788                 case OP_ATOMIC_STORE_U2:
5789                 case OP_ATOMIC_STORE_I4:
5790                 case OP_ATOMIC_STORE_U4:
5791                 case OP_ATOMIC_STORE_I8:
5792                 case OP_ATOMIC_STORE_U8: {
5793                         int size;
5794
5795                         switch (ins->opcode) {
5796                         case OP_ATOMIC_STORE_I1:
5797                         case OP_ATOMIC_STORE_U1:
5798                                 size = 1;
5799                                 break;
5800                         case OP_ATOMIC_STORE_I2:
5801                         case OP_ATOMIC_STORE_U2:
5802                                 size = 2;
5803                                 break;
5804                         case OP_ATOMIC_STORE_I4:
5805                         case OP_ATOMIC_STORE_U4:
5806                                 size = 4;
5807                                 break;
5808                         case OP_ATOMIC_STORE_I8:
5809                         case OP_ATOMIC_STORE_U8:
5810                                 size = 8;
5811                                 break;
5812                         }
5813
5814                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5815
5816                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5817                                 x86_mfence (code);
5818                         break;
5819                 }
5820                 case OP_ATOMIC_STORE_R4: {
5821                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5822                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5823
5824                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5825                                 x86_mfence (code);
5826                         break;
5827                 }
5828                 case OP_ATOMIC_STORE_R8: {
5829                         x86_nop (code);
5830                         x86_nop (code);
5831                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5832                         x86_nop (code);
5833                         x86_nop (code);
5834
5835                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5836                                 x86_mfence (code);
5837                         break;
5838                 }
5839                 case OP_CARD_TABLE_WBARRIER: {
5840                         int ptr = ins->sreg1;
5841                         int value = ins->sreg2;
5842                         guchar *br = 0;
5843                         int nursery_shift, card_table_shift;
5844                         gpointer card_table_mask;
5845                         size_t nursery_size;
5846
5847                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5848                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5849                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5850
5851                         /*If either point to the stack we can simply avoid the WB. This happens due to
5852                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5853                          */
5854                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5855                                 continue;
5856
5857                         /*
5858                          * We need one register we can clobber, we choose EDX and make sreg1
5859                          * fixed EAX to work around limitations in the local register allocator.
5860                          * sreg2 might get allocated to EDX, but that is not a problem since
5861                          * we use it before clobbering EDX.
5862                          */
5863                         g_assert (ins->sreg1 == AMD64_RAX);
5864
5865                         /*
5866                          * This is the code we produce:
5867                          *
5868                          *   edx = value
5869                          *   edx >>= nursery_shift
5870                          *   cmp edx, (nursery_start >> nursery_shift)
5871                          *   jne done
5872                          *   edx = ptr
5873                          *   edx >>= card_table_shift
5874                          *   edx += cardtable
5875                          *   [edx] = 1
5876                          * done:
5877                          */
5878
5879                         if (mono_gc_card_table_nursery_check ()) {
5880                                 if (value != AMD64_RDX)
5881                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5882                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5883                                 if (shifted_nursery_start >> 31) {
5884                                         /*
5885                                          * The value we need to compare against is 64 bits, so we need
5886                                          * another spare register.  We use RBX, which we save and
5887                                          * restore.
5888                                          */
5889                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5890                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5891                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5892                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5893                                 } else {
5894                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5895                                 }
5896                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5897                         }
5898                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5899                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5900                         if (card_table_mask)
5901                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5902
5903                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5904                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5905
5906                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5907
5908                         if (mono_gc_card_table_nursery_check ())
5909                                 x86_patch (br, code);
5910                         break;
5911                 }
5912 #ifdef MONO_ARCH_SIMD_INTRINSICS
5913                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5914                 case OP_ADDPS:
5915                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917                 case OP_DIVPS:
5918                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5919                         break;
5920                 case OP_MULPS:
5921                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5922                         break;
5923                 case OP_SUBPS:
5924                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5925                         break;
5926                 case OP_MAXPS:
5927                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5928                         break;
5929                 case OP_MINPS:
5930                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5931                         break;
5932                 case OP_COMPPS:
5933                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5934                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5935                         break;
5936                 case OP_ANDPS:
5937                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5938                         break;
5939                 case OP_ANDNPS:
5940                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5941                         break;
5942                 case OP_ORPS:
5943                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5944                         break;
5945                 case OP_XORPS:
5946                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 case OP_SQRTPS:
5949                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5950                         break;
5951                 case OP_RSQRTPS:
5952                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5953                         break;
5954                 case OP_RCPPS:
5955                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5956                         break;
5957                 case OP_ADDSUBPS:
5958                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5959                         break;
5960                 case OP_HADDPS:
5961                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963                 case OP_HSUBPS:
5964                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5965                         break;
5966                 case OP_DUPPS_HIGH:
5967                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5968                         break;
5969                 case OP_DUPPS_LOW:
5970                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5971                         break;
5972
5973                 case OP_PSHUFLEW_HIGH:
5974                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5975                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5976                         break;
5977                 case OP_PSHUFLEW_LOW:
5978                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5979                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5980                         break;
5981                 case OP_PSHUFLED:
5982                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5983                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5984                         break;
5985                 case OP_SHUFPS:
5986                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5987                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5988                         break;
5989                 case OP_SHUFPD:
5990                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5991                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5992                         break;
5993
5994                 case OP_ADDPD:
5995                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997                 case OP_DIVPD:
5998                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_MULPD:
6001                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6002                         break;
6003                 case OP_SUBPD:
6004                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6005                         break;
6006                 case OP_MAXPD:
6007                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6008                         break;
6009                 case OP_MINPD:
6010                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6011                         break;
6012                 case OP_COMPPD:
6013                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6014                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6015                         break;
6016                 case OP_ANDPD:
6017                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6018                         break;
6019                 case OP_ANDNPD:
6020                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6021                         break;
6022                 case OP_ORPD:
6023                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6024                         break;
6025                 case OP_XORPD:
6026                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6027                         break;
6028                 case OP_SQRTPD:
6029                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6030                         break;
6031                 case OP_ADDSUBPD:
6032                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6033                         break;
6034                 case OP_HADDPD:
6035                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6036                         break;
6037                 case OP_HSUBPD:
6038                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6039                         break;
6040                 case OP_DUPPD:
6041                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6042                         break;
6043
6044                 case OP_EXTRACT_MASK:
6045                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6046                         break;
6047
6048                 case OP_PAND:
6049                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6050                         break;
6051                 case OP_POR:
6052                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6053                         break;
6054                 case OP_PXOR:
6055                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6056                         break;
6057
6058                 case OP_PADDB:
6059                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6060                         break;
6061                 case OP_PADDW:
6062                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6063                         break;
6064                 case OP_PADDD:
6065                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6066                         break;
6067                 case OP_PADDQ:
6068                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6069                         break;
6070
6071                 case OP_PSUBB:
6072                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6073                         break;
6074                 case OP_PSUBW:
6075                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6076                         break;
6077                 case OP_PSUBD:
6078                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6079                         break;
6080                 case OP_PSUBQ:
6081                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6082                         break;
6083
6084                 case OP_PMAXB_UN:
6085                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6086                         break;
6087                 case OP_PMAXW_UN:
6088                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6089                         break;
6090                 case OP_PMAXD_UN:
6091                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6092                         break;
6093
6094                 case OP_PMAXB:
6095                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6096                         break;
6097                 case OP_PMAXW:
6098                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6099                         break;
6100                 case OP_PMAXD:
6101                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6102                         break;
6103
6104                 case OP_PAVGB_UN:
6105                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6106                         break;
6107                 case OP_PAVGW_UN:
6108                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6109                         break;
6110
6111                 case OP_PMINB_UN:
6112                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6113                         break;
6114                 case OP_PMINW_UN:
6115                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6116                         break;
6117                 case OP_PMIND_UN:
6118                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6119                         break;
6120
6121                 case OP_PMINB:
6122                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124                 case OP_PMINW:
6125                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6126                         break;
6127                 case OP_PMIND:
6128                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6129                         break;
6130
6131                 case OP_PCMPEQB:
6132                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134                 case OP_PCMPEQW:
6135                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137                 case OP_PCMPEQD:
6138                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6139                         break;
6140                 case OP_PCMPEQQ:
6141                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6142                         break;
6143
6144                 case OP_PCMPGTB:
6145                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6146                         break;
6147                 case OP_PCMPGTW:
6148                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6149                         break;
6150                 case OP_PCMPGTD:
6151                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6152                         break;
6153                 case OP_PCMPGTQ:
6154                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6155                         break;
6156
6157                 case OP_PSUM_ABS_DIFF:
6158                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6159                         break;
6160
6161                 case OP_UNPACK_LOWB:
6162                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6163                         break;
6164                 case OP_UNPACK_LOWW:
6165                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6166                         break;
6167                 case OP_UNPACK_LOWD:
6168                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6169                         break;
6170                 case OP_UNPACK_LOWQ:
6171                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6172                         break;
6173                 case OP_UNPACK_LOWPS:
6174                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6175                         break;
6176                 case OP_UNPACK_LOWPD:
6177                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6178                         break;
6179
6180                 case OP_UNPACK_HIGHB:
6181                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_UNPACK_HIGHW:
6184                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186                 case OP_UNPACK_HIGHD:
6187                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_UNPACK_HIGHQ:
6190                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6191                         break;
6192                 case OP_UNPACK_HIGHPS:
6193                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6194                         break;
6195                 case OP_UNPACK_HIGHPD:
6196                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6197                         break;
6198
6199                 case OP_PACKW:
6200                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6201                         break;
6202                 case OP_PACKD:
6203                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6204                         break;
6205                 case OP_PACKW_UN:
6206                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6207                         break;
6208                 case OP_PACKD_UN:
6209                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6210                         break;
6211
6212                 case OP_PADDB_SAT_UN:
6213                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6214                         break;
6215                 case OP_PSUBB_SAT_UN:
6216                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6217                         break;
6218                 case OP_PADDW_SAT_UN:
6219                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6220                         break;
6221                 case OP_PSUBW_SAT_UN:
6222                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6223                         break;
6224
6225                 case OP_PADDB_SAT:
6226                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6227                         break;
6228                 case OP_PSUBB_SAT:
6229                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6230                         break;
6231                 case OP_PADDW_SAT:
6232                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6233                         break;
6234                 case OP_PSUBW_SAT:
6235                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6236                         break;
6237
6238                 case OP_PMULW:
6239                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6240                         break;
6241                 case OP_PMULD:
6242                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6243                         break;
6244                 case OP_PMULQ:
6245                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6246                         break;
6247                 case OP_PMULW_HIGH_UN:
6248                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6249                         break;
6250                 case OP_PMULW_HIGH:
6251                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6252                         break;
6253
6254                 case OP_PSHRW:
6255                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6256                         break;
6257                 case OP_PSHRW_REG:
6258                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6259                         break;
6260
6261                 case OP_PSARW:
6262                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6263                         break;
6264                 case OP_PSARW_REG:
6265                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6266                         break;
6267
6268                 case OP_PSHLW:
6269                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6270                         break;
6271                 case OP_PSHLW_REG:
6272                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6273                         break;
6274
6275                 case OP_PSHRD:
6276                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6277                         break;
6278                 case OP_PSHRD_REG:
6279                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6280                         break;
6281
6282                 case OP_PSARD:
6283                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6284                         break;
6285                 case OP_PSARD_REG:
6286                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6287                         break;
6288
6289                 case OP_PSHLD:
6290                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6291                         break;
6292                 case OP_PSHLD_REG:
6293                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6294                         break;
6295
6296                 case OP_PSHRQ:
6297                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6298                         break;
6299                 case OP_PSHRQ_REG:
6300                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6301                         break;
6302
6303                 /*TODO: This is appart of the sse spec but not added
6304                 case OP_PSARQ:
6305                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6306                         break;
6307                 case OP_PSARQ_REG:
6308                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6309                         break;
6310                 */
6311
6312                 case OP_PSHLQ:
6313                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6314                         break;
6315                 case OP_PSHLQ_REG:
6316                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6317                         break;
6318                 case OP_CVTDQ2PD:
6319                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6320                         break;
6321                 case OP_CVTDQ2PS:
6322                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6323                         break;
6324                 case OP_CVTPD2DQ:
6325                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6326                         break;
6327                 case OP_CVTPD2PS:
6328                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6329                         break;
6330                 case OP_CVTPS2DQ:
6331                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6332                         break;
6333                 case OP_CVTPS2PD:
6334                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6335                         break;
6336                 case OP_CVTTPD2DQ:
6337                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6338                         break;
6339                 case OP_CVTTPS2DQ:
6340                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6341                         break;
6342
6343                 case OP_ICONV_TO_X:
6344                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6345                         break;
6346                 case OP_EXTRACT_I4:
6347                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6348                         break;
6349                 case OP_EXTRACT_I8:
6350                         if (ins->inst_c0) {
6351                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6352                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6353                         } else {
6354                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6355                         }
6356                         break;
6357                 case OP_EXTRACT_I1:
6358                 case OP_EXTRACT_U1:
6359                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6360                         if (ins->inst_c0)
6361                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6362                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6363                         break;
6364                 case OP_EXTRACT_I2:
6365                 case OP_EXTRACT_U2:
6366                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6367                         if (ins->inst_c0)
6368                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6369                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6370                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6371                         break;
6372                 case OP_EXTRACT_R8:
6373                         if (ins->inst_c0)
6374                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6375                         else
6376                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6377                         break;
6378                 case OP_INSERT_I2:
6379                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6380                         break;
6381                 case OP_EXTRACTX_U2:
6382                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6383                         break;
6384                 case OP_INSERTX_U1_SLOW:
6385                         /*sreg1 is the extracted ireg (scratch)
6386                         /sreg2 is the to be inserted ireg (scratch)
6387                         /dreg is the xreg to receive the value*/
6388
6389                         /*clear the bits from the extracted word*/
6390                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6391                         /*shift the value to insert if needed*/
6392                         if (ins->inst_c0 & 1)
6393                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6394                         /*join them together*/
6395                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6396                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6397                         break;
6398                 case OP_INSERTX_I4_SLOW:
6399                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6400                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6401                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6402                         break;
6403                 case OP_INSERTX_I8_SLOW:
6404                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6405                         if (ins->inst_c0)
6406                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6407                         else
6408                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6409                         break;
6410
6411                 case OP_INSERTX_R4_SLOW:
6412                         switch (ins->inst_c0) {
6413                         case 0:
6414                                 if (cfg->r4fp)
6415                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6416                                 else
6417                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6418                                 break;
6419                         case 1:
6420                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6421                                 if (cfg->r4fp)
6422                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6423                                 else
6424                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6425                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6426                                 break;
6427                         case 2:
6428                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6429                                 if (cfg->r4fp)
6430                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6431                                 else
6432                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6433                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6434                                 break;
6435                         case 3:
6436                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6437                                 if (cfg->r4fp)
6438                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6439                                 else
6440                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6441                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6442                                 break;
6443                         }
6444                         break;
6445                 case OP_INSERTX_R8_SLOW:
6446                         if (ins->inst_c0)
6447                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6448                         else
6449                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6450                         break;
6451                 case OP_STOREX_MEMBASE_REG:
6452                 case OP_STOREX_MEMBASE:
6453                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6454                         break;
6455                 case OP_LOADX_MEMBASE:
6456                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6457                         break;
6458                 case OP_LOADX_ALIGNED_MEMBASE:
6459                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6460                         break;
6461                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6462                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6463                         break;
6464                 case OP_STOREX_NTA_MEMBASE_REG:
6465                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6466                         break;
6467                 case OP_PREFETCH_MEMBASE:
6468                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6469                         break;
6470
6471                 case OP_XMOVE:
6472                         /*FIXME the peephole pass should have killed this*/
6473                         if (ins->dreg != ins->sreg1)
6474                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6475                         break;
6476                 case OP_XZERO:
6477                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6478                         break;
6479                 case OP_ICONV_TO_R4_RAW:
6480                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6481                         break;
6482
6483                 case OP_FCONV_TO_R8_X:
6484                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6485                         break;
6486
6487                 case OP_XCONV_R8_TO_I4:
6488                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6489                         switch (ins->backend.source_opcode) {
6490                         case OP_FCONV_TO_I1:
6491                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6492                                 break;
6493                         case OP_FCONV_TO_U1:
6494                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6495                                 break;
6496                         case OP_FCONV_TO_I2:
6497                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6498                                 break;
6499                         case OP_FCONV_TO_U2:
6500                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6501                                 break;
6502                         }
6503                         break;
6504
6505                 case OP_EXPAND_I2:
6506                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6507                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6508                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6509                         break;
6510                 case OP_EXPAND_I4:
6511                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6512                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6513                         break;
6514                 case OP_EXPAND_I8:
6515                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6516                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6517                         break;
6518                 case OP_EXPAND_R4:
6519                         if (cfg->r4fp) {
6520                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6521                         } else {
6522                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6523                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6524                         }
6525                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6526                         break;
6527                 case OP_EXPAND_R8:
6528                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6529                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6530                         break;
6531 #endif
6532                 case OP_LIVERANGE_START: {
6533                         if (cfg->verbose_level > 1)
6534                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6535                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6536                         break;
6537                 }
6538                 case OP_LIVERANGE_END: {
6539                         if (cfg->verbose_level > 1)
6540                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6541                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6542                         break;
6543                 }
6544                 case OP_NACL_GC_SAFE_POINT: {
6545 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6546                         if (cfg->compile_aot)
6547                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6548                         else {
6549                                 guint8 *br [1];
6550
6551                                 amd64_mov_reg_imm_size (code, AMD64_R11, (gpointer)&__nacl_thread_suspension_needed, 4);
6552                                 amd64_test_membase_imm_size (code, AMD64_R11, 0, 0xFFFFFFFF, 4);
6553                                 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6554                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)mono_nacl_gc, TRUE);
6555                                 amd64_patch (br[0], code);
6556                         }
6557 #endif
6558                         break;
6559                 }
6560                 case OP_GC_LIVENESS_DEF:
6561                 case OP_GC_LIVENESS_USE:
6562                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6563                         ins->backend.pc_offset = code - cfg->native_code;
6564                         break;
6565                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6566                         ins->backend.pc_offset = code - cfg->native_code;
6567                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6568                         break;
6569                 default:
6570                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6571                         g_assert_not_reached ();
6572                 }
6573
6574                 if ((code - cfg->native_code - offset) > max_len) {
6575 #if !defined(__native_client_codegen__)
6576                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6577                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6578                         g_assert_not_reached ();
6579 #endif
6580                 }
6581         }
6582
6583         cfg->code_len = code - cfg->native_code;
6584 }
6585
6586 #endif /* DISABLE_JIT */
6587
6588 void
6589 mono_arch_register_lowlevel_calls (void)
6590 {
6591         /* The signature doesn't matter */
6592         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6593 }
6594
6595 void
6596 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, MonoCodeManager *dyn_code_mp, gboolean run_cctors)
6597 {
6598         MonoJumpInfo *patch_info;
6599         gboolean compile_aot = !run_cctors;
6600
6601         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
6602                 unsigned char *ip = patch_info->ip.i + code;
6603                 unsigned char *target;
6604
6605                 if (compile_aot) {
6606                         switch (patch_info->type) {
6607                         case MONO_PATCH_INFO_BB:
6608                         case MONO_PATCH_INFO_LABEL:
6609                                 break;
6610                         default:
6611                                 /* No need to patch these */
6612                                 continue;
6613                         }
6614                 }
6615
6616                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
6617
6618                 switch (patch_info->type) {
6619                 case MONO_PATCH_INFO_NONE:
6620                         continue;
6621                 case MONO_PATCH_INFO_METHOD_REL:
6622                 case MONO_PATCH_INFO_R8:
6623                 case MONO_PATCH_INFO_R4:
6624                         g_assert_not_reached ();
6625                         continue;
6626                 case MONO_PATCH_INFO_BB:
6627                         break;
6628                 default:
6629                         break;
6630                 }
6631
6632                 /*
6633                  * Debug code to help track down problems where the target of a near call is
6634                  * is not valid.
6635                  */
6636                 if (amd64_is_near_call (ip)) {
6637                         gint64 disp = (guint8*)target - (guint8*)ip;
6638
6639                         if (!amd64_is_imm32 (disp)) {
6640                                 printf ("TYPE: %d\n", patch_info->type);
6641                                 switch (patch_info->type) {
6642                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
6643                                         printf ("V: %s\n", patch_info->data.name);
6644                                         break;
6645                                 case MONO_PATCH_INFO_METHOD_JUMP:
6646                                 case MONO_PATCH_INFO_METHOD:
6647                                         printf ("V: %s\n", patch_info->data.method->name);
6648                                         break;
6649                                 default:
6650                                         break;
6651                                 }
6652                         }
6653                 }
6654
6655                 amd64_patch (ip, (gpointer)target);
6656         }
6657 }
6658
6659 #ifndef DISABLE_JIT
6660
6661 static int
6662 get_max_epilog_size (MonoCompile *cfg)
6663 {
6664         int max_epilog_size = 16;
6665
6666         if (cfg->method->save_lmf)
6667                 max_epilog_size += 256;
6668
6669         if (mono_jit_trace_calls != NULL)
6670                 max_epilog_size += 50;
6671
6672         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6673                 max_epilog_size += 50;
6674
6675         max_epilog_size += (AMD64_NREG * 2);
6676
6677         return max_epilog_size;
6678 }
6679
6680 /*
6681  * This macro is used for testing whenever the unwinder works correctly at every point
6682  * where an async exception can happen.
6683  */
6684 /* This will generate a SIGSEGV at the given point in the code */
6685 #define async_exc_point(code) do { \
6686     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6687          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6688              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6689          cfg->arch.async_point_count ++; \
6690     } \
6691 } while (0)
6692
6693 guint8 *
6694 mono_arch_emit_prolog (MonoCompile *cfg)
6695 {
6696         MonoMethod *method = cfg->method;
6697         MonoBasicBlock *bb;
6698         MonoMethodSignature *sig;
6699         MonoInst *ins;
6700         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6701         guint8 *code;
6702         CallInfo *cinfo;
6703         MonoInst *lmf_var = cfg->lmf_var;
6704         gboolean args_clobbered = FALSE;
6705         gboolean trace = FALSE;
6706 #ifdef __native_client_codegen__
6707         guint alignment_check;
6708 #endif
6709
6710         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6711
6712 #if defined(__default_codegen__)
6713         code = cfg->native_code = g_malloc (cfg->code_size);
6714 #elif defined(__native_client_codegen__)
6715         /* native_code_alloc is not 32-byte aligned, native_code is. */
6716         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6717
6718         /* Align native_code to next nearest kNaclAlignment byte. */
6719         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6720         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6721
6722         code = cfg->native_code;
6723
6724         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6725         g_assert (alignment_check == 0);
6726 #endif
6727
6728         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6729                 trace = TRUE;
6730
6731         /* Amount of stack space allocated by register saving code */
6732         pos = 0;
6733
6734         /* Offset between RSP and the CFA */
6735         cfa_offset = 0;
6736
6737         /*
6738          * The prolog consists of the following parts:
6739          * FP present:
6740          * - push rbp, mov rbp, rsp
6741          * - save callee saved regs using pushes
6742          * - allocate frame
6743          * - save rgctx if needed
6744          * - save lmf if needed
6745          * FP not present:
6746          * - allocate frame
6747          * - save rgctx if needed
6748          * - save lmf if needed
6749          * - save callee saved regs using moves
6750          */
6751
6752         // CFA = sp + 8
6753         cfa_offset = 8;
6754         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6755         // IP saved at CFA - 8
6756         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6757         async_exc_point (code);
6758         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6759
6760         if (!cfg->arch.omit_fp) {
6761                 amd64_push_reg (code, AMD64_RBP);
6762                 cfa_offset += 8;
6763                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6764                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6765                 async_exc_point (code);
6766 #ifdef HOST_WIN32
6767                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6768 #endif
6769                 /* These are handled automatically by the stack marking code */
6770                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6771
6772                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6773                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6774                 async_exc_point (code);
6775 #ifdef HOST_WIN32
6776                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6777 #endif
6778         }
6779
6780         /* The param area is always at offset 0 from sp */
6781         /* This needs to be allocated here, since it has to come after the spill area */
6782         if (cfg->param_area) {
6783                 if (cfg->arch.omit_fp)
6784                         // FIXME:
6785                         g_assert_not_reached ();
6786                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6787         }
6788
6789         if (cfg->arch.omit_fp) {
6790                 /*
6791                  * On enter, the stack is misaligned by the pushing of the return
6792                  * address. It is either made aligned by the pushing of %rbp, or by
6793                  * this.
6794                  */
6795                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6796                 if ((alloc_size % 16) == 0) {
6797                         alloc_size += 8;
6798                         /* Mark the padding slot as NOREF */
6799                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6800                 }
6801         } else {
6802                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6803                 if (cfg->stack_offset != alloc_size) {
6804                         /* Mark the padding slot as NOREF */
6805                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6806                 }
6807                 cfg->arch.sp_fp_offset = alloc_size;
6808                 alloc_size -= pos;
6809         }
6810
6811         cfg->arch.stack_alloc_size = alloc_size;
6812
6813         /* Allocate stack frame */
6814         if (alloc_size) {
6815                 /* See mono_emit_stack_alloc */
6816 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6817                 guint32 remaining_size = alloc_size;
6818                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6819                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6820                 guint32 offset = code - cfg->native_code;
6821                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6822                         while (required_code_size >= (cfg->code_size - offset))
6823                                 cfg->code_size *= 2;
6824                         cfg->native_code = mono_realloc_native_code (cfg);
6825                         code = cfg->native_code + offset;
6826                         cfg->stat_code_reallocs++;
6827                 }
6828
6829                 while (remaining_size >= 0x1000) {
6830                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6831                         if (cfg->arch.omit_fp) {
6832                                 cfa_offset += 0x1000;
6833                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6834                         }
6835                         async_exc_point (code);
6836 #ifdef HOST_WIN32
6837                         if (cfg->arch.omit_fp)
6838                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
6839 #endif
6840
6841                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6842                         remaining_size -= 0x1000;
6843                 }
6844                 if (remaining_size) {
6845                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6846                         if (cfg->arch.omit_fp) {
6847                                 cfa_offset += remaining_size;
6848                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6849                                 async_exc_point (code);
6850                         }
6851 #ifdef HOST_WIN32
6852                         if (cfg->arch.omit_fp)
6853                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
6854 #endif
6855                 }
6856 #else
6857                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6858                 if (cfg->arch.omit_fp) {
6859                         cfa_offset += alloc_size;
6860                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6861                         async_exc_point (code);
6862                 }
6863 #endif
6864         }
6865
6866         /* Stack alignment check */
6867 #if 0
6868         {
6869                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6870                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6871                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6872                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
6873                 amd64_breakpoint (code);
6874         }
6875 #endif
6876
6877         if (mini_get_debug_options ()->init_stacks) {
6878                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6879
6880                 /* Save registers to the red zone */
6881                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6882                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6883
6884                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6885                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6886                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6887
6888                 amd64_cld (code);
6889 #if defined(__default_codegen__)
6890                 amd64_prefix (code, X86_REP_PREFIX);
6891                 amd64_stosl (code);
6892 #elif defined(__native_client_codegen__)
6893                 /* NaCl stos pseudo-instruction */
6894                 amd64_codegen_pre (code);
6895                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
6896                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
6897                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
6898                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
6899                 amd64_prefix (code, X86_REP_PREFIX);
6900                 amd64_stosl (code);
6901                 amd64_codegen_post (code);
6902 #endif /* __native_client_codegen__ */
6903
6904                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6905                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6906         }
6907
6908         /* Save LMF */
6909         if (method->save_lmf)
6910                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6911
6912         /* Save callee saved registers */
6913         if (cfg->arch.omit_fp) {
6914                 save_area_offset = cfg->arch.reg_save_area_offset;
6915                 /* Save caller saved registers after sp is adjusted */
6916                 /* The registers are saved at the bottom of the frame */
6917                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6918         } else {
6919                 /* The registers are saved just below the saved rbp */
6920                 save_area_offset = cfg->arch.reg_save_area_offset;
6921         }
6922
6923         for (i = 0; i < AMD64_NREG; ++i) {
6924                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6925                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6926
6927                         if (cfg->arch.omit_fp) {
6928                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6929                                 /* These are handled automatically by the stack marking code */
6930                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6931                         } else {
6932                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6933                                 // FIXME: GC
6934                         }
6935
6936                         save_area_offset += 8;
6937                         async_exc_point (code);
6938                 }
6939         }
6940
6941         /* store runtime generic context */
6942         if (cfg->rgctx_var) {
6943                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6944                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6945
6946                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6947
6948                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6949                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6950         }
6951
6952         /* compute max_length in order to use short forward jumps */
6953         max_epilog_size = get_max_epilog_size (cfg);
6954         if (cfg->opt & MONO_OPT_BRANCH) {
6955                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6956                         MonoInst *ins;
6957                         int max_length = 0;
6958
6959                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6960                                 max_length += 6;
6961                         /* max alignment for loops */
6962                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6963                                 max_length += LOOP_ALIGNMENT;
6964 #ifdef __native_client_codegen__
6965                         /* max alignment for native client */
6966                         max_length += kNaClAlignment;
6967 #endif
6968
6969                         MONO_BB_FOR_EACH_INS (bb, ins) {
6970 #ifdef __native_client_codegen__
6971                                 {
6972                                         int space_in_block = kNaClAlignment -
6973                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
6974                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6975                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
6976                                                 max_length += space_in_block;
6977                                         }
6978                                 }
6979 #endif  /*__native_client_codegen__*/
6980                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6981                         }
6982
6983                         /* Take prolog and epilog instrumentation into account */
6984                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6985                                 max_length += max_epilog_size;
6986
6987                         bb->max_length = max_length;
6988                 }
6989         }
6990
6991         sig = mono_method_signature (method);
6992         pos = 0;
6993
6994         cinfo = cfg->arch.cinfo;
6995
6996         if (sig->ret->type != MONO_TYPE_VOID) {
6997                 /* Save volatile arguments to the stack */
6998                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6999                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7000         }
7001
7002         /* Keep this in sync with emit_load_volatile_arguments */
7003         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7004                 ArgInfo *ainfo = cinfo->args + i;
7005
7006                 ins = cfg->args [i];
7007
7008                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7009                         /* Unused arguments */
7010                         continue;
7011
7012                 if (cfg->globalra) {
7013                         /* All the other moves are done by the register allocator */
7014                         switch (ainfo->storage) {
7015                         case ArgInFloatSSEReg:
7016                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
7017                                 break;
7018                         case ArgValuetypeInReg:
7019                                 for (quad = 0; quad < 2; quad ++) {
7020                                         switch (ainfo->pair_storage [quad]) {
7021                                         case ArgInIReg:
7022                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7023                                                 break;
7024                                         case ArgInFloatSSEReg:
7025                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7026                                                 break;
7027                                         case ArgInDoubleSSEReg:
7028                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7029                                                 break;
7030                                         case ArgNone:
7031                                                 break;
7032                                         default:
7033                                                 g_assert_not_reached ();
7034                                         }
7035                                 }
7036                                 break;
7037                         default:
7038                                 break;
7039                         }
7040
7041                         continue;
7042                 }
7043
7044                 /* Save volatile arguments to the stack */
7045                 if (ins->opcode != OP_REGVAR) {
7046                         switch (ainfo->storage) {
7047                         case ArgInIReg: {
7048                                 guint32 size = 8;
7049
7050                                 /* FIXME: I1 etc */
7051                                 /*
7052                                 if (stack_offset & 0x1)
7053                                         size = 1;
7054                                 else if (stack_offset & 0x2)
7055                                         size = 2;
7056                                 else if (stack_offset & 0x4)
7057                                         size = 4;
7058                                 else
7059                                         size = 8;
7060                                 */
7061                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7062
7063                                 /*
7064                                  * Save the original location of 'this',
7065                                  * get_generic_info_from_stack_frame () needs this to properly look up
7066                                  * the argument value during the handling of async exceptions.
7067                                  */
7068                                 if (ins == cfg->args [0]) {
7069                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7070                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7071                                 }
7072                                 break;
7073                         }
7074                         case ArgInFloatSSEReg:
7075                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7076                                 break;
7077                         case ArgInDoubleSSEReg:
7078                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7079                                 break;
7080                         case ArgValuetypeInReg:
7081                                 for (quad = 0; quad < 2; quad ++) {
7082                                         switch (ainfo->pair_storage [quad]) {
7083                                         case ArgInIReg:
7084                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7085                                                 break;
7086                                         case ArgInFloatSSEReg:
7087                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7088                                                 break;
7089                                         case ArgInDoubleSSEReg:
7090                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7091                                                 break;
7092                                         case ArgNone:
7093                                                 break;
7094                                         default:
7095                                                 g_assert_not_reached ();
7096                                         }
7097                                 }
7098                                 break;
7099                         case ArgValuetypeAddrInIReg:
7100                                 if (ainfo->pair_storage [0] == ArgInIReg)
7101                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7102                                 break;
7103                         default:
7104                                 break;
7105                         }
7106                 } else {
7107                         /* Argument allocated to (non-volatile) register */
7108                         switch (ainfo->storage) {
7109                         case ArgInIReg:
7110                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7111                                 break;
7112                         case ArgOnStack:
7113                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7114                                 break;
7115                         default:
7116                                 g_assert_not_reached ();
7117                         }
7118
7119                         if (ins == cfg->args [0]) {
7120                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7121                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7122                         }
7123                 }
7124         }
7125
7126         if (cfg->method->save_lmf)
7127                 args_clobbered = TRUE;
7128
7129         if (trace) {
7130                 args_clobbered = TRUE;
7131                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7132         }
7133
7134         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7135                 args_clobbered = TRUE;
7136
7137         /*
7138          * Optimize the common case of the first bblock making a call with the same
7139          * arguments as the method. This works because the arguments are still in their
7140          * original argument registers.
7141          * FIXME: Generalize this
7142          */
7143         if (!args_clobbered) {
7144                 MonoBasicBlock *first_bb = cfg->bb_entry;
7145                 MonoInst *next;
7146                 int filter = FILTER_IL_SEQ_POINT;
7147
7148                 next = mono_bb_first_inst (first_bb, filter);
7149                 if (!next && first_bb->next_bb) {
7150                         first_bb = first_bb->next_bb;
7151                         next = mono_bb_first_inst (first_bb, filter);
7152                 }
7153
7154                 if (first_bb->in_count > 1)
7155                         next = NULL;
7156
7157                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7158                         ArgInfo *ainfo = cinfo->args + i;
7159                         gboolean match = FALSE;
7160
7161                         ins = cfg->args [i];
7162                         if (ins->opcode != OP_REGVAR) {
7163                                 switch (ainfo->storage) {
7164                                 case ArgInIReg: {
7165                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7166                                                 if (next->dreg == ainfo->reg) {
7167                                                         NULLIFY_INS (next);
7168                                                         match = TRUE;
7169                                                 } else {
7170                                                         next->opcode = OP_MOVE;
7171                                                         next->sreg1 = ainfo->reg;
7172                                                         /* Only continue if the instruction doesn't change argument regs */
7173                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7174                                                                 match = TRUE;
7175                                                 }
7176                                         }
7177                                         break;
7178                                 }
7179                                 default:
7180                                         break;
7181                                 }
7182                         } else {
7183                                 /* Argument allocated to (non-volatile) register */
7184                                 switch (ainfo->storage) {
7185                                 case ArgInIReg:
7186                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7187                                                 NULLIFY_INS (next);
7188                                                 match = TRUE;
7189                                         }
7190                                         break;
7191                                 default:
7192                                         break;
7193                                 }
7194                         }
7195
7196                         if (match) {
7197                                 next = mono_inst_next (next, filter);
7198                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7199                                 if (!next)
7200                                         break;
7201                         }
7202                 }
7203         }
7204
7205         if (cfg->gen_seq_points_debug_data) {
7206                 MonoInst *info_var = cfg->arch.seq_point_info_var;
7207
7208                 /* Initialize seq_point_info_var */
7209                 if (cfg->compile_aot) {
7210                         /* Initialize the variable from a GOT slot */
7211                         /* Same as OP_AOTCONST */
7212                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7213                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7214                         g_assert (info_var->opcode == OP_REGOFFSET);
7215                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7216                 }
7217
7218                 /* Initialize ss_trigger_page_var */
7219                 ins = cfg->arch.ss_trigger_page_var;
7220
7221                 g_assert (ins->opcode == OP_REGOFFSET);
7222
7223                 if (cfg->compile_aot) {
7224                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7225                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_trigger_page), 8);
7226                 } else {
7227                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
7228                 }
7229                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7230         }
7231
7232         cfg->code_len = code - cfg->native_code;
7233
7234         g_assert (cfg->code_len < cfg->code_size);
7235
7236         return code;
7237 }
7238
7239 void
7240 mono_arch_emit_epilog (MonoCompile *cfg)
7241 {
7242         MonoMethod *method = cfg->method;
7243         int quad, i;
7244         guint8 *code;
7245         int max_epilog_size;
7246         CallInfo *cinfo;
7247         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7248         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7249
7250         max_epilog_size = get_max_epilog_size (cfg);
7251
7252         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7253                 cfg->code_size *= 2;
7254                 cfg->native_code = mono_realloc_native_code (cfg);
7255                 cfg->stat_code_reallocs++;
7256         }
7257         code = cfg->native_code + cfg->code_len;
7258
7259         cfg->has_unwind_info_for_epilog = TRUE;
7260
7261         /* Mark the start of the epilog */
7262         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7263
7264         /* Save the uwind state which is needed by the out-of-line code */
7265         mono_emit_unwind_op_remember_state (cfg, code);
7266
7267         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7268                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7269
7270         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7271
7272         if (method->save_lmf) {
7273                 /* check if we need to restore protection of the stack after a stack overflow */
7274                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7275                         guint8 *patch;
7276                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7277                         /* we load the value in a separate instruction: this mechanism may be
7278                          * used later as a safer way to do thread interruption
7279                          */
7280                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7281                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7282                         patch = code;
7283                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7284                         /* note that the call trampoline will preserve eax/edx */
7285                         x86_call_reg (code, X86_ECX);
7286                         x86_patch (patch, code);
7287                 } else {
7288                         /* FIXME: maybe save the jit tls in the prolog */
7289                 }
7290                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7291                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7292                 }
7293         }
7294
7295         /* Restore callee saved regs */
7296         for (i = 0; i < AMD64_NREG; ++i) {
7297                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7298                         /* Restore only used_int_regs, not arch.saved_iregs */
7299                         if (cfg->used_int_regs & (1 << i)) {
7300                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7301                                 mono_emit_unwind_op_same_value (cfg, code, i);
7302                                 async_exc_point (code);
7303                         }
7304                         save_area_offset += 8;
7305                 }
7306         }
7307
7308         /* Load returned vtypes into registers if needed */
7309         cinfo = cfg->arch.cinfo;
7310         if (cinfo->ret.storage == ArgValuetypeInReg) {
7311                 ArgInfo *ainfo = &cinfo->ret;
7312                 MonoInst *inst = cfg->ret;
7313
7314                 for (quad = 0; quad < 2; quad ++) {
7315                         switch (ainfo->pair_storage [quad]) {
7316                         case ArgInIReg:
7317                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7318                                 break;
7319                         case ArgInFloatSSEReg:
7320                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7321                                 break;
7322                         case ArgInDoubleSSEReg:
7323                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7324                                 break;
7325                         case ArgNone:
7326                                 break;
7327                         default:
7328                                 g_assert_not_reached ();
7329                         }
7330                 }
7331         }
7332
7333         if (cfg->arch.omit_fp) {
7334                 if (cfg->arch.stack_alloc_size) {
7335                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7336                 }
7337         } else {
7338                 amd64_leave (code);
7339                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7340         }
7341         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7342         async_exc_point (code);
7343         amd64_ret (code);
7344
7345         /* Restore the unwind state to be the same as before the epilog */
7346         mono_emit_unwind_op_restore_state (cfg, code);
7347
7348         cfg->code_len = code - cfg->native_code;
7349
7350         g_assert (cfg->code_len < cfg->code_size);
7351 }
7352
7353 void
7354 mono_arch_emit_exceptions (MonoCompile *cfg)
7355 {
7356         MonoJumpInfo *patch_info;
7357         int nthrows, i;
7358         guint8 *code;
7359         MonoClass *exc_classes [16];
7360         guint8 *exc_throw_start [16], *exc_throw_end [16];
7361         guint32 code_size = 0;
7362
7363         /* Compute needed space */
7364         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7365                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7366                         code_size += 40;
7367                 if (patch_info->type == MONO_PATCH_INFO_R8)
7368                         code_size += 8 + 15; /* sizeof (double) + alignment */
7369                 if (patch_info->type == MONO_PATCH_INFO_R4)
7370                         code_size += 4 + 15; /* sizeof (float) + alignment */
7371                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7372                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7373         }
7374
7375 #ifdef __native_client_codegen__
7376         /* Give us extra room on Native Client.  This could be   */
7377         /* more carefully calculated, but bundle alignment makes */
7378         /* it much trickier, so *2 like other places is good.    */
7379         code_size *= 2;
7380 #endif
7381
7382         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7383                 cfg->code_size *= 2;
7384                 cfg->native_code = mono_realloc_native_code (cfg);
7385                 cfg->stat_code_reallocs++;
7386         }
7387
7388         code = cfg->native_code + cfg->code_len;
7389
7390         /* add code to raise exceptions */
7391         nthrows = 0;
7392         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7393                 switch (patch_info->type) {
7394                 case MONO_PATCH_INFO_EXC: {
7395                         MonoClass *exc_class;
7396                         guint8 *buf, *buf2;
7397                         guint32 throw_ip;
7398
7399                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7400
7401                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7402                         g_assert (exc_class);
7403                         throw_ip = patch_info->ip.i;
7404
7405                         //x86_breakpoint (code);
7406                         /* Find a throw sequence for the same exception class */
7407                         for (i = 0; i < nthrows; ++i)
7408                                 if (exc_classes [i] == exc_class)
7409                                         break;
7410                         if (i < nthrows) {
7411                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7412                                 x86_jump_code (code, exc_throw_start [i]);
7413                                 patch_info->type = MONO_PATCH_INFO_NONE;
7414                         }
7415                         else {
7416                                 buf = code;
7417                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7418                                 buf2 = code;
7419
7420                                 if (nthrows < 16) {
7421                                         exc_classes [nthrows] = exc_class;
7422                                         exc_throw_start [nthrows] = code;
7423                                 }
7424                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7425
7426                                 patch_info->type = MONO_PATCH_INFO_NONE;
7427
7428                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7429
7430                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7431                                 while (buf < buf2)
7432                                         x86_nop (buf);
7433
7434                                 if (nthrows < 16) {
7435                                         exc_throw_end [nthrows] = code;
7436                                         nthrows ++;
7437                                 }
7438                         }
7439                         break;
7440                 }
7441                 default:
7442                         /* do nothing */
7443                         break;
7444                 }
7445                 g_assert(code < cfg->native_code + cfg->code_size);
7446         }
7447
7448         /* Handle relocations with RIP relative addressing */
7449         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7450                 gboolean remove = FALSE;
7451                 guint8 *orig_code = code;
7452
7453                 switch (patch_info->type) {
7454                 case MONO_PATCH_INFO_R8:
7455                 case MONO_PATCH_INFO_R4: {
7456                         guint8 *pos, *patch_pos;
7457                         guint32 target_pos;
7458
7459                         /* The SSE opcodes require a 16 byte alignment */
7460 #if defined(__default_codegen__)
7461                         code = (guint8*)ALIGN_TO (code, 16);
7462 #elif defined(__native_client_codegen__)
7463                         {
7464                                 /* Pad this out with HLT instructions  */
7465                                 /* or we can get garbage bytes emitted */
7466                                 /* which will fail validation          */
7467                                 guint8 *aligned_code;
7468                                 /* extra align to make room for  */
7469                                 /* mov/push below                      */
7470                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7471                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7472                                 /* The technique of hiding data in an  */
7473                                 /* instruction has a problem here: we  */
7474                                 /* need the data aligned to a 16-byte  */
7475                                 /* boundary but the instruction cannot */
7476                                 /* cross the bundle boundary. so only  */
7477                                 /* odd multiples of 16 can be used     */
7478                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7479                                         aligned_code += 16;
7480                                 }
7481                                 while (code < aligned_code) {
7482                                         *(code++) = 0xf4; /* hlt */
7483                                 }
7484                         }
7485 #endif
7486
7487                         pos = cfg->native_code + patch_info->ip.i;
7488                         if (IS_REX (pos [1])) {
7489                                 patch_pos = pos + 5;
7490                                 target_pos = code - pos - 9;
7491                         }
7492                         else {
7493                                 patch_pos = pos + 4;
7494                                 target_pos = code - pos - 8;
7495                         }
7496
7497                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7498 #ifdef __native_client_codegen__
7499                                 /* Hide 64-bit data in a         */
7500                                 /* "mov imm64, r11" instruction. */
7501                                 /* write it before the start of  */
7502                                 /* the data*/
7503                                 *(code-2) = 0x49; /* prefix      */
7504                                 *(code-1) = 0xbb; /* mov X, %r11 */
7505 #endif
7506                                 *(double*)code = *(double*)patch_info->data.target;
7507                                 code += sizeof (double);
7508                         } else {
7509 #ifdef __native_client_codegen__
7510                                 /* Hide 32-bit data in a        */
7511                                 /* "push imm32" instruction.    */
7512                                 *(code-1) = 0x68; /* push */
7513 #endif
7514                                 *(float*)code = *(float*)patch_info->data.target;
7515                                 code += sizeof (float);
7516                         }
7517
7518                         *(guint32*)(patch_pos) = target_pos;
7519
7520                         remove = TRUE;
7521                         break;
7522                 }
7523                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7524                         guint8 *pos;
7525
7526                         if (cfg->compile_aot)
7527                                 continue;
7528
7529                         /*loading is faster against aligned addresses.*/
7530                         code = (guint8*)ALIGN_TO (code, 8);
7531                         memset (orig_code, 0, code - orig_code);
7532
7533                         pos = cfg->native_code + patch_info->ip.i;
7534
7535                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7536                         if (IS_REX (pos [1]))
7537                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7538                         else
7539                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7540
7541                         *(gpointer*)code = (gpointer)patch_info->data.target;
7542                         code += sizeof (gpointer);
7543
7544                         remove = TRUE;
7545                         break;
7546                 }
7547                 default:
7548                         break;
7549                 }
7550
7551                 if (remove) {
7552                         if (patch_info == cfg->patch_info)
7553                                 cfg->patch_info = patch_info->next;
7554                         else {
7555                                 MonoJumpInfo *tmp;
7556
7557                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7558                                         ;
7559                                 tmp->next = patch_info->next;
7560                         }
7561                 }
7562                 g_assert (code < cfg->native_code + cfg->code_size);
7563         }
7564
7565         cfg->code_len = code - cfg->native_code;
7566
7567         g_assert (cfg->code_len < cfg->code_size);
7568
7569 }
7570
7571 #endif /* DISABLE_JIT */
7572
7573 void*
7574 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7575 {
7576         guchar *code = p;
7577         MonoMethodSignature *sig;
7578         MonoInst *inst;
7579         int i, n, stack_area = 0;
7580
7581         /* Keep this in sync with mono_arch_get_argument_info */
7582
7583         if (enable_arguments) {
7584                 /* Allocate a new area on the stack and save arguments there */
7585                 sig = mono_method_signature (cfg->method);
7586
7587                 n = sig->param_count + sig->hasthis;
7588
7589                 stack_area = ALIGN_TO (n * 8, 16);
7590
7591                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7592
7593                 for (i = 0; i < n; ++i) {
7594                         inst = cfg->args [i];
7595
7596                         if (inst->opcode == OP_REGVAR)
7597                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7598                         else {
7599                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7600                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7601                         }
7602                 }
7603         }
7604
7605         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7606         amd64_set_reg_template (code, AMD64_ARG_REG1);
7607         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7608         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7609
7610         if (enable_arguments)
7611                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7612
7613         return code;
7614 }
7615
7616 enum {
7617         SAVE_NONE,
7618         SAVE_STRUCT,
7619         SAVE_EAX,
7620         SAVE_EAX_EDX,
7621         SAVE_XMM
7622 };
7623
7624 void*
7625 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7626 {
7627         guchar *code = p;
7628         int save_mode = SAVE_NONE;
7629         MonoMethod *method = cfg->method;
7630         MonoType *ret_type = mini_get_underlying_type (cfg, mono_method_signature (method)->ret);
7631         int i;
7632
7633         switch (ret_type->type) {
7634         case MONO_TYPE_VOID:
7635                 /* special case string .ctor icall */
7636                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7637                         save_mode = SAVE_EAX;
7638                 else
7639                         save_mode = SAVE_NONE;
7640                 break;
7641         case MONO_TYPE_I8:
7642         case MONO_TYPE_U8:
7643                 save_mode = SAVE_EAX;
7644                 break;
7645         case MONO_TYPE_R4:
7646         case MONO_TYPE_R8:
7647                 save_mode = SAVE_XMM;
7648                 break;
7649         case MONO_TYPE_GENERICINST:
7650                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7651                         save_mode = SAVE_EAX;
7652                         break;
7653                 }
7654                 /* Fall through */
7655         case MONO_TYPE_VALUETYPE:
7656                 save_mode = SAVE_STRUCT;
7657                 break;
7658         default:
7659                 save_mode = SAVE_EAX;
7660                 break;
7661         }
7662
7663         /* Save the result and copy it into the proper argument register */
7664         switch (save_mode) {
7665         case SAVE_EAX:
7666                 amd64_push_reg (code, AMD64_RAX);
7667                 /* Align stack */
7668                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7669                 if (enable_arguments)
7670                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7671                 break;
7672         case SAVE_STRUCT:
7673                 /* FIXME: */
7674                 if (enable_arguments)
7675                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7676                 break;
7677         case SAVE_XMM:
7678                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7679                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7680                 /* Align stack */
7681                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7682                 /*
7683                  * The result is already in the proper argument register so no copying
7684                  * needed.
7685                  */
7686                 break;
7687         case SAVE_NONE:
7688                 break;
7689         default:
7690                 g_assert_not_reached ();
7691         }
7692
7693         /* Set %al since this is a varargs call */
7694         if (save_mode == SAVE_XMM)
7695                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7696         else
7697                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7698
7699         if (preserve_argument_registers) {
7700                 for (i = 0; i < PARAM_REGS; ++i)
7701                         amd64_push_reg (code, param_regs [i]);
7702         }
7703
7704         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7705         amd64_set_reg_template (code, AMD64_ARG_REG1);
7706         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7707
7708         if (preserve_argument_registers) {
7709                 for (i = PARAM_REGS - 1; i >= 0; --i)
7710                         amd64_pop_reg (code, param_regs [i]);
7711         }
7712
7713         /* Restore result */
7714         switch (save_mode) {
7715         case SAVE_EAX:
7716                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7717                 amd64_pop_reg (code, AMD64_RAX);
7718                 break;
7719         case SAVE_STRUCT:
7720                 /* FIXME: */
7721                 break;
7722         case SAVE_XMM:
7723                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7724                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7725                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7726                 break;
7727         case SAVE_NONE:
7728                 break;
7729         default:
7730                 g_assert_not_reached ();
7731         }
7732
7733         return code;
7734 }
7735
7736 void
7737 mono_arch_flush_icache (guint8 *code, gint size)
7738 {
7739         /* Not needed */
7740 }
7741
7742 void
7743 mono_arch_flush_register_windows (void)
7744 {
7745 }
7746
7747 gboolean
7748 mono_arch_is_inst_imm (gint64 imm)
7749 {
7750         return amd64_is_imm32 (imm);
7751 }
7752
7753 /*
7754  * Determine whenever the trap whose info is in SIGINFO is caused by
7755  * integer overflow.
7756  */
7757 gboolean
7758 mono_arch_is_int_overflow (void *sigctx, void *info)
7759 {
7760         MonoContext ctx;
7761         guint8* rip;
7762         int reg;
7763         gint64 value;
7764
7765         mono_sigctx_to_monoctx (sigctx, &ctx);
7766
7767         rip = (guint8*)ctx.rip;
7768
7769         if (IS_REX (rip [0])) {
7770                 reg = amd64_rex_b (rip [0]);
7771                 rip ++;
7772         }
7773         else
7774                 reg = 0;
7775
7776         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7777                 /* idiv REG */
7778                 reg += x86_modrm_rm (rip [1]);
7779
7780                 switch (reg) {
7781                 case AMD64_RAX:
7782                         value = ctx.rax;
7783                         break;
7784                 case AMD64_RBX:
7785                         value = ctx.rbx;
7786                         break;
7787                 case AMD64_RCX:
7788                         value = ctx.rcx;
7789                         break;
7790                 case AMD64_RDX:
7791                         value = ctx.rdx;
7792                         break;
7793                 case AMD64_RBP:
7794                         value = ctx.rbp;
7795                         break;
7796                 case AMD64_RSP:
7797                         value = ctx.rsp;
7798                         break;
7799                 case AMD64_RSI:
7800                         value = ctx.rsi;
7801                         break;
7802                 case AMD64_RDI:
7803                         value = ctx.rdi;
7804                         break;
7805                 case AMD64_R12:
7806                         value = ctx.r12;
7807                         break;
7808                 case AMD64_R13:
7809                         value = ctx.r13;
7810                         break;
7811                 case AMD64_R14:
7812                         value = ctx.r14;
7813                         break;
7814                 case AMD64_R15:
7815                         value = ctx.r15;
7816                         break;
7817                 default:
7818                         g_assert_not_reached ();
7819                         reg = -1;
7820                 }
7821
7822                 if (value == -1)
7823                         return TRUE;
7824         }
7825
7826         return FALSE;
7827 }
7828
7829 guint32
7830 mono_arch_get_patch_offset (guint8 *code)
7831 {
7832         return 3;
7833 }
7834
7835 /**
7836  * mono_breakpoint_clean_code:
7837  *
7838  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7839  * breakpoints in the original code, they are removed in the copy.
7840  *
7841  * Returns TRUE if no sw breakpoint was present.
7842  */
7843 gboolean
7844 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7845 {
7846         /*
7847          * If method_start is non-NULL we need to perform bound checks, since we access memory
7848          * at code - offset we could go before the start of the method and end up in a different
7849          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7850          * instead.
7851          */
7852         if (!method_start || code - offset >= method_start) {
7853                 memcpy (buf, code - offset, size);
7854         } else {
7855                 int diff = code - method_start;
7856                 memset (buf, 0, size);
7857                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7858         }
7859         return TRUE;
7860 }
7861
7862 #if defined(__native_client_codegen__)
7863 /* For membase calls, we want the base register. for Native Client,  */
7864 /* all indirect calls have the following sequence with the given sizes: */
7865 /* mov %eXX,%eXX                                [2-3]   */
7866 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7867 /* and $0xffffffffffffffe0,%r11d                [4]     */
7868 /* add %r15,%r11                                [3]     */
7869 /* callq *%r11                                  [3]     */
7870
7871
7872 /* Determine if code points to a NaCl call-through-register sequence, */
7873 /* (i.e., the last 3 instructions listed above) */
7874 int
7875 is_nacl_call_reg_sequence(guint8* code)
7876 {
7877         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7878                                "\x4d\x03\xdf"     /* add */
7879                                "\x41\xff\xd3";   /* call */
7880         return memcmp(code, sequence, 10) == 0;
7881 }
7882
7883 /* Determine if code points to the first opcode of the mov membase component */
7884 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7885 /* (there could be a REX prefix before the opcode but it is ignored) */
7886 static int
7887 is_nacl_indirect_call_membase_sequence(guint8* code)
7888 {
7889                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7890         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7891                /* and that src reg = dest reg */
7892                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7893                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7894                IS_REX(code[2]) &&
7895                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7896                /* and has dst of r11 and base of r15 */
7897                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
7898                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
7899 }
7900 #endif /* __native_client_codegen__ */
7901
7902 int
7903 mono_arch_get_this_arg_reg (guint8 *code)
7904 {
7905         return AMD64_ARG_REG1;
7906 }
7907
7908 gpointer
7909 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7910 {
7911         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7912 }
7913
7914 #define MAX_ARCH_DELEGATE_PARAMS 10
7915
7916 static gpointer
7917 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
7918 {
7919         guint8 *code, *start;
7920         int i;
7921
7922         if (has_target) {
7923                 start = code = mono_global_codeman_reserve (64);
7924
7925                 /* Replace the this argument with the target */
7926                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7927                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7928                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7929
7930                 g_assert ((code - start) < 64);
7931         } else {
7932                 start = code = mono_global_codeman_reserve (64);
7933
7934                 if (param_count == 0) {
7935                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7936                 } else {
7937                         /* We have to shift the arguments left */
7938                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7939                         for (i = 0; i < param_count; ++i) {
7940 #ifdef HOST_WIN32
7941                                 if (i < 3)
7942                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7943                                 else
7944                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7945 #else
7946                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7947 #endif
7948                         }
7949
7950                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7951                 }
7952                 g_assert ((code - start) < 64);
7953         }
7954
7955         nacl_global_codeman_validate (&start, 64, &code);
7956
7957         if (code_len)
7958                 *code_len = code - start;
7959
7960         if (mono_jit_map_is_enabled ()) {
7961                 char *buff;
7962                 if (has_target)
7963                         buff = (char*)"delegate_invoke_has_target";
7964                 else
7965                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7966                 mono_emit_jit_tramp (start, code - start, buff);
7967                 if (!has_target)
7968                         g_free (buff);
7969         }
7970         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7971
7972         return start;
7973 }
7974
7975 /*
7976  * mono_arch_get_delegate_invoke_impls:
7977  *
7978  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7979  * trampolines.
7980  */
7981 GSList*
7982 mono_arch_get_delegate_invoke_impls (void)
7983 {
7984         GSList *res = NULL;
7985         guint8 *code;
7986         guint32 code_len;
7987         int i;
7988         char *tramp_name;
7989
7990         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7991         res = g_slist_prepend (res, mono_tramp_info_create ("delegate_invoke_impl_has_target", code, code_len, NULL, NULL));
7992
7993         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7994                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7995                 tramp_name = g_strdup_printf ("delegate_invoke_impl_target_%d", i);
7996                 res = g_slist_prepend (res, mono_tramp_info_create (tramp_name, code, code_len, NULL, NULL));
7997                 g_free (tramp_name);
7998         }
7999
8000         return res;
8001 }
8002
8003 gpointer
8004 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8005 {
8006         guint8 *code, *start;
8007         int i;
8008
8009         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8010                 return NULL;
8011
8012         /* FIXME: Support more cases */
8013         if (MONO_TYPE_ISSTRUCT (mini_replace_type (sig->ret)))
8014                 return NULL;
8015
8016         if (has_target) {
8017                 static guint8* cached = NULL;
8018
8019                 if (cached)
8020                         return cached;
8021
8022                 if (mono_aot_only)
8023                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8024                 else
8025                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
8026
8027                 mono_memory_barrier ();
8028
8029                 cached = start;
8030         } else {
8031                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8032                 for (i = 0; i < sig->param_count; ++i)
8033                         if (!mono_is_regsize_var (sig->params [i]))
8034                                 return NULL;
8035                 if (sig->param_count > 4)
8036                         return NULL;
8037
8038                 code = cache [sig->param_count];
8039                 if (code)
8040                         return code;
8041
8042                 if (mono_aot_only) {
8043                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8044                         start = mono_aot_get_trampoline (name);
8045                         g_free (name);
8046                 } else {
8047                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
8048                 }
8049
8050                 mono_memory_barrier ();
8051
8052                 cache [sig->param_count] = start;
8053         }
8054
8055         return start;
8056 }
8057
8058 gpointer
8059 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8060 {
8061         guint8 *code, *start;
8062         int size = 20;
8063
8064         start = code = mono_global_codeman_reserve (size);
8065
8066         /* Replace the this argument with the target */
8067         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8068         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8069
8070         if (load_imt_reg) {
8071                 /* Load the IMT reg */
8072                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8073         }
8074
8075         /* Load the vtable */
8076         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8077         amd64_jump_membase (code, AMD64_RAX, offset);
8078         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8079
8080         return start;
8081 }
8082
8083 void
8084 mono_arch_finish_init (void)
8085 {
8086 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8087         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8088 #endif
8089 }
8090
8091 void
8092 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8093 {
8094 }
8095
8096 #if defined(__default_codegen__)
8097 #define CMP_SIZE (6 + 1)
8098 #define CMP_REG_REG_SIZE (4 + 1)
8099 #define BR_SMALL_SIZE 2
8100 #define BR_LARGE_SIZE 6
8101 #define MOV_REG_IMM_SIZE 10
8102 #define MOV_REG_IMM_32BIT_SIZE 6
8103 #define JUMP_REG_SIZE (2 + 1)
8104 #elif defined(__native_client_codegen__)
8105 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8106 #define CMP_SIZE ((6 + 1) * 2 - 1)
8107 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8108 #define BR_SMALL_SIZE (2 * 2 - 1)
8109 #define BR_LARGE_SIZE (6 * 2 - 1)
8110 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8111 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8112 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8113 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8114 /* Jump membase's size is large and unpredictable    */
8115 /* in native client, just pad it out a whole bundle. */
8116 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8117 #endif
8118
8119 static int
8120 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8121 {
8122         int i, distance = 0;
8123         for (i = start; i < target; ++i)
8124                 distance += imt_entries [i]->chunk_size;
8125         return distance;
8126 }
8127
8128 /*
8129  * LOCKING: called with the domain lock held
8130  */
8131 gpointer
8132 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8133         gpointer fail_tramp)
8134 {
8135         int i;
8136         int size = 0;
8137         guint8 *code, *start;
8138         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8139
8140         for (i = 0; i < count; ++i) {
8141                 MonoIMTCheckItem *item = imt_entries [i];
8142                 if (item->is_equals) {
8143                         if (item->check_target_idx) {
8144                                 if (!item->compare_done) {
8145                                         if (amd64_is_imm32 (item->key))
8146                                                 item->chunk_size += CMP_SIZE;
8147                                         else
8148                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8149                                 }
8150                                 if (item->has_target_code) {
8151                                         item->chunk_size += MOV_REG_IMM_SIZE;
8152                                 } else {
8153                                         if (vtable_is_32bit)
8154                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8155                                         else
8156                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8157 #ifdef __native_client_codegen__
8158                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8159 #endif
8160                                 }
8161                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8162                         } else {
8163                                 if (fail_tramp) {
8164                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8165                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8166                                 } else {
8167                                         if (vtable_is_32bit)
8168                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8169                                         else
8170                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8171                                         item->chunk_size += JUMP_REG_SIZE;
8172                                         /* with assert below:
8173                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8174                                          */
8175 #ifdef __native_client_codegen__
8176                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8177 #endif
8178                                 }
8179                         }
8180                 } else {
8181                         if (amd64_is_imm32 (item->key))
8182                                 item->chunk_size += CMP_SIZE;
8183                         else
8184                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8185                         item->chunk_size += BR_LARGE_SIZE;
8186                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8187                 }
8188                 size += item->chunk_size;
8189         }
8190 #if defined(__native_client__) && defined(__native_client_codegen__)
8191         /* In Native Client, we don't re-use thunks, allocate from the */
8192         /* normal code manager paths. */
8193         code = mono_domain_code_reserve (domain, size);
8194 #else
8195         if (fail_tramp)
8196                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
8197         else
8198                 code = mono_domain_code_reserve (domain, size);
8199 #endif
8200         start = code;
8201         for (i = 0; i < count; ++i) {
8202                 MonoIMTCheckItem *item = imt_entries [i];
8203                 item->code_target = code;
8204                 if (item->is_equals) {
8205                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8206
8207                         if (item->check_target_idx || fail_case) {
8208                                 if (!item->compare_done || fail_case) {
8209                                         if (amd64_is_imm32 (item->key))
8210                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8211                                         else {
8212                                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8213                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8214                                         }
8215                                 }
8216                                 item->jmp_code = code;
8217                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8218                                 if (item->has_target_code) {
8219                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8220                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8221                                 } else {
8222                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8223                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8224                                 }
8225
8226                                 if (fail_case) {
8227                                         amd64_patch (item->jmp_code, code);
8228                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8229                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8230                                         item->jmp_code = NULL;
8231                                 }
8232                         } else {
8233                                 /* enable the commented code to assert on wrong method */
8234 #if 0
8235                                 if (amd64_is_imm32 (item->key))
8236                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8237                                 else {
8238                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8239                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8240                                 }
8241                                 item->jmp_code = code;
8242                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8243                                 /* See the comment below about R10 */
8244                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8245                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8246                                 amd64_patch (item->jmp_code, code);
8247                                 amd64_breakpoint (code);
8248                                 item->jmp_code = NULL;
8249 #else
8250                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8251                                    needs to be preserved.  R10 needs
8252                                    to be preserved for calls which
8253                                    require a runtime generic context,
8254                                    but interface calls don't. */
8255                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8256                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8257 #endif
8258                         }
8259                 } else {
8260                         if (amd64_is_imm32 (item->key))
8261                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8262                         else {
8263                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8264                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8265                         }
8266                         item->jmp_code = code;
8267                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8268                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8269                         else
8270                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8271                 }
8272                 g_assert (code - item->code_target <= item->chunk_size);
8273         }
8274         /* patch the branches to get to the target items */
8275         for (i = 0; i < count; ++i) {
8276                 MonoIMTCheckItem *item = imt_entries [i];
8277                 if (item->jmp_code) {
8278                         if (item->check_target_idx) {
8279                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8280                         }
8281                 }
8282         }
8283
8284         if (!fail_tramp)
8285                 mono_stats.imt_thunks_size += code - start;
8286         g_assert (code - start <= size);
8287
8288         nacl_domain_code_validate(domain, &start, size, &code);
8289         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8290
8291         return start;
8292 }
8293
8294 MonoMethod*
8295 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8296 {
8297         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8298 }
8299
8300 MonoVTable*
8301 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8302 {
8303         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8304 }
8305
8306 GSList*
8307 mono_arch_get_cie_program (void)
8308 {
8309         GSList *l = NULL;
8310
8311         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8312         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8313
8314         return l;
8315 }
8316
8317 #ifndef DISABLE_JIT
8318
8319 MonoInst*
8320 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8321 {
8322         MonoInst *ins = NULL;
8323         int opcode = 0;
8324
8325         if (cmethod->klass == mono_defaults.math_class) {
8326                 if (strcmp (cmethod->name, "Sin") == 0) {
8327                         opcode = OP_SIN;
8328                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8329                         opcode = OP_COS;
8330                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8331                         opcode = OP_SQRT;
8332                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8333                         opcode = OP_ABS;
8334                 }
8335
8336                 if (opcode && fsig->param_count == 1) {
8337                         MONO_INST_NEW (cfg, ins, opcode);
8338                         ins->type = STACK_R8;
8339                         ins->dreg = mono_alloc_freg (cfg);
8340                         ins->sreg1 = args [0]->dreg;
8341                         MONO_ADD_INS (cfg->cbb, ins);
8342                 }
8343
8344                 opcode = 0;
8345                 if (cfg->opt & MONO_OPT_CMOV) {
8346                         if (strcmp (cmethod->name, "Min") == 0) {
8347                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8348                                         opcode = OP_IMIN;
8349                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8350                                         opcode = OP_IMIN_UN;
8351                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8352                                         opcode = OP_LMIN;
8353                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8354                                         opcode = OP_LMIN_UN;
8355                         } else if (strcmp (cmethod->name, "Max") == 0) {
8356                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8357                                         opcode = OP_IMAX;
8358                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8359                                         opcode = OP_IMAX_UN;
8360                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8361                                         opcode = OP_LMAX;
8362                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8363                                         opcode = OP_LMAX_UN;
8364                         }
8365                 }
8366
8367                 if (opcode && fsig->param_count == 2) {
8368                         MONO_INST_NEW (cfg, ins, opcode);
8369                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8370                         ins->dreg = mono_alloc_ireg (cfg);
8371                         ins->sreg1 = args [0]->dreg;
8372                         ins->sreg2 = args [1]->dreg;
8373                         MONO_ADD_INS (cfg->cbb, ins);
8374                 }
8375
8376 #if 0
8377                 /* OP_FREM is not IEEE compatible */
8378                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8379                         MONO_INST_NEW (cfg, ins, OP_FREM);
8380                         ins->inst_i0 = args [0];
8381                         ins->inst_i1 = args [1];
8382                 }
8383 #endif
8384         }
8385
8386         return ins;
8387 }
8388 #endif
8389
8390 gboolean
8391 mono_arch_print_tree (MonoInst *tree, int arity)
8392 {
8393         return 0;
8394 }
8395
8396 #define _CTX_REG(ctx,fld,i) ((&ctx->fld)[i])
8397
8398 mgreg_t
8399 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8400 {
8401         switch (reg) {
8402         case AMD64_RCX: return ctx->rcx;
8403         case AMD64_RDX: return ctx->rdx;
8404         case AMD64_RBX: return ctx->rbx;
8405         case AMD64_RBP: return ctx->rbp;
8406         case AMD64_RSP: return ctx->rsp;
8407         default:
8408                 return _CTX_REG (ctx, rax, reg);
8409         }
8410 }
8411
8412 void
8413 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8414 {
8415         switch (reg) {
8416         case AMD64_RCX:
8417                 ctx->rcx = val;
8418                 break;
8419         case AMD64_RDX:
8420                 ctx->rdx = val;
8421                 break;
8422         case AMD64_RBX:
8423                 ctx->rbx = val;
8424                 break;
8425         case AMD64_RBP:
8426                 ctx->rbp = val;
8427                 break;
8428         case AMD64_RSP:
8429                 ctx->rsp = val;
8430                 break;
8431         default:
8432                 _CTX_REG (ctx, rax, reg) = val;
8433         }
8434 }
8435
8436 gpointer
8437 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8438 {
8439         gpointer *sp, old_value;
8440         char *bp;
8441
8442         /*Load the spvar*/
8443         bp = MONO_CONTEXT_GET_BP (ctx);
8444         sp = *(gpointer*)(bp + clause->exvar_offset);
8445
8446         old_value = *sp;
8447         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8448                 return old_value;
8449
8450         *sp = new_value;
8451
8452         return old_value;
8453 }
8454
8455 /*
8456  * mono_arch_emit_load_aotconst:
8457  *
8458  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8459  * TARGET from the mscorlib GOT in full-aot code.
8460  * On AMD64, the result is placed into R11.
8461  */
8462 guint8*
8463 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
8464 {
8465         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8466         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8467
8468         return code;
8469 }
8470
8471 /*
8472  * mono_arch_get_trampolines:
8473  *
8474  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8475  * for AOT.
8476  */
8477 GSList *
8478 mono_arch_get_trampolines (gboolean aot)
8479 {
8480         return mono_amd64_get_exception_trampolines (aot);
8481 }
8482
8483 /* Soft Debug support */
8484 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8485
8486 /*
8487  * mono_arch_set_breakpoint:
8488  *
8489  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8490  * The location should contain code emitted by OP_SEQ_POINT.
8491  */
8492 void
8493 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8494 {
8495         guint8 *code = ip;
8496         guint8 *orig_code = code;
8497
8498         if (ji->from_aot) {
8499                 guint32 native_offset = ip - (guint8*)ji->code_start;
8500                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8501
8502                 g_assert (info->bp_addrs [native_offset] == 0);
8503                 info->bp_addrs [native_offset] = bp_trigger_page;
8504         } else {
8505                 /*
8506                  * In production, we will use int3 (has to fix the size in the md
8507                  * file). But that could confuse gdb, so during development, we emit a SIGSEGV
8508                  * instead.
8509                  */
8510                 g_assert (code [0] == 0x90);
8511                 if (breakpoint_size == 8) {
8512                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
8513                 } else {
8514                         amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
8515                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
8516                 }
8517
8518                 g_assert (code - orig_code == breakpoint_size);
8519         }
8520 }
8521
8522 /*
8523  * mono_arch_clear_breakpoint:
8524  *
8525  *   Clear the breakpoint at IP.
8526  */
8527 void
8528 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8529 {
8530         guint8 *code = ip;
8531         int i;
8532
8533         if (ji->from_aot) {
8534                 guint32 native_offset = ip - (guint8*)ji->code_start;
8535                 SeqPointInfo *info = mono_arch_get_seq_point_info (mono_domain_get (), ji->code_start);
8536
8537                 g_assert (info->bp_addrs [native_offset] == 0);
8538                 info->bp_addrs [native_offset] = info;
8539         } else {
8540                 for (i = 0; i < breakpoint_size; ++i)
8541                         x86_nop (code);
8542         }
8543 }
8544
8545 gboolean
8546 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8547 {
8548 #ifdef HOST_WIN32
8549         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8550         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == bp_trigger_page)
8551                 return TRUE;
8552         else
8553                 return FALSE;
8554 #else
8555         siginfo_t* sinfo = (siginfo_t*) info;
8556         /* Sometimes the address is off by 4 */
8557         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
8558                 return TRUE;
8559         else
8560                 return FALSE;
8561 #endif
8562 }
8563
8564 /*
8565  * mono_arch_skip_breakpoint:
8566  *
8567  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8568  * we resume, the instruction is not executed again.
8569  */
8570 void
8571 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8572 {
8573         if (ji->from_aot) {
8574                 /* amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8) */
8575                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 3);
8576         } else {
8577                 MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
8578         }
8579 }
8580
8581 /*
8582  * mono_arch_start_single_stepping:
8583  *
8584  *   Start single stepping.
8585  */
8586 void
8587 mono_arch_start_single_stepping (void)
8588 {
8589         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
8590 }
8591
8592 /*
8593  * mono_arch_stop_single_stepping:
8594  *
8595  *   Stop single stepping.
8596  */
8597 void
8598 mono_arch_stop_single_stepping (void)
8599 {
8600         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
8601 }
8602
8603 /*
8604  * mono_arch_is_single_step_event:
8605  *
8606  *   Return whenever the machine state in SIGCTX corresponds to a single
8607  * step event.
8608  */
8609 gboolean
8610 mono_arch_is_single_step_event (void *info, void *sigctx)
8611 {
8612 #ifdef HOST_WIN32
8613         EXCEPTION_RECORD* einfo = ((EXCEPTION_POINTERS*)info)->ExceptionRecord;
8614         if (einfo->ExceptionCode == EXCEPTION_ACCESS_VIOLATION && (gpointer)einfo->ExceptionInformation [1] == ss_trigger_page)
8615                 return TRUE;
8616         else
8617                 return FALSE;
8618 #else
8619         siginfo_t* sinfo = (siginfo_t*) info;
8620         /* Sometimes the address is off by 4 */
8621         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
8622                 return TRUE;
8623         else
8624                 return FALSE;
8625 #endif
8626 }
8627
8628 /*
8629  * mono_arch_skip_single_step:
8630  *
8631  *   Modify CTX so the ip is placed after the single step trigger instruction,
8632  * we resume, the instruction is not executed again.
8633  */
8634 void
8635 mono_arch_skip_single_step (MonoContext *ctx)
8636 {
8637         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
8638 }
8639
8640 /*
8641  * mono_arch_create_seq_point_info:
8642  *
8643  *   Return a pointer to a data structure which is used by the sequence
8644  * point implementation in AOTed code.
8645  */
8646 gpointer
8647 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8648 {
8649         SeqPointInfo *info;
8650         MonoJitInfo *ji;
8651         int i;
8652
8653         // FIXME: Add a free function
8654
8655         mono_domain_lock (domain);
8656         info = g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8657                                                                 code);
8658         mono_domain_unlock (domain);
8659
8660         if (!info) {
8661                 ji = mono_jit_info_table_find (domain, (char*)code);
8662                 g_assert (ji);
8663
8664                 // FIXME: Optimize the size
8665                 info = g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8666
8667                 info->ss_trigger_page = ss_trigger_page;
8668                 info->bp_trigger_page = bp_trigger_page;
8669                 /* Initialize to a valid address */
8670                 for (i = 0; i < ji->code_size; ++i)
8671                         info->bp_addrs [i] = info;
8672
8673                 mono_domain_lock (domain);
8674                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8675                                                          code, info);
8676                 mono_domain_unlock (domain);
8677         }
8678
8679         return info;
8680 }
8681
8682 void
8683 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8684 {
8685         ext->lmf.previous_lmf = prev_lmf;
8686         /* Mark that this is a MonoLMFExt */
8687         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8688         ext->lmf.rsp = (gssize)ext;
8689 }
8690
8691 #endif
8692
8693 gboolean
8694 mono_arch_opcode_supported (int opcode)
8695 {
8696         switch (opcode) {
8697         case OP_ATOMIC_ADD_I4:
8698         case OP_ATOMIC_ADD_I8:
8699         case OP_ATOMIC_EXCHANGE_I4:
8700         case OP_ATOMIC_EXCHANGE_I8:
8701         case OP_ATOMIC_CAS_I4:
8702         case OP_ATOMIC_CAS_I8:
8703         case OP_ATOMIC_LOAD_I1:
8704         case OP_ATOMIC_LOAD_I2:
8705         case OP_ATOMIC_LOAD_I4:
8706         case OP_ATOMIC_LOAD_I8:
8707         case OP_ATOMIC_LOAD_U1:
8708         case OP_ATOMIC_LOAD_U2:
8709         case OP_ATOMIC_LOAD_U4:
8710         case OP_ATOMIC_LOAD_U8:
8711         case OP_ATOMIC_LOAD_R4:
8712         case OP_ATOMIC_LOAD_R8:
8713         case OP_ATOMIC_STORE_I1:
8714         case OP_ATOMIC_STORE_I2:
8715         case OP_ATOMIC_STORE_I4:
8716         case OP_ATOMIC_STORE_I8:
8717         case OP_ATOMIC_STORE_U1:
8718         case OP_ATOMIC_STORE_U2:
8719         case OP_ATOMIC_STORE_U4:
8720         case OP_ATOMIC_STORE_U8:
8721         case OP_ATOMIC_STORE_R4:
8722         case OP_ATOMIC_STORE_R8:
8723                 return TRUE;
8724         default:
8725                 return FALSE;
8726         }
8727 }