mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27 #include <mono/utils/mono-mmap.h>
  28
  29 #include "trace.h"
  30 #include "ir-emit.h"
  31 #include "mini-amd64.h"
  32 #include "cpu-amd64.h"
  33 #include "debugger-agent.h"
  34
  35 /*
  36  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  37  * method-to-ir.c.
  38  */
  39 #define MONO_ARCH_IMT_REG AMD64_R11
  40
  41 static gint lmf_tls_offset = -1;
  42 static gint lmf_addr_tls_offset = -1;
  43 static gint appdomain_tls_offset = -1;
  44
  45 #ifdef MONO_XEN_OPT
  46 static gboolean optimize_for_xen = TRUE;
  47 #else
  48 #define optimize_for_xen 0
  49 #endif
  50
  51 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  52
  53 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  54
  55 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  56
  57 #ifdef PLATFORM_WIN32
  58 /* Under windows, the calling convention is never stdcall */
  59 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  60 #else
  61 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  62 #endif
  63
  64 /* amd64_mov_reg_imm () */
  65 #define BREAKPOINT_SIZE 8
  66
  67 /* This mutex protects architecture specific caches */
  68 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  69 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  70 static CRITICAL_SECTION mini_arch_mutex;
  71
  72 MonoBreakpointInfo
  73 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  74
  75 /*
  76  * The code generated for sequence points reads from this location, which is
  77  * made read-only when single stepping is enabled.
  78  */
  79 static gpointer ss_trigger_page;
  80
  81 /* Enabled breakpoints read from this trigger page */
  82 static gpointer bp_trigger_page;
  83
  84 #ifdef PLATFORM_WIN32
  85 /* On Win64 always reserve first 32 bytes for first four arguments */
  86 #define ARGS_OFFSET 48
  87 #else
  88 #define ARGS_OFFSET 16
  89 #endif
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 G_GNUC_UNUSED static void
 162 break_count (void)
 163 {
 164 }
 165
 166 G_GNUC_UNUSED static gboolean
 167 debug_count (void)
 168 {
 169         static int count = 0;
 170         count ++;
 171
 172         if (!getenv ("COUNT"))
 173                 return TRUE;
 174
 175         if (count == atoi (getenv ("COUNT"))) {
 176                 break_count ();
 177         }
 178
 179         if (count > atoi (getenv ("COUNT"))) {
 180                 return FALSE;
 181         }
 182
 183         return TRUE;
 184 }
 185
 186 static gboolean
 187 debug_omit_fp (void)
 188 {
 189 #if 0
 190         return debug_count ();
 191 #else
 192         return TRUE;
 193 #endif
 194 }
 195
 196 static inline gboolean
 197 amd64_is_near_call (guint8 *code)
 198 {
 199         /* Skip REX */
 200         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 201                 code += 1;
 202
 203         return code [0] == 0xe8;
 204 }
 205
 206 static inline void
 207 amd64_patch (unsigned char* code, gpointer target)
 208 {
 209         guint8 rex = 0;
 210
 211         /* Skip REX */
 212         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 213                 rex = code [0];
 214                 code += 1;
 215         }
 216
 217         if ((code [0] & 0xf8) == 0xb8) {
 218                 /* amd64_set_reg_template */
 219                 *(guint64*)(code + 1) = (guint64)target;
 220         }
 221         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 222                 /* mov 0(%rip), %dreg */
 223                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 224         }
 225         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 226                 /* call *<OFFSET>(%rip) */
 227                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 228         }
 229         else if ((code [0] == 0xe8)) {
 230                 /* call <DISP> */
 231                 gint64 disp = (guint8*)target - (guint8*)code;
 232                 g_assert (amd64_is_imm32 (disp));
 233                 x86_patch (code, (unsigned char*)target);
 234         }
 235         else
 236                 x86_patch (code, (unsigned char*)target);
 237 }
 238
 239 void
 240 mono_amd64_patch (unsigned char* code, gpointer target)
 241 {
 242         amd64_patch (code, target);
 243 }
 244
 245 typedef enum {
 246         ArgInIReg,
 247         ArgInFloatSSEReg,
 248         ArgInDoubleSSEReg,
 249         ArgOnStack,
 250         ArgValuetypeInReg,
 251         ArgValuetypeAddrInIReg,
 252         ArgNone /* only in pair_storage */
 253 } ArgStorage;
 254
 255 typedef struct {
 256         gint16 offset;
 257         gint8  reg;
 258         ArgStorage storage;
 259
 260         /* Only if storage == ArgValuetypeInReg */
 261         ArgStorage pair_storage [2];
 262         gint8 pair_regs [2];
 263 } ArgInfo;
 264
 265 typedef struct {
 266         int nargs;
 267         guint32 stack_usage;
 268         guint32 reg_usage;
 269         guint32 freg_usage;
 270         gboolean need_stack_align;
 271         gboolean vtype_retaddr;
 272         ArgInfo ret;
 273         ArgInfo sig_cookie;
 274         ArgInfo args [1];
 275 } CallInfo;
 276
 277 #define DEBUG(a) if (cfg->verbose_level > 1) a
 278
 279 #ifdef PLATFORM_WIN32
 280 #define PARAM_REGS 4
 281
 282 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 283
 284 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 285 #else
 286 #define PARAM_REGS 6
 287
 288 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 289
 290  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 291 #endif
 292
 293 static void inline
 294 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 295 {
 296     ainfo->offset = *stack_size;
 297
 298     if (*gr >= PARAM_REGS) {
 299                 ainfo->storage = ArgOnStack;
 300                 (*stack_size) += sizeof (gpointer);
 301     }
 302     else {
 303                 ainfo->storage = ArgInIReg;
 304                 ainfo->reg = param_regs [*gr];
 305                 (*gr) ++;
 306     }
 307 }
 308
 309 #ifdef PLATFORM_WIN32
 310 #define FLOAT_PARAM_REGS 4
 311 #else
 312 #define FLOAT_PARAM_REGS 8
 313 #endif
 314
 315 static void inline
 316 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 317 {
 318     ainfo->offset = *stack_size;
 319
 320     if (*gr >= FLOAT_PARAM_REGS) {
 321                 ainfo->storage = ArgOnStack;
 322                 (*stack_size) += sizeof (gpointer);
 323     }
 324     else {
 325                 /* A double register */
 326                 if (is_double)
 327                         ainfo->storage = ArgInDoubleSSEReg;
 328                 else
 329                         ainfo->storage = ArgInFloatSSEReg;
 330                 ainfo->reg = *gr;
 331                 (*gr) += 1;
 332     }
 333 }
 334
 335 typedef enum ArgumentClass {
 336         ARG_CLASS_NO_CLASS,
 337         ARG_CLASS_MEMORY,
 338         ARG_CLASS_INTEGER,
 339         ARG_CLASS_SSE
 340 } ArgumentClass;
 341
 342 static ArgumentClass
 343 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 344 {
 345         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 346         MonoType *ptype;
 347
 348         ptype = mini_type_get_underlying_type (NULL, type);
 349         switch (ptype->type) {
 350         case MONO_TYPE_BOOLEAN:
 351         case MONO_TYPE_CHAR:
 352         case MONO_TYPE_I1:
 353         case MONO_TYPE_U1:
 354         case MONO_TYPE_I2:
 355         case MONO_TYPE_U2:
 356         case MONO_TYPE_I4:
 357         case MONO_TYPE_U4:
 358         case MONO_TYPE_I:
 359         case MONO_TYPE_U:
 360         case MONO_TYPE_STRING:
 361         case MONO_TYPE_OBJECT:
 362         case MONO_TYPE_CLASS:
 363         case MONO_TYPE_SZARRAY:
 364         case MONO_TYPE_PTR:
 365         case MONO_TYPE_FNPTR:
 366         case MONO_TYPE_ARRAY:
 367         case MONO_TYPE_I8:
 368         case MONO_TYPE_U8:
 369                 class2 = ARG_CLASS_INTEGER;
 370                 break;
 371         case MONO_TYPE_R4:
 372         case MONO_TYPE_R8:
 373 #ifdef PLATFORM_WIN32
 374                 class2 = ARG_CLASS_INTEGER;
 375 #else
 376                 class2 = ARG_CLASS_SSE;
 377 #endif
 378                 break;
 379
 380         case MONO_TYPE_TYPEDBYREF:
 381                 g_assert_not_reached ();
 382
 383         case MONO_TYPE_GENERICINST:
 384                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 385                         class2 = ARG_CLASS_INTEGER;
 386                         break;
 387                 }
 388                 /* fall through */
 389         case MONO_TYPE_VALUETYPE: {
 390                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 391                 int i;
 392
 393                 for (i = 0; i < info->num_fields; ++i) {
 394                         class2 = class1;
 395                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 396                 }
 397                 break;
 398         }
 399         default:
 400                 g_assert_not_reached ();
 401         }
 402
 403         /* Merge */
 404         if (class1 == class2)
 405                 ;
 406         else if (class1 == ARG_CLASS_NO_CLASS)
 407                 class1 = class2;
 408         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 409                 class1 = ARG_CLASS_MEMORY;
 410         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 411                 class1 = ARG_CLASS_INTEGER;
 412         else
 413                 class1 = ARG_CLASS_SSE;
 414
 415         return class1;
 416 }
 417
 418 static void
 419 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 420                            gboolean is_return,
 421                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 422 {
 423         guint32 size, quad, nquads, i;
 424         ArgumentClass args [2];
 425         MonoMarshalType *info = NULL;
 426         MonoClass *klass;
 427         MonoGenericSharingContext tmp_gsctx;
 428         gboolean pass_on_stack = FALSE;
 429
 430         /*
 431          * The gsctx currently contains no data, it is only used for checking whenever
 432          * open types are allowed, some callers like mono_arch_get_argument_info ()
 433          * don't pass it to us, so work around that.
 434          */
 435         if (!gsctx)
 436                 gsctx = &tmp_gsctx;
 437
 438         klass = mono_class_from_mono_type (type);
 439         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 440 #ifndef PLATFORM_WIN32
 441         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 442                 /* We pass and return vtypes of size 8 in a register */
 443         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 444                 pass_on_stack = TRUE;
 445         }
 446 #else
 447         if (!sig->pinvoke) {
 448                 pass_on_stack = TRUE;
 449         }
 450 #endif
 451
 452         if (pass_on_stack) {
 453                 /* Allways pass in memory */
 454                 ainfo->offset = *stack_size;
 455                 *stack_size += ALIGN_TO (size, 8);
 456                 ainfo->storage = ArgOnStack;
 457
 458                 return;
 459         }
 460
 461         /* FIXME: Handle structs smaller than 8 bytes */
 462         //if ((size % 8) != 0)
 463         //      NOT_IMPLEMENTED;
 464
 465         if (size > 8)
 466                 nquads = 2;
 467         else
 468                 nquads = 1;
 469
 470         if (!sig->pinvoke) {
 471                 /* Always pass in 1 or 2 integer registers */
 472                 args [0] = ARG_CLASS_INTEGER;
 473                 args [1] = ARG_CLASS_INTEGER;
 474                 /* Only the simplest cases are supported */
 475                 if (is_return && nquads != 1) {
 476                         args [0] = ARG_CLASS_MEMORY;
 477                         args [1] = ARG_CLASS_MEMORY;
 478                 }
 479         } else {
 480                 /*
 481                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 482                  * The X87 and SSEUP stuff is left out since there are no such types in
 483                  * the CLR.
 484                  */
 485                 info = mono_marshal_load_type_info (klass);
 486                 g_assert (info);
 487
 488 #ifndef PLATFORM_WIN32
 489                 if (info->native_size > 16) {
 490                         ainfo->offset = *stack_size;
 491                         *stack_size += ALIGN_TO (info->native_size, 8);
 492                         ainfo->storage = ArgOnStack;
 493
 494                         return;
 495                 }
 496 #else
 497                 switch (info->native_size) {
 498                 case 1: case 2: case 4: case 8:
 499                         break;
 500                 default:
 501                         if (is_return) {
 502                                 ainfo->storage = ArgOnStack;
 503                                 ainfo->offset = *stack_size;
 504                                 *stack_size += ALIGN_TO (info->native_size, 8);
 505                         }
 506                         else {
 507                                 ainfo->storage = ArgValuetypeAddrInIReg;
 508
 509                                 if (*gr < PARAM_REGS) {
 510                                         ainfo->pair_storage [0] = ArgInIReg;
 511                                         ainfo->pair_regs [0] = param_regs [*gr];
 512                                         (*gr) ++;
 513                                 }
 514                                 else {
 515                                         ainfo->pair_storage [0] = ArgOnStack;
 516                                         ainfo->offset = *stack_size;
 517                                         *stack_size += 8;
 518                                 }
 519                         }
 520
 521                         return;
 522                 }
 523 #endif
 524
 525                 args [0] = ARG_CLASS_NO_CLASS;
 526                 args [1] = ARG_CLASS_NO_CLASS;
 527                 for (quad = 0; quad < nquads; ++quad) {
 528                         int size;
 529                         guint32 align;
 530                         ArgumentClass class1;
 531
 532                         if (info->num_fields == 0)
 533                                 class1 = ARG_CLASS_MEMORY;
 534                         else
 535                                 class1 = ARG_CLASS_NO_CLASS;
 536                         for (i = 0; i < info->num_fields; ++i) {
 537                                 size = mono_marshal_type_size (info->fields [i].field->type,
 538                                                                                            info->fields [i].mspec,
 539                                                                                            &align, TRUE, klass->unicode);
 540                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 541                                         /* Unaligned field */
 542                                         NOT_IMPLEMENTED;
 543                                 }
 544
 545                                 /* Skip fields in other quad */
 546                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 547                                         continue;
 548                                 if ((quad == 1) && (info->fields [i].offset < 8))
 549                                         continue;
 550
 551                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 552                         }
 553                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 554                         args [quad] = class1;
 555                 }
 556         }
 557
 558         /* Post merger cleanup */
 559         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 560                 args [0] = args [1] = ARG_CLASS_MEMORY;
 561
 562         /* Allocate registers */
 563         {
 564                 int orig_gr = *gr;
 565                 int orig_fr = *fr;
 566
 567                 ainfo->storage = ArgValuetypeInReg;
 568                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 569                 for (quad = 0; quad < nquads; ++quad) {
 570                         switch (args [quad]) {
 571                         case ARG_CLASS_INTEGER:
 572                                 if (*gr >= PARAM_REGS)
 573                                         args [quad] = ARG_CLASS_MEMORY;
 574                                 else {
 575                                         ainfo->pair_storage [quad] = ArgInIReg;
 576                                         if (is_return)
 577                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 578                                         else
 579                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 580                                         (*gr) ++;
 581                                 }
 582                                 break;
 583                         case ARG_CLASS_SSE:
 584                                 if (*fr >= FLOAT_PARAM_REGS)
 585                                         args [quad] = ARG_CLASS_MEMORY;
 586                                 else {
 587                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 588                                         ainfo->pair_regs [quad] = *fr;
 589                                         (*fr) ++;
 590                                 }
 591                                 break;
 592                         case ARG_CLASS_MEMORY:
 593                                 break;
 594                         default:
 595                                 g_assert_not_reached ();
 596                         }
 597                 }
 598
 599                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 600                         /* Revert possible register assignments */
 601                         *gr = orig_gr;
 602                         *fr = orig_fr;
 603
 604                         ainfo->offset = *stack_size;
 605                         if (sig->pinvoke)
 606                                 *stack_size += ALIGN_TO (info->native_size, 8);
 607                         else
 608                                 *stack_size += nquads * sizeof (gpointer);
 609                         ainfo->storage = ArgOnStack;
 610                 }
 611         }
 612 }
 613
 614 /*
 615  * get_call_info:
 616  *
 617  *  Obtain information about a call according to the calling convention.
 618  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 619  * Draft Version 0.23" document for more information.
 620  */
 621 static CallInfo*
 622 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 623 {
 624         guint32 i, gr, fr;
 625         MonoType *ret_type;
 626         int n = sig->hasthis + sig->param_count;
 627         guint32 stack_size = 0;
 628         CallInfo *cinfo;
 629
 630         if (mp)
 631                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 632         else
 633                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 634
 635         cinfo->nargs = n;
 636
 637         gr = 0;
 638         fr = 0;
 639
 640         /* return value */
 641         {
 642                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 643                 switch (ret_type->type) {
 644                 case MONO_TYPE_BOOLEAN:
 645                 case MONO_TYPE_I1:
 646                 case MONO_TYPE_U1:
 647                 case MONO_TYPE_I2:
 648                 case MONO_TYPE_U2:
 649                 case MONO_TYPE_CHAR:
 650                 case MONO_TYPE_I4:
 651                 case MONO_TYPE_U4:
 652                 case MONO_TYPE_I:
 653                 case MONO_TYPE_U:
 654                 case MONO_TYPE_PTR:
 655                 case MONO_TYPE_FNPTR:
 656                 case MONO_TYPE_CLASS:
 657                 case MONO_TYPE_OBJECT:
 658                 case MONO_TYPE_SZARRAY:
 659                 case MONO_TYPE_ARRAY:
 660                 case MONO_TYPE_STRING:
 661                         cinfo->ret.storage = ArgInIReg;
 662                         cinfo->ret.reg = AMD64_RAX;
 663                         break;
 664                 case MONO_TYPE_U8:
 665                 case MONO_TYPE_I8:
 666                         cinfo->ret.storage = ArgInIReg;
 667                         cinfo->ret.reg = AMD64_RAX;
 668                         break;
 669                 case MONO_TYPE_R4:
 670                         cinfo->ret.storage = ArgInFloatSSEReg;
 671                         cinfo->ret.reg = AMD64_XMM0;
 672                         break;
 673                 case MONO_TYPE_R8:
 674                         cinfo->ret.storage = ArgInDoubleSSEReg;
 675                         cinfo->ret.reg = AMD64_XMM0;
 676                         break;
 677                 case MONO_TYPE_GENERICINST:
 678                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 679                                 cinfo->ret.storage = ArgInIReg;
 680                                 cinfo->ret.reg = AMD64_RAX;
 681                                 break;
 682                         }
 683                         /* fall through */
 684                 case MONO_TYPE_VALUETYPE: {
 685                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 686
 687                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 688                         if (cinfo->ret.storage == ArgOnStack) {
 689                                 cinfo->vtype_retaddr = TRUE;
 690                                 /* The caller passes the address where the value is stored */
 691                                 add_general (&gr, &stack_size, &cinfo->ret);
 692                         }
 693                         break;
 694                 }
 695                 case MONO_TYPE_TYPEDBYREF:
 696                         /* Same as a valuetype with size 24 */
 697                         add_general (&gr, &stack_size, &cinfo->ret);
 698                         ;
 699                         break;
 700                 case MONO_TYPE_VOID:
 701                         break;
 702                 default:
 703                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 704                 }
 705         }
 706
 707         /* this */
 708         if (sig->hasthis)
 709                 add_general (&gr, &stack_size, cinfo->args + 0);
 710
 711         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 712                 gr = PARAM_REGS;
 713                 fr = FLOAT_PARAM_REGS;
 714
 715                 /* Emit the signature cookie just before the implicit arguments */
 716                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 717         }
 718
 719         for (i = 0; i < sig->param_count; ++i) {
 720                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 721                 MonoType *ptype;
 722
 723 #ifdef PLATFORM_WIN32
 724                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 725                 if (gr > fr)
 726                         fr = gr;
 727                 else if (fr > gr)
 728                         gr = fr;
 729 #endif
 730
 731                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 732                         /* We allways pass the sig cookie on the stack for simplicity */
 733                         /*
 734                          * Prevent implicit arguments + the sig cookie from being passed
 735                          * in registers.
 736                          */
 737                         gr = PARAM_REGS;
 738                         fr = FLOAT_PARAM_REGS;
 739
 740                         /* Emit the signature cookie just before the implicit arguments */
 741                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 742                 }
 743
 744                 if (sig->params [i]->byref) {
 745                         add_general (&gr, &stack_size, ainfo);
 746                         continue;
 747                 }
 748                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 749                 switch (ptype->type) {
 750                 case MONO_TYPE_BOOLEAN:
 751                 case MONO_TYPE_I1:
 752                 case MONO_TYPE_U1:
 753                         add_general (&gr, &stack_size, ainfo);
 754                         break;
 755                 case MONO_TYPE_I2:
 756                 case MONO_TYPE_U2:
 757                 case MONO_TYPE_CHAR:
 758                         add_general (&gr, &stack_size, ainfo);
 759                         break;
 760                 case MONO_TYPE_I4:
 761                 case MONO_TYPE_U4:
 762                         add_general (&gr, &stack_size, ainfo);
 763                         break;
 764                 case MONO_TYPE_I:
 765                 case MONO_TYPE_U:
 766                 case MONO_TYPE_PTR:
 767                 case MONO_TYPE_FNPTR:
 768                 case MONO_TYPE_CLASS:
 769                 case MONO_TYPE_OBJECT:
 770                 case MONO_TYPE_STRING:
 771                 case MONO_TYPE_SZARRAY:
 772                 case MONO_TYPE_ARRAY:
 773                         add_general (&gr, &stack_size, ainfo);
 774                         break;
 775                 case MONO_TYPE_GENERICINST:
 776                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 777                                 add_general (&gr, &stack_size, ainfo);
 778                                 break;
 779                         }
 780                         /* fall through */
 781                 case MONO_TYPE_VALUETYPE:
 782                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 783                         break;
 784                 case MONO_TYPE_TYPEDBYREF:
 785 #ifdef PLATFORM_WIN32
 786                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 787 #else
 788                         stack_size += sizeof (MonoTypedRef);
 789                         ainfo->storage = ArgOnStack;
 790 #endif
 791                         break;
 792                 case MONO_TYPE_U8:
 793                 case MONO_TYPE_I8:
 794                         add_general (&gr, &stack_size, ainfo);
 795                         break;
 796                 case MONO_TYPE_R4:
 797                         add_float (&fr, &stack_size, ainfo, FALSE);
 798                         break;
 799                 case MONO_TYPE_R8:
 800                         add_float (&fr, &stack_size, ainfo, TRUE);
 801                         break;
 802                 default:
 803                         g_assert_not_reached ();
 804                 }
 805         }
 806
 807         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 808                 gr = PARAM_REGS;
 809                 fr = FLOAT_PARAM_REGS;
 810
 811                 /* Emit the signature cookie just before the implicit arguments */
 812                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 813         }
 814
 815 #ifdef PLATFORM_WIN32
 816         // There always is 32 bytes reserved on the stack when calling on Winx64
 817         stack_size += 0x20;
 818 #endif
 819
 820         if (stack_size & 0x8) {
 821                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 822                 cinfo->need_stack_align = TRUE;
 823                 stack_size += 8;
 824         }
 825
 826         cinfo->stack_usage = stack_size;
 827         cinfo->reg_usage = gr;
 828         cinfo->freg_usage = fr;
 829         return cinfo;
 830 }
 831
 832 /*
 833  * mono_arch_get_argument_info:
 834  * @csig:  a method signature
 835  * @param_count: the number of parameters to consider
 836  * @arg_info: an array to store the result infos
 837  *
 838  * Gathers information on parameters such as size, alignment and
 839  * padding. arg_info should be large enought to hold param_count + 1 entries.
 840  *
 841  * Returns the size of the argument area on the stack.
 842  */
 843 int
 844 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 845 {
 846         int k;
 847         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 848         guint32 args_size = cinfo->stack_usage;
 849
 850         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 851         if (csig->hasthis) {
 852                 arg_info [0].offset = 0;
 853         }
 854
 855         for (k = 0; k < param_count; k++) {
 856                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 857                 /* FIXME: */
 858                 arg_info [k + 1].size = 0;
 859         }
 860
 861         g_free (cinfo);
 862
 863         return args_size;
 864 }
 865
 866 static int
 867 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 868 {
 869 #ifndef _MSC_VER
 870         __asm__ __volatile__ ("cpuid"
 871                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 872                 : "a" (id));
 873 #else
 874         int info[4];
 875         __cpuid(info, id);
 876         *p_eax = info[0];
 877         *p_ebx = info[1];
 878         *p_ecx = info[2];
 879         *p_edx = info[3];
 880 #endif
 881         return 1;
 882 }
 883
 884 /*
 885  * Initialize the cpu to execute managed code.
 886  */
 887 void
 888 mono_arch_cpu_init (void)
 889 {
 890 #ifndef _MSC_VER
 891         guint16 fpcw;
 892
 893         /* spec compliance requires running with double precision */
 894         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 895         fpcw &= ~X86_FPCW_PRECC_MASK;
 896         fpcw |= X86_FPCW_PREC_DOUBLE;
 897         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 898         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 899 #else
 900         /* TODO: This is crashing on Win64 right now.
 901         * _control87 (_PC_53, MCW_PC);
 902         */
 903 #endif
 904 }
 905
 906 /*
 907  * Initialize architecture specific code.
 908  */
 909 void
 910 mono_arch_init (void)
 911 {
 912         InitializeCriticalSection (&mini_arch_mutex);
 913
 914         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 915         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), MONO_MMAP_READ|MONO_MMAP_32BIT);
 916         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 917 }
 918
 919 /*
 920  * Cleanup architecture specific code.
 921  */
 922 void
 923 mono_arch_cleanup (void)
 924 {
 925         DeleteCriticalSection (&mini_arch_mutex);
 926 }
 927
 928 /*
 929  * This function returns the optimizations supported on this cpu.
 930  */
 931 guint32
 932 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 933 {
 934         int eax, ebx, ecx, edx;
 935         guint32 opts = 0;
 936
 937         /* FIXME: AMD64 */
 938
 939         *exclude_mask = 0;
 940         /* Feature Flags function, flags returned in EDX. */
 941         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 942                 if (edx & (1 << 15)) {
 943                         opts |= MONO_OPT_CMOV;
 944                         if (edx & 1)
 945                                 opts |= MONO_OPT_FCMOV;
 946                         else
 947                                 *exclude_mask |= MONO_OPT_FCMOV;
 948                 } else
 949                         *exclude_mask |= MONO_OPT_CMOV;
 950         }
 951
 952         return opts;
 953 }
 954
 955 /*
 956  * This function test for all SSE functions supported.
 957  *
 958  * Returns a bitmask corresponding to all supported versions.
 959  *
 960  */
 961 guint32
 962 mono_arch_cpu_enumerate_simd_versions (void)
 963 {
 964         int eax, ebx, ecx, edx;
 965         guint32 sse_opts = 0;
 966
 967         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 968                 if (edx & (1 << 25))
 969                         sse_opts |= 1 << SIMD_VERSION_SSE1;
 970                 if (edx & (1 << 26))
 971                         sse_opts |= 1 << SIMD_VERSION_SSE2;
 972                 if (ecx & (1 << 0))
 973                         sse_opts |= 1 << SIMD_VERSION_SSE3;
 974                 if (ecx & (1 << 9))
 975                         sse_opts |= 1 << SIMD_VERSION_SSSE3;
 976                 if (ecx & (1 << 19))
 977                         sse_opts |= 1 << SIMD_VERSION_SSE41;
 978                 if (ecx & (1 << 20))
 979                         sse_opts |= 1 << SIMD_VERSION_SSE42;
 980         }
 981
 982         /* Yes, all this needs to be done to check for sse4a.
 983            See: "Amd: CPUID Specification"
 984          */
 985         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
 986                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
 987                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
 988                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
 989                         if (ecx & (1 << 6))
 990                                 sse_opts |= 1 << SIMD_VERSION_SSE4a;
 991                 }
 992         }
 993
 994         return sse_opts;
 995 }
 996
 997 GList *
 998 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 999 {
1000         GList *vars = NULL;
1001         int i;
1002
1003         for (i = 0; i < cfg->num_varinfo; i++) {
1004                 MonoInst *ins = cfg->varinfo [i];
1005                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1006
1007                 /* unused vars */
1008                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1009                         continue;
1010
1011                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1012                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1013                         continue;
1014
1015                 if (mono_is_regsize_var (ins->inst_vtype)) {
1016                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1017                         g_assert (i == vmv->idx);
1018                         vars = g_list_prepend (vars, vmv);
1019                 }
1020         }
1021
1022         vars = mono_varlist_sort (cfg, vars, 0);
1023
1024         return vars;
1025 }
1026
1027 /**
1028  * mono_arch_compute_omit_fp:
1029  *
1030  *   Determine whenever the frame pointer can be eliminated.
1031  */
1032 static void
1033 mono_arch_compute_omit_fp (MonoCompile *cfg)
1034 {
1035         MonoMethodSignature *sig;
1036         MonoMethodHeader *header;
1037         int i, locals_size;
1038         CallInfo *cinfo;
1039
1040         if (cfg->arch.omit_fp_computed)
1041                 return;
1042
1043         header = mono_method_get_header (cfg->method);
1044
1045         sig = mono_method_signature (cfg->method);
1046
1047         if (!cfg->arch.cinfo)
1048                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1049         cinfo = cfg->arch.cinfo;
1050
1051         /*
1052          * FIXME: Remove some of the restrictions.
1053          */
1054         cfg->arch.omit_fp = TRUE;
1055         cfg->arch.omit_fp_computed = TRUE;
1056
1057         if (cfg->disable_omit_fp)
1058                 cfg->arch.omit_fp = FALSE;
1059
1060         if (!debug_omit_fp ())
1061                 cfg->arch.omit_fp = FALSE;
1062         /*
1063         if (cfg->method->save_lmf)
1064                 cfg->arch.omit_fp = FALSE;
1065         */
1066         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1067                 cfg->arch.omit_fp = FALSE;
1068         if (header->num_clauses)
1069                 cfg->arch.omit_fp = FALSE;
1070         if (cfg->param_area)
1071                 cfg->arch.omit_fp = FALSE;
1072         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1073                 cfg->arch.omit_fp = FALSE;
1074         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1075                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1076                 cfg->arch.omit_fp = FALSE;
1077         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1078                 ArgInfo *ainfo = &cinfo->args [i];
1079
1080                 if (ainfo->storage == ArgOnStack) {
1081                         /*
1082                          * The stack offset can only be determined when the frame
1083                          * size is known.
1084                          */
1085                         cfg->arch.omit_fp = FALSE;
1086                 }
1087         }
1088
1089         locals_size = 0;
1090         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1091                 MonoInst *ins = cfg->varinfo [i];
1092                 int ialign;
1093
1094                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1095         }
1096 }
1097
1098 GList *
1099 mono_arch_get_global_int_regs (MonoCompile *cfg)
1100 {
1101         GList *regs = NULL;
1102
1103         mono_arch_compute_omit_fp (cfg);
1104
1105         if (cfg->globalra) {
1106                 if (cfg->arch.omit_fp)
1107                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1108
1109                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1110                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1111                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1112                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1113                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1114
1115                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1116                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1117                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1118                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1119                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1120                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1121                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1122                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1123         } else {
1124                 if (cfg->arch.omit_fp)
1125                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1126
1127                 /* We use the callee saved registers for global allocation */
1128                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1129                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1130                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1131                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1132                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1133 #ifdef PLATFORM_WIN32
1134                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1135                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1136 #endif
1137         }
1138
1139         return regs;
1140 }
1141
1142 GList*
1143 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1144 {
1145         GList *regs = NULL;
1146         int i;
1147
1148         /* All XMM registers */
1149         for (i = 0; i < 16; ++i)
1150                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1151
1152         return regs;
1153 }
1154
1155 GList*
1156 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1157 {
1158         static GList *r = NULL;
1159
1160         if (r == NULL) {
1161                 GList *regs = NULL;
1162
1163                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1164                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1165                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1166                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1167                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1168                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1169
1170                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1171                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1172                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1173                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1174                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1175                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1176                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1177                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1178
1179                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1180         }
1181
1182         return r;
1183 }
1184
1185 GList*
1186 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1187 {
1188         int i;
1189         static GList *r = NULL;
1190
1191         if (r == NULL) {
1192                 GList *regs = NULL;
1193
1194                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1195                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1196
1197                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1198         }
1199
1200         return r;
1201 }
1202
1203 /*
1204  * mono_arch_regalloc_cost:
1205  *
1206  *  Return the cost, in number of memory references, of the action of
1207  * allocating the variable VMV into a register during global register
1208  * allocation.
1209  */
1210 guint32
1211 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1212 {
1213         MonoInst *ins = cfg->varinfo [vmv->idx];
1214
1215         if (cfg->method->save_lmf)
1216                 /* The register is already saved */
1217                 /* substract 1 for the invisible store in the prolog */
1218                 return (ins->opcode == OP_ARG) ? 0 : 1;
1219         else
1220                 /* push+pop */
1221                 return (ins->opcode == OP_ARG) ? 1 : 2;
1222 }
1223
1224 /*
1225  * mono_arch_fill_argument_info:
1226  *
1227  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1228  * of the method.
1229  */
1230 void
1231 mono_arch_fill_argument_info (MonoCompile *cfg)
1232 {
1233         MonoMethodSignature *sig;
1234         MonoMethodHeader *header;
1235         MonoInst *ins;
1236         int i;
1237         CallInfo *cinfo;
1238
1239         header = mono_method_get_header (cfg->method);
1240
1241         sig = mono_method_signature (cfg->method);
1242
1243         cinfo = cfg->arch.cinfo;
1244
1245         /*
1246          * Contrary to mono_arch_allocate_vars (), the information should describe
1247          * where the arguments are at the beginning of the method, not where they can be
1248          * accessed during the execution of the method. The later makes no sense for the
1249          * global register allocator, since a variable can be in more than one location.
1250          */
1251         if (sig->ret->type != MONO_TYPE_VOID) {
1252                 switch (cinfo->ret.storage) {
1253                 case ArgInIReg:
1254                 case ArgInFloatSSEReg:
1255                 case ArgInDoubleSSEReg:
1256                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1257                                 cfg->vret_addr->opcode = OP_REGVAR;
1258                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1259                         }
1260                         else {
1261                                 cfg->ret->opcode = OP_REGVAR;
1262                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1263                         }
1264                         break;
1265                 case ArgValuetypeInReg:
1266                         cfg->ret->opcode = OP_REGOFFSET;
1267                         cfg->ret->inst_basereg = -1;
1268                         cfg->ret->inst_offset = -1;
1269                         break;
1270                 default:
1271                         g_assert_not_reached ();
1272                 }
1273         }
1274
1275         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1276                 ArgInfo *ainfo = &cinfo->args [i];
1277                 MonoType *arg_type;
1278
1279                 ins = cfg->args [i];
1280
1281                 if (sig->hasthis && (i == 0))
1282                         arg_type = &mono_defaults.object_class->byval_arg;
1283                 else
1284                         arg_type = sig->params [i - sig->hasthis];
1285
1286                 switch (ainfo->storage) {
1287                 case ArgInIReg:
1288                 case ArgInFloatSSEReg:
1289                 case ArgInDoubleSSEReg:
1290                         ins->opcode = OP_REGVAR;
1291                         ins->inst_c0 = ainfo->reg;
1292                         break;
1293                 case ArgOnStack:
1294                         ins->opcode = OP_REGOFFSET;
1295                         ins->inst_basereg = -1;
1296                         ins->inst_offset = -1;
1297                         break;
1298                 case ArgValuetypeInReg:
1299                         /* Dummy */
1300                         ins->opcode = OP_NOP;
1301                         break;
1302                 default:
1303                         g_assert_not_reached ();
1304                 }
1305         }
1306 }
1307
1308 void
1309 mono_arch_allocate_vars (MonoCompile *cfg)
1310 {
1311         MonoMethodSignature *sig;
1312         MonoMethodHeader *header;
1313         MonoInst *ins;
1314         int i, offset;
1315         guint32 locals_stack_size, locals_stack_align;
1316         gint32 *offsets;
1317         CallInfo *cinfo;
1318
1319         header = mono_method_get_header (cfg->method);
1320
1321         sig = mono_method_signature (cfg->method);
1322
1323         cinfo = cfg->arch.cinfo;
1324
1325         mono_arch_compute_omit_fp (cfg);
1326
1327         /*
1328          * We use the ABI calling conventions for managed code as well.
1329          * Exception: valuetypes are only sometimes passed or returned in registers.
1330          */
1331
1332         /*
1333          * The stack looks like this:
1334          * <incoming arguments passed on the stack>
1335          * <return value>
1336          * <lmf/caller saved registers>
1337          * <locals>
1338          * <spill area>
1339          * <localloc area>  -> grows dynamically
1340          * <params area>
1341          */
1342
1343         if (cfg->arch.omit_fp) {
1344                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1345                 cfg->frame_reg = AMD64_RSP;
1346                 offset = 0;
1347         } else {
1348                 /* Locals are allocated backwards from %fp */
1349                 cfg->frame_reg = AMD64_RBP;
1350                 offset = 0;
1351         }
1352
1353         if (cfg->method->save_lmf) {
1354                 /* Reserve stack space for saving LMF */
1355                 if (cfg->arch.omit_fp) {
1356                         cfg->arch.lmf_offset = offset;
1357                         offset += sizeof (MonoLMF);
1358                 }
1359                 else {
1360                         offset += sizeof (MonoLMF);
1361                         cfg->arch.lmf_offset = -offset;
1362                 }
1363         } else {
1364                 if (cfg->arch.omit_fp)
1365                         cfg->arch.reg_save_area_offset = offset;
1366                 /* Reserve space for caller saved registers */
1367                 for (i = 0; i < AMD64_NREG; ++i)
1368                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1369                                 offset += sizeof (gpointer);
1370                         }
1371         }
1372
1373         if (sig->ret->type != MONO_TYPE_VOID) {
1374                 switch (cinfo->ret.storage) {
1375                 case ArgInIReg:
1376                 case ArgInFloatSSEReg:
1377                 case ArgInDoubleSSEReg:
1378                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1379                                 if (cfg->globalra) {
1380                                         cfg->vret_addr->opcode = OP_REGVAR;
1381                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1382                                 } else {
1383                                         /* The register is volatile */
1384                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1385                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1386                                         if (cfg->arch.omit_fp) {
1387                                                 cfg->vret_addr->inst_offset = offset;
1388                                                 offset += 8;
1389                                         } else {
1390                                                 offset += 8;
1391                                                 cfg->vret_addr->inst_offset = -offset;
1392                                         }
1393                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1394                                                 printf ("vret_addr =");
1395                                                 mono_print_ins (cfg->vret_addr);
1396                                         }
1397                                 }
1398                         }
1399                         else {
1400                                 cfg->ret->opcode = OP_REGVAR;
1401                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1402                         }
1403                         break;
1404                 case ArgValuetypeInReg:
1405                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1406                         cfg->ret->opcode = OP_REGOFFSET;
1407                         cfg->ret->inst_basereg = cfg->frame_reg;
1408                         if (cfg->arch.omit_fp) {
1409                                 cfg->ret->inst_offset = offset;
1410                                 offset += 16;
1411                         } else {
1412                                 offset += 16;
1413                                 cfg->ret->inst_offset = - offset;
1414                         }
1415                         break;
1416                 default:
1417                         g_assert_not_reached ();
1418                 }
1419                 if (!cfg->globalra)
1420                         cfg->ret->dreg = cfg->ret->inst_c0;
1421         }
1422
1423         /* Allocate locals */
1424         if (!cfg->globalra) {
1425                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1426                 if (locals_stack_align) {
1427                         offset += (locals_stack_align - 1);
1428                         offset &= ~(locals_stack_align - 1);
1429                 }
1430                 if (cfg->arch.omit_fp) {
1431                         cfg->locals_min_stack_offset = offset;
1432                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1433                 } else {
1434                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1435                         cfg->locals_max_stack_offset = - offset;
1436                 }
1437
1438                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1439                         if (offsets [i] != -1) {
1440                                 MonoInst *ins = cfg->varinfo [i];
1441                                 ins->opcode = OP_REGOFFSET;
1442                                 ins->inst_basereg = cfg->frame_reg;
1443                                 if (cfg->arch.omit_fp)
1444                                         ins->inst_offset = (offset + offsets [i]);
1445                                 else
1446                                         ins->inst_offset = - (offset + offsets [i]);
1447                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1448                         }
1449                 }
1450                 offset += locals_stack_size;
1451         }
1452
1453         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1454                 g_assert (!cfg->arch.omit_fp);
1455                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1456                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1457         }
1458
1459         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1460                 ins = cfg->args [i];
1461                 if (ins->opcode != OP_REGVAR) {
1462                         ArgInfo *ainfo = &cinfo->args [i];
1463                         gboolean inreg = TRUE;
1464                         MonoType *arg_type;
1465
1466                         if (sig->hasthis && (i == 0))
1467                                 arg_type = &mono_defaults.object_class->byval_arg;
1468                         else
1469                                 arg_type = sig->params [i - sig->hasthis];
1470
1471                         if (cfg->globalra) {
1472                                 /* The new allocator needs info about the original locations of the arguments */
1473                                 switch (ainfo->storage) {
1474                                 case ArgInIReg:
1475                                 case ArgInFloatSSEReg:
1476                                 case ArgInDoubleSSEReg:
1477                                         ins->opcode = OP_REGVAR;
1478                                         ins->inst_c0 = ainfo->reg;
1479                                         break;
1480                                 case ArgOnStack:
1481                                         g_assert (!cfg->arch.omit_fp);
1482                                         ins->opcode = OP_REGOFFSET;
1483                                         ins->inst_basereg = cfg->frame_reg;
1484                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1485                                         break;
1486                                 case ArgValuetypeInReg:
1487                                         ins->opcode = OP_REGOFFSET;
1488                                         ins->inst_basereg = cfg->frame_reg;
1489                                         /* These arguments are saved to the stack in the prolog */
1490                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1491                                         if (cfg->arch.omit_fp) {
1492                                                 ins->inst_offset = offset;
1493                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1494                                         } else {
1495                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1496                                                 ins->inst_offset = - offset;
1497                                         }
1498                                         break;
1499                                 default:
1500                                         g_assert_not_reached ();
1501                                 }
1502
1503                                 continue;
1504                         }
1505
1506                         /* FIXME: Allocate volatile arguments to registers */
1507                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1508                                 inreg = FALSE;
1509
1510                         /*
1511                          * Under AMD64, all registers used to pass arguments to functions
1512                          * are volatile across calls.
1513                          * FIXME: Optimize this.
1514                          */
1515                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1516                                 inreg = FALSE;
1517
1518                         ins->opcode = OP_REGOFFSET;
1519
1520                         switch (ainfo->storage) {
1521                         case ArgInIReg:
1522                         case ArgInFloatSSEReg:
1523                         case ArgInDoubleSSEReg:
1524                                 if (inreg) {
1525                                         ins->opcode = OP_REGVAR;
1526                                         ins->dreg = ainfo->reg;
1527                                 }
1528                                 break;
1529                         case ArgOnStack:
1530                                 g_assert (!cfg->arch.omit_fp);
1531                                 ins->opcode = OP_REGOFFSET;
1532                                 ins->inst_basereg = cfg->frame_reg;
1533                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1534                                 break;
1535                         case ArgValuetypeInReg:
1536                                 break;
1537                         case ArgValuetypeAddrInIReg: {
1538                                 MonoInst *indir;
1539                                 g_assert (!cfg->arch.omit_fp);
1540
1541                                 MONO_INST_NEW (cfg, indir, 0);
1542                                 indir->opcode = OP_REGOFFSET;
1543                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1544                                         indir->inst_basereg = cfg->frame_reg;
1545                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1546                                         offset += (sizeof (gpointer));
1547                                         indir->inst_offset = - offset;
1548                                 }
1549                                 else {
1550                                         indir->inst_basereg = cfg->frame_reg;
1551                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1552                                 }
1553
1554                                 ins->opcode = OP_VTARG_ADDR;
1555                                 ins->inst_left = indir;
1556
1557                                 break;
1558                         }
1559                         default:
1560                                 NOT_IMPLEMENTED;
1561                         }
1562
1563                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1564                                 ins->opcode = OP_REGOFFSET;
1565                                 ins->inst_basereg = cfg->frame_reg;
1566                                 /* These arguments are saved to the stack in the prolog */
1567                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1568                                 if (cfg->arch.omit_fp) {
1569                                         ins->inst_offset = offset;
1570                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1571                                 } else {
1572                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1573                                         ins->inst_offset = - offset;
1574                                 }
1575                         }
1576                 }
1577         }
1578
1579         cfg->stack_offset = offset;
1580 }
1581
1582 void
1583 mono_arch_create_vars (MonoCompile *cfg)
1584 {
1585         MonoMethodSignature *sig;
1586         CallInfo *cinfo;
1587
1588         sig = mono_method_signature (cfg->method);
1589
1590         if (!cfg->arch.cinfo)
1591                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1592         cinfo = cfg->arch.cinfo;
1593
1594         if (cinfo->ret.storage == ArgValuetypeInReg)
1595                 cfg->ret_var_is_local = TRUE;
1596
1597         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1598                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1599                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1600                         printf ("vret_addr = ");
1601                         mono_print_ins (cfg->vret_addr);
1602                 }
1603         }
1604
1605 #ifdef MONO_AMD64_NO_PUSHES
1606         /*
1607          * When this is set, we pass arguments on the stack by moves, and by allocating
1608          * a bigger stack frame, instead of pushes.
1609          * Pushes complicate exception handling because the arguments on the stack have
1610          * to be popped each time a frame is unwound. They also make fp elimination
1611          * impossible.
1612          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1613          * on a new frame which doesn't include a param area.
1614          */
1615         cfg->arch.no_pushes = TRUE;
1616 #endif
1617 }
1618
1619 static void
1620 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1621 {
1622         MonoInst *ins;
1623
1624         switch (storage) {
1625         case ArgInIReg:
1626                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1627                 ins->dreg = mono_alloc_ireg (cfg);
1628                 ins->sreg1 = tree->dreg;
1629                 MONO_ADD_INS (cfg->cbb, ins);
1630                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1631                 break;
1632         case ArgInFloatSSEReg:
1633                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1634                 ins->dreg = mono_alloc_freg (cfg);
1635                 ins->sreg1 = tree->dreg;
1636                 MONO_ADD_INS (cfg->cbb, ins);
1637
1638                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1639                 break;
1640         case ArgInDoubleSSEReg:
1641                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1642                 ins->dreg = mono_alloc_freg (cfg);
1643                 ins->sreg1 = tree->dreg;
1644                 MONO_ADD_INS (cfg->cbb, ins);
1645
1646                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1647
1648                 break;
1649         default:
1650                 g_assert_not_reached ();
1651         }
1652 }
1653
1654 static int
1655 arg_storage_to_load_membase (ArgStorage storage)
1656 {
1657         switch (storage) {
1658         case ArgInIReg:
1659                 return OP_LOAD_MEMBASE;
1660         case ArgInDoubleSSEReg:
1661                 return OP_LOADR8_MEMBASE;
1662         case ArgInFloatSSEReg:
1663                 return OP_LOADR4_MEMBASE;
1664         default:
1665                 g_assert_not_reached ();
1666         }
1667
1668         return -1;
1669 }
1670
1671 static void
1672 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1673 {
1674         MonoInst *arg;
1675         MonoMethodSignature *tmp_sig;
1676         MonoInst *sig_arg;
1677
1678         if (call->tail_call)
1679                 NOT_IMPLEMENTED;
1680
1681         /* FIXME: Add support for signature tokens to AOT */
1682         cfg->disable_aot = TRUE;
1683
1684         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1685
1686         /*
1687          * mono_ArgIterator_Setup assumes the signature cookie is
1688          * passed first and all the arguments which were before it are
1689          * passed on the stack after the signature. So compensate by
1690          * passing a different signature.
1691          */
1692         tmp_sig = mono_metadata_signature_dup (call->signature);
1693         tmp_sig->param_count -= call->signature->sentinelpos;
1694         tmp_sig->sentinelpos = 0;
1695         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1696
1697         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1698         sig_arg->dreg = mono_alloc_ireg (cfg);
1699         sig_arg->inst_p0 = tmp_sig;
1700         MONO_ADD_INS (cfg->cbb, sig_arg);
1701
1702         if (cfg->arch.no_pushes) {
1703                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1704         } else {
1705                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1706                 arg->sreg1 = sig_arg->dreg;
1707                 MONO_ADD_INS (cfg->cbb, arg);
1708         }
1709 }
1710
1711 static inline LLVMArgStorage
1712 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1713 {
1714         switch (storage) {
1715         case ArgInIReg:
1716                 return LLVMArgInIReg;
1717         case ArgNone:
1718                 return LLVMArgNone;
1719         default:
1720                 g_assert_not_reached ();
1721                 return LLVMArgNone;
1722         }
1723 }
1724
1725 #ifdef ENABLE_LLVM
1726 LLVMCallInfo*
1727 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1728 {
1729         int i, n;
1730         CallInfo *cinfo;
1731         ArgInfo *ainfo;
1732         int j;
1733         LLVMCallInfo *linfo;
1734
1735         n = sig->param_count + sig->hasthis;
1736
1737         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1738
1739         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1740
1741         /*
1742          * LLVM always uses the native ABI while we use our own ABI, the
1743          * only difference is the handling of vtypes:
1744          * - we only pass/receive them in registers in some cases, and only
1745          *   in 1 or 2 integer registers.
1746          */
1747         if (cinfo->ret.storage == ArgValuetypeInReg) {
1748                 if (sig->pinvoke) {
1749                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1750                         cfg->disable_llvm = TRUE;
1751                         return linfo;
1752                 }
1753
1754                 linfo->ret.storage = LLVMArgVtypeInReg;
1755                 for (j = 0; j < 2; ++j)
1756                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1757         }
1758
1759         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1760                 /* Vtype returned using a hidden argument */
1761                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1762         }
1763
1764         for (i = 0; i < n; ++i) {
1765                 ainfo = cinfo->args + i;
1766
1767                 linfo->args [i].storage = LLVMArgNone;
1768
1769                 switch (ainfo->storage) {
1770                 case ArgInIReg:
1771                         linfo->args [i].storage = LLVMArgInIReg;
1772                         break;
1773                 case ArgInDoubleSSEReg:
1774                 case ArgInFloatSSEReg:
1775                         linfo->args [i].storage = LLVMArgInFPReg;
1776                         break;
1777                 case ArgOnStack:
1778                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1779                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1780                         } else {
1781                                 linfo->args [i].storage = LLVMArgInIReg;
1782                                 if (!sig->params [i - sig->hasthis]->byref) {
1783                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1784                                                 linfo->args [i].storage = LLVMArgInFPReg;
1785                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1786                                                 linfo->args [i].storage = LLVMArgInFPReg;
1787                                         }
1788                                 }
1789                         }
1790                         break;
1791                 case ArgValuetypeInReg:
1792                         if (sig->pinvoke) {
1793                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1794                                 cfg->disable_llvm = TRUE;
1795                                 return linfo;
1796                         }
1797
1798                         linfo->args [i].storage = LLVMArgVtypeInReg;
1799                         for (j = 0; j < 2; ++j)
1800                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1801                         break;
1802                 default:
1803                         cfg->exception_message = g_strdup ("ainfo->storage");
1804                         cfg->disable_llvm = TRUE;
1805                         break;
1806                 }
1807         }
1808
1809         return linfo;
1810 }
1811 #endif
1812
1813 void
1814 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1815 {
1816         MonoInst *arg, *in;
1817         MonoMethodSignature *sig;
1818         int i, n, stack_size;
1819         CallInfo *cinfo;
1820         ArgInfo *ainfo;
1821
1822         stack_size = 0;
1823
1824         sig = call->signature;
1825         n = sig->param_count + sig->hasthis;
1826
1827         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1828
1829         if (COMPILE_LLVM (cfg)) {
1830                 /* We shouldn't be called in the llvm case */
1831                 cfg->disable_llvm = TRUE;
1832                 return;
1833         }
1834
1835         if (cinfo->need_stack_align) {
1836                 if (!cfg->arch.no_pushes)
1837                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1838         }
1839
1840         /*
1841          * Emit all arguments which are passed on the stack to prevent register
1842          * allocation problems.
1843          */
1844         if (cfg->arch.no_pushes) {
1845                 for (i = 0; i < n; ++i) {
1846                         MonoType *t;
1847                         ainfo = cinfo->args + i;
1848
1849                         in = call->args [i];
1850
1851                         if (sig->hasthis && i == 0)
1852                                 t = &mono_defaults.object_class->byval_arg;
1853                         else
1854                                 t = sig->params [i - sig->hasthis];
1855
1856                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1857                                 if (!t->byref) {
1858                                         if (t->type == MONO_TYPE_R4)
1859                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1860                                         else if (t->type == MONO_TYPE_R8)
1861                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1862                                         else
1863                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1864                                 } else {
1865                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1866                                 }
1867                         }
1868                 }
1869         }
1870
1871         /*
1872          * Emit all parameters passed in registers in non-reverse order for better readability
1873          * and to help the optimization in emit_prolog ().
1874          */
1875         for (i = 0; i < n; ++i) {
1876                 ainfo = cinfo->args + i;
1877
1878                 in = call->args [i];
1879
1880                 if (ainfo->storage == ArgInIReg)
1881                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1882         }
1883
1884         for (i = n - 1; i >= 0; --i) {
1885                 ainfo = cinfo->args + i;
1886
1887                 in = call->args [i];
1888
1889                 switch (ainfo->storage) {
1890                 case ArgInIReg:
1891                         /* Already done */
1892                         break;
1893                 case ArgInFloatSSEReg:
1894                 case ArgInDoubleSSEReg:
1895                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1896                         break;
1897                 case ArgOnStack:
1898                 case ArgValuetypeInReg:
1899                 case ArgValuetypeAddrInIReg:
1900                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1901                                 MonoInst *call_inst = (MonoInst*)call;
1902                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1903                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1904                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1905                                 guint32 align;
1906                                 guint32 size;
1907
1908                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1909                                         size = sizeof (MonoTypedRef);
1910                                         align = sizeof (gpointer);
1911                                 }
1912                                 else {
1913                                         if (sig->pinvoke)
1914                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1915                                         else {
1916                                                 /*
1917                                                  * Other backends use mono_type_stack_size (), but that
1918                                                  * aligns the size to 8, which is larger than the size of
1919                                                  * the source, leading to reads of invalid memory if the
1920                                                  * source is at the end of address space.
1921                                                  */
1922                                                 size = mono_class_value_size (in->klass, &align);
1923                                         }
1924                                 }
1925                                 g_assert (in->klass);
1926
1927                                 if (size > 0) {
1928                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1929                                         arg->sreg1 = in->dreg;
1930                                         arg->klass = in->klass;
1931                                         arg->backend.size = size;
1932                                         arg->inst_p0 = call;
1933                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1934                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1935
1936                                         MONO_ADD_INS (cfg->cbb, arg);
1937                                 }
1938                         } else {
1939                                 if (cfg->arch.no_pushes) {
1940                                         /* Already done */
1941                                 } else {
1942                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1943                                         arg->sreg1 = in->dreg;
1944                                         if (!sig->params [i - sig->hasthis]->byref) {
1945                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1946                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1947                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
1948                                                         arg->inst_destbasereg = X86_ESP;
1949                                                         arg->inst_offset = 0;
1950                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1951                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1952                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
1953                                                         arg->inst_destbasereg = X86_ESP;
1954                                                         arg->inst_offset = 0;
1955                                                 }
1956                                         }
1957                                         MONO_ADD_INS (cfg->cbb, arg);
1958                                 }
1959                         }
1960                         break;
1961                 default:
1962                         g_assert_not_reached ();
1963                 }
1964
1965                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1966                         /* Emit the signature cookie just before the implicit arguments */
1967                         emit_sig_cookie (cfg, call, cinfo);
1968         }
1969
1970         /* Handle the case where there are no implicit arguments */
1971         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1972                 emit_sig_cookie (cfg, call, cinfo);
1973
1974         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1975                 MonoInst *vtarg;
1976
1977                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1978                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1979                                 /*
1980                                  * Tell the JIT to use a more efficient calling convention: call using
1981                                  * OP_CALL, compute the result location after the call, and save the
1982                                  * result there.
1983                                  */
1984                                 call->vret_in_reg = TRUE;
1985                                 /*
1986                                  * Nullify the instruction computing the vret addr to enable
1987                                  * future optimizations.
1988                                  */
1989                                 if (call->vret_var)
1990                                         NULLIFY_INS (call->vret_var);
1991                         } else {
1992                                 if (call->tail_call)
1993                                         NOT_IMPLEMENTED;
1994                                 /*
1995                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1996                                  * the stack. Push the address here, so the call instruction can
1997                                  * access it.
1998                                  */
1999                                 if (!cfg->arch.vret_addr_loc) {
2000                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2001                                         /* Prevent it from being register allocated or optimized away */
2002                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2003                                 }
2004
2005                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2006                         }
2007                 }
2008                 else {
2009                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2010                         vtarg->sreg1 = call->vret_var->dreg;
2011                         vtarg->dreg = mono_alloc_preg (cfg);
2012                         MONO_ADD_INS (cfg->cbb, vtarg);
2013
2014                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2015                 }
2016         }
2017
2018 #ifdef PLATFORM_WIN32
2019         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2020                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2021         }
2022 #endif
2023
2024         if (cfg->method->save_lmf) {
2025                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2026                 MONO_ADD_INS (cfg->cbb, arg);
2027         }
2028
2029         call->stack_usage = cinfo->stack_usage;
2030 }
2031
2032 void
2033 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2034 {
2035         MonoInst *arg;
2036         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2037         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2038         int size = ins->backend.size;
2039
2040         if (ainfo->storage == ArgValuetypeInReg) {
2041                 MonoInst *load;
2042                 int part;
2043
2044                 for (part = 0; part < 2; ++part) {
2045                         if (ainfo->pair_storage [part] == ArgNone)
2046                                 continue;
2047
2048                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2049                         load->inst_basereg = src->dreg;
2050                         load->inst_offset = part * sizeof (gpointer);
2051
2052                         switch (ainfo->pair_storage [part]) {
2053                         case ArgInIReg:
2054                                 load->dreg = mono_alloc_ireg (cfg);
2055                                 break;
2056                         case ArgInDoubleSSEReg:
2057                         case ArgInFloatSSEReg:
2058                                 load->dreg = mono_alloc_freg (cfg);
2059                                 break;
2060                         default:
2061                                 g_assert_not_reached ();
2062                         }
2063                         MONO_ADD_INS (cfg->cbb, load);
2064
2065                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2066                 }
2067         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2068                 MonoInst *vtaddr, *load;
2069                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2070
2071                 g_assert (!cfg->arch.no_pushes);
2072
2073                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2074                 load->inst_p0 = vtaddr;
2075                 vtaddr->flags |= MONO_INST_INDIRECT;
2076                 load->type = STACK_MP;
2077                 load->klass = vtaddr->klass;
2078                 load->dreg = mono_alloc_ireg (cfg);
2079                 MONO_ADD_INS (cfg->cbb, load);
2080                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2081
2082                 if (ainfo->pair_storage [0] == ArgInIReg) {
2083                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2084                         arg->dreg = mono_alloc_ireg (cfg);
2085                         arg->sreg1 = load->dreg;
2086                         arg->inst_imm = 0;
2087                         MONO_ADD_INS (cfg->cbb, arg);
2088                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2089                 } else {
2090                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2091                         arg->sreg1 = load->dreg;
2092                         MONO_ADD_INS (cfg->cbb, arg);
2093                 }
2094         } else {
2095                 if (size == 8) {
2096                         if (cfg->arch.no_pushes) {
2097                                 int dreg = mono_alloc_ireg (cfg);
2098
2099                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2100                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2101                         } else {
2102                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2103                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2104                                 arg->inst_basereg = src->dreg;
2105                                 arg->inst_offset = 0;
2106                                 MONO_ADD_INS (cfg->cbb, arg);
2107                         }
2108                 } else if (size <= 40) {
2109                         if (cfg->arch.no_pushes) {
2110                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2111                         } else {
2112                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2113                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2114                         }
2115                 } else {
2116                         if (cfg->arch.no_pushes) {
2117                                 // FIXME: Code growth
2118                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2119                         } else {
2120                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2121                                 arg->inst_basereg = src->dreg;
2122                                 arg->inst_offset = 0;
2123                                 arg->inst_imm = size;
2124                                 MONO_ADD_INS (cfg->cbb, arg);
2125                         }
2126                 }
2127         }
2128 }
2129
2130 void
2131 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2132 {
2133         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2134
2135         if (!ret->byref) {
2136                 if (ret->type == MONO_TYPE_R4) {
2137                         if (COMPILE_LLVM (cfg))
2138                                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2139                         else
2140                                 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2141                         return;
2142                 } else if (ret->type == MONO_TYPE_R8) {
2143                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2144                         return;
2145                 }
2146         }
2147
2148         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2149 }
2150
2151 #define EMIT_COND_BRANCH(ins,cond,sign) \
2152         if (ins->inst_true_bb->native_offset) { \
2153                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2154         } else { \
2155                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2156                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2157             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2158                         x86_branch8 (code, cond, 0, sign); \
2159                 else \
2160                         x86_branch32 (code, cond, 0, sign); \
2161 }
2162
2163 typedef struct {
2164         MonoMethodSignature *sig;
2165         CallInfo *cinfo;
2166 } ArchDynCallInfo;
2167
2168 typedef struct {
2169         mgreg_t regs [PARAM_REGS];
2170         mgreg_t res;
2171         guint8 *ret;
2172 } DynCallArgs;
2173
2174 static gboolean
2175 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2176 {
2177         int i;
2178
2179 #ifdef PLATFORM_WIN32
2180         return FALSE;
2181 #endif
2182
2183         switch (cinfo->ret.storage) {
2184         case ArgNone:
2185         case ArgInIReg:
2186                 break;
2187         case ArgValuetypeInReg: {
2188                 ArgInfo *ainfo = &cinfo->ret;
2189
2190                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2191                         return FALSE;
2192                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2193                         return FALSE;
2194                 break;
2195         }
2196         default:
2197                 return FALSE;
2198         }
2199
2200         for (i = 0; i < cinfo->nargs; ++i) {
2201                 ArgInfo *ainfo = &cinfo->args [i];
2202                 switch (ainfo->storage) {
2203                 case ArgInIReg:
2204                         break;
2205                 case ArgValuetypeInReg:
2206                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2207                                 return FALSE;
2208                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2209                                 return FALSE;
2210                         break;
2211                 default:
2212                         return FALSE;
2213                 }
2214         }
2215
2216         return TRUE;
2217 }
2218
2219 /*
2220  * mono_arch_dyn_call_prepare:
2221  *
2222  *   Return a pointer to an arch-specific structure which contains information
2223  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2224  * supported for SIG.
2225  * This function is equivalent to ffi_prep_cif in libffi.
2226  */
2227 MonoDynCallInfo*
2228 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2229 {
2230         ArchDynCallInfo *info;
2231         CallInfo *cinfo;
2232
2233         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2234
2235         if (!dyn_call_supported (sig, cinfo)) {
2236                 g_free (cinfo);
2237                 return NULL;
2238         }
2239
2240         info = g_new0 (ArchDynCallInfo, 1);
2241         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2242         info->sig = sig;
2243         info->cinfo = cinfo;
2244
2245         return (MonoDynCallInfo*)info;
2246 }
2247
2248 /*
2249  * mono_arch_dyn_call_free:
2250  *
2251  *   Free a MonoDynCallInfo structure.
2252  */
2253 void
2254 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2255 {
2256         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2257
2258         g_free (ainfo->cinfo);
2259         g_free (ainfo);
2260 }
2261
2262 /*
2263  * mono_arch_get_start_dyn_call:
2264  *
2265  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2266  * store the result into BUF.
2267  * ARGS should be an array of pointers pointing to the arguments.
2268  * RET should point to a memory buffer large enought to hold the result of the
2269  * call.
2270  * This function should be as fast as possible, any work which does not depend
2271  * on the actual values of the arguments should be done in
2272  * mono_arch_dyn_call_prepare ().
2273  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2274  * libffi.
2275  */
2276 void
2277 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2278 {
2279         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2280         DynCallArgs *p = (DynCallArgs*)buf;
2281         int arg_index, greg, i;
2282         MonoMethodSignature *sig = dinfo->sig;
2283
2284         g_assert (buf_len >= sizeof (DynCallArgs));
2285
2286         p->res = 0;
2287         p->ret = ret;
2288
2289         arg_index = 0;
2290         greg = 0;
2291
2292         if (dinfo->cinfo->vtype_retaddr)
2293                 p->regs [greg ++] = (mgreg_t)ret;
2294
2295         if (sig->hasthis) {
2296                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2297         }
2298
2299         for (i = 0; i < sig->param_count; i++) {
2300                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2301                 gpointer *arg = args [arg_index ++];
2302
2303                 if (t->byref) {
2304                         p->regs [greg ++] = (mgreg_t)*(arg);
2305                         continue;
2306                 }
2307
2308                 switch (t->type) {
2309                 case MONO_TYPE_STRING:
2310                 case MONO_TYPE_CLASS:
2311                 case MONO_TYPE_ARRAY:
2312                 case MONO_TYPE_SZARRAY:
2313                 case MONO_TYPE_OBJECT:
2314                 case MONO_TYPE_PTR:
2315                 case MONO_TYPE_I:
2316                 case MONO_TYPE_U:
2317                 case MONO_TYPE_I8:
2318                 case MONO_TYPE_U8:
2319                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2320                         p->regs [greg ++] = (mgreg_t)*(arg);
2321                         break;
2322                 case MONO_TYPE_BOOLEAN:
2323                 case MONO_TYPE_U1:
2324                         p->regs [greg ++] = *(guint8*)(arg);
2325                         break;
2326                 case MONO_TYPE_I1:
2327                         p->regs [greg ++] = *(gint8*)(arg);
2328                         break;
2329                 case MONO_TYPE_I2:
2330                         p->regs [greg ++] = *(gint16*)(arg);
2331                         break;
2332                 case MONO_TYPE_U2:
2333                 case MONO_TYPE_CHAR:
2334                         p->regs [greg ++] = *(guint16*)(arg);
2335                         break;
2336                 case MONO_TYPE_I4:
2337                         p->regs [greg ++] = *(gint32*)(arg);
2338                         break;
2339                 case MONO_TYPE_U4:
2340                         p->regs [greg ++] = *(guint32*)(arg);
2341                         break;
2342                 case MONO_TYPE_GENERICINST:
2343                     if (MONO_TYPE_IS_REFERENCE (t)) {
2344                                 p->regs [greg ++] = (mgreg_t)*(arg);
2345                                 break;
2346                         } else {
2347                                 /* Fall through */
2348                         }
2349                 case MONO_TYPE_VALUETYPE: {
2350                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2351
2352                         g_assert (ainfo->storage == ArgValuetypeInReg);
2353                         if (ainfo->pair_storage [0] != ArgNone) {
2354                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2355                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2356                         }
2357                         if (ainfo->pair_storage [1] != ArgNone) {
2358                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2359                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2360                         }
2361                         break;
2362                 }
2363                 default:
2364                         g_assert_not_reached ();
2365                 }
2366         }
2367
2368         g_assert (greg <= PARAM_REGS);
2369 }
2370
2371 /*
2372  * mono_arch_finish_dyn_call:
2373  *
2374  *   Store the result of a dyn call into the return value buffer passed to
2375  * start_dyn_call ().
2376  * This function should be as fast as possible, any work which does not depend
2377  * on the actual values of the arguments should be done in
2378  * mono_arch_dyn_call_prepare ().
2379  */
2380 void
2381 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2382 {
2383         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2384         MonoMethodSignature *sig = dinfo->sig;
2385         guint8 *ret = ((DynCallArgs*)buf)->ret;
2386         mgreg_t res = ((DynCallArgs*)buf)->res;
2387
2388         switch (mono_type_get_underlying_type (sig->ret)->type) {
2389         case MONO_TYPE_VOID:
2390                 *(gpointer*)ret = NULL;
2391                 break;
2392         case MONO_TYPE_STRING:
2393         case MONO_TYPE_CLASS:
2394         case MONO_TYPE_ARRAY:
2395         case MONO_TYPE_SZARRAY:
2396         case MONO_TYPE_OBJECT:
2397         case MONO_TYPE_I:
2398         case MONO_TYPE_U:
2399         case MONO_TYPE_PTR:
2400                 *(gpointer*)ret = (gpointer)res;
2401                 break;
2402         case MONO_TYPE_I1:
2403                 *(gint8*)ret = res;
2404                 break;
2405         case MONO_TYPE_U1:
2406         case MONO_TYPE_BOOLEAN:
2407                 *(guint8*)ret = res;
2408                 break;
2409         case MONO_TYPE_I2:
2410                 *(gint16*)ret = res;
2411                 break;
2412         case MONO_TYPE_U2:
2413         case MONO_TYPE_CHAR:
2414                 *(guint16*)ret = res;
2415                 break;
2416         case MONO_TYPE_I4:
2417                 *(gint32*)ret = res;
2418                 break;
2419         case MONO_TYPE_U4:
2420                 *(guint32*)ret = res;
2421                 break;
2422         case MONO_TYPE_I8:
2423                 *(gint64*)ret = res;
2424                 break;
2425         case MONO_TYPE_U8:
2426                 *(guint64*)ret = res;
2427                 break;
2428         case MONO_TYPE_GENERICINST:
2429                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2430                         *(gpointer*)ret = (gpointer)res;
2431                         break;
2432                 } else {
2433                         /* Fall through */
2434                 }
2435         case MONO_TYPE_VALUETYPE:
2436                 if (dinfo->cinfo->vtype_retaddr) {
2437                         /* Nothing to do */
2438                 } else {
2439                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2440
2441                         g_assert (ainfo->storage == ArgValuetypeInReg);
2442
2443                         if (ainfo->pair_storage [0] != ArgNone) {
2444                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2445                                 ((mgreg_t*)ret)[0] = res;
2446                         }
2447
2448                         g_assert (ainfo->pair_storage [1] == ArgNone);
2449                 }
2450                 break;
2451         default:
2452                 g_assert_not_reached ();
2453         }
2454 }
2455
2456 /* emit an exception if condition is fail */
2457 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2458         do {                                                        \
2459                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2460                 if (tins == NULL) {                                                                             \
2461                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2462                                         MONO_PATCH_INFO_EXC, exc_name);  \
2463                         x86_branch32 (code, cond, 0, signed);               \
2464                 } else {        \
2465                         EMIT_COND_BRANCH (tins, cond, signed);  \
2466                 }                       \
2467         } while (0);
2468
2469 #define EMIT_FPCOMPARE(code) do { \
2470         amd64_fcompp (code); \
2471         amd64_fnstsw (code); \
2472 } while (0);
2473
2474 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2475     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2476         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2477         amd64_ ##op (code); \
2478         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2479         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2480 } while (0);
2481
2482 static guint8*
2483 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2484 {
2485         gboolean no_patch = FALSE;
2486
2487         /*
2488          * FIXME: Add support for thunks
2489          */
2490         {
2491                 gboolean near_call = FALSE;
2492
2493                 /*
2494                  * Indirect calls are expensive so try to make a near call if possible.
2495                  * The caller memory is allocated by the code manager so it is
2496                  * guaranteed to be at a 32 bit offset.
2497                  */
2498
2499                 if (patch_type != MONO_PATCH_INFO_ABS) {
2500                         /* The target is in memory allocated using the code manager */
2501                         near_call = TRUE;
2502
2503                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2504                                 if (((MonoMethod*)data)->klass->image->aot_module)
2505                                         /* The callee might be an AOT method */
2506                                         near_call = FALSE;
2507                                 if (((MonoMethod*)data)->dynamic)
2508                                         /* The target is in malloc-ed memory */
2509                                         near_call = FALSE;
2510                         }
2511
2512                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2513                                 /*
2514                                  * The call might go directly to a native function without
2515                                  * the wrapper.
2516                                  */
2517                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2518                                 if (mi) {
2519                                         gconstpointer target = mono_icall_get_wrapper (mi);
2520                                         if ((((guint64)target) >> 32) != 0)
2521                                                 near_call = FALSE;
2522                                 }
2523                         }
2524                 }
2525                 else {
2526                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2527                                 /*
2528                                  * This is not really an optimization, but required because the
2529                                  * generic class init trampolines use R11 to pass the vtable.
2530                                  */
2531                                 near_call = TRUE;
2532                         } else {
2533                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2534                                 if (info) {
2535                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2536                                                 strstr (cfg->method->name, info->name)) {
2537                                                 /* A call to the wrapped function */
2538                                                 if ((((guint64)data) >> 32) == 0)
2539                                                         near_call = TRUE;
2540                                                 no_patch = TRUE;
2541                                         }
2542                                         else if (info->func == info->wrapper) {
2543                                                 /* No wrapper */
2544                                                 if ((((guint64)info->func) >> 32) == 0)
2545                                                         near_call = TRUE;
2546                                         }
2547                                         else {
2548                                                 /* See the comment in mono_codegen () */
2549                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2550                                                         near_call = TRUE;
2551                                         }
2552                                 }
2553                                 else if ((((guint64)data) >> 32) == 0) {
2554                                         near_call = TRUE;
2555                                         no_patch = TRUE;
2556                                 }
2557                         }
2558                 }
2559
2560                 if (cfg->method->dynamic)
2561                         /* These methods are allocated using malloc */
2562                         near_call = FALSE;
2563
2564                 if (cfg->compile_aot) {
2565                         near_call = TRUE;
2566                         no_patch = TRUE;
2567                 }
2568
2569 #ifdef MONO_ARCH_NOMAP32BIT
2570                 near_call = FALSE;
2571 #endif
2572
2573                 if (near_call) {
2574                         /*
2575                          * Align the call displacement to an address divisible by 4 so it does
2576                          * not span cache lines. This is required for code patching to work on SMP
2577                          * systems.
2578                          */
2579                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2580                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2581                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2582                         amd64_call_code (code, 0);
2583                 }
2584                 else {
2585                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2586                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2587                         amd64_call_reg (code, GP_SCRATCH_REG);
2588                 }
2589         }
2590
2591         return code;
2592 }
2593
2594 static inline guint8*
2595 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2596 {
2597 #ifdef PLATFORM_WIN32
2598         if (win64_adjust_stack)
2599                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2600 #endif
2601         code = emit_call_body (cfg, code, patch_type, data);
2602 #ifdef PLATFORM_WIN32
2603         if (win64_adjust_stack)
2604                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2605 #endif
2606
2607         return code;
2608 }
2609
2610 static inline int
2611 store_membase_imm_to_store_membase_reg (int opcode)
2612 {
2613         switch (opcode) {
2614         case OP_STORE_MEMBASE_IMM:
2615                 return OP_STORE_MEMBASE_REG;
2616         case OP_STOREI4_MEMBASE_IMM:
2617                 return OP_STOREI4_MEMBASE_REG;
2618         case OP_STOREI8_MEMBASE_IMM:
2619                 return OP_STOREI8_MEMBASE_REG;
2620         }
2621
2622         return -1;
2623 }
2624
2625 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2626
2627 /*
2628  * mono_arch_peephole_pass_1:
2629  *
2630  *   Perform peephole opts which should/can be performed before local regalloc
2631  */
2632 void
2633 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2634 {
2635         MonoInst *ins, *n;
2636
2637         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2638                 MonoInst *last_ins = ins->prev;
2639
2640                 switch (ins->opcode) {
2641                 case OP_ADD_IMM:
2642                 case OP_IADD_IMM:
2643                 case OP_LADD_IMM:
2644                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2645                                 /*
2646                                  * X86_LEA is like ADD, but doesn't have the
2647                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2648                                  * its operand to 64 bit.
2649                                  */
2650                                 ins->opcode = OP_X86_LEA_MEMBASE;
2651                                 ins->inst_basereg = ins->sreg1;
2652                         }
2653                         break;
2654                 case OP_LXOR:
2655                 case OP_IXOR:
2656                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2657                                 MonoInst *ins2;
2658
2659                                 /*
2660                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2661                                  * the latter has length 2-3 instead of 6 (reverse constant
2662                                  * propagation). These instruction sequences are very common
2663                                  * in the initlocals bblock.
2664                                  */
2665                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2666                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2667                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2668                                                 ins2->sreg1 = ins->dreg;
2669                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2670                                                 /* Continue */
2671                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2672                                                 NULLIFY_INS (ins2);
2673                                                 /* Continue */
2674                                         } else {
2675                                                 break;
2676                                         }
2677                                 }
2678                         }
2679                         break;
2680                 case OP_COMPARE_IMM:
2681                 case OP_LCOMPARE_IMM:
2682                         /* OP_COMPARE_IMM (reg, 0)
2683                          * -->
2684                          * OP_AMD64_TEST_NULL (reg)
2685                          */
2686                         if (!ins->inst_imm)
2687                                 ins->opcode = OP_AMD64_TEST_NULL;
2688                         break;
2689                 case OP_ICOMPARE_IMM:
2690                         if (!ins->inst_imm)
2691                                 ins->opcode = OP_X86_TEST_NULL;
2692                         break;
2693                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2694                         /*
2695                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2696                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2697                          * -->
2698                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2699                          * OP_COMPARE_IMM reg, imm
2700                          *
2701                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2702                          */
2703                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2704                             ins->inst_basereg == last_ins->inst_destbasereg &&
2705                             ins->inst_offset == last_ins->inst_offset) {
2706                                         ins->opcode = OP_ICOMPARE_IMM;
2707                                         ins->sreg1 = last_ins->sreg1;
2708
2709                                         /* check if we can remove cmp reg,0 with test null */
2710                                         if (!ins->inst_imm)
2711                                                 ins->opcode = OP_X86_TEST_NULL;
2712                                 }
2713
2714                         break;
2715                 }
2716
2717                 mono_peephole_ins (bb, ins);
2718         }
2719 }
2720
2721 void
2722 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2723 {
2724         MonoInst *ins, *n;
2725
2726         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2727                 switch (ins->opcode) {
2728                 case OP_ICONST:
2729                 case OP_I8CONST: {
2730                         /* reg = 0 -> XOR (reg, reg) */
2731                         /* XOR sets cflags on x86, so we cant do it always */
2732                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2733                                 ins->opcode = OP_LXOR;
2734                                 ins->sreg1 = ins->dreg;
2735                                 ins->sreg2 = ins->dreg;
2736                                 /* Fall through */
2737                         } else {
2738                                 break;
2739                         }
2740                 }
2741                 case OP_LXOR:
2742                         /*
2743                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2744                          * 0 result into 64 bits.
2745                          */
2746                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2747                                 ins->opcode = OP_IXOR;
2748                         }
2749                         /* Fall through */
2750                 case OP_IXOR:
2751                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2752                                 MonoInst *ins2;
2753
2754                                 /*
2755                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2756                                  * the latter has length 2-3 instead of 6 (reverse constant
2757                                  * propagation). These instruction sequences are very common
2758                                  * in the initlocals bblock.
2759                                  */
2760                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2761                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2762                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2763                                                 ins2->sreg1 = ins->dreg;
2764                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2765                                                 /* Continue */
2766                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2767                                                 NULLIFY_INS (ins2);
2768                                                 /* Continue */
2769                                         } else {
2770                                                 break;
2771                                         }
2772                                 }
2773                         }
2774                         break;
2775                 case OP_IADD_IMM:
2776                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2777                                 ins->opcode = OP_X86_INC_REG;
2778                         break;
2779                 case OP_ISUB_IMM:
2780                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2781                                 ins->opcode = OP_X86_DEC_REG;
2782                         break;
2783                 }
2784
2785                 mono_peephole_ins (bb, ins);
2786         }
2787 }
2788
2789 #define NEW_INS(cfg,ins,dest,op) do {   \
2790                 MONO_INST_NEW ((cfg), (dest), (op)); \
2791         (dest)->cil_code = (ins)->cil_code; \
2792         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2793         } while (0)
2794
2795 /*
2796  * mono_arch_lowering_pass:
2797  *
2798  *  Converts complex opcodes into simpler ones so that each IR instruction
2799  * corresponds to one machine instruction.
2800  */
2801 void
2802 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2803 {
2804         MonoInst *ins, *n, *temp;
2805
2806         /*
2807          * FIXME: Need to add more instructions, but the current machine
2808          * description can't model some parts of the composite instructions like
2809          * cdq.
2810          */
2811         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2812                 switch (ins->opcode) {
2813                 case OP_DIV_IMM:
2814                 case OP_REM_IMM:
2815                 case OP_IDIV_IMM:
2816                 case OP_IDIV_UN_IMM:
2817                 case OP_IREM_UN_IMM:
2818                         mono_decompose_op_imm (cfg, bb, ins);
2819                         break;
2820                 case OP_IREM_IMM:
2821                         /* Keep the opcode if we can implement it efficiently */
2822                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2823                                 mono_decompose_op_imm (cfg, bb, ins);
2824                         break;
2825                 case OP_COMPARE_IMM:
2826                 case OP_LCOMPARE_IMM:
2827                         if (!amd64_is_imm32 (ins->inst_imm)) {
2828                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2829                                 temp->inst_c0 = ins->inst_imm;
2830                                 temp->dreg = mono_alloc_ireg (cfg);
2831                                 ins->opcode = OP_COMPARE;
2832                                 ins->sreg2 = temp->dreg;
2833                         }
2834                         break;
2835                 case OP_LOAD_MEMBASE:
2836                 case OP_LOADI8_MEMBASE:
2837                         if (!amd64_is_imm32 (ins->inst_offset)) {
2838                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2839                                 temp->inst_c0 = ins->inst_offset;
2840                                 temp->dreg = mono_alloc_ireg (cfg);
2841                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2842                                 ins->inst_indexreg = temp->dreg;
2843                         }
2844                         break;
2845                 case OP_STORE_MEMBASE_IMM:
2846                 case OP_STOREI8_MEMBASE_IMM:
2847                         if (!amd64_is_imm32 (ins->inst_imm)) {
2848                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2849                                 temp->inst_c0 = ins->inst_imm;
2850                                 temp->dreg = mono_alloc_ireg (cfg);
2851                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2852                                 ins->sreg1 = temp->dreg;
2853                         }
2854                         break;
2855 #ifdef MONO_ARCH_SIMD_INTRINSICS
2856                 case OP_EXPAND_I1: {
2857                                 int temp_reg1 = mono_alloc_ireg (cfg);
2858                                 int temp_reg2 = mono_alloc_ireg (cfg);
2859                                 int original_reg = ins->sreg1;
2860
2861                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2862                                 temp->sreg1 = original_reg;
2863                                 temp->dreg = temp_reg1;
2864
2865                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2866                                 temp->sreg1 = temp_reg1;
2867                                 temp->dreg = temp_reg2;
2868                                 temp->inst_imm = 8;
2869
2870                                 NEW_INS (cfg, ins, temp, OP_LOR);
2871                                 temp->sreg1 = temp->dreg = temp_reg2;
2872                                 temp->sreg2 = temp_reg1;
2873
2874                                 ins->opcode = OP_EXPAND_I2;
2875                                 ins->sreg1 = temp_reg2;
2876                         }
2877                         break;
2878 #endif
2879                 default:
2880                         break;
2881                 }
2882         }
2883
2884         bb->max_vreg = cfg->next_vreg;
2885 }
2886
2887 static const int
2888 branch_cc_table [] = {
2889         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2890         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2891         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2892 };
2893
2894 /* Maps CMP_... constants to X86_CC_... constants */
2895 static const int
2896 cc_table [] = {
2897         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2898         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2899 };
2900
2901 static const int
2902 cc_signed_table [] = {
2903         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2904         FALSE, FALSE, FALSE, FALSE
2905 };
2906
2907 /*#include "cprop.c"*/
2908
2909 static unsigned char*
2910 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2911 {
2912         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2913
2914         if (size == 1)
2915                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2916         else if (size == 2)
2917                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2918         return code;
2919 }
2920
2921 static unsigned char*
2922 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2923 {
2924         int sreg = tree->sreg1;
2925         int need_touch = FALSE;
2926
2927 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2928         if (!tree->flags & MONO_INST_INIT)
2929                 need_touch = TRUE;
2930 #endif
2931
2932         if (need_touch) {
2933                 guint8* br[5];
2934
2935                 /*
2936                  * Under Windows:
2937                  * If requested stack size is larger than one page,
2938                  * perform stack-touch operation
2939                  */
2940                 /*
2941                  * Generate stack probe code.
2942                  * Under Windows, it is necessary to allocate one page at a time,
2943                  * "touching" stack after each successful sub-allocation. This is
2944                  * because of the way stack growth is implemented - there is a
2945                  * guard page before the lowest stack page that is currently commited.
2946                  * Stack normally grows sequentially so OS traps access to the
2947                  * guard page and commits more pages when needed.
2948                  */
2949                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2950                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2951
2952                 br[2] = code; /* loop */
2953                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2954                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2955                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2956                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2957                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2958                 amd64_patch (br[3], br[2]);
2959                 amd64_test_reg_reg (code, sreg, sreg);
2960                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2961                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2962
2963                 br[1] = code; x86_jump8 (code, 0);
2964
2965                 amd64_patch (br[0], code);
2966                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2967                 amd64_patch (br[1], code);
2968                 amd64_patch (br[4], code);
2969         }
2970         else
2971                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2972
2973         if (tree->flags & MONO_INST_INIT) {
2974                 int offset = 0;
2975                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2976                         amd64_push_reg (code, AMD64_RAX);
2977                         offset += 8;
2978                 }
2979                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2980                         amd64_push_reg (code, AMD64_RCX);
2981                         offset += 8;
2982                 }
2983                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2984                         amd64_push_reg (code, AMD64_RDI);
2985                         offset += 8;
2986                 }
2987
2988                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2989                 if (sreg != AMD64_RCX)
2990                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2991                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2992
2993                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2994                 if (cfg->param_area && cfg->arch.no_pushes)
2995                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
2996                 amd64_cld (code);
2997                 amd64_prefix (code, X86_REP_PREFIX);
2998                 amd64_stosl (code);
2999
3000                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3001                         amd64_pop_reg (code, AMD64_RDI);
3002                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3003                         amd64_pop_reg (code, AMD64_RCX);
3004                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3005                         amd64_pop_reg (code, AMD64_RAX);
3006         }
3007         return code;
3008 }
3009
3010 static guint8*
3011 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3012 {
3013         CallInfo *cinfo;
3014         guint32 quad;
3015
3016         /* Move return value to the target register */
3017         /* FIXME: do this in the local reg allocator */
3018         switch (ins->opcode) {
3019         case OP_CALL:
3020         case OP_CALL_REG:
3021         case OP_CALL_MEMBASE:
3022         case OP_LCALL:
3023         case OP_LCALL_REG:
3024         case OP_LCALL_MEMBASE:
3025                 g_assert (ins->dreg == AMD64_RAX);
3026                 break;
3027         case OP_FCALL:
3028         case OP_FCALL_REG:
3029         case OP_FCALL_MEMBASE:
3030                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3031                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3032                 }
3033                 else {
3034                         if (ins->dreg != AMD64_XMM0)
3035                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3036                 }
3037                 break;
3038         case OP_VCALL:
3039         case OP_VCALL_REG:
3040         case OP_VCALL_MEMBASE:
3041         case OP_VCALL2:
3042         case OP_VCALL2_REG:
3043         case OP_VCALL2_MEMBASE:
3044                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3045                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3046                         MonoInst *loc = cfg->arch.vret_addr_loc;
3047
3048                         /* Load the destination address */
3049                         g_assert (loc->opcode == OP_REGOFFSET);
3050                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3051
3052                         for (quad = 0; quad < 2; quad ++) {
3053                                 switch (cinfo->ret.pair_storage [quad]) {
3054                                 case ArgInIReg:
3055                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3056                                         break;
3057                                 case ArgInFloatSSEReg:
3058                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3059                                         break;
3060                                 case ArgInDoubleSSEReg:
3061                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3062                                         break;
3063                                 case ArgNone:
3064                                         break;
3065                                 default:
3066                                         NOT_IMPLEMENTED;
3067                                 }
3068                         }
3069                 }
3070                 break;
3071         }
3072
3073         return code;
3074 }
3075
3076 /*
3077  * mono_amd64_emit_tls_get:
3078  * @code: buffer to store code to
3079  * @dreg: hard register where to place the result
3080  * @tls_offset: offset info
3081  *
3082  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3083  * the dreg register the item in the thread local storage identified
3084  * by tls_offset.
3085  *
3086  * Returns: a pointer to the end of the stored code
3087  */
3088 guint8*
3089 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3090 {
3091 #ifdef PLATFORM_WIN32
3092         g_assert (tls_offset < 64);
3093         x86_prefix (code, X86_GS_PREFIX);
3094         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3095 #else
3096         if (optimize_for_xen) {
3097                 x86_prefix (code, X86_FS_PREFIX);
3098                 amd64_mov_reg_mem (code, dreg, 0, 8);
3099                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3100         } else {
3101                 x86_prefix (code, X86_FS_PREFIX);
3102                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3103         }
3104 #endif
3105         return code;
3106 }
3107
3108 #define REAL_PRINT_REG(text,reg) \
3109 mono_assert (reg >= 0); \
3110 amd64_push_reg (code, AMD64_RAX); \
3111 amd64_push_reg (code, AMD64_RDX); \
3112 amd64_push_reg (code, AMD64_RCX); \
3113 amd64_push_reg (code, reg); \
3114 amd64_push_imm (code, reg); \
3115 amd64_push_imm (code, text " %d %p\n"); \
3116 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3117 amd64_call_reg (code, AMD64_RAX); \
3118 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3119 amd64_pop_reg (code, AMD64_RCX); \
3120 amd64_pop_reg (code, AMD64_RDX); \
3121 amd64_pop_reg (code, AMD64_RAX);
3122
3123 /* benchmark and set based on cpu */
3124 #define LOOP_ALIGNMENT 8
3125 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3126
3127 #ifndef DISABLE_JIT
3128
3129 void
3130 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3131 {
3132         MonoInst *ins;
3133         MonoCallInst *call;
3134         guint offset;
3135         guint8 *code = cfg->native_code + cfg->code_len;
3136         MonoInst *last_ins = NULL;
3137         guint last_offset = 0;
3138         int max_len;
3139
3140         /* Fix max_offset estimate for each successor bb */
3141         if (cfg->opt & MONO_OPT_BRANCH) {
3142                 int current_offset = cfg->code_len;
3143                 MonoBasicBlock *current_bb;
3144                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3145                         current_bb->max_offset = current_offset;
3146                         current_offset += current_bb->max_length;
3147                 }
3148         }
3149
3150         if (cfg->opt & MONO_OPT_LOOP) {
3151                 int pad, align = LOOP_ALIGNMENT;
3152                 /* set alignment depending on cpu */
3153                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3154                         pad = align - pad;
3155                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3156                         amd64_padding (code, pad);
3157                         cfg->code_len += pad;
3158                         bb->native_offset = cfg->code_len;
3159                 }
3160         }
3161
3162         if (cfg->verbose_level > 2)
3163                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3164
3165         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3166                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3167                 g_assert (!cfg->compile_aot);
3168
3169                 cov->data [bb->dfn].cil_code = bb->cil_code;
3170                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3171                 /* this is not thread save, but good enough */
3172                 amd64_inc_membase (code, AMD64_R11, 0);
3173         }
3174
3175         offset = code - cfg->native_code;
3176
3177         mono_debug_open_block (cfg, bb, offset);
3178
3179     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3180                 x86_breakpoint (code);
3181
3182         MONO_BB_FOR_EACH_INS (bb, ins) {
3183                 offset = code - cfg->native_code;
3184
3185                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3186
3187                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3188                         cfg->code_size *= 2;
3189                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3190                         code = cfg->native_code + offset;
3191                         mono_jit_stats.code_reallocs++;
3192                 }
3193
3194                 if (cfg->debug_info)
3195                         mono_debug_record_line_number (cfg, ins, offset);
3196
3197                 switch (ins->opcode) {
3198                 case OP_BIGMUL:
3199                         amd64_mul_reg (code, ins->sreg2, TRUE);
3200                         break;
3201                 case OP_BIGMUL_UN:
3202                         amd64_mul_reg (code, ins->sreg2, FALSE);
3203                         break;
3204                 case OP_X86_SETEQ_MEMBASE:
3205                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3206                         break;
3207                 case OP_STOREI1_MEMBASE_IMM:
3208                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3209                         break;
3210                 case OP_STOREI2_MEMBASE_IMM:
3211                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3212                         break;
3213                 case OP_STOREI4_MEMBASE_IMM:
3214                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3215                         break;
3216                 case OP_STOREI1_MEMBASE_REG:
3217                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3218                         break;
3219                 case OP_STOREI2_MEMBASE_REG:
3220                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3221                         break;
3222                 case OP_STORE_MEMBASE_REG:
3223                 case OP_STOREI8_MEMBASE_REG:
3224                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3225                         break;
3226                 case OP_STOREI4_MEMBASE_REG:
3227                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3228                         break;
3229                 case OP_STORE_MEMBASE_IMM:
3230                 case OP_STOREI8_MEMBASE_IMM:
3231                         g_assert (amd64_is_imm32 (ins->inst_imm));
3232                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3233                         break;
3234                 case OP_LOAD_MEM:
3235                 case OP_LOADI8_MEM:
3236                         // FIXME: Decompose this earlier
3237                         if (amd64_is_imm32 (ins->inst_imm))
3238                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3239                         else {
3240                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3241                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3242                         }
3243                         break;
3244                 case OP_LOADI4_MEM:
3245                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3246                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3247                         break;
3248                 case OP_LOADU4_MEM:
3249                         // FIXME: Decompose this earlier
3250                         if (amd64_is_imm32 (ins->inst_imm))
3251                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3252                         else {
3253                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3254                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3255                         }
3256                         break;
3257                 case OP_LOADU1_MEM:
3258                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3259                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3260                         break;
3261                 case OP_LOADU2_MEM:
3262                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3263                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3264                         break;
3265                 case OP_LOAD_MEMBASE:
3266                 case OP_LOADI8_MEMBASE:
3267                         g_assert (amd64_is_imm32 (ins->inst_offset));
3268                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3269                         break;
3270                 case OP_LOADI4_MEMBASE:
3271                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3272                         break;
3273                 case OP_LOADU4_MEMBASE:
3274                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3275                         break;
3276                 case OP_LOADU1_MEMBASE:
3277                         /* The cpu zero extends the result into 64 bits */
3278                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3279                         break;
3280                 case OP_LOADI1_MEMBASE:
3281                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3282                         break;
3283                 case OP_LOADU2_MEMBASE:
3284                         /* The cpu zero extends the result into 64 bits */
3285                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3286                         break;
3287                 case OP_LOADI2_MEMBASE:
3288                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3289                         break;
3290                 case OP_AMD64_LOADI8_MEMINDEX:
3291                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3292                         break;
3293                 case OP_LCONV_TO_I1:
3294                 case OP_ICONV_TO_I1:
3295                 case OP_SEXT_I1:
3296                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3297                         break;
3298                 case OP_LCONV_TO_I2:
3299                 case OP_ICONV_TO_I2:
3300                 case OP_SEXT_I2:
3301                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3302                         break;
3303                 case OP_LCONV_TO_U1:
3304                 case OP_ICONV_TO_U1:
3305                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3306                         break;
3307                 case OP_LCONV_TO_U2:
3308                 case OP_ICONV_TO_U2:
3309                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3310                         break;
3311                 case OP_ZEXT_I4:
3312                         /* Clean out the upper word */
3313                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3314                         break;
3315                 case OP_SEXT_I4:
3316                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3317                         break;
3318                 case OP_COMPARE:
3319                 case OP_LCOMPARE:
3320                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3321                         break;
3322                 case OP_COMPARE_IMM:
3323                 case OP_LCOMPARE_IMM:
3324                         g_assert (amd64_is_imm32 (ins->inst_imm));
3325                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3326                         break;
3327                 case OP_X86_COMPARE_REG_MEMBASE:
3328                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3329                         break;
3330                 case OP_X86_TEST_NULL:
3331                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3332                         break;
3333                 case OP_AMD64_TEST_NULL:
3334                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3335                         break;
3336
3337                 case OP_X86_ADD_REG_MEMBASE:
3338                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3339                         break;
3340                 case OP_X86_SUB_REG_MEMBASE:
3341                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3342                         break;
3343                 case OP_X86_AND_REG_MEMBASE:
3344                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3345                         break;
3346                 case OP_X86_OR_REG_MEMBASE:
3347                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3348                         break;
3349                 case OP_X86_XOR_REG_MEMBASE:
3350                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3351                         break;
3352
3353                 case OP_X86_ADD_MEMBASE_IMM:
3354                         /* FIXME: Make a 64 version too */
3355                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3356                         break;
3357                 case OP_X86_SUB_MEMBASE_IMM:
3358                         g_assert (amd64_is_imm32 (ins->inst_imm));
3359                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3360                         break;
3361                 case OP_X86_AND_MEMBASE_IMM:
3362                         g_assert (amd64_is_imm32 (ins->inst_imm));
3363                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3364                         break;
3365                 case OP_X86_OR_MEMBASE_IMM:
3366                         g_assert (amd64_is_imm32 (ins->inst_imm));
3367                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3368                         break;
3369                 case OP_X86_XOR_MEMBASE_IMM:
3370                         g_assert (amd64_is_imm32 (ins->inst_imm));
3371                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3372                         break;
3373                 case OP_X86_ADD_MEMBASE_REG:
3374                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3375                         break;
3376                 case OP_X86_SUB_MEMBASE_REG:
3377                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3378                         break;
3379                 case OP_X86_AND_MEMBASE_REG:
3380                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3381                         break;
3382                 case OP_X86_OR_MEMBASE_REG:
3383                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3384                         break;
3385                 case OP_X86_XOR_MEMBASE_REG:
3386                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3387                         break;
3388                 case OP_X86_INC_MEMBASE:
3389                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3390                         break;
3391                 case OP_X86_INC_REG:
3392                         amd64_inc_reg_size (code, ins->dreg, 4);
3393                         break;
3394                 case OP_X86_DEC_MEMBASE:
3395                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3396                         break;
3397                 case OP_X86_DEC_REG:
3398                         amd64_dec_reg_size (code, ins->dreg, 4);
3399                         break;
3400                 case OP_X86_MUL_REG_MEMBASE:
3401                 case OP_X86_MUL_MEMBASE_REG:
3402                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3403                         break;
3404                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3405                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3406                         break;
3407                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3408                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3409                         break;
3410                 case OP_AMD64_COMPARE_MEMBASE_REG:
3411                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3412                         break;
3413                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3414                         g_assert (amd64_is_imm32 (ins->inst_imm));
3415                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3416                         break;
3417                 case OP_X86_COMPARE_MEMBASE8_IMM:
3418                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3419                         break;
3420                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3421                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3422                         break;
3423                 case OP_AMD64_COMPARE_REG_MEMBASE:
3424                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3425                         break;
3426
3427                 case OP_AMD64_ADD_REG_MEMBASE:
3428                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3429                         break;
3430                 case OP_AMD64_SUB_REG_MEMBASE:
3431                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3432                         break;
3433                 case OP_AMD64_AND_REG_MEMBASE:
3434                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3435                         break;
3436                 case OP_AMD64_OR_REG_MEMBASE:
3437                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3438                         break;
3439                 case OP_AMD64_XOR_REG_MEMBASE:
3440                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3441                         break;
3442
3443                 case OP_AMD64_ADD_MEMBASE_REG:
3444                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3445                         break;
3446                 case OP_AMD64_SUB_MEMBASE_REG:
3447                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3448                         break;
3449                 case OP_AMD64_AND_MEMBASE_REG:
3450                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3451                         break;
3452                 case OP_AMD64_OR_MEMBASE_REG:
3453                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3454                         break;
3455                 case OP_AMD64_XOR_MEMBASE_REG:
3456                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3457                         break;
3458
3459                 case OP_AMD64_ADD_MEMBASE_IMM:
3460                         g_assert (amd64_is_imm32 (ins->inst_imm));
3461                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3462                         break;
3463                 case OP_AMD64_SUB_MEMBASE_IMM:
3464                         g_assert (amd64_is_imm32 (ins->inst_imm));
3465                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3466                         break;
3467                 case OP_AMD64_AND_MEMBASE_IMM:
3468                         g_assert (amd64_is_imm32 (ins->inst_imm));
3469                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3470                         break;
3471                 case OP_AMD64_OR_MEMBASE_IMM:
3472                         g_assert (amd64_is_imm32 (ins->inst_imm));
3473                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3474                         break;
3475                 case OP_AMD64_XOR_MEMBASE_IMM:
3476                         g_assert (amd64_is_imm32 (ins->inst_imm));
3477                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3478                         break;
3479
3480                 case OP_BREAK:
3481                         amd64_breakpoint (code);
3482                         break;
3483                 case OP_RELAXED_NOP:
3484                         x86_prefix (code, X86_REP_PREFIX);
3485                         x86_nop (code);
3486                         break;
3487                 case OP_HARD_NOP:
3488                         x86_nop (code);
3489                         break;
3490                 case OP_NOP:
3491                 case OP_DUMMY_USE:
3492                 case OP_DUMMY_STORE:
3493                 case OP_NOT_REACHED:
3494                 case OP_NOT_NULL:
3495                         break;
3496                 case OP_SEQ_POINT: {
3497                         int i, il_offset;
3498
3499                         /*
3500                          * Read from the single stepping trigger page. This will cause a
3501                          * SIGSEGV when single stepping is enabled.
3502                          * We do this _before_ the breakpoint, so single stepping after
3503                          * a breakpoint is hit will step to the next IL offset.
3504                          */
3505                         g_assert (((guint64)ss_trigger_page >> 32) == 0);
3506
3507                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC)
3508                                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3509
3510                         il_offset = ins->inst_imm;
3511
3512                         if (!cfg->seq_points)
3513                                 cfg->seq_points = g_ptr_array_new ();
3514                         g_ptr_array_add (cfg->seq_points, GUINT_TO_POINTER (il_offset));
3515                         g_ptr_array_add (cfg->seq_points, GUINT_TO_POINTER (code - cfg->native_code));
3516                         /*
3517                          * A placeholder for a possible breakpoint inserted by
3518                          * mono_arch_set_breakpoint ().
3519                          */
3520                         for (i = 0; i < BREAKPOINT_SIZE; ++i)
3521                                 x86_nop (code);
3522                         break;
3523                 }
3524                 case OP_ADDCC:
3525                 case OP_LADD:
3526                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3527                         break;
3528                 case OP_ADC:
3529                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3530                         break;
3531                 case OP_ADD_IMM:
3532                 case OP_LADD_IMM:
3533                         g_assert (amd64_is_imm32 (ins->inst_imm));
3534                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3535                         break;
3536                 case OP_ADC_IMM:
3537                         g_assert (amd64_is_imm32 (ins->inst_imm));
3538                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3539                         break;
3540                 case OP_SUBCC:
3541                 case OP_LSUB:
3542                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3543                         break;
3544                 case OP_SBB:
3545                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3546                         break;
3547                 case OP_SUB_IMM:
3548                 case OP_LSUB_IMM:
3549                         g_assert (amd64_is_imm32 (ins->inst_imm));
3550                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3551                         break;
3552                 case OP_SBB_IMM:
3553                         g_assert (amd64_is_imm32 (ins->inst_imm));
3554                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3555                         break;
3556                 case OP_LAND:
3557                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3558                         break;
3559                 case OP_AND_IMM:
3560                 case OP_LAND_IMM:
3561                         g_assert (amd64_is_imm32 (ins->inst_imm));
3562                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3563                         break;
3564                 case OP_LMUL:
3565                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3566                         break;
3567                 case OP_MUL_IMM:
3568                 case OP_LMUL_IMM:
3569                 case OP_IMUL_IMM: {
3570                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3571
3572                         switch (ins->inst_imm) {
3573                         case 2:
3574                                 /* MOV r1, r2 */
3575                                 /* ADD r1, r1 */
3576                                 if (ins->dreg != ins->sreg1)
3577                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3578                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3579                                 break;
3580                         case 3:
3581                                 /* LEA r1, [r2 + r2*2] */
3582                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3583                                 break;
3584                         case 5:
3585                                 /* LEA r1, [r2 + r2*4] */
3586                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3587                                 break;
3588                         case 6:
3589                                 /* LEA r1, [r2 + r2*2] */
3590                                 /* ADD r1, r1          */
3591                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3592                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3593                                 break;
3594                         case 9:
3595                                 /* LEA r1, [r2 + r2*8] */
3596                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3597                                 break;
3598                         case 10:
3599                                 /* LEA r1, [r2 + r2*4] */
3600                                 /* ADD r1, r1          */
3601                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3602                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3603                                 break;
3604                         case 12:
3605                                 /* LEA r1, [r2 + r2*2] */
3606                                 /* SHL r1, 2           */
3607                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3608                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3609                                 break;
3610                         case 25:
3611                                 /* LEA r1, [r2 + r2*4] */
3612                                 /* LEA r1, [r1 + r1*4] */
3613                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3614                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3615                                 break;
3616                         case 100:
3617                                 /* LEA r1, [r2 + r2*4] */
3618                                 /* SHL r1, 2           */
3619                                 /* LEA r1, [r1 + r1*4] */
3620                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3621                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3622                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3623                                 break;
3624                         default:
3625                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3626                                 break;
3627                         }
3628                         break;
3629                 }
3630                 case OP_LDIV:
3631                 case OP_LREM:
3632                         /* Regalloc magic makes the div/rem cases the same */
3633                         if (ins->sreg2 == AMD64_RDX) {
3634                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3635                                 amd64_cdq (code);
3636                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3637                         } else {
3638                                 amd64_cdq (code);
3639                                 amd64_div_reg (code, ins->sreg2, TRUE);
3640                         }
3641                         break;
3642                 case OP_LDIV_UN:
3643                 case OP_LREM_UN:
3644                         if (ins->sreg2 == AMD64_RDX) {
3645                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3646                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3647                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3648                         } else {
3649                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3650                                 amd64_div_reg (code, ins->sreg2, FALSE);
3651                         }
3652                         break;
3653                 case OP_IDIV:
3654                 case OP_IREM:
3655                         if (ins->sreg2 == AMD64_RDX) {
3656                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3657                                 amd64_cdq_size (code, 4);
3658                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3659                         } else {
3660                                 amd64_cdq_size (code, 4);
3661                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3662                         }
3663                         break;
3664                 case OP_IDIV_UN:
3665                 case OP_IREM_UN:
3666                         if (ins->sreg2 == AMD64_RDX) {
3667                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3668                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3669                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3670                         } else {
3671                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3672                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3673                         }
3674                         break;
3675                 case OP_IREM_IMM: {
3676                         int power = mono_is_power_of_two (ins->inst_imm);
3677
3678                         g_assert (ins->sreg1 == X86_EAX);
3679                         g_assert (ins->dreg == X86_EAX);
3680                         g_assert (power >= 0);
3681
3682                         if (power == 0) {
3683                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3684                                 break;
3685                         }
3686
3687                         /* Based on gcc code */
3688
3689                         /* Add compensation for negative dividents */
3690                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3691                         if (power > 1)
3692                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3693                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3694                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3695                         /* Compute remainder */
3696                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3697                         /* Remove compensation */
3698                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3699                         break;
3700                 }
3701                 case OP_LMUL_OVF:
3702                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3703                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3704                         break;
3705                 case OP_LOR:
3706                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3707                         break;
3708                 case OP_OR_IMM:
3709                 case OP_LOR_IMM:
3710                         g_assert (amd64_is_imm32 (ins->inst_imm));
3711                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3712                         break;
3713                 case OP_LXOR:
3714                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3715                         break;
3716                 case OP_XOR_IMM:
3717                 case OP_LXOR_IMM:
3718                         g_assert (amd64_is_imm32 (ins->inst_imm));
3719                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3720                         break;
3721                 case OP_LSHL:
3722                         g_assert (ins->sreg2 == AMD64_RCX);
3723                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3724                         break;
3725                 case OP_LSHR:
3726                         g_assert (ins->sreg2 == AMD64_RCX);
3727                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3728                         break;
3729                 case OP_SHR_IMM:
3730                         g_assert (amd64_is_imm32 (ins->inst_imm));
3731                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3732                         break;
3733                 case OP_LSHR_IMM:
3734                         g_assert (amd64_is_imm32 (ins->inst_imm));
3735                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3736                         break;
3737                 case OP_SHR_UN_IMM:
3738                         g_assert (amd64_is_imm32 (ins->inst_imm));
3739                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3740                         break;
3741                 case OP_LSHR_UN_IMM:
3742                         g_assert (amd64_is_imm32 (ins->inst_imm));
3743                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3744                         break;
3745                 case OP_LSHR_UN:
3746                         g_assert (ins->sreg2 == AMD64_RCX);
3747                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3748                         break;
3749                 case OP_SHL_IMM:
3750                         g_assert (amd64_is_imm32 (ins->inst_imm));
3751                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3752                         break;
3753                 case OP_LSHL_IMM:
3754                         g_assert (amd64_is_imm32 (ins->inst_imm));
3755                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3756                         break;
3757
3758                 case OP_IADDCC:
3759                 case OP_IADD:
3760                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3761                         break;
3762                 case OP_IADC:
3763                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3764                         break;
3765                 case OP_IADD_IMM:
3766                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3767                         break;
3768                 case OP_IADC_IMM:
3769                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3770                         break;
3771                 case OP_ISUBCC:
3772                 case OP_ISUB:
3773                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3774                         break;
3775                 case OP_ISBB:
3776                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3777                         break;
3778                 case OP_ISUB_IMM:
3779                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3780                         break;
3781                 case OP_ISBB_IMM:
3782                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3783                         break;
3784                 case OP_IAND:
3785                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3786                         break;
3787                 case OP_IAND_IMM:
3788                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3789                         break;
3790                 case OP_IOR:
3791                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3792                         break;
3793                 case OP_IOR_IMM:
3794                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3795                         break;
3796                 case OP_IXOR:
3797                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3798                         break;
3799                 case OP_IXOR_IMM:
3800                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3801                         break;
3802                 case OP_INEG:
3803                         amd64_neg_reg_size (code, ins->sreg1, 4);
3804                         break;
3805                 case OP_INOT:
3806                         amd64_not_reg_size (code, ins->sreg1, 4);
3807                         break;
3808                 case OP_ISHL:
3809                         g_assert (ins->sreg2 == AMD64_RCX);
3810                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3811                         break;
3812                 case OP_ISHR:
3813                         g_assert (ins->sreg2 == AMD64_RCX);
3814                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3815                         break;
3816                 case OP_ISHR_IMM:
3817                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3818                         break;
3819                 case OP_ISHR_UN_IMM:
3820                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3821                         break;
3822                 case OP_ISHR_UN:
3823                         g_assert (ins->sreg2 == AMD64_RCX);
3824                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3825                         break;
3826                 case OP_ISHL_IMM:
3827                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3828                         break;
3829                 case OP_IMUL:
3830                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3831                         break;
3832                 case OP_IMUL_OVF:
3833                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3834                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3835                         break;
3836                 case OP_IMUL_OVF_UN:
3837                 case OP_LMUL_OVF_UN: {
3838                         /* the mul operation and the exception check should most likely be split */
3839                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3840                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3841                         /*g_assert (ins->sreg2 == X86_EAX);
3842                         g_assert (ins->dreg == X86_EAX);*/
3843                         if (ins->sreg2 == X86_EAX) {
3844                                 non_eax_reg = ins->sreg1;
3845                         } else if (ins->sreg1 == X86_EAX) {
3846                                 non_eax_reg = ins->sreg2;
3847                         } else {
3848                                 /* no need to save since we're going to store to it anyway */
3849                                 if (ins->dreg != X86_EAX) {
3850                                         saved_eax = TRUE;
3851                                         amd64_push_reg (code, X86_EAX);
3852                                 }
3853                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3854                                 non_eax_reg = ins->sreg2;
3855                         }
3856                         if (ins->dreg == X86_EDX) {
3857                                 if (!saved_eax) {
3858                                         saved_eax = TRUE;
3859                                         amd64_push_reg (code, X86_EAX);
3860                                 }
3861                         } else {
3862                                 saved_edx = TRUE;
3863                                 amd64_push_reg (code, X86_EDX);
3864                         }
3865                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3866                         /* save before the check since pop and mov don't change the flags */
3867                         if (ins->dreg != X86_EAX)
3868                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3869                         if (saved_edx)
3870                                 amd64_pop_reg (code, X86_EDX);
3871                         if (saved_eax)
3872                                 amd64_pop_reg (code, X86_EAX);
3873                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3874                         break;
3875                 }
3876                 case OP_ICOMPARE:
3877                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3878                         break;
3879                 case OP_ICOMPARE_IMM:
3880                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3881                         break;
3882                 case OP_IBEQ:
3883                 case OP_IBLT:
3884                 case OP_IBGT:
3885                 case OP_IBGE:
3886                 case OP_IBLE:
3887                 case OP_LBEQ:
3888                 case OP_LBLT:
3889                 case OP_LBGT:
3890                 case OP_LBGE:
3891                 case OP_LBLE:
3892                 case OP_IBNE_UN:
3893                 case OP_IBLT_UN:
3894                 case OP_IBGT_UN:
3895                 case OP_IBGE_UN:
3896                 case OP_IBLE_UN:
3897                 case OP_LBNE_UN:
3898                 case OP_LBLT_UN:
3899                 case OP_LBGT_UN:
3900                 case OP_LBGE_UN:
3901                 case OP_LBLE_UN:
3902                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3903                         break;
3904
3905                 case OP_CMOV_IEQ:
3906                 case OP_CMOV_IGE:
3907                 case OP_CMOV_IGT:
3908                 case OP_CMOV_ILE:
3909                 case OP_CMOV_ILT:
3910                 case OP_CMOV_INE_UN:
3911                 case OP_CMOV_IGE_UN:
3912                 case OP_CMOV_IGT_UN:
3913                 case OP_CMOV_ILE_UN:
3914                 case OP_CMOV_ILT_UN:
3915                 case OP_CMOV_LEQ:
3916                 case OP_CMOV_LGE:
3917                 case OP_CMOV_LGT:
3918                 case OP_CMOV_LLE:
3919                 case OP_CMOV_LLT:
3920                 case OP_CMOV_LNE_UN:
3921                 case OP_CMOV_LGE_UN:
3922                 case OP_CMOV_LGT_UN:
3923                 case OP_CMOV_LLE_UN:
3924                 case OP_CMOV_LLT_UN:
3925                         g_assert (ins->dreg == ins->sreg1);
3926                         /* This needs to operate on 64 bit values */
3927                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3928                         break;
3929
3930                 case OP_LNOT:
3931                         amd64_not_reg (code, ins->sreg1);
3932                         break;
3933                 case OP_LNEG:
3934                         amd64_neg_reg (code, ins->sreg1);
3935                         break;
3936
3937                 case OP_ICONST:
3938                 case OP_I8CONST:
3939                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3940                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3941                         else
3942                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3943                         break;
3944                 case OP_AOTCONST:
3945                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3946                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3947                         break;
3948                 case OP_JUMP_TABLE:
3949                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3950                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3951                         break;
3952                 case OP_MOVE:
3953                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3954                         break;
3955                 case OP_AMD64_SET_XMMREG_R4: {
3956                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3957                         break;
3958                 }
3959                 case OP_AMD64_SET_XMMREG_R8: {
3960                         if (ins->dreg != ins->sreg1)
3961                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3962                         break;
3963                 }
3964                 case OP_TAILCALL: {
3965                         /*
3966                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3967                          * Keep in sync with the code in emit_epilog.
3968                          */
3969                         int pos = 0, i;
3970
3971                         /* FIXME: no tracing support... */
3972                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3973                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
3974
3975                         g_assert (!cfg->method->save_lmf);
3976
3977                         if (cfg->arch.omit_fp) {
3978                                 guint32 save_offset = 0;
3979                                 /* Pop callee-saved registers */
3980                                 for (i = 0; i < AMD64_NREG; ++i)
3981                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3982                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3983                                                 save_offset += 8;
3984                                         }
3985                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3986                         }
3987                         else {
3988                                 for (i = 0; i < AMD64_NREG; ++i)
3989                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3990                                                 pos -= sizeof (gpointer);
3991
3992                                 if (pos)
3993                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3994
3995                                 /* Pop registers in reverse order */
3996                                 for (i = AMD64_NREG - 1; i > 0; --i)
3997                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3998                                                 amd64_pop_reg (code, i);
3999                                         }
4000
4001                                 amd64_leave (code);
4002                         }
4003
4004                         offset = code - cfg->native_code;
4005                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4006                         if (cfg->compile_aot)
4007                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4008                         else
4009                                 amd64_set_reg_template (code, AMD64_R11);
4010                         amd64_jump_reg (code, AMD64_R11);
4011                         break;
4012                 }
4013                 case OP_CHECK_THIS:
4014                         /* ensure ins->sreg1 is not NULL */
4015                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4016                         break;
4017                 case OP_ARGLIST: {
4018                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4019                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4020                         break;
4021                 }
4022                 case OP_CALL:
4023                 case OP_FCALL:
4024                 case OP_LCALL:
4025                 case OP_VCALL:
4026                 case OP_VCALL2:
4027                 case OP_VOIDCALL:
4028                         call = (MonoCallInst*)ins;
4029                         /*
4030                          * The AMD64 ABI forces callers to know about varargs.
4031                          */
4032                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4033                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4034                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4035                                 /*
4036                                  * Since the unmanaged calling convention doesn't contain a
4037                                  * 'vararg' entry, we have to treat every pinvoke call as a
4038                                  * potential vararg call.
4039                                  */
4040                                 guint32 nregs, i;
4041                                 nregs = 0;
4042                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4043                                         if (call->used_fregs & (1 << i))
4044                                                 nregs ++;
4045                                 if (!nregs)
4046                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4047                                 else
4048                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4049                         }
4050
4051                         if (ins->flags & MONO_INST_HAS_METHOD)
4052                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4053                         else
4054                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4055                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4056                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4057                         code = emit_move_return_value (cfg, ins, code);
4058                         break;
4059                 case OP_FCALL_REG:
4060                 case OP_LCALL_REG:
4061                 case OP_VCALL_REG:
4062                 case OP_VCALL2_REG:
4063                 case OP_VOIDCALL_REG:
4064                 case OP_CALL_REG:
4065                         call = (MonoCallInst*)ins;
4066
4067                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4068                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4069                                 ins->sreg1 = AMD64_R11;
4070                         }
4071
4072                         /*
4073                          * The AMD64 ABI forces callers to know about varargs.
4074                          */
4075                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4076                                 if (ins->sreg1 == AMD64_RAX) {
4077                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4078                                         ins->sreg1 = AMD64_R11;
4079                                 }
4080                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4081                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4082                                 /*
4083                                  * Since the unmanaged calling convention doesn't contain a
4084                                  * 'vararg' entry, we have to treat every pinvoke call as a
4085                                  * potential vararg call.
4086                                  */
4087                                 guint32 nregs, i;
4088                                 nregs = 0;
4089                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4090                                         if (call->used_fregs & (1 << i))
4091                                                 nregs ++;
4092                                 if (ins->sreg1 == AMD64_RAX) {
4093                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4094                                         ins->sreg1 = AMD64_R11;
4095                                 }
4096                                 if (!nregs)
4097                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4098                                 else
4099                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4100                         }
4101
4102                         amd64_call_reg (code, ins->sreg1);
4103                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4104                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4105                         code = emit_move_return_value (cfg, ins, code);
4106                         break;
4107                 case OP_FCALL_MEMBASE:
4108                 case OP_LCALL_MEMBASE:
4109                 case OP_VCALL_MEMBASE:
4110                 case OP_VCALL2_MEMBASE:
4111                 case OP_VOIDCALL_MEMBASE:
4112                 case OP_CALL_MEMBASE:
4113                         call = (MonoCallInst*)ins;
4114
4115                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4116                                 /*
4117                                  * Can't use R11 because it is clobbered by the trampoline
4118                                  * code, and the reg value is needed by get_vcall_slot_addr.
4119                                  */
4120                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4121                                 ins->sreg1 = AMD64_RAX;
4122                         }
4123
4124                         /*
4125                          * Emit a few nops to simplify get_vcall_slot ().
4126                          */
4127                         amd64_nop (code);
4128                         amd64_nop (code);
4129                         amd64_nop (code);
4130
4131                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4132                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4133                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4134                         code = emit_move_return_value (cfg, ins, code);
4135                         break;
4136                 case OP_DYN_CALL: {
4137                         int i;
4138                         MonoInst *var = cfg->dyn_call_var;
4139
4140                         g_assert (var->opcode == OP_REGOFFSET);
4141
4142                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4143                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4144                         /* r10 = ftn */
4145                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4146
4147                         /* Save args buffer */
4148                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4149
4150                         /* Set argument registers */
4151                         for (i = 0; i < PARAM_REGS; ++i)
4152                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4153
4154                         /* Make the call */
4155                         amd64_call_reg (code, AMD64_R10);
4156
4157                         /* Save result */
4158                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4159                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4160                         break;
4161                 }
4162                 case OP_AMD64_SAVE_SP_TO_LMF:
4163                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4164                         break;
4165                 case OP_X86_PUSH:
4166                         g_assert (!cfg->arch.no_pushes);
4167                         amd64_push_reg (code, ins->sreg1);
4168                         break;
4169                 case OP_X86_PUSH_IMM:
4170                         g_assert (!cfg->arch.no_pushes);
4171                         g_assert (amd64_is_imm32 (ins->inst_imm));
4172                         amd64_push_imm (code, ins->inst_imm);
4173                         break;
4174                 case OP_X86_PUSH_MEMBASE:
4175                         g_assert (!cfg->arch.no_pushes);
4176                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4177                         break;
4178                 case OP_X86_PUSH_OBJ: {
4179                         int size = ALIGN_TO (ins->inst_imm, 8);
4180
4181                         g_assert (!cfg->arch.no_pushes);
4182
4183                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4184                         amd64_push_reg (code, AMD64_RDI);
4185                         amd64_push_reg (code, AMD64_RSI);
4186                         amd64_push_reg (code, AMD64_RCX);
4187                         if (ins->inst_offset)
4188                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4189                         else
4190                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4191                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4192                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4193                         amd64_cld (code);
4194                         amd64_prefix (code, X86_REP_PREFIX);
4195                         amd64_movsd (code);
4196                         amd64_pop_reg (code, AMD64_RCX);
4197                         amd64_pop_reg (code, AMD64_RSI);
4198                         amd64_pop_reg (code, AMD64_RDI);
4199                         break;
4200                 }
4201                 case OP_X86_LEA:
4202                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4203                         break;
4204                 case OP_X86_LEA_MEMBASE:
4205                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4206                         break;
4207                 case OP_X86_XCHG:
4208                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4209                         break;
4210                 case OP_LOCALLOC:
4211                         /* keep alignment */
4212                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4213                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4214                         code = mono_emit_stack_alloc (cfg, code, ins);
4215                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4216                         if (cfg->param_area && cfg->arch.no_pushes)
4217                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4218                         break;
4219                 case OP_LOCALLOC_IMM: {
4220                         guint32 size = ins->inst_imm;
4221                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4222
4223                         if (ins->flags & MONO_INST_INIT) {
4224                                 if (size < 64) {
4225                                         int i;
4226
4227                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4228                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4229
4230                                         for (i = 0; i < size; i += 8)
4231                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4232                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4233                                 } else {
4234                                         amd64_mov_reg_imm (code, ins->dreg, size);
4235                                         ins->sreg1 = ins->dreg;
4236
4237                                         code = mono_emit_stack_alloc (cfg, code, ins);
4238                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4239                                 }
4240                         } else {
4241                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4242                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4243                         }
4244                         if (cfg->param_area && cfg->arch.no_pushes)
4245                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4246                         break;
4247                 }
4248                 case OP_THROW: {
4249                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4250                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4251                                              (gpointer)"mono_arch_throw_exception", FALSE);
4252                         break;
4253                 }
4254                 case OP_RETHROW: {
4255                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4256                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4257                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4258                         break;
4259                 }
4260                 case OP_CALL_HANDLER:
4261                         /* Align stack */
4262                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4263                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4264                         amd64_call_imm (code, 0);
4265                         /* Restore stack alignment */
4266                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4267                         break;
4268                 case OP_START_HANDLER: {
4269                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4270                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4271
4272                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4273                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4274                                 cfg->param_area && cfg->arch.no_pushes) {
4275                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4276                         }
4277                         break;
4278                 }
4279                 case OP_ENDFINALLY: {
4280                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4281                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4282                         amd64_ret (code);
4283                         break;
4284                 }
4285                 case OP_ENDFILTER: {
4286                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4287                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4288                         /* The local allocator will put the result into RAX */
4289                         amd64_ret (code);
4290                         break;
4291                 }
4292
4293                 case OP_LABEL:
4294                         ins->inst_c0 = code - cfg->native_code;
4295                         break;
4296                 case OP_BR:
4297                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4298                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4299                         //break;
4300                                 if (ins->inst_target_bb->native_offset) {
4301                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4302                                 } else {
4303                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4304                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4305                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4306                                                 x86_jump8 (code, 0);
4307                                         else
4308                                                 x86_jump32 (code, 0);
4309                         }
4310                         break;
4311                 case OP_BR_REG:
4312                         amd64_jump_reg (code, ins->sreg1);
4313                         break;
4314                 case OP_CEQ:
4315                 case OP_LCEQ:
4316                 case OP_ICEQ:
4317                 case OP_CLT:
4318                 case OP_LCLT:
4319                 case OP_ICLT:
4320                 case OP_CGT:
4321                 case OP_ICGT:
4322                 case OP_LCGT:
4323                 case OP_CLT_UN:
4324                 case OP_LCLT_UN:
4325                 case OP_ICLT_UN:
4326                 case OP_CGT_UN:
4327                 case OP_LCGT_UN:
4328                 case OP_ICGT_UN:
4329                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4330                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4331                         break;
4332                 case OP_COND_EXC_EQ:
4333                 case OP_COND_EXC_NE_UN:
4334                 case OP_COND_EXC_LT:
4335                 case OP_COND_EXC_LT_UN:
4336                 case OP_COND_EXC_GT:
4337                 case OP_COND_EXC_GT_UN:
4338                 case OP_COND_EXC_GE:
4339                 case OP_COND_EXC_GE_UN:
4340                 case OP_COND_EXC_LE:
4341                 case OP_COND_EXC_LE_UN:
4342                 case OP_COND_EXC_IEQ:
4343                 case OP_COND_EXC_INE_UN:
4344                 case OP_COND_EXC_ILT:
4345                 case OP_COND_EXC_ILT_UN:
4346                 case OP_COND_EXC_IGT:
4347                 case OP_COND_EXC_IGT_UN:
4348                 case OP_COND_EXC_IGE:
4349                 case OP_COND_EXC_IGE_UN:
4350                 case OP_COND_EXC_ILE:
4351                 case OP_COND_EXC_ILE_UN:
4352                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4353                         break;
4354                 case OP_COND_EXC_OV:
4355                 case OP_COND_EXC_NO:
4356                 case OP_COND_EXC_C:
4357                 case OP_COND_EXC_NC:
4358                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4359                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4360                         break;
4361                 case OP_COND_EXC_IOV:
4362                 case OP_COND_EXC_INO:
4363                 case OP_COND_EXC_IC:
4364                 case OP_COND_EXC_INC:
4365                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4366                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4367                         break;
4368
4369                 /* floating point opcodes */
4370                 case OP_R8CONST: {
4371                         double d = *(double *)ins->inst_p0;
4372
4373                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4374                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4375                         }
4376                         else {
4377                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4378                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4379                         }
4380                         break;
4381                 }
4382                 case OP_R4CONST: {
4383                         float f = *(float *)ins->inst_p0;
4384
4385                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4386                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4387                         }
4388                         else {
4389                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4390                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4391                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4392                         }
4393                         break;
4394                 }
4395                 case OP_STORER8_MEMBASE_REG:
4396                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4397                         break;
4398                 case OP_LOADR8_MEMBASE:
4399                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4400                         break;
4401                 case OP_STORER4_MEMBASE_REG:
4402                         /* This requires a double->single conversion */
4403                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4404                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4405                         break;
4406                 case OP_LOADR4_MEMBASE:
4407                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4408                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4409                         break;
4410                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4411                 case OP_ICONV_TO_R8:
4412                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4413                         break;
4414                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4415                 case OP_LCONV_TO_R8:
4416                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4417                         break;
4418                 case OP_FCONV_TO_R4:
4419                         /* FIXME: nothing to do ?? */
4420                         break;
4421                 case OP_FCONV_TO_I1:
4422                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4423                         break;
4424                 case OP_FCONV_TO_U1:
4425                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4426                         break;
4427                 case OP_FCONV_TO_I2:
4428                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4429                         break;
4430                 case OP_FCONV_TO_U2:
4431                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4432                         break;
4433                 case OP_FCONV_TO_U4:
4434                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4435                         break;
4436                 case OP_FCONV_TO_I4:
4437                 case OP_FCONV_TO_I:
4438                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4439                         break;
4440                 case OP_FCONV_TO_I8:
4441                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4442                         break;
4443                 case OP_LCONV_TO_R_UN: {
4444                         guint8 *br [2];
4445
4446                         /* Based on gcc code */
4447                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4448                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4449
4450                         /* Positive case */
4451                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4452                         br [1] = code; x86_jump8 (code, 0);
4453                         amd64_patch (br [0], code);
4454
4455                         /* Negative case */
4456                         /* Save to the red zone */
4457                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4458                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4459                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4460                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4461                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4462                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4463                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4464                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4465                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4466                         /* Restore */
4467                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4468                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4469                         amd64_patch (br [1], code);
4470                         break;
4471                 }
4472                 case OP_LCONV_TO_OVF_U4:
4473                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4474                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4475                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4476                         break;
4477                 case OP_LCONV_TO_OVF_I4_UN:
4478                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4479                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4480                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4481                         break;
4482                 case OP_FMOVE:
4483                         if (ins->dreg != ins->sreg1)
4484                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4485                         break;
4486                 case OP_FADD:
4487                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4488                         break;
4489                 case OP_FSUB:
4490                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4491                         break;
4492                 case OP_FMUL:
4493                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4494                         break;
4495                 case OP_FDIV:
4496                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4497                         break;
4498                 case OP_FNEG: {
4499                         static double r8_0 = -0.0;
4500
4501                         g_assert (ins->sreg1 == ins->dreg);
4502
4503                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4504                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4505                         break;
4506                 }
4507                 case OP_SIN:
4508                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4509                         break;
4510                 case OP_COS:
4511                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4512                         break;
4513                 case OP_ABS: {
4514                         static guint64 d = 0x7fffffffffffffffUL;
4515
4516                         g_assert (ins->sreg1 == ins->dreg);
4517
4518                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4519                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4520                         break;
4521                 }
4522                 case OP_SQRT:
4523                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4524                         break;
4525                 case OP_IMIN:
4526                         g_assert (cfg->opt & MONO_OPT_CMOV);
4527                         g_assert (ins->dreg == ins->sreg1);
4528                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4529                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4530                         break;
4531                 case OP_IMIN_UN:
4532                         g_assert (cfg->opt & MONO_OPT_CMOV);
4533                         g_assert (ins->dreg == ins->sreg1);
4534                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4535                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4536                         break;
4537                 case OP_IMAX:
4538                         g_assert (cfg->opt & MONO_OPT_CMOV);
4539                         g_assert (ins->dreg == ins->sreg1);
4540                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4541                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4542                         break;
4543                 case OP_IMAX_UN:
4544                         g_assert (cfg->opt & MONO_OPT_CMOV);
4545                         g_assert (ins->dreg == ins->sreg1);
4546                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4547                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4548                         break;
4549                 case OP_LMIN:
4550                         g_assert (cfg->opt & MONO_OPT_CMOV);
4551                         g_assert (ins->dreg == ins->sreg1);
4552                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4553                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4554                         break;
4555                 case OP_LMIN_UN:
4556                         g_assert (cfg->opt & MONO_OPT_CMOV);
4557                         g_assert (ins->dreg == ins->sreg1);
4558                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4559                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4560                         break;
4561                 case OP_LMAX:
4562                         g_assert (cfg->opt & MONO_OPT_CMOV);
4563                         g_assert (ins->dreg == ins->sreg1);
4564                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4565                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4566                         break;
4567                 case OP_LMAX_UN:
4568                         g_assert (cfg->opt & MONO_OPT_CMOV);
4569                         g_assert (ins->dreg == ins->sreg1);
4570                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4571                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4572                         break;
4573                 case OP_X86_FPOP:
4574                         break;
4575                 case OP_FCOMPARE:
4576                         /*
4577                          * The two arguments are swapped because the fbranch instructions
4578                          * depend on this for the non-sse case to work.
4579                          */
4580                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4581                         break;
4582                 case OP_FCEQ: {
4583                         /* zeroing the register at the start results in
4584                          * shorter and faster code (we can also remove the widening op)
4585                          */
4586                         guchar *unordered_check;
4587                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4588                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4589                         unordered_check = code;
4590                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4591                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4592                         amd64_patch (unordered_check, code);
4593                         break;
4594                 }
4595                 case OP_FCLT:
4596                 case OP_FCLT_UN:
4597                         /* zeroing the register at the start results in
4598                          * shorter and faster code (we can also remove the widening op)
4599                          */
4600                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4601                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4602                         if (ins->opcode == OP_FCLT_UN) {
4603                                 guchar *unordered_check = code;
4604                                 guchar *jump_to_end;
4605                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4606                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4607                                 jump_to_end = code;
4608                                 x86_jump8 (code, 0);
4609                                 amd64_patch (unordered_check, code);
4610                                 amd64_inc_reg (code, ins->dreg);
4611                                 amd64_patch (jump_to_end, code);
4612                         } else {
4613                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4614                         }
4615                         break;
4616                 case OP_FCGT:
4617                 case OP_FCGT_UN: {
4618                         /* zeroing the register at the start results in
4619                          * shorter and faster code (we can also remove the widening op)
4620                          */
4621                         guchar *unordered_check;
4622                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4623                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4624                         if (ins->opcode == OP_FCGT) {
4625                                 unordered_check = code;
4626                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4627                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4628                                 amd64_patch (unordered_check, code);
4629                         } else {
4630                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4631                         }
4632                         break;
4633                 }
4634                 case OP_FCLT_MEMBASE:
4635                 case OP_FCGT_MEMBASE:
4636                 case OP_FCLT_UN_MEMBASE:
4637                 case OP_FCGT_UN_MEMBASE:
4638                 case OP_FCEQ_MEMBASE: {
4639                         guchar *unordered_check, *jump_to_end;
4640                         int x86_cond;
4641
4642                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4643                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4644
4645                         switch (ins->opcode) {
4646                         case OP_FCEQ_MEMBASE:
4647                                 x86_cond = X86_CC_EQ;
4648                                 break;
4649                         case OP_FCLT_MEMBASE:
4650                         case OP_FCLT_UN_MEMBASE:
4651                                 x86_cond = X86_CC_LT;
4652                                 break;
4653                         case OP_FCGT_MEMBASE:
4654                         case OP_FCGT_UN_MEMBASE:
4655                                 x86_cond = X86_CC_GT;
4656                                 break;
4657                         default:
4658                                 g_assert_not_reached ();
4659                         }
4660
4661                         unordered_check = code;
4662                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4663                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4664
4665                         switch (ins->opcode) {
4666                         case OP_FCEQ_MEMBASE:
4667                         case OP_FCLT_MEMBASE:
4668                         case OP_FCGT_MEMBASE:
4669                                 amd64_patch (unordered_check, code);
4670                                 break;
4671                         case OP_FCLT_UN_MEMBASE:
4672                         case OP_FCGT_UN_MEMBASE:
4673                                 jump_to_end = code;
4674                                 x86_jump8 (code, 0);
4675                                 amd64_patch (unordered_check, code);
4676                                 amd64_inc_reg (code, ins->dreg);
4677                                 amd64_patch (jump_to_end, code);
4678                                 break;
4679                         default:
4680                                 break;
4681                         }
4682                         break;
4683                 }
4684                 case OP_FBEQ: {
4685                         guchar *jump = code;
4686                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4687                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4688                         amd64_patch (jump, code);
4689                         break;
4690                 }
4691                 case OP_FBNE_UN:
4692                         /* Branch if C013 != 100 */
4693                         /* branch if !ZF or (PF|CF) */
4694                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4695                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4696                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4697                         break;
4698                 case OP_FBLT:
4699                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4700                         break;
4701                 case OP_FBLT_UN:
4702                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4703                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4704                         break;
4705                 case OP_FBGT:
4706                 case OP_FBGT_UN:
4707                         if (ins->opcode == OP_FBGT) {
4708                                 guchar *br1;
4709
4710                                 /* skip branch if C1=1 */
4711                                 br1 = code;
4712                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4713                                 /* branch if (C0 | C3) = 1 */
4714                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4715                                 amd64_patch (br1, code);
4716                                 break;
4717                         } else {
4718                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4719                         }
4720                         break;
4721                 case OP_FBGE: {
4722                         /* Branch if C013 == 100 or 001 */
4723                         guchar *br1;
4724
4725                         /* skip branch if C1=1 */
4726                         br1 = code;
4727                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4728                         /* branch if (C0 | C3) = 1 */
4729                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4730                         amd64_patch (br1, code);
4731                         break;
4732                 }
4733                 case OP_FBGE_UN:
4734                         /* Branch if C013 == 000 */
4735                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4736                         break;
4737                 case OP_FBLE: {
4738                         /* Branch if C013=000 or 100 */
4739                         guchar *br1;
4740
4741                         /* skip branch if C1=1 */
4742                         br1 = code;
4743                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4744                         /* branch if C0=0 */
4745                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4746                         amd64_patch (br1, code);
4747                         break;
4748                 }
4749                 case OP_FBLE_UN:
4750                         /* Branch if C013 != 001 */
4751                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4752                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4753                         break;
4754                 case OP_CKFINITE:
4755                         /* Transfer value to the fp stack */
4756                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4757                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4758                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4759
4760                         amd64_push_reg (code, AMD64_RAX);
4761                         amd64_fxam (code);
4762                         amd64_fnstsw (code);
4763                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4764                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4765                         amd64_pop_reg (code, AMD64_RAX);
4766                         amd64_fstp (code, 0);
4767                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4768                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4769                         break;
4770                 case OP_TLS_GET: {
4771                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4772                         break;
4773                 }
4774                 case OP_MEMORY_BARRIER: {
4775                         /* Not needed on amd64 */
4776                         break;
4777                 }
4778                 case OP_ATOMIC_ADD_I4:
4779                 case OP_ATOMIC_ADD_I8: {
4780                         int dreg = ins->dreg;
4781                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4782
4783                         if (dreg == ins->inst_basereg)
4784                                 dreg = AMD64_R11;
4785
4786                         if (dreg != ins->sreg2)
4787                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4788
4789                         x86_prefix (code, X86_LOCK_PREFIX);
4790                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4791
4792                         if (dreg != ins->dreg)
4793                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4794
4795                         break;
4796                 }
4797                 case OP_ATOMIC_ADD_NEW_I4:
4798                 case OP_ATOMIC_ADD_NEW_I8: {
4799                         int dreg = ins->dreg;
4800                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4801
4802                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4803                                 dreg = AMD64_R11;
4804
4805                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4806                         amd64_prefix (code, X86_LOCK_PREFIX);
4807                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4808                         /* dreg contains the old value, add with sreg2 value */
4809                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4810
4811                         if (ins->dreg != dreg)
4812                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4813
4814                         break;
4815                 }
4816                 case OP_ATOMIC_EXCHANGE_I4:
4817                 case OP_ATOMIC_EXCHANGE_I8: {
4818                         guchar *br[2];
4819                         int sreg2 = ins->sreg2;
4820                         int breg = ins->inst_basereg;
4821                         guint32 size;
4822                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4823
4824                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4825                                 size = 8;
4826                         else
4827                                 size = 4;
4828
4829                         /*
4830                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4831                          * an explanation of how this works.
4832                          */
4833
4834                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4835                          * hack to overcome limits in x86 reg allocator
4836                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4837                          */
4838                         g_assert (ins->dreg == AMD64_RAX);
4839
4840                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4841                                 /* Highly unlikely, but possible */
4842                                 need_push = TRUE;
4843
4844                         /* The pushes invalidate rsp */
4845                         if ((breg == AMD64_RAX) || need_push) {
4846                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4847                                 breg = AMD64_R11;
4848                         }
4849
4850                         /* We need the EAX reg for the comparand */
4851                         if (ins->sreg2 == AMD64_RAX) {
4852                                 if (breg != AMD64_R11) {
4853                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4854                                         sreg2 = AMD64_R11;
4855                                 } else {
4856                                         g_assert (need_push);
4857                                         amd64_push_reg (code, AMD64_RDX);
4858                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4859                                         sreg2 = AMD64_RDX;
4860                                         rdx_pushed = TRUE;
4861                                 }
4862                         }
4863
4864                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4865
4866                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4867                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4868                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4869                         amd64_patch (br [1], br [0]);
4870
4871                         if (rdx_pushed)
4872                                 amd64_pop_reg (code, AMD64_RDX);
4873
4874                         break;
4875                 }
4876                 case OP_ATOMIC_CAS_I4:
4877                 case OP_ATOMIC_CAS_I8: {
4878                         guint32 size;
4879
4880                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4881                                 size = 8;
4882                         else
4883                                 size = 4;
4884
4885                         /*
4886                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4887                          * an explanation of how this works.
4888                          */
4889                         g_assert (ins->sreg3 == AMD64_RAX);
4890                         g_assert (ins->sreg1 != AMD64_RAX);
4891                         g_assert (ins->sreg1 != ins->sreg2);
4892
4893                         amd64_prefix (code, X86_LOCK_PREFIX);
4894                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4895
4896                         if (ins->dreg != AMD64_RAX)
4897                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4898                         break;
4899                 }
4900 #ifdef MONO_ARCH_SIMD_INTRINSICS
4901                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4902                 case OP_ADDPS:
4903                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4904                         break;
4905                 case OP_DIVPS:
4906                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4907                         break;
4908                 case OP_MULPS:
4909                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4910                         break;
4911                 case OP_SUBPS:
4912                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4913                         break;
4914                 case OP_MAXPS:
4915                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4916                         break;
4917                 case OP_MINPS:
4918                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4919                         break;
4920                 case OP_COMPPS:
4921                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4922                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4923                         break;
4924                 case OP_ANDPS:
4925                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4926                         break;
4927                 case OP_ANDNPS:
4928                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4929                         break;
4930                 case OP_ORPS:
4931                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4932                         break;
4933                 case OP_XORPS:
4934                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
4935                         break;
4936                 case OP_SQRTPS:
4937                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4938                         break;
4939                 case OP_RSQRTPS:
4940                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4941                         break;
4942                 case OP_RCPPS:
4943                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
4944                         break;
4945                 case OP_ADDSUBPS:
4946                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4947                         break;
4948                 case OP_HADDPS:
4949                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
4950                         break;
4951                 case OP_HSUBPS:
4952                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4953                         break;
4954                 case OP_DUPPS_HIGH:
4955                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
4956                         break;
4957                 case OP_DUPPS_LOW:
4958                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
4959                         break;
4960
4961                 case OP_PSHUFLEW_HIGH:
4962                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4963                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4964                         break;
4965                 case OP_PSHUFLEW_LOW:
4966                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4967                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4968                         break;
4969                 case OP_PSHUFLED:
4970                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4971                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4972                         break;
4973
4974                 case OP_ADDPD:
4975                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
4976                         break;
4977                 case OP_DIVPD:
4978                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
4979                         break;
4980                 case OP_MULPD:
4981                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
4982                         break;
4983                 case OP_SUBPD:
4984                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
4985                         break;
4986                 case OP_MAXPD:
4987                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
4988                         break;
4989                 case OP_MINPD:
4990                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
4991                         break;
4992                 case OP_COMPPD:
4993                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4994                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4995                         break;
4996                 case OP_ANDPD:
4997                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
4998                         break;
4999                 case OP_ANDNPD:
5000                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5001                         break;
5002                 case OP_ORPD:
5003                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5004                         break;
5005                 case OP_XORPD:
5006                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5007                         break;
5008                 case OP_SQRTPD:
5009                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5010                         break;
5011                 case OP_ADDSUBPD:
5012                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5013                         break;
5014                 case OP_HADDPD:
5015                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5016                         break;
5017                 case OP_HSUBPD:
5018                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5019                         break;
5020                 case OP_DUPPD:
5021                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5022                         break;
5023
5024                 case OP_EXTRACT_MASK:
5025                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5026                         break;
5027
5028                 case OP_PAND:
5029                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5030                         break;
5031                 case OP_POR:
5032                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5033                         break;
5034                 case OP_PXOR:
5035                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5036                         break;
5037
5038                 case OP_PADDB:
5039                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5040                         break;
5041                 case OP_PADDW:
5042                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5043                         break;
5044                 case OP_PADDD:
5045                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5046                         break;
5047                 case OP_PADDQ:
5048                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5049                         break;
5050
5051                 case OP_PSUBB:
5052                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5053                         break;
5054                 case OP_PSUBW:
5055                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5056                         break;
5057                 case OP_PSUBD:
5058                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5059                         break;
5060                 case OP_PSUBQ:
5061                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5062                         break;
5063
5064                 case OP_PMAXB_UN:
5065                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5066                         break;
5067                 case OP_PMAXW_UN:
5068                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5069                         break;
5070                 case OP_PMAXD_UN:
5071                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5072                         break;
5073
5074                 case OP_PMAXB:
5075                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5076                         break;
5077                 case OP_PMAXW:
5078                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5079                         break;
5080                 case OP_PMAXD:
5081                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5082                         break;
5083
5084                 case OP_PAVGB_UN:
5085                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5086                         break;
5087                 case OP_PAVGW_UN:
5088                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5089                         break;
5090
5091                 case OP_PMINB_UN:
5092                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5093                         break;
5094                 case OP_PMINW_UN:
5095                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5096                         break;
5097                 case OP_PMIND_UN:
5098                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5099                         break;
5100
5101                 case OP_PMINB:
5102                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5103                         break;
5104                 case OP_PMINW:
5105                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5106                         break;
5107                 case OP_PMIND:
5108                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5109                         break;
5110
5111                 case OP_PCMPEQB:
5112                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5113                         break;
5114                 case OP_PCMPEQW:
5115                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5116                         break;
5117                 case OP_PCMPEQD:
5118                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5119                         break;
5120                 case OP_PCMPEQQ:
5121                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5122                         break;
5123
5124                 case OP_PCMPGTB:
5125                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5126                         break;
5127                 case OP_PCMPGTW:
5128                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5129                         break;
5130                 case OP_PCMPGTD:
5131                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5132                         break;
5133                 case OP_PCMPGTQ:
5134                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5135                         break;
5136
5137                 case OP_PSUM_ABS_DIFF:
5138                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5139                         break;
5140
5141                 case OP_UNPACK_LOWB:
5142                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5143                         break;
5144                 case OP_UNPACK_LOWW:
5145                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5146                         break;
5147                 case OP_UNPACK_LOWD:
5148                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5149                         break;
5150                 case OP_UNPACK_LOWQ:
5151                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5152                         break;
5153                 case OP_UNPACK_LOWPS:
5154                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5155                         break;
5156                 case OP_UNPACK_LOWPD:
5157                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5158                         break;
5159
5160                 case OP_UNPACK_HIGHB:
5161                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5162                         break;
5163                 case OP_UNPACK_HIGHW:
5164                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5165                         break;
5166                 case OP_UNPACK_HIGHD:
5167                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5168                         break;
5169                 case OP_UNPACK_HIGHQ:
5170                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5171                         break;
5172                 case OP_UNPACK_HIGHPS:
5173                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5174                         break;
5175                 case OP_UNPACK_HIGHPD:
5176                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5177                         break;
5178
5179                 case OP_PACKW:
5180                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5181                         break;
5182                 case OP_PACKD:
5183                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5184                         break;
5185                 case OP_PACKW_UN:
5186                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5187                         break;
5188                 case OP_PACKD_UN:
5189                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5190                         break;
5191
5192                 case OP_PADDB_SAT_UN:
5193                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5194                         break;
5195                 case OP_PSUBB_SAT_UN:
5196                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5197                         break;
5198                 case OP_PADDW_SAT_UN:
5199                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5200                         break;
5201                 case OP_PSUBW_SAT_UN:
5202                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5203                         break;
5204
5205                 case OP_PADDB_SAT:
5206                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5207                         break;
5208                 case OP_PSUBB_SAT:
5209                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5210                         break;
5211                 case OP_PADDW_SAT:
5212                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5213                         break;
5214                 case OP_PSUBW_SAT:
5215                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5216                         break;
5217
5218                 case OP_PMULW:
5219                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5220                         break;
5221                 case OP_PMULD:
5222                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5223                         break;
5224                 case OP_PMULQ:
5225                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5226                         break;
5227                 case OP_PMULW_HIGH_UN:
5228                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5229                         break;
5230                 case OP_PMULW_HIGH:
5231                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5232                         break;
5233
5234                 case OP_PSHRW:
5235                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5236                         break;
5237                 case OP_PSHRW_REG:
5238                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5239                         break;
5240
5241                 case OP_PSARW:
5242                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5243                         break;
5244                 case OP_PSARW_REG:
5245                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5246                         break;
5247
5248                 case OP_PSHLW:
5249                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5250                         break;
5251                 case OP_PSHLW_REG:
5252                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5253                         break;
5254
5255                 case OP_PSHRD:
5256                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5257                         break;
5258                 case OP_PSHRD_REG:
5259                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5260                         break;
5261
5262                 case OP_PSARD:
5263                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5264                         break;
5265                 case OP_PSARD_REG:
5266                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5267                         break;
5268
5269                 case OP_PSHLD:
5270                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5271                         break;
5272                 case OP_PSHLD_REG:
5273                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5274                         break;
5275
5276                 case OP_PSHRQ:
5277                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5278                         break;
5279                 case OP_PSHRQ_REG:
5280                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5281                         break;
5282
5283                 /*TODO: This is appart of the sse spec but not added
5284                 case OP_PSARQ:
5285                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5286                         break;
5287                 case OP_PSARQ_REG:
5288                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5289                         break;
5290                 */
5291
5292                 case OP_PSHLQ:
5293                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5294                         break;
5295                 case OP_PSHLQ_REG:
5296                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5297                         break;
5298
5299                 case OP_ICONV_TO_X:
5300                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5301                         break;
5302                 case OP_EXTRACT_I4:
5303                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5304                         break;
5305                 case OP_EXTRACT_I8:
5306                         if (ins->inst_c0) {
5307                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5308                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5309                         } else {
5310                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5311                         }
5312                         break;
5313                 case OP_EXTRACT_I1:
5314                 case OP_EXTRACT_U1:
5315                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5316                         if (ins->inst_c0)
5317                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5318                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5319                         break;
5320                 case OP_EXTRACT_I2:
5321                 case OP_EXTRACT_U2:
5322                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5323                         if (ins->inst_c0)
5324                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5325                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5326                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5327                         break;
5328                 case OP_EXTRACT_R8:
5329                         if (ins->inst_c0)
5330                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5331                         else
5332                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5333                         break;
5334                 case OP_INSERT_I2:
5335                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5336                         break;
5337                 case OP_EXTRACTX_U2:
5338                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5339                         break;
5340                 case OP_INSERTX_U1_SLOW:
5341                         /*sreg1 is the extracted ireg (scratch)
5342                         /sreg2 is the to be inserted ireg (scratch)
5343                         /dreg is the xreg to receive the value*/
5344
5345                         /*clear the bits from the extracted word*/
5346                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5347                         /*shift the value to insert if needed*/
5348                         if (ins->inst_c0 & 1)
5349                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5350                         /*join them together*/
5351                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5352                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5353                         break;
5354                 case OP_INSERTX_I4_SLOW:
5355                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5356                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5357                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5358                         break;
5359                 case OP_INSERTX_I8_SLOW:
5360                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5361                         if (ins->inst_c0)
5362                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5363                         else
5364                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5365                         break;
5366
5367                 case OP_INSERTX_R4_SLOW:
5368                         switch (ins->inst_c0) {
5369                         case 0:
5370                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5371                                 break;
5372                         case 1:
5373                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5374                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5375                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5376                                 break;
5377                         case 2:
5378                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5379                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5380                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5381                                 break;
5382                         case 3:
5383                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5384                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5385                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5386                                 break;
5387                         }
5388                         break;
5389                 case OP_INSERTX_R8_SLOW:
5390                         if (ins->inst_c0)
5391                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5392                         else
5393                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5394                         break;
5395                 case OP_STOREX_MEMBASE_REG:
5396                 case OP_STOREX_MEMBASE:
5397                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5398                         break;
5399                 case OP_LOADX_MEMBASE:
5400                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5401                         break;
5402                 case OP_LOADX_ALIGNED_MEMBASE:
5403                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5404                         break;
5405                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5406                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5407                         break;
5408                 case OP_STOREX_NTA_MEMBASE_REG:
5409                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5410                         break;
5411                 case OP_PREFETCH_MEMBASE:
5412                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5413                         break;
5414
5415                 case OP_XMOVE:
5416                         /*FIXME the peephole pass should have killed this*/
5417                         if (ins->dreg != ins->sreg1)
5418                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5419                         break;
5420                 case OP_XZERO:
5421                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5422                         break;
5423                 case OP_ICONV_TO_R8_RAW:
5424                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5425                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5426                         break;
5427
5428                 case OP_FCONV_TO_R8_X:
5429                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5430                         break;
5431
5432                 case OP_XCONV_R8_TO_I4:
5433                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5434                         switch (ins->backend.source_opcode) {
5435                         case OP_FCONV_TO_I1:
5436                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5437                                 break;
5438                         case OP_FCONV_TO_U1:
5439                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5440                                 break;
5441                         case OP_FCONV_TO_I2:
5442                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5443                                 break;
5444                         case OP_FCONV_TO_U2:
5445                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5446                                 break;
5447                         }
5448                         break;
5449
5450                 case OP_EXPAND_I2:
5451                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5452                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5453                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5454                         break;
5455                 case OP_EXPAND_I4:
5456                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5457                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5458                         break;
5459                 case OP_EXPAND_I8:
5460                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5461                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5462                         break;
5463                 case OP_EXPAND_R4:
5464                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5465                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5466                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5467                         break;
5468                 case OP_EXPAND_R8:
5469                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5470                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5471                         break;
5472 #endif
5473                 case OP_LIVERANGE_START: {
5474                         if (cfg->verbose_level > 1)
5475                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5476                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5477                         break;
5478                 }
5479                 case OP_LIVERANGE_END: {
5480                         if (cfg->verbose_level > 1)
5481                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5482                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5483                         break;
5484                 }
5485                 default:
5486                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5487                         g_assert_not_reached ();
5488                 }
5489
5490                 if ((code - cfg->native_code - offset) > max_len) {
5491                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5492                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5493                         g_assert_not_reached ();
5494                 }
5495
5496                 last_ins = ins;
5497                 last_offset = offset;
5498         }
5499
5500         cfg->code_len = code - cfg->native_code;
5501 }
5502
5503 #endif /* DISABLE_JIT */
5504
5505 void
5506 mono_arch_register_lowlevel_calls (void)
5507 {
5508         /* The signature doesn't matter */
5509         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5510 }
5511
5512 void
5513 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5514 {
5515         MonoJumpInfo *patch_info;
5516         gboolean compile_aot = !run_cctors;
5517
5518         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5519                 unsigned char *ip = patch_info->ip.i + code;
5520                 unsigned char *target;
5521
5522                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5523
5524                 if (compile_aot) {
5525                         switch (patch_info->type) {
5526                         case MONO_PATCH_INFO_BB:
5527                         case MONO_PATCH_INFO_LABEL:
5528                                 break;
5529                         default:
5530                                 /* No need to patch these */
5531                                 continue;
5532                         }
5533                 }
5534
5535                 switch (patch_info->type) {
5536                 case MONO_PATCH_INFO_NONE:
5537                         continue;
5538                 case MONO_PATCH_INFO_METHOD_REL:
5539                 case MONO_PATCH_INFO_R8:
5540                 case MONO_PATCH_INFO_R4:
5541                         g_assert_not_reached ();
5542                         continue;
5543                 case MONO_PATCH_INFO_BB:
5544                         break;
5545                 default:
5546                         break;
5547                 }
5548
5549                 /*
5550                  * Debug code to help track down problems where the target of a near call is
5551                  * is not valid.
5552                  */
5553                 if (amd64_is_near_call (ip)) {
5554                         gint64 disp = (guint8*)target - (guint8*)ip;
5555
5556                         if (!amd64_is_imm32 (disp)) {
5557                                 printf ("TYPE: %d\n", patch_info->type);
5558                                 switch (patch_info->type) {
5559                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5560                                         printf ("V: %s\n", patch_info->data.name);
5561                                         break;
5562                                 case MONO_PATCH_INFO_METHOD_JUMP:
5563                                 case MONO_PATCH_INFO_METHOD:
5564                                         printf ("V: %s\n", patch_info->data.method->name);
5565                                         break;
5566                                 default:
5567                                         break;
5568                                 }
5569                         }
5570                 }
5571
5572                 amd64_patch (ip, (gpointer)target);
5573         }
5574 }
5575
5576 static int
5577 get_max_epilog_size (MonoCompile *cfg)
5578 {
5579         int max_epilog_size = 16;
5580
5581         if (cfg->method->save_lmf)
5582                 max_epilog_size += 256;
5583
5584         if (mono_jit_trace_calls != NULL)
5585                 max_epilog_size += 50;
5586
5587         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5588                 max_epilog_size += 50;
5589
5590         max_epilog_size += (AMD64_NREG * 2);
5591
5592         return max_epilog_size;
5593 }
5594
5595 /*
5596  * This macro is used for testing whenever the unwinder works correctly at every point
5597  * where an async exception can happen.
5598  */
5599 /* This will generate a SIGSEGV at the given point in the code */
5600 #define async_exc_point(code) do { \
5601     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5602          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5603              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5604          cfg->arch.async_point_count ++; \
5605     } \
5606 } while (0)
5607
5608 guint8 *
5609 mono_arch_emit_prolog (MonoCompile *cfg)
5610 {
5611         MonoMethod *method = cfg->method;
5612         MonoBasicBlock *bb;
5613         MonoMethodSignature *sig;
5614         MonoInst *ins;
5615         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5616         guint8 *code;
5617         CallInfo *cinfo;
5618         gint32 lmf_offset = cfg->arch.lmf_offset;
5619         gboolean args_clobbered = FALSE;
5620         gboolean trace = FALSE;
5621
5622         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
5623
5624         code = cfg->native_code = g_malloc (cfg->code_size);
5625
5626         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5627                 trace = TRUE;
5628
5629         /* Amount of stack space allocated by register saving code */
5630         pos = 0;
5631
5632         /* Offset between RSP and the CFA */
5633         cfa_offset = 0;
5634
5635         /*
5636          * The prolog consists of the following parts:
5637          * FP present:
5638          * - push rbp, mov rbp, rsp
5639          * - save callee saved regs using pushes
5640          * - allocate frame
5641          * - save rgctx if needed
5642          * - save lmf if needed
5643          * FP not present:
5644          * - allocate frame
5645          * - save rgctx if needed
5646          * - save lmf if needed
5647          * - save callee saved regs using moves
5648          */
5649
5650         // CFA = sp + 8
5651         cfa_offset = 8;
5652         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5653         // IP saved at CFA - 8
5654         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5655         async_exc_point (code);
5656
5657         if (!cfg->arch.omit_fp) {
5658                 amd64_push_reg (code, AMD64_RBP);
5659                 cfa_offset += 8;
5660                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5661                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5662                 async_exc_point (code);
5663 #ifdef PLATFORM_WIN32
5664                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5665 #endif
5666
5667                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5668                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5669                 async_exc_point (code);
5670 #ifdef PLATFORM_WIN32
5671                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5672 #endif
5673         }
5674
5675         /* Save callee saved registers */
5676         if (!cfg->arch.omit_fp && !method->save_lmf) {
5677                 int offset = cfa_offset;
5678
5679                 for (i = 0; i < AMD64_NREG; ++i)
5680                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5681                                 amd64_push_reg (code, i);
5682                                 pos += sizeof (gpointer);
5683                                 offset += 8;
5684                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5685                                 async_exc_point (code);
5686                         }
5687         }
5688
5689         /* The param area is always at offset 0 from sp */
5690         /* This needs to be allocated here, since it has to come after the spill area */
5691         if (cfg->arch.no_pushes && cfg->param_area) {
5692                 if (cfg->arch.omit_fp)
5693                         // FIXME:
5694                         g_assert_not_reached ();
5695                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5696         }
5697
5698         if (cfg->arch.omit_fp) {
5699                 /*
5700                  * On enter, the stack is misaligned by the the pushing of the return
5701                  * address. It is either made aligned by the pushing of %rbp, or by
5702                  * this.
5703                  */
5704                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5705                 if ((alloc_size % 16) == 0)
5706                         alloc_size += 8;
5707         } else {
5708                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5709
5710                 alloc_size -= pos;
5711         }
5712
5713         cfg->arch.stack_alloc_size = alloc_size;
5714
5715         /* Allocate stack frame */
5716         if (alloc_size) {
5717                 /* See mono_emit_stack_alloc */
5718 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5719                 guint32 remaining_size = alloc_size;
5720                 while (remaining_size >= 0x1000) {
5721                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5722                         if (cfg->arch.omit_fp) {
5723                                 cfa_offset += 0x1000;
5724                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5725                         }
5726                         async_exc_point (code);
5727 #ifdef PLATFORM_WIN32
5728                         if (cfg->arch.omit_fp)
5729                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5730 #endif
5731
5732                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5733                         remaining_size -= 0x1000;
5734                 }
5735                 if (remaining_size) {
5736                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5737                         if (cfg->arch.omit_fp) {
5738                                 cfa_offset += remaining_size;
5739                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5740                                 async_exc_point (code);
5741                         }
5742 #ifdef PLATFORM_WIN32
5743                         if (cfg->arch.omit_fp)
5744                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5745 #endif
5746                 }
5747 #else
5748                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5749                 if (cfg->arch.omit_fp) {
5750                         cfa_offset += alloc_size;
5751                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5752                         async_exc_point (code);
5753                 }
5754 #endif
5755         }
5756
5757         /* Stack alignment check */
5758 #if 0
5759         {
5760                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5761                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5762                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5763                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5764                 amd64_breakpoint (code);
5765         }
5766 #endif
5767
5768         /* Save LMF */
5769         if (method->save_lmf) {
5770                 /*
5771                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5772                  */
5773                 /* sp is saved right before calls */
5774                 /* Skip method (only needed for trampoline LMF frames) */
5775                 /* Save callee saved regs */
5776                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5777                         int offset;
5778
5779                         switch (i) {
5780                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5781                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5782                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5783                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5784                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5785                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5786 #ifdef PLATFORM_WIN32
5787                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5788                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5789 #endif
5790                         default:
5791                                 offset = -1;
5792                                 break;
5793                         }
5794
5795                         if (offset != -1) {
5796                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5797                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5798                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5799                         }
5800                 }
5801         }
5802
5803         /* Save callee saved registers */
5804         if (cfg->arch.omit_fp && !method->save_lmf) {
5805                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5806
5807                 /* Save caller saved registers after sp is adjusted */
5808                 /* The registers are saved at the bottom of the frame */
5809                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5810                 for (i = 0; i < AMD64_NREG; ++i)
5811                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5812                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5813                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5814                                 save_area_offset += 8;
5815                                 async_exc_point (code);
5816                         }
5817         }
5818
5819         /* store runtime generic context */
5820         if (cfg->rgctx_var) {
5821                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5822                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5823
5824                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5825         }
5826
5827         /* compute max_length in order to use short forward jumps */
5828         max_epilog_size = get_max_epilog_size (cfg);
5829         if (cfg->opt & MONO_OPT_BRANCH) {
5830                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5831                         MonoInst *ins;
5832                         int max_length = 0;
5833
5834                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5835                                 max_length += 6;
5836                         /* max alignment for loops */
5837                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5838                                 max_length += LOOP_ALIGNMENT;
5839
5840                         MONO_BB_FOR_EACH_INS (bb, ins) {
5841                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5842                         }
5843
5844                         /* Take prolog and epilog instrumentation into account */
5845                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5846                                 max_length += max_epilog_size;
5847
5848                         bb->max_length = max_length;
5849                 }
5850         }
5851
5852         sig = mono_method_signature (method);
5853         pos = 0;
5854
5855         cinfo = cfg->arch.cinfo;
5856
5857         if (sig->ret->type != MONO_TYPE_VOID) {
5858                 /* Save volatile arguments to the stack */
5859                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5860                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5861         }
5862
5863         /* Keep this in sync with emit_load_volatile_arguments */
5864         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5865                 ArgInfo *ainfo = cinfo->args + i;
5866                 gint32 stack_offset;
5867                 MonoType *arg_type;
5868
5869                 ins = cfg->args [i];
5870
5871                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5872                         /* Unused arguments */
5873                         continue;
5874
5875                 if (sig->hasthis && (i == 0))
5876                         arg_type = &mono_defaults.object_class->byval_arg;
5877                 else
5878                         arg_type = sig->params [i - sig->hasthis];
5879
5880                 stack_offset = ainfo->offset + ARGS_OFFSET;
5881
5882                 if (cfg->globalra) {
5883                         /* All the other moves are done by the register allocator */
5884                         switch (ainfo->storage) {
5885                         case ArgInFloatSSEReg:
5886                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5887                                 break;
5888                         case ArgValuetypeInReg:
5889                                 for (quad = 0; quad < 2; quad ++) {
5890                                         switch (ainfo->pair_storage [quad]) {
5891                                         case ArgInIReg:
5892                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5893                                                 break;
5894                                         case ArgInFloatSSEReg:
5895                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5896                                                 break;
5897                                         case ArgInDoubleSSEReg:
5898                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5899                                                 break;
5900                                         case ArgNone:
5901                                                 break;
5902                                         default:
5903                                                 g_assert_not_reached ();
5904                                         }
5905                                 }
5906                                 break;
5907                         default:
5908                                 break;
5909                         }
5910
5911                         continue;
5912                 }
5913
5914                 /* Save volatile arguments to the stack */
5915                 if (ins->opcode != OP_REGVAR) {
5916                         switch (ainfo->storage) {
5917                         case ArgInIReg: {
5918                                 guint32 size = 8;
5919
5920                                 /* FIXME: I1 etc */
5921                                 /*
5922                                 if (stack_offset & 0x1)
5923                                         size = 1;
5924                                 else if (stack_offset & 0x2)
5925                                         size = 2;
5926                                 else if (stack_offset & 0x4)
5927                                         size = 4;
5928                                 else
5929                                         size = 8;
5930                                 */
5931                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5932                                 break;
5933                         }
5934                         case ArgInFloatSSEReg:
5935                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5936                                 break;
5937                         case ArgInDoubleSSEReg:
5938                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5939                                 break;
5940                         case ArgValuetypeInReg:
5941                                 for (quad = 0; quad < 2; quad ++) {
5942                                         switch (ainfo->pair_storage [quad]) {
5943                                         case ArgInIReg:
5944                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5945                                                 break;
5946                                         case ArgInFloatSSEReg:
5947                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5948                                                 break;
5949                                         case ArgInDoubleSSEReg:
5950                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5951                                                 break;
5952                                         case ArgNone:
5953                                                 break;
5954                                         default:
5955                                                 g_assert_not_reached ();
5956                                         }
5957                                 }
5958                                 break;
5959                         case ArgValuetypeAddrInIReg:
5960                                 if (ainfo->pair_storage [0] == ArgInIReg)
5961                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5962                                 break;
5963                         default:
5964                                 break;
5965                         }
5966                 } else {
5967                         /* Argument allocated to (non-volatile) register */
5968                         switch (ainfo->storage) {
5969                         case ArgInIReg:
5970                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5971                                 break;
5972                         case ArgOnStack:
5973                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5974                                 break;
5975                         default:
5976                                 g_assert_not_reached ();
5977                         }
5978                 }
5979         }
5980
5981         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5982         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5983                 guint64 domain = (guint64)cfg->domain;
5984
5985                 args_clobbered = TRUE;
5986
5987                 /*
5988                  * The call might clobber argument registers, but they are already
5989                  * saved to the stack/global regs.
5990                  */
5991                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5992                         guint8 *buf, *no_domain_branch;
5993
5994                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5995                         if (cfg->compile_aot) {
5996                                 /* AOT code is only used in the root domain */
5997                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
5998                         } else {
5999                                 if ((domain >> 32) == 0)
6000                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6001                                 else
6002                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6003                         }
6004                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6005                         no_domain_branch = code;
6006                         x86_branch8 (code, X86_CC_NE, 0, 0);
6007                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6008                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6009                         buf = code;
6010                         x86_branch8 (code, X86_CC_NE, 0, 0);
6011                         amd64_patch (no_domain_branch, code);
6012                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6013                                           (gpointer)"mono_jit_thread_attach", TRUE);
6014                         amd64_patch (buf, code);
6015 #ifdef PLATFORM_WIN32
6016                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6017                         /* FIXME: Add a separate key for LMF to avoid this */
6018                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6019 #endif
6020                 } else {
6021                         g_assert (!cfg->compile_aot);
6022                         if (cfg->compile_aot) {
6023                                 /* AOT code is only used in the root domain */
6024                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6025                         } else {
6026                                 if ((domain >> 32) == 0)
6027                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6028                                 else
6029                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6030                         }
6031                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6032                                           (gpointer)"mono_jit_thread_attach", TRUE);
6033                 }
6034         }
6035
6036         if (method->save_lmf) {
6037                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6038                         /*
6039                          * Optimized version which uses the mono_lmf TLS variable instead of
6040                          * indirection through the mono_lmf_addr TLS variable.
6041                          */
6042                         /* %rax = previous_lmf */
6043                         x86_prefix (code, X86_FS_PREFIX);
6044                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6045
6046                         /* Save previous_lmf */
6047                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6048                         /* Set new lmf */
6049                         if (lmf_offset == 0) {
6050                                 x86_prefix (code, X86_FS_PREFIX);
6051                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6052                         } else {
6053                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6054                                 x86_prefix (code, X86_FS_PREFIX);
6055                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6056                         }
6057                 } else {
6058                         if (lmf_addr_tls_offset != -1) {
6059                                 /* Load lmf quicky using the FS register */
6060                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6061 #ifdef PLATFORM_WIN32
6062                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6063                                 /* FIXME: Add a separate key for LMF to avoid this */
6064                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6065 #endif
6066                         }
6067                         else {
6068                                 /*
6069                                  * The call might clobber argument registers, but they are already
6070                                  * saved to the stack/global regs.
6071                                  */
6072                                 args_clobbered = TRUE;
6073                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6074                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6075                         }
6076
6077                         /* Save lmf_addr */
6078                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6079                         /* Save previous_lmf */
6080                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6081                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6082                         /* Set new lmf */
6083                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6084                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6085                 }
6086         }
6087
6088         if (trace) {
6089                 args_clobbered = TRUE;
6090                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6091         }
6092
6093         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6094                 args_clobbered = TRUE;
6095
6096         /*
6097          * Optimize the common case of the first bblock making a call with the same
6098          * arguments as the method. This works because the arguments are still in their
6099          * original argument registers.
6100          * FIXME: Generalize this
6101          */
6102         if (!args_clobbered) {
6103                 MonoBasicBlock *first_bb = cfg->bb_entry;
6104                 MonoInst *next;
6105
6106                 next = mono_bb_first_ins (first_bb);
6107                 if (!next && first_bb->next_bb) {
6108                         first_bb = first_bb->next_bb;
6109                         next = mono_bb_first_ins (first_bb);
6110                 }
6111
6112                 if (first_bb->in_count > 1)
6113                         next = NULL;
6114
6115                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6116                         ArgInfo *ainfo = cinfo->args + i;
6117                         gboolean match = FALSE;
6118
6119                         ins = cfg->args [i];
6120                         if (ins->opcode != OP_REGVAR) {
6121                                 switch (ainfo->storage) {
6122                                 case ArgInIReg: {
6123                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6124                                                 if (next->dreg == ainfo->reg) {
6125                                                         NULLIFY_INS (next);
6126                                                         match = TRUE;
6127                                                 } else {
6128                                                         next->opcode = OP_MOVE;
6129                                                         next->sreg1 = ainfo->reg;
6130                                                         /* Only continue if the instruction doesn't change argument regs */
6131                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6132                                                                 match = TRUE;
6133                                                 }
6134                                         }
6135                                         break;
6136                                 }
6137                                 default:
6138                                         break;
6139                                 }
6140                         } else {
6141                                 /* Argument allocated to (non-volatile) register */
6142                                 switch (ainfo->storage) {
6143                                 case ArgInIReg:
6144                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6145                                                 NULLIFY_INS (next);
6146                                                 match = TRUE;
6147                                         }
6148                                         break;
6149                                 default:
6150                                         break;
6151                                 }
6152                         }
6153
6154                         if (match) {
6155                                 next = next->next;
6156                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6157                                 if (!next)
6158                                         break;
6159                         }
6160                 }
6161         }
6162
6163         cfg->code_len = code - cfg->native_code;
6164
6165         g_assert (cfg->code_len < cfg->code_size);
6166
6167         return code;
6168 }
6169
6170 void
6171 mono_arch_emit_epilog (MonoCompile *cfg)
6172 {
6173         MonoMethod *method = cfg->method;
6174         int quad, pos, i;
6175         guint8 *code;
6176         int max_epilog_size;
6177         CallInfo *cinfo;
6178         gint32 lmf_offset = cfg->arch.lmf_offset;
6179
6180         max_epilog_size = get_max_epilog_size (cfg);
6181
6182         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6183                 cfg->code_size *= 2;
6184                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6185                 mono_jit_stats.code_reallocs++;
6186         }
6187
6188         code = cfg->native_code + cfg->code_len;
6189
6190         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6191                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6192
6193         /* the code restoring the registers must be kept in sync with OP_JMP */
6194         pos = 0;
6195
6196         if (method->save_lmf) {
6197                 /* check if we need to restore protection of the stack after a stack overflow */
6198                 if (mono_get_jit_tls_offset () != -1) {
6199                         guint8 *patch;
6200                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6201                         /* we load the value in a separate instruction: this mechanism may be
6202                          * used later as a safer way to do thread interruption
6203                          */
6204                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6205                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6206                         patch = code;
6207                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6208                         /* note that the call trampoline will preserve eax/edx */
6209                         x86_call_reg (code, X86_ECX);
6210                         x86_patch (patch, code);
6211                 } else {
6212                         /* FIXME: maybe save the jit tls in the prolog */
6213                 }
6214                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6215                         /*
6216                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6217                          * through the mono_lmf_addr TLS variable.
6218                          */
6219                         /* reg = previous_lmf */
6220                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6221                         x86_prefix (code, X86_FS_PREFIX);
6222                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6223                 } else {
6224                         /* Restore previous lmf */
6225                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6226                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6227                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6228                 }
6229
6230                 /* Restore caller saved regs */
6231                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6232                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6233                 }
6234                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6235                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6236                 }
6237                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6238                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6239                 }
6240                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6241                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6242                 }
6243                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6244                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6245                 }
6246                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6247                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6248                 }
6249 #ifdef PLATFORM_WIN32
6250                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6251                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6252                 }
6253                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6254                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6255                 }
6256 #endif
6257         } else {
6258
6259                 if (cfg->arch.omit_fp) {
6260                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6261
6262                         for (i = 0; i < AMD64_NREG; ++i)
6263                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6264                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6265                                         save_area_offset += 8;
6266                                 }
6267                 }
6268                 else {
6269                         for (i = 0; i < AMD64_NREG; ++i)
6270                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6271                                         pos -= sizeof (gpointer);
6272
6273                         if (pos) {
6274                                 if (pos == - sizeof (gpointer)) {
6275                                         /* Only one register, so avoid lea */
6276                                         for (i = AMD64_NREG - 1; i > 0; --i)
6277                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6278                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6279                                                 }
6280                                 }
6281                                 else {
6282                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6283
6284                                         /* Pop registers in reverse order */
6285                                         for (i = AMD64_NREG - 1; i > 0; --i)
6286                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6287                                                         amd64_pop_reg (code, i);
6288                                                 }
6289                                 }
6290                         }
6291                 }
6292         }
6293
6294         /* Load returned vtypes into registers if needed */
6295         cinfo = cfg->arch.cinfo;
6296         if (cinfo->ret.storage == ArgValuetypeInReg) {
6297                 ArgInfo *ainfo = &cinfo->ret;
6298                 MonoInst *inst = cfg->ret;
6299
6300                 for (quad = 0; quad < 2; quad ++) {
6301                         switch (ainfo->pair_storage [quad]) {
6302                         case ArgInIReg:
6303                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6304                                 break;
6305                         case ArgInFloatSSEReg:
6306                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6307                                 break;
6308                         case ArgInDoubleSSEReg:
6309                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6310                                 break;
6311                         case ArgNone:
6312                                 break;
6313                         default:
6314                                 g_assert_not_reached ();
6315                         }
6316                 }
6317         }
6318
6319         if (cfg->arch.omit_fp) {
6320                 if (cfg->arch.stack_alloc_size)
6321                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6322         } else {
6323                 amd64_leave (code);
6324         }
6325         async_exc_point (code);
6326         amd64_ret (code);
6327
6328         cfg->code_len = code - cfg->native_code;
6329
6330         g_assert (cfg->code_len < cfg->code_size);
6331 }
6332
6333 void
6334 mono_arch_emit_exceptions (MonoCompile *cfg)
6335 {
6336         MonoJumpInfo *patch_info;
6337         int nthrows, i;
6338         guint8 *code;
6339         MonoClass *exc_classes [16];
6340         guint8 *exc_throw_start [16], *exc_throw_end [16];
6341         guint32 code_size = 0;
6342
6343         /* Compute needed space */
6344         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6345                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6346                         code_size += 40;
6347                 if (patch_info->type == MONO_PATCH_INFO_R8)
6348                         code_size += 8 + 15; /* sizeof (double) + alignment */
6349                 if (patch_info->type == MONO_PATCH_INFO_R4)
6350                         code_size += 4 + 15; /* sizeof (float) + alignment */
6351         }
6352
6353         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6354                 cfg->code_size *= 2;
6355                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6356                 mono_jit_stats.code_reallocs++;
6357         }
6358
6359         code = cfg->native_code + cfg->code_len;
6360
6361         /* add code to raise exceptions */
6362         nthrows = 0;
6363         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6364                 switch (patch_info->type) {
6365                 case MONO_PATCH_INFO_EXC: {
6366                         MonoClass *exc_class;
6367                         guint8 *buf, *buf2;
6368                         guint32 throw_ip;
6369
6370                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6371
6372                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6373                         g_assert (exc_class);
6374                         throw_ip = patch_info->ip.i;
6375
6376                         //x86_breakpoint (code);
6377                         /* Find a throw sequence for the same exception class */
6378                         for (i = 0; i < nthrows; ++i)
6379                                 if (exc_classes [i] == exc_class)
6380                                         break;
6381                         if (i < nthrows) {
6382                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6383                                 x86_jump_code (code, exc_throw_start [i]);
6384                                 patch_info->type = MONO_PATCH_INFO_NONE;
6385                         }
6386                         else {
6387                                 buf = code;
6388                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6389                                 buf2 = code;
6390
6391                                 if (nthrows < 16) {
6392                                         exc_classes [nthrows] = exc_class;
6393                                         exc_throw_start [nthrows] = code;
6394                                 }
6395                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6396
6397                                 patch_info->type = MONO_PATCH_INFO_NONE;
6398
6399                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6400
6401                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6402                                 while (buf < buf2)
6403                                         x86_nop (buf);
6404
6405                                 if (nthrows < 16) {
6406                                         exc_throw_end [nthrows] = code;
6407                                         nthrows ++;
6408                                 }
6409                         }
6410                         break;
6411                 }
6412                 default:
6413                         /* do nothing */
6414                         break;
6415                 }
6416         }
6417
6418         /* Handle relocations with RIP relative addressing */
6419         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6420                 gboolean remove = FALSE;
6421
6422                 switch (patch_info->type) {
6423                 case MONO_PATCH_INFO_R8:
6424                 case MONO_PATCH_INFO_R4: {
6425                         guint8 *pos;
6426
6427                         /* The SSE opcodes require a 16 byte alignment */
6428                         code = (guint8*)ALIGN_TO (code, 16);
6429
6430                         pos = cfg->native_code + patch_info->ip.i;
6431
6432                         if (IS_REX (pos [1]))
6433                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6434                         else
6435                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6436
6437                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6438                                 *(double*)code = *(double*)patch_info->data.target;
6439                                 code += sizeof (double);
6440                         } else {
6441                                 *(float*)code = *(float*)patch_info->data.target;
6442                                 code += sizeof (float);
6443                         }
6444
6445                         remove = TRUE;
6446                         break;
6447                 }
6448                 default:
6449                         break;
6450                 }
6451
6452                 if (remove) {
6453                         if (patch_info == cfg->patch_info)
6454                                 cfg->patch_info = patch_info->next;
6455                         else {
6456                                 MonoJumpInfo *tmp;
6457
6458                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6459                                         ;
6460                                 tmp->next = patch_info->next;
6461                         }
6462                 }
6463         }
6464
6465         cfg->code_len = code - cfg->native_code;
6466
6467         g_assert (cfg->code_len < cfg->code_size);
6468
6469 }
6470
6471 void*
6472 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6473 {
6474         guchar *code = p;
6475         CallInfo *cinfo = NULL;
6476         MonoMethodSignature *sig;
6477         MonoInst *inst;
6478         int i, n, stack_area = 0;
6479
6480         /* Keep this in sync with mono_arch_get_argument_info */
6481
6482         if (enable_arguments) {
6483                 /* Allocate a new area on the stack and save arguments there */
6484                 sig = mono_method_signature (cfg->method);
6485
6486                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6487
6488                 n = sig->param_count + sig->hasthis;
6489
6490                 stack_area = ALIGN_TO (n * 8, 16);
6491
6492                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6493
6494                 for (i = 0; i < n; ++i) {
6495                         inst = cfg->args [i];
6496
6497                         if (inst->opcode == OP_REGVAR)
6498                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6499                         else {
6500                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6501                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6502                         }
6503                 }
6504         }
6505
6506         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6507         amd64_set_reg_template (code, AMD64_ARG_REG1);
6508         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6509         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6510
6511         if (enable_arguments)
6512                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6513
6514         return code;
6515 }
6516
6517 enum {
6518         SAVE_NONE,
6519         SAVE_STRUCT,
6520         SAVE_EAX,
6521         SAVE_EAX_EDX,
6522         SAVE_XMM
6523 };
6524
6525 void*
6526 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6527 {
6528         guchar *code = p;
6529         int save_mode = SAVE_NONE;
6530         MonoMethod *method = cfg->method;
6531         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
6532
6533         switch (rtype) {
6534         case MONO_TYPE_VOID:
6535                 /* special case string .ctor icall */
6536                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6537                         save_mode = SAVE_EAX;
6538                 else
6539                         save_mode = SAVE_NONE;
6540                 break;
6541         case MONO_TYPE_I8:
6542         case MONO_TYPE_U8:
6543                 save_mode = SAVE_EAX;
6544                 break;
6545         case MONO_TYPE_R4:
6546         case MONO_TYPE_R8:
6547                 save_mode = SAVE_XMM;
6548                 break;
6549         case MONO_TYPE_GENERICINST:
6550                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
6551                         save_mode = SAVE_EAX;
6552                         break;
6553                 }
6554                 /* Fall through */
6555         case MONO_TYPE_VALUETYPE:
6556                 save_mode = SAVE_STRUCT;
6557                 break;
6558         default:
6559                 save_mode = SAVE_EAX;
6560                 break;
6561         }
6562
6563         /* Save the result and copy it into the proper argument register */
6564         switch (save_mode) {
6565         case SAVE_EAX:
6566                 amd64_push_reg (code, AMD64_RAX);
6567                 /* Align stack */
6568                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6569                 if (enable_arguments)
6570                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6571                 break;
6572         case SAVE_STRUCT:
6573                 /* FIXME: */
6574                 if (enable_arguments)
6575                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6576                 break;
6577         case SAVE_XMM:
6578                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6579                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6580                 /* Align stack */
6581                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6582                 /*
6583                  * The result is already in the proper argument register so no copying
6584                  * needed.
6585                  */
6586                 break;
6587         case SAVE_NONE:
6588                 break;
6589         default:
6590                 g_assert_not_reached ();
6591         }
6592
6593         /* Set %al since this is a varargs call */
6594         if (save_mode == SAVE_XMM)
6595                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6596         else
6597                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6598
6599         if (preserve_argument_registers) {
6600                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6601                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6602         }
6603
6604         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6605         amd64_set_reg_template (code, AMD64_ARG_REG1);
6606         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6607
6608         if (preserve_argument_registers) {
6609                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6610                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6611         }
6612
6613         /* Restore result */
6614         switch (save_mode) {
6615         case SAVE_EAX:
6616                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6617                 amd64_pop_reg (code, AMD64_RAX);
6618                 break;
6619         case SAVE_STRUCT:
6620                 /* FIXME: */
6621                 break;
6622         case SAVE_XMM:
6623                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6624                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6625                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6626                 break;
6627         case SAVE_NONE:
6628                 break;
6629         default:
6630                 g_assert_not_reached ();
6631         }
6632
6633         return code;
6634 }
6635
6636 void
6637 mono_arch_flush_icache (guint8 *code, gint size)
6638 {
6639         /* Not needed */
6640 }
6641
6642 void
6643 mono_arch_flush_register_windows (void)
6644 {
6645 }
6646
6647 gboolean
6648 mono_arch_is_inst_imm (gint64 imm)
6649 {
6650         return amd64_is_imm32 (imm);
6651 }
6652
6653 /*
6654  * Determine whenever the trap whose info is in SIGINFO is caused by
6655  * integer overflow.
6656  */
6657 gboolean
6658 mono_arch_is_int_overflow (void *sigctx, void *info)
6659 {
6660         MonoContext ctx;
6661         guint8* rip;
6662         int reg;
6663         gint64 value;
6664
6665         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6666
6667         rip = (guint8*)ctx.rip;
6668
6669         if (IS_REX (rip [0])) {
6670                 reg = amd64_rex_b (rip [0]);
6671                 rip ++;
6672         }
6673         else
6674                 reg = 0;
6675
6676         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6677                 /* idiv REG */
6678                 reg += x86_modrm_rm (rip [1]);
6679
6680                 switch (reg) {
6681                 case AMD64_RAX:
6682                         value = ctx.rax;
6683                         break;
6684                 case AMD64_RBX:
6685                         value = ctx.rbx;
6686                         break;
6687                 case AMD64_RCX:
6688                         value = ctx.rcx;
6689                         break;
6690                 case AMD64_RDX:
6691                         value = ctx.rdx;
6692                         break;
6693                 case AMD64_RBP:
6694                         value = ctx.rbp;
6695                         break;
6696                 case AMD64_RSP:
6697                         value = ctx.rsp;
6698                         break;
6699                 case AMD64_RSI:
6700                         value = ctx.rsi;
6701                         break;
6702                 case AMD64_RDI:
6703                         value = ctx.rdi;
6704                         break;
6705                 case AMD64_R12:
6706                         value = ctx.r12;
6707                         break;
6708                 case AMD64_R13:
6709                         value = ctx.r13;
6710                         break;
6711                 case AMD64_R14:
6712                         value = ctx.r14;
6713                         break;
6714                 case AMD64_R15:
6715                         value = ctx.r15;
6716                         break;
6717                 default:
6718                         g_assert_not_reached ();
6719                         reg = -1;
6720                 }
6721
6722                 if (value == -1)
6723                         return TRUE;
6724         }
6725
6726         return FALSE;
6727 }
6728
6729 guint32
6730 mono_arch_get_patch_offset (guint8 *code)
6731 {
6732         return 3;
6733 }
6734
6735 /**
6736  * mono_breakpoint_clean_code:
6737  *
6738  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6739  * breakpoints in the original code, they are removed in the copy.
6740  *
6741  * Returns TRUE if no sw breakpoint was present.
6742  */
6743 gboolean
6744 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6745 {
6746         int i;
6747         gboolean can_write = TRUE;
6748         /*
6749          * If method_start is non-NULL we need to perform bound checks, since we access memory
6750          * at code - offset we could go before the start of the method and end up in a different
6751          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6752          * instead.
6753          */
6754         if (!method_start || code - offset >= method_start) {
6755                 memcpy (buf, code - offset, size);
6756         } else {
6757                 int diff = code - method_start;
6758                 memset (buf, 0, size);
6759                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6760         }
6761         code -= offset;
6762         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6763                 int idx = mono_breakpoint_info_index [i];
6764                 guint8 *ptr;
6765                 if (idx < 1)
6766                         continue;
6767                 ptr = mono_breakpoint_info [idx].address;
6768                 if (ptr >= code && ptr < code + size) {
6769                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6770                         can_write = FALSE;
6771                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6772                         buf [ptr - code] = saved_byte;
6773                 }
6774         }
6775         return can_write;
6776 }
6777
6778 gpointer
6779 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6780 {
6781         guint8 buf [10];
6782         guint32 reg;
6783         gint32 disp;
6784         guint8 rex = 0;
6785         MonoJitInfo *ji = NULL;
6786
6787 #ifdef ENABLE_LLVM
6788         /* code - 9 might be before the start of the method */
6789         /* FIXME: Avoid this expensive call somehow */
6790         ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6791 #endif
6792
6793         mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6794         code = buf + 9;
6795
6796         *displacement = 0;
6797
6798         code -= 7;
6799
6800         /*
6801          * A given byte sequence can match more than case here, so we have to be
6802          * really careful about the ordering of the cases. Longer sequences
6803          * come first.
6804          * There are two types of calls:
6805          * - direct calls: 0xff address_byte 8/32 bits displacement
6806          * - indirect calls: nop nop nop <call>
6807          * The nops make sure we don't confuse the instruction preceeding an indirect
6808          * call with a direct call.
6809          */
6810         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6811                 /* call OFFSET(%rip) */
6812                 disp = *(guint32*)(code + 3);
6813                 return (gpointer*)(code + disp + 7);
6814         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6815                 /* call *[reg+disp32] using indexed addressing */
6816                 /* The LLVM JIT emits this, and we emit it too for %r12 */
6817                 if (IS_REX (code [-1])) {
6818                         rex = code [-1];
6819                         g_assert (amd64_rex_x (rex) == 0);
6820                 }
6821                 reg = amd64_sib_base (code [2]);
6822                 disp = *(gint32*)(code + 3);
6823         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6824                 /* call *[reg+disp32] */
6825                 if (IS_REX (code [0]))
6826                         rex = code [0];
6827                 reg = amd64_modrm_rm (code [2]);
6828                 disp = *(gint32*)(code + 3);
6829                 /* R10 is clobbered by the IMT thunk code */
6830                 g_assert (reg != AMD64_R10);
6831         } else if (code [2] == 0xe8) {
6832                 /* call <ADDR> */
6833                 return NULL;
6834         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6835                 /* call *[r12+disp8] using indexed addressing */
6836                 if (IS_REX (code [2]))
6837                         rex = code [2];
6838                 reg = amd64_sib_base (code [5]);
6839                 disp = *(gint8*)(code + 6);
6840         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6841                 /* call *%reg */
6842                 return NULL;
6843         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6844                 /* call *[reg+disp8] */
6845                 if (IS_REX (code [3]))
6846                         rex = code [3];
6847                 reg = amd64_modrm_rm (code [5]);
6848                 disp = *(gint8*)(code + 6);
6849                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6850         }
6851         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6852                 /* call *%reg */
6853                 if (IS_REX (code [4]))
6854                         rex = code [4];
6855                 reg = amd64_modrm_rm (code [6]);
6856                 disp = 0;
6857         }
6858         else
6859                 g_assert_not_reached ();
6860
6861         reg += amd64_rex_b (rex);
6862
6863         /* R11 is clobbered by the trampoline code */
6864         g_assert (reg != AMD64_R11);
6865
6866         *displacement = disp;
6867         return (gpointer)regs [reg];
6868 }
6869
6870 int
6871 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6872 {
6873         int this_reg = AMD64_ARG_REG1;
6874
6875         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6876                 CallInfo *cinfo;
6877
6878                 if (!gsctx && code)
6879                         gsctx = mono_get_generic_context_from_code (code);
6880
6881                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6882
6883                 if (cinfo->ret.storage != ArgValuetypeInReg)
6884                         this_reg = AMD64_ARG_REG2;
6885                 g_free (cinfo);
6886         }
6887
6888         return this_reg;
6889 }
6890
6891 gpointer
6892 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
6893 {
6894         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6895 }
6896
6897 #define MAX_ARCH_DELEGATE_PARAMS 10
6898
6899 static gpointer
6900 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6901 {
6902         guint8 *code, *start;
6903         int i;
6904
6905         if (has_target) {
6906                 start = code = mono_global_codeman_reserve (64);
6907
6908                 /* Replace the this argument with the target */
6909                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6910                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6911                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6912
6913                 g_assert ((code - start) < 64);
6914         } else {
6915                 start = code = mono_global_codeman_reserve (64);
6916
6917                 if (param_count == 0) {
6918                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6919                 } else {
6920                         /* We have to shift the arguments left */
6921                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6922                         for (i = 0; i < param_count; ++i) {
6923 #ifdef PLATFORM_WIN32
6924                                 if (i < 3)
6925                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6926                                 else
6927                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6928 #else
6929                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6930 #endif
6931                         }
6932
6933                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6934                 }
6935                 g_assert ((code - start) < 64);
6936         }
6937
6938         mono_debug_add_delegate_trampoline (start, code - start);
6939
6940         if (code_len)
6941                 *code_len = code - start;
6942
6943         return start;
6944 }
6945
6946 /*
6947  * mono_arch_get_delegate_invoke_impls:
6948  *
6949  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
6950  * trampolines.
6951  */
6952 GSList*
6953 mono_arch_get_delegate_invoke_impls (void)
6954 {
6955         GSList *res = NULL;
6956         guint8 *code;
6957         guint32 code_len;
6958         int i;
6959
6960         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6961         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
6962
6963         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6964                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6965                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
6966         }
6967
6968         return res;
6969 }
6970
6971 gpointer
6972 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6973 {
6974         guint8 *code, *start;
6975         int i;
6976
6977         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6978                 return NULL;
6979
6980         /* FIXME: Support more cases */
6981         if (MONO_TYPE_ISSTRUCT (sig->ret))
6982                 return NULL;
6983
6984         if (has_target) {
6985                 static guint8* cached = NULL;
6986
6987                 if (cached)
6988                         return cached;
6989
6990                 if (mono_aot_only)
6991                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
6992                 else
6993                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
6994
6995                 mono_memory_barrier ();
6996
6997                 cached = start;
6998         } else {
6999                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7000                 for (i = 0; i < sig->param_count; ++i)
7001                         if (!mono_is_regsize_var (sig->params [i]))
7002                                 return NULL;
7003                 if (sig->param_count > 4)
7004                         return NULL;
7005
7006                 code = cache [sig->param_count];
7007                 if (code)
7008                         return code;
7009
7010                 if (mono_aot_only) {
7011                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7012                         start = mono_aot_get_named_code (name);
7013                         g_free (name);
7014                 } else {
7015                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7016                 }
7017
7018                 mono_memory_barrier ();
7019
7020                 cache [sig->param_count] = start;
7021         }
7022
7023         return start;
7024 }
7025
7026 /*
7027  * Support for fast access to the thread-local lmf structure using the GS
7028  * segment register on NPTL + kernel 2.6.x.
7029  */
7030
7031 static gboolean tls_offset_inited = FALSE;
7032
7033 void
7034 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7035 {
7036         if (!tls_offset_inited) {
7037 #ifdef PLATFORM_WIN32
7038                 /*
7039                  * We need to init this multiple times, since when we are first called, the key might not
7040                  * be initialized yet.
7041                  */
7042                 appdomain_tls_offset = mono_domain_get_tls_key ();
7043                 lmf_tls_offset = mono_get_jit_tls_key ();
7044                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7045
7046                 /* Only 64 tls entries can be accessed using inline code */
7047                 if (appdomain_tls_offset >= 64)
7048                         appdomain_tls_offset = -1;
7049                 if (lmf_tls_offset >= 64)
7050                         lmf_tls_offset = -1;
7051 #else
7052                 tls_offset_inited = TRUE;
7053 #ifdef MONO_XEN_OPT
7054                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7055 #endif
7056                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7057                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7058                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7059 #endif
7060         }
7061 }
7062
7063 void
7064 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7065 {
7066 }
7067
7068 #ifdef MONO_ARCH_HAVE_IMT
7069
7070 #define CMP_SIZE (6 + 1)
7071 #define CMP_REG_REG_SIZE (4 + 1)
7072 #define BR_SMALL_SIZE 2
7073 #define BR_LARGE_SIZE 6
7074 #define MOV_REG_IMM_SIZE 10
7075 #define MOV_REG_IMM_32BIT_SIZE 6
7076 #define JUMP_REG_SIZE (2 + 1)
7077
7078 static int
7079 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7080 {
7081         int i, distance = 0;
7082         for (i = start; i < target; ++i)
7083                 distance += imt_entries [i]->chunk_size;
7084         return distance;
7085 }
7086
7087 /*
7088  * LOCKING: called with the domain lock held
7089  */
7090 gpointer
7091 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7092         gpointer fail_tramp)
7093 {
7094         int i;
7095         int size = 0;
7096         guint8 *code, *start;
7097         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7098
7099         for (i = 0; i < count; ++i) {
7100                 MonoIMTCheckItem *item = imt_entries [i];
7101                 if (item->is_equals) {
7102                         if (item->check_target_idx) {
7103                                 if (!item->compare_done) {
7104                                         if (amd64_is_imm32 (item->key))
7105                                                 item->chunk_size += CMP_SIZE;
7106                                         else
7107                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7108                                 }
7109                                 if (item->has_target_code) {
7110                                         item->chunk_size += MOV_REG_IMM_SIZE;
7111                                 } else {
7112                                         if (vtable_is_32bit)
7113                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7114                                         else
7115                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7116                                 }
7117                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7118                         } else {
7119                                 if (fail_tramp) {
7120                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7121                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7122                                 } else {
7123                                         if (vtable_is_32bit)
7124                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7125                                         else
7126                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7127                                         item->chunk_size += JUMP_REG_SIZE;
7128                                         /* with assert below:
7129                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7130                                          */
7131                                 }
7132                         }
7133                 } else {
7134                         if (amd64_is_imm32 (item->key))
7135                                 item->chunk_size += CMP_SIZE;
7136                         else
7137                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7138                         item->chunk_size += BR_LARGE_SIZE;
7139                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7140                 }
7141                 size += item->chunk_size;
7142         }
7143         if (fail_tramp)
7144                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7145         else
7146                 code = mono_domain_code_reserve (domain, size);
7147         start = code;
7148         for (i = 0; i < count; ++i) {
7149                 MonoIMTCheckItem *item = imt_entries [i];
7150                 item->code_target = code;
7151                 if (item->is_equals) {
7152                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7153
7154                         if (item->check_target_idx || fail_case) {
7155                                 if (!item->compare_done || fail_case) {
7156                                         if (amd64_is_imm32 (item->key))
7157                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7158                                         else {
7159                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7160                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7161                                         }
7162                                 }
7163                                 item->jmp_code = code;
7164                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7165                                 /* See the comment below about R10 */
7166                                 if (item->has_target_code) {
7167                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7168                                         amd64_jump_reg (code, AMD64_R10);
7169                                 } else {
7170                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7171                                         amd64_jump_membase (code, AMD64_R10, 0);
7172                                 }
7173
7174                                 if (fail_case) {
7175                                         amd64_patch (item->jmp_code, code);
7176                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7177                                         amd64_jump_reg (code, AMD64_R10);
7178                                         item->jmp_code = NULL;
7179                                 }
7180                         } else {
7181                                 /* enable the commented code to assert on wrong method */
7182 #if 0
7183                                 if (amd64_is_imm32 (item->key))
7184                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7185                                 else {
7186                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
7187                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7188                                 }
7189                                 item->jmp_code = code;
7190                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7191                                 /* See the comment below about R10 */
7192                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7193                                 amd64_jump_membase (code, AMD64_R10, 0);
7194                                 amd64_patch (item->jmp_code, code);
7195                                 amd64_breakpoint (code);
7196                                 item->jmp_code = NULL;
7197 #else
7198                                 /* We're using R10 here because R11
7199                                    needs to be preserved.  R10 needs
7200                                    to be preserved for calls which
7201                                    require a runtime generic context,
7202                                    but interface calls don't. */
7203                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7204                                 amd64_jump_membase (code, AMD64_R10, 0);
7205 #endif
7206                         }
7207                 } else {
7208                         if (amd64_is_imm32 (item->key))
7209                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7210                         else {
7211                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7212                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7213                         }
7214                         item->jmp_code = code;
7215                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7216                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7217                         else
7218                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7219                 }
7220                 g_assert (code - item->code_target <= item->chunk_size);
7221         }
7222         /* patch the branches to get to the target items */
7223         for (i = 0; i < count; ++i) {
7224                 MonoIMTCheckItem *item = imt_entries [i];
7225                 if (item->jmp_code) {
7226                         if (item->check_target_idx) {
7227                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7228                         }
7229                 }
7230         }
7231
7232         if (!fail_tramp)
7233                 mono_stats.imt_thunks_size += code - start;
7234         g_assert (code - start <= size);
7235
7236         return start;
7237 }
7238
7239 MonoMethod*
7240 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7241 {
7242         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7243 }
7244
7245 MonoObject*
7246 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
7247 {
7248         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), regs, NULL);
7249 }
7250 #endif
7251
7252 MonoVTable*
7253 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7254 {
7255         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7256 }
7257
7258 MonoInst*
7259 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7260 {
7261         MonoInst *ins = NULL;
7262         int opcode = 0;
7263
7264         if (cmethod->klass == mono_defaults.math_class) {
7265                 if (strcmp (cmethod->name, "Sin") == 0) {
7266                         opcode = OP_SIN;
7267                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7268                         opcode = OP_COS;
7269                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7270                         opcode = OP_SQRT;
7271                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7272                         opcode = OP_ABS;
7273                 }
7274
7275                 if (opcode) {
7276                         MONO_INST_NEW (cfg, ins, opcode);
7277                         ins->type = STACK_R8;
7278                         ins->dreg = mono_alloc_freg (cfg);
7279                         ins->sreg1 = args [0]->dreg;
7280                         MONO_ADD_INS (cfg->cbb, ins);
7281                 }
7282
7283                 opcode = 0;
7284                 if (cfg->opt & MONO_OPT_CMOV) {
7285                         if (strcmp (cmethod->name, "Min") == 0) {
7286                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7287                                         opcode = OP_IMIN;
7288                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7289                                         opcode = OP_IMIN_UN;
7290                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7291                                         opcode = OP_LMIN;
7292                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7293                                         opcode = OP_LMIN_UN;
7294                         } else if (strcmp (cmethod->name, "Max") == 0) {
7295                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7296                                         opcode = OP_IMAX;
7297                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7298                                         opcode = OP_IMAX_UN;
7299                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7300                                         opcode = OP_LMAX;
7301                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7302                                         opcode = OP_LMAX_UN;
7303                         }
7304                 }
7305
7306                 if (opcode) {
7307                         MONO_INST_NEW (cfg, ins, opcode);
7308                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7309                         ins->dreg = mono_alloc_ireg (cfg);
7310                         ins->sreg1 = args [0]->dreg;
7311                         ins->sreg2 = args [1]->dreg;
7312                         MONO_ADD_INS (cfg->cbb, ins);
7313                 }
7314
7315 #if 0
7316                 /* OP_FREM is not IEEE compatible */
7317                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7318                         MONO_INST_NEW (cfg, ins, OP_FREM);
7319                         ins->inst_i0 = args [0];
7320                         ins->inst_i1 = args [1];
7321                 }
7322 #endif
7323         }
7324
7325         /*
7326          * Can't implement CompareExchange methods this way since they have
7327          * three arguments.
7328          */
7329
7330         return ins;
7331 }
7332
7333 gboolean
7334 mono_arch_print_tree (MonoInst *tree, int arity)
7335 {
7336         return 0;
7337 }
7338
7339 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7340 {
7341         MonoInst* ins;
7342
7343         if (appdomain_tls_offset == -1)
7344                 return NULL;
7345
7346         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7347         ins->inst_offset = appdomain_tls_offset;
7348         return ins;
7349 }
7350
7351 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7352
7353 gpointer
7354 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7355 {
7356         switch (reg) {
7357         case AMD64_RCX: return (gpointer)ctx->rcx;
7358         case AMD64_RDX: return (gpointer)ctx->rdx;
7359         case AMD64_RBX: return (gpointer)ctx->rbx;
7360         case AMD64_RBP: return (gpointer)ctx->rbp;
7361         case AMD64_RSP: return (gpointer)ctx->rsp;
7362         default:
7363                 if (reg < 8)
7364                         return _CTX_REG (ctx, rax, reg);
7365                 else if (reg >= 12)
7366                         return _CTX_REG (ctx, r12, reg - 12);
7367                 else
7368                         g_assert_not_reached ();
7369         }
7370 }
7371
7372 /*
7373  * mono_arch_set_breakpoint:
7374  *
7375  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7376  * The location should contain code emitted by OP_SEQ_POINT.
7377  */
7378 void
7379 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7380 {
7381         guint8 *code = ip;
7382         guint8 *orig_code = code;
7383
7384         /*
7385          * In production, we will use int3 (has to fix the size in the md
7386          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7387          * instead.
7388          */
7389         g_assert (code [0] == 0x90);
7390
7391         g_assert (((guint64)bp_trigger_page >> 32) == 0);
7392
7393         amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7394         g_assert (code - orig_code == BREAKPOINT_SIZE);
7395 }
7396
7397 /*
7398  * mono_arch_clear_breakpoint:
7399  *
7400  *   Clear the breakpoint at IP.
7401  */
7402 void
7403 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7404 {
7405         guint8 *code = ip;
7406         int i;
7407
7408         for (i = 0; i < BREAKPOINT_SIZE; ++i)
7409                 x86_nop (code);
7410 }
7411
7412 /*
7413  * mono_arch_start_single_stepping:
7414  *
7415  *   Start single stepping.
7416  */
7417 void
7418 mono_arch_start_single_stepping (void)
7419 {
7420         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7421 }
7422
7423 /*
7424  * mono_arch_stop_single_stepping:
7425  *
7426  *   Stop single stepping.
7427  */
7428 void
7429 mono_arch_stop_single_stepping (void)
7430 {
7431         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7432 }
7433
7434 /*
7435  * mono_arch_is_single_step_event:
7436  *
7437  *   Return whenever the machine state in SIGCTX corresponds to a single
7438  * step event.
7439  */
7440 gboolean
7441 mono_arch_is_single_step_event (siginfo_t *info, void *sigctx)
7442 {
7443         /* Sometimes the address is off by 4 */
7444         if (info->si_addr >= ss_trigger_page && (guint8*)info->si_addr <= (guint8*)ss_trigger_page + 128)
7445                 return TRUE;
7446         else
7447                 return FALSE;
7448 }
7449
7450 gboolean
7451 mono_arch_is_breakpoint_event (siginfo_t *info, void *sigctx)
7452 {
7453         /* Sometimes the address is off by 4 */
7454         if (info->si_addr >= bp_trigger_page && (guint8*)info->si_addr <= (guint8*)bp_trigger_page + 128)
7455                 return TRUE;
7456         else
7457                 return FALSE;
7458 }
7459
7460 /*
7461  * mono_arch_get_ip_for_breakpoint:
7462  *
7463  *   Convert the ip in CTX to the address where a breakpoint was placed.
7464  */
7465 guint8*
7466 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7467 {
7468         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7469
7470         /* size of xor r11, r11 */
7471         ip -= 0;
7472
7473         return ip;
7474 }
7475
7476 /*
7477  * mono_arch_get_ip_for_single_step:
7478  *
7479  *   Convert the ip in CTX to the address stored in seq_points.
7480  */
7481 guint8*
7482 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7483 {
7484         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7485
7486         /* Size of amd64_mov_reg_mem (r11) */
7487         ip += 8;
7488
7489         return ip;
7490 }
7491
7492 /*
7493  * mono_arch_skip_breakpoint:
7494  *
7495  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7496  * we resume, the instruction is not executed again.
7497  */
7498 void
7499 mono_arch_skip_breakpoint (MonoContext *ctx)
7500 {
7501         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + BREAKPOINT_SIZE);
7502 }
7503
7504 /*
7505  * mono_arch_skip_single_step:
7506  *
7507  *   Modify CTX so the ip is placed after the single step trigger instruction,
7508  * we resume, the instruction is not executed again.
7509  */
7510 void
7511 mono_arch_skip_single_step (MonoContext *ctx)
7512 {
7513         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + 8);
7514 }
7515
7516 /*
7517  * mono_arch_create_seq_point_info:
7518  *
7519  *   Return a pointer to a data structure which is used by the sequence
7520  * point implementation in AOTed code.
7521  */
7522 gpointer
7523 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7524 {
7525         NOT_IMPLEMENTED;
7526         return NULL;
7527 }