2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/utils/mono-math.h>
29 #include "mini-amd64.h"
31 #include "cpu-amd64.h"
33 static gint lmf_tls_offset = -1;
34 static gint lmf_addr_tls_offset = -1;
35 static gint appdomain_tls_offset = -1;
36 static gint thread_tls_offset = -1;
39 static gboolean optimize_for_xen = TRUE;
41 #define optimize_for_xen 0
44 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
46 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
48 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
51 /* Under windows, the default pinvoke calling convention is stdcall */
52 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
54 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
57 /* This mutex protects architecture specific caches */
58 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
59 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
60 static CRITICAL_SECTION mini_arch_mutex;
63 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
66 /* On Win64 always reserve first 32 bytes for first four arguments */
67 #define ARGS_OFFSET 48
69 #define ARGS_OFFSET 16
71 #define GP_SCRATCH_REG AMD64_R11
74 * AMD64 register usage:
75 * - callee saved registers are used for global register allocation
76 * - %r11 is used for materializing 64 bit constants in opcodes
77 * - the rest is used for local allocation
81 * Floating point comparison results:
91 mono_arch_regname (int reg)
94 case AMD64_RAX: return "%rax";
95 case AMD64_RBX: return "%rbx";
96 case AMD64_RCX: return "%rcx";
97 case AMD64_RDX: return "%rdx";
98 case AMD64_RSP: return "%rsp";
99 case AMD64_RBP: return "%rbp";
100 case AMD64_RDI: return "%rdi";
101 case AMD64_RSI: return "%rsi";
102 case AMD64_R8: return "%r8";
103 case AMD64_R9: return "%r9";
104 case AMD64_R10: return "%r10";
105 case AMD64_R11: return "%r11";
106 case AMD64_R12: return "%r12";
107 case AMD64_R13: return "%r13";
108 case AMD64_R14: return "%r14";
109 case AMD64_R15: return "%r15";
114 static const char * xmmregs [] = {
115 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
116 "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
120 mono_arch_fregname (int reg)
122 if (reg < AMD64_XMM_NREG)
123 return xmmregs [reg];
128 G_GNUC_UNUSED static void
133 G_GNUC_UNUSED static gboolean
136 static int count = 0;
139 if (!getenv ("COUNT"))
142 if (count == atoi (getenv ("COUNT"))) {
146 if (count > atoi (getenv ("COUNT"))) {
157 return debug_count ();
163 static inline gboolean
164 amd64_is_near_call (guint8 *code)
167 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
170 return code [0] == 0xe8;
174 amd64_patch (unsigned char* code, gpointer target)
179 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
184 if ((code [0] & 0xf8) == 0xb8) {
185 /* amd64_set_reg_template */
186 *(guint64*)(code + 1) = (guint64)target;
188 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
189 /* mov 0(%rip), %dreg */
190 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
192 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
193 /* call *<OFFSET>(%rip) */
194 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
196 else if ((code [0] == 0xe8)) {
198 gint64 disp = (guint8*)target - (guint8*)code;
199 g_assert (amd64_is_imm32 (disp));
200 x86_patch (code, (unsigned char*)target);
203 x86_patch (code, (unsigned char*)target);
207 mono_amd64_patch (unsigned char* code, gpointer target)
209 amd64_patch (code, target);
218 ArgValuetypeAddrInIReg,
219 ArgNone /* only in pair_storage */
227 /* Only if storage == ArgValuetypeInReg */
228 ArgStorage pair_storage [2];
237 gboolean need_stack_align;
243 #define DEBUG(a) if (cfg->verbose_level > 1) a
245 #define NEW_ICONST(cfg,dest,val) do { \
246 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
247 (dest)->opcode = OP_ICONST; \
248 (dest)->inst_c0 = (val); \
249 (dest)->type = STACK_I4; \
252 #ifdef PLATFORM_WIN32
255 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
257 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
261 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
263 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
267 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
269 ainfo->offset = *stack_size;
271 if (*gr >= PARAM_REGS) {
272 ainfo->storage = ArgOnStack;
273 (*stack_size) += sizeof (gpointer);
276 ainfo->storage = ArgInIReg;
277 ainfo->reg = param_regs [*gr];
282 #ifdef PLATFORM_WIN32
283 #define FLOAT_PARAM_REGS 4
285 #define FLOAT_PARAM_REGS 8
289 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
291 ainfo->offset = *stack_size;
293 if (*gr >= FLOAT_PARAM_REGS) {
294 ainfo->storage = ArgOnStack;
295 (*stack_size) += sizeof (gpointer);
298 /* A double register */
300 ainfo->storage = ArgInDoubleSSEReg;
302 ainfo->storage = ArgInFloatSSEReg;
308 typedef enum ArgumentClass {
316 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
318 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
321 ptype = mono_type_get_underlying_type (type);
322 switch (ptype->type) {
323 case MONO_TYPE_BOOLEAN:
333 case MONO_TYPE_STRING:
334 case MONO_TYPE_OBJECT:
335 case MONO_TYPE_CLASS:
336 case MONO_TYPE_SZARRAY:
338 case MONO_TYPE_FNPTR:
339 case MONO_TYPE_ARRAY:
342 class2 = ARG_CLASS_INTEGER;
346 #ifdef PLATFORM_WIN32
347 class2 = ARG_CLASS_INTEGER;
349 class2 = ARG_CLASS_SSE;
353 case MONO_TYPE_TYPEDBYREF:
354 g_assert_not_reached ();
356 case MONO_TYPE_GENERICINST:
357 if (!mono_type_generic_inst_is_valuetype (ptype)) {
358 class2 = ARG_CLASS_INTEGER;
362 case MONO_TYPE_VALUETYPE: {
363 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
366 for (i = 0; i < info->num_fields; ++i) {
368 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
373 g_assert_not_reached ();
377 if (class1 == class2)
379 else if (class1 == ARG_CLASS_NO_CLASS)
381 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
382 class1 = ARG_CLASS_MEMORY;
383 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
384 class1 = ARG_CLASS_INTEGER;
386 class1 = ARG_CLASS_SSE;
392 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
394 guint32 *gr, guint32 *fr, guint32 *stack_size)
396 guint32 size, quad, nquads, i;
397 ArgumentClass args [2];
398 MonoMarshalType *info;
401 klass = mono_class_from_mono_type (type);
403 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
405 size = mini_type_stack_size (gsctx, &klass->byval_arg, NULL);
406 #ifndef PLATFORM_WIN32
407 if (!sig->pinvoke || (size == 0) || (size > 16)) {
411 /* Allways pass in memory */
412 ainfo->offset = *stack_size;
413 *stack_size += ALIGN_TO (size, 8);
414 ainfo->storage = ArgOnStack;
419 /* FIXME: Handle structs smaller than 8 bytes */
420 //if ((size % 8) != 0)
429 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
430 * The X87 and SSEUP stuff is left out since there are no such types in
433 info = mono_marshal_load_type_info (klass);
436 #ifndef PLATFORM_WIN32
437 if (info->native_size > 16) {
438 ainfo->offset = *stack_size;
439 *stack_size += ALIGN_TO (info->native_size, 8);
440 ainfo->storage = ArgOnStack;
445 switch (info->native_size) {
446 case 1: case 2: case 4: case 8:
450 ainfo->storage = ArgOnStack;
451 ainfo->offset = *stack_size;
452 *stack_size += ALIGN_TO (info->native_size, 8);
455 ainfo->storage = ArgValuetypeAddrInIReg;
457 if (*gr < PARAM_REGS) {
458 ainfo->pair_storage [0] = ArgInIReg;
459 ainfo->pair_regs [0] = param_regs [*gr];
463 ainfo->pair_storage [0] = ArgOnStack;
464 ainfo->offset = *stack_size;
473 args [0] = ARG_CLASS_NO_CLASS;
474 args [1] = ARG_CLASS_NO_CLASS;
475 for (quad = 0; quad < nquads; ++quad) {
478 ArgumentClass class1;
480 class1 = ARG_CLASS_NO_CLASS;
481 for (i = 0; i < info->num_fields; ++i) {
482 size = mono_marshal_type_size (info->fields [i].field->type,
483 info->fields [i].mspec,
484 &align, TRUE, klass->unicode);
485 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
486 /* Unaligned field */
490 /* Skip fields in other quad */
491 if ((quad == 0) && (info->fields [i].offset >= 8))
493 if ((quad == 1) && (info->fields [i].offset < 8))
496 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
498 g_assert (class1 != ARG_CLASS_NO_CLASS);
499 args [quad] = class1;
502 /* Post merger cleanup */
503 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
504 args [0] = args [1] = ARG_CLASS_MEMORY;
506 /* Allocate registers */
511 ainfo->storage = ArgValuetypeInReg;
512 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
513 for (quad = 0; quad < nquads; ++quad) {
514 switch (args [quad]) {
515 case ARG_CLASS_INTEGER:
516 if (*gr >= PARAM_REGS)
517 args [quad] = ARG_CLASS_MEMORY;
519 ainfo->pair_storage [quad] = ArgInIReg;
521 ainfo->pair_regs [quad] = return_regs [*gr];
523 ainfo->pair_regs [quad] = param_regs [*gr];
528 if (*fr >= FLOAT_PARAM_REGS)
529 args [quad] = ARG_CLASS_MEMORY;
531 ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
532 ainfo->pair_regs [quad] = *fr;
536 case ARG_CLASS_MEMORY:
539 g_assert_not_reached ();
543 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
544 /* Revert possible register assignments */
548 ainfo->offset = *stack_size;
549 *stack_size += ALIGN_TO (info->native_size, 8);
550 ainfo->storage = ArgOnStack;
558 * Obtain information about a call according to the calling convention.
559 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
560 * Draft Version 0.23" document for more information.
563 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
567 int n = sig->hasthis + sig->param_count;
568 guint32 stack_size = 0;
572 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
574 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
581 ret_type = mono_type_get_underlying_type (sig->ret);
582 ret_type = mini_get_basic_type_from_generic (gsctx, ret_type);
583 switch (ret_type->type) {
584 case MONO_TYPE_BOOLEAN:
595 case MONO_TYPE_FNPTR:
596 case MONO_TYPE_CLASS:
597 case MONO_TYPE_OBJECT:
598 case MONO_TYPE_SZARRAY:
599 case MONO_TYPE_ARRAY:
600 case MONO_TYPE_STRING:
601 cinfo->ret.storage = ArgInIReg;
602 cinfo->ret.reg = AMD64_RAX;
606 cinfo->ret.storage = ArgInIReg;
607 cinfo->ret.reg = AMD64_RAX;
610 cinfo->ret.storage = ArgInFloatSSEReg;
611 cinfo->ret.reg = AMD64_XMM0;
614 cinfo->ret.storage = ArgInDoubleSSEReg;
615 cinfo->ret.reg = AMD64_XMM0;
617 case MONO_TYPE_GENERICINST:
618 if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
619 cinfo->ret.storage = ArgInIReg;
620 cinfo->ret.reg = AMD64_RAX;
624 case MONO_TYPE_VALUETYPE: {
625 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
627 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
628 if (cinfo->ret.storage == ArgOnStack)
629 /* The caller passes the address where the value is stored */
630 add_general (&gr, &stack_size, &cinfo->ret);
633 case MONO_TYPE_TYPEDBYREF:
634 /* Same as a valuetype with size 24 */
635 add_general (&gr, &stack_size, &cinfo->ret);
641 g_error ("Can't handle as return value 0x%x", sig->ret->type);
647 add_general (&gr, &stack_size, cinfo->args + 0);
649 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
651 fr = FLOAT_PARAM_REGS;
653 /* Emit the signature cookie just before the implicit arguments */
654 add_general (&gr, &stack_size, &cinfo->sig_cookie);
657 for (i = 0; i < sig->param_count; ++i) {
658 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
661 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
662 /* We allways pass the sig cookie on the stack for simplicity */
664 * Prevent implicit arguments + the sig cookie from being passed
668 fr = FLOAT_PARAM_REGS;
670 /* Emit the signature cookie just before the implicit arguments */
671 add_general (&gr, &stack_size, &cinfo->sig_cookie);
674 if (sig->params [i]->byref) {
675 add_general (&gr, &stack_size, ainfo);
678 ptype = mono_type_get_underlying_type (sig->params [i]);
679 ptype = mini_get_basic_type_from_generic (gsctx, ptype);
680 switch (ptype->type) {
681 case MONO_TYPE_BOOLEAN:
684 add_general (&gr, &stack_size, ainfo);
689 add_general (&gr, &stack_size, ainfo);
693 add_general (&gr, &stack_size, ainfo);
698 case MONO_TYPE_FNPTR:
699 case MONO_TYPE_CLASS:
700 case MONO_TYPE_OBJECT:
701 case MONO_TYPE_STRING:
702 case MONO_TYPE_SZARRAY:
703 case MONO_TYPE_ARRAY:
704 add_general (&gr, &stack_size, ainfo);
706 case MONO_TYPE_GENERICINST:
707 if (!mono_type_generic_inst_is_valuetype (ptype)) {
708 add_general (&gr, &stack_size, ainfo);
712 case MONO_TYPE_VALUETYPE:
713 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
715 case MONO_TYPE_TYPEDBYREF:
716 stack_size += sizeof (MonoTypedRef);
717 ainfo->storage = ArgOnStack;
721 add_general (&gr, &stack_size, ainfo);
724 add_float (&fr, &stack_size, ainfo, FALSE);
727 add_float (&fr, &stack_size, ainfo, TRUE);
730 g_assert_not_reached ();
734 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
736 fr = FLOAT_PARAM_REGS;
738 /* Emit the signature cookie just before the implicit arguments */
739 add_general (&gr, &stack_size, &cinfo->sig_cookie);
742 #ifdef PLATFORM_WIN32
743 // There always is 32 bytes reserved on the stack when calling on Winx64
747 if (stack_size & 0x8) {
748 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
749 cinfo->need_stack_align = TRUE;
753 cinfo->stack_usage = stack_size;
754 cinfo->reg_usage = gr;
755 cinfo->freg_usage = fr;
760 * mono_arch_get_argument_info:
761 * @csig: a method signature
762 * @param_count: the number of parameters to consider
763 * @arg_info: an array to store the result infos
765 * Gathers information on parameters such as size, alignment and
766 * padding. arg_info should be large enought to hold param_count + 1 entries.
768 * Returns the size of the argument area on the stack.
771 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
774 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
775 guint32 args_size = cinfo->stack_usage;
777 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
779 arg_info [0].offset = 0;
782 for (k = 0; k < param_count; k++) {
783 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
785 arg_info [k + 1].size = 0;
794 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
797 __asm__ __volatile__ ("cpuid"
798 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
812 * Initialize the cpu to execute managed code.
815 mono_arch_cpu_init (void)
820 /* spec compliance requires running with double precision */
821 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
822 fpcw &= ~X86_FPCW_PRECC_MASK;
823 fpcw |= X86_FPCW_PREC_DOUBLE;
824 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
825 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
827 /* TODO: This is crashing on Win64 right now.
828 * _control87 (_PC_53, MCW_PC);
834 * Initialize architecture specific code.
837 mono_arch_init (void)
839 InitializeCriticalSection (&mini_arch_mutex);
843 * Cleanup architecture specific code.
846 mono_arch_cleanup (void)
848 DeleteCriticalSection (&mini_arch_mutex);
852 * This function returns the optimizations supported on this cpu.
855 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
857 int eax, ebx, ecx, edx;
863 /* Feature Flags function, flags returned in EDX. */
864 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
865 if (edx & (1 << 15)) {
866 opts |= MONO_OPT_CMOV;
868 opts |= MONO_OPT_FCMOV;
870 *exclude_mask |= MONO_OPT_FCMOV;
872 *exclude_mask |= MONO_OPT_CMOV;
878 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
883 for (i = 0; i < cfg->num_varinfo; i++) {
884 MonoInst *ins = cfg->varinfo [i];
885 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
888 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
891 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
892 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
895 if (mono_is_regsize_var (ins->inst_vtype)) {
896 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
897 g_assert (i == vmv->idx);
898 vars = g_list_prepend (vars, vmv);
902 vars = mono_varlist_sort (cfg, vars, 0);
908 * mono_arch_compute_omit_fp:
910 * Determine whenever the frame pointer can be eliminated.
913 mono_arch_compute_omit_fp (MonoCompile *cfg)
915 MonoMethodSignature *sig;
916 MonoMethodHeader *header;
920 if (cfg->arch.omit_fp_computed)
923 header = mono_method_get_header (cfg->method);
925 sig = mono_method_signature (cfg->method);
927 if (!cfg->arch.cinfo)
928 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
929 cinfo = cfg->arch.cinfo;
932 * FIXME: Remove some of the restrictions.
934 cfg->arch.omit_fp = TRUE;
935 cfg->arch.omit_fp_computed = TRUE;
937 if (cfg->disable_omit_fp)
938 cfg->arch.omit_fp = FALSE;
940 if (!debug_omit_fp ())
941 cfg->arch.omit_fp = FALSE;
943 if (cfg->method->save_lmf)
944 cfg->arch.omit_fp = FALSE;
946 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
947 cfg->arch.omit_fp = FALSE;
948 if (header->num_clauses)
949 cfg->arch.omit_fp = FALSE;
951 cfg->arch.omit_fp = FALSE;
952 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
953 cfg->arch.omit_fp = FALSE;
954 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
955 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
956 cfg->arch.omit_fp = FALSE;
957 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
958 ArgInfo *ainfo = &cinfo->args [i];
960 if (ainfo->storage == ArgOnStack) {
962 * The stack offset can only be determined when the frame
965 cfg->arch.omit_fp = FALSE;
970 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
971 MonoInst *ins = cfg->varinfo [i];
974 locals_size += mono_type_size (ins->inst_vtype, &ialign);
977 if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
978 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
979 cfg->arch.omit_fp = FALSE;
984 mono_arch_get_global_int_regs (MonoCompile *cfg)
988 mono_arch_compute_omit_fp (cfg);
990 if (cfg->arch.omit_fp)
991 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
993 /* We use the callee saved registers for global allocation */
994 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
995 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
996 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
997 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
998 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1004 * mono_arch_regalloc_cost:
1006 * Return the cost, in number of memory references, of the action of
1007 * allocating the variable VMV into a register during global register
1011 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1013 MonoInst *ins = cfg->varinfo [vmv->idx];
1015 if (cfg->method->save_lmf)
1016 /* The register is already saved */
1017 /* substract 1 for the invisible store in the prolog */
1018 return (ins->opcode == OP_ARG) ? 0 : 1;
1021 return (ins->opcode == OP_ARG) ? 1 : 2;
1025 mono_arch_allocate_vars (MonoCompile *cfg)
1027 MonoMethodSignature *sig;
1028 MonoMethodHeader *header;
1031 guint32 locals_stack_size, locals_stack_align;
1035 header = mono_method_get_header (cfg->method);
1037 sig = mono_method_signature (cfg->method);
1039 cinfo = cfg->arch.cinfo;
1041 mono_arch_compute_omit_fp (cfg);
1044 * We use the ABI calling conventions for managed code as well.
1045 * Exception: valuetypes are never passed or returned in registers.
1048 if (cfg->arch.omit_fp) {
1049 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1050 cfg->frame_reg = AMD64_RSP;
1053 /* Locals are allocated backwards from %fp */
1054 cfg->frame_reg = AMD64_RBP;
1058 if (cfg->method->save_lmf) {
1059 /* Reserve stack space for saving LMF */
1060 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1061 g_assert (offset == 0);
1062 if (cfg->arch.omit_fp) {
1063 cfg->arch.lmf_offset = offset;
1064 offset += sizeof (MonoLMF);
1067 offset += sizeof (MonoLMF);
1068 cfg->arch.lmf_offset = -offset;
1071 if (cfg->arch.omit_fp)
1072 cfg->arch.reg_save_area_offset = offset;
1073 /* Reserve space for caller saved registers */
1074 for (i = 0; i < AMD64_NREG; ++i)
1075 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1076 offset += sizeof (gpointer);
1080 if (sig->ret->type != MONO_TYPE_VOID) {
1081 switch (cinfo->ret.storage) {
1083 case ArgInFloatSSEReg:
1084 case ArgInDoubleSSEReg:
1085 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1086 /* The register is volatile */
1087 cfg->vret_addr->opcode = OP_REGOFFSET;
1088 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1089 if (cfg->arch.omit_fp) {
1090 cfg->vret_addr->inst_offset = offset;
1094 cfg->vret_addr->inst_offset = -offset;
1096 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1097 printf ("vret_addr =");
1098 mono_print_ins (cfg->vret_addr);
1102 cfg->ret->opcode = OP_REGVAR;
1103 cfg->ret->inst_c0 = cinfo->ret.reg;
1106 case ArgValuetypeInReg:
1107 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1108 cfg->ret->opcode = OP_REGOFFSET;
1109 cfg->ret->inst_basereg = cfg->frame_reg;
1110 if (cfg->arch.omit_fp) {
1111 cfg->ret->inst_offset = offset;
1115 cfg->ret->inst_offset = - offset;
1119 g_assert_not_reached ();
1121 cfg->ret->dreg = cfg->ret->inst_c0;
1124 /* Allocate locals */
1125 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1126 if (locals_stack_align) {
1127 offset += (locals_stack_align - 1);
1128 offset &= ~(locals_stack_align - 1);
1130 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1131 if (offsets [i] != -1) {
1132 MonoInst *inst = cfg->varinfo [i];
1133 inst->opcode = OP_REGOFFSET;
1134 inst->inst_basereg = cfg->frame_reg;
1135 if (cfg->arch.omit_fp)
1136 inst->inst_offset = (offset + offsets [i]);
1138 inst->inst_offset = - (offset + offsets [i]);
1139 //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1142 offset += locals_stack_size;
1144 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1145 g_assert (!cfg->arch.omit_fp);
1146 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1147 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1150 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1151 inst = cfg->args [i];
1152 if (inst->opcode != OP_REGVAR) {
1153 ArgInfo *ainfo = &cinfo->args [i];
1154 gboolean inreg = TRUE;
1157 if (sig->hasthis && (i == 0))
1158 arg_type = &mono_defaults.object_class->byval_arg;
1160 arg_type = sig->params [i - sig->hasthis];
1162 /* FIXME: Allocate volatile arguments to registers */
1163 if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1167 * Under AMD64, all registers used to pass arguments to functions
1168 * are volatile across calls.
1169 * FIXME: Optimize this.
1171 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1174 inst->opcode = OP_REGOFFSET;
1176 switch (ainfo->storage) {
1178 case ArgInFloatSSEReg:
1179 case ArgInDoubleSSEReg:
1180 inst->opcode = OP_REGVAR;
1181 inst->dreg = ainfo->reg;
1184 g_assert (!cfg->arch.omit_fp);
1185 inst->opcode = OP_REGOFFSET;
1186 inst->inst_basereg = cfg->frame_reg;
1187 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1189 case ArgValuetypeInReg:
1191 case ArgValuetypeAddrInIReg:
1192 break; /*FIXME: Not sure what to do for this case yet on Winx64*/
1197 if (!inreg && (ainfo->storage != ArgOnStack)) {
1198 inst->opcode = OP_REGOFFSET;
1199 inst->inst_basereg = cfg->frame_reg;
1200 /* These arguments are saved to the stack in the prolog */
1201 offset = ALIGN_TO (offset, sizeof (gpointer));
1202 if (cfg->arch.omit_fp) {
1203 inst->inst_offset = offset;
1204 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1206 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1207 inst->inst_offset = - offset;
1213 cfg->stack_offset = offset;
1217 mono_arch_create_vars (MonoCompile *cfg)
1219 MonoMethodSignature *sig;
1222 sig = mono_method_signature (cfg->method);
1224 if (!cfg->arch.cinfo)
1225 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1226 cinfo = cfg->arch.cinfo;
1228 if (cinfo->ret.storage == ArgValuetypeInReg)
1229 cfg->ret_var_is_local = TRUE;
1231 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1232 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1233 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1234 printf ("vret_addr = ");
1235 mono_print_ins (cfg->vret_addr);
1241 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1245 arg->opcode = OP_OUTARG_REG;
1246 arg->inst_left = tree;
1247 arg->inst_call = call;
1248 arg->backend.reg3 = reg;
1250 case ArgInFloatSSEReg:
1251 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1252 arg->inst_left = tree;
1253 arg->inst_call = call;
1254 arg->backend.reg3 = reg;
1256 case ArgInDoubleSSEReg:
1257 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1258 arg->inst_left = tree;
1259 arg->inst_call = call;
1260 arg->backend.reg3 = reg;
1263 g_assert_not_reached ();
1267 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1268 * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1272 arg_storage_to_ldind (ArgStorage storage)
1277 case ArgInDoubleSSEReg:
1278 return CEE_LDIND_R8;
1279 case ArgInFloatSSEReg:
1280 return CEE_LDIND_R4;
1282 g_assert_not_reached ();
1289 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1292 MonoMethodSignature *tmp_sig;
1295 /* FIXME: Add support for signature tokens to AOT */
1296 cfg->disable_aot = TRUE;
1298 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1301 * mono_ArgIterator_Setup assumes the signature cookie is
1302 * passed first and all the arguments which were before it are
1303 * passed on the stack after the signature. So compensate by
1304 * passing a different signature.
1306 tmp_sig = mono_metadata_signature_dup (call->signature);
1307 tmp_sig->param_count -= call->signature->sentinelpos;
1308 tmp_sig->sentinelpos = 0;
1309 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1311 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1312 sig_arg->inst_p0 = tmp_sig;
1314 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1315 arg->inst_left = sig_arg;
1316 arg->type = STACK_PTR;
1317 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1321 * take the arguments and generate the arch-specific
1322 * instructions to properly call the function in call.
1323 * This includes pushing, moving arguments to the right register
1325 * Issue: who does the spilling if needed, and when?
1328 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1330 MonoMethodSignature *sig;
1331 int i, n, stack_size;
1337 sig = call->signature;
1338 n = sig->param_count + sig->hasthis;
1340 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1342 for (i = 0; i < n; ++i) {
1343 ainfo = cinfo->args + i;
1345 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1346 /* Emit the signature cookie just before the implicit arguments */
1347 emit_sig_cookie (cfg, call, cinfo);
1350 if (is_virtual && i == 0) {
1351 /* the argument will be attached to the call instruction */
1352 in = call->args [i];
1354 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1355 in = call->args [i];
1356 arg->cil_code = in->cil_code;
1357 arg->inst_left = in;
1358 arg->type = in->type;
1359 if (!cinfo->stack_usage)
1360 /* Keep the assignments to the arg registers in order if possible */
1361 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1363 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1365 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1369 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1370 size = sizeof (MonoTypedRef);
1371 align = sizeof (gpointer);
1375 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1378 * Other backends use mini_type_stack_size (), but that
1379 * aligns the size to 8, which is larger than the size of
1380 * the source, leading to reads of invalid memory if the
1381 * source is at the end of address space.
1383 size = mono_class_value_size (in->klass, &align);
1385 if (ainfo->storage == ArgValuetypeInReg) {
1386 if (ainfo->pair_storage [1] == ArgNone) {
1391 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1392 load->inst_left = in;
1394 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1397 /* Trees can't be shared so make a copy */
1398 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1399 MonoInst *load, *load2, *offset_ins;
1402 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1403 load->ssa_op = MONO_SSA_LOAD;
1404 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1406 NEW_ICONST (cfg, offset_ins, 0);
1407 MONO_INST_NEW (cfg, load2, CEE_ADD);
1408 load2->inst_left = load;
1409 load2->inst_right = offset_ins;
1411 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1412 load->inst_left = load2;
1414 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1417 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1418 load->ssa_op = MONO_SSA_LOAD;
1419 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1421 NEW_ICONST (cfg, offset_ins, 8);
1422 MONO_INST_NEW (cfg, load2, CEE_ADD);
1423 load2->inst_left = load;
1424 load2->inst_right = offset_ins;
1426 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1427 load->inst_left = load2;
1429 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1430 arg->cil_code = in->cil_code;
1431 arg->type = in->type;
1432 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1434 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1436 /* Prepend a copy inst */
1437 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1438 arg->cil_code = in->cil_code;
1439 arg->ssa_op = MONO_SSA_STORE;
1440 arg->inst_left = vtaddr;
1441 arg->inst_right = in;
1442 arg->type = in->type;
1444 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1447 else if (ainfo->storage == ArgValuetypeAddrInIReg){
1449 /* Add a temp variable to the method*/
1451 MonoInst *vtaddr = mono_compile_create_var (cfg, &in->klass->byval_arg, OP_LOCAL);
1453 MONO_INST_NEW (cfg, load, OP_LDADDR);
1454 load->ssa_op = MONO_SSA_LOAD;
1455 load->inst_left = vtaddr;
1457 if (ainfo->pair_storage [0] == ArgInIReg) {
1458 /* Inserted after the copy. Load the address of the temp to the argument regster.*/
1459 arg->opcode = OP_OUTARG_REG;
1460 arg->inst_left = load;
1461 arg->inst_call = call;
1462 arg->backend.reg3 = ainfo->pair_regs [0];
1465 /* Inserted after the copy. Load the address of the temp on the stack.*/
1466 arg->opcode = OP_OUTARG_VT;
1467 arg->inst_left = load;
1468 arg->type = STACK_PTR;
1469 arg->klass = mono_defaults.int_class;
1470 arg->backend.is_pinvoke = sig->pinvoke;
1471 arg->inst_imm = size;
1474 /*Copy the argument to the temp variable.*/
1475 MONO_INST_NEW (cfg, load, OP_MEMCPY);
1476 load->backend.memcpy_args = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoMemcpyArgs));
1477 load->backend.memcpy_args->size = mono_class_value_size (in->klass, &align);
1478 load->backend.memcpy_args->align = align;
1479 load->inst_left = (cfg)->varinfo [vtaddr->inst_c0];
1480 load->inst_right = in->inst_i0;
1481 MONO_INST_LIST_ADD (&load->node, &call->out_args);
1484 arg->opcode = OP_OUTARG_VT;
1485 arg->klass = in->klass;
1486 arg->backend.is_pinvoke = sig->pinvoke;
1487 arg->inst_imm = size;
1491 switch (ainfo->storage) {
1493 add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1495 case ArgInFloatSSEReg:
1496 case ArgInDoubleSSEReg:
1497 add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1500 arg->opcode = OP_OUTARG;
1501 if (!sig->params [i - sig->hasthis]->byref) {
1502 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1503 arg->opcode = OP_OUTARG_R4;
1505 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1506 arg->opcode = OP_OUTARG_R8;
1510 g_assert_not_reached ();
1516 /* Handle the case where there are no implicit arguments */
1517 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1518 emit_sig_cookie (cfg, call, cinfo);
1521 if (cinfo->need_stack_align) {
1522 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1524 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1527 #ifdef PLATFORM_WIN32
1528 /* Always reserve 32 bytes of stack space on Win64 */
1529 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1531 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1534 if (cfg->method->save_lmf) {
1535 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1536 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1539 call->stack_usage = cinfo->stack_usage;
1540 cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1541 cfg->flags |= MONO_CFG_HAS_CALLS;
1546 #define EMIT_COND_BRANCH(ins,cond,sign) \
1547 if (ins->flags & MONO_INST_BRLABEL) { \
1548 if (ins->inst_i0->inst_c0) { \
1549 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1551 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1552 if ((cfg->opt & MONO_OPT_BRANCH) && \
1553 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1554 x86_branch8 (code, cond, 0, sign); \
1556 x86_branch32 (code, cond, 0, sign); \
1559 if (ins->inst_true_bb->native_offset) { \
1560 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1562 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1563 if ((cfg->opt & MONO_OPT_BRANCH) && \
1564 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1565 x86_branch8 (code, cond, 0, sign); \
1567 x86_branch32 (code, cond, 0, sign); \
1571 /* emit an exception if condition is fail */
1572 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
1574 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1575 if (tins == NULL) { \
1576 mono_add_patch_info (cfg, code - cfg->native_code, \
1577 MONO_PATCH_INFO_EXC, exc_name); \
1578 x86_branch32 (code, cond, 0, signed); \
1580 EMIT_COND_BRANCH (tins, cond, signed); \
1584 #define EMIT_FPCOMPARE(code) do { \
1585 amd64_fcompp (code); \
1586 amd64_fnstsw (code); \
1589 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1590 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1591 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1592 amd64_ ##op (code); \
1593 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1594 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1598 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1601 * FIXME: Add support for thunks
1604 gboolean near_call = FALSE;
1607 * Indirect calls are expensive so try to make a near call if possible.
1608 * The caller memory is allocated by the code manager so it is
1609 * guaranteed to be at a 32 bit offset.
1612 if (patch_type != MONO_PATCH_INFO_ABS) {
1613 /* The target is in memory allocated using the code manager */
1616 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1617 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1618 /* The callee might be an AOT method */
1620 if (((MonoMethod*)data)->dynamic)
1621 /* The target is in malloc-ed memory */
1625 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1627 * The call might go directly to a native function without
1630 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1632 gconstpointer target = mono_icall_get_wrapper (mi);
1633 if ((((guint64)target) >> 32) != 0)
1639 if (mono_find_class_init_trampoline_by_addr (data))
1642 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1644 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1645 strstr (cfg->method->name, info->name)) {
1646 /* A call to the wrapped function */
1647 if ((((guint64)data) >> 32) == 0)
1650 else if (info->func == info->wrapper) {
1652 if ((((guint64)info->func) >> 32) == 0)
1656 /* See the comment in mono_codegen () */
1657 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1661 else if ((((guint64)data) >> 32) == 0)
1666 if (cfg->method->dynamic)
1667 /* These methods are allocated using malloc */
1670 if (cfg->compile_aot)
1673 #ifdef MONO_ARCH_NOMAP32BIT
1679 * Align the call displacement to an address divisible by 4 so it does
1680 * not span cache lines. This is required for code patching to work on SMP
1683 if (((guint32)(code + 1 - cfg->native_code) % 4) != 0)
1684 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
1685 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1686 amd64_call_code (code, 0);
1689 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1690 amd64_set_reg_template (code, GP_SCRATCH_REG);
1691 amd64_call_reg (code, GP_SCRATCH_REG);
1698 static inline guint8*
1699 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
1701 #ifdef PLATFORM_WIN32
1702 if (win64_adjust_stack)
1703 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
1705 code = emit_call_body (cfg, code, patch_type, data);
1706 #ifdef PLATFORM_WIN32
1707 if (win64_adjust_stack)
1708 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
1715 store_membase_imm_to_store_membase_reg (int opcode)
1718 case OP_STORE_MEMBASE_IMM:
1719 return OP_STORE_MEMBASE_REG;
1720 case OP_STOREI4_MEMBASE_IMM:
1721 return OP_STOREI4_MEMBASE_REG;
1722 case OP_STOREI8_MEMBASE_IMM:
1723 return OP_STOREI8_MEMBASE_REG;
1729 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
1732 * mono_arch_peephole_pass_1:
1734 * Perform peephole opts which should/can be performed before local regalloc
1737 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
1741 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1742 MonoInst *last_ins = mono_inst_list_prev (&ins->node, &bb->ins_list);
1744 switch (ins->opcode) {
1748 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
1750 * X86_LEA is like ADD, but doesn't have the
1751 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
1752 * its operand to 64 bit.
1754 ins->opcode = OP_X86_LEA_MEMBASE;
1755 ins->inst_basereg = ins->sreg1;
1760 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1764 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1765 * the latter has length 2-3 instead of 6 (reverse constant
1766 * propagation). These instruction sequences are very common
1767 * in the initlocals bblock.
1769 for (ins2 = mono_inst_list_next (&ins->node, &bb->ins_list); ins2;
1770 ins2 = mono_inst_list_next (&ins2->node, &bb->ins_list)) {
1771 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1772 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1773 ins2->sreg1 = ins->dreg;
1774 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1776 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1785 case OP_COMPARE_IMM:
1786 case OP_LCOMPARE_IMM:
1787 /* OP_COMPARE_IMM (reg, 0)
1789 * OP_AMD64_TEST_NULL (reg)
1792 ins->opcode = OP_AMD64_TEST_NULL;
1794 case OP_ICOMPARE_IMM:
1796 ins->opcode = OP_X86_TEST_NULL;
1798 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1800 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1801 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1803 * OP_STORE_MEMBASE_REG reg, offset(basereg)
1804 * OP_COMPARE_IMM reg, imm
1806 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1808 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1809 ins->inst_basereg == last_ins->inst_destbasereg &&
1810 ins->inst_offset == last_ins->inst_offset) {
1811 ins->opcode = OP_ICOMPARE_IMM;
1812 ins->sreg1 = last_ins->sreg1;
1814 /* check if we can remove cmp reg,0 with test null */
1816 ins->opcode = OP_X86_TEST_NULL;
1822 mono_peephole_ins (bb, ins);
1827 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
1831 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1832 switch (ins->opcode) {
1837 /* reg = 0 -> XOR (reg, reg) */
1838 /* XOR sets cflags on x86, so we cant do it always */
1839 next = mono_inst_list_next (&ins->node, &bb->ins_list);
1840 if (ins->inst_c0 == 0 && (!next ||
1841 (next && INST_IGNORES_CFLAGS (next->opcode)))) {
1842 ins->opcode = OP_LXOR;
1843 ins->sreg1 = ins->dreg;
1844 ins->sreg2 = ins->dreg;
1852 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
1853 * 0 result into 64 bits.
1855 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1856 ins->opcode = OP_IXOR;
1860 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
1864 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
1865 * the latter has length 2-3 instead of 6 (reverse constant
1866 * propagation). These instruction sequences are very common
1867 * in the initlocals bblock.
1869 for (ins2 = mono_inst_list_next (&ins->node, &bb->ins_list); ins2;
1870 ins2 = mono_inst_list_next (&ins2->node, &bb->ins_list)) {
1871 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
1872 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
1873 ins2->sreg1 = ins->dreg;
1874 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
1876 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
1886 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1887 ins->opcode = OP_X86_INC_REG;
1890 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
1891 ins->opcode = OP_X86_DEC_REG;
1895 mono_peephole_ins (bb, ins);
1899 #define NEW_INS(cfg,ins,dest,op) do { \
1900 MONO_INST_NEW ((cfg), (dest), (op)); \
1901 (dest)->cil_code = (ins)->cil_code; \
1902 MONO_INST_LIST_ADD_TAIL (&(dest)->node, &(ins)->node); \
1906 * mono_arch_lowering_pass:
1908 * Converts complex opcodes into simpler ones so that each IR instruction
1909 * corresponds to one machine instruction.
1912 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1914 MonoInst *ins, *n, *temp;
1916 if (bb->max_vreg > cfg->rs->next_vreg)
1917 cfg->rs->next_vreg = bb->max_vreg;
1920 * FIXME: Need to add more instructions, but the current machine
1921 * description can't model some parts of the composite instructions like
1924 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
1925 switch (ins->opcode) {
1930 case OP_IDIV_UN_IMM:
1931 case OP_IREM_UN_IMM:
1932 mono_decompose_op_imm (cfg, ins);
1934 case OP_COMPARE_IMM:
1935 case OP_LCOMPARE_IMM:
1936 if (!amd64_is_imm32 (ins->inst_imm)) {
1937 NEW_INS (cfg, ins, temp, OP_I8CONST);
1938 temp->inst_c0 = ins->inst_imm;
1939 temp->dreg = mono_regstate_next_int (cfg->rs);
1940 ins->opcode = OP_COMPARE;
1941 ins->sreg2 = temp->dreg;
1944 case OP_LOAD_MEMBASE:
1945 case OP_LOADI8_MEMBASE:
1946 if (!amd64_is_imm32 (ins->inst_offset)) {
1947 NEW_INS (cfg, ins, temp, OP_I8CONST);
1948 temp->inst_c0 = ins->inst_offset;
1949 temp->dreg = mono_regstate_next_int (cfg->rs);
1950 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1951 ins->inst_indexreg = temp->dreg;
1954 case OP_STORE_MEMBASE_IMM:
1955 case OP_STOREI8_MEMBASE_IMM:
1956 if (!amd64_is_imm32 (ins->inst_imm)) {
1957 NEW_INS (cfg, ins, temp, OP_I8CONST);
1958 temp->inst_c0 = ins->inst_imm;
1959 temp->dreg = mono_regstate_next_int (cfg->rs);
1960 ins->opcode = OP_STOREI8_MEMBASE_REG;
1961 ins->sreg1 = temp->dreg;
1969 bb->max_vreg = cfg->rs->next_vreg;
1973 branch_cc_table [] = {
1974 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1975 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1976 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1979 /* Maps CMP_... constants to X86_CC_... constants */
1982 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
1983 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
1987 cc_signed_table [] = {
1988 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
1989 FALSE, FALSE, FALSE, FALSE
1992 /*#include "cprop.c"*/
1994 static unsigned char*
1995 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1997 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2000 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2002 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2006 static unsigned char*
2007 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2009 int sreg = tree->sreg1;
2010 int need_touch = FALSE;
2012 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2013 if (!tree->flags & MONO_INST_INIT)
2022 * If requested stack size is larger than one page,
2023 * perform stack-touch operation
2026 * Generate stack probe code.
2027 * Under Windows, it is necessary to allocate one page at a time,
2028 * "touching" stack after each successful sub-allocation. This is
2029 * because of the way stack growth is implemented - there is a
2030 * guard page before the lowest stack page that is currently commited.
2031 * Stack normally grows sequentially so OS traps access to the
2032 * guard page and commits more pages when needed.
2034 amd64_test_reg_imm (code, sreg, ~0xFFF);
2035 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2037 br[2] = code; /* loop */
2038 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2039 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2040 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2041 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2042 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2043 amd64_patch (br[3], br[2]);
2044 amd64_test_reg_reg (code, sreg, sreg);
2045 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2046 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2048 br[1] = code; x86_jump8 (code, 0);
2050 amd64_patch (br[0], code);
2051 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2052 amd64_patch (br[1], code);
2053 amd64_patch (br[4], code);
2056 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2058 if (tree->flags & MONO_INST_INIT) {
2060 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2061 amd64_push_reg (code, AMD64_RAX);
2064 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2065 amd64_push_reg (code, AMD64_RCX);
2068 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2069 amd64_push_reg (code, AMD64_RDI);
2073 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2074 if (sreg != AMD64_RCX)
2075 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2076 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2078 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2080 amd64_prefix (code, X86_REP_PREFIX);
2083 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2084 amd64_pop_reg (code, AMD64_RDI);
2085 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2086 amd64_pop_reg (code, AMD64_RCX);
2087 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2088 amd64_pop_reg (code, AMD64_RAX);
2094 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2099 /* Move return value to the target register */
2100 /* FIXME: do this in the local reg allocator */
2101 switch (ins->opcode) {
2104 case OP_CALL_MEMBASE:
2107 case OP_LCALL_MEMBASE:
2108 g_assert (ins->dreg == AMD64_RAX);
2112 case OP_FCALL_MEMBASE:
2113 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2114 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2117 if (ins->dreg != AMD64_XMM0)
2118 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2123 case OP_VCALL_MEMBASE:
2124 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2125 if (cinfo->ret.storage == ArgValuetypeInReg) {
2126 /* Pop the destination address from the stack */
2127 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2128 amd64_pop_reg (code, AMD64_RCX);
2130 for (quad = 0; quad < 2; quad ++) {
2131 switch (cinfo->ret.pair_storage [quad]) {
2133 amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2135 case ArgInFloatSSEReg:
2136 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2138 case ArgInDoubleSSEReg:
2139 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2156 * @code: buffer to store code to
2157 * @dreg: hard register where to place the result
2158 * @tls_offset: offset info
2160 * emit_tls_get emits in @code the native code that puts in the dreg register
2161 * the item in the thread local storage identified by tls_offset.
2163 * Returns: a pointer to the end of the stored code
2166 emit_tls_get (guint8* code, int dreg, int tls_offset)
2168 if (optimize_for_xen) {
2169 x86_prefix (code, X86_FS_PREFIX);
2170 amd64_mov_reg_mem (code, dreg, 0, 8);
2171 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2173 x86_prefix (code, X86_FS_PREFIX);
2174 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2180 * emit_load_volatile_arguments:
2182 * Load volatile arguments from the stack to the original input registers.
2183 * Required before a tail call.
2186 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2188 MonoMethod *method = cfg->method;
2189 MonoMethodSignature *sig;
2194 /* FIXME: Generate intermediate code instead */
2196 sig = mono_method_signature (method);
2198 cinfo = cfg->arch.cinfo;
2200 /* This is the opposite of the code in emit_prolog */
2201 if (sig->ret->type != MONO_TYPE_VOID) {
2202 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2203 amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2206 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2207 ArgInfo *ainfo = cinfo->args + i;
2209 ins = cfg->args [i];
2211 if (sig->hasthis && (i == 0))
2212 arg_type = &mono_defaults.object_class->byval_arg;
2214 arg_type = sig->params [i - sig->hasthis];
2216 if (ins->opcode != OP_REGVAR) {
2217 switch (ainfo->storage) {
2222 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2225 case ArgInFloatSSEReg:
2226 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2228 case ArgInDoubleSSEReg:
2229 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2231 case ArgValuetypeInReg:
2232 for (quad = 0; quad < 2; quad ++) {
2233 switch (ainfo->pair_storage [quad]) {
2235 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2237 case ArgInFloatSSEReg:
2238 case ArgInDoubleSSEReg:
2239 g_assert_not_reached ();
2244 g_assert_not_reached ();
2253 g_assert (ainfo->storage == ArgInIReg);
2255 amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2262 #define REAL_PRINT_REG(text,reg) \
2263 mono_assert (reg >= 0); \
2264 amd64_push_reg (code, AMD64_RAX); \
2265 amd64_push_reg (code, AMD64_RDX); \
2266 amd64_push_reg (code, AMD64_RCX); \
2267 amd64_push_reg (code, reg); \
2268 amd64_push_imm (code, reg); \
2269 amd64_push_imm (code, text " %d %p\n"); \
2270 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2271 amd64_call_reg (code, AMD64_RAX); \
2272 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2273 amd64_pop_reg (code, AMD64_RCX); \
2274 amd64_pop_reg (code, AMD64_RDX); \
2275 amd64_pop_reg (code, AMD64_RAX);
2277 /* benchmark and set based on cpu */
2278 #define LOOP_ALIGNMENT 8
2279 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2282 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2287 guint8 *code = cfg->native_code + cfg->code_len;
2288 guint last_offset = 0;
2291 if (cfg->opt & MONO_OPT_LOOP) {
2292 int pad, align = LOOP_ALIGNMENT;
2293 /* set alignment depending on cpu */
2294 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2296 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2297 amd64_padding (code, pad);
2298 cfg->code_len += pad;
2299 bb->native_offset = cfg->code_len;
2303 if (cfg->verbose_level > 2)
2304 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2306 cpos = bb->max_offset;
2308 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2309 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2310 g_assert (!cfg->compile_aot);
2313 cov->data [bb->dfn].cil_code = bb->cil_code;
2314 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2315 /* this is not thread save, but good enough */
2316 amd64_inc_membase (code, AMD64_R11, 0);
2319 offset = code - cfg->native_code;
2321 mono_debug_open_block (cfg, bb, offset);
2323 MONO_BB_FOR_EACH_INS (bb, ins) {
2324 offset = code - cfg->native_code;
2326 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2328 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
2329 cfg->code_size *= 2;
2330 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2331 code = cfg->native_code + offset;
2332 mono_jit_stats.code_reallocs++;
2335 if (cfg->debug_info)
2336 mono_debug_record_line_number (cfg, ins, offset);
2338 switch (ins->opcode) {
2340 amd64_mul_reg (code, ins->sreg2, TRUE);
2343 amd64_mul_reg (code, ins->sreg2, FALSE);
2345 case OP_X86_SETEQ_MEMBASE:
2346 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2348 case OP_STOREI1_MEMBASE_IMM:
2349 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2351 case OP_STOREI2_MEMBASE_IMM:
2352 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2354 case OP_STOREI4_MEMBASE_IMM:
2355 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2357 case OP_STOREI1_MEMBASE_REG:
2358 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2360 case OP_STOREI2_MEMBASE_REG:
2361 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2363 case OP_STORE_MEMBASE_REG:
2364 case OP_STOREI8_MEMBASE_REG:
2365 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2367 case OP_STOREI4_MEMBASE_REG:
2368 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2370 case OP_STORE_MEMBASE_IMM:
2371 case OP_STOREI8_MEMBASE_IMM:
2372 g_assert (amd64_is_imm32 (ins->inst_imm));
2373 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2377 // FIXME: Decompose this earlier
2378 if (amd64_is_imm32 (ins->inst_imm))
2379 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
2381 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2382 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
2386 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2387 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
2390 amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2391 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2394 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2395 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
2398 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
2399 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
2401 case OP_LOAD_MEMBASE:
2402 case OP_LOADI8_MEMBASE:
2403 g_assert (amd64_is_imm32 (ins->inst_offset));
2404 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2406 case OP_LOADI4_MEMBASE:
2407 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2409 case OP_LOADU4_MEMBASE:
2410 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2412 case OP_LOADU1_MEMBASE:
2413 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2415 case OP_LOADI1_MEMBASE:
2416 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2418 case OP_LOADU2_MEMBASE:
2419 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2421 case OP_LOADI2_MEMBASE:
2422 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2424 case OP_AMD64_LOADI8_MEMINDEX:
2425 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2427 case OP_LCONV_TO_I1:
2428 case OP_ICONV_TO_I1:
2430 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2432 case OP_LCONV_TO_I2:
2433 case OP_ICONV_TO_I2:
2435 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2437 case OP_LCONV_TO_U1:
2438 case OP_ICONV_TO_U1:
2439 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2441 case OP_LCONV_TO_U2:
2442 case OP_ICONV_TO_U2:
2443 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2446 /* Clean out the upper word */
2447 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2450 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2454 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2456 case OP_COMPARE_IMM:
2457 case OP_LCOMPARE_IMM:
2458 g_assert (amd64_is_imm32 (ins->inst_imm));
2459 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2461 case OP_X86_COMPARE_REG_MEMBASE:
2462 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2464 case OP_X86_TEST_NULL:
2465 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2467 case OP_AMD64_TEST_NULL:
2468 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2471 case OP_X86_ADD_REG_MEMBASE:
2472 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2474 case OP_X86_SUB_REG_MEMBASE:
2475 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2477 case OP_X86_AND_REG_MEMBASE:
2478 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2480 case OP_X86_OR_REG_MEMBASE:
2481 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2483 case OP_X86_XOR_REG_MEMBASE:
2484 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2487 case OP_X86_ADD_MEMBASE_IMM:
2488 /* FIXME: Make a 64 version too */
2489 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2491 case OP_X86_SUB_MEMBASE_IMM:
2492 g_assert (amd64_is_imm32 (ins->inst_imm));
2493 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2495 case OP_X86_AND_MEMBASE_IMM:
2496 g_assert (amd64_is_imm32 (ins->inst_imm));
2497 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2499 case OP_X86_OR_MEMBASE_IMM:
2500 g_assert (amd64_is_imm32 (ins->inst_imm));
2501 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2503 case OP_X86_XOR_MEMBASE_IMM:
2504 g_assert (amd64_is_imm32 (ins->inst_imm));
2505 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2507 case OP_X86_ADD_MEMBASE_REG:
2508 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2510 case OP_X86_SUB_MEMBASE_REG:
2511 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2513 case OP_X86_AND_MEMBASE_REG:
2514 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2516 case OP_X86_OR_MEMBASE_REG:
2517 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2519 case OP_X86_XOR_MEMBASE_REG:
2520 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2522 case OP_X86_INC_MEMBASE:
2523 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2525 case OP_X86_INC_REG:
2526 amd64_inc_reg_size (code, ins->dreg, 4);
2528 case OP_X86_DEC_MEMBASE:
2529 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2531 case OP_X86_DEC_REG:
2532 amd64_dec_reg_size (code, ins->dreg, 4);
2534 case OP_X86_MUL_REG_MEMBASE:
2535 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2537 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2538 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2540 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2541 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2543 case OP_AMD64_COMPARE_MEMBASE_REG:
2544 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2546 case OP_AMD64_COMPARE_MEMBASE_IMM:
2547 g_assert (amd64_is_imm32 (ins->inst_imm));
2548 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2550 case OP_X86_COMPARE_MEMBASE8_IMM:
2551 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2553 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2554 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2556 case OP_AMD64_COMPARE_REG_MEMBASE:
2557 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2560 case OP_AMD64_ADD_REG_MEMBASE:
2561 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2563 case OP_AMD64_SUB_REG_MEMBASE:
2564 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2566 case OP_AMD64_AND_REG_MEMBASE:
2567 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2569 case OP_AMD64_OR_REG_MEMBASE:
2570 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2572 case OP_AMD64_XOR_REG_MEMBASE:
2573 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
2576 case OP_AMD64_ADD_MEMBASE_REG:
2577 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2579 case OP_AMD64_SUB_MEMBASE_REG:
2580 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2582 case OP_AMD64_AND_MEMBASE_REG:
2583 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2585 case OP_AMD64_OR_MEMBASE_REG:
2586 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2588 case OP_AMD64_XOR_MEMBASE_REG:
2589 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
2592 case OP_AMD64_ADD_MEMBASE_IMM:
2593 g_assert (amd64_is_imm32 (ins->inst_imm));
2594 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2596 case OP_AMD64_SUB_MEMBASE_IMM:
2597 g_assert (amd64_is_imm32 (ins->inst_imm));
2598 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2600 case OP_AMD64_AND_MEMBASE_IMM:
2601 g_assert (amd64_is_imm32 (ins->inst_imm));
2602 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2604 case OP_AMD64_OR_MEMBASE_IMM:
2605 g_assert (amd64_is_imm32 (ins->inst_imm));
2606 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2608 case OP_AMD64_XOR_MEMBASE_IMM:
2609 g_assert (amd64_is_imm32 (ins->inst_imm));
2610 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
2614 amd64_breakpoint (code);
2618 case OP_DUMMY_STORE:
2619 case OP_NOT_REACHED:
2624 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2627 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2631 g_assert (amd64_is_imm32 (ins->inst_imm));
2632 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2635 g_assert (amd64_is_imm32 (ins->inst_imm));
2636 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2640 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2643 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2647 g_assert (amd64_is_imm32 (ins->inst_imm));
2648 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2651 g_assert (amd64_is_imm32 (ins->inst_imm));
2652 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2655 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2659 g_assert (amd64_is_imm32 (ins->inst_imm));
2660 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2663 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2668 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2670 switch (ins->inst_imm) {
2674 if (ins->dreg != ins->sreg1)
2675 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2676 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2679 /* LEA r1, [r2 + r2*2] */
2680 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2683 /* LEA r1, [r2 + r2*4] */
2684 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2687 /* LEA r1, [r2 + r2*2] */
2689 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2690 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2693 /* LEA r1, [r2 + r2*8] */
2694 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2697 /* LEA r1, [r2 + r2*4] */
2699 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2700 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2703 /* LEA r1, [r2 + r2*2] */
2705 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2706 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2709 /* LEA r1, [r2 + r2*4] */
2710 /* LEA r1, [r1 + r1*4] */
2711 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2712 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2715 /* LEA r1, [r2 + r2*4] */
2717 /* LEA r1, [r1 + r1*4] */
2718 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2719 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2720 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2723 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2730 /* Regalloc magic makes the div/rem cases the same */
2731 if (ins->sreg2 == AMD64_RDX) {
2732 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2734 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
2737 amd64_div_reg (code, ins->sreg2, TRUE);
2742 if (ins->sreg2 == AMD64_RDX) {
2743 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2744 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2745 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
2747 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2748 amd64_div_reg (code, ins->sreg2, FALSE);
2753 if (ins->sreg2 == AMD64_RDX) {
2754 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2755 amd64_cdq_size (code, 4);
2756 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
2758 amd64_cdq_size (code, 4);
2759 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2764 if (ins->sreg2 == AMD64_RDX) {
2765 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
2766 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2767 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
2769 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2770 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2774 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2775 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2778 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2782 g_assert (amd64_is_imm32 (ins->inst_imm));
2783 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2786 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2790 g_assert (amd64_is_imm32 (ins->inst_imm));
2791 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2794 g_assert (ins->sreg2 == AMD64_RCX);
2795 amd64_shift_reg (code, X86_SHL, ins->dreg);
2798 g_assert (ins->sreg2 == AMD64_RCX);
2799 amd64_shift_reg (code, X86_SAR, ins->dreg);
2802 g_assert (amd64_is_imm32 (ins->inst_imm));
2803 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2806 g_assert (amd64_is_imm32 (ins->inst_imm));
2807 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2810 g_assert (amd64_is_imm32 (ins->inst_imm));
2811 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2813 case OP_LSHR_UN_IMM:
2814 g_assert (amd64_is_imm32 (ins->inst_imm));
2815 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2818 g_assert (ins->sreg2 == AMD64_RCX);
2819 amd64_shift_reg (code, X86_SHR, ins->dreg);
2822 g_assert (amd64_is_imm32 (ins->inst_imm));
2823 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2826 g_assert (amd64_is_imm32 (ins->inst_imm));
2827 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2832 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2835 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2838 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2841 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2845 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2848 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2851 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2854 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2857 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2860 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2863 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2866 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2869 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2872 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2875 amd64_neg_reg_size (code, ins->sreg1, 4);
2878 amd64_not_reg_size (code, ins->sreg1, 4);
2881 g_assert (ins->sreg2 == AMD64_RCX);
2882 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2885 g_assert (ins->sreg2 == AMD64_RCX);
2886 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2889 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2891 case OP_ISHR_UN_IMM:
2892 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2895 g_assert (ins->sreg2 == AMD64_RCX);
2896 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2899 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2902 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2905 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2906 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2908 case OP_IMUL_OVF_UN:
2909 case OP_LMUL_OVF_UN: {
2910 /* the mul operation and the exception check should most likely be split */
2911 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2912 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2913 /*g_assert (ins->sreg2 == X86_EAX);
2914 g_assert (ins->dreg == X86_EAX);*/
2915 if (ins->sreg2 == X86_EAX) {
2916 non_eax_reg = ins->sreg1;
2917 } else if (ins->sreg1 == X86_EAX) {
2918 non_eax_reg = ins->sreg2;
2920 /* no need to save since we're going to store to it anyway */
2921 if (ins->dreg != X86_EAX) {
2923 amd64_push_reg (code, X86_EAX);
2925 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2926 non_eax_reg = ins->sreg2;
2928 if (ins->dreg == X86_EDX) {
2931 amd64_push_reg (code, X86_EAX);
2935 amd64_push_reg (code, X86_EDX);
2937 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2938 /* save before the check since pop and mov don't change the flags */
2939 if (ins->dreg != X86_EAX)
2940 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2942 amd64_pop_reg (code, X86_EDX);
2944 amd64_pop_reg (code, X86_EAX);
2945 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2949 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2951 case OP_ICOMPARE_IMM:
2952 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2974 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
2978 amd64_not_reg (code, ins->sreg1);
2981 amd64_neg_reg (code, ins->sreg1);
2986 if ((((guint64)ins->inst_c0) >> 32) == 0)
2987 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2989 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2992 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2993 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2996 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2998 case OP_AMD64_SET_XMMREG_R4: {
2999 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3002 case OP_AMD64_SET_XMMREG_R8: {
3003 if (ins->dreg != ins->sreg1)
3004 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3009 * Note: this 'frame destruction' logic is useful for tail calls, too.
3010 * Keep in sync with the code in emit_epilog.
3014 /* FIXME: no tracing support... */
3015 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3016 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3018 g_assert (!cfg->method->save_lmf);
3020 code = emit_load_volatile_arguments (cfg, code);
3022 if (cfg->arch.omit_fp) {
3023 guint32 save_offset = 0;
3024 /* Pop callee-saved registers */
3025 for (i = 0; i < AMD64_NREG; ++i)
3026 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3027 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3030 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3033 for (i = 0; i < AMD64_NREG; ++i)
3034 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3035 pos -= sizeof (gpointer);
3038 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3040 /* Pop registers in reverse order */
3041 for (i = AMD64_NREG - 1; i > 0; --i)
3042 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3043 amd64_pop_reg (code, i);
3049 offset = code - cfg->native_code;
3050 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3051 if (cfg->compile_aot)
3052 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3054 amd64_set_reg_template (code, AMD64_R11);
3055 amd64_jump_reg (code, AMD64_R11);
3059 /* ensure ins->sreg1 is not NULL */
3060 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3063 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3064 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3072 call = (MonoCallInst*)ins;
3074 * The AMD64 ABI forces callers to know about varargs.
3076 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3077 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3078 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3080 * Since the unmanaged calling convention doesn't contain a
3081 * 'vararg' entry, we have to treat every pinvoke call as a
3082 * potential vararg call.
3086 for (i = 0; i < AMD64_XMM_NREG; ++i)
3087 if (call->used_fregs & (1 << i))
3090 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3092 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3095 if (ins->flags & MONO_INST_HAS_METHOD)
3096 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3098 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3099 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3100 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3101 code = emit_move_return_value (cfg, ins, code);
3106 case OP_VOIDCALL_REG:
3108 call = (MonoCallInst*)ins;
3110 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3111 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3112 ins->sreg1 = AMD64_R11;
3116 * The AMD64 ABI forces callers to know about varargs.
3118 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3119 if (ins->sreg1 == AMD64_RAX) {
3120 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3121 ins->sreg1 = AMD64_R11;
3123 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3125 amd64_call_reg (code, ins->sreg1);
3126 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3127 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3128 code = emit_move_return_value (cfg, ins, code);
3130 case OP_FCALL_MEMBASE:
3131 case OP_LCALL_MEMBASE:
3132 case OP_VCALL_MEMBASE:
3133 case OP_VOIDCALL_MEMBASE:
3134 case OP_CALL_MEMBASE:
3135 call = (MonoCallInst*)ins;
3137 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3139 * Can't use R11 because it is clobbered by the trampoline
3140 * code, and the reg value is needed by get_vcall_slot_addr.
3142 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3143 ins->sreg1 = AMD64_RAX;
3146 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3147 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3148 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3149 code = emit_move_return_value (cfg, ins, code);
3151 case OP_AMD64_SAVE_SP_TO_LMF:
3152 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3156 amd64_push_reg (code, ins->sreg1);
3158 case OP_X86_PUSH_IMM:
3159 g_assert (amd64_is_imm32 (ins->inst_imm));
3160 amd64_push_imm (code, ins->inst_imm);
3162 case OP_X86_PUSH_MEMBASE:
3163 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3165 case OP_X86_PUSH_OBJ:
3166 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3167 amd64_push_reg (code, AMD64_RDI);
3168 amd64_push_reg (code, AMD64_RSI);
3169 amd64_push_reg (code, AMD64_RCX);
3170 if (ins->inst_offset)
3171 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3173 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3174 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3175 amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3177 amd64_prefix (code, X86_REP_PREFIX);
3179 amd64_pop_reg (code, AMD64_RCX);
3180 amd64_pop_reg (code, AMD64_RSI);
3181 amd64_pop_reg (code, AMD64_RDI);
3184 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3186 case OP_X86_LEA_MEMBASE:
3187 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3190 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3193 /* keep alignment */
3194 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3195 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3196 code = mono_emit_stack_alloc (code, ins);
3197 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3199 case OP_LOCALLOC_IMM: {
3200 guint32 size = ins->inst_imm;
3201 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3203 if (ins->flags & MONO_INST_INIT) {
3204 /* FIXME: Optimize this */
3205 amd64_mov_reg_imm (code, ins->dreg, size);
3206 ins->sreg1 = ins->dreg;
3208 code = mono_emit_stack_alloc (code, ins);
3209 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3211 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3212 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3217 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3218 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3219 (gpointer)"mono_arch_throw_exception", FALSE);
3223 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
3224 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3225 (gpointer)"mono_arch_rethrow_exception", FALSE);
3228 case OP_CALL_HANDLER:
3230 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3231 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3232 amd64_call_imm (code, 0);
3233 /* Restore stack alignment */
3234 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3236 case OP_START_HANDLER: {
3237 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3238 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
3241 case OP_ENDFINALLY: {
3242 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3243 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3247 case OP_ENDFILTER: {
3248 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
3249 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
3250 /* The local allocator will put the result into RAX */
3256 ins->inst_c0 = code - cfg->native_code;
3259 if (ins->flags & MONO_INST_BRLABEL) {
3260 if (ins->inst_i0->inst_c0) {
3261 amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3263 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3264 if ((cfg->opt & MONO_OPT_BRANCH) &&
3265 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3266 x86_jump8 (code, 0);
3268 x86_jump32 (code, 0);
3271 if (ins->inst_target_bb->native_offset) {
3272 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3274 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3275 if ((cfg->opt & MONO_OPT_BRANCH) &&
3276 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3277 x86_jump8 (code, 0);
3279 x86_jump32 (code, 0);
3284 amd64_jump_reg (code, ins->sreg1);
3301 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3302 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3304 case OP_COND_EXC_EQ:
3305 case OP_COND_EXC_NE_UN:
3306 case OP_COND_EXC_LT:
3307 case OP_COND_EXC_LT_UN:
3308 case OP_COND_EXC_GT:
3309 case OP_COND_EXC_GT_UN:
3310 case OP_COND_EXC_GE:
3311 case OP_COND_EXC_GE_UN:
3312 case OP_COND_EXC_LE:
3313 case OP_COND_EXC_LE_UN:
3314 case OP_COND_EXC_IEQ:
3315 case OP_COND_EXC_INE_UN:
3316 case OP_COND_EXC_ILT:
3317 case OP_COND_EXC_ILT_UN:
3318 case OP_COND_EXC_IGT:
3319 case OP_COND_EXC_IGT_UN:
3320 case OP_COND_EXC_IGE:
3321 case OP_COND_EXC_IGE_UN:
3322 case OP_COND_EXC_ILE:
3323 case OP_COND_EXC_ILE_UN:
3324 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
3326 case OP_COND_EXC_OV:
3327 case OP_COND_EXC_NO:
3329 case OP_COND_EXC_NC:
3330 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3331 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3333 case OP_COND_EXC_IOV:
3334 case OP_COND_EXC_INO:
3335 case OP_COND_EXC_IC:
3336 case OP_COND_EXC_INC:
3337 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
3338 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
3341 /* floating point opcodes */
3343 double d = *(double *)ins->inst_p0;
3345 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3346 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3349 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3350 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3355 float f = *(float *)ins->inst_p0;
3357 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3358 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3361 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3362 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3363 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3367 case OP_STORER8_MEMBASE_REG:
3368 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3370 case OP_LOADR8_SPILL_MEMBASE:
3371 g_assert_not_reached ();
3373 case OP_LOADR8_MEMBASE:
3374 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3376 case OP_STORER4_MEMBASE_REG:
3377 /* This requires a double->single conversion */
3378 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3379 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3381 case OP_LOADR4_MEMBASE:
3382 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3383 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3385 case OP_ICONV_TO_R4: /* FIXME: change precision */
3386 case OP_ICONV_TO_R8:
3387 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3389 case OP_LCONV_TO_R4: /* FIXME: change precision */
3390 case OP_LCONV_TO_R8:
3391 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3393 case OP_FCONV_TO_R4:
3394 /* FIXME: nothing to do ?? */
3396 case OP_FCONV_TO_I1:
3397 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3399 case OP_FCONV_TO_U1:
3400 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3402 case OP_FCONV_TO_I2:
3403 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3405 case OP_FCONV_TO_U2:
3406 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3408 case OP_FCONV_TO_U4:
3409 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
3411 case OP_FCONV_TO_I4:
3413 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3415 case OP_FCONV_TO_I8:
3416 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3418 case OP_LCONV_TO_R_UN: {
3421 /* Based on gcc code */
3422 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3423 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
3426 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3427 br [1] = code; x86_jump8 (code, 0);
3428 amd64_patch (br [0], code);
3431 /* Save to the red zone */
3432 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
3433 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
3434 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
3435 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3436 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
3437 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
3438 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
3439 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
3440 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
3442 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
3443 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
3444 amd64_patch (br [1], code);
3447 case OP_LCONV_TO_OVF_U4:
3448 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3449 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3450 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3452 case OP_LCONV_TO_OVF_I4_UN:
3453 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3454 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3455 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3458 if (ins->dreg != ins->sreg1)
3459 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3462 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3465 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3468 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3471 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3474 static double r8_0 = -0.0;
3476 g_assert (ins->sreg1 == ins->dreg);
3478 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3479 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3483 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3486 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3489 static guint64 d = 0x7fffffffffffffffUL;
3491 g_assert (ins->sreg1 == ins->dreg);
3493 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
3494 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3498 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3501 g_assert (cfg->opt & MONO_OPT_CMOV);
3502 g_assert (ins->dreg == ins->sreg1);
3503 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3504 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
3507 g_assert (cfg->opt & MONO_OPT_CMOV);
3508 g_assert (ins->dreg == ins->sreg1);
3509 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3510 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
3513 g_assert (cfg->opt & MONO_OPT_CMOV);
3514 g_assert (ins->dreg == ins->sreg1);
3515 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3516 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
3519 g_assert (cfg->opt & MONO_OPT_CMOV);
3520 g_assert (ins->dreg == ins->sreg1);
3521 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3522 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
3525 g_assert (cfg->opt & MONO_OPT_CMOV);
3526 g_assert (ins->dreg == ins->sreg1);
3527 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3528 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
3531 g_assert (cfg->opt & MONO_OPT_CMOV);
3532 g_assert (ins->dreg == ins->sreg1);
3533 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3534 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
3537 g_assert (cfg->opt & MONO_OPT_CMOV);
3538 g_assert (ins->dreg == ins->sreg1);
3539 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3540 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
3543 g_assert (cfg->opt & MONO_OPT_CMOV);
3544 g_assert (ins->dreg == ins->sreg1);
3545 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3546 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
3552 * The two arguments are swapped because the fbranch instructions
3553 * depend on this for the non-sse case to work.
3555 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3558 /* zeroing the register at the start results in
3559 * shorter and faster code (we can also remove the widening op)
3561 guchar *unordered_check;
3562 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3563 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3564 unordered_check = code;
3565 x86_branch8 (code, X86_CC_P, 0, FALSE);
3566 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3567 amd64_patch (unordered_check, code);
3572 /* zeroing the register at the start results in
3573 * shorter and faster code (we can also remove the widening op)
3575 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3576 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3577 if (ins->opcode == OP_FCLT_UN) {
3578 guchar *unordered_check = code;
3579 guchar *jump_to_end;
3580 x86_branch8 (code, X86_CC_P, 0, FALSE);
3581 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3583 x86_jump8 (code, 0);
3584 amd64_patch (unordered_check, code);
3585 amd64_inc_reg (code, ins->dreg);
3586 amd64_patch (jump_to_end, code);
3588 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3593 /* zeroing the register at the start results in
3594 * shorter and faster code (we can also remove the widening op)
3596 guchar *unordered_check;
3597 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3598 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3599 if (ins->opcode == OP_FCGT) {
3600 unordered_check = code;
3601 x86_branch8 (code, X86_CC_P, 0, FALSE);
3602 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3603 amd64_patch (unordered_check, code);
3605 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3609 case OP_FCLT_MEMBASE:
3610 case OP_FCGT_MEMBASE:
3611 case OP_FCLT_UN_MEMBASE:
3612 case OP_FCGT_UN_MEMBASE:
3613 case OP_FCEQ_MEMBASE: {
3614 guchar *unordered_check, *jump_to_end;
3617 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3618 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3620 switch (ins->opcode) {
3621 case OP_FCEQ_MEMBASE:
3622 x86_cond = X86_CC_EQ;
3624 case OP_FCLT_MEMBASE:
3625 case OP_FCLT_UN_MEMBASE:
3626 x86_cond = X86_CC_LT;
3628 case OP_FCGT_MEMBASE:
3629 case OP_FCGT_UN_MEMBASE:
3630 x86_cond = X86_CC_GT;
3633 g_assert_not_reached ();
3636 unordered_check = code;
3637 x86_branch8 (code, X86_CC_P, 0, FALSE);
3638 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3640 switch (ins->opcode) {
3641 case OP_FCEQ_MEMBASE:
3642 case OP_FCLT_MEMBASE:
3643 case OP_FCGT_MEMBASE:
3644 amd64_patch (unordered_check, code);
3646 case OP_FCLT_UN_MEMBASE:
3647 case OP_FCGT_UN_MEMBASE:
3649 x86_jump8 (code, 0);
3650 amd64_patch (unordered_check, code);
3651 amd64_inc_reg (code, ins->dreg);
3652 amd64_patch (jump_to_end, code);
3660 guchar *jump = code;
3661 x86_branch8 (code, X86_CC_P, 0, TRUE);
3662 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3663 amd64_patch (jump, code);
3667 /* Branch if C013 != 100 */
3668 /* branch if !ZF or (PF|CF) */
3669 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3670 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3671 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3674 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3677 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3678 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3682 if (ins->opcode == OP_FBGT) {
3685 /* skip branch if C1=1 */
3687 x86_branch8 (code, X86_CC_P, 0, FALSE);
3688 /* branch if (C0 | C3) = 1 */
3689 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3690 amd64_patch (br1, code);
3693 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3697 /* Branch if C013 == 100 or 001 */
3700 /* skip branch if C1=1 */
3702 x86_branch8 (code, X86_CC_P, 0, FALSE);
3703 /* branch if (C0 | C3) = 1 */
3704 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3705 amd64_patch (br1, code);
3709 /* Branch if C013 == 000 */
3710 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3713 /* Branch if C013=000 or 100 */
3716 /* skip branch if C1=1 */
3718 x86_branch8 (code, X86_CC_P, 0, FALSE);
3719 /* branch if C0=0 */
3720 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3721 amd64_patch (br1, code);
3725 /* Branch if C013 != 001 */
3726 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3727 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3730 /* Transfer value to the fp stack */
3731 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3732 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3733 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3735 amd64_push_reg (code, AMD64_RAX);
3737 amd64_fnstsw (code);
3738 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3739 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3740 amd64_pop_reg (code, AMD64_RAX);
3741 amd64_fstp (code, 0);
3742 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3743 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3746 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
3749 case OP_MEMORY_BARRIER: {
3750 /* Not needed on amd64 */
3753 case OP_ATOMIC_ADD_I4:
3754 case OP_ATOMIC_ADD_I8: {
3755 int dreg = ins->dreg;
3756 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3758 if (dreg == ins->inst_basereg)
3761 if (dreg != ins->sreg2)
3762 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3764 x86_prefix (code, X86_LOCK_PREFIX);
3765 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3767 if (dreg != ins->dreg)
3768 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3772 case OP_ATOMIC_ADD_NEW_I4:
3773 case OP_ATOMIC_ADD_NEW_I8: {
3774 int dreg = ins->dreg;
3775 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3777 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3780 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3781 amd64_prefix (code, X86_LOCK_PREFIX);
3782 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3783 /* dreg contains the old value, add with sreg2 value */
3784 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3786 if (ins->dreg != dreg)
3787 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3791 case OP_ATOMIC_EXCHANGE_I4:
3792 case OP_ATOMIC_EXCHANGE_I8:
3793 case OP_ATOMIC_CAS_IMM_I4: {
3795 int sreg2 = ins->sreg2;
3796 int breg = ins->inst_basereg;
3798 gboolean need_push = FALSE, rdx_pushed = FALSE;
3800 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
3806 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
3807 * an explanation of how this works.
3810 /* cmpxchg uses eax as comperand, need to make sure we can use it
3811 * hack to overcome limits in x86 reg allocator
3812 * (req: dreg == eax and sreg2 != eax and breg != eax)
3814 g_assert (ins->dreg == AMD64_RAX);
3816 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
3817 /* Highly unlikely, but possible */
3820 /* The pushes invalidate rsp */
3821 if ((breg == AMD64_RAX) || need_push) {
3822 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
3826 /* We need the EAX reg for the comparand */
3827 if (ins->sreg2 == AMD64_RAX) {
3828 if (breg != AMD64_R11) {
3829 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3832 g_assert (need_push);
3833 amd64_push_reg (code, AMD64_RDX);
3834 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3840 if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
3841 if (ins->backend.data == NULL)
3842 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3844 amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
3846 amd64_prefix (code, X86_LOCK_PREFIX);
3847 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3849 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3851 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3852 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3853 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3854 amd64_patch (br [1], br [0]);
3858 amd64_pop_reg (code, AMD64_RDX);
3863 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3864 g_assert_not_reached ();
3867 if ((code - cfg->native_code - offset) > max_len) {
3868 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3869 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3870 g_assert_not_reached ();
3875 last_offset = offset;
3878 cfg->code_len = code - cfg->native_code;
3882 mono_arch_register_lowlevel_calls (void)
3887 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3889 MonoJumpInfo *patch_info;
3890 gboolean compile_aot = !run_cctors;
3892 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3893 unsigned char *ip = patch_info->ip.i + code;
3894 unsigned char *target;
3896 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3899 switch (patch_info->type) {
3900 case MONO_PATCH_INFO_BB:
3901 case MONO_PATCH_INFO_LABEL:
3904 /* No need to patch these */
3909 switch (patch_info->type) {
3910 case MONO_PATCH_INFO_NONE:
3912 case MONO_PATCH_INFO_METHOD_REL:
3913 case MONO_PATCH_INFO_R8:
3914 case MONO_PATCH_INFO_R4:
3915 g_assert_not_reached ();
3917 case MONO_PATCH_INFO_BB:
3924 * Debug code to help track down problems where the target of a near call is
3927 if (amd64_is_near_call (ip)) {
3928 gint64 disp = (guint8*)target - (guint8*)ip;
3930 if (!amd64_is_imm32 (disp)) {
3931 printf ("TYPE: %d\n", patch_info->type);
3932 switch (patch_info->type) {
3933 case MONO_PATCH_INFO_INTERNAL_METHOD:
3934 printf ("V: %s\n", patch_info->data.name);
3936 case MONO_PATCH_INFO_METHOD_JUMP:
3937 case MONO_PATCH_INFO_METHOD:
3938 printf ("V: %s\n", patch_info->data.method->name);
3946 amd64_patch (ip, (gpointer)target);
3951 get_max_epilog_size (MonoCompile *cfg)
3953 int max_epilog_size = 16;
3955 if (cfg->method->save_lmf)
3956 max_epilog_size += 256;
3958 if (mono_jit_trace_calls != NULL)
3959 max_epilog_size += 50;
3961 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3962 max_epilog_size += 50;
3964 max_epilog_size += (AMD64_NREG * 2);
3966 return max_epilog_size;
3970 * This macro is used for testing whenever the unwinder works correctly at every point
3971 * where an async exception can happen.
3973 /* This will generate a SIGSEGV at the given point in the code */
3974 #define async_exc_point(code) do { \
3975 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
3976 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
3977 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
3978 cfg->arch.async_point_count ++; \
3983 mono_arch_emit_prolog (MonoCompile *cfg)
3985 MonoMethod *method = cfg->method;
3987 MonoMethodSignature *sig;
3989 int alloc_size, pos, max_offset, i, quad, max_epilog_size;
3992 gint32 lmf_offset = cfg->arch.lmf_offset;
3993 gboolean args_clobbered = FALSE;
3994 gboolean trace = FALSE;
3996 cfg->code_size = MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
3998 code = cfg->native_code = g_malloc (cfg->code_size);
4000 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4003 /* Amount of stack space allocated by register saving code */
4007 * The prolog consists of the following parts:
4009 * - push rbp, mov rbp, rsp
4010 * - save callee saved regs using pushes
4012 * - save rgctx if needed
4013 * - save lmf if needed
4016 * - save rgctx if needed
4017 * - save lmf if needed
4018 * - save callee saved regs using moves
4021 async_exc_point (code);
4023 if (!cfg->arch.omit_fp) {
4024 amd64_push_reg (code, AMD64_RBP);
4025 async_exc_point (code);
4026 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4027 async_exc_point (code);
4030 /* Save callee saved registers */
4031 if (!cfg->arch.omit_fp && !method->save_lmf) {
4032 for (i = 0; i < AMD64_NREG; ++i)
4033 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4034 amd64_push_reg (code, i);
4035 pos += sizeof (gpointer);
4036 async_exc_point (code);
4040 if (cfg->arch.omit_fp) {
4042 * On enter, the stack is misaligned by the the pushing of the return
4043 * address. It is either made aligned by the pushing of %rbp, or by
4046 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4047 if ((alloc_size % 16) == 0)
4050 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4055 cfg->arch.stack_alloc_size = alloc_size;
4057 /* Allocate stack frame */
4059 /* See mono_emit_stack_alloc */
4060 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4061 guint32 remaining_size = alloc_size;
4062 while (remaining_size >= 0x1000) {
4063 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4064 async_exc_point (code);
4065 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4066 remaining_size -= 0x1000;
4068 if (remaining_size) {
4069 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4070 async_exc_point (code);
4073 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4074 async_exc_point (code);
4078 /* Stack alignment check */
4081 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4082 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4083 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4084 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4085 amd64_breakpoint (code);
4090 if (method->save_lmf) {
4092 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4094 /* sp is saved right before calls */
4095 /* Skip method (only needed for trampoline LMF frames) */
4096 /* Save callee saved regs */
4097 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4098 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4099 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4100 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4101 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4102 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4105 /* Save callee saved registers */
4106 if (cfg->arch.omit_fp && !method->save_lmf) {
4107 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4109 /* Save caller saved registers after sp is adjusted */
4110 /* The registers are saved at the bottom of the frame */
4111 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4112 for (i = 0; i < AMD64_NREG; ++i)
4113 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4114 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4115 save_area_offset += 8;
4116 async_exc_point (code);
4120 /* store runtime generic context */
4121 if (cfg->rgctx_var) {
4122 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4123 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4125 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4128 /* compute max_offset in order to use short forward jumps */
4130 max_epilog_size = get_max_epilog_size (cfg);
4131 if (cfg->opt & MONO_OPT_BRANCH) {
4132 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4133 bb->max_offset = max_offset;
4135 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4137 /* max alignment for loops */
4138 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4139 max_offset += LOOP_ALIGNMENT;
4141 MONO_BB_FOR_EACH_INS (bb, ins) {
4142 if (ins->opcode == OP_LABEL)
4143 ins->inst_c1 = max_offset;
4145 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4148 if (mono_jit_trace_calls && bb == cfg->bb_exit)
4149 /* The tracing code can be quite large */
4150 max_offset += max_epilog_size;
4154 sig = mono_method_signature (method);
4157 cinfo = cfg->arch.cinfo;
4159 if (sig->ret->type != MONO_TYPE_VOID) {
4160 /* Save volatile arguments to the stack */
4161 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4162 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4165 /* Keep this in sync with emit_load_volatile_arguments */
4166 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4167 ArgInfo *ainfo = cinfo->args + i;
4168 gint32 stack_offset;
4171 ins = cfg->args [i];
4173 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
4174 /* Unused arguments */
4177 if (sig->hasthis && (i == 0))
4178 arg_type = &mono_defaults.object_class->byval_arg;
4180 arg_type = sig->params [i - sig->hasthis];
4182 stack_offset = ainfo->offset + ARGS_OFFSET;
4184 /* Save volatile arguments to the stack */
4185 if (ins->opcode != OP_REGVAR) {
4186 switch (ainfo->storage) {
4192 if (stack_offset & 0x1)
4194 else if (stack_offset & 0x2)
4196 else if (stack_offset & 0x4)
4201 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
4204 case ArgInFloatSSEReg:
4205 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4207 case ArgInDoubleSSEReg:
4208 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
4210 case ArgValuetypeInReg:
4211 for (quad = 0; quad < 2; quad ++) {
4212 switch (ainfo->pair_storage [quad]) {
4214 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4216 case ArgInFloatSSEReg:
4217 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4219 case ArgInDoubleSSEReg:
4220 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4225 g_assert_not_reached ();
4233 /* Argument allocated to (non-volatile) register */
4234 switch (ainfo->storage) {
4236 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
4239 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4242 g_assert_not_reached ();
4247 /* Might need to attach the thread to the JIT or change the domain for the callback */
4248 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4249 guint64 domain = (guint64)cfg->domain;
4251 args_clobbered = TRUE;
4254 * The call might clobber argument registers, but they are already
4255 * saved to the stack/global regs.
4257 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
4258 guint8 *buf, *no_domain_branch;
4260 code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
4261 if ((domain >> 32) == 0)
4262 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4264 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4265 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
4266 no_domain_branch = code;
4267 x86_branch8 (code, X86_CC_NE, 0, 0);
4268 code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4269 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4271 x86_branch8 (code, X86_CC_NE, 0, 0);
4272 amd64_patch (no_domain_branch, code);
4273 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4274 (gpointer)"mono_jit_thread_attach", TRUE);
4275 amd64_patch (buf, code);
4277 g_assert (!cfg->compile_aot);
4278 if ((domain >> 32) == 0)
4279 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
4281 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
4282 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4283 (gpointer)"mono_jit_thread_attach", TRUE);
4287 if (method->save_lmf) {
4288 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4290 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4291 * through the mono_lmf_addr TLS variable.
4293 /* %rax = previous_lmf */
4294 x86_prefix (code, X86_FS_PREFIX);
4295 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4297 /* Save previous_lmf */
4298 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4300 if (lmf_offset == 0) {
4301 x86_prefix (code, X86_FS_PREFIX);
4302 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
4304 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4305 x86_prefix (code, X86_FS_PREFIX);
4306 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4309 if (lmf_addr_tls_offset != -1) {
4310 /* Load lmf quicky using the FS register */
4311 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4315 * The call might clobber argument registers, but they are already
4316 * saved to the stack/global regs.
4318 args_clobbered = TRUE;
4319 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4320 (gpointer)"mono_get_lmf_addr", TRUE);
4324 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4325 /* Save previous_lmf */
4326 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4327 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4329 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4330 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4335 args_clobbered = TRUE;
4336 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4339 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4340 args_clobbered = TRUE;
4343 * Optimize the common case of the first bblock making a call with the same
4344 * arguments as the method. This works because the arguments are still in their
4345 * original argument registers.
4346 * FIXME: Generalize this
4348 if (!args_clobbered) {
4349 MonoBasicBlock *first_bb = cfg->bb_entry;
4352 next = mono_inst_list_first (&first_bb->ins_list);
4353 if (!next && first_bb->next_bb) {
4354 first_bb = first_bb->next_bb;
4355 next = mono_inst_list_first (&first_bb->ins_list);
4358 if (first_bb->in_count > 1)
4361 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
4362 ArgInfo *ainfo = cinfo->args + i;
4363 gboolean match = FALSE;
4365 ins = cfg->args [i];
4366 if (ins->opcode != OP_REGVAR) {
4367 switch (ainfo->storage) {
4369 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
4370 if (next->dreg == ainfo->reg) {
4374 next->opcode = OP_MOVE;
4375 next->sreg1 = ainfo->reg;
4376 /* Only continue if the instruction doesn't change argument regs */
4377 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
4387 /* Argument allocated to (non-volatile) register */
4388 switch (ainfo->storage) {
4390 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
4401 next = mono_inst_list_next (&next->node, &first_bb->ins_list);
4408 cfg->code_len = code - cfg->native_code;
4410 g_assert (cfg->code_len < cfg->code_size);
4416 mono_arch_emit_epilog (MonoCompile *cfg)
4418 MonoMethod *method = cfg->method;
4421 int max_epilog_size;
4423 gint32 lmf_offset = cfg->arch.lmf_offset;
4425 max_epilog_size = get_max_epilog_size (cfg);
4427 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4428 cfg->code_size *= 2;
4429 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4430 mono_jit_stats.code_reallocs++;
4433 code = cfg->native_code + cfg->code_len;
4435 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4436 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4438 /* the code restoring the registers must be kept in sync with OP_JMP */
4441 if (method->save_lmf) {
4442 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4444 * Optimized version which uses the mono_lmf TLS variable instead of indirection
4445 * through the mono_lmf_addr TLS variable.
4447 /* reg = previous_lmf */
4448 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4449 x86_prefix (code, X86_FS_PREFIX);
4450 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4452 /* Restore previous lmf */
4453 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4454 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4455 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4458 /* Restore caller saved regs */
4459 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4460 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
4462 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4463 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4465 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4466 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4468 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4469 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4471 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4472 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4474 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4475 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4479 if (cfg->arch.omit_fp) {
4480 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4482 for (i = 0; i < AMD64_NREG; ++i)
4483 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4484 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4485 save_area_offset += 8;
4489 for (i = 0; i < AMD64_NREG; ++i)
4490 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4491 pos -= sizeof (gpointer);
4494 if (pos == - sizeof (gpointer)) {
4495 /* Only one register, so avoid lea */
4496 for (i = AMD64_NREG - 1; i > 0; --i)
4497 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4498 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4502 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4504 /* Pop registers in reverse order */
4505 for (i = AMD64_NREG - 1; i > 0; --i)
4506 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4507 amd64_pop_reg (code, i);
4514 /* Load returned vtypes into registers if needed */
4515 cinfo = cfg->arch.cinfo;
4516 if (cinfo->ret.storage == ArgValuetypeInReg) {
4517 ArgInfo *ainfo = &cinfo->ret;
4518 MonoInst *inst = cfg->ret;
4520 for (quad = 0; quad < 2; quad ++) {
4521 switch (ainfo->pair_storage [quad]) {
4523 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4525 case ArgInFloatSSEReg:
4526 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4528 case ArgInDoubleSSEReg:
4529 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4534 g_assert_not_reached ();
4539 if (cfg->arch.omit_fp) {
4540 if (cfg->arch.stack_alloc_size)
4541 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4545 async_exc_point (code);
4548 cfg->code_len = code - cfg->native_code;
4550 g_assert (cfg->code_len < cfg->code_size);
4552 if (cfg->arch.omit_fp) {
4554 * Encode the stack size into used_int_regs so the exception handler
4557 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4558 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4563 mono_arch_emit_exceptions (MonoCompile *cfg)
4565 MonoJumpInfo *patch_info;
4568 MonoClass *exc_classes [16];
4569 guint8 *exc_throw_start [16], *exc_throw_end [16];
4570 guint32 code_size = 0;
4572 /* Compute needed space */
4573 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4574 if (patch_info->type == MONO_PATCH_INFO_EXC)
4576 if (patch_info->type == MONO_PATCH_INFO_R8)
4577 code_size += 8 + 15; /* sizeof (double) + alignment */
4578 if (patch_info->type == MONO_PATCH_INFO_R4)
4579 code_size += 4 + 15; /* sizeof (float) + alignment */
4582 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4583 cfg->code_size *= 2;
4584 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4585 mono_jit_stats.code_reallocs++;
4588 code = cfg->native_code + cfg->code_len;
4590 /* add code to raise exceptions */
4592 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4593 switch (patch_info->type) {
4594 case MONO_PATCH_INFO_EXC: {
4595 MonoClass *exc_class;
4599 amd64_patch (patch_info->ip.i + cfg->native_code, code);
4601 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4602 g_assert (exc_class);
4603 throw_ip = patch_info->ip.i;
4605 //x86_breakpoint (code);
4606 /* Find a throw sequence for the same exception class */
4607 for (i = 0; i < nthrows; ++i)
4608 if (exc_classes [i] == exc_class)
4611 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4612 x86_jump_code (code, exc_throw_start [i]);
4613 patch_info->type = MONO_PATCH_INFO_NONE;
4617 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
4621 exc_classes [nthrows] = exc_class;
4622 exc_throw_start [nthrows] = code;
4624 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
4626 patch_info->type = MONO_PATCH_INFO_NONE;
4628 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
4630 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
4635 exc_throw_end [nthrows] = code;
4647 /* Handle relocations with RIP relative addressing */
4648 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4649 gboolean remove = FALSE;
4651 switch (patch_info->type) {
4652 case MONO_PATCH_INFO_R8:
4653 case MONO_PATCH_INFO_R4: {
4656 /* The SSE opcodes require a 16 byte alignment */
4657 code = (guint8*)ALIGN_TO (code, 16);
4659 pos = cfg->native_code + patch_info->ip.i;
4661 if (IS_REX (pos [1]))
4662 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
4664 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4666 if (patch_info->type == MONO_PATCH_INFO_R8) {
4667 *(double*)code = *(double*)patch_info->data.target;
4668 code += sizeof (double);
4670 *(float*)code = *(float*)patch_info->data.target;
4671 code += sizeof (float);
4682 if (patch_info == cfg->patch_info)
4683 cfg->patch_info = patch_info->next;
4687 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4689 tmp->next = patch_info->next;
4694 cfg->code_len = code - cfg->native_code;
4696 g_assert (cfg->code_len < cfg->code_size);
4701 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4704 CallInfo *cinfo = NULL;
4705 MonoMethodSignature *sig;
4707 int i, n, stack_area = 0;
4709 /* Keep this in sync with mono_arch_get_argument_info */
4711 if (enable_arguments) {
4712 /* Allocate a new area on the stack and save arguments there */
4713 sig = mono_method_signature (cfg->method);
4715 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
4717 n = sig->param_count + sig->hasthis;
4719 stack_area = ALIGN_TO (n * 8, 16);
4721 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4723 for (i = 0; i < n; ++i) {
4724 inst = cfg->args [i];
4726 if (inst->opcode == OP_REGVAR)
4727 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4729 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4730 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4735 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4736 amd64_set_reg_template (code, AMD64_ARG_REG1);
4737 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
4738 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
4740 if (enable_arguments)
4741 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4755 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4758 int save_mode = SAVE_NONE;
4759 MonoMethod *method = cfg->method;
4760 int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4763 case MONO_TYPE_VOID:
4764 /* special case string .ctor icall */
4765 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4766 save_mode = SAVE_EAX;
4768 save_mode = SAVE_NONE;
4772 save_mode = SAVE_EAX;
4776 save_mode = SAVE_XMM;
4778 case MONO_TYPE_GENERICINST:
4779 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
4780 save_mode = SAVE_EAX;
4784 case MONO_TYPE_VALUETYPE:
4785 save_mode = SAVE_STRUCT;
4788 save_mode = SAVE_EAX;
4792 /* Save the result and copy it into the proper argument register */
4793 switch (save_mode) {
4795 amd64_push_reg (code, AMD64_RAX);
4797 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4798 if (enable_arguments)
4799 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
4803 if (enable_arguments)
4804 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
4807 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4808 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4810 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4812 * The result is already in the proper argument register so no copying
4819 g_assert_not_reached ();
4822 /* Set %al since this is a varargs call */
4823 if (save_mode == SAVE_XMM)
4824 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4826 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4828 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4829 amd64_set_reg_template (code, AMD64_ARG_REG1);
4830 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
4832 /* Restore result */
4833 switch (save_mode) {
4835 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4836 amd64_pop_reg (code, AMD64_RAX);
4842 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4843 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4844 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4849 g_assert_not_reached ();
4856 mono_arch_flush_icache (guint8 *code, gint size)
4862 mono_arch_flush_register_windows (void)
4867 mono_arch_is_inst_imm (gint64 imm)
4869 return amd64_is_imm32 (imm);
4873 * Determine whenever the trap whose info is in SIGINFO is caused by
4877 mono_arch_is_int_overflow (void *sigctx, void *info)
4884 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
4886 rip = (guint8*)ctx.rip;
4888 if (IS_REX (rip [0])) {
4889 reg = amd64_rex_b (rip [0]);
4895 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4897 reg += x86_modrm_rm (rip [1]);
4937 g_assert_not_reached ();
4949 mono_arch_get_patch_offset (guint8 *code)
4955 * mono_breakpoint_clean_code:
4957 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
4958 * breakpoints in the original code, they are removed in the copy.
4960 * Returns TRUE if no sw breakpoint was present.
4963 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
4966 gboolean can_write = TRUE;
4968 * If method_start is non-NULL we need to perform bound checks, since we access memory
4969 * at code - offset we could go before the start of the method and end up in a different
4970 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
4973 if (!method_start || code - offset >= method_start) {
4974 memcpy (buf, code - offset, size);
4976 int diff = code - method_start;
4977 memset (buf, 0, size);
4978 memcpy (buf + offset - diff, method_start, diff + size - offset);
4981 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
4982 int idx = mono_breakpoint_info_index [i];
4986 ptr = mono_breakpoint_info [idx].address;
4987 if (ptr >= code && ptr < code + size) {
4988 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
4990 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
4991 buf [ptr - code] = saved_byte;
4998 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5005 mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5010 /* go to the start of the call instruction
5012 * address_byte = (m << 6) | (o << 3) | reg
5013 * call opcode: 0xff address_byte displacement
5015 * 0xff m=2,o=2 imm32
5020 * A given byte sequence can match more than case here, so we have to be
5021 * really careful about the ordering of the cases. Longer sequences
5024 #ifdef MONO_ARCH_HAVE_IMT
5025 if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5026 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5027 * 41 bb 14 f8 28 08 mov $0x828f814,%r11d
5028 * ff 50 fc call *0xfffffffc(%rax)
5030 reg = amd64_modrm_rm (code [5]);
5031 disp = (signed char)code [6];
5032 /* R10 is clobbered by the IMT thunk code */
5033 g_assert (reg != AMD64_R10);
5039 else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5041 * This is a interface call
5042 * 48 8b 80 f0 e8 ff ff mov 0xffffffffffffe8f0(%rax),%rax
5043 * ff 10 callq *(%rax)
5045 if (IS_REX (code [4]))
5047 reg = amd64_modrm_rm (code [6]);
5049 /* R10 is clobbered by the IMT thunk code */
5050 g_assert (reg != AMD64_R10);
5051 } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5052 /* call OFFSET(%rip) */
5053 disp = *(guint32*)(code + 3);
5054 return (gpointer*)(code + disp + 7);
5056 else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5057 /* call *[reg+disp32] */
5058 if (IS_REX (code [0]))
5060 reg = amd64_modrm_rm (code [2]);
5061 disp = *(gint32*)(code + 3);
5062 /* R10 is clobbered by the IMT thunk code */
5063 g_assert (reg != AMD64_R10);
5065 else if (code [2] == 0xe8) {
5069 else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5073 else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5074 /* call *[reg+disp8] */
5075 if (IS_REX (code [3]))
5077 reg = amd64_modrm_rm (code [5]);
5078 disp = *(gint8*)(code + 6);
5079 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5081 else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5083 * This is a interface call: should check the above code can't catch it earlier
5084 * 8b 40 30 mov 0x30(%eax),%eax
5085 * ff 10 call *(%eax)
5087 if (IS_REX (code [4]))
5089 reg = amd64_modrm_rm (code [6]);
5093 g_assert_not_reached ();
5095 reg += amd64_rex_b (rex);
5097 /* R11 is clobbered by the trampoline code */
5098 g_assert (reg != AMD64_R11);
5100 *displacement = disp;
5105 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5109 vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5112 return (gpointer*)((char*)vt + displacement);
5116 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx)
5118 int this_reg = AMD64_ARG_REG1;
5120 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
5121 CallInfo *cinfo = get_call_info (gsctx, NULL, sig, FALSE);
5123 if (cinfo->ret.storage != ArgValuetypeInReg)
5124 this_reg = AMD64_ARG_REG2;
5132 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
5134 return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx)];
5137 #define MAX_ARCH_DELEGATE_PARAMS 10
5140 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
5142 guint8 *code, *start;
5145 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
5148 /* FIXME: Support more cases */
5149 if (MONO_TYPE_ISSTRUCT (sig->ret))
5153 static guint8* cached = NULL;
5154 mono_mini_arch_lock ();
5156 mono_mini_arch_unlock ();
5160 start = code = mono_global_codeman_reserve (64);
5162 /* Replace the this argument with the target */
5163 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5164 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
5165 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5167 g_assert ((code - start) < 64);
5170 mono_debug_add_delegate_trampoline (start, code - start);
5171 mono_mini_arch_unlock ();
5173 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
5174 for (i = 0; i < sig->param_count; ++i)
5175 if (!mono_is_regsize_var (sig->params [i]))
5177 if (sig->param_count > 4)
5180 mono_mini_arch_lock ();
5181 code = cache [sig->param_count];
5183 mono_mini_arch_unlock ();
5187 start = code = mono_global_codeman_reserve (64);
5189 if (sig->param_count == 0) {
5190 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5192 /* We have to shift the arguments left */
5193 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
5194 for (i = 0; i < sig->param_count; ++i)
5195 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
5197 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
5199 g_assert ((code - start) < 64);
5201 cache [sig->param_count] = start;
5203 mono_debug_add_delegate_trampoline (start, code - start);
5204 mono_mini_arch_unlock ();
5211 * Support for fast access to the thread-local lmf structure using the GS
5212 * segment register on NPTL + kernel 2.6.x.
5215 static gboolean tls_offset_inited = FALSE;
5218 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5220 if (!tls_offset_inited) {
5221 tls_offset_inited = TRUE;
5223 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5225 appdomain_tls_offset = mono_domain_get_tls_offset ();
5226 lmf_tls_offset = mono_get_lmf_tls_offset ();
5227 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5228 thread_tls_offset = mono_thread_get_tls_offset ();
5233 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5238 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5240 MonoCallInst *call = (MonoCallInst*)inst;
5241 CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
5246 if (cinfo->ret.storage == ArgValuetypeInReg) {
5248 * The valuetype is in RAX:RDX after the call, need to be copied to
5249 * the stack. Push the address here, so the call instruction can
5252 MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5253 vtarg->sreg1 = vt_reg;
5254 mono_bblock_add_inst (cfg->cbb, vtarg);
5257 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5260 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
5261 vtarg->sreg1 = vt_reg;
5262 vtarg->dreg = mono_regstate_next_int (cfg->rs);
5263 mono_bblock_add_inst (cfg->cbb, vtarg);
5265 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
5269 /* add the this argument */
5270 if (this_reg != -1) {
5272 MONO_INST_NEW (cfg, this, OP_MOVE);
5273 this->type = this_type;
5274 this->sreg1 = this_reg;
5275 this->dreg = mono_regstate_next_int (cfg->rs);
5276 mono_bblock_add_inst (cfg->cbb, this);
5278 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
5282 #ifdef MONO_ARCH_HAVE_IMT
5284 #define CMP_SIZE (6 + 1)
5285 #define CMP_REG_REG_SIZE (4 + 1)
5286 #define BR_SMALL_SIZE 2
5287 #define BR_LARGE_SIZE 6
5288 #define MOV_REG_IMM_SIZE 10
5289 #define MOV_REG_IMM_32BIT_SIZE 6
5290 #define JUMP_REG_SIZE (2 + 1)
5293 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
5295 int i, distance = 0;
5296 for (i = start; i < target; ++i)
5297 distance += imt_entries [i]->chunk_size;
5302 * LOCKING: called with the domain lock held
5305 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count)
5309 guint8 *code, *start;
5310 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
5312 for (i = 0; i < count; ++i) {
5313 MonoIMTCheckItem *item = imt_entries [i];
5314 if (item->is_equals) {
5315 if (item->check_target_idx) {
5316 if (!item->compare_done) {
5317 if (amd64_is_imm32 (item->method))
5318 item->chunk_size += CMP_SIZE;
5320 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5322 if (vtable_is_32bit)
5323 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5325 item->chunk_size += MOV_REG_IMM_SIZE;
5326 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
5328 if (vtable_is_32bit)
5329 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
5331 item->chunk_size += MOV_REG_IMM_SIZE;
5332 item->chunk_size += JUMP_REG_SIZE;
5333 /* with assert below:
5334 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
5338 if (amd64_is_imm32 (item->method))
5339 item->chunk_size += CMP_SIZE;
5341 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
5342 item->chunk_size += BR_LARGE_SIZE;
5343 imt_entries [item->check_target_idx]->compare_done = TRUE;
5345 size += item->chunk_size;
5347 code = mono_code_manager_reserve (domain->code_mp, size);
5349 for (i = 0; i < count; ++i) {
5350 MonoIMTCheckItem *item = imt_entries [i];
5351 item->code_target = code;
5352 if (item->is_equals) {
5353 if (item->check_target_idx) {
5354 if (!item->compare_done) {
5355 if (amd64_is_imm32 (item->method))
5356 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5358 amd64_mov_reg_imm (code, AMD64_R10, item->method);
5359 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5362 item->jmp_code = code;
5363 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5364 /* See the comment below about R10 */
5365 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
5366 amd64_jump_membase (code, AMD64_R10, 0);
5368 /* enable the commented code to assert on wrong method */
5370 if (amd64_is_imm32 (item->method))
5371 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5373 amd64_mov_reg_imm (code, AMD64_R10, item->method);
5374 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5376 item->jmp_code = code;
5377 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
5378 /* See the comment below about R10 */
5379 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
5380 amd64_jump_membase (code, AMD64_R10, 0);
5381 amd64_patch (item->jmp_code, code);
5382 amd64_breakpoint (code);
5383 item->jmp_code = NULL;
5385 /* We're using R10 here because R11
5386 needs to be preserved. R10 needs
5387 to be preserved for calls which
5388 require a runtime generic context,
5389 but interface calls don't. */
5390 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
5391 amd64_jump_membase (code, AMD64_R10, 0);
5395 if (amd64_is_imm32 (item->method))
5396 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
5398 amd64_mov_reg_imm (code, AMD64_R10, item->method);
5399 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
5401 item->jmp_code = code;
5402 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
5403 x86_branch8 (code, X86_CC_GE, 0, FALSE);
5405 x86_branch32 (code, X86_CC_GE, 0, FALSE);
5407 g_assert (code - item->code_target <= item->chunk_size);
5409 /* patch the branches to get to the target items */
5410 for (i = 0; i < count; ++i) {
5411 MonoIMTCheckItem *item = imt_entries [i];
5412 if (item->jmp_code) {
5413 if (item->check_target_idx) {
5414 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
5419 mono_stats.imt_thunks_size += code - start;
5420 g_assert (code - start <= size);
5426 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
5428 return regs [MONO_ARCH_IMT_REG];
5432 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
5434 return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
5439 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
5441 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
5445 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5447 MonoInst *ins = NULL;
5449 if (cmethod->klass == mono_defaults.math_class) {
5450 if (strcmp (cmethod->name, "Sin") == 0) {
5451 MONO_INST_NEW (cfg, ins, OP_SIN);
5452 ins->inst_i0 = args [0];
5453 } else if (strcmp (cmethod->name, "Cos") == 0) {
5454 MONO_INST_NEW (cfg, ins, OP_COS);
5455 ins->inst_i0 = args [0];
5456 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5457 MONO_INST_NEW (cfg, ins, OP_SQRT);
5458 ins->inst_i0 = args [0];
5459 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5460 MONO_INST_NEW (cfg, ins, OP_ABS);
5461 ins->inst_i0 = args [0];
5464 if (cfg->opt & MONO_OPT_CMOV) {
5467 if (strcmp (cmethod->name, "Min") == 0) {
5468 if (fsig->params [0]->type == MONO_TYPE_I4)
5470 if (fsig->params [0]->type == MONO_TYPE_U4)
5471 opcode = OP_IMIN_UN;
5472 else if (fsig->params [0]->type == MONO_TYPE_I8)
5474 else if (fsig->params [0]->type == MONO_TYPE_U8)
5475 opcode = OP_LMIN_UN;
5476 } else if (strcmp (cmethod->name, "Max") == 0) {
5477 if (fsig->params [0]->type == MONO_TYPE_I4)
5479 if (fsig->params [0]->type == MONO_TYPE_U4)
5480 opcode = OP_IMAX_UN;
5481 else if (fsig->params [0]->type == MONO_TYPE_I8)
5483 else if (fsig->params [0]->type == MONO_TYPE_U8)
5484 opcode = OP_LMAX_UN;
5488 MONO_INST_NEW (cfg, ins, opcode);
5489 ins->inst_i0 = args [0];
5490 ins->inst_i1 = args [1];
5495 /* OP_FREM is not IEEE compatible */
5496 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5497 MONO_INST_NEW (cfg, ins, OP_FREM);
5498 ins->inst_i0 = args [0];
5499 ins->inst_i1 = args [1];
5508 mono_arch_print_tree (MonoInst *tree, int arity)
5513 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5517 if (appdomain_tls_offset == -1)
5520 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5521 ins->inst_offset = appdomain_tls_offset;
5525 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5529 if (thread_tls_offset == -1)
5532 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5533 ins->inst_offset = thread_tls_offset;
5537 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
5540 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
5543 case AMD64_RCX: return (gpointer)ctx->rcx;
5544 case AMD64_RDX: return (gpointer)ctx->rdx;
5545 case AMD64_RBX: return (gpointer)ctx->rbx;
5546 case AMD64_RBP: return (gpointer)ctx->rbp;
5547 case AMD64_RSP: return (gpointer)ctx->rsp;
5550 return _CTX_REG (ctx, rax, reg);
5552 return _CTX_REG (ctx, r12, reg - 12);
5554 g_assert_not_reached ();