mono/mini/mini-amd64.c

   1 /**
   2  * \file
   3  * AMD64 backend for the Mono code generator
   4  *
   5  * Based on mini-x86.c.
   6  *
   7  * Authors:
   8  *   Paolo Molaro (lupus@ximian.com)
   9  *   Dietmar Maurer (dietmar@ximian.com)
  10  *   Patrik Torstensson
  11  *   Zoltan Varga (vargaz@gmail.com)
  12  *   Johan Lorensson (lateralusx.github@gmail.com)
  13  *
  14  * (C) 2003 Ximian, Inc.
  15  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  16  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  17  * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  18  */
  19 #include "mini.h"
  20 #include <string.h>
  21 #include <math.h>
  22 #include <assert.h>
  23 #ifdef HAVE_UNISTD_H
  24 #include <unistd.h>
  25 #endif
  26
  27 #include <mono/metadata/abi-details.h>
  28 #include <mono/metadata/appdomain.h>
  29 #include <mono/metadata/debug-helpers.h>
  30 #include <mono/metadata/threads.h>
  31 #include <mono/metadata/profiler-private.h>
  32 #include <mono/metadata/mono-debug.h>
  33 #include <mono/metadata/gc-internals.h>
  34 #include <mono/utils/mono-math.h>
  35 #include <mono/utils/mono-mmap.h>
  36 #include <mono/utils/mono-memory-model.h>
  37 #include <mono/utils/mono-tls.h>
  38 #include <mono/utils/mono-hwcap.h>
  39 #include <mono/utils/mono-threads.h>
  40
  41 #include "trace.h"
  42 #include "ir-emit.h"
  43 #include "mini-amd64.h"
  44 #include "cpu-amd64.h"
  45 #include "debugger-agent.h"
  46 #include "mini-gc.h"
  47
  48 #ifdef MONO_XEN_OPT
  49 static gboolean optimize_for_xen = TRUE;
  50 #else
  51 #define optimize_for_xen 0
  52 #endif
  53
  54 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  55
  56 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  57
  58 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  59
  60 #ifdef TARGET_WIN32
  61 /* Under windows, the calling convention is never stdcall */
  62 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  63 #else
  64 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  65 #endif
  66
  67 /* This mutex protects architecture specific caches */
  68 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  69 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  70 static mono_mutex_t mini_arch_mutex;
  71
  72 /* The single step trampoline */
  73 static gpointer ss_trampoline;
  74
  75 /* The breakpoint trampoline */
  76 static gpointer bp_trampoline;
  77
  78 /* Offset between fp and the first argument in the callee */
  79 #define ARGS_OFFSET 16
  80 #define GP_SCRATCH_REG AMD64_R11
  81
  82 /*
  83  * AMD64 register usage:
  84  * - callee saved registers are used for global register allocation
  85  * - %r11 is used for materializing 64 bit constants in opcodes
  86  * - the rest is used for local allocation
  87  */
  88
  89 /*
  90  * Floating point comparison results:
  91  *                  ZF PF CF
  92  * A > B            0  0  0
  93  * A < B            0  0  1
  94  * A = B            1  0  0
  95  * A > B            0  0  0
  96  * UNORDERED        1  1  1
  97  */
  98
  99 const char*
 100 mono_arch_regname (int reg)
 101 {
 102         switch (reg) {
 103         case AMD64_RAX: return "%rax";
 104         case AMD64_RBX: return "%rbx";
 105         case AMD64_RCX: return "%rcx";
 106         case AMD64_RDX: return "%rdx";
 107         case AMD64_RSP: return "%rsp";
 108         case AMD64_RBP: return "%rbp";
 109         case AMD64_RDI: return "%rdi";
 110         case AMD64_RSI: return "%rsi";
 111         case AMD64_R8: return "%r8";
 112         case AMD64_R9: return "%r9";
 113         case AMD64_R10: return "%r10";
 114         case AMD64_R11: return "%r11";
 115         case AMD64_R12: return "%r12";
 116         case AMD64_R13: return "%r13";
 117         case AMD64_R14: return "%r14";
 118         case AMD64_R15: return "%r15";
 119         }
 120         return "unknown";
 121 }
 122
 123 static const char * packed_xmmregs [] = {
 124         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 125         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 126 };
 127
 128 static const char * single_xmmregs [] = {
 129         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 130         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 131 };
 132
 133 const char*
 134 mono_arch_fregname (int reg)
 135 {
 136         if (reg < AMD64_XMM_NREG)
 137                 return single_xmmregs [reg];
 138         else
 139                 return "unknown";
 140 }
 141
 142 const char *
 143 mono_arch_xregname (int reg)
 144 {
 145         if (reg < AMD64_XMM_NREG)
 146                 return packed_xmmregs [reg];
 147         else
 148                 return "unknown";
 149 }
 150
 151 static gboolean
 152 debug_omit_fp (void)
 153 {
 154 #if 0
 155         return mono_debug_count ();
 156 #else
 157         return TRUE;
 158 #endif
 159 }
 160
 161 static inline gboolean
 162 amd64_is_near_call (guint8 *code)
 163 {
 164         /* Skip REX */
 165         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 166                 code += 1;
 167
 168         return code [0] == 0xe8;
 169 }
 170
 171 static inline gboolean
 172 amd64_use_imm32 (gint64 val)
 173 {
 174         if (mini_get_debug_options()->single_imm_size)
 175                 return FALSE;
 176
 177         return amd64_is_imm32 (val);
 178 }
 179
 180 static void
 181 amd64_patch (unsigned char* code, gpointer target)
 182 {
 183         guint8 rex = 0;
 184
 185         /* Skip REX */
 186         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 187                 rex = code [0];
 188                 code += 1;
 189         }
 190
 191         if ((code [0] & 0xf8) == 0xb8) {
 192                 /* amd64_set_reg_template */
 193                 *(guint64*)(code + 1) = (guint64)target;
 194         }
 195         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 196                 /* mov 0(%rip), %dreg */
 197                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 198         }
 199         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 200                 /* call *<OFFSET>(%rip) */
 201                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 202         }
 203         else if (code [0] == 0xe8) {
 204                 /* call <DISP> */
 205                 gint64 disp = (guint8*)target - (guint8*)code;
 206                 g_assert (amd64_is_imm32 (disp));
 207                 x86_patch (code, (unsigned char*)target);
 208         }
 209         else
 210                 x86_patch (code, (unsigned char*)target);
 211 }
 212
 213 void
 214 mono_amd64_patch (unsigned char* code, gpointer target)
 215 {
 216         amd64_patch (code, target);
 217 }
 218
 219 #define DEBUG(a) if (cfg->verbose_level > 1) a
 220
 221 static void inline
 222 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 223 {
 224     ainfo->offset = *stack_size;
 225
 226     if (*gr >= PARAM_REGS) {
 227                 ainfo->storage = ArgOnStack;
 228                 ainfo->arg_size = sizeof (mgreg_t);
 229                 /* Since the same stack slot size is used for all arg */
 230                 /*  types, it needs to be big enough to hold them all */
 231                 (*stack_size) += sizeof(mgreg_t);
 232     }
 233     else {
 234                 ainfo->storage = ArgInIReg;
 235                 ainfo->reg = param_regs [*gr];
 236                 (*gr) ++;
 237     }
 238 }
 239
 240 static void inline
 241 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 242 {
 243     ainfo->offset = *stack_size;
 244
 245     if (*gr >= FLOAT_PARAM_REGS) {
 246                 ainfo->storage = ArgOnStack;
 247                 ainfo->arg_size = sizeof (mgreg_t);
 248                 /* Since the same stack slot size is used for both float */
 249                 /*  types, it needs to be big enough to hold them both */
 250                 (*stack_size) += sizeof(mgreg_t);
 251     }
 252     else {
 253                 /* A double register */
 254                 if (is_double)
 255                         ainfo->storage = ArgInDoubleSSEReg;
 256                 else
 257                         ainfo->storage = ArgInFloatSSEReg;
 258                 ainfo->reg = *gr;
 259                 (*gr) += 1;
 260     }
 261 }
 262
 263 typedef enum ArgumentClass {
 264         ARG_CLASS_NO_CLASS,
 265         ARG_CLASS_MEMORY,
 266         ARG_CLASS_INTEGER,
 267         ARG_CLASS_SSE
 268 } ArgumentClass;
 269
 270 static ArgumentClass
 271 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 272 {
 273         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 274         MonoType *ptype;
 275
 276         ptype = mini_get_underlying_type (type);
 277         switch (ptype->type) {
 278         case MONO_TYPE_I1:
 279         case MONO_TYPE_U1:
 280         case MONO_TYPE_I2:
 281         case MONO_TYPE_U2:
 282         case MONO_TYPE_I4:
 283         case MONO_TYPE_U4:
 284         case MONO_TYPE_I:
 285         case MONO_TYPE_U:
 286         case MONO_TYPE_OBJECT:
 287         case MONO_TYPE_PTR:
 288         case MONO_TYPE_FNPTR:
 289         case MONO_TYPE_I8:
 290         case MONO_TYPE_U8:
 291                 class2 = ARG_CLASS_INTEGER;
 292                 break;
 293         case MONO_TYPE_R4:
 294         case MONO_TYPE_R8:
 295 #ifdef TARGET_WIN32
 296                 class2 = ARG_CLASS_INTEGER;
 297 #else
 298                 class2 = ARG_CLASS_SSE;
 299 #endif
 300                 break;
 301
 302         case MONO_TYPE_TYPEDBYREF:
 303                 g_assert_not_reached ();
 304
 305         case MONO_TYPE_GENERICINST:
 306                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 307                         class2 = ARG_CLASS_INTEGER;
 308                         break;
 309                 }
 310                 /* fall through */
 311         case MONO_TYPE_VALUETYPE: {
 312                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 313                 int i;
 314
 315                 for (i = 0; i < info->num_fields; ++i) {
 316                         class2 = class1;
 317                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 318                 }
 319                 break;
 320         }
 321         default:
 322                 g_assert_not_reached ();
 323         }
 324
 325         /* Merge */
 326         if (class1 == class2)
 327                 ;
 328         else if (class1 == ARG_CLASS_NO_CLASS)
 329                 class1 = class2;
 330         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 331                 class1 = ARG_CLASS_MEMORY;
 332         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 333                 class1 = ARG_CLASS_INTEGER;
 334         else
 335                 class1 = ARG_CLASS_SSE;
 336
 337         return class1;
 338 }
 339
 340 typedef struct {
 341         MonoType *type;
 342         int size, offset;
 343 } StructFieldInfo;
 344
 345 /*
 346  * collect_field_info_nested:
 347  *
 348  *   Collect field info from KLASS recursively into FIELDS.
 349  */
 350 static void
 351 collect_field_info_nested (MonoClass *klass, GArray *fields_array, int offset, gboolean pinvoke, gboolean unicode)
 352 {
 353         MonoMarshalType *info;
 354         int i;
 355
 356         if (pinvoke) {
 357                 info = mono_marshal_load_type_info (klass);
 358                 g_assert(info);
 359                 for (i = 0; i < info->num_fields; ++i) {
 360                         if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 361                                 collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields_array, info->fields [i].offset, pinvoke, unicode);
 362                         } else {
 363                                 guint32 align;
 364                                 StructFieldInfo f;
 365
 366                                 f.type = info->fields [i].field->type;
 367                                 f.size = mono_marshal_type_size (info->fields [i].field->type,
 368                                                                                                                            info->fields [i].mspec,
 369                                                                                                                            &align, TRUE, unicode);
 370                                 f.offset = offset + info->fields [i].offset;
 371                                 if (i == info->num_fields - 1 && f.size + f.offset < info->native_size) {
 372                                         /* This can happen with .pack directives eg. 'fixed' arrays */
 373                                         if (MONO_TYPE_IS_PRIMITIVE (f.type)) {
 374                                                 /* Replicate the last field to fill out the remaining place, since the code in add_valuetype () needs type information */
 375                                                 g_array_append_val (fields_array, f);
 376                                                 while (f.size + f.offset < info->native_size) {
 377                                                         f.offset += f.size;
 378                                                         g_array_append_val (fields_array, f);
 379                                                 }
 380                                         } else {
 381                                                 f.size = info->native_size - f.offset;
 382                                                 g_array_append_val (fields_array, f);
 383                                         }
 384                                 } else {
 385                                         g_array_append_val (fields_array, f);
 386                                 }
 387                         }
 388                 }
 389         } else {
 390                 gpointer iter;
 391                 MonoClassField *field;
 392
 393                 iter = NULL;
 394                 while ((field = mono_class_get_fields (klass, &iter))) {
 395                         if (field->type->attrs & FIELD_ATTRIBUTE_STATIC)
 396                                 continue;
 397                         if (MONO_TYPE_ISSTRUCT (field->type)) {
 398                                 collect_field_info_nested (mono_class_from_mono_type (field->type), fields_array, field->offset - sizeof (MonoObject), pinvoke, unicode);
 399                         } else {
 400                                 int align;
 401                                 StructFieldInfo f;
 402
 403                                 f.type = field->type;
 404                                 f.size = mono_type_size (field->type, &align);
 405                                 f.offset = field->offset - sizeof (MonoObject) + offset;
 406
 407                                 g_array_append_val (fields_array, f);
 408                         }
 409                 }
 410         }
 411 }
 412
 413 #ifdef TARGET_WIN32
 414
 415 /* Windows x64 ABI can pass/return value types in register of size 1,2,4,8 bytes. */
 416 #define MONO_WIN64_VALUE_TYPE_FITS_REG(arg_size) (arg_size <= SIZEOF_REGISTER && (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8))
 417
 418 static gboolean
 419 allocate_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, AMD64_Reg_No int_regs [], int int_reg_count, AMD64_XMM_Reg_No float_regs [], int float_reg_count, guint32 *current_int_reg, guint32 *current_float_reg)
 420 {
 421         gboolean result = FALSE;
 422
 423         assert (arg_info != NULL && int_regs != NULL && float_regs != NULL && current_int_reg != NULL && current_float_reg != NULL);
 424         assert (arg_info->storage == ArgValuetypeInReg || arg_info->storage == ArgValuetypeAddrInIReg);
 425
 426         arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 427         arg_info->pair_regs [0] = arg_info->pair_regs [1] = ArgNone;
 428         arg_info->pair_size [0] = 0;
 429         arg_info->pair_size [1] = 0;
 430         arg_info->nregs = 0;
 431
 432         if (arg_class == ARG_CLASS_INTEGER && *current_int_reg < int_reg_count) {
 433                 /* Pass parameter in integer register. */
 434                 arg_info->pair_storage [0] = ArgInIReg;
 435                 arg_info->pair_regs [0] = int_regs [*current_int_reg];
 436                 (*current_int_reg) ++;
 437                 result = TRUE;
 438         } else if (arg_class == ARG_CLASS_SSE && *current_float_reg < float_reg_count) {
 439                 /* Pass parameter in float register. */
 440                 arg_info->pair_storage [0] = (arg_size <= sizeof (gfloat)) ? ArgInFloatSSEReg : ArgInDoubleSSEReg;
 441                 arg_info->pair_regs [0] = float_regs [*current_float_reg];
 442                 (*current_float_reg) ++;
 443                 result = TRUE;
 444         }
 445
 446         if (result == TRUE) {
 447                 arg_info->pair_size [0] = arg_size;
 448                 arg_info->nregs = 1;
 449         }
 450
 451         return result;
 452 }
 453
 454 static inline gboolean
 455 allocate_parameter_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 456 {
 457         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, param_regs, PARAM_REGS, float_param_regs, FLOAT_PARAM_REGS, current_int_reg, current_float_reg);
 458 }
 459
 460 static inline gboolean
 461 allocate_return_register_for_valuetype_win64 (ArgInfo *arg_info, ArgumentClass arg_class, guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg)
 462 {
 463         return allocate_register_for_valuetype_win64 (arg_info, arg_class, arg_size, return_regs, RETURN_REGS, float_return_regs, FLOAT_RETURN_REGS, current_int_reg, current_float_reg);
 464 }
 465
 466 static void
 467 allocate_storage_for_valuetype_win64 (ArgInfo *arg_info, MonoType *type, gboolean is_return, ArgumentClass arg_class,
 468                                                                           guint32 arg_size, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 469 {
 470         /* Windows x64 value type ABI.
 471         *
 472         * Parameters: https://msdn.microsoft.com/en-us/library/zthk2dkh.aspx
 473         *
 474         * Integer/Float types smaller than or equals to 8 bytes or porperly sized struct/union (1,2,4,8)
 475         *    Try pass in register using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8), if no more registers, pass on stack using ArgOnStack as storage and size of parameter(1,2,4,8).
 476         * Integer/Float types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 477         *    Try to pass pointer in register using ArgValuetypeAddrInIReg, if no more registers, pass pointer on stack using ArgValuetypeAddrOnStack as storage and parameter size of register (8 bytes).
 478         *
 479         * Return values:  https://msdn.microsoft.com/en-us/library/7572ztz4.aspx.
 480         *
 481         * Integers/Float types smaller than or equal to 8 bytes
 482         *    Return in corresponding register RAX/XMM0 using ArgValuetypeInReg/(ArgInIReg|ArgInFloatSSEReg|ArgInDoubleSSEReg) as storage and size of parameter(1,2,4,8).
 483         * Properly sized struct/unions (1,2,4,8)
 484         *    Return in register RAX using ArgValuetypeInReg as storage and size of parameter(1,2,4,8).
 485         * Types bigger than 8 bytes or struct/unions larger than 8 bytes or (3,5,6,7).
 486         *    Return pointer to allocated stack space (allocated by caller) using ArgValuetypeAddrInIReg as storage and parameter size.
 487         */
 488
 489         assert (arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 490
 491         if (!is_return) {
 492
 493                 /* Parameter cases. */
 494                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 495                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 496
 497                         /* First, try to use registers for parameter. If type is struct it can only be passed by value in integer register. */
 498                         arg_info->storage = ArgValuetypeInReg;
 499                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 500                                 /* No more registers, fallback passing parameter on stack as value. */
 501                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 502
 503                                 /* Passing value directly on stack, so use size of value. */
 504                                 arg_info->storage = ArgOnStack;
 505                                 arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 506                                 arg_info->offset = *stack_size;
 507                                 arg_info->arg_size = arg_size;
 508                                 *stack_size += arg_size;
 509                         }
 510                 } else {
 511                         /* Fallback to stack, try to pass address to parameter in register. Always use integer register to represent stack address. */
 512                         arg_info->storage = ArgValuetypeAddrInIReg;
 513                         if (!allocate_parameter_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg)) {
 514                                 /* No more registers, fallback passing address to parameter on stack. */
 515                                 assert (arg_info->pair_storage [0] == ArgNone && arg_info->pair_storage [1] == ArgNone && arg_info->pair_size [0] == 0 && arg_info->pair_size [1] == 0 && arg_info->nregs == 0);
 516
 517                                 /* Passing an address to value on stack, so use size of register as argument size. */
 518                                 arg_info->storage = ArgValuetypeAddrOnStack;
 519                                 arg_size = sizeof (mgreg_t);
 520                                 arg_info->offset = *stack_size;
 521                                 arg_info->arg_size = arg_size;
 522                                 *stack_size += arg_size;
 523                         }
 524                 }
 525         } else {
 526                 /* Return value cases. */
 527                 if (arg_class != ARG_CLASS_MEMORY && MONO_WIN64_VALUE_TYPE_FITS_REG (arg_size)) {
 528                         assert (arg_size == 1 || arg_size == 2 || arg_size == 4 || arg_size == 8);
 529
 530                         /* Return value fits into return registers. If type is struct it can only be returned by value in integer register. */
 531                         arg_info->storage = ArgValuetypeInReg;
 532                         allocate_return_register_for_valuetype_win64 (arg_info, !MONO_TYPE_ISSTRUCT (type) ? arg_class : ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 533
 534                         /* Only RAX/XMM0 should be used to return valuetype. */
 535                         assert ((arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone) || (arg_info->pair_regs[0] == AMD64_XMM0 && arg_info->pair_regs[1] == ArgNone));
 536                 } else {
 537                         /* Return value doesn't fit into return register, return address to allocated stack space (allocated by caller and passed as input). */
 538                         arg_info->storage = ArgValuetypeAddrInIReg;
 539                         allocate_return_register_for_valuetype_win64 (arg_info, ARG_CLASS_INTEGER, arg_size, current_int_reg, current_float_reg);
 540
 541                         /* Only RAX should be used to return valuetype address. */
 542                         assert (arg_info->pair_regs[0] == AMD64_RAX && arg_info->pair_regs[1] == ArgNone);
 543
 544                         arg_size = ALIGN_TO (arg_size, sizeof (mgreg_t));
 545                         arg_info->offset = *stack_size;
 546                         *stack_size += arg_size;
 547                 }
 548         }
 549 }
 550
 551 static void
 552 get_valuetype_size_win64 (MonoClass *klass, gboolean pinvoke, ArgInfo *arg_info, MonoType *type, ArgumentClass *arg_class, guint32 *arg_size)
 553 {
 554         *arg_size = 0;
 555         *arg_class = ARG_CLASS_NO_CLASS;
 556
 557         assert (klass != NULL && arg_info != NULL && type != NULL && arg_class != NULL && arg_size != NULL);
 558
 559         if (pinvoke) {
 560                 /* Calculate argument class type and size of marshalled type. */
 561                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 562                 *arg_size = info->native_size;
 563         } else {
 564                 /* Calculate argument class type and size of managed type. */
 565                 *arg_size = mono_class_value_size (klass, NULL);
 566         }
 567
 568         /* Windows ABI only handle value types on stack or passed in integer register (if it fits register size). */
 569         *arg_class = MONO_WIN64_VALUE_TYPE_FITS_REG (*arg_size) ? ARG_CLASS_INTEGER : ARG_CLASS_MEMORY;
 570
 571         if (*arg_class == ARG_CLASS_MEMORY) {
 572                 /* Value type has a size that doesn't seem to fit register according to ABI. Try to used full stack size of type. */
 573                 *arg_size = mini_type_stack_size_full (&klass->byval_arg, NULL, pinvoke);
 574         }
 575
 576         /*
 577         * Standard C and C++ doesn't allow empty structs, empty structs will always have a size of 1 byte.
 578         * GCC have an extension to allow empty structs, https://gcc.gnu.org/onlinedocs/gcc/Empty-Structures.html.
 579         * This cause a little dilemma since runtime build using none GCC compiler will not be compatible with
 580         * GCC build C libraries and the other way around. On platforms where empty structs has size of 1 byte
 581         * it must be represented in call and cannot be dropped.
 582         */
 583         if (*arg_size == 0 && MONO_TYPE_ISSTRUCT (type)) {
 584                 arg_info->pass_empty_struct = TRUE;
 585                 *arg_size = SIZEOF_REGISTER;
 586                 *arg_class = ARG_CLASS_INTEGER;
 587         }
 588
 589         assert (*arg_class != ARG_CLASS_NO_CLASS);
 590 }
 591
 592 static void
 593 add_valuetype_win64 (MonoMethodSignature *signature, ArgInfo *arg_info, MonoType *type,
 594                                                 gboolean is_return, guint32 *current_int_reg, guint32 *current_float_reg, guint32 *stack_size)
 595 {
 596         guint32 arg_size = SIZEOF_REGISTER;
 597         MonoClass *klass = NULL;
 598         ArgumentClass arg_class;
 599
 600         assert (signature != NULL && arg_info != NULL && type != NULL && current_int_reg != NULL && current_float_reg != NULL && stack_size != NULL);
 601
 602         klass = mono_class_from_mono_type (type);
 603         get_valuetype_size_win64 (klass, signature->pinvoke, arg_info, type, &arg_class, &arg_size);
 604
 605         /* Only drop value type if its not an empty struct as input that must be represented in call */
 606         if ((arg_size == 0 && !arg_info->pass_empty_struct) || (arg_size == 0 && arg_info->pass_empty_struct && is_return)) {
 607                 arg_info->storage = ArgValuetypeInReg;
 608                 arg_info->pair_storage [0] = arg_info->pair_storage [1] = ArgNone;
 609         } else {
 610                 /* Alocate storage for value type. */
 611                 allocate_storage_for_valuetype_win64 (arg_info, type, is_return, arg_class, arg_size, current_int_reg, current_float_reg, stack_size);
 612         }
 613 }
 614
 615 #endif /* TARGET_WIN32 */
 616
 617 static void
 618 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 619                            gboolean is_return,
 620                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 621 {
 622 #ifdef TARGET_WIN32
 623         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 624 #else
 625         guint32 size, quad, nquads, i, nfields;
 626         /* Keep track of the size used in each quad so we can */
 627         /* use the right size when copying args/return vars.  */
 628         guint32 quadsize [2] = {8, 8};
 629         ArgumentClass args [2];
 630         StructFieldInfo *fields = NULL;
 631         GArray *fields_array;
 632         MonoClass *klass;
 633         gboolean pass_on_stack = FALSE;
 634         int struct_size;
 635
 636         klass = mono_class_from_mono_type (type);
 637         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 638
 639         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 640                 /* We pass and return vtypes of size 8 in a register */
 641         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 642                 pass_on_stack = TRUE;
 643         }
 644
 645         /* If this struct can't be split up naturally into 8-byte */
 646         /* chunks (registers), pass it on the stack.              */
 647         if (sig->pinvoke) {
 648                 MonoMarshalType *info = mono_marshal_load_type_info (klass);
 649                 g_assert (info);
 650                 struct_size = info->native_size;
 651         } else {
 652                 struct_size = mono_class_value_size (klass, NULL);
 653         }
 654         /*
 655          * Collect field information recursively to be able to
 656          * handle nested structures.
 657          */
 658         fields_array = g_array_new (FALSE, TRUE, sizeof (StructFieldInfo));
 659         collect_field_info_nested (klass, fields_array, 0, sig->pinvoke, klass->unicode);
 660         fields = (StructFieldInfo*)fields_array->data;
 661         nfields = fields_array->len;
 662
 663         for (i = 0; i < nfields; ++i) {
 664                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 665                         pass_on_stack = TRUE;
 666                         break;
 667                 }
 668         }
 669
 670         if (size == 0) {
 671                 ainfo->storage = ArgValuetypeInReg;
 672                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 673                 return;
 674         }
 675
 676         if (pass_on_stack) {
 677                 /* Allways pass in memory */
 678                 ainfo->offset = *stack_size;
 679                 *stack_size += ALIGN_TO (size, 8);
 680                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 681                 if (!is_return)
 682                         ainfo->arg_size = ALIGN_TO (size, 8);
 683
 684                 g_array_free (fields_array, TRUE);
 685                 return;
 686         }
 687
 688         if (size > 8)
 689                 nquads = 2;
 690         else
 691                 nquads = 1;
 692
 693         if (!sig->pinvoke) {
 694                 int n = mono_class_value_size (klass, NULL);
 695
 696                 quadsize [0] = n >= 8 ? 8 : n;
 697                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 698
 699                 /* Always pass in 1 or 2 integer registers */
 700                 args [0] = ARG_CLASS_INTEGER;
 701                 args [1] = ARG_CLASS_INTEGER;
 702                 /* Only the simplest cases are supported */
 703                 if (is_return && nquads != 1) {
 704                         args [0] = ARG_CLASS_MEMORY;
 705                         args [1] = ARG_CLASS_MEMORY;
 706                 }
 707         } else {
 708                 /*
 709                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 710                  * The X87 and SSEUP stuff is left out since there are no such types in
 711                  * the CLR.
 712                  */
 713                 if (!nfields) {
 714                         ainfo->storage = ArgValuetypeInReg;
 715                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 716                         return;
 717                 }
 718
 719                 if (struct_size > 16) {
 720                         ainfo->offset = *stack_size;
 721                         *stack_size += ALIGN_TO (struct_size, 8);
 722                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 723                         if (!is_return)
 724                                 ainfo->arg_size = ALIGN_TO (struct_size, 8);
 725
 726                         g_array_free (fields_array, TRUE);
 727                         return;
 728                 }
 729
 730                 args [0] = ARG_CLASS_NO_CLASS;
 731                 args [1] = ARG_CLASS_NO_CLASS;
 732                 for (quad = 0; quad < nquads; ++quad) {
 733                         ArgumentClass class1;
 734
 735                         if (nfields == 0)
 736                                 class1 = ARG_CLASS_MEMORY;
 737                         else
 738                                 class1 = ARG_CLASS_NO_CLASS;
 739                         for (i = 0; i < nfields; ++i) {
 740                                 if ((fields [i].offset < 8) && (fields [i].offset + fields [i].size) > 8) {
 741                                         /* Unaligned field */
 742                                         NOT_IMPLEMENTED;
 743                                 }
 744
 745                                 /* Skip fields in other quad */
 746                                 if ((quad == 0) && (fields [i].offset >= 8))
 747                                         continue;
 748                                 if ((quad == 1) && (fields [i].offset < 8))
 749                                         continue;
 750
 751                                 /* How far into this quad this data extends.*/
 752                                 /* (8 is size of quad) */
 753                                 quadsize [quad] = fields [i].offset + fields [i].size - (quad * 8);
 754
 755                                 class1 = merge_argument_class_from_type (fields [i].type, class1);
 756                         }
 757                         /* Empty structs have a nonzero size, causing this assert to be hit */
 758                         if (sig->pinvoke)
 759                                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 760                         args [quad] = class1;
 761                 }
 762         }
 763
 764         g_array_free (fields_array, TRUE);
 765
 766         /* Post merger cleanup */
 767         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 768                 args [0] = args [1] = ARG_CLASS_MEMORY;
 769
 770         /* Allocate registers */
 771         {
 772                 int orig_gr = *gr;
 773                 int orig_fr = *fr;
 774
 775                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
 776                         quadsize [0] ++;
 777                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
 778                         quadsize [1] ++;
 779
 780                 ainfo->storage = ArgValuetypeInReg;
 781                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 782                 g_assert (quadsize [0] <= 8);
 783                 g_assert (quadsize [1] <= 8);
 784                 ainfo->pair_size [0] = quadsize [0];
 785                 ainfo->pair_size [1] = quadsize [1];
 786                 ainfo->nregs = nquads;
 787                 for (quad = 0; quad < nquads; ++quad) {
 788                         switch (args [quad]) {
 789                         case ARG_CLASS_INTEGER:
 790                                 if (*gr >= PARAM_REGS)
 791                                         args [quad] = ARG_CLASS_MEMORY;
 792                                 else {
 793                                         ainfo->pair_storage [quad] = ArgInIReg;
 794                                         if (is_return)
 795                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 796                                         else
 797                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 798                                         (*gr) ++;
 799                                 }
 800                                 break;
 801                         case ARG_CLASS_SSE:
 802                                 if (*fr >= FLOAT_PARAM_REGS)
 803                                         args [quad] = ARG_CLASS_MEMORY;
 804                                 else {
 805                                         if (quadsize[quad] <= 4)
 806                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
 807                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 808                                         ainfo->pair_regs [quad] = *fr;
 809                                         (*fr) ++;
 810                                 }
 811                                 break;
 812                         case ARG_CLASS_MEMORY:
 813                                 break;
 814                         case ARG_CLASS_NO_CLASS:
 815                                 break;
 816                         default:
 817                                 g_assert_not_reached ();
 818                         }
 819                 }
 820
 821                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 822                         int arg_size;
 823                         /* Revert possible register assignments */
 824                         *gr = orig_gr;
 825                         *fr = orig_fr;
 826
 827                         ainfo->offset = *stack_size;
 828                         if (sig->pinvoke)
 829                                 arg_size = ALIGN_TO (struct_size, 8);
 830                         else
 831                                 arg_size = nquads * sizeof(mgreg_t);
 832                         *stack_size += arg_size;
 833                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 834                         if (!is_return)
 835                                 ainfo->arg_size = arg_size;
 836                 }
 837         }
 838 #endif /* !TARGET_WIN32 */
 839 }
 840
 841 /*
 842  * get_call_info:
 843  *
 844  * Obtain information about a call according to the calling convention.
 845  * For AMD64 System V, see the "System V ABI, x86-64 Architecture Processor Supplement
 846  * Draft Version 0.23" document for more information.
 847  * For AMD64 Windows, see "Overview of x64 Calling Conventions",
 848  * https://msdn.microsoft.com/en-us/library/ms235286.aspx
 849  */
 850 static CallInfo*
 851 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
 852 {
 853         guint32 i, gr, fr, pstart;
 854         MonoType *ret_type;
 855         int n = sig->hasthis + sig->param_count;
 856         guint32 stack_size = 0;
 857         CallInfo *cinfo;
 858         gboolean is_pinvoke = sig->pinvoke;
 859
 860         if (mp)
 861                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 862         else
 863                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 864
 865         cinfo->nargs = n;
 866         cinfo->gsharedvt = mini_is_gsharedvt_variable_signature (sig);
 867
 868         gr = 0;
 869         fr = 0;
 870
 871 #ifdef TARGET_WIN32
 872         /* Reserve space where the callee can save the argument registers */
 873         stack_size = 4 * sizeof (mgreg_t);
 874 #endif
 875
 876         /* return value */
 877         ret_type = mini_get_underlying_type (sig->ret);
 878         switch (ret_type->type) {
 879         case MONO_TYPE_I1:
 880         case MONO_TYPE_U1:
 881         case MONO_TYPE_I2:
 882         case MONO_TYPE_U2:
 883         case MONO_TYPE_I4:
 884         case MONO_TYPE_U4:
 885         case MONO_TYPE_I:
 886         case MONO_TYPE_U:
 887         case MONO_TYPE_PTR:
 888         case MONO_TYPE_FNPTR:
 889         case MONO_TYPE_OBJECT:
 890                 cinfo->ret.storage = ArgInIReg;
 891                 cinfo->ret.reg = AMD64_RAX;
 892                 break;
 893         case MONO_TYPE_U8:
 894         case MONO_TYPE_I8:
 895                 cinfo->ret.storage = ArgInIReg;
 896                 cinfo->ret.reg = AMD64_RAX;
 897                 break;
 898         case MONO_TYPE_R4:
 899                 cinfo->ret.storage = ArgInFloatSSEReg;
 900                 cinfo->ret.reg = AMD64_XMM0;
 901                 break;
 902         case MONO_TYPE_R8:
 903                 cinfo->ret.storage = ArgInDoubleSSEReg;
 904                 cinfo->ret.reg = AMD64_XMM0;
 905                 break;
 906         case MONO_TYPE_GENERICINST:
 907                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 908                         cinfo->ret.storage = ArgInIReg;
 909                         cinfo->ret.reg = AMD64_RAX;
 910                         break;
 911                 }
 912                 if (mini_is_gsharedvt_type (ret_type)) {
 913                         cinfo->ret.storage = ArgGsharedvtVariableInReg;
 914                         break;
 915                 }
 916                 /* fall through */
 917         case MONO_TYPE_VALUETYPE:
 918         case MONO_TYPE_TYPEDBYREF: {
 919                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 920
 921                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 922                 g_assert (cinfo->ret.storage != ArgInIReg);
 923                 break;
 924         }
 925         case MONO_TYPE_VAR:
 926         case MONO_TYPE_MVAR:
 927                 g_assert (mini_is_gsharedvt_type (ret_type));
 928                 cinfo->ret.storage = ArgGsharedvtVariableInReg;
 929                 break;
 930         case MONO_TYPE_VOID:
 931                 break;
 932         default:
 933                 g_error ("Can't handle as return value 0x%x", ret_type->type);
 934         }
 935
 936         pstart = 0;
 937         /*
 938          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 939          * the first argument, allowing 'this' to be always passed in the first arg reg.
 940          * Also do this if the first argument is a reference type, since virtual calls
 941          * are sometimes made using calli without sig->hasthis set, like in the delegate
 942          * invoke wrappers.
 943          */
 944         ArgStorage ret_storage = cinfo->ret.storage;
 945         if ((ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
 946                 if (sig->hasthis) {
 947                         add_general (&gr, &stack_size, cinfo->args + 0);
 948                 } else {
 949                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 950                         pstart = 1;
 951                 }
 952                 add_general (&gr, &stack_size, &cinfo->ret);
 953                 cinfo->ret.storage = ret_storage;
 954                 cinfo->vret_arg_index = 1;
 955         } else {
 956                 /* this */
 957                 if (sig->hasthis)
 958                         add_general (&gr, &stack_size, cinfo->args + 0);
 959
 960                 if (ret_storage == ArgValuetypeAddrInIReg || ret_storage == ArgGsharedvtVariableInReg) {
 961                         add_general (&gr, &stack_size, &cinfo->ret);
 962                         cinfo->ret.storage = ret_storage;
 963                 }
 964         }
 965
 966         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 967                 gr = PARAM_REGS;
 968                 fr = FLOAT_PARAM_REGS;
 969
 970                 /* Emit the signature cookie just before the implicit arguments */
 971                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 972         }
 973
 974         for (i = pstart; i < sig->param_count; ++i) {
 975                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 976                 MonoType *ptype;
 977
 978 #ifdef TARGET_WIN32
 979                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 980                 if (gr > fr)
 981                         fr = gr;
 982                 else if (fr > gr)
 983                         gr = fr;
 984 #endif
 985
 986                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 987                         /* We allways pass the sig cookie on the stack for simplicity */
 988                         /*
 989                          * Prevent implicit arguments + the sig cookie from being passed
 990                          * in registers.
 991                          */
 992                         gr = PARAM_REGS;
 993                         fr = FLOAT_PARAM_REGS;
 994
 995                         /* Emit the signature cookie just before the implicit arguments */
 996                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 997                 }
 998
 999                 ptype = mini_get_underlying_type (sig->params [i]);
1000                 switch (ptype->type) {
1001                 case MONO_TYPE_I1:
1002                 case MONO_TYPE_U1:
1003                         add_general (&gr, &stack_size, ainfo);
1004                         ainfo->byte_arg_size = 1;
1005                         break;
1006                 case MONO_TYPE_I2:
1007                 case MONO_TYPE_U2:
1008                         add_general (&gr, &stack_size, ainfo);
1009                         ainfo->byte_arg_size = 2;
1010                         break;
1011                 case MONO_TYPE_I4:
1012                 case MONO_TYPE_U4:
1013                         add_general (&gr, &stack_size, ainfo);
1014                         ainfo->byte_arg_size = 4;
1015                         break;
1016                 case MONO_TYPE_I:
1017                 case MONO_TYPE_U:
1018                 case MONO_TYPE_PTR:
1019                 case MONO_TYPE_FNPTR:
1020                 case MONO_TYPE_OBJECT:
1021                         add_general (&gr, &stack_size, ainfo);
1022                         break;
1023                 case MONO_TYPE_GENERICINST:
1024                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1025                                 add_general (&gr, &stack_size, ainfo);
1026                                 break;
1027                         }
1028                         if (mini_is_gsharedvt_variable_type (ptype)) {
1029                                 /* gsharedvt arguments are passed by ref */
1030                                 add_general (&gr, &stack_size, ainfo);
1031                                 if (ainfo->storage == ArgInIReg)
1032                                         ainfo->storage = ArgGSharedVtInReg;
1033                                 else
1034                                         ainfo->storage = ArgGSharedVtOnStack;
1035                                 break;
1036                         }
1037                         /* fall through */
1038                 case MONO_TYPE_VALUETYPE:
1039                 case MONO_TYPE_TYPEDBYREF:
1040                         add_valuetype (sig, ainfo, ptype, FALSE, &gr, &fr, &stack_size);
1041                         break;
1042                 case MONO_TYPE_U8:
1043
1044                 case MONO_TYPE_I8:
1045                         add_general (&gr, &stack_size, ainfo);
1046                         break;
1047                 case MONO_TYPE_R4:
1048                         add_float (&fr, &stack_size, ainfo, FALSE);
1049                         break;
1050                 case MONO_TYPE_R8:
1051                         add_float (&fr, &stack_size, ainfo, TRUE);
1052                         break;
1053                 case MONO_TYPE_VAR:
1054                 case MONO_TYPE_MVAR:
1055                         /* gsharedvt arguments are passed by ref */
1056                         g_assert (mini_is_gsharedvt_type (ptype));
1057                         add_general (&gr, &stack_size, ainfo);
1058                         if (ainfo->storage == ArgInIReg)
1059                                 ainfo->storage = ArgGSharedVtInReg;
1060                         else
1061                                 ainfo->storage = ArgGSharedVtOnStack;
1062                         break;
1063                 default:
1064                         g_assert_not_reached ();
1065                 }
1066         }
1067
1068         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1069                 gr = PARAM_REGS;
1070                 fr = FLOAT_PARAM_REGS;
1071
1072                 /* Emit the signature cookie just before the implicit arguments */
1073                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1074         }
1075
1076         cinfo->stack_usage = stack_size;
1077         cinfo->reg_usage = gr;
1078         cinfo->freg_usage = fr;
1079         return cinfo;
1080 }
1081
1082 /*
1083  * mono_arch_get_argument_info:
1084  * @csig:  a method signature
1085  * @param_count: the number of parameters to consider
1086  * @arg_info: an array to store the result infos
1087  *
1088  * Gathers information on parameters such as size, alignment and
1089  * padding. arg_info should be large enought to hold param_count + 1 entries.
1090  *
1091  * Returns the size of the argument area on the stack.
1092  */
1093 int
1094 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1095 {
1096         int k;
1097         CallInfo *cinfo = get_call_info (NULL, csig);
1098         guint32 args_size = cinfo->stack_usage;
1099
1100         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1101         if (csig->hasthis) {
1102                 arg_info [0].offset = 0;
1103         }
1104
1105         for (k = 0; k < param_count; k++) {
1106                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1107                 /* FIXME: */
1108                 arg_info [k + 1].size = 0;
1109         }
1110
1111         g_free (cinfo);
1112
1113         return args_size;
1114 }
1115
1116 gboolean
1117 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1118 {
1119         CallInfo *c1, *c2;
1120         gboolean res;
1121         MonoType *callee_ret;
1122
1123         c1 = get_call_info (NULL, caller_sig);
1124         c2 = get_call_info (NULL, callee_sig);
1125         res = c1->stack_usage >= c2->stack_usage;
1126         callee_ret = mini_get_underlying_type (callee_sig->ret);
1127         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1128                 /* An address on the callee's stack is passed as the first argument */
1129                 res = FALSE;
1130
1131         g_free (c1);
1132         g_free (c2);
1133
1134         return res;
1135 }
1136
1137 /*
1138  * Initialize the cpu to execute managed code.
1139  */
1140 void
1141 mono_arch_cpu_init (void)
1142 {
1143 #ifndef _MSC_VER
1144         guint16 fpcw;
1145
1146         /* spec compliance requires running with double precision */
1147         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1148         fpcw &= ~X86_FPCW_PRECC_MASK;
1149         fpcw |= X86_FPCW_PREC_DOUBLE;
1150         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1151         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1152 #else
1153         /* TODO: This is crashing on Win64 right now.
1154         * _control87 (_PC_53, MCW_PC);
1155         */
1156 #endif
1157 }
1158
1159 /*
1160  * Initialize architecture specific code.
1161  */
1162 void
1163 mono_arch_init (void)
1164 {
1165         mono_os_mutex_init_recursive (&mini_arch_mutex);
1166
1167         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1168         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1169         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1170         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1171         mono_aot_register_jit_icall ("mono_amd64_handler_block_trampoline_helper", mono_amd64_handler_block_trampoline_helper);
1172
1173 #if defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
1174         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1175 #endif
1176
1177         if (!mono_aot_only)
1178                 bp_trampoline = mini_get_breakpoint_trampoline ();
1179 }
1180
1181 /*
1182  * Cleanup architecture specific code.
1183  */
1184 void
1185 mono_arch_cleanup (void)
1186 {
1187         mono_os_mutex_destroy (&mini_arch_mutex);
1188 }
1189
1190 /*
1191  * This function returns the optimizations supported on this cpu.
1192  */
1193 guint32
1194 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1195 {
1196         guint32 opts = 0;
1197
1198         *exclude_mask = 0;
1199
1200         if (mono_hwcap_x86_has_cmov) {
1201                 opts |= MONO_OPT_CMOV;
1202
1203                 if (mono_hwcap_x86_has_fcmov)
1204                         opts |= MONO_OPT_FCMOV;
1205                 else
1206                         *exclude_mask |= MONO_OPT_FCMOV;
1207         } else {
1208                 *exclude_mask |= MONO_OPT_CMOV;
1209         }
1210
1211 #ifdef TARGET_WIN32
1212         /* The current SIMD doesn't support the argument used by a LD_ADDR to be of type OP_VTARG_ADDR. */
1213         /* This will now be used for value types > 8 or of size 3,5,6,7 as dictated by windows x64 value type ABI. */
1214         /* Since OP_VTARG_ADDR needs to be resolved in mono_spill_global_vars and the SIMD implementation optimize */
1215         /* away the LD_ADDR in load_simd_vreg, that will cause an error in mono_spill_global_vars since incorrect opcode */
1216         /* will now have a reference to an argument that won't be fully decomposed. */
1217         *exclude_mask |= MONO_OPT_SIMD;
1218 #endif
1219
1220         return opts;
1221 }
1222
1223 /*
1224  * This function test for all SSE functions supported.
1225  *
1226  * Returns a bitmask corresponding to all supported versions.
1227  *
1228  */
1229 guint32
1230 mono_arch_cpu_enumerate_simd_versions (void)
1231 {
1232         guint32 sse_opts = 0;
1233
1234         if (mono_hwcap_x86_has_sse1)
1235                 sse_opts |= SIMD_VERSION_SSE1;
1236
1237         if (mono_hwcap_x86_has_sse2)
1238                 sse_opts |= SIMD_VERSION_SSE2;
1239
1240         if (mono_hwcap_x86_has_sse3)
1241                 sse_opts |= SIMD_VERSION_SSE3;
1242
1243         if (mono_hwcap_x86_has_ssse3)
1244                 sse_opts |= SIMD_VERSION_SSSE3;
1245
1246         if (mono_hwcap_x86_has_sse41)
1247                 sse_opts |= SIMD_VERSION_SSE41;
1248
1249         if (mono_hwcap_x86_has_sse42)
1250                 sse_opts |= SIMD_VERSION_SSE42;
1251
1252         if (mono_hwcap_x86_has_sse4a)
1253                 sse_opts |= SIMD_VERSION_SSE4a;
1254
1255         return sse_opts;
1256 }
1257
1258 #ifndef DISABLE_JIT
1259
1260 GList *
1261 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1262 {
1263         GList *vars = NULL;
1264         int i;
1265
1266         for (i = 0; i < cfg->num_varinfo; i++) {
1267                 MonoInst *ins = cfg->varinfo [i];
1268                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1269
1270                 /* unused vars */
1271                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1272                         continue;
1273
1274                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1275                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1276                         continue;
1277
1278                 if (mono_is_regsize_var (ins->inst_vtype)) {
1279                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1280                         g_assert (i == vmv->idx);
1281                         vars = g_list_prepend (vars, vmv);
1282                 }
1283         }
1284
1285         vars = mono_varlist_sort (cfg, vars, 0);
1286
1287         return vars;
1288 }
1289
1290 /**
1291  * mono_arch_compute_omit_fp:
1292  * Determine whether the frame pointer can be eliminated.
1293  */
1294 static void
1295 mono_arch_compute_omit_fp (MonoCompile *cfg)
1296 {
1297         MonoMethodSignature *sig;
1298         MonoMethodHeader *header;
1299         int i, locals_size;
1300         CallInfo *cinfo;
1301
1302         if (cfg->arch.omit_fp_computed)
1303                 return;
1304
1305         header = cfg->header;
1306
1307         sig = mono_method_signature (cfg->method);
1308
1309         if (!cfg->arch.cinfo)
1310                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1311         cinfo = (CallInfo *)cfg->arch.cinfo;
1312
1313         /*
1314          * FIXME: Remove some of the restrictions.
1315          */
1316         cfg->arch.omit_fp = TRUE;
1317         cfg->arch.omit_fp_computed = TRUE;
1318
1319         if (cfg->disable_omit_fp)
1320                 cfg->arch.omit_fp = FALSE;
1321
1322         if (!debug_omit_fp ())
1323                 cfg->arch.omit_fp = FALSE;
1324         /*
1325         if (cfg->method->save_lmf)
1326                 cfg->arch.omit_fp = FALSE;
1327         */
1328         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1329                 cfg->arch.omit_fp = FALSE;
1330         if (header->num_clauses)
1331                 cfg->arch.omit_fp = FALSE;
1332         if (cfg->param_area)
1333                 cfg->arch.omit_fp = FALSE;
1334         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1335                 cfg->arch.omit_fp = FALSE;
1336         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)))
1337                 cfg->arch.omit_fp = FALSE;
1338         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1339                 ArgInfo *ainfo = &cinfo->args [i];
1340
1341                 if (ainfo->storage == ArgOnStack || ainfo->storage == ArgValuetypeAddrInIReg || ainfo->storage == ArgValuetypeAddrOnStack) {
1342                         /*
1343                          * The stack offset can only be determined when the frame
1344                          * size is known.
1345                          */
1346                         cfg->arch.omit_fp = FALSE;
1347                 }
1348         }
1349
1350         locals_size = 0;
1351         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1352                 MonoInst *ins = cfg->varinfo [i];
1353                 int ialign;
1354
1355                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1356         }
1357 }
1358
1359 GList *
1360 mono_arch_get_global_int_regs (MonoCompile *cfg)
1361 {
1362         GList *regs = NULL;
1363
1364         mono_arch_compute_omit_fp (cfg);
1365
1366         if (cfg->arch.omit_fp)
1367                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1368
1369         /* We use the callee saved registers for global allocation */
1370         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1371         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1372         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1373         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1374         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1375 #ifdef TARGET_WIN32
1376         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1377         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1378 #endif
1379
1380         return regs;
1381 }
1382
1383 GList*
1384 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1385 {
1386         GList *regs = NULL;
1387         int i;
1388
1389         /* All XMM registers */
1390         for (i = 0; i < 16; ++i)
1391                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1392
1393         return regs;
1394 }
1395
1396 GList*
1397 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1398 {
1399         static GList *r = NULL;
1400
1401         if (r == NULL) {
1402                 GList *regs = NULL;
1403
1404                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1405                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1406                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1407                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1408                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1409                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1410
1411                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1412                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1413                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1414                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1415                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1416                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1417                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1418                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1419
1420                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1421         }
1422
1423         return r;
1424 }
1425
1426 GList*
1427 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1428 {
1429         int i;
1430         static GList *r = NULL;
1431
1432         if (r == NULL) {
1433                 GList *regs = NULL;
1434
1435                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1436                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1437
1438                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1439         }
1440
1441         return r;
1442 }
1443
1444 /*
1445  * mono_arch_regalloc_cost:
1446  *
1447  *  Return the cost, in number of memory references, of the action of
1448  * allocating the variable VMV into a register during global register
1449  * allocation.
1450  */
1451 guint32
1452 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1453 {
1454         MonoInst *ins = cfg->varinfo [vmv->idx];
1455
1456         if (cfg->method->save_lmf)
1457                 /* The register is already saved */
1458                 /* substract 1 for the invisible store in the prolog */
1459                 return (ins->opcode == OP_ARG) ? 0 : 1;
1460         else
1461                 /* push+pop */
1462                 return (ins->opcode == OP_ARG) ? 1 : 2;
1463 }
1464
1465 /*
1466  * mono_arch_fill_argument_info:
1467  *
1468  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1469  * of the method.
1470  */
1471 void
1472 mono_arch_fill_argument_info (MonoCompile *cfg)
1473 {
1474         MonoType *sig_ret;
1475         MonoMethodSignature *sig;
1476         MonoInst *ins;
1477         int i;
1478         CallInfo *cinfo;
1479
1480         sig = mono_method_signature (cfg->method);
1481
1482         cinfo = (CallInfo *)cfg->arch.cinfo;
1483         sig_ret = mini_get_underlying_type (sig->ret);
1484
1485         /*
1486          * Contrary to mono_arch_allocate_vars (), the information should describe
1487          * where the arguments are at the beginning of the method, not where they can be
1488          * accessed during the execution of the method. The later makes no sense for the
1489          * global register allocator, since a variable can be in more than one location.
1490          */
1491         switch (cinfo->ret.storage) {
1492         case ArgInIReg:
1493         case ArgInFloatSSEReg:
1494         case ArgInDoubleSSEReg:
1495                 cfg->ret->opcode = OP_REGVAR;
1496                 cfg->ret->inst_c0 = cinfo->ret.reg;
1497                 break;
1498         case ArgValuetypeInReg:
1499                 cfg->ret->opcode = OP_REGOFFSET;
1500                 cfg->ret->inst_basereg = -1;
1501                 cfg->ret->inst_offset = -1;
1502                 break;
1503         case ArgNone:
1504                 break;
1505         default:
1506                 g_assert_not_reached ();
1507         }
1508
1509         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1510                 ArgInfo *ainfo = &cinfo->args [i];
1511
1512                 ins = cfg->args [i];
1513
1514                 switch (ainfo->storage) {
1515                 case ArgInIReg:
1516                 case ArgInFloatSSEReg:
1517                 case ArgInDoubleSSEReg:
1518                         ins->opcode = OP_REGVAR;
1519                         ins->inst_c0 = ainfo->reg;
1520                         break;
1521                 case ArgOnStack:
1522                         ins->opcode = OP_REGOFFSET;
1523                         ins->inst_basereg = -1;
1524                         ins->inst_offset = -1;
1525                         break;
1526                 case ArgValuetypeInReg:
1527                         /* Dummy */
1528                         ins->opcode = OP_NOP;
1529                         break;
1530                 default:
1531                         g_assert_not_reached ();
1532                 }
1533         }
1534 }
1535
1536 void
1537 mono_arch_allocate_vars (MonoCompile *cfg)
1538 {
1539         MonoType *sig_ret;
1540         MonoMethodSignature *sig;
1541         MonoInst *ins;
1542         int i, offset;
1543         guint32 locals_stack_size, locals_stack_align;
1544         gint32 *offsets;
1545         CallInfo *cinfo;
1546
1547         sig = mono_method_signature (cfg->method);
1548
1549         cinfo = (CallInfo *)cfg->arch.cinfo;
1550         sig_ret = mini_get_underlying_type (sig->ret);
1551
1552         mono_arch_compute_omit_fp (cfg);
1553
1554         /*
1555          * We use the ABI calling conventions for managed code as well.
1556          * Exception: valuetypes are only sometimes passed or returned in registers.
1557          */
1558
1559         /*
1560          * The stack looks like this:
1561          * <incoming arguments passed on the stack>
1562          * <return value>
1563          * <lmf/caller saved registers>
1564          * <locals>
1565          * <spill area>
1566          * <localloc area>  -> grows dynamically
1567          * <params area>
1568          */
1569
1570         if (cfg->arch.omit_fp) {
1571                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1572                 cfg->frame_reg = AMD64_RSP;
1573                 offset = 0;
1574         } else {
1575                 /* Locals are allocated backwards from %fp */
1576                 cfg->frame_reg = AMD64_RBP;
1577                 offset = 0;
1578         }
1579
1580         cfg->arch.saved_iregs = cfg->used_int_regs;
1581         if (cfg->method->save_lmf) {
1582                 /* Save all callee-saved registers normally (except RBP, if not already used), and restore them when unwinding through an LMF */
1583                 guint32 iregs_to_save = AMD64_CALLEE_SAVED_REGS & ~(1<<AMD64_RBP);
1584                 cfg->arch.saved_iregs |= iregs_to_save;
1585         }
1586
1587         if (cfg->arch.omit_fp)
1588                 cfg->arch.reg_save_area_offset = offset;
1589         /* Reserve space for callee saved registers */
1590         for (i = 0; i < AMD64_NREG; ++i)
1591                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1592                         offset += sizeof(mgreg_t);
1593                 }
1594         if (!cfg->arch.omit_fp)
1595                 cfg->arch.reg_save_area_offset = -offset;
1596
1597         if (sig_ret->type != MONO_TYPE_VOID) {
1598                 switch (cinfo->ret.storage) {
1599                 case ArgInIReg:
1600                 case ArgInFloatSSEReg:
1601                 case ArgInDoubleSSEReg:
1602                         cfg->ret->opcode = OP_REGVAR;
1603                         cfg->ret->inst_c0 = cinfo->ret.reg;
1604                         cfg->ret->dreg = cinfo->ret.reg;
1605                         break;
1606                 case ArgValuetypeAddrInIReg:
1607                 case ArgGsharedvtVariableInReg:
1608                         /* The register is volatile */
1609                         cfg->vret_addr->opcode = OP_REGOFFSET;
1610                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1611                         if (cfg->arch.omit_fp) {
1612                                 cfg->vret_addr->inst_offset = offset;
1613                                 offset += 8;
1614                         } else {
1615                                 offset += 8;
1616                                 cfg->vret_addr->inst_offset = -offset;
1617                         }
1618                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1619                                 printf ("vret_addr =");
1620                                 mono_print_ins (cfg->vret_addr);
1621                         }
1622                         break;
1623                 case ArgValuetypeInReg:
1624                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1625                         cfg->ret->opcode = OP_REGOFFSET;
1626                         cfg->ret->inst_basereg = cfg->frame_reg;
1627                         if (cfg->arch.omit_fp) {
1628                                 cfg->ret->inst_offset = offset;
1629                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1630                         } else {
1631                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1632                                 cfg->ret->inst_offset = - offset;
1633                         }
1634                         break;
1635                 default:
1636                         g_assert_not_reached ();
1637                 }
1638         }
1639
1640         /* Allocate locals */
1641         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1642         if (locals_stack_align) {
1643                 offset += (locals_stack_align - 1);
1644                 offset &= ~(locals_stack_align - 1);
1645         }
1646         if (cfg->arch.omit_fp) {
1647                 cfg->locals_min_stack_offset = offset;
1648                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1649         } else {
1650                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1651                 cfg->locals_max_stack_offset = - offset;
1652         }
1653
1654         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1655                 if (offsets [i] != -1) {
1656                         MonoInst *ins = cfg->varinfo [i];
1657                         ins->opcode = OP_REGOFFSET;
1658                         ins->inst_basereg = cfg->frame_reg;
1659                         if (cfg->arch.omit_fp)
1660                                 ins->inst_offset = (offset + offsets [i]);
1661                         else
1662                                 ins->inst_offset = - (offset + offsets [i]);
1663                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1664                 }
1665         }
1666         offset += locals_stack_size;
1667
1668         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1669                 g_assert (!cfg->arch.omit_fp);
1670                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1671                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1672         }
1673
1674         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1675                 ins = cfg->args [i];
1676                 if (ins->opcode != OP_REGVAR) {
1677                         ArgInfo *ainfo = &cinfo->args [i];
1678                         gboolean inreg = TRUE;
1679
1680                         /* FIXME: Allocate volatile arguments to registers */
1681                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1682                                 inreg = FALSE;
1683
1684                         /*
1685                          * Under AMD64, all registers used to pass arguments to functions
1686                          * are volatile across calls.
1687                          * FIXME: Optimize this.
1688                          */
1689                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1690                                 inreg = FALSE;
1691
1692                         ins->opcode = OP_REGOFFSET;
1693
1694                         switch (ainfo->storage) {
1695                         case ArgInIReg:
1696                         case ArgInFloatSSEReg:
1697                         case ArgInDoubleSSEReg:
1698                         case ArgGSharedVtInReg:
1699                                 if (inreg) {
1700                                         ins->opcode = OP_REGVAR;
1701                                         ins->dreg = ainfo->reg;
1702                                 }
1703                                 break;
1704                         case ArgOnStack:
1705                         case ArgGSharedVtOnStack:
1706                                 g_assert (!cfg->arch.omit_fp);
1707                                 ins->opcode = OP_REGOFFSET;
1708                                 ins->inst_basereg = cfg->frame_reg;
1709                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1710                                 break;
1711                         case ArgValuetypeInReg:
1712                                 break;
1713                         case ArgValuetypeAddrInIReg:
1714                         case ArgValuetypeAddrOnStack: {
1715                                 MonoInst *indir;
1716                                 g_assert (!cfg->arch.omit_fp);
1717                                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
1718                                 MONO_INST_NEW (cfg, indir, 0);
1719
1720                                 indir->opcode = OP_REGOFFSET;
1721                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1722                                         indir->inst_basereg = cfg->frame_reg;
1723                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1724                                         offset += (sizeof (gpointer));
1725                                         indir->inst_offset = - offset;
1726                                 }
1727                                 else {
1728                                         indir->inst_basereg = cfg->frame_reg;
1729                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1730                                 }
1731
1732                                 ins->opcode = OP_VTARG_ADDR;
1733                                 ins->inst_left = indir;
1734
1735                                 break;
1736                         }
1737                         default:
1738                                 NOT_IMPLEMENTED;
1739                         }
1740
1741                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgValuetypeAddrOnStack) && (ainfo->storage != ArgGSharedVtOnStack)) {
1742                                 ins->opcode = OP_REGOFFSET;
1743                                 ins->inst_basereg = cfg->frame_reg;
1744                                 /* These arguments are saved to the stack in the prolog */
1745                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
1746                                 if (cfg->arch.omit_fp) {
1747                                         ins->inst_offset = offset;
1748                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1749                                         // Arguments are yet supported by the stack map creation code
1750                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1751                                 } else {
1752                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
1753                                         ins->inst_offset = - offset;
1754                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1755                                 }
1756                         }
1757                 }
1758         }
1759
1760         cfg->stack_offset = offset;
1761 }
1762
1763 void
1764 mono_arch_create_vars (MonoCompile *cfg)
1765 {
1766         MonoMethodSignature *sig;
1767         CallInfo *cinfo;
1768         MonoType *sig_ret;
1769
1770         sig = mono_method_signature (cfg->method);
1771
1772         if (!cfg->arch.cinfo)
1773                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1774         cinfo = (CallInfo *)cfg->arch.cinfo;
1775
1776         if (cinfo->ret.storage == ArgValuetypeInReg)
1777                 cfg->ret_var_is_local = TRUE;
1778
1779         sig_ret = mini_get_underlying_type (sig->ret);
1780         if (cinfo->ret.storage == ArgValuetypeAddrInIReg || cinfo->ret.storage == ArgGsharedvtVariableInReg) {
1781                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1782                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1783                         printf ("vret_addr = ");
1784                         mono_print_ins (cfg->vret_addr);
1785                 }
1786         }
1787
1788         if (cfg->gen_sdb_seq_points) {
1789                 MonoInst *ins;
1790
1791                 if (cfg->compile_aot) {
1792                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1793                         ins->flags |= MONO_INST_VOLATILE;
1794                         cfg->arch.seq_point_info_var = ins;
1795                 }
1796                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1797                 ins->flags |= MONO_INST_VOLATILE;
1798                 cfg->arch.ss_tramp_var = ins;
1799
1800                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1801                 ins->flags |= MONO_INST_VOLATILE;
1802                 cfg->arch.bp_tramp_var = ins;
1803         }
1804
1805         if (cfg->method->save_lmf)
1806                 cfg->create_lmf_var = TRUE;
1807
1808         if (cfg->method->save_lmf) {
1809                 cfg->lmf_ir = TRUE;
1810         }
1811 }
1812
1813 static void
1814 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1815 {
1816         MonoInst *ins;
1817
1818         switch (storage) {
1819         case ArgInIReg:
1820                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1821                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
1822                 ins->sreg1 = tree->dreg;
1823                 MONO_ADD_INS (cfg->cbb, ins);
1824                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1825                 break;
1826         case ArgInFloatSSEReg:
1827                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1828                 ins->dreg = mono_alloc_freg (cfg);
1829                 ins->sreg1 = tree->dreg;
1830                 MONO_ADD_INS (cfg->cbb, ins);
1831
1832                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1833                 break;
1834         case ArgInDoubleSSEReg:
1835                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1836                 ins->dreg = mono_alloc_freg (cfg);
1837                 ins->sreg1 = tree->dreg;
1838                 MONO_ADD_INS (cfg->cbb, ins);
1839
1840                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1841
1842                 break;
1843         default:
1844                 g_assert_not_reached ();
1845         }
1846 }
1847
1848 static int
1849 arg_storage_to_load_membase (ArgStorage storage)
1850 {
1851         switch (storage) {
1852         case ArgInIReg:
1853 #if defined(__mono_ilp32__)
1854                 return OP_LOADI8_MEMBASE;
1855 #else
1856                 return OP_LOAD_MEMBASE;
1857 #endif
1858         case ArgInDoubleSSEReg:
1859                 return OP_LOADR8_MEMBASE;
1860         case ArgInFloatSSEReg:
1861                 return OP_LOADR4_MEMBASE;
1862         default:
1863                 g_assert_not_reached ();
1864         }
1865
1866         return -1;
1867 }
1868
1869 static void
1870 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1871 {
1872         MonoMethodSignature *tmp_sig;
1873         int sig_reg;
1874
1875         if (call->tail_call)
1876                 NOT_IMPLEMENTED;
1877
1878         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1879
1880         /*
1881          * mono_ArgIterator_Setup assumes the signature cookie is
1882          * passed first and all the arguments which were before it are
1883          * passed on the stack after the signature. So compensate by
1884          * passing a different signature.
1885          */
1886         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
1887         tmp_sig->param_count -= call->signature->sentinelpos;
1888         tmp_sig->sentinelpos = 0;
1889         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1890
1891         sig_reg = mono_alloc_ireg (cfg);
1892         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
1893
1894         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
1895 }
1896
1897 #ifdef ENABLE_LLVM
1898 static inline LLVMArgStorage
1899 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1900 {
1901         switch (storage) {
1902         case ArgInIReg:
1903                 return LLVMArgInIReg;
1904         case ArgNone:
1905                 return LLVMArgNone;
1906         case ArgGSharedVtInReg:
1907         case ArgGSharedVtOnStack:
1908                 return LLVMArgGSharedVt;
1909         default:
1910                 g_assert_not_reached ();
1911                 return LLVMArgNone;
1912         }
1913 }
1914
1915 LLVMCallInfo*
1916 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1917 {
1918         int i, n;
1919         CallInfo *cinfo;
1920         ArgInfo *ainfo;
1921         int j;
1922         LLVMCallInfo *linfo;
1923         MonoType *t, *sig_ret;
1924
1925         n = sig->param_count + sig->hasthis;
1926         sig_ret = mini_get_underlying_type (sig->ret);
1927
1928         cinfo = get_call_info (cfg->mempool, sig);
1929
1930         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1931
1932         /*
1933          * LLVM always uses the native ABI while we use our own ABI, the
1934          * only difference is the handling of vtypes:
1935          * - we only pass/receive them in registers in some cases, and only
1936          *   in 1 or 2 integer registers.
1937          */
1938         switch (cinfo->ret.storage) {
1939         case ArgNone:
1940                 linfo->ret.storage = LLVMArgNone;
1941                 break;
1942         case ArgInIReg:
1943         case ArgInFloatSSEReg:
1944         case ArgInDoubleSSEReg:
1945                 linfo->ret.storage = LLVMArgNormal;
1946                 break;
1947         case ArgValuetypeInReg: {
1948                 ainfo = &cinfo->ret;
1949
1950                 if (sig->pinvoke &&
1951                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
1952                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
1953                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
1954                         cfg->disable_llvm = TRUE;
1955                         return linfo;
1956                 }
1957
1958                 linfo->ret.storage = LLVMArgVtypeInReg;
1959                 for (j = 0; j < 2; ++j)
1960                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1961                 break;
1962         }
1963         case ArgValuetypeAddrInIReg:
1964         case ArgGsharedvtVariableInReg:
1965                 /* Vtype returned using a hidden argument */
1966                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1967                 linfo->vret_arg_index = cinfo->vret_arg_index;
1968                 break;
1969         default:
1970                 g_assert_not_reached ();
1971                 break;
1972         }
1973
1974         for (i = 0; i < n; ++i) {
1975                 ainfo = cinfo->args + i;
1976
1977                 if (i >= sig->hasthis)
1978                         t = sig->params [i - sig->hasthis];
1979                 else
1980                         t = &mono_defaults.int_class->byval_arg;
1981                 t = mini_type_get_underlying_type (t);
1982
1983                 linfo->args [i].storage = LLVMArgNone;
1984
1985                 switch (ainfo->storage) {
1986                 case ArgInIReg:
1987                         linfo->args [i].storage = LLVMArgNormal;
1988                         break;
1989                 case ArgInDoubleSSEReg:
1990                 case ArgInFloatSSEReg:
1991                         linfo->args [i].storage = LLVMArgNormal;
1992                         break;
1993                 case ArgOnStack:
1994                         if (MONO_TYPE_ISSTRUCT (t))
1995                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1996                         else
1997                                 linfo->args [i].storage = LLVMArgNormal;
1998                         break;
1999                 case ArgValuetypeInReg:
2000                         if (sig->pinvoke &&
2001                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2002                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2003                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2004                                 cfg->disable_llvm = TRUE;
2005                                 return linfo;
2006                         }
2007
2008                         linfo->args [i].storage = LLVMArgVtypeInReg;
2009                         for (j = 0; j < 2; ++j)
2010                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2011                         break;
2012                 case ArgGSharedVtInReg:
2013                 case ArgGSharedVtOnStack:
2014                         linfo->args [i].storage = LLVMArgGSharedVt;
2015                         break;
2016                 default:
2017                         cfg->exception_message = g_strdup ("ainfo->storage");
2018                         cfg->disable_llvm = TRUE;
2019                         break;
2020                 }
2021         }
2022
2023         return linfo;
2024 }
2025 #endif
2026
2027 void
2028 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2029 {
2030         MonoInst *arg, *in;
2031         MonoMethodSignature *sig;
2032         MonoType *sig_ret;
2033         int i, n;
2034         CallInfo *cinfo;
2035         ArgInfo *ainfo;
2036
2037         sig = call->signature;
2038         n = sig->param_count + sig->hasthis;
2039
2040         cinfo = get_call_info (cfg->mempool, sig);
2041
2042         sig_ret = sig->ret;
2043
2044         if (COMPILE_LLVM (cfg)) {
2045                 /* We shouldn't be called in the llvm case */
2046                 cfg->disable_llvm = TRUE;
2047                 return;
2048         }
2049
2050         /*
2051          * Emit all arguments which are passed on the stack to prevent register
2052          * allocation problems.
2053          */
2054         for (i = 0; i < n; ++i) {
2055                 MonoType *t;
2056                 ainfo = cinfo->args + i;
2057
2058                 in = call->args [i];
2059
2060                 if (sig->hasthis && i == 0)
2061                         t = &mono_defaults.object_class->byval_arg;
2062                 else
2063                         t = sig->params [i - sig->hasthis];
2064
2065                 t = mini_get_underlying_type (t);
2066                 //XXX what about ArgGSharedVtOnStack here?
2067                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2068                         if (!t->byref) {
2069                                 if (t->type == MONO_TYPE_R4)
2070                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2071                                 else if (t->type == MONO_TYPE_R8)
2072                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2073                                 else
2074                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2075                         } else {
2076                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2077                         }
2078                         if (cfg->compute_gc_maps) {
2079                                 MonoInst *def;
2080
2081                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2082                         }
2083                 }
2084         }
2085
2086         /*
2087          * Emit all parameters passed in registers in non-reverse order for better readability
2088          * and to help the optimization in emit_prolog ().
2089          */
2090         for (i = 0; i < n; ++i) {
2091                 ainfo = cinfo->args + i;
2092
2093                 in = call->args [i];
2094
2095                 if (ainfo->storage == ArgInIReg)
2096                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2097         }
2098
2099         for (i = n - 1; i >= 0; --i) {
2100                 MonoType *t;
2101
2102                 ainfo = cinfo->args + i;
2103
2104                 in = call->args [i];
2105
2106                 if (sig->hasthis && i == 0)
2107                         t = &mono_defaults.object_class->byval_arg;
2108                 else
2109                         t = sig->params [i - sig->hasthis];
2110                 t = mini_get_underlying_type (t);
2111
2112                 switch (ainfo->storage) {
2113                 case ArgInIReg:
2114                         /* Already done */
2115                         break;
2116                 case ArgInFloatSSEReg:
2117                 case ArgInDoubleSSEReg:
2118                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2119                         break;
2120                 case ArgOnStack:
2121                 case ArgValuetypeInReg:
2122                 case ArgValuetypeAddrInIReg:
2123                 case ArgValuetypeAddrOnStack:
2124                 case ArgGSharedVtInReg:
2125                 case ArgGSharedVtOnStack: {
2126                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2127                                 /* Already emitted above */
2128                                 break;
2129                         //FIXME what about ArgGSharedVtOnStack ?
2130                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2131                                 MonoInst *call_inst = (MonoInst*)call;
2132                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2133                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2134                                 break;
2135                         }
2136
2137                         guint32 align;
2138                         guint32 size;
2139
2140                         if (sig->pinvoke)
2141                                 size = mono_type_native_stack_size (t, &align);
2142                         else {
2143                                 /*
2144                                  * Other backends use mono_type_stack_size (), but that
2145                                  * aligns the size to 8, which is larger than the size of
2146                                  * the source, leading to reads of invalid memory if the
2147                                  * source is at the end of address space.
2148                                  */
2149                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2150                         }
2151
2152                         if (size >= 10000) {
2153                                 /* Avoid asserts in emit_memcpy () */
2154                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2155                                 /* Continue normally */
2156                         }
2157
2158                         if (size > 0 || ainfo->pass_empty_struct) {
2159                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2160                                 arg->sreg1 = in->dreg;
2161                                 arg->klass = mono_class_from_mono_type (t);
2162                                 arg->backend.size = size;
2163                                 arg->inst_p0 = call;
2164                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2165                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2166
2167                                 MONO_ADD_INS (cfg->cbb, arg);
2168                         }
2169                         break;
2170                 }
2171                 default:
2172                         g_assert_not_reached ();
2173                 }
2174
2175                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2176                         /* Emit the signature cookie just before the implicit arguments */
2177                         emit_sig_cookie (cfg, call, cinfo);
2178         }
2179
2180         /* Handle the case where there are no implicit arguments */
2181         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2182                 emit_sig_cookie (cfg, call, cinfo);
2183
2184         switch (cinfo->ret.storage) {
2185         case ArgValuetypeInReg:
2186                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2187                         /*
2188                          * Tell the JIT to use a more efficient calling convention: call using
2189                          * OP_CALL, compute the result location after the call, and save the
2190                          * result there.
2191                          */
2192                         call->vret_in_reg = TRUE;
2193                         /*
2194                          * Nullify the instruction computing the vret addr to enable
2195                          * future optimizations.
2196                          */
2197                         if (call->vret_var)
2198                                 NULLIFY_INS (call->vret_var);
2199                 } else {
2200                         if (call->tail_call)
2201                                 NOT_IMPLEMENTED;
2202                         /*
2203                          * The valuetype is in RAX:RDX after the call, need to be copied to
2204                          * the stack. Push the address here, so the call instruction can
2205                          * access it.
2206                          */
2207                         if (!cfg->arch.vret_addr_loc) {
2208                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2209                                 /* Prevent it from being register allocated or optimized away */
2210                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2211                         }
2212
2213                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2214                 }
2215                 break;
2216         case ArgValuetypeAddrInIReg:
2217         case ArgGsharedvtVariableInReg: {
2218                 MonoInst *vtarg;
2219                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2220                 vtarg->sreg1 = call->vret_var->dreg;
2221                 vtarg->dreg = mono_alloc_preg (cfg);
2222                 MONO_ADD_INS (cfg->cbb, vtarg);
2223
2224                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2225                 break;
2226         }
2227         default:
2228                 break;
2229         }
2230
2231         if (cfg->method->save_lmf) {
2232                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2233                 MONO_ADD_INS (cfg->cbb, arg);
2234         }
2235
2236         call->stack_usage = cinfo->stack_usage;
2237 }
2238
2239 void
2240 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2241 {
2242         MonoInst *arg;
2243         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2244         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2245         int size = ins->backend.size;
2246
2247         switch (ainfo->storage) {
2248         case ArgValuetypeInReg: {
2249                 MonoInst *load;
2250                 int part;
2251
2252                 for (part = 0; part < 2; ++part) {
2253                         if (ainfo->pair_storage [part] == ArgNone)
2254                                 continue;
2255
2256                         if (ainfo->pass_empty_struct) {
2257                                 //Pass empty struct value as 0 on platforms representing empty structs as 1 byte.
2258                                 NEW_ICONST (cfg, load, 0);
2259                         }
2260                         else {
2261                                 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2262                                 load->inst_basereg = src->dreg;
2263                                 load->inst_offset = part * sizeof(mgreg_t);
2264
2265                                 switch (ainfo->pair_storage [part]) {
2266                                 case ArgInIReg:
2267                                         load->dreg = mono_alloc_ireg (cfg);
2268                                         break;
2269                                 case ArgInDoubleSSEReg:
2270                                 case ArgInFloatSSEReg:
2271                                         load->dreg = mono_alloc_freg (cfg);
2272                                         break;
2273                                 default:
2274                                         g_assert_not_reached ();
2275                                 }
2276                         }
2277
2278                         MONO_ADD_INS (cfg->cbb, load);
2279
2280                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2281                 }
2282                 break;
2283         }
2284         case ArgValuetypeAddrInIReg:
2285         case ArgValuetypeAddrOnStack: {
2286                 MonoInst *vtaddr, *load;
2287
2288                 g_assert (ainfo->storage == ArgValuetypeAddrInIReg || (ainfo->storage == ArgValuetypeAddrOnStack && ainfo->pair_storage [0] == ArgNone));
2289
2290                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2291
2292                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2293                 cfg->has_indirection = TRUE;
2294                 load->inst_p0 = vtaddr;
2295                 vtaddr->flags |= MONO_INST_INDIRECT;
2296                 load->type = STACK_MP;
2297                 load->klass = vtaddr->klass;
2298                 load->dreg = mono_alloc_ireg (cfg);
2299                 MONO_ADD_INS (cfg->cbb, load);
2300                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, SIZEOF_VOID_P);
2301
2302                 if (ainfo->pair_storage [0] == ArgInIReg) {
2303                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2304                         arg->dreg = mono_alloc_ireg (cfg);
2305                         arg->sreg1 = load->dreg;
2306                         arg->inst_imm = 0;
2307                         MONO_ADD_INS (cfg->cbb, arg);
2308                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2309                 } else {
2310                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2311                 }
2312                 break;
2313         }
2314         case ArgGSharedVtInReg:
2315                 /* Pass by addr */
2316                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2317                 break;
2318         case ArgGSharedVtOnStack:
2319                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2320                 break;
2321         default:
2322                 if (size == 8) {
2323                         int dreg = mono_alloc_ireg (cfg);
2324
2325                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2326                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2327                 } else if (size <= 40) {
2328                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2329                 } else {
2330                         // FIXME: Code growth
2331                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, SIZEOF_VOID_P);
2332                 }
2333
2334                 if (cfg->compute_gc_maps) {
2335                         MonoInst *def;
2336                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2337                 }
2338         }
2339 }
2340
2341 void
2342 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2343 {
2344         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2345
2346         if (ret->type == MONO_TYPE_R4) {
2347                 if (COMPILE_LLVM (cfg))
2348                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2349                 else
2350                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2351                 return;
2352         } else if (ret->type == MONO_TYPE_R8) {
2353                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2354                 return;
2355         }
2356
2357         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2358 }
2359
2360 #endif /* DISABLE_JIT */
2361
2362 #define EMIT_COND_BRANCH(ins,cond,sign) \
2363         if (ins->inst_true_bb->native_offset) { \
2364                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2365         } else { \
2366                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2367                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2368             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2369                         x86_branch8 (code, cond, 0, sign); \
2370                 else \
2371                         x86_branch32 (code, cond, 0, sign); \
2372 }
2373
2374 typedef struct {
2375         MonoMethodSignature *sig;
2376         CallInfo *cinfo;
2377 } ArchDynCallInfo;
2378
2379 static gboolean
2380 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2381 {
2382         int i;
2383
2384         switch (cinfo->ret.storage) {
2385         case ArgNone:
2386         case ArgInIReg:
2387         case ArgInFloatSSEReg:
2388         case ArgInDoubleSSEReg:
2389         case ArgValuetypeAddrInIReg:
2390         case ArgValuetypeInReg:
2391                 break;
2392         default:
2393                 return FALSE;
2394         }
2395
2396         for (i = 0; i < cinfo->nargs; ++i) {
2397                 ArgInfo *ainfo = &cinfo->args [i];
2398                 switch (ainfo->storage) {
2399                 case ArgInIReg:
2400                 case ArgInFloatSSEReg:
2401                 case ArgInDoubleSSEReg:
2402                 case ArgValuetypeInReg:
2403                         break;
2404                 case ArgOnStack:
2405                         if (!(ainfo->offset + (ainfo->arg_size / 8) <= DYN_CALL_STACK_ARGS))
2406                                 return FALSE;
2407                         break;
2408                 default:
2409                         return FALSE;
2410                 }
2411         }
2412
2413         return TRUE;
2414 }
2415
2416 /*
2417  * mono_arch_dyn_call_prepare:
2418  *
2419  *   Return a pointer to an arch-specific structure which contains information
2420  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2421  * supported for SIG.
2422  * This function is equivalent to ffi_prep_cif in libffi.
2423  */
2424 MonoDynCallInfo*
2425 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2426 {
2427         ArchDynCallInfo *info;
2428         CallInfo *cinfo;
2429
2430         cinfo = get_call_info (NULL, sig);
2431
2432         if (!dyn_call_supported (sig, cinfo)) {
2433                 g_free (cinfo);
2434                 return NULL;
2435         }
2436
2437         info = g_new0 (ArchDynCallInfo, 1);
2438         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2439         info->sig = sig;
2440         info->cinfo = cinfo;
2441
2442         return (MonoDynCallInfo*)info;
2443 }
2444
2445 /*
2446  * mono_arch_dyn_call_free:
2447  *
2448  *   Free a MonoDynCallInfo structure.
2449  */
2450 void
2451 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2452 {
2453         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2454
2455         g_free (ainfo->cinfo);
2456         g_free (ainfo);
2457 }
2458
2459 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2460 #define GREG_TO_PTR(greg) (gpointer)(greg)
2461
2462 /*
2463  * mono_arch_get_start_dyn_call:
2464  *
2465  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2466  * store the result into BUF.
2467  * ARGS should be an array of pointers pointing to the arguments.
2468  * RET should point to a memory buffer large enought to hold the result of the
2469  * call.
2470  * This function should be as fast as possible, any work which does not depend
2471  * on the actual values of the arguments should be done in
2472  * mono_arch_dyn_call_prepare ().
2473  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2474  * libffi.
2475  */
2476 void
2477 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2478 {
2479         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2480         DynCallArgs *p = (DynCallArgs*)buf;
2481         int arg_index, greg, freg, i, pindex;
2482         MonoMethodSignature *sig = dinfo->sig;
2483         int buffer_offset = 0;
2484         static int param_reg_to_index [16];
2485         static gboolean param_reg_to_index_inited;
2486
2487         if (!param_reg_to_index_inited) {
2488                 for (i = 0; i < PARAM_REGS; ++i)
2489                         param_reg_to_index [param_regs [i]] = i;
2490                 mono_memory_barrier ();
2491                 param_reg_to_index_inited = 1;
2492         }
2493
2494         g_assert (buf_len >= sizeof (DynCallArgs));
2495
2496         p->res = 0;
2497         p->ret = ret;
2498
2499         arg_index = 0;
2500         greg = 0;
2501         freg = 0;
2502         pindex = 0;
2503
2504         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2505                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2506                 if (!sig->hasthis)
2507                         pindex = 1;
2508         }
2509
2510         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg)
2511                 p->regs [greg ++] = PTR_TO_GREG(ret);
2512
2513         for (; pindex < sig->param_count; pindex++) {
2514                 MonoType *t = mini_get_underlying_type (sig->params [pindex]);
2515                 gpointer *arg = args [arg_index ++];
2516                 ArgInfo *ainfo = &dinfo->cinfo->args [pindex + sig->hasthis];
2517                 int slot;
2518
2519                 if (ainfo->storage == ArgOnStack) {
2520                         slot = PARAM_REGS + (ainfo->offset / sizeof (mgreg_t));
2521                 } else {
2522                         slot = param_reg_to_index [ainfo->reg];
2523                 }
2524
2525                 if (t->byref) {
2526                         p->regs [slot] = PTR_TO_GREG(*(arg));
2527                         greg ++;
2528                         continue;
2529                 }
2530
2531                 switch (t->type) {
2532                 case MONO_TYPE_OBJECT:
2533                 case MONO_TYPE_PTR:
2534                 case MONO_TYPE_I:
2535                 case MONO_TYPE_U:
2536 #if !defined(__mono_ilp32__)
2537                 case MONO_TYPE_I8:
2538                 case MONO_TYPE_U8:
2539 #endif
2540                         p->regs [slot] = PTR_TO_GREG(*(arg));
2541                         break;
2542 #if defined(__mono_ilp32__)
2543                 case MONO_TYPE_I8:
2544                 case MONO_TYPE_U8:
2545                         p->regs [slot] = *(guint64*)(arg);
2546                         break;
2547 #endif
2548                 case MONO_TYPE_U1:
2549                         p->regs [slot] = *(guint8*)(arg);
2550                         break;
2551                 case MONO_TYPE_I1:
2552                         p->regs [slot] = *(gint8*)(arg);
2553                         break;
2554                 case MONO_TYPE_I2:
2555                         p->regs [slot] = *(gint16*)(arg);
2556                         break;
2557                 case MONO_TYPE_U2:
2558                         p->regs [slot] = *(guint16*)(arg);
2559                         break;
2560                 case MONO_TYPE_I4:
2561                         p->regs [slot] = *(gint32*)(arg);
2562                         break;
2563                 case MONO_TYPE_U4:
2564                         p->regs [slot] = *(guint32*)(arg);
2565                         break;
2566                 case MONO_TYPE_R4: {
2567                         double d;
2568
2569                         *(float*)&d = *(float*)(arg);
2570                         p->has_fp = 1;
2571                         p->fregs [freg ++] = d;
2572                         break;
2573                 }
2574                 case MONO_TYPE_R8:
2575                         p->has_fp = 1;
2576                         p->fregs [freg ++] = *(double*)(arg);
2577                         break;
2578                 case MONO_TYPE_GENERICINST:
2579                     if (MONO_TYPE_IS_REFERENCE (t)) {
2580                                 p->regs [slot] = PTR_TO_GREG(*(arg));
2581                                 break;
2582                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2583                                         MonoClass *klass = mono_class_from_mono_type (t);
2584                                         guint8 *nullable_buf;
2585                                         int size;
2586
2587                                         size = mono_class_value_size (klass, NULL);
2588                                         nullable_buf = p->buffer + buffer_offset;
2589                                         buffer_offset += size;
2590                                         g_assert (buffer_offset <= 256);
2591
2592                                         /* The argument pointed to by arg is either a boxed vtype or null */
2593                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2594
2595                                         arg = (gpointer*)nullable_buf;
2596                                         /* Fall though */
2597
2598                         } else {
2599                                 /* Fall through */
2600                         }
2601                 case MONO_TYPE_VALUETYPE: {
2602                         switch (ainfo->storage) {
2603                         case ArgValuetypeInReg:
2604                                 for (i = 0; i < 2; ++i) {
2605                                         switch (ainfo->pair_storage [i]) {
2606                                         case ArgNone:
2607                                                 break;
2608                                         case ArgInIReg:
2609                                                 slot = param_reg_to_index [ainfo->pair_regs [i]];
2610                                                 p->regs [slot] = ((mgreg_t*)(arg))[i];
2611                                                 break;
2612                                         case ArgInDoubleSSEReg:
2613                                                 p->has_fp = 1;
2614                                                 p->fregs [ainfo->pair_regs [i]] = ((double*)(arg))[i];
2615                                                 break;
2616                                         default:
2617                                                 g_assert_not_reached ();
2618                                                 break;
2619                                         }
2620                                 }
2621                                 break;
2622                         case ArgOnStack:
2623                                 for (i = 0; i < ainfo->arg_size / 8; ++i)
2624                                         p->regs [slot + i] = ((mgreg_t*)(arg))[i];
2625                                 break;
2626                         default:
2627                                 g_assert_not_reached ();
2628                                 break;
2629                         }
2630                         break;
2631                 }
2632                 default:
2633                         g_assert_not_reached ();
2634                 }
2635         }
2636 }
2637
2638 /*
2639  * mono_arch_finish_dyn_call:
2640  *
2641  *   Store the result of a dyn call into the return value buffer passed to
2642  * start_dyn_call ().
2643  * This function should be as fast as possible, any work which does not depend
2644  * on the actual values of the arguments should be done in
2645  * mono_arch_dyn_call_prepare ().
2646  */
2647 void
2648 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2649 {
2650         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2651         MonoMethodSignature *sig = dinfo->sig;
2652         DynCallArgs *dargs = (DynCallArgs*)buf;
2653         guint8 *ret = dargs->ret;
2654         mgreg_t res = dargs->res;
2655         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2656         int i;
2657
2658         switch (sig_ret->type) {
2659         case MONO_TYPE_VOID:
2660                 *(gpointer*)ret = NULL;
2661                 break;
2662         case MONO_TYPE_OBJECT:
2663         case MONO_TYPE_I:
2664         case MONO_TYPE_U:
2665         case MONO_TYPE_PTR:
2666                 *(gpointer*)ret = GREG_TO_PTR(res);
2667                 break;
2668         case MONO_TYPE_I1:
2669                 *(gint8*)ret = res;
2670                 break;
2671         case MONO_TYPE_U1:
2672                 *(guint8*)ret = res;
2673                 break;
2674         case MONO_TYPE_I2:
2675                 *(gint16*)ret = res;
2676                 break;
2677         case MONO_TYPE_U2:
2678                 *(guint16*)ret = res;
2679                 break;
2680         case MONO_TYPE_I4:
2681                 *(gint32*)ret = res;
2682                 break;
2683         case MONO_TYPE_U4:
2684                 *(guint32*)ret = res;
2685                 break;
2686         case MONO_TYPE_I8:
2687                 *(gint64*)ret = res;
2688                 break;
2689         case MONO_TYPE_U8:
2690                 *(guint64*)ret = res;
2691                 break;
2692         case MONO_TYPE_R4:
2693                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2694                 break;
2695         case MONO_TYPE_R8:
2696                 *(double*)ret = dargs->fregs [0];
2697                 break;
2698         case MONO_TYPE_GENERICINST:
2699                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2700                         *(gpointer*)ret = GREG_TO_PTR(res);
2701                         break;
2702                 } else {
2703                         /* Fall through */
2704                 }
2705         case MONO_TYPE_VALUETYPE:
2706                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg || dinfo->cinfo->ret.storage == ArgGsharedvtVariableInReg) {
2707                         /* Nothing to do */
2708                 } else {
2709                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2710
2711                         g_assert (ainfo->storage == ArgValuetypeInReg);
2712
2713                         for (i = 0; i < 2; ++i) {
2714                                 switch (ainfo->pair_storage [0]) {
2715                                 case ArgInIReg:
2716                                         ((mgreg_t*)ret)[i] = res;
2717                                         break;
2718                                 case ArgInDoubleSSEReg:
2719                                         ((double*)ret)[i] = dargs->fregs [i];
2720                                         break;
2721                                 case ArgNone:
2722                                         break;
2723                                 default:
2724                                         g_assert_not_reached ();
2725                                         break;
2726                                 }
2727                         }
2728                 }
2729                 break;
2730         default:
2731                 g_assert_not_reached ();
2732         }
2733 }
2734
2735 /* emit an exception if condition is fail */
2736 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2737         do {                                                        \
2738                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2739                 if (tins == NULL) {                                                                             \
2740                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2741                                         MONO_PATCH_INFO_EXC, exc_name);  \
2742                         x86_branch32 (code, cond, 0, signed);               \
2743                 } else {        \
2744                         EMIT_COND_BRANCH (tins, cond, signed);  \
2745                 }                       \
2746         } while (0);
2747
2748 #define EMIT_FPCOMPARE(code) do { \
2749         amd64_fcompp (code); \
2750         amd64_fnstsw (code); \
2751 } while (0);
2752
2753 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2754     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2755         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2756         amd64_ ##op (code); \
2757         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2758         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2759 } while (0);
2760
2761 static guint8*
2762 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
2763 {
2764         gboolean no_patch = FALSE;
2765
2766         /*
2767          * FIXME: Add support for thunks
2768          */
2769         {
2770                 gboolean near_call = FALSE;
2771
2772                 /*
2773                  * Indirect calls are expensive so try to make a near call if possible.
2774                  * The caller memory is allocated by the code manager so it is
2775                  * guaranteed to be at a 32 bit offset.
2776                  */
2777
2778                 if (patch_type != MONO_PATCH_INFO_ABS) {
2779                         /* The target is in memory allocated using the code manager */
2780                         near_call = TRUE;
2781
2782                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2783                                 if (((MonoMethod*)data)->klass->image->aot_module)
2784                                         /* The callee might be an AOT method */
2785                                         near_call = FALSE;
2786                                 if (((MonoMethod*)data)->dynamic)
2787                                         /* The target is in malloc-ed memory */
2788                                         near_call = FALSE;
2789                         }
2790
2791                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2792                                 /*
2793                                  * The call might go directly to a native function without
2794                                  * the wrapper.
2795                                  */
2796                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
2797                                 if (mi) {
2798                                         gconstpointer target = mono_icall_get_wrapper (mi);
2799                                         if ((((guint64)target) >> 32) != 0)
2800                                                 near_call = FALSE;
2801                                 }
2802                         }
2803                 }
2804                 else {
2805                         MonoJumpInfo *jinfo = NULL;
2806
2807                         if (cfg->abs_patches)
2808                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
2809                         if (jinfo) {
2810                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
2811                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
2812                                         if (mi && (((guint64)mi->func) >> 32) == 0)
2813                                                 near_call = TRUE;
2814                                         no_patch = TRUE;
2815                                 } else {
2816                                         /*
2817                                          * This is not really an optimization, but required because the
2818                                          * generic class init trampolines use R11 to pass the vtable.
2819                                          */
2820                                         near_call = TRUE;
2821                                 }
2822                         } else {
2823                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2824                                 if (info) {
2825                                         if (info->func == info->wrapper) {
2826                                                 /* No wrapper */
2827                                                 if ((((guint64)info->func) >> 32) == 0)
2828                                                         near_call = TRUE;
2829                                         }
2830                                         else {
2831                                                 /* See the comment in mono_codegen () */
2832                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2833                                                         near_call = TRUE;
2834                                         }
2835                                 }
2836                                 else if ((((guint64)data) >> 32) == 0) {
2837                                         near_call = TRUE;
2838                                         no_patch = TRUE;
2839                                 }
2840                         }
2841                 }
2842
2843                 if (cfg->method->dynamic)
2844                         /* These methods are allocated using malloc */
2845                         near_call = FALSE;
2846
2847 #ifdef MONO_ARCH_NOMAP32BIT
2848                 near_call = FALSE;
2849 #endif
2850                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2851                 if (optimize_for_xen)
2852                         near_call = FALSE;
2853
2854                 if (cfg->compile_aot) {
2855                         near_call = TRUE;
2856                         no_patch = TRUE;
2857                 }
2858
2859                 if (near_call) {
2860                         /*
2861                          * Align the call displacement to an address divisible by 4 so it does
2862                          * not span cache lines. This is required for code patching to work on SMP
2863                          * systems.
2864                          */
2865                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
2866                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
2867                                 amd64_padding (code, pad_size);
2868                         }
2869                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2870                         amd64_call_code (code, 0);
2871                 }
2872                 else {
2873                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2874                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2875                         amd64_call_reg (code, GP_SCRATCH_REG);
2876                 }
2877         }
2878
2879         return code;
2880 }
2881
2882 static inline guint8*
2883 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
2884 {
2885 #ifdef TARGET_WIN32
2886         if (win64_adjust_stack)
2887                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2888 #endif
2889         code = emit_call_body (cfg, code, patch_type, data);
2890 #ifdef TARGET_WIN32
2891         if (win64_adjust_stack)
2892                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2893 #endif
2894
2895         return code;
2896 }
2897
2898 static inline int
2899 store_membase_imm_to_store_membase_reg (int opcode)
2900 {
2901         switch (opcode) {
2902         case OP_STORE_MEMBASE_IMM:
2903                 return OP_STORE_MEMBASE_REG;
2904         case OP_STOREI4_MEMBASE_IMM:
2905                 return OP_STOREI4_MEMBASE_REG;
2906         case OP_STOREI8_MEMBASE_IMM:
2907                 return OP_STOREI8_MEMBASE_REG;
2908         }
2909
2910         return -1;
2911 }
2912
2913 #ifndef DISABLE_JIT
2914
2915 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2916
2917 /*
2918  * mono_arch_peephole_pass_1:
2919  *
2920  *   Perform peephole opts which should/can be performed before local regalloc
2921  */
2922 void
2923 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2924 {
2925         MonoInst *ins, *n;
2926
2927         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2928                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
2929
2930                 switch (ins->opcode) {
2931                 case OP_ADD_IMM:
2932                 case OP_IADD_IMM:
2933                 case OP_LADD_IMM:
2934                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2935                                 /*
2936                                  * X86_LEA is like ADD, but doesn't have the
2937                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2938                                  * its operand to 64 bit.
2939                                  */
2940                                 ins->opcode = OP_X86_LEA_MEMBASE;
2941                                 ins->inst_basereg = ins->sreg1;
2942                         }
2943                         break;
2944                 case OP_LXOR:
2945                 case OP_IXOR:
2946                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2947                                 MonoInst *ins2;
2948
2949                                 /*
2950                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2951                                  * the latter has length 2-3 instead of 6 (reverse constant
2952                                  * propagation). These instruction sequences are very common
2953                                  * in the initlocals bblock.
2954                                  */
2955                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2956                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2957                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2958                                                 ins2->sreg1 = ins->dreg;
2959                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2960                                                 /* Continue */
2961                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2962                                                 NULLIFY_INS (ins2);
2963                                                 /* Continue */
2964                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
2965                                                 /* Continue */
2966                                         } else {
2967                                                 break;
2968                                         }
2969                                 }
2970                         }
2971                         break;
2972                 case OP_COMPARE_IMM:
2973                 case OP_LCOMPARE_IMM:
2974                         /* OP_COMPARE_IMM (reg, 0)
2975                          * -->
2976                          * OP_AMD64_TEST_NULL (reg)
2977                          */
2978                         if (!ins->inst_imm)
2979                                 ins->opcode = OP_AMD64_TEST_NULL;
2980                         break;
2981                 case OP_ICOMPARE_IMM:
2982                         if (!ins->inst_imm)
2983                                 ins->opcode = OP_X86_TEST_NULL;
2984                         break;
2985                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2986                         /*
2987                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2988                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2989                          * -->
2990                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2991                          * OP_COMPARE_IMM reg, imm
2992                          *
2993                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2994                          */
2995                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2996                             ins->inst_basereg == last_ins->inst_destbasereg &&
2997                             ins->inst_offset == last_ins->inst_offset) {
2998                                         ins->opcode = OP_ICOMPARE_IMM;
2999                                         ins->sreg1 = last_ins->sreg1;
3000
3001                                         /* check if we can remove cmp reg,0 with test null */
3002                                         if (!ins->inst_imm)
3003                                                 ins->opcode = OP_X86_TEST_NULL;
3004                                 }
3005
3006                         break;
3007                 }
3008
3009                 mono_peephole_ins (bb, ins);
3010         }
3011 }
3012
3013 void
3014 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3015 {
3016         MonoInst *ins, *n;
3017
3018         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3019                 switch (ins->opcode) {
3020                 case OP_ICONST:
3021                 case OP_I8CONST: {
3022                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3023                         /* reg = 0 -> XOR (reg, reg) */
3024                         /* XOR sets cflags on x86, so we cant do it always */
3025                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3026                                 ins->opcode = OP_LXOR;
3027                                 ins->sreg1 = ins->dreg;
3028                                 ins->sreg2 = ins->dreg;
3029                                 /* Fall through */
3030                         } else {
3031                                 break;
3032                         }
3033                 }
3034                 case OP_LXOR:
3035                         /*
3036                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3037                          * 0 result into 64 bits.
3038                          */
3039                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3040                                 ins->opcode = OP_IXOR;
3041                         }
3042                         /* Fall through */
3043                 case OP_IXOR:
3044                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3045                                 MonoInst *ins2;
3046
3047                                 /*
3048                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3049                                  * the latter has length 2-3 instead of 6 (reverse constant
3050                                  * propagation). These instruction sequences are very common
3051                                  * in the initlocals bblock.
3052                                  */
3053                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3054                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3055                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3056                                                 ins2->sreg1 = ins->dreg;
3057                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3058                                                 /* Continue */
3059                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3060                                                 NULLIFY_INS (ins2);
3061                                                 /* Continue */
3062                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3063                                                 /* Continue */
3064                                         } else {
3065                                                 break;
3066                                         }
3067                                 }
3068                         }
3069                         break;
3070                 case OP_IADD_IMM:
3071                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3072                                 ins->opcode = OP_X86_INC_REG;
3073                         break;
3074                 case OP_ISUB_IMM:
3075                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3076                                 ins->opcode = OP_X86_DEC_REG;
3077                         break;
3078                 }
3079
3080                 mono_peephole_ins (bb, ins);
3081         }
3082 }
3083
3084 #define NEW_INS(cfg,ins,dest,op) do {   \
3085                 MONO_INST_NEW ((cfg), (dest), (op)); \
3086         (dest)->cil_code = (ins)->cil_code; \
3087         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3088         } while (0)
3089
3090 /*
3091  * mono_arch_lowering_pass:
3092  *
3093  *  Converts complex opcodes into simpler ones so that each IR instruction
3094  * corresponds to one machine instruction.
3095  */
3096 void
3097 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3098 {
3099         MonoInst *ins, *n, *temp;
3100
3101         /*
3102          * FIXME: Need to add more instructions, but the current machine
3103          * description can't model some parts of the composite instructions like
3104          * cdq.
3105          */
3106         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3107                 switch (ins->opcode) {
3108                 case OP_DIV_IMM:
3109                 case OP_REM_IMM:
3110                 case OP_IDIV_IMM:
3111                 case OP_IDIV_UN_IMM:
3112                 case OP_IREM_UN_IMM:
3113                 case OP_LREM_IMM:
3114                 case OP_IREM_IMM:
3115                         mono_decompose_op_imm (cfg, bb, ins);
3116                         break;
3117                 case OP_COMPARE_IMM:
3118                 case OP_LCOMPARE_IMM:
3119                         if (!amd64_use_imm32 (ins->inst_imm)) {
3120                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3121                                 temp->inst_c0 = ins->inst_imm;
3122                                 temp->dreg = mono_alloc_ireg (cfg);
3123                                 ins->opcode = OP_COMPARE;
3124                                 ins->sreg2 = temp->dreg;
3125                         }
3126                         break;
3127 #ifndef __mono_ilp32__
3128                 case OP_LOAD_MEMBASE:
3129 #endif
3130                 case OP_LOADI8_MEMBASE:
3131                 /*  Don't generate memindex opcodes (to simplify */
3132                 /*  read sandboxing) */
3133                         if (!amd64_use_imm32 (ins->inst_offset)) {
3134                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3135                                 temp->inst_c0 = ins->inst_offset;
3136                                 temp->dreg = mono_alloc_ireg (cfg);
3137                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3138                                 ins->inst_indexreg = temp->dreg;
3139                         }
3140                         break;
3141 #ifndef __mono_ilp32__
3142                 case OP_STORE_MEMBASE_IMM:
3143 #endif
3144                 case OP_STOREI8_MEMBASE_IMM:
3145                         if (!amd64_use_imm32 (ins->inst_imm)) {
3146                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3147                                 temp->inst_c0 = ins->inst_imm;
3148                                 temp->dreg = mono_alloc_ireg (cfg);
3149                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3150                                 ins->sreg1 = temp->dreg;
3151                         }
3152                         break;
3153 #ifdef MONO_ARCH_SIMD_INTRINSICS
3154                 case OP_EXPAND_I1: {
3155                                 int temp_reg1 = mono_alloc_ireg (cfg);
3156                                 int temp_reg2 = mono_alloc_ireg (cfg);
3157                                 int original_reg = ins->sreg1;
3158
3159                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3160                                 temp->sreg1 = original_reg;
3161                                 temp->dreg = temp_reg1;
3162
3163                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3164                                 temp->sreg1 = temp_reg1;
3165                                 temp->dreg = temp_reg2;
3166                                 temp->inst_imm = 8;
3167
3168                                 NEW_INS (cfg, ins, temp, OP_LOR);
3169                                 temp->sreg1 = temp->dreg = temp_reg2;
3170                                 temp->sreg2 = temp_reg1;
3171
3172                                 ins->opcode = OP_EXPAND_I2;
3173                                 ins->sreg1 = temp_reg2;
3174                         }
3175                         break;
3176 #endif
3177                 default:
3178                         break;
3179                 }
3180         }
3181
3182         bb->max_vreg = cfg->next_vreg;
3183 }
3184
3185 static const int
3186 branch_cc_table [] = {
3187         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3188         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3189         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3190 };
3191
3192 /* Maps CMP_... constants to X86_CC_... constants */
3193 static const int
3194 cc_table [] = {
3195         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3196         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3197 };
3198
3199 static const int
3200 cc_signed_table [] = {
3201         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3202         FALSE, FALSE, FALSE, FALSE
3203 };
3204
3205 /*#include "cprop.c"*/
3206
3207 static unsigned char*
3208 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3209 {
3210         if (size == 8)
3211                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3212         else
3213                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3214
3215         if (size == 1)
3216                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3217         else if (size == 2)
3218                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3219         return code;
3220 }
3221
3222 static unsigned char*
3223 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3224 {
3225         int sreg = tree->sreg1;
3226         int need_touch = FALSE;
3227
3228 #if defined(TARGET_WIN32)
3229         need_touch = TRUE;
3230 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3231         if (!(tree->flags & MONO_INST_INIT))
3232                 need_touch = TRUE;
3233 #endif
3234
3235         if (need_touch) {
3236                 guint8* br[5];
3237
3238                 /*
3239                  * Under Windows:
3240                  * If requested stack size is larger than one page,
3241                  * perform stack-touch operation
3242                  */
3243                 /*
3244                  * Generate stack probe code.
3245                  * Under Windows, it is necessary to allocate one page at a time,
3246                  * "touching" stack after each successful sub-allocation. This is
3247                  * because of the way stack growth is implemented - there is a
3248                  * guard page before the lowest stack page that is currently commited.
3249                  * Stack normally grows sequentially so OS traps access to the
3250                  * guard page and commits more pages when needed.
3251                  */
3252                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3253                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3254
3255                 br[2] = code; /* loop */
3256                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3257                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3258                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3259                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3260                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3261                 amd64_patch (br[3], br[2]);
3262                 amd64_test_reg_reg (code, sreg, sreg);
3263                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3264                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3265
3266                 br[1] = code; x86_jump8 (code, 0);
3267
3268                 amd64_patch (br[0], code);
3269                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3270                 amd64_patch (br[1], code);
3271                 amd64_patch (br[4], code);
3272         }
3273         else
3274                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3275
3276         if (tree->flags & MONO_INST_INIT) {
3277                 int offset = 0;
3278                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3279                         amd64_push_reg (code, AMD64_RAX);
3280                         offset += 8;
3281                 }
3282                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3283                         amd64_push_reg (code, AMD64_RCX);
3284                         offset += 8;
3285                 }
3286                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3287                         amd64_push_reg (code, AMD64_RDI);
3288                         offset += 8;
3289                 }
3290
3291                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3292                 if (sreg != AMD64_RCX)
3293                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3294                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3295
3296                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3297                 if (cfg->param_area)
3298                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3299                 amd64_cld (code);
3300                 amd64_prefix (code, X86_REP_PREFIX);
3301                 amd64_stosl (code);
3302
3303                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3304                         amd64_pop_reg (code, AMD64_RDI);
3305                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3306                         amd64_pop_reg (code, AMD64_RCX);
3307                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3308                         amd64_pop_reg (code, AMD64_RAX);
3309         }
3310         return code;
3311 }
3312
3313 static guint8*
3314 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3315 {
3316         CallInfo *cinfo;
3317         guint32 quad;
3318
3319         /* Move return value to the target register */
3320         /* FIXME: do this in the local reg allocator */
3321         switch (ins->opcode) {
3322         case OP_CALL:
3323         case OP_CALL_REG:
3324         case OP_CALL_MEMBASE:
3325         case OP_LCALL:
3326         case OP_LCALL_REG:
3327         case OP_LCALL_MEMBASE:
3328                 g_assert (ins->dreg == AMD64_RAX);
3329                 break;
3330         case OP_FCALL:
3331         case OP_FCALL_REG:
3332         case OP_FCALL_MEMBASE: {
3333                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3334                 if (rtype->type == MONO_TYPE_R4) {
3335                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3336                 }
3337                 else {
3338                         if (ins->dreg != AMD64_XMM0)
3339                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3340                 }
3341                 break;
3342         }
3343         case OP_RCALL:
3344         case OP_RCALL_REG:
3345         case OP_RCALL_MEMBASE:
3346                 if (ins->dreg != AMD64_XMM0)
3347                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3348                 break;
3349         case OP_VCALL:
3350         case OP_VCALL_REG:
3351         case OP_VCALL_MEMBASE:
3352         case OP_VCALL2:
3353         case OP_VCALL2_REG:
3354         case OP_VCALL2_MEMBASE:
3355                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3356                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3357                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3358
3359                         /* Load the destination address */
3360                         g_assert (loc->opcode == OP_REGOFFSET);
3361                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3362
3363                         for (quad = 0; quad < 2; quad ++) {
3364                                 switch (cinfo->ret.pair_storage [quad]) {
3365                                 case ArgInIReg:
3366                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3367                                         break;
3368                                 case ArgInFloatSSEReg:
3369                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3370                                         break;
3371                                 case ArgInDoubleSSEReg:
3372                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3373                                         break;
3374                                 case ArgNone:
3375                                         break;
3376                                 default:
3377                                         NOT_IMPLEMENTED;
3378                                 }
3379                         }
3380                 }
3381                 break;
3382         }
3383
3384         return code;
3385 }
3386
3387 #endif /* DISABLE_JIT */
3388
3389 #ifdef TARGET_MACH
3390 static int tls_gs_offset;
3391 #endif
3392
3393 gboolean
3394 mono_arch_have_fast_tls (void)
3395 {
3396 #ifdef TARGET_MACH
3397         static gboolean have_fast_tls = FALSE;
3398         static gboolean inited = FALSE;
3399         guint8 *ins;
3400
3401         if (mini_get_debug_options ()->use_fallback_tls)
3402                 return FALSE;
3403
3404         if (inited)
3405                 return have_fast_tls;
3406
3407         ins = (guint8*)pthread_getspecific;
3408
3409         /*
3410          * We're looking for these two instructions:
3411          *
3412          * mov    %gs:[offset](,%rdi,8),%rax
3413          * retq
3414          */
3415         have_fast_tls = ins [0] == 0x65 &&
3416                        ins [1] == 0x48 &&
3417                        ins [2] == 0x8b &&
3418                        ins [3] == 0x04 &&
3419                        ins [4] == 0xfd &&
3420                        ins [6] == 0x00 &&
3421                        ins [7] == 0x00 &&
3422                        ins [8] == 0x00 &&
3423                        ins [9] == 0xc3;
3424
3425         tls_gs_offset = ins[5];
3426
3427         /*
3428          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3429          * For that version we're looking for these instructions:
3430          *
3431          * pushq  %rbp
3432          * movq   %rsp, %rbp
3433          * mov    %gs:[offset](,%rdi,8),%rax
3434          * popq   %rbp
3435          * retq
3436          */
3437         if (!have_fast_tls) {
3438                 have_fast_tls = ins [0] == 0x55 &&
3439                                ins [1] == 0x48 &&
3440                                ins [2] == 0x89 &&
3441                                ins [3] == 0xe5 &&
3442                                ins [4] == 0x65 &&
3443                                ins [5] == 0x48 &&
3444                                ins [6] == 0x8b &&
3445                                ins [7] == 0x04 &&
3446                                ins [8] == 0xfd &&
3447                                ins [10] == 0x00 &&
3448                                ins [11] == 0x00 &&
3449                                ins [12] == 0x00 &&
3450                                ins [13] == 0x5d &&
3451                                ins [14] == 0xc3;
3452
3453                 tls_gs_offset = ins[9];
3454         }
3455         inited = TRUE;
3456
3457         return have_fast_tls;
3458 #elif defined(TARGET_ANDROID)
3459         return FALSE;
3460 #else
3461         if (mini_get_debug_options ()->use_fallback_tls)
3462                 return FALSE;
3463         return TRUE;
3464 #endif
3465 }
3466
3467 int
3468 mono_amd64_get_tls_gs_offset (void)
3469 {
3470 #ifdef TARGET_OSX
3471         return tls_gs_offset;
3472 #else
3473         g_assert_not_reached ();
3474         return -1;
3475 #endif
3476 }
3477
3478 /*
3479  * \param code buffer to store code to
3480  * \param dreg hard register where to place the result
3481  * \param tls_offset offset info
3482  * \return a pointer to the end of the stored code
3483  *
3484  * mono_amd64_emit_tls_get emits in \p code the native code that puts in
3485  * the dreg register the item in the thread local storage identified
3486  * by tls_offset.
3487  */
3488 static guint8*
3489 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3490 {
3491 #ifdef TARGET_WIN32
3492         if (tls_offset < 64) {
3493                 x86_prefix (code, X86_GS_PREFIX);
3494                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3495         } else {
3496                 guint8 *buf [16];
3497
3498                 g_assert (tls_offset < 0x440);
3499                 /* Load TEB->TlsExpansionSlots */
3500                 x86_prefix (code, X86_GS_PREFIX);
3501                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3502                 amd64_test_reg_reg (code, dreg, dreg);
3503                 buf [0] = code;
3504                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3505                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3506                 amd64_patch (buf [0], code);
3507         }
3508 #elif defined(TARGET_MACH)
3509         x86_prefix (code, X86_GS_PREFIX);
3510         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3511 #else
3512         if (optimize_for_xen) {
3513                 x86_prefix (code, X86_FS_PREFIX);
3514                 amd64_mov_reg_mem (code, dreg, 0, 8);
3515                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3516         } else {
3517                 x86_prefix (code, X86_FS_PREFIX);
3518                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3519         }
3520 #endif
3521         return code;
3522 }
3523
3524 static guint8*
3525 mono_amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3526 {
3527 #ifdef TARGET_WIN32
3528         g_assert_not_reached ();
3529 #elif defined(TARGET_MACH)
3530         x86_prefix (code, X86_GS_PREFIX);
3531         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3532 #else
3533         g_assert (!optimize_for_xen);
3534         x86_prefix (code, X86_FS_PREFIX);
3535         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3536 #endif
3537         return code;
3538 }
3539
3540 /*
3541  * emit_setup_lmf:
3542  *
3543  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3544  */
3545 static guint8*
3546 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3547 {
3548         /*
3549          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3550          */
3551         /*
3552          * sp is saved right before calls but we need to save it here too so
3553          * async stack walks would work.
3554          */
3555         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3556         /* Save rbp */
3557         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3558         if (cfg->arch.omit_fp && cfa_offset != -1)
3559                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3560
3561         /* These can't contain refs */
3562         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3563         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3564         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3565         /* These are handled automatically by the stack marking code */
3566         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3567
3568         return code;
3569 }
3570
3571 #ifdef TARGET_WIN32
3572
3573 #define TEB_LAST_ERROR_OFFSET 0x068
3574
3575 static guint8*
3576 emit_get_last_error (guint8* code, int dreg)
3577 {
3578         /* Threads last error value is located in TEB_LAST_ERROR_OFFSET. */
3579         x86_prefix (code, X86_GS_PREFIX);
3580         amd64_mov_reg_membase (code, dreg, TEB_LAST_ERROR_OFFSET, 0, sizeof (guint32));
3581
3582         return code;
3583 }
3584
3585 #else
3586
3587 static guint8*
3588 emit_get_last_error (guint8* code, int dreg)
3589 {
3590         g_assert_not_reached ();
3591 }
3592
3593 #endif
3594
3595 /* benchmark and set based on cpu */
3596 #define LOOP_ALIGNMENT 8
3597 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3598
3599 #ifndef DISABLE_JIT
3600 void
3601 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3602 {
3603         MonoInst *ins;
3604         MonoCallInst *call;
3605         guint offset;
3606         guint8 *code = cfg->native_code + cfg->code_len;
3607         int max_len;
3608
3609         /* Fix max_offset estimate for each successor bb */
3610         if (cfg->opt & MONO_OPT_BRANCH) {
3611                 int current_offset = cfg->code_len;
3612                 MonoBasicBlock *current_bb;
3613                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3614                         current_bb->max_offset = current_offset;
3615                         current_offset += current_bb->max_length;
3616                 }
3617         }
3618
3619         if (cfg->opt & MONO_OPT_LOOP) {
3620                 int pad, align = LOOP_ALIGNMENT;
3621                 /* set alignment depending on cpu */
3622                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3623                         pad = align - pad;
3624                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3625                         amd64_padding (code, pad);
3626                         cfg->code_len += pad;
3627                         bb->native_offset = cfg->code_len;
3628                 }
3629         }
3630
3631         if (cfg->verbose_level > 2)
3632                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3633
3634         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3635                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3636                 g_assert (!cfg->compile_aot);
3637
3638                 cov->data [bb->dfn].cil_code = bb->cil_code;
3639                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3640                 /* this is not thread save, but good enough */
3641                 amd64_inc_membase (code, AMD64_R11, 0);
3642         }
3643
3644         offset = code - cfg->native_code;
3645
3646         mono_debug_open_block (cfg, bb, offset);
3647
3648     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3649                 x86_breakpoint (code);
3650
3651         MONO_BB_FOR_EACH_INS (bb, ins) {
3652                 offset = code - cfg->native_code;
3653
3654                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3655
3656 #define EXTRA_CODE_SPACE (16)
3657
3658                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3659                         cfg->code_size *= 2;
3660                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3661                         code = cfg->native_code + offset;
3662                         cfg->stat_code_reallocs++;
3663                 }
3664
3665                 if (cfg->debug_info)
3666                         mono_debug_record_line_number (cfg, ins, offset);
3667
3668                 switch (ins->opcode) {
3669                 case OP_BIGMUL:
3670                         amd64_mul_reg (code, ins->sreg2, TRUE);
3671                         break;
3672                 case OP_BIGMUL_UN:
3673                         amd64_mul_reg (code, ins->sreg2, FALSE);
3674                         break;
3675                 case OP_X86_SETEQ_MEMBASE:
3676                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3677                         break;
3678                 case OP_STOREI1_MEMBASE_IMM:
3679                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3680                         break;
3681                 case OP_STOREI2_MEMBASE_IMM:
3682                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3683                         break;
3684                 case OP_STOREI4_MEMBASE_IMM:
3685                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3686                         break;
3687                 case OP_STOREI1_MEMBASE_REG:
3688                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3689                         break;
3690                 case OP_STOREI2_MEMBASE_REG:
3691                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3692                         break;
3693                 /* In AMD64 NaCl, pointers are 4 bytes, */
3694                 /*  so STORE_* != STOREI8_*. Likewise below. */
3695                 case OP_STORE_MEMBASE_REG:
3696                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
3697                         break;
3698                 case OP_STOREI8_MEMBASE_REG:
3699                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3700                         break;
3701                 case OP_STOREI4_MEMBASE_REG:
3702                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3703                         break;
3704                 case OP_STORE_MEMBASE_IMM:
3705                         /* In NaCl, this could be a PCONST type, which could */
3706                         /* mean a pointer type was copied directly into the  */
3707                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
3708                         /* the value would be 0x00000000FFFFFFFF which is    */
3709                         /* not proper for an imm32 unless you cast it.       */
3710                         g_assert (amd64_is_imm32 (ins->inst_imm));
3711                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
3712                         break;
3713                 case OP_STOREI8_MEMBASE_IMM:
3714                         g_assert (amd64_is_imm32 (ins->inst_imm));
3715                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3716                         break;
3717                 case OP_LOAD_MEM:
3718 #ifdef __mono_ilp32__
3719                         /* In ILP32, pointers are 4 bytes, so separate these */
3720                         /* cases, use literal 8 below where we really want 8 */
3721                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3722                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
3723                         break;
3724 #endif
3725                 case OP_LOADI8_MEM:
3726                         // FIXME: Decompose this earlier
3727                         if (amd64_use_imm32 (ins->inst_imm))
3728                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
3729                         else {
3730                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3731                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3732                         }
3733                         break;
3734                 case OP_LOADI4_MEM:
3735                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3736                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3737                         break;
3738                 case OP_LOADU4_MEM:
3739                         // FIXME: Decompose this earlier
3740                         if (amd64_use_imm32 (ins->inst_imm))
3741                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3742                         else {
3743                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
3744                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3745                         }
3746                         break;
3747                 case OP_LOADU1_MEM:
3748                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3749                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3750                         break;
3751                 case OP_LOADU2_MEM:
3752                         /* For NaCl, pointers are 4 bytes, so separate these */
3753                         /* cases, use literal 8 below where we really want 8 */
3754                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3755                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3756                         break;
3757                 case OP_LOAD_MEMBASE:
3758                         g_assert (amd64_is_imm32 (ins->inst_offset));
3759                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
3760                         break;
3761                 case OP_LOADI8_MEMBASE:
3762                         /* Use literal 8 instead of sizeof pointer or */
3763                         /* register, we really want 8 for this opcode */
3764                         g_assert (amd64_is_imm32 (ins->inst_offset));
3765                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
3766                         break;
3767                 case OP_LOADI4_MEMBASE:
3768                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3769                         break;
3770                 case OP_LOADU4_MEMBASE:
3771                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3772                         break;
3773                 case OP_LOADU1_MEMBASE:
3774                         /* The cpu zero extends the result into 64 bits */
3775                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3776                         break;
3777                 case OP_LOADI1_MEMBASE:
3778                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3779                         break;
3780                 case OP_LOADU2_MEMBASE:
3781                         /* The cpu zero extends the result into 64 bits */
3782                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3783                         break;
3784                 case OP_LOADI2_MEMBASE:
3785                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3786                         break;
3787                 case OP_AMD64_LOADI8_MEMINDEX:
3788                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3789                         break;
3790                 case OP_LCONV_TO_I1:
3791                 case OP_ICONV_TO_I1:
3792                 case OP_SEXT_I1:
3793                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3794                         break;
3795                 case OP_LCONV_TO_I2:
3796                 case OP_ICONV_TO_I2:
3797                 case OP_SEXT_I2:
3798                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3799                         break;
3800                 case OP_LCONV_TO_U1:
3801                 case OP_ICONV_TO_U1:
3802                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3803                         break;
3804                 case OP_LCONV_TO_U2:
3805                 case OP_ICONV_TO_U2:
3806                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3807                         break;
3808                 case OP_ZEXT_I4:
3809                         /* Clean out the upper word */
3810                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3811                         break;
3812                 case OP_SEXT_I4:
3813                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3814                         break;
3815                 case OP_COMPARE:
3816                 case OP_LCOMPARE:
3817                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3818                         break;
3819                 case OP_COMPARE_IMM:
3820 #if defined(__mono_ilp32__)
3821                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
3822                         g_assert (amd64_is_imm32 (ins->inst_imm));
3823                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3824                         break;
3825 #endif
3826                 case OP_LCOMPARE_IMM:
3827                         g_assert (amd64_is_imm32 (ins->inst_imm));
3828                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3829                         break;
3830                 case OP_X86_COMPARE_REG_MEMBASE:
3831                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3832                         break;
3833                 case OP_X86_TEST_NULL:
3834                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3835                         break;
3836                 case OP_AMD64_TEST_NULL:
3837                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3838                         break;
3839
3840                 case OP_X86_ADD_REG_MEMBASE:
3841                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3842                         break;
3843                 case OP_X86_SUB_REG_MEMBASE:
3844                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3845                         break;
3846                 case OP_X86_AND_REG_MEMBASE:
3847                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3848                         break;
3849                 case OP_X86_OR_REG_MEMBASE:
3850                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3851                         break;
3852                 case OP_X86_XOR_REG_MEMBASE:
3853                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3854                         break;
3855
3856                 case OP_X86_ADD_MEMBASE_IMM:
3857                         /* FIXME: Make a 64 version too */
3858                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3859                         break;
3860                 case OP_X86_SUB_MEMBASE_IMM:
3861                         g_assert (amd64_is_imm32 (ins->inst_imm));
3862                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3863                         break;
3864                 case OP_X86_AND_MEMBASE_IMM:
3865                         g_assert (amd64_is_imm32 (ins->inst_imm));
3866                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3867                         break;
3868                 case OP_X86_OR_MEMBASE_IMM:
3869                         g_assert (amd64_is_imm32 (ins->inst_imm));
3870                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3871                         break;
3872                 case OP_X86_XOR_MEMBASE_IMM:
3873                         g_assert (amd64_is_imm32 (ins->inst_imm));
3874                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3875                         break;
3876                 case OP_X86_ADD_MEMBASE_REG:
3877                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3878                         break;
3879                 case OP_X86_SUB_MEMBASE_REG:
3880                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3881                         break;
3882                 case OP_X86_AND_MEMBASE_REG:
3883                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3884                         break;
3885                 case OP_X86_OR_MEMBASE_REG:
3886                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3887                         break;
3888                 case OP_X86_XOR_MEMBASE_REG:
3889                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3890                         break;
3891                 case OP_X86_INC_MEMBASE:
3892                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3893                         break;
3894                 case OP_X86_INC_REG:
3895                         amd64_inc_reg_size (code, ins->dreg, 4);
3896                         break;
3897                 case OP_X86_DEC_MEMBASE:
3898                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3899                         break;
3900                 case OP_X86_DEC_REG:
3901                         amd64_dec_reg_size (code, ins->dreg, 4);
3902                         break;
3903                 case OP_X86_MUL_REG_MEMBASE:
3904                 case OP_X86_MUL_MEMBASE_REG:
3905                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3906                         break;
3907                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3908                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3909                         break;
3910                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3911                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3912                         break;
3913                 case OP_AMD64_COMPARE_MEMBASE_REG:
3914                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3915                         break;
3916                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3917                         g_assert (amd64_is_imm32 (ins->inst_imm));
3918                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3919                         break;
3920                 case OP_X86_COMPARE_MEMBASE8_IMM:
3921                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3922                         break;
3923                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3924                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3925                         break;
3926                 case OP_AMD64_COMPARE_REG_MEMBASE:
3927                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3928                         break;
3929
3930                 case OP_AMD64_ADD_REG_MEMBASE:
3931                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3932                         break;
3933                 case OP_AMD64_SUB_REG_MEMBASE:
3934                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3935                         break;
3936                 case OP_AMD64_AND_REG_MEMBASE:
3937                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3938                         break;
3939                 case OP_AMD64_OR_REG_MEMBASE:
3940                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3941                         break;
3942                 case OP_AMD64_XOR_REG_MEMBASE:
3943                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3944                         break;
3945
3946                 case OP_AMD64_ADD_MEMBASE_REG:
3947                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3948                         break;
3949                 case OP_AMD64_SUB_MEMBASE_REG:
3950                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3951                         break;
3952                 case OP_AMD64_AND_MEMBASE_REG:
3953                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3954                         break;
3955                 case OP_AMD64_OR_MEMBASE_REG:
3956                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3957                         break;
3958                 case OP_AMD64_XOR_MEMBASE_REG:
3959                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3960                         break;
3961
3962                 case OP_AMD64_ADD_MEMBASE_IMM:
3963                         g_assert (amd64_is_imm32 (ins->inst_imm));
3964                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3965                         break;
3966                 case OP_AMD64_SUB_MEMBASE_IMM:
3967                         g_assert (amd64_is_imm32 (ins->inst_imm));
3968                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3969                         break;
3970                 case OP_AMD64_AND_MEMBASE_IMM:
3971                         g_assert (amd64_is_imm32 (ins->inst_imm));
3972                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3973                         break;
3974                 case OP_AMD64_OR_MEMBASE_IMM:
3975                         g_assert (amd64_is_imm32 (ins->inst_imm));
3976                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3977                         break;
3978                 case OP_AMD64_XOR_MEMBASE_IMM:
3979                         g_assert (amd64_is_imm32 (ins->inst_imm));
3980                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3981                         break;
3982
3983                 case OP_BREAK:
3984                         amd64_breakpoint (code);
3985                         break;
3986                 case OP_RELAXED_NOP:
3987                         x86_prefix (code, X86_REP_PREFIX);
3988                         x86_nop (code);
3989                         break;
3990                 case OP_HARD_NOP:
3991                         x86_nop (code);
3992                         break;
3993                 case OP_NOP:
3994                 case OP_DUMMY_USE:
3995                 case OP_DUMMY_STORE:
3996                 case OP_DUMMY_ICONST:
3997                 case OP_DUMMY_R8CONST:
3998                 case OP_NOT_REACHED:
3999                 case OP_NOT_NULL:
4000                         break;
4001                 case OP_IL_SEQ_POINT:
4002                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4003                         break;
4004                 case OP_SEQ_POINT: {
4005                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4006                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4007                                 guint8 *label;
4008
4009                                 /* Load ss_tramp_var */
4010                                 /* This is equal to &ss_trampoline */
4011                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4012                                 /* Load the trampoline address */
4013                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4014                                 /* Call it if it is non-null */
4015                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4016                                 label = code;
4017                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4018                                 amd64_call_reg (code, AMD64_R11);
4019                                 amd64_patch (label, code);
4020                         }
4021
4022                         /*
4023                          * This is the address which is saved in seq points,
4024                          */
4025                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4026
4027                         if (cfg->compile_aot) {
4028                                 guint32 offset = code - cfg->native_code;
4029                                 guint32 val;
4030                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4031                                 guint8 *label;
4032
4033                                 /* Load info var */
4034                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4035                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4036                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4037                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4038                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4039                                 label = code;
4040                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4041                                 /* Call the trampoline */
4042                                 amd64_call_reg (code, AMD64_R11);
4043                                 amd64_patch (label, code);
4044                         } else {
4045                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4046                                 guint8 *label;
4047
4048                                 /*
4049                                  * Emit a test+branch against a constant, the constant will be overwritten
4050                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4051                                  */
4052                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4053                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4054                                 label = code;
4055                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4056
4057                                 g_assert (var);
4058                                 g_assert (var->opcode == OP_REGOFFSET);
4059                                 /* Load bp_tramp_var */
4060                                 /* This is equal to &bp_trampoline */
4061                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4062                                 /* Call the trampoline */
4063                                 amd64_call_membase (code, AMD64_R11, 0);
4064                                 amd64_patch (label, code);
4065                         }
4066                         /*
4067                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4068                          * to another IL offset.
4069                          */
4070                         x86_nop (code);
4071                         break;
4072                 }
4073                 case OP_ADDCC:
4074                 case OP_LADDCC:
4075                 case OP_LADD:
4076                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4077                         break;
4078                 case OP_ADC:
4079                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4080                         break;
4081                 case OP_ADD_IMM:
4082                 case OP_LADD_IMM:
4083                         g_assert (amd64_is_imm32 (ins->inst_imm));
4084                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4085                         break;
4086                 case OP_ADC_IMM:
4087                         g_assert (amd64_is_imm32 (ins->inst_imm));
4088                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4089                         break;
4090                 case OP_SUBCC:
4091                 case OP_LSUBCC:
4092                 case OP_LSUB:
4093                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4094                         break;
4095                 case OP_SBB:
4096                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4097                         break;
4098                 case OP_SUB_IMM:
4099                 case OP_LSUB_IMM:
4100                         g_assert (amd64_is_imm32 (ins->inst_imm));
4101                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4102                         break;
4103                 case OP_SBB_IMM:
4104                         g_assert (amd64_is_imm32 (ins->inst_imm));
4105                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4106                         break;
4107                 case OP_LAND:
4108                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4109                         break;
4110                 case OP_AND_IMM:
4111                 case OP_LAND_IMM:
4112                         g_assert (amd64_is_imm32 (ins->inst_imm));
4113                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4114                         break;
4115                 case OP_LMUL:
4116                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4117                         break;
4118                 case OP_MUL_IMM:
4119                 case OP_LMUL_IMM:
4120                 case OP_IMUL_IMM: {
4121                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4122
4123                         switch (ins->inst_imm) {
4124                         case 2:
4125                                 /* MOV r1, r2 */
4126                                 /* ADD r1, r1 */
4127                                 if (ins->dreg != ins->sreg1)
4128                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4129                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4130                                 break;
4131                         case 3:
4132                                 /* LEA r1, [r2 + r2*2] */
4133                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4134                                 break;
4135                         case 5:
4136                                 /* LEA r1, [r2 + r2*4] */
4137                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4138                                 break;
4139                         case 6:
4140                                 /* LEA r1, [r2 + r2*2] */
4141                                 /* ADD r1, r1          */
4142                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4143                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4144                                 break;
4145                         case 9:
4146                                 /* LEA r1, [r2 + r2*8] */
4147                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4148                                 break;
4149                         case 10:
4150                                 /* LEA r1, [r2 + r2*4] */
4151                                 /* ADD r1, r1          */
4152                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4153                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4154                                 break;
4155                         case 12:
4156                                 /* LEA r1, [r2 + r2*2] */
4157                                 /* SHL r1, 2           */
4158                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4159                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4160                                 break;
4161                         case 25:
4162                                 /* LEA r1, [r2 + r2*4] */
4163                                 /* LEA r1, [r1 + r1*4] */
4164                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4165                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4166                                 break;
4167                         case 100:
4168                                 /* LEA r1, [r2 + r2*4] */
4169                                 /* SHL r1, 2           */
4170                                 /* LEA r1, [r1 + r1*4] */
4171                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4172                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4173                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4174                                 break;
4175                         default:
4176                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4177                                 break;
4178                         }
4179                         break;
4180                 }
4181                 case OP_LDIV:
4182                 case OP_LREM:
4183                         /* Regalloc magic makes the div/rem cases the same */
4184                         if (ins->sreg2 == AMD64_RDX) {
4185                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4186                                 amd64_cdq (code);
4187                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4188                         } else {
4189                                 amd64_cdq (code);
4190                                 amd64_div_reg (code, ins->sreg2, TRUE);
4191                         }
4192                         break;
4193                 case OP_LDIV_UN:
4194                 case OP_LREM_UN:
4195                         if (ins->sreg2 == AMD64_RDX) {
4196                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4197                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4198                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4199                         } else {
4200                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4201                                 amd64_div_reg (code, ins->sreg2, FALSE);
4202                         }
4203                         break;
4204                 case OP_IDIV:
4205                 case OP_IREM:
4206                         if (ins->sreg2 == AMD64_RDX) {
4207                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4208                                 amd64_cdq_size (code, 4);
4209                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4210                         } else {
4211                                 amd64_cdq_size (code, 4);
4212                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4213                         }
4214                         break;
4215                 case OP_IDIV_UN:
4216                 case OP_IREM_UN:
4217                         if (ins->sreg2 == AMD64_RDX) {
4218                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4219                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4220                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4221                         } else {
4222                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4223                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4224                         }
4225                         break;
4226                 case OP_LMUL_OVF:
4227                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4228                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4229                         break;
4230                 case OP_LOR:
4231                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4232                         break;
4233                 case OP_OR_IMM:
4234                 case OP_LOR_IMM:
4235                         g_assert (amd64_is_imm32 (ins->inst_imm));
4236                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4237                         break;
4238                 case OP_LXOR:
4239                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4240                         break;
4241                 case OP_XOR_IMM:
4242                 case OP_LXOR_IMM:
4243                         g_assert (amd64_is_imm32 (ins->inst_imm));
4244                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4245                         break;
4246                 case OP_LSHL:
4247                         g_assert (ins->sreg2 == AMD64_RCX);
4248                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4249                         break;
4250                 case OP_LSHR:
4251                         g_assert (ins->sreg2 == AMD64_RCX);
4252                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4253                         break;
4254                 case OP_SHR_IMM:
4255                 case OP_LSHR_IMM:
4256                         g_assert (amd64_is_imm32 (ins->inst_imm));
4257                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4258                         break;
4259                 case OP_SHR_UN_IMM:
4260                         g_assert (amd64_is_imm32 (ins->inst_imm));
4261                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4262                         break;
4263                 case OP_LSHR_UN_IMM:
4264                         g_assert (amd64_is_imm32 (ins->inst_imm));
4265                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4266                         break;
4267                 case OP_LSHR_UN:
4268                         g_assert (ins->sreg2 == AMD64_RCX);
4269                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4270                         break;
4271                 case OP_SHL_IMM:
4272                 case OP_LSHL_IMM:
4273                         g_assert (amd64_is_imm32 (ins->inst_imm));
4274                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4275                         break;
4276
4277                 case OP_IADDCC:
4278                 case OP_IADD:
4279                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4280                         break;
4281                 case OP_IADC:
4282                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4283                         break;
4284                 case OP_IADD_IMM:
4285                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4286                         break;
4287                 case OP_IADC_IMM:
4288                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4289                         break;
4290                 case OP_ISUBCC:
4291                 case OP_ISUB:
4292                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4293                         break;
4294                 case OP_ISBB:
4295                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4296                         break;
4297                 case OP_ISUB_IMM:
4298                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4299                         break;
4300                 case OP_ISBB_IMM:
4301                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4302                         break;
4303                 case OP_IAND:
4304                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4305                         break;
4306                 case OP_IAND_IMM:
4307                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4308                         break;
4309                 case OP_IOR:
4310                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4311                         break;
4312                 case OP_IOR_IMM:
4313                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4314                         break;
4315                 case OP_IXOR:
4316                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4317                         break;
4318                 case OP_IXOR_IMM:
4319                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4320                         break;
4321                 case OP_INEG:
4322                         amd64_neg_reg_size (code, ins->sreg1, 4);
4323                         break;
4324                 case OP_INOT:
4325                         amd64_not_reg_size (code, ins->sreg1, 4);
4326                         break;
4327                 case OP_ISHL:
4328                         g_assert (ins->sreg2 == AMD64_RCX);
4329                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4330                         break;
4331                 case OP_ISHR:
4332                         g_assert (ins->sreg2 == AMD64_RCX);
4333                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4334                         break;
4335                 case OP_ISHR_IMM:
4336                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4337                         break;
4338                 case OP_ISHR_UN_IMM:
4339                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4340                         break;
4341                 case OP_ISHR_UN:
4342                         g_assert (ins->sreg2 == AMD64_RCX);
4343                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4344                         break;
4345                 case OP_ISHL_IMM:
4346                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4347                         break;
4348                 case OP_IMUL:
4349                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4350                         break;
4351                 case OP_IMUL_OVF:
4352                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4353                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4354                         break;
4355                 case OP_IMUL_OVF_UN:
4356                 case OP_LMUL_OVF_UN: {
4357                         /* the mul operation and the exception check should most likely be split */
4358                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4359                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4360                         /*g_assert (ins->sreg2 == X86_EAX);
4361                         g_assert (ins->dreg == X86_EAX);*/
4362                         if (ins->sreg2 == X86_EAX) {
4363                                 non_eax_reg = ins->sreg1;
4364                         } else if (ins->sreg1 == X86_EAX) {
4365                                 non_eax_reg = ins->sreg2;
4366                         } else {
4367                                 /* no need to save since we're going to store to it anyway */
4368                                 if (ins->dreg != X86_EAX) {
4369                                         saved_eax = TRUE;
4370                                         amd64_push_reg (code, X86_EAX);
4371                                 }
4372                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4373                                 non_eax_reg = ins->sreg2;
4374                         }
4375                         if (ins->dreg == X86_EDX) {
4376                                 if (!saved_eax) {
4377                                         saved_eax = TRUE;
4378                                         amd64_push_reg (code, X86_EAX);
4379                                 }
4380                         } else {
4381                                 saved_edx = TRUE;
4382                                 amd64_push_reg (code, X86_EDX);
4383                         }
4384                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4385                         /* save before the check since pop and mov don't change the flags */
4386                         if (ins->dreg != X86_EAX)
4387                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4388                         if (saved_edx)
4389                                 amd64_pop_reg (code, X86_EDX);
4390                         if (saved_eax)
4391                                 amd64_pop_reg (code, X86_EAX);
4392                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4393                         break;
4394                 }
4395                 case OP_ICOMPARE:
4396                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4397                         break;
4398                 case OP_ICOMPARE_IMM:
4399                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4400                         break;
4401                 case OP_IBEQ:
4402                 case OP_IBLT:
4403                 case OP_IBGT:
4404                 case OP_IBGE:
4405                 case OP_IBLE:
4406                 case OP_LBEQ:
4407                 case OP_LBLT:
4408                 case OP_LBGT:
4409                 case OP_LBGE:
4410                 case OP_LBLE:
4411                 case OP_IBNE_UN:
4412                 case OP_IBLT_UN:
4413                 case OP_IBGT_UN:
4414                 case OP_IBGE_UN:
4415                 case OP_IBLE_UN:
4416                 case OP_LBNE_UN:
4417                 case OP_LBLT_UN:
4418                 case OP_LBGT_UN:
4419                 case OP_LBGE_UN:
4420                 case OP_LBLE_UN:
4421                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4422                         break;
4423
4424                 case OP_CMOV_IEQ:
4425                 case OP_CMOV_IGE:
4426                 case OP_CMOV_IGT:
4427                 case OP_CMOV_ILE:
4428                 case OP_CMOV_ILT:
4429                 case OP_CMOV_INE_UN:
4430                 case OP_CMOV_IGE_UN:
4431                 case OP_CMOV_IGT_UN:
4432                 case OP_CMOV_ILE_UN:
4433                 case OP_CMOV_ILT_UN:
4434                 case OP_CMOV_LEQ:
4435                 case OP_CMOV_LGE:
4436                 case OP_CMOV_LGT:
4437                 case OP_CMOV_LLE:
4438                 case OP_CMOV_LLT:
4439                 case OP_CMOV_LNE_UN:
4440                 case OP_CMOV_LGE_UN:
4441                 case OP_CMOV_LGT_UN:
4442                 case OP_CMOV_LLE_UN:
4443                 case OP_CMOV_LLT_UN:
4444                         g_assert (ins->dreg == ins->sreg1);
4445                         /* This needs to operate on 64 bit values */
4446                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4447                         break;
4448
4449                 case OP_LNOT:
4450                         amd64_not_reg (code, ins->sreg1);
4451                         break;
4452                 case OP_LNEG:
4453                         amd64_neg_reg (code, ins->sreg1);
4454                         break;
4455
4456                 case OP_ICONST:
4457                 case OP_I8CONST:
4458                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4459                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4460                         else
4461                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4462                         break;
4463                 case OP_AOTCONST:
4464                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4465                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4466                         break;
4467                 case OP_JUMP_TABLE:
4468                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4469                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4470                         break;
4471                 case OP_MOVE:
4472                         if (ins->dreg != ins->sreg1)
4473                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4474                         break;
4475                 case OP_AMD64_SET_XMMREG_R4: {
4476                         if (cfg->r4fp) {
4477                                 if (ins->dreg != ins->sreg1)
4478                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4479                         } else {
4480                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4481                         }
4482                         break;
4483                 }
4484                 case OP_AMD64_SET_XMMREG_R8: {
4485                         if (ins->dreg != ins->sreg1)
4486                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4487                         break;
4488                 }
4489                 case OP_TAILCALL: {
4490                         MonoCallInst *call = (MonoCallInst*)ins;
4491                         int i, save_area_offset;
4492
4493                         g_assert (!cfg->method->save_lmf);
4494
4495                         /* Restore callee saved registers */
4496                         save_area_offset = cfg->arch.reg_save_area_offset;
4497                         for (i = 0; i < AMD64_NREG; ++i)
4498                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4499                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4500                                         save_area_offset += 8;
4501                                 }
4502
4503                         if (cfg->arch.omit_fp) {
4504                                 if (cfg->arch.stack_alloc_size)
4505                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4506                                 // FIXME:
4507                                 if (call->stack_usage)
4508                                         NOT_IMPLEMENTED;
4509                         } else {
4510                                 /* Copy arguments on the stack to our argument area */
4511                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4512                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4513                                         amd64_mov_membase_reg (code, AMD64_RBP, ARGS_OFFSET + i, AMD64_RAX, sizeof(mgreg_t));
4514                                 }
4515
4516 #ifdef TARGET_WIN32
4517                                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
4518                                 amd64_pop_reg (code, AMD64_RBP);
4519                                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
4520 #else
4521                                 amd64_leave (code);
4522 #endif
4523                         }
4524
4525                         offset = code - cfg->native_code;
4526                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4527                         if (cfg->compile_aot)
4528                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4529                         else
4530                                 amd64_set_reg_template (code, AMD64_R11);
4531                         amd64_jump_reg (code, AMD64_R11);
4532                         ins->flags |= MONO_INST_GC_CALLSITE;
4533                         ins->backend.pc_offset = code - cfg->native_code;
4534                         break;
4535                 }
4536                 case OP_CHECK_THIS:
4537                         /* ensure ins->sreg1 is not NULL */
4538                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4539                         break;
4540                 case OP_ARGLIST: {
4541                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4542                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4543                         break;
4544                 }
4545                 case OP_CALL:
4546                 case OP_FCALL:
4547                 case OP_RCALL:
4548                 case OP_LCALL:
4549                 case OP_VCALL:
4550                 case OP_VCALL2:
4551                 case OP_VOIDCALL:
4552                         call = (MonoCallInst*)ins;
4553                         /*
4554                          * The AMD64 ABI forces callers to know about varargs.
4555                          */
4556                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4557                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4558                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4559                                 /*
4560                                  * Since the unmanaged calling convention doesn't contain a
4561                                  * 'vararg' entry, we have to treat every pinvoke call as a
4562                                  * potential vararg call.
4563                                  */
4564                                 guint32 nregs, i;
4565                                 nregs = 0;
4566                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4567                                         if (call->used_fregs & (1 << i))
4568                                                 nregs ++;
4569                                 if (!nregs)
4570                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4571                                 else
4572                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4573                         }
4574
4575                         if (ins->flags & MONO_INST_HAS_METHOD)
4576                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4577                         else
4578                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4579                         ins->flags |= MONO_INST_GC_CALLSITE;
4580                         ins->backend.pc_offset = code - cfg->native_code;
4581                         code = emit_move_return_value (cfg, ins, code);
4582                         break;
4583                 case OP_FCALL_REG:
4584                 case OP_RCALL_REG:
4585                 case OP_LCALL_REG:
4586                 case OP_VCALL_REG:
4587                 case OP_VCALL2_REG:
4588                 case OP_VOIDCALL_REG:
4589                 case OP_CALL_REG:
4590                         call = (MonoCallInst*)ins;
4591
4592                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4593                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4594                                 ins->sreg1 = AMD64_R11;
4595                         }
4596
4597                         /*
4598                          * The AMD64 ABI forces callers to know about varargs.
4599                          */
4600                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4601                                 if (ins->sreg1 == AMD64_RAX) {
4602                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4603                                         ins->sreg1 = AMD64_R11;
4604                                 }
4605                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4606                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4607                                 /*
4608                                  * Since the unmanaged calling convention doesn't contain a
4609                                  * 'vararg' entry, we have to treat every pinvoke call as a
4610                                  * potential vararg call.
4611                                  */
4612                                 guint32 nregs, i;
4613                                 nregs = 0;
4614                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4615                                         if (call->used_fregs & (1 << i))
4616                                                 nregs ++;
4617                                 if (ins->sreg1 == AMD64_RAX) {
4618                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4619                                         ins->sreg1 = AMD64_R11;
4620                                 }
4621                                 if (!nregs)
4622                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4623                                 else
4624                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4625                         }
4626
4627                         amd64_call_reg (code, ins->sreg1);
4628                         ins->flags |= MONO_INST_GC_CALLSITE;
4629                         ins->backend.pc_offset = code - cfg->native_code;
4630                         code = emit_move_return_value (cfg, ins, code);
4631                         break;
4632                 case OP_FCALL_MEMBASE:
4633                 case OP_RCALL_MEMBASE:
4634                 case OP_LCALL_MEMBASE:
4635                 case OP_VCALL_MEMBASE:
4636                 case OP_VCALL2_MEMBASE:
4637                 case OP_VOIDCALL_MEMBASE:
4638                 case OP_CALL_MEMBASE:
4639                         call = (MonoCallInst*)ins;
4640
4641                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4642                         ins->flags |= MONO_INST_GC_CALLSITE;
4643                         ins->backend.pc_offset = code - cfg->native_code;
4644                         code = emit_move_return_value (cfg, ins, code);
4645                         break;
4646                 case OP_DYN_CALL: {
4647                         int i;
4648                         MonoInst *var = cfg->dyn_call_var;
4649                         guint8 *label;
4650
4651                         g_assert (var->opcode == OP_REGOFFSET);
4652
4653                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4654                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4655                         /* r10 = ftn */
4656                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4657
4658                         /* Save args buffer */
4659                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4660
4661                         /* Set fp arg regs */
4662                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
4663                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4664                         label = code;
4665                         amd64_branch8 (code, X86_CC_Z, -1, 1);
4666                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
4667                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
4668                         amd64_patch (label, code);
4669
4670                         /* Set stack args */
4671                         for (i = 0; i < DYN_CALL_STACK_ARGS; ++i) {
4672                                 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, regs) + ((PARAM_REGS + i) * sizeof(mgreg_t)), sizeof(mgreg_t));
4673                                 amd64_mov_membase_reg (code, AMD64_RSP, i * sizeof (mgreg_t), AMD64_RAX, sizeof (mgreg_t));
4674                         }
4675
4676                         /* Set argument registers */
4677                         for (i = 0; i < PARAM_REGS; ++i)
4678                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
4679
4680                         /* Make the call */
4681                         amd64_call_reg (code, AMD64_R10);
4682
4683                         ins->flags |= MONO_INST_GC_CALLSITE;
4684                         ins->backend.pc_offset = code - cfg->native_code;
4685
4686                         /* Save result */
4687                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4688                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4689                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
4690                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + sizeof (double), AMD64_XMM1);
4691                         break;
4692                 }
4693                 case OP_AMD64_SAVE_SP_TO_LMF: {
4694                         MonoInst *lmf_var = cfg->lmf_var;
4695                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4696                         break;
4697                 }
4698                 case OP_X86_PUSH:
4699                         g_assert_not_reached ();
4700                         amd64_push_reg (code, ins->sreg1);
4701                         break;
4702                 case OP_X86_PUSH_IMM:
4703                         g_assert_not_reached ();
4704                         g_assert (amd64_is_imm32 (ins->inst_imm));
4705                         amd64_push_imm (code, ins->inst_imm);
4706                         break;
4707                 case OP_X86_PUSH_MEMBASE:
4708                         g_assert_not_reached ();
4709                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4710                         break;
4711                 case OP_X86_PUSH_OBJ: {
4712                         int size = ALIGN_TO (ins->inst_imm, 8);
4713
4714                         g_assert_not_reached ();
4715
4716                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4717                         amd64_push_reg (code, AMD64_RDI);
4718                         amd64_push_reg (code, AMD64_RSI);
4719                         amd64_push_reg (code, AMD64_RCX);
4720                         if (ins->inst_offset)
4721                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4722                         else
4723                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4724                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4725                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4726                         amd64_cld (code);
4727                         amd64_prefix (code, X86_REP_PREFIX);
4728                         amd64_movsd (code);
4729                         amd64_pop_reg (code, AMD64_RCX);
4730                         amd64_pop_reg (code, AMD64_RSI);
4731                         amd64_pop_reg (code, AMD64_RDI);
4732                         break;
4733                 }
4734                 case OP_GENERIC_CLASS_INIT: {
4735                         guint8 *jump;
4736
4737                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
4738
4739                         amd64_test_membase_imm_size (code, ins->sreg1, MONO_STRUCT_OFFSET (MonoVTable, initialized), 1, 1);
4740                         jump = code;
4741                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
4742
4743                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
4744                         ins->flags |= MONO_INST_GC_CALLSITE;
4745                         ins->backend.pc_offset = code - cfg->native_code;
4746
4747                         x86_patch (jump, code);
4748                         break;
4749                 }
4750
4751                 case OP_X86_LEA:
4752                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4753                         break;
4754                 case OP_X86_LEA_MEMBASE:
4755                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4756                         break;
4757                 case OP_X86_XCHG:
4758                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4759                         break;
4760                 case OP_LOCALLOC:
4761                         /* keep alignment */
4762                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4763                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4764                         code = mono_emit_stack_alloc (cfg, code, ins);
4765                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4766                         if (cfg->param_area)
4767                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4768                         break;
4769                 case OP_LOCALLOC_IMM: {
4770                         guint32 size = ins->inst_imm;
4771                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4772
4773                         if (ins->flags & MONO_INST_INIT) {
4774                                 if (size < 64) {
4775                                         int i;
4776
4777                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4778                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4779
4780                                         for (i = 0; i < size; i += 8)
4781                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4782                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4783                                 } else {
4784                                         amd64_mov_reg_imm (code, ins->dreg, size);
4785                                         ins->sreg1 = ins->dreg;
4786
4787                                         code = mono_emit_stack_alloc (cfg, code, ins);
4788                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4789                                 }
4790                         } else {
4791                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4792                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4793                         }
4794                         if (cfg->param_area)
4795                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4796                         break;
4797                 }
4798                 case OP_THROW: {
4799                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4800                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4801                                              (gpointer)"mono_arch_throw_exception", FALSE);
4802                         ins->flags |= MONO_INST_GC_CALLSITE;
4803                         ins->backend.pc_offset = code - cfg->native_code;
4804                         break;
4805                 }
4806                 case OP_RETHROW: {
4807                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4808                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4809                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4810                         ins->flags |= MONO_INST_GC_CALLSITE;
4811                         ins->backend.pc_offset = code - cfg->native_code;
4812                         break;
4813                 }
4814                 case OP_CALL_HANDLER:
4815                         /* Align stack */
4816                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4817                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4818                         amd64_call_imm (code, 0);
4819                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4820                         /* Restore stack alignment */
4821                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4822                         break;
4823                 case OP_START_HANDLER: {
4824                         /* Even though we're saving RSP, use sizeof */
4825                         /* gpointer because spvar is of type IntPtr */
4826                         /* see: mono_create_spvar_for_region */
4827                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4828                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
4829
4830                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4831                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FILTER)) &&
4832                                 cfg->param_area) {
4833                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4834                         }
4835                         break;
4836                 }
4837                 case OP_ENDFINALLY: {
4838                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4839                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4840                         amd64_ret (code);
4841                         break;
4842                 }
4843                 case OP_ENDFILTER: {
4844                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4845                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
4846                         /* The local allocator will put the result into RAX */
4847                         amd64_ret (code);
4848                         break;
4849                 }
4850                 case OP_GET_EX_OBJ:
4851                         if (ins->dreg != AMD64_RAX)
4852                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
4853                         break;
4854                 case OP_LABEL:
4855                         ins->inst_c0 = code - cfg->native_code;
4856                         break;
4857                 case OP_BR:
4858                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4859                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4860                         //break;
4861                                 if (ins->inst_target_bb->native_offset) {
4862                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4863                                 } else {
4864                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4865                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4866                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4867                                                 x86_jump8 (code, 0);
4868                                         else
4869                                                 x86_jump32 (code, 0);
4870                         }
4871                         break;
4872                 case OP_BR_REG:
4873                         amd64_jump_reg (code, ins->sreg1);
4874                         break;
4875                 case OP_ICNEQ:
4876                 case OP_ICGE:
4877                 case OP_ICLE:
4878                 case OP_ICGE_UN:
4879                 case OP_ICLE_UN:
4880
4881                 case OP_CEQ:
4882                 case OP_LCEQ:
4883                 case OP_ICEQ:
4884                 case OP_CLT:
4885                 case OP_LCLT:
4886                 case OP_ICLT:
4887                 case OP_CGT:
4888                 case OP_ICGT:
4889                 case OP_LCGT:
4890                 case OP_CLT_UN:
4891                 case OP_LCLT_UN:
4892                 case OP_ICLT_UN:
4893                 case OP_CGT_UN:
4894                 case OP_LCGT_UN:
4895                 case OP_ICGT_UN:
4896                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4897                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4898                         break;
4899                 case OP_COND_EXC_EQ:
4900                 case OP_COND_EXC_NE_UN:
4901                 case OP_COND_EXC_LT:
4902                 case OP_COND_EXC_LT_UN:
4903                 case OP_COND_EXC_GT:
4904                 case OP_COND_EXC_GT_UN:
4905                 case OP_COND_EXC_GE:
4906                 case OP_COND_EXC_GE_UN:
4907                 case OP_COND_EXC_LE:
4908                 case OP_COND_EXC_LE_UN:
4909                 case OP_COND_EXC_IEQ:
4910                 case OP_COND_EXC_INE_UN:
4911                 case OP_COND_EXC_ILT:
4912                 case OP_COND_EXC_ILT_UN:
4913                 case OP_COND_EXC_IGT:
4914                 case OP_COND_EXC_IGT_UN:
4915                 case OP_COND_EXC_IGE:
4916                 case OP_COND_EXC_IGE_UN:
4917                 case OP_COND_EXC_ILE:
4918                 case OP_COND_EXC_ILE_UN:
4919                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
4920                         break;
4921                 case OP_COND_EXC_OV:
4922                 case OP_COND_EXC_NO:
4923                 case OP_COND_EXC_C:
4924                 case OP_COND_EXC_NC:
4925                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4926                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
4927                         break;
4928                 case OP_COND_EXC_IOV:
4929                 case OP_COND_EXC_INO:
4930                 case OP_COND_EXC_IC:
4931                 case OP_COND_EXC_INC:
4932                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4933                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
4934                         break;
4935
4936                 /* floating point opcodes */
4937                 case OP_R8CONST: {
4938                         double d = *(double *)ins->inst_p0;
4939
4940                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4941                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4942                         }
4943                         else {
4944                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4945                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4946                         }
4947                         break;
4948                 }
4949                 case OP_R4CONST: {
4950                         float f = *(float *)ins->inst_p0;
4951
4952                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4953                                 if (cfg->r4fp)
4954                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
4955                                 else
4956                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4957                         }
4958                         else {
4959                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4960                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4961                                 if (!cfg->r4fp)
4962                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4963                         }
4964                         break;
4965                 }
4966                 case OP_STORER8_MEMBASE_REG:
4967                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4968                         break;
4969                 case OP_LOADR8_MEMBASE:
4970                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4971                         break;
4972                 case OP_STORER4_MEMBASE_REG:
4973                         if (cfg->r4fp) {
4974                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4975                         } else {
4976                                 /* This requires a double->single conversion */
4977                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
4978                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
4979                         }
4980                         break;
4981                 case OP_LOADR4_MEMBASE:
4982                         if (cfg->r4fp) {
4983                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4984                         } else {
4985                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4986                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4987                         }
4988                         break;
4989                 case OP_ICONV_TO_R4:
4990                         if (cfg->r4fp) {
4991                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4992                         } else {
4993                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4994                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4995                         }
4996                         break;
4997                 case OP_ICONV_TO_R8:
4998                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4999                         break;
5000                 case OP_LCONV_TO_R4:
5001                         if (cfg->r4fp) {
5002                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5003                         } else {
5004                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5005                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5006                         }
5007                         break;
5008                 case OP_LCONV_TO_R8:
5009                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5010                         break;
5011                 case OP_FCONV_TO_R4:
5012                         if (cfg->r4fp) {
5013                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5014                         } else {
5015                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5016                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5017                         }
5018                         break;
5019                 case OP_FCONV_TO_I1:
5020                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5021                         break;
5022                 case OP_FCONV_TO_U1:
5023                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5024                         break;
5025                 case OP_FCONV_TO_I2:
5026                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5027                         break;
5028                 case OP_FCONV_TO_U2:
5029                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5030                         break;
5031                 case OP_FCONV_TO_U4:
5032                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5033                         break;
5034                 case OP_FCONV_TO_I4:
5035                 case OP_FCONV_TO_I:
5036                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5037                         break;
5038                 case OP_FCONV_TO_I8:
5039                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5040                         break;
5041
5042                 case OP_RCONV_TO_I1:
5043                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5044                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5045                         break;
5046                 case OP_RCONV_TO_U1:
5047                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5048                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5049                         break;
5050                 case OP_RCONV_TO_I2:
5051                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5052                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5053                         break;
5054                 case OP_RCONV_TO_U2:
5055                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5056                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5057                         break;
5058                 case OP_RCONV_TO_I4:
5059                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5060                         break;
5061                 case OP_RCONV_TO_U4:
5062                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5063                         break;
5064                 case OP_RCONV_TO_I8:
5065                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5066                         break;
5067                 case OP_RCONV_TO_R8:
5068                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5069                         break;
5070                 case OP_RCONV_TO_R4:
5071                         if (ins->dreg != ins->sreg1)
5072                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5073                         break;
5074
5075                 case OP_LCONV_TO_R_UN: {
5076                         guint8 *br [2];
5077
5078                         /* Based on gcc code */
5079                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5080                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5081
5082                         /* Positive case */
5083                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5084                         br [1] = code; x86_jump8 (code, 0);
5085                         amd64_patch (br [0], code);
5086
5087                         /* Negative case */
5088                         /* Save to the red zone */
5089                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5090                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5091                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5092                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5093                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5094                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5095                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5096                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5097                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5098                         /* Restore */
5099                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5100                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5101                         amd64_patch (br [1], code);
5102                         break;
5103                 }
5104                 case OP_LCONV_TO_OVF_U4:
5105                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5106                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5107                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5108                         break;
5109                 case OP_LCONV_TO_OVF_I4_UN:
5110                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5111                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5112                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5113                         break;
5114                 case OP_FMOVE:
5115                         if (ins->dreg != ins->sreg1)
5116                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5117                         break;
5118                 case OP_RMOVE:
5119                         if (ins->dreg != ins->sreg1)
5120                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5121                         break;
5122                 case OP_MOVE_F_TO_I4:
5123                         if (cfg->r4fp) {
5124                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5125                         } else {
5126                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5127                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5128                         }
5129                         break;
5130                 case OP_MOVE_I4_TO_F:
5131                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5132                         if (!cfg->r4fp)
5133                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5134                         break;
5135                 case OP_MOVE_F_TO_I8:
5136                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5137                         break;
5138                 case OP_MOVE_I8_TO_F:
5139                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5140                         break;
5141                 case OP_FADD:
5142                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5143                         break;
5144                 case OP_FSUB:
5145                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5146                         break;
5147                 case OP_FMUL:
5148                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5149                         break;
5150                 case OP_FDIV:
5151                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5152                         break;
5153                 case OP_FNEG: {
5154                         static double r8_0 = -0.0;
5155
5156                         g_assert (ins->sreg1 == ins->dreg);
5157
5158                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5159                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5160                         break;
5161                 }
5162                 case OP_SIN:
5163                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5164                         break;
5165                 case OP_COS:
5166                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5167                         break;
5168                 case OP_ABS: {
5169                         static guint64 d = 0x7fffffffffffffffUL;
5170
5171                         g_assert (ins->sreg1 == ins->dreg);
5172
5173                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5174                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5175                         break;
5176                 }
5177                 case OP_SQRT:
5178                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5179                         break;
5180
5181                 case OP_RADD:
5182                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5183                         break;
5184                 case OP_RSUB:
5185                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5186                         break;
5187                 case OP_RMUL:
5188                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5189                         break;
5190                 case OP_RDIV:
5191                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5192                         break;
5193                 case OP_RNEG: {
5194                         static float r4_0 = -0.0;
5195
5196                         g_assert (ins->sreg1 == ins->dreg);
5197
5198                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5199                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5200                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5201                         break;
5202                 }
5203
5204                 case OP_IMIN:
5205                         g_assert (cfg->opt & MONO_OPT_CMOV);
5206                         g_assert (ins->dreg == ins->sreg1);
5207                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5208                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5209                         break;
5210                 case OP_IMIN_UN:
5211                         g_assert (cfg->opt & MONO_OPT_CMOV);
5212                         g_assert (ins->dreg == ins->sreg1);
5213                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5214                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5215                         break;
5216                 case OP_IMAX:
5217                         g_assert (cfg->opt & MONO_OPT_CMOV);
5218                         g_assert (ins->dreg == ins->sreg1);
5219                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5220                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5221                         break;
5222                 case OP_IMAX_UN:
5223                         g_assert (cfg->opt & MONO_OPT_CMOV);
5224                         g_assert (ins->dreg == ins->sreg1);
5225                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5226                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5227                         break;
5228                 case OP_LMIN:
5229                         g_assert (cfg->opt & MONO_OPT_CMOV);
5230                         g_assert (ins->dreg == ins->sreg1);
5231                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5232                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5233                         break;
5234                 case OP_LMIN_UN:
5235                         g_assert (cfg->opt & MONO_OPT_CMOV);
5236                         g_assert (ins->dreg == ins->sreg1);
5237                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5238                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5239                         break;
5240                 case OP_LMAX:
5241                         g_assert (cfg->opt & MONO_OPT_CMOV);
5242                         g_assert (ins->dreg == ins->sreg1);
5243                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5244                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5245                         break;
5246                 case OP_LMAX_UN:
5247                         g_assert (cfg->opt & MONO_OPT_CMOV);
5248                         g_assert (ins->dreg == ins->sreg1);
5249                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5250                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5251                         break;
5252                 case OP_X86_FPOP:
5253                         break;
5254                 case OP_FCOMPARE:
5255                         /*
5256                          * The two arguments are swapped because the fbranch instructions
5257                          * depend on this for the non-sse case to work.
5258                          */
5259                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5260                         break;
5261                 case OP_RCOMPARE:
5262                         /*
5263                          * FIXME: Get rid of this.
5264                          * The two arguments are swapped because the fbranch instructions
5265                          * depend on this for the non-sse case to work.
5266                          */
5267                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5268                         break;
5269                 case OP_FCNEQ:
5270                 case OP_FCEQ: {
5271                         /* zeroing the register at the start results in
5272                          * shorter and faster code (we can also remove the widening op)
5273                          */
5274                         guchar *unordered_check;
5275
5276                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5277                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5278                         unordered_check = code;
5279                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5280
5281                         if (ins->opcode == OP_FCEQ) {
5282                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5283                                 amd64_patch (unordered_check, code);
5284                         } else {
5285                                 guchar *jump_to_end;
5286                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5287                                 jump_to_end = code;
5288                                 x86_jump8 (code, 0);
5289                                 amd64_patch (unordered_check, code);
5290                                 amd64_inc_reg (code, ins->dreg);
5291                                 amd64_patch (jump_to_end, code);
5292                         }
5293                         break;
5294                 }
5295                 case OP_FCLT:
5296                 case OP_FCLT_UN: {
5297                         /* zeroing the register at the start results in
5298                          * shorter and faster code (we can also remove the widening op)
5299                          */
5300                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5301                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5302                         if (ins->opcode == OP_FCLT_UN) {
5303                                 guchar *unordered_check = code;
5304                                 guchar *jump_to_end;
5305                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5306                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5307                                 jump_to_end = code;
5308                                 x86_jump8 (code, 0);
5309                                 amd64_patch (unordered_check, code);
5310                                 amd64_inc_reg (code, ins->dreg);
5311                                 amd64_patch (jump_to_end, code);
5312                         } else {
5313                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5314                         }
5315                         break;
5316                 }
5317                 case OP_FCLE: {
5318                         guchar *unordered_check;
5319                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5320                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5321                         unordered_check = code;
5322                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5323                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5324                         amd64_patch (unordered_check, code);
5325                         break;
5326                 }
5327                 case OP_FCGT:
5328                 case OP_FCGT_UN: {
5329                         /* zeroing the register at the start results in
5330                          * shorter and faster code (we can also remove the widening op)
5331                          */
5332                         guchar *unordered_check;
5333
5334                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5335                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5336                         if (ins->opcode == OP_FCGT) {
5337                                 unordered_check = code;
5338                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5339                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5340                                 amd64_patch (unordered_check, code);
5341                         } else {
5342                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5343                         }
5344                         break;
5345                 }
5346                 case OP_FCGE: {
5347                         guchar *unordered_check;
5348                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5349                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5350                         unordered_check = code;
5351                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5352                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5353                         amd64_patch (unordered_check, code);
5354                         break;
5355                 }
5356
5357                 case OP_RCEQ:
5358                 case OP_RCGT:
5359                 case OP_RCLT:
5360                 case OP_RCLT_UN:
5361                 case OP_RCGT_UN: {
5362                         int x86_cond;
5363                         gboolean unordered = FALSE;
5364
5365                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5366                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5367
5368                         switch (ins->opcode) {
5369                         case OP_RCEQ:
5370                                 x86_cond = X86_CC_EQ;
5371                                 break;
5372                         case OP_RCGT:
5373                                 x86_cond = X86_CC_LT;
5374                                 break;
5375                         case OP_RCLT:
5376                                 x86_cond = X86_CC_GT;
5377                                 break;
5378                         case OP_RCLT_UN:
5379                                 x86_cond = X86_CC_GT;
5380                                 unordered = TRUE;
5381                                 break;
5382                         case OP_RCGT_UN:
5383                                 x86_cond = X86_CC_LT;
5384                                 unordered = TRUE;
5385                                 break;
5386                         default:
5387                                 g_assert_not_reached ();
5388                                 break;
5389                         }
5390
5391                         if (unordered) {
5392                                 guchar *unordered_check;
5393                                 guchar *jump_to_end;
5394
5395                                 unordered_check = code;
5396                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5397                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5398                                 jump_to_end = code;
5399                                 x86_jump8 (code, 0);
5400                                 amd64_patch (unordered_check, code);
5401                                 amd64_inc_reg (code, ins->dreg);
5402                                 amd64_patch (jump_to_end, code);
5403                         } else {
5404                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5405                         }
5406                         break;
5407                 }
5408                 case OP_FCLT_MEMBASE:
5409                 case OP_FCGT_MEMBASE:
5410                 case OP_FCLT_UN_MEMBASE:
5411                 case OP_FCGT_UN_MEMBASE:
5412                 case OP_FCEQ_MEMBASE: {
5413                         guchar *unordered_check, *jump_to_end;
5414                         int x86_cond;
5415
5416                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5417                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5418
5419                         switch (ins->opcode) {
5420                         case OP_FCEQ_MEMBASE:
5421                                 x86_cond = X86_CC_EQ;
5422                                 break;
5423                         case OP_FCLT_MEMBASE:
5424                         case OP_FCLT_UN_MEMBASE:
5425                                 x86_cond = X86_CC_LT;
5426                                 break;
5427                         case OP_FCGT_MEMBASE:
5428                         case OP_FCGT_UN_MEMBASE:
5429                                 x86_cond = X86_CC_GT;
5430                                 break;
5431                         default:
5432                                 g_assert_not_reached ();
5433                         }
5434
5435                         unordered_check = code;
5436                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5437                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5438
5439                         switch (ins->opcode) {
5440                         case OP_FCEQ_MEMBASE:
5441                         case OP_FCLT_MEMBASE:
5442                         case OP_FCGT_MEMBASE:
5443                                 amd64_patch (unordered_check, code);
5444                                 break;
5445                         case OP_FCLT_UN_MEMBASE:
5446                         case OP_FCGT_UN_MEMBASE:
5447                                 jump_to_end = code;
5448                                 x86_jump8 (code, 0);
5449                                 amd64_patch (unordered_check, code);
5450                                 amd64_inc_reg (code, ins->dreg);
5451                                 amd64_patch (jump_to_end, code);
5452                                 break;
5453                         default:
5454                                 break;
5455                         }
5456                         break;
5457                 }
5458                 case OP_FBEQ: {
5459                         guchar *jump = code;
5460                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5461                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5462                         amd64_patch (jump, code);
5463                         break;
5464                 }
5465                 case OP_FBNE_UN:
5466                         /* Branch if C013 != 100 */
5467                         /* branch if !ZF or (PF|CF) */
5468                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5469                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5470                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5471                         break;
5472                 case OP_FBLT:
5473                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5474                         break;
5475                 case OP_FBLT_UN:
5476                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5477                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5478                         break;
5479                 case OP_FBGT:
5480                 case OP_FBGT_UN:
5481                         if (ins->opcode == OP_FBGT) {
5482                                 guchar *br1;
5483
5484                                 /* skip branch if C1=1 */
5485                                 br1 = code;
5486                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5487                                 /* branch if (C0 | C3) = 1 */
5488                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5489                                 amd64_patch (br1, code);
5490                                 break;
5491                         } else {
5492                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5493                         }
5494                         break;
5495                 case OP_FBGE: {
5496                         /* Branch if C013 == 100 or 001 */
5497                         guchar *br1;
5498
5499                         /* skip branch if C1=1 */
5500                         br1 = code;
5501                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5502                         /* branch if (C0 | C3) = 1 */
5503                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5504                         amd64_patch (br1, code);
5505                         break;
5506                 }
5507                 case OP_FBGE_UN:
5508                         /* Branch if C013 == 000 */
5509                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5510                         break;
5511                 case OP_FBLE: {
5512                         /* Branch if C013=000 or 100 */
5513                         guchar *br1;
5514
5515                         /* skip branch if C1=1 */
5516                         br1 = code;
5517                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5518                         /* branch if C0=0 */
5519                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5520                         amd64_patch (br1, code);
5521                         break;
5522                 }
5523                 case OP_FBLE_UN:
5524                         /* Branch if C013 != 001 */
5525                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5526                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5527                         break;
5528                 case OP_CKFINITE:
5529                         /* Transfer value to the fp stack */
5530                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5531                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5532                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5533
5534                         amd64_push_reg (code, AMD64_RAX);
5535                         amd64_fxam (code);
5536                         amd64_fnstsw (code);
5537                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5538                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5539                         amd64_pop_reg (code, AMD64_RAX);
5540                         amd64_fstp (code, 0);
5541                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "OverflowException");
5542                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5543                         break;
5544                 case OP_TLS_GET: {
5545                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5546                         break;
5547                 }
5548                 case OP_TLS_SET: {
5549                         code = mono_amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5550                         break;
5551                 }
5552                 case OP_MEMORY_BARRIER: {
5553                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5554                                 x86_mfence (code);
5555                         break;
5556                 }
5557                 case OP_ATOMIC_ADD_I4:
5558                 case OP_ATOMIC_ADD_I8: {
5559                         int dreg = ins->dreg;
5560                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5561
5562                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5563                                 dreg = AMD64_R11;
5564
5565                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5566                         amd64_prefix (code, X86_LOCK_PREFIX);
5567                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5568                         /* dreg contains the old value, add with sreg2 value */
5569                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5570
5571                         if (ins->dreg != dreg)
5572                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5573
5574                         break;
5575                 }
5576                 case OP_ATOMIC_EXCHANGE_I4:
5577                 case OP_ATOMIC_EXCHANGE_I8: {
5578                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5579
5580                         /* LOCK prefix is implied. */
5581                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5582                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5583                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5584                         break;
5585                 }
5586                 case OP_ATOMIC_CAS_I4:
5587                 case OP_ATOMIC_CAS_I8: {
5588                         guint32 size;
5589
5590                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5591                                 size = 8;
5592                         else
5593                                 size = 4;
5594
5595                         /*
5596                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5597                          * an explanation of how this works.
5598                          */
5599                         g_assert (ins->sreg3 == AMD64_RAX);
5600                         g_assert (ins->sreg1 != AMD64_RAX);
5601                         g_assert (ins->sreg1 != ins->sreg2);
5602
5603                         amd64_prefix (code, X86_LOCK_PREFIX);
5604                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5605
5606                         if (ins->dreg != AMD64_RAX)
5607                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5608                         break;
5609                 }
5610                 case OP_ATOMIC_LOAD_I1: {
5611                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5612                         break;
5613                 }
5614                 case OP_ATOMIC_LOAD_U1: {
5615                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5616                         break;
5617                 }
5618                 case OP_ATOMIC_LOAD_I2: {
5619                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5620                         break;
5621                 }
5622                 case OP_ATOMIC_LOAD_U2: {
5623                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5624                         break;
5625                 }
5626                 case OP_ATOMIC_LOAD_I4: {
5627                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5628                         break;
5629                 }
5630                 case OP_ATOMIC_LOAD_U4:
5631                 case OP_ATOMIC_LOAD_I8:
5632                 case OP_ATOMIC_LOAD_U8: {
5633                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5634                         break;
5635                 }
5636                 case OP_ATOMIC_LOAD_R4: {
5637                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5638                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5639                         break;
5640                 }
5641                 case OP_ATOMIC_LOAD_R8: {
5642                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5643                         break;
5644                 }
5645                 case OP_ATOMIC_STORE_I1:
5646                 case OP_ATOMIC_STORE_U1:
5647                 case OP_ATOMIC_STORE_I2:
5648                 case OP_ATOMIC_STORE_U2:
5649                 case OP_ATOMIC_STORE_I4:
5650                 case OP_ATOMIC_STORE_U4:
5651                 case OP_ATOMIC_STORE_I8:
5652                 case OP_ATOMIC_STORE_U8: {
5653                         int size;
5654
5655                         switch (ins->opcode) {
5656                         case OP_ATOMIC_STORE_I1:
5657                         case OP_ATOMIC_STORE_U1:
5658                                 size = 1;
5659                                 break;
5660                         case OP_ATOMIC_STORE_I2:
5661                         case OP_ATOMIC_STORE_U2:
5662                                 size = 2;
5663                                 break;
5664                         case OP_ATOMIC_STORE_I4:
5665                         case OP_ATOMIC_STORE_U4:
5666                                 size = 4;
5667                                 break;
5668                         case OP_ATOMIC_STORE_I8:
5669                         case OP_ATOMIC_STORE_U8:
5670                                 size = 8;
5671                                 break;
5672                         }
5673
5674                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
5675
5676                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5677                                 x86_mfence (code);
5678                         break;
5679                 }
5680                 case OP_ATOMIC_STORE_R4: {
5681                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5682                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5683
5684                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5685                                 x86_mfence (code);
5686                         break;
5687                 }
5688                 case OP_ATOMIC_STORE_R8: {
5689                         x86_nop (code);
5690                         x86_nop (code);
5691                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5692                         x86_nop (code);
5693                         x86_nop (code);
5694
5695                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5696                                 x86_mfence (code);
5697                         break;
5698                 }
5699                 case OP_CARD_TABLE_WBARRIER: {
5700                         int ptr = ins->sreg1;
5701                         int value = ins->sreg2;
5702                         guchar *br = 0;
5703                         int nursery_shift, card_table_shift;
5704                         gpointer card_table_mask;
5705                         size_t nursery_size;
5706
5707                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
5708                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
5709                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
5710
5711                         /*If either point to the stack we can simply avoid the WB. This happens due to
5712                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
5713                          */
5714                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
5715                                 continue;
5716
5717                         /*
5718                          * We need one register we can clobber, we choose EDX and make sreg1
5719                          * fixed EAX to work around limitations in the local register allocator.
5720                          * sreg2 might get allocated to EDX, but that is not a problem since
5721                          * we use it before clobbering EDX.
5722                          */
5723                         g_assert (ins->sreg1 == AMD64_RAX);
5724
5725                         /*
5726                          * This is the code we produce:
5727                          *
5728                          *   edx = value
5729                          *   edx >>= nursery_shift
5730                          *   cmp edx, (nursery_start >> nursery_shift)
5731                          *   jne done
5732                          *   edx = ptr
5733                          *   edx >>= card_table_shift
5734                          *   edx += cardtable
5735                          *   [edx] = 1
5736                          * done:
5737                          */
5738
5739                         if (mono_gc_card_table_nursery_check ()) {
5740                                 if (value != AMD64_RDX)
5741                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
5742                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
5743                                 if (shifted_nursery_start >> 31) {
5744                                         /*
5745                                          * The value we need to compare against is 64 bits, so we need
5746                                          * another spare register.  We use RBX, which we save and
5747                                          * restore.
5748                                          */
5749                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
5750                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
5751                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
5752                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
5753                                 } else {
5754                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
5755                                 }
5756                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
5757                         }
5758                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
5759                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
5760                         if (card_table_mask)
5761                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
5762
5763                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
5764                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
5765
5766                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
5767
5768                         if (mono_gc_card_table_nursery_check ())
5769                                 x86_patch (br, code);
5770                         break;
5771                 }
5772 #ifdef MONO_ARCH_SIMD_INTRINSICS
5773                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
5774                 case OP_ADDPS:
5775                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
5776                         break;
5777                 case OP_DIVPS:
5778                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
5779                         break;
5780                 case OP_MULPS:
5781                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
5782                         break;
5783                 case OP_SUBPS:
5784                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
5785                         break;
5786                 case OP_MAXPS:
5787                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
5788                         break;
5789                 case OP_MINPS:
5790                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
5791                         break;
5792                 case OP_COMPPS:
5793                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5794                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5795                         break;
5796                 case OP_ANDPS:
5797                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5798                         break;
5799                 case OP_ANDNPS:
5800                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5801                         break;
5802                 case OP_ORPS:
5803                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5804                         break;
5805                 case OP_XORPS:
5806                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5807                         break;
5808                 case OP_SQRTPS:
5809                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5810                         break;
5811                 case OP_RSQRTPS:
5812                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5813                         break;
5814                 case OP_RCPPS:
5815                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5816                         break;
5817                 case OP_ADDSUBPS:
5818                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5819                         break;
5820                 case OP_HADDPS:
5821                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5822                         break;
5823                 case OP_HSUBPS:
5824                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5825                         break;
5826                 case OP_DUPPS_HIGH:
5827                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5828                         break;
5829                 case OP_DUPPS_LOW:
5830                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5831                         break;
5832
5833                 case OP_PSHUFLEW_HIGH:
5834                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5835                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5836                         break;
5837                 case OP_PSHUFLEW_LOW:
5838                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5839                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5840                         break;
5841                 case OP_PSHUFLED:
5842                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5843                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5844                         break;
5845                 case OP_SHUFPS:
5846                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5847                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5848                         break;
5849                 case OP_SHUFPD:
5850                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
5851                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5852                         break;
5853
5854                 case OP_ADDPD:
5855                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5856                         break;
5857                 case OP_DIVPD:
5858                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5859                         break;
5860                 case OP_MULPD:
5861                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5862                         break;
5863                 case OP_SUBPD:
5864                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5865                         break;
5866                 case OP_MAXPD:
5867                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5868                         break;
5869                 case OP_MINPD:
5870                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5871                         break;
5872                 case OP_COMPPD:
5873                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5874                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5875                         break;
5876                 case OP_ANDPD:
5877                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5878                         break;
5879                 case OP_ANDNPD:
5880                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5881                         break;
5882                 case OP_ORPD:
5883                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5884                         break;
5885                 case OP_XORPD:
5886                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5887                         break;
5888                 case OP_SQRTPD:
5889                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5890                         break;
5891                 case OP_ADDSUBPD:
5892                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5893                         break;
5894                 case OP_HADDPD:
5895                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5896                         break;
5897                 case OP_HSUBPD:
5898                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5899                         break;
5900                 case OP_DUPPD:
5901                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5902                         break;
5903
5904                 case OP_EXTRACT_MASK:
5905                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5906                         break;
5907
5908                 case OP_PAND:
5909                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5910                         break;
5911                 case OP_POR:
5912                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5913                         break;
5914                 case OP_PXOR:
5915                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5916                         break;
5917
5918                 case OP_PADDB:
5919                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5920                         break;
5921                 case OP_PADDW:
5922                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5923                         break;
5924                 case OP_PADDD:
5925                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5926                         break;
5927                 case OP_PADDQ:
5928                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5929                         break;
5930
5931                 case OP_PSUBB:
5932                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5933                         break;
5934                 case OP_PSUBW:
5935                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5936                         break;
5937                 case OP_PSUBD:
5938                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5939                         break;
5940                 case OP_PSUBQ:
5941                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5942                         break;
5943
5944                 case OP_PMAXB_UN:
5945                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5946                         break;
5947                 case OP_PMAXW_UN:
5948                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5949                         break;
5950                 case OP_PMAXD_UN:
5951                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5952                         break;
5953
5954                 case OP_PMAXB:
5955                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5956                         break;
5957                 case OP_PMAXW:
5958                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5959                         break;
5960                 case OP_PMAXD:
5961                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5962                         break;
5963
5964                 case OP_PAVGB_UN:
5965                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5966                         break;
5967                 case OP_PAVGW_UN:
5968                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5969                         break;
5970
5971                 case OP_PMINB_UN:
5972                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5973                         break;
5974                 case OP_PMINW_UN:
5975                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5976                         break;
5977                 case OP_PMIND_UN:
5978                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5979                         break;
5980
5981                 case OP_PMINB:
5982                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5983                         break;
5984                 case OP_PMINW:
5985                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5986                         break;
5987                 case OP_PMIND:
5988                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5989                         break;
5990
5991                 case OP_PCMPEQB:
5992                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5993                         break;
5994                 case OP_PCMPEQW:
5995                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5996                         break;
5997                 case OP_PCMPEQD:
5998                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5999                         break;
6000                 case OP_PCMPEQQ:
6001                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6002                         break;
6003
6004                 case OP_PCMPGTB:
6005                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6006                         break;
6007                 case OP_PCMPGTW:
6008                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6009                         break;
6010                 case OP_PCMPGTD:
6011                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6012                         break;
6013                 case OP_PCMPGTQ:
6014                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6015                         break;
6016
6017                 case OP_PSUM_ABS_DIFF:
6018                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6019                         break;
6020
6021                 case OP_UNPACK_LOWB:
6022                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6023                         break;
6024                 case OP_UNPACK_LOWW:
6025                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6026                         break;
6027                 case OP_UNPACK_LOWD:
6028                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6029                         break;
6030                 case OP_UNPACK_LOWQ:
6031                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6032                         break;
6033                 case OP_UNPACK_LOWPS:
6034                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6035                         break;
6036                 case OP_UNPACK_LOWPD:
6037                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6038                         break;
6039
6040                 case OP_UNPACK_HIGHB:
6041                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6042                         break;
6043                 case OP_UNPACK_HIGHW:
6044                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6045                         break;
6046                 case OP_UNPACK_HIGHD:
6047                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6048                         break;
6049                 case OP_UNPACK_HIGHQ:
6050                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6051                         break;
6052                 case OP_UNPACK_HIGHPS:
6053                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6054                         break;
6055                 case OP_UNPACK_HIGHPD:
6056                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6057                         break;
6058
6059                 case OP_PACKW:
6060                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6061                         break;
6062                 case OP_PACKD:
6063                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6064                         break;
6065                 case OP_PACKW_UN:
6066                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6067                         break;
6068                 case OP_PACKD_UN:
6069                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6070                         break;
6071
6072                 case OP_PADDB_SAT_UN:
6073                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6074                         break;
6075                 case OP_PSUBB_SAT_UN:
6076                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6077                         break;
6078                 case OP_PADDW_SAT_UN:
6079                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6080                         break;
6081                 case OP_PSUBW_SAT_UN:
6082                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6083                         break;
6084
6085                 case OP_PADDB_SAT:
6086                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6087                         break;
6088                 case OP_PSUBB_SAT:
6089                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6090                         break;
6091                 case OP_PADDW_SAT:
6092                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6093                         break;
6094                 case OP_PSUBW_SAT:
6095                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6096                         break;
6097
6098                 case OP_PMULW:
6099                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6100                         break;
6101                 case OP_PMULD:
6102                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6103                         break;
6104                 case OP_PMULQ:
6105                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6106                         break;
6107                 case OP_PMULW_HIGH_UN:
6108                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6109                         break;
6110                 case OP_PMULW_HIGH:
6111                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6112                         break;
6113
6114                 case OP_PSHRW:
6115                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6116                         break;
6117                 case OP_PSHRW_REG:
6118                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6119                         break;
6120
6121                 case OP_PSARW:
6122                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6123                         break;
6124                 case OP_PSARW_REG:
6125                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6126                         break;
6127
6128                 case OP_PSHLW:
6129                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6130                         break;
6131                 case OP_PSHLW_REG:
6132                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6133                         break;
6134
6135                 case OP_PSHRD:
6136                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6137                         break;
6138                 case OP_PSHRD_REG:
6139                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6140                         break;
6141
6142                 case OP_PSARD:
6143                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6144                         break;
6145                 case OP_PSARD_REG:
6146                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6147                         break;
6148
6149                 case OP_PSHLD:
6150                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6151                         break;
6152                 case OP_PSHLD_REG:
6153                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6154                         break;
6155
6156                 case OP_PSHRQ:
6157                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6158                         break;
6159                 case OP_PSHRQ_REG:
6160                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6161                         break;
6162
6163                 /*TODO: This is appart of the sse spec but not added
6164                 case OP_PSARQ:
6165                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6166                         break;
6167                 case OP_PSARQ_REG:
6168                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6169                         break;
6170                 */
6171
6172                 case OP_PSHLQ:
6173                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6174                         break;
6175                 case OP_PSHLQ_REG:
6176                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6177                         break;
6178                 case OP_CVTDQ2PD:
6179                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6180                         break;
6181                 case OP_CVTDQ2PS:
6182                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6183                         break;
6184                 case OP_CVTPD2DQ:
6185                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6186                         break;
6187                 case OP_CVTPD2PS:
6188                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6189                         break;
6190                 case OP_CVTPS2DQ:
6191                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6192                         break;
6193                 case OP_CVTPS2PD:
6194                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6195                         break;
6196                 case OP_CVTTPD2DQ:
6197                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6198                         break;
6199                 case OP_CVTTPS2DQ:
6200                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6201                         break;
6202
6203                 case OP_ICONV_TO_X:
6204                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6205                         break;
6206                 case OP_EXTRACT_I4:
6207                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6208                         break;
6209                 case OP_EXTRACT_I8:
6210                         if (ins->inst_c0) {
6211                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6212                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6213                         } else {
6214                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6215                         }
6216                         break;
6217                 case OP_EXTRACT_I1:
6218                 case OP_EXTRACT_U1:
6219                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6220                         if (ins->inst_c0)
6221                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6222                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6223                         break;
6224                 case OP_EXTRACT_I2:
6225                 case OP_EXTRACT_U2:
6226                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6227                         if (ins->inst_c0)
6228                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6229                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6230                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6231                         break;
6232                 case OP_EXTRACT_R8:
6233                         if (ins->inst_c0)
6234                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6235                         else
6236                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6237                         break;
6238                 case OP_INSERT_I2:
6239                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6240                         break;
6241                 case OP_EXTRACTX_U2:
6242                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6243                         break;
6244                 case OP_INSERTX_U1_SLOW:
6245                         /*sreg1 is the extracted ireg (scratch)
6246                         /sreg2 is the to be inserted ireg (scratch)
6247                         /dreg is the xreg to receive the value*/
6248
6249                         /*clear the bits from the extracted word*/
6250                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6251                         /*shift the value to insert if needed*/
6252                         if (ins->inst_c0 & 1)
6253                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6254                         /*join them together*/
6255                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6256                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6257                         break;
6258                 case OP_INSERTX_I4_SLOW:
6259                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6260                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6261                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6262                         break;
6263                 case OP_INSERTX_I8_SLOW:
6264                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6265                         if (ins->inst_c0)
6266                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6267                         else
6268                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6269                         break;
6270
6271                 case OP_INSERTX_R4_SLOW:
6272                         switch (ins->inst_c0) {
6273                         case 0:
6274                                 if (cfg->r4fp)
6275                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6276                                 else
6277                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6278                                 break;
6279                         case 1:
6280                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6281                                 if (cfg->r4fp)
6282                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6283                                 else
6284                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6285                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6286                                 break;
6287                         case 2:
6288                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6289                                 if (cfg->r4fp)
6290                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6291                                 else
6292                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6293                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6294                                 break;
6295                         case 3:
6296                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6297                                 if (cfg->r4fp)
6298                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6299                                 else
6300                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6301                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6302                                 break;
6303                         }
6304                         break;
6305                 case OP_INSERTX_R8_SLOW:
6306                         if (ins->inst_c0)
6307                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6308                         else
6309                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6310                         break;
6311                 case OP_STOREX_MEMBASE_REG:
6312                 case OP_STOREX_MEMBASE:
6313                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6314                         break;
6315                 case OP_LOADX_MEMBASE:
6316                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6317                         break;
6318                 case OP_LOADX_ALIGNED_MEMBASE:
6319                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6320                         break;
6321                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6322                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6323                         break;
6324                 case OP_STOREX_NTA_MEMBASE_REG:
6325                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6326                         break;
6327                 case OP_PREFETCH_MEMBASE:
6328                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6329                         break;
6330
6331                 case OP_XMOVE:
6332                         /*FIXME the peephole pass should have killed this*/
6333                         if (ins->dreg != ins->sreg1)
6334                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6335                         break;
6336                 case OP_XZERO:
6337                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6338                         break;
6339                 case OP_XONES:
6340                         amd64_sse_pcmpeqb_reg_reg (code, ins->dreg, ins->dreg);
6341                         break;
6342                 case OP_ICONV_TO_R4_RAW:
6343                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6344                         if (!cfg->r4fp)
6345                           amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6346                         break;
6347
6348                 case OP_FCONV_TO_R8_X:
6349                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6350                         break;
6351
6352                 case OP_XCONV_R8_TO_I4:
6353                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6354                         switch (ins->backend.source_opcode) {
6355                         case OP_FCONV_TO_I1:
6356                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6357                                 break;
6358                         case OP_FCONV_TO_U1:
6359                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6360                                 break;
6361                         case OP_FCONV_TO_I2:
6362                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6363                                 break;
6364                         case OP_FCONV_TO_U2:
6365                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6366                                 break;
6367                         }
6368                         break;
6369
6370                 case OP_EXPAND_I2:
6371                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6372                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6373                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6374                         break;
6375                 case OP_EXPAND_I4:
6376                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6377                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6378                         break;
6379                 case OP_EXPAND_I8:
6380                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6381                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6382                         break;
6383                 case OP_EXPAND_R4:
6384                         if (cfg->r4fp) {
6385                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6386                         } else {
6387                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6388                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6389                         }
6390                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6391                         break;
6392                 case OP_EXPAND_R8:
6393                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6394                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6395                         break;
6396 #endif
6397                 case OP_LIVERANGE_START: {
6398                         if (cfg->verbose_level > 1)
6399                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6400                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6401                         break;
6402                 }
6403                 case OP_LIVERANGE_END: {
6404                         if (cfg->verbose_level > 1)
6405                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6406                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6407                         break;
6408                 }
6409                 case OP_GC_SAFE_POINT: {
6410                         guint8 *br [1];
6411
6412                         g_assert (mono_threads_is_coop_enabled ());
6413
6414                         amd64_test_membase_imm_size (code, ins->sreg1, 0, 1, 4);
6415                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6416                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_threads_state_poll", FALSE);
6417                         amd64_patch (br[0], code);
6418                         break;
6419                 }
6420
6421                 case OP_GC_LIVENESS_DEF:
6422                 case OP_GC_LIVENESS_USE:
6423                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6424                         ins->backend.pc_offset = code - cfg->native_code;
6425                         break;
6426                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6427                         ins->backend.pc_offset = code - cfg->native_code;
6428                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6429                         break;
6430                 case OP_GET_LAST_ERROR:
6431                         emit_get_last_error(code, ins->dreg);
6432                         break;
6433                 default:
6434                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6435                         g_assert_not_reached ();
6436                 }
6437
6438                 if ((code - cfg->native_code - offset) > max_len) {
6439                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6440                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6441                         g_assert_not_reached ();
6442                 }
6443         }
6444
6445         cfg->code_len = code - cfg->native_code;
6446 }
6447
6448 #endif /* DISABLE_JIT */
6449
6450 void
6451 mono_arch_register_lowlevel_calls (void)
6452 {
6453         /* The signature doesn't matter */
6454         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6455
6456 #if defined(TARGET_WIN32) || defined(HOST_WIN32)
6457 #if _MSC_VER
6458         extern void __chkstk (void);
6459         mono_register_jit_icall_full (__chkstk, "mono_chkstk_win64", NULL, TRUE, FALSE, "__chkstk");
6460 #else
6461         extern void ___chkstk_ms (void);
6462         mono_register_jit_icall_full (___chkstk_ms, "mono_chkstk_win64", NULL, TRUE, FALSE, "___chkstk_ms");
6463 #endif
6464 #endif
6465 }
6466
6467 void
6468 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6469 {
6470         unsigned char *ip = ji->ip.i + code;
6471
6472         /*
6473          * Debug code to help track down problems where the target of a near call is
6474          * is not valid.
6475          */
6476         if (amd64_is_near_call (ip)) {
6477                 gint64 disp = (guint8*)target - (guint8*)ip;
6478
6479                 if (!amd64_is_imm32 (disp)) {
6480                         printf ("TYPE: %d\n", ji->type);
6481                         switch (ji->type) {
6482                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6483                                 printf ("V: %s\n", ji->data.name);
6484                                 break;
6485                         case MONO_PATCH_INFO_METHOD_JUMP:
6486                         case MONO_PATCH_INFO_METHOD:
6487                                 printf ("V: %s\n", ji->data.method->name);
6488                                 break;
6489                         default:
6490                                 break;
6491                         }
6492                 }
6493         }
6494
6495         amd64_patch (ip, (gpointer)target);
6496 }
6497
6498 #ifndef DISABLE_JIT
6499
6500 static int
6501 get_max_epilog_size (MonoCompile *cfg)
6502 {
6503         int max_epilog_size = 16;
6504
6505         if (cfg->method->save_lmf)
6506                 max_epilog_size += 256;
6507
6508         if (mono_jit_trace_calls != NULL)
6509                 max_epilog_size += 50;
6510
6511         max_epilog_size += (AMD64_NREG * 2);
6512
6513         return max_epilog_size;
6514 }
6515
6516 /*
6517  * This macro is used for testing whenever the unwinder works correctly at every point
6518  * where an async exception can happen.
6519  */
6520 /* This will generate a SIGSEGV at the given point in the code */
6521 #define async_exc_point(code) do { \
6522     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6523          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6524              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6525          cfg->arch.async_point_count ++; \
6526     } \
6527 } while (0)
6528
6529 #ifdef TARGET_WIN32
6530 static guint8 *
6531 emit_prolog_setup_sp_win64 (MonoCompile *cfg, guint8 *code, int alloc_size, int *cfa_offset_input)
6532 {
6533         int cfa_offset = *cfa_offset_input;
6534
6535         /* Allocate windows stack frame using stack probing method */
6536         if (alloc_size) {
6537
6538                 if (alloc_size >= 0x1000) {
6539                         amd64_mov_reg_imm (code, AMD64_RAX, alloc_size);
6540                         code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_chkstk_win64");
6541                 }
6542
6543                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6544                 if (cfg->arch.omit_fp) {
6545                         cfa_offset += alloc_size;
6546                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6547                         async_exc_point (code);
6548                 }
6549
6550                 // NOTE, in a standard win64 prolog the alloc unwind info is always emitted, but since mono
6551                 // uses a frame pointer with negative offsets and a standard win64 prolog assumes positive offsets, we can't
6552                 // emit sp alloc unwind metadata since the native OS unwinder will incorrectly restore sp. Excluding the alloc
6553                 // metadata on the other hand won't give the OS the information so it can just restore the frame pointer to sp and
6554                 // that will retrieve the expected results.
6555                 if (cfg->arch.omit_fp)
6556                         mono_emit_unwind_op_sp_alloc (cfg, code, alloc_size);
6557         }
6558
6559         *cfa_offset_input = cfa_offset;
6560         return code;
6561 }
6562 #endif /* TARGET_WIN32 */
6563
6564 guint8 *
6565 mono_arch_emit_prolog (MonoCompile *cfg)
6566 {
6567         MonoMethod *method = cfg->method;
6568         MonoBasicBlock *bb;
6569         MonoMethodSignature *sig;
6570         MonoInst *ins;
6571         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6572         guint8 *code;
6573         CallInfo *cinfo;
6574         MonoInst *lmf_var = cfg->lmf_var;
6575         gboolean args_clobbered = FALSE;
6576         gboolean trace = FALSE;
6577
6578         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6579
6580         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6581
6582         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6583                 trace = TRUE;
6584
6585         /* Amount of stack space allocated by register saving code */
6586         pos = 0;
6587
6588         /* Offset between RSP and the CFA */
6589         cfa_offset = 0;
6590
6591         /*
6592          * The prolog consists of the following parts:
6593          * FP present:
6594          * - push rbp
6595          * - mov rbp, rsp
6596          * - save callee saved regs using moves
6597          * - allocate frame
6598          * - save rgctx if needed
6599          * - save lmf if needed
6600          * FP not present:
6601          * - allocate frame
6602          * - save rgctx if needed
6603          * - save lmf if needed
6604          * - save callee saved regs using moves
6605          */
6606
6607         // CFA = sp + 8
6608         cfa_offset = 8;
6609         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6610         // IP saved at CFA - 8
6611         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6612         async_exc_point (code);
6613         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6614
6615         if (!cfg->arch.omit_fp) {
6616                 amd64_push_reg (code, AMD64_RBP);
6617                 cfa_offset += 8;
6618                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6619                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6620                 async_exc_point (code);
6621                 /* These are handled automatically by the stack marking code */
6622                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6623
6624                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6625                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6626                 mono_emit_unwind_op_fp_alloc (cfg, code, AMD64_RBP, 0);
6627                 async_exc_point (code);
6628         }
6629
6630         /* The param area is always at offset 0 from sp */
6631         /* This needs to be allocated here, since it has to come after the spill area */
6632         if (cfg->param_area) {
6633                 if (cfg->arch.omit_fp)
6634                         // FIXME:
6635                         g_assert_not_reached ();
6636                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6637         }
6638
6639         if (cfg->arch.omit_fp) {
6640                 /*
6641                  * On enter, the stack is misaligned by the pushing of the return
6642                  * address. It is either made aligned by the pushing of %rbp, or by
6643                  * this.
6644                  */
6645                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6646                 if ((alloc_size % 16) == 0) {
6647                         alloc_size += 8;
6648                         /* Mark the padding slot as NOREF */
6649                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6650                 }
6651         } else {
6652                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6653                 if (cfg->stack_offset != alloc_size) {
6654                         /* Mark the padding slot as NOREF */
6655                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6656                 }
6657                 cfg->arch.sp_fp_offset = alloc_size;
6658                 alloc_size -= pos;
6659         }
6660
6661         cfg->arch.stack_alloc_size = alloc_size;
6662
6663         /* Allocate stack frame */
6664 #ifdef TARGET_WIN32
6665         code = emit_prolog_setup_sp_win64 (cfg, code, alloc_size, &cfa_offset);
6666 #else
6667         if (alloc_size) {
6668                 /* See mono_emit_stack_alloc */
6669 #if defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6670                 guint32 remaining_size = alloc_size;
6671
6672                 /* Use a loop for large sizes */
6673                 if (remaining_size > 10 * 0x1000) {
6674                         amd64_mov_reg_imm (code, X86_EAX, remaining_size / 0x1000);
6675                         guint8 *label = code;
6676                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6677                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6678                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RAX, 1);
6679                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6680                         guint8 *label2 = code;
6681                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
6682                         amd64_patch (label2, label);
6683                         if (cfg->arch.omit_fp) {
6684                                 cfa_offset += (remaining_size / 0x1000) * 0x1000;
6685                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6686                         }
6687
6688                         remaining_size = remaining_size % 0x1000;
6689                 }
6690
6691                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 11; /*11 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6692                 guint32 offset = code - cfg->native_code;
6693                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6694                         while (required_code_size >= (cfg->code_size - offset))
6695                                 cfg->code_size *= 2;
6696                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6697                         code = cfg->native_code + offset;
6698                         cfg->stat_code_reallocs++;
6699                 }
6700
6701                 while (remaining_size >= 0x1000) {
6702                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6703                         if (cfg->arch.omit_fp) {
6704                                 cfa_offset += 0x1000;
6705                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6706                         }
6707                         async_exc_point (code);
6708
6709                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
6710                         remaining_size -= 0x1000;
6711                 }
6712                 if (remaining_size) {
6713                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
6714                         if (cfg->arch.omit_fp) {
6715                                 cfa_offset += remaining_size;
6716                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6717                                 async_exc_point (code);
6718                         }
6719                 }
6720 #else
6721                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
6722                 if (cfg->arch.omit_fp) {
6723                         cfa_offset += alloc_size;
6724                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6725                         async_exc_point (code);
6726                 }
6727 #endif
6728         }
6729 #endif
6730
6731         /* Stack alignment check */
6732 #if 0
6733         {
6734                 guint8 *buf;
6735
6736                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
6737                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
6738                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
6739                 buf = code;
6740                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
6741                 amd64_breakpoint (code);
6742                 amd64_patch (buf, code);
6743         }
6744 #endif
6745
6746         if (mini_get_debug_options ()->init_stacks) {
6747                 /* Fill the stack frame with a dummy value to force deterministic behavior */
6748
6749                 /* Save registers to the red zone */
6750                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
6751                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
6752
6753                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
6754                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
6755                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
6756
6757                 amd64_cld (code);
6758                 amd64_prefix (code, X86_REP_PREFIX);
6759                 amd64_stosl (code);
6760
6761                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
6762                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
6763         }
6764
6765         /* Save LMF */
6766         if (method->save_lmf)
6767                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
6768
6769         /* Save callee saved registers */
6770         if (cfg->arch.omit_fp) {
6771                 save_area_offset = cfg->arch.reg_save_area_offset;
6772                 /* Save caller saved registers after sp is adjusted */
6773                 /* The registers are saved at the bottom of the frame */
6774                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
6775         } else {
6776                 /* The registers are saved just below the saved rbp */
6777                 save_area_offset = cfg->arch.reg_save_area_offset;
6778         }
6779
6780         for (i = 0; i < AMD64_NREG; ++i) {
6781                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
6782                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
6783
6784                         if (cfg->arch.omit_fp) {
6785                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
6786                                 /* These are handled automatically by the stack marking code */
6787                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
6788                         } else {
6789                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
6790                                 // FIXME: GC
6791                         }
6792
6793                         save_area_offset += 8;
6794                         async_exc_point (code);
6795                 }
6796         }
6797
6798         /* store runtime generic context */
6799         if (cfg->rgctx_var) {
6800                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
6801                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
6802
6803                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
6804
6805                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
6806                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
6807         }
6808
6809         /* compute max_length in order to use short forward jumps */
6810         max_epilog_size = get_max_epilog_size (cfg);
6811         if (cfg->opt & MONO_OPT_BRANCH) {
6812                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
6813                         MonoInst *ins;
6814                         int max_length = 0;
6815
6816                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
6817                                 max_length += 6;
6818                         /* max alignment for loops */
6819                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
6820                                 max_length += LOOP_ALIGNMENT;
6821
6822                         MONO_BB_FOR_EACH_INS (bb, ins) {
6823                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
6824                         }
6825
6826                         /* Take prolog and epilog instrumentation into account */
6827                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
6828                                 max_length += max_epilog_size;
6829
6830                         bb->max_length = max_length;
6831                 }
6832         }
6833
6834         sig = mono_method_signature (method);
6835         pos = 0;
6836
6837         cinfo = (CallInfo *)cfg->arch.cinfo;
6838
6839         if (sig->ret->type != MONO_TYPE_VOID) {
6840                 /* Save volatile arguments to the stack */
6841                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
6842                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
6843         }
6844
6845         /* Keep this in sync with emit_load_volatile_arguments */
6846         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
6847                 ArgInfo *ainfo = cinfo->args + i;
6848
6849                 ins = cfg->args [i];
6850
6851                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
6852                         /* Unused arguments */
6853                         continue;
6854
6855                 /* Save volatile arguments to the stack */
6856                 if (ins->opcode != OP_REGVAR) {
6857                         switch (ainfo->storage) {
6858                         case ArgInIReg: {
6859                                 guint32 size = 8;
6860
6861                                 /* FIXME: I1 etc */
6862                                 /*
6863                                 if (stack_offset & 0x1)
6864                                         size = 1;
6865                                 else if (stack_offset & 0x2)
6866                                         size = 2;
6867                                 else if (stack_offset & 0x4)
6868                                         size = 4;
6869                                 else
6870                                         size = 8;
6871                                 */
6872                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6873
6874                                 /*
6875                                  * Save the original location of 'this',
6876                                  * get_generic_info_from_stack_frame () needs this to properly look up
6877                                  * the argument value during the handling of async exceptions.
6878                                  */
6879                                 if (ins == cfg->args [0]) {
6880                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6881                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
6882                                 }
6883                                 break;
6884                         }
6885                         case ArgInFloatSSEReg:
6886                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6887                                 break;
6888                         case ArgInDoubleSSEReg:
6889                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6890                                 break;
6891                         case ArgValuetypeInReg:
6892                                 for (quad = 0; quad < 2; quad ++) {
6893                                         switch (ainfo->pair_storage [quad]) {
6894                                         case ArgInIReg:
6895                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
6896                                                 break;
6897                                         case ArgInFloatSSEReg:
6898                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6899                                                 break;
6900                                         case ArgInDoubleSSEReg:
6901                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
6902                                                 break;
6903                                         case ArgNone:
6904                                                 break;
6905                                         default:
6906                                                 g_assert_not_reached ();
6907                                         }
6908                                 }
6909                                 break;
6910                         case ArgValuetypeAddrInIReg:
6911                                 if (ainfo->pair_storage [0] == ArgInIReg)
6912                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6913                                 break;
6914                         case ArgValuetypeAddrOnStack:
6915                                 break;
6916                         case ArgGSharedVtInReg:
6917                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
6918                                 break;
6919                         default:
6920                                 break;
6921                         }
6922                 } else {
6923                         /* Argument allocated to (non-volatile) register */
6924                         switch (ainfo->storage) {
6925                         case ArgInIReg:
6926                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6927                                 break;
6928                         case ArgOnStack:
6929                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6930                                 break;
6931                         default:
6932                                 g_assert_not_reached ();
6933                         }
6934
6935                         if (ins == cfg->args [0]) {
6936                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
6937                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
6938                         }
6939                 }
6940         }
6941
6942         if (cfg->method->save_lmf)
6943                 args_clobbered = TRUE;
6944
6945         if (trace) {
6946                 args_clobbered = TRUE;
6947                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6948         }
6949
6950         /*
6951          * Optimize the common case of the first bblock making a call with the same
6952          * arguments as the method. This works because the arguments are still in their
6953          * original argument registers.
6954          * FIXME: Generalize this
6955          */
6956         if (!args_clobbered) {
6957                 MonoBasicBlock *first_bb = cfg->bb_entry;
6958                 MonoInst *next;
6959                 int filter = FILTER_IL_SEQ_POINT;
6960
6961                 next = mono_bb_first_inst (first_bb, filter);
6962                 if (!next && first_bb->next_bb) {
6963                         first_bb = first_bb->next_bb;
6964                         next = mono_bb_first_inst (first_bb, filter);
6965                 }
6966
6967                 if (first_bb->in_count > 1)
6968                         next = NULL;
6969
6970                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6971                         ArgInfo *ainfo = cinfo->args + i;
6972                         gboolean match = FALSE;
6973
6974                         ins = cfg->args [i];
6975                         if (ins->opcode != OP_REGVAR) {
6976                                 switch (ainfo->storage) {
6977                                 case ArgInIReg: {
6978                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6979                                                 if (next->dreg == ainfo->reg) {
6980                                                         NULLIFY_INS (next);
6981                                                         match = TRUE;
6982                                                 } else {
6983                                                         next->opcode = OP_MOVE;
6984                                                         next->sreg1 = ainfo->reg;
6985                                                         /* Only continue if the instruction doesn't change argument regs */
6986                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6987                                                                 match = TRUE;
6988                                                 }
6989                                         }
6990                                         break;
6991                                 }
6992                                 default:
6993                                         break;
6994                                 }
6995                         } else {
6996                                 /* Argument allocated to (non-volatile) register */
6997                                 switch (ainfo->storage) {
6998                                 case ArgInIReg:
6999                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7000                                                 NULLIFY_INS (next);
7001                                                 match = TRUE;
7002                                         }
7003                                         break;
7004                                 default:
7005                                         break;
7006                                 }
7007                         }
7008
7009                         if (match) {
7010                                 next = mono_inst_next (next, filter);
7011                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7012                                 if (!next)
7013                                         break;
7014                         }
7015                 }
7016         }
7017
7018         if (cfg->gen_sdb_seq_points) {
7019                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7020
7021                 /* Initialize seq_point_info_var */
7022                 if (cfg->compile_aot) {
7023                         /* Initialize the variable from a GOT slot */
7024                         /* Same as OP_AOTCONST */
7025                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7026                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7027                         g_assert (info_var->opcode == OP_REGOFFSET);
7028                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7029                 }
7030
7031                 if (cfg->compile_aot) {
7032                         /* Initialize ss_tramp_var */
7033                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7034                         g_assert (ins->opcode == OP_REGOFFSET);
7035
7036                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7037                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7038                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7039                 } else {
7040                         /* Initialize ss_tramp_var */
7041                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7042                         g_assert (ins->opcode == OP_REGOFFSET);
7043
7044                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7045                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7046
7047                         /* Initialize bp_tramp_var */
7048                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7049                         g_assert (ins->opcode == OP_REGOFFSET);
7050
7051                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7052                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7053                 }
7054         }
7055
7056         cfg->code_len = code - cfg->native_code;
7057
7058         g_assert (cfg->code_len < cfg->code_size);
7059
7060         return code;
7061 }
7062
7063 void
7064 mono_arch_emit_epilog (MonoCompile *cfg)
7065 {
7066         MonoMethod *method = cfg->method;
7067         int quad, i;
7068         guint8 *code;
7069         int max_epilog_size;
7070         CallInfo *cinfo;
7071         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7072         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7073
7074         max_epilog_size = get_max_epilog_size (cfg);
7075
7076         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7077                 cfg->code_size *= 2;
7078                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7079                 cfg->stat_code_reallocs++;
7080         }
7081         code = cfg->native_code + cfg->code_len;
7082
7083         cfg->has_unwind_info_for_epilog = TRUE;
7084
7085         /* Mark the start of the epilog */
7086         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7087
7088         /* Save the uwind state which is needed by the out-of-line code */
7089         mono_emit_unwind_op_remember_state (cfg, code);
7090
7091         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7092                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7093
7094         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7095
7096         if (method->save_lmf) {
7097                 /* check if we need to restore protection of the stack after a stack overflow */
7098                 if (!cfg->compile_aot && mono_arch_have_fast_tls () && mono_tls_get_tls_offset (TLS_KEY_JIT_TLS) != -1) {
7099                         guint8 *patch;
7100                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_tls_get_tls_offset (TLS_KEY_JIT_TLS));
7101                         /* we load the value in a separate instruction: this mechanism may be
7102                          * used later as a safer way to do thread interruption
7103                          */
7104                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7105                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7106                         patch = code;
7107                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7108                         /* note that the call trampoline will preserve eax/edx */
7109                         x86_call_reg (code, X86_ECX);
7110                         x86_patch (patch, code);
7111                 } else {
7112                         /* FIXME: maybe save the jit tls in the prolog */
7113                 }
7114                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7115                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7116                 }
7117         }
7118
7119         /* Restore callee saved regs */
7120         for (i = 0; i < AMD64_NREG; ++i) {
7121                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7122                         /* Restore only used_int_regs, not arch.saved_iregs */
7123 #if defined(MONO_SUPPORT_TASKLETS)
7124                         int restore_reg=1;
7125 #else
7126                         int restore_reg=(cfg->used_int_regs & (1 << i));
7127 #endif
7128                         if (restore_reg) {
7129                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7130                                 mono_emit_unwind_op_same_value (cfg, code, i);
7131                                 async_exc_point (code);
7132                         }
7133                         save_area_offset += 8;
7134                 }
7135         }
7136
7137         /* Load returned vtypes into registers if needed */
7138         cinfo = (CallInfo *)cfg->arch.cinfo;
7139         if (cinfo->ret.storage == ArgValuetypeInReg) {
7140                 ArgInfo *ainfo = &cinfo->ret;
7141                 MonoInst *inst = cfg->ret;
7142
7143                 for (quad = 0; quad < 2; quad ++) {
7144                         switch (ainfo->pair_storage [quad]) {
7145                         case ArgInIReg:
7146                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7147                                 break;
7148                         case ArgInFloatSSEReg:
7149                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7150                                 break;
7151                         case ArgInDoubleSSEReg:
7152                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7153                                 break;
7154                         case ArgNone:
7155                                 break;
7156                         default:
7157                                 g_assert_not_reached ();
7158                         }
7159                 }
7160         }
7161
7162         if (cfg->arch.omit_fp) {
7163                 if (cfg->arch.stack_alloc_size) {
7164                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7165                 }
7166         } else {
7167 #ifdef TARGET_WIN32
7168                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, 0);
7169                 amd64_pop_reg (code, AMD64_RBP);
7170                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7171 #else
7172                 amd64_leave (code);
7173                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7174 #endif
7175         }
7176         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7177         async_exc_point (code);
7178         amd64_ret (code);
7179
7180         /* Restore the unwind state to be the same as before the epilog */
7181         mono_emit_unwind_op_restore_state (cfg, code);
7182
7183         cfg->code_len = code - cfg->native_code;
7184
7185         g_assert (cfg->code_len < cfg->code_size);
7186 }
7187
7188 void
7189 mono_arch_emit_exceptions (MonoCompile *cfg)
7190 {
7191         MonoJumpInfo *patch_info;
7192         int nthrows, i;
7193         guint8 *code;
7194         MonoClass *exc_classes [16];
7195         guint8 *exc_throw_start [16], *exc_throw_end [16];
7196         guint32 code_size = 0;
7197
7198         /* Compute needed space */
7199         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7200                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7201                         code_size += 40;
7202                 if (patch_info->type == MONO_PATCH_INFO_R8)
7203                         code_size += 8 + 15; /* sizeof (double) + alignment */
7204                 if (patch_info->type == MONO_PATCH_INFO_R4)
7205                         code_size += 4 + 15; /* sizeof (float) + alignment */
7206                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7207                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7208         }
7209
7210         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7211                 cfg->code_size *= 2;
7212                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7213                 cfg->stat_code_reallocs++;
7214         }
7215
7216         code = cfg->native_code + cfg->code_len;
7217
7218         /* add code to raise exceptions */
7219         nthrows = 0;
7220         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7221                 switch (patch_info->type) {
7222                 case MONO_PATCH_INFO_EXC: {
7223                         MonoClass *exc_class;
7224                         guint8 *buf, *buf2;
7225                         guint32 throw_ip;
7226
7227                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7228
7229                         exc_class = mono_class_load_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7230                         throw_ip = patch_info->ip.i;
7231
7232                         //x86_breakpoint (code);
7233                         /* Find a throw sequence for the same exception class */
7234                         for (i = 0; i < nthrows; ++i)
7235                                 if (exc_classes [i] == exc_class)
7236                                         break;
7237                         if (i < nthrows) {
7238                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7239                                 x86_jump_code (code, exc_throw_start [i]);
7240                                 patch_info->type = MONO_PATCH_INFO_NONE;
7241                         }
7242                         else {
7243                                 buf = code;
7244                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7245                                 buf2 = code;
7246
7247                                 if (nthrows < 16) {
7248                                         exc_classes [nthrows] = exc_class;
7249                                         exc_throw_start [nthrows] = code;
7250                                 }
7251                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7252
7253                                 patch_info->type = MONO_PATCH_INFO_NONE;
7254
7255                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7256
7257                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7258                                 while (buf < buf2)
7259                                         x86_nop (buf);
7260
7261                                 if (nthrows < 16) {
7262                                         exc_throw_end [nthrows] = code;
7263                                         nthrows ++;
7264                                 }
7265                         }
7266                         break;
7267                 }
7268                 default:
7269                         /* do nothing */
7270                         break;
7271                 }
7272                 g_assert(code < cfg->native_code + cfg->code_size);
7273         }
7274
7275         /* Handle relocations with RIP relative addressing */
7276         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7277                 gboolean remove = FALSE;
7278                 guint8 *orig_code = code;
7279
7280                 switch (patch_info->type) {
7281                 case MONO_PATCH_INFO_R8:
7282                 case MONO_PATCH_INFO_R4: {
7283                         guint8 *pos, *patch_pos;
7284                         guint32 target_pos;
7285
7286                         /* The SSE opcodes require a 16 byte alignment */
7287                         code = (guint8*)ALIGN_TO (code, 16);
7288
7289                         pos = cfg->native_code + patch_info->ip.i;
7290                         if (IS_REX (pos [1])) {
7291                                 patch_pos = pos + 5;
7292                                 target_pos = code - pos - 9;
7293                         }
7294                         else {
7295                                 patch_pos = pos + 4;
7296                                 target_pos = code - pos - 8;
7297                         }
7298
7299                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7300                                 *(double*)code = *(double*)patch_info->data.target;
7301                                 code += sizeof (double);
7302                         } else {
7303                                 *(float*)code = *(float*)patch_info->data.target;
7304                                 code += sizeof (float);
7305                         }
7306
7307                         *(guint32*)(patch_pos) = target_pos;
7308
7309                         remove = TRUE;
7310                         break;
7311                 }
7312                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7313                         guint8 *pos;
7314
7315                         if (cfg->compile_aot)
7316                                 continue;
7317
7318                         /*loading is faster against aligned addresses.*/
7319                         code = (guint8*)ALIGN_TO (code, 8);
7320                         memset (orig_code, 0, code - orig_code);
7321
7322                         pos = cfg->native_code + patch_info->ip.i;
7323
7324                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7325                         if (IS_REX (pos [1]))
7326                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7327                         else
7328                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7329
7330                         *(gpointer*)code = (gpointer)patch_info->data.target;
7331                         code += sizeof (gpointer);
7332
7333                         remove = TRUE;
7334                         break;
7335                 }
7336                 default:
7337                         break;
7338                 }
7339
7340                 if (remove) {
7341                         if (patch_info == cfg->patch_info)
7342                                 cfg->patch_info = patch_info->next;
7343                         else {
7344                                 MonoJumpInfo *tmp;
7345
7346                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7347                                         ;
7348                                 tmp->next = patch_info->next;
7349                         }
7350                 }
7351                 g_assert (code < cfg->native_code + cfg->code_size);
7352         }
7353
7354         cfg->code_len = code - cfg->native_code;
7355
7356         g_assert (cfg->code_len < cfg->code_size);
7357
7358 }
7359
7360 #endif /* DISABLE_JIT */
7361
7362 void*
7363 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7364 {
7365         guchar *code = (guchar *)p;
7366         MonoMethodSignature *sig;
7367         MonoInst *inst;
7368         int i, n, stack_area = 0;
7369
7370         /* Keep this in sync with mono_arch_get_argument_info */
7371
7372         if (enable_arguments) {
7373                 /* Allocate a new area on the stack and save arguments there */
7374                 sig = mono_method_signature (cfg->method);
7375
7376                 n = sig->param_count + sig->hasthis;
7377
7378                 stack_area = ALIGN_TO (n * 8, 16);
7379
7380                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7381
7382                 for (i = 0; i < n; ++i) {
7383                         inst = cfg->args [i];
7384
7385                         if (inst->opcode == OP_REGVAR)
7386                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7387                         else {
7388                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7389                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7390                         }
7391                 }
7392         }
7393
7394         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7395         amd64_set_reg_template (code, AMD64_ARG_REG1);
7396         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7397         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7398
7399         if (enable_arguments)
7400                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7401
7402         return code;
7403 }
7404
7405 enum {
7406         SAVE_NONE,
7407         SAVE_STRUCT,
7408         SAVE_EAX,
7409         SAVE_EAX_EDX,
7410         SAVE_XMM
7411 };
7412
7413 void*
7414 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7415 {
7416         guchar *code = (guchar *)p;
7417         int save_mode = SAVE_NONE;
7418         MonoMethod *method = cfg->method;
7419         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7420         int i;
7421
7422         switch (ret_type->type) {
7423         case MONO_TYPE_VOID:
7424                 /* special case string .ctor icall */
7425                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7426                         save_mode = SAVE_EAX;
7427                 else
7428                         save_mode = SAVE_NONE;
7429                 break;
7430         case MONO_TYPE_I8:
7431         case MONO_TYPE_U8:
7432                 save_mode = SAVE_EAX;
7433                 break;
7434         case MONO_TYPE_R4:
7435         case MONO_TYPE_R8:
7436                 save_mode = SAVE_XMM;
7437                 break;
7438         case MONO_TYPE_GENERICINST:
7439                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7440                         save_mode = SAVE_EAX;
7441                         break;
7442                 }
7443                 /* Fall through */
7444         case MONO_TYPE_VALUETYPE:
7445                 save_mode = SAVE_STRUCT;
7446                 break;
7447         default:
7448                 save_mode = SAVE_EAX;
7449                 break;
7450         }
7451
7452         /* Save the result and copy it into the proper argument register */
7453         switch (save_mode) {
7454         case SAVE_EAX:
7455                 amd64_push_reg (code, AMD64_RAX);
7456                 /* Align stack */
7457                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7458                 if (enable_arguments)
7459                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7460                 break;
7461         case SAVE_STRUCT:
7462                 /* FIXME: */
7463                 if (enable_arguments)
7464                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7465                 break;
7466         case SAVE_XMM:
7467                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7468                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7469                 /* Align stack */
7470                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7471                 /*
7472                  * The result is already in the proper argument register so no copying
7473                  * needed.
7474                  */
7475                 break;
7476         case SAVE_NONE:
7477                 break;
7478         default:
7479                 g_assert_not_reached ();
7480         }
7481
7482         /* Set %al since this is a varargs call */
7483         if (save_mode == SAVE_XMM)
7484                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7485         else
7486                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7487
7488         if (preserve_argument_registers) {
7489                 for (i = 0; i < PARAM_REGS; ++i)
7490                         amd64_push_reg (code, param_regs [i]);
7491         }
7492
7493         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7494         amd64_set_reg_template (code, AMD64_ARG_REG1);
7495         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7496
7497         if (preserve_argument_registers) {
7498                 for (i = PARAM_REGS - 1; i >= 0; --i)
7499                         amd64_pop_reg (code, param_regs [i]);
7500         }
7501
7502         /* Restore result */
7503         switch (save_mode) {
7504         case SAVE_EAX:
7505                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7506                 amd64_pop_reg (code, AMD64_RAX);
7507                 break;
7508         case SAVE_STRUCT:
7509                 /* FIXME: */
7510                 break;
7511         case SAVE_XMM:
7512                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7513                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7514                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7515                 break;
7516         case SAVE_NONE:
7517                 break;
7518         default:
7519                 g_assert_not_reached ();
7520         }
7521
7522         return code;
7523 }
7524
7525 void
7526 mono_arch_flush_icache (guint8 *code, gint size)
7527 {
7528         /* Not needed */
7529 }
7530
7531 void
7532 mono_arch_flush_register_windows (void)
7533 {
7534 }
7535
7536 gboolean
7537 mono_arch_is_inst_imm (gint64 imm)
7538 {
7539         return amd64_use_imm32 (imm);
7540 }
7541
7542 /*
7543  * Determine whenever the trap whose info is in SIGINFO is caused by
7544  * integer overflow.
7545  */
7546 gboolean
7547 mono_arch_is_int_overflow (void *sigctx, void *info)
7548 {
7549         MonoContext ctx;
7550         guint8* rip;
7551         int reg;
7552         gint64 value;
7553
7554         mono_sigctx_to_monoctx (sigctx, &ctx);
7555
7556         rip = (guint8*)ctx.gregs [AMD64_RIP];
7557
7558         if (IS_REX (rip [0])) {
7559                 reg = amd64_rex_b (rip [0]);
7560                 rip ++;
7561         }
7562         else
7563                 reg = 0;
7564
7565         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7566                 /* idiv REG */
7567                 reg += x86_modrm_rm (rip [1]);
7568
7569                 value = ctx.gregs [reg];
7570
7571                 if (value == -1)
7572                         return TRUE;
7573         }
7574
7575         return FALSE;
7576 }
7577
7578 guint32
7579 mono_arch_get_patch_offset (guint8 *code)
7580 {
7581         return 3;
7582 }
7583
7584 /**
7585  * \return TRUE if no sw breakpoint was present.
7586  *
7587  * Copy \p size bytes from \p code - \p offset to the buffer \p buf. If the debugger inserted software
7588  * breakpoints in the original code, they are removed in the copy.
7589  */
7590 gboolean
7591 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7592 {
7593         /*
7594          * If method_start is non-NULL we need to perform bound checks, since we access memory
7595          * at code - offset we could go before the start of the method and end up in a different
7596          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7597          * instead.
7598          */
7599         if (!method_start || code - offset >= method_start) {
7600                 memcpy (buf, code - offset, size);
7601         } else {
7602                 int diff = code - method_start;
7603                 memset (buf, 0, size);
7604                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7605         }
7606         return TRUE;
7607 }
7608
7609 int
7610 mono_arch_get_this_arg_reg (guint8 *code)
7611 {
7612         return AMD64_ARG_REG1;
7613 }
7614
7615 gpointer
7616 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
7617 {
7618         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
7619 }
7620
7621 #define MAX_ARCH_DELEGATE_PARAMS 10
7622
7623 static gpointer
7624 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
7625 {
7626         guint8 *code, *start;
7627         GSList *unwind_ops = NULL;
7628         int i;
7629
7630         unwind_ops = mono_arch_get_cie_program ();
7631
7632         if (has_target) {
7633                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7634
7635                 /* Replace the this argument with the target */
7636                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7637                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7638                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7639
7640                 g_assert ((code - start) < 64);
7641                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7642         } else {
7643                 start = code = (guint8 *)mono_global_codeman_reserve (64 + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7644
7645                 if (param_count == 0) {
7646                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7647                 } else {
7648                         /* We have to shift the arguments left */
7649                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7650                         for (i = 0; i < param_count; ++i) {
7651 #ifdef TARGET_WIN32
7652                                 if (i < 3)
7653                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7654                                 else
7655                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
7656 #else
7657                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
7658 #endif
7659                         }
7660
7661                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
7662                 }
7663                 g_assert ((code - start) < 64);
7664                 g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
7665         }
7666
7667         mono_arch_flush_icache (start, code - start);
7668
7669         if (has_target) {
7670                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
7671         } else {
7672                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
7673                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
7674                 g_free (name);
7675         }
7676
7677         if (mono_jit_map_is_enabled ()) {
7678                 char *buff;
7679                 if (has_target)
7680                         buff = (char*)"delegate_invoke_has_target";
7681                 else
7682                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
7683                 mono_emit_jit_tramp (start, code - start, buff);
7684                 if (!has_target)
7685                         g_free (buff);
7686         }
7687         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7688
7689         return start;
7690 }
7691
7692 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
7693
7694 static gpointer
7695 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
7696 {
7697         guint8 *code, *start;
7698         int size = 20;
7699         char *tramp_name;
7700         GSList *unwind_ops;
7701
7702         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
7703                 return NULL;
7704
7705         start = code = (guint8 *)mono_global_codeman_reserve (size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7706
7707         unwind_ops = mono_arch_get_cie_program ();
7708
7709         /* Replace the this argument with the target */
7710         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
7711         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
7712
7713         if (load_imt_reg) {
7714                 /* Load the IMT reg */
7715                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
7716         }
7717
7718         /* Load the vtable */
7719         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
7720         amd64_jump_membase (code, AMD64_RAX, offset);
7721         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
7722
7723         tramp_name = mono_get_delegate_virtual_invoke_impl_name (load_imt_reg, offset);
7724         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
7725         g_free (tramp_name);
7726
7727         return start;
7728 }
7729
7730 /*
7731  * mono_arch_get_delegate_invoke_impls:
7732  *
7733  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7734  * trampolines.
7735  */
7736 GSList*
7737 mono_arch_get_delegate_invoke_impls (void)
7738 {
7739         GSList *res = NULL;
7740         MonoTrampInfo *info;
7741         int i;
7742
7743         get_delegate_invoke_impl (&info, TRUE, 0);
7744         res = g_slist_prepend (res, info);
7745
7746         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
7747                 get_delegate_invoke_impl (&info, FALSE, i);
7748                 res = g_slist_prepend (res, info);
7749         }
7750
7751         for (i = 1; i <= MONO_IMT_SIZE; ++i) {
7752                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
7753                 res = g_slist_prepend (res, info);
7754         }
7755
7756         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
7757                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
7758                 res = g_slist_prepend (res, info);
7759                 get_delegate_virtual_invoke_impl (&info, TRUE, i * SIZEOF_VOID_P);
7760                 res = g_slist_prepend (res, info);
7761         }
7762
7763         return res;
7764 }
7765
7766 gpointer
7767 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7768 {
7769         guint8 *code, *start;
7770         int i;
7771
7772         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7773                 return NULL;
7774
7775         /* FIXME: Support more cases */
7776         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
7777                 return NULL;
7778
7779         if (has_target) {
7780                 static guint8* cached = NULL;
7781
7782                 if (cached)
7783                         return cached;
7784
7785                 if (mono_aot_only) {
7786                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7787                 } else {
7788                         MonoTrampInfo *info;
7789                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
7790                         mono_tramp_info_register (info, NULL);
7791                 }
7792
7793                 mono_memory_barrier ();
7794
7795                 cached = start;
7796         } else {
7797                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7798                 for (i = 0; i < sig->param_count; ++i)
7799                         if (!mono_is_regsize_var (sig->params [i]))
7800                                 return NULL;
7801                 if (sig->param_count > 4)
7802                         return NULL;
7803
7804                 code = cache [sig->param_count];
7805                 if (code)
7806                         return code;
7807
7808                 if (mono_aot_only) {
7809                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7810                         start = (guint8 *)mono_aot_get_trampoline (name);
7811                         g_free (name);
7812                 } else {
7813                         MonoTrampInfo *info;
7814                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
7815                         mono_tramp_info_register (info, NULL);
7816                 }
7817
7818                 mono_memory_barrier ();
7819
7820                 cache [sig->param_count] = start;
7821         }
7822
7823         return start;
7824 }
7825
7826 gpointer
7827 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
7828 {
7829         MonoTrampInfo *info;
7830         gpointer code;
7831
7832         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
7833         if (code)
7834                 mono_tramp_info_register (info, NULL);
7835         return code;
7836 }
7837
7838 void
7839 mono_arch_finish_init (void)
7840 {
7841 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
7842         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7843 #endif
7844 }
7845
7846 void
7847 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7848 {
7849 }
7850
7851 #define CMP_SIZE (6 + 1)
7852 #define CMP_REG_REG_SIZE (4 + 1)
7853 #define BR_SMALL_SIZE 2
7854 #define BR_LARGE_SIZE 6
7855 #define MOV_REG_IMM_SIZE 10
7856 #define MOV_REG_IMM_32BIT_SIZE 6
7857 #define JUMP_REG_SIZE (2 + 1)
7858
7859 static int
7860 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7861 {
7862         int i, distance = 0;
7863         for (i = start; i < target; ++i)
7864                 distance += imt_entries [i]->chunk_size;
7865         return distance;
7866 }
7867
7868 /*
7869  * LOCKING: called with the domain lock held
7870  */
7871 gpointer
7872 mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7873         gpointer fail_tramp)
7874 {
7875         int i;
7876         int size = 0;
7877         guint8 *code, *start;
7878         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7879         GSList *unwind_ops;
7880
7881         for (i = 0; i < count; ++i) {
7882                 MonoIMTCheckItem *item = imt_entries [i];
7883                 if (item->is_equals) {
7884                         if (item->check_target_idx) {
7885                                 if (!item->compare_done) {
7886                                         if (amd64_use_imm32 ((gint64)item->key))
7887                                                 item->chunk_size += CMP_SIZE;
7888                                         else
7889                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7890                                 }
7891                                 if (item->has_target_code) {
7892                                         item->chunk_size += MOV_REG_IMM_SIZE;
7893                                 } else {
7894                                         if (vtable_is_32bit)
7895                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7896                                         else
7897                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7898                                 }
7899                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7900                         } else {
7901                                 if (fail_tramp) {
7902                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7903                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7904                                 } else {
7905                                         if (vtable_is_32bit)
7906                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7907                                         else
7908                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7909                                         item->chunk_size += JUMP_REG_SIZE;
7910                                         /* with assert below:
7911                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7912                                          */
7913                                 }
7914                         }
7915                 } else {
7916                         if (amd64_use_imm32 ((gint64)item->key))
7917                                 item->chunk_size += CMP_SIZE;
7918                         else
7919                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7920                         item->chunk_size += BR_LARGE_SIZE;
7921                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7922                 }
7923                 size += item->chunk_size;
7924         }
7925         if (fail_tramp)
7926                 code = (guint8 *)mono_method_alloc_generic_virtual_trampoline (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7927         else
7928                 code = (guint8 *)mono_domain_code_reserve (domain, size + MONO_TRAMPOLINE_UNWINDINFO_SIZE(0));
7929         start = code;
7930
7931         unwind_ops = mono_arch_get_cie_program ();
7932
7933         for (i = 0; i < count; ++i) {
7934                 MonoIMTCheckItem *item = imt_entries [i];
7935                 item->code_target = code;
7936                 if (item->is_equals) {
7937                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7938
7939                         if (item->check_target_idx || fail_case) {
7940                                 if (!item->compare_done || fail_case) {
7941                                         if (amd64_use_imm32 ((gint64)item->key))
7942                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7943                                         else {
7944                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
7945                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7946                                         }
7947                                 }
7948                                 item->jmp_code = code;
7949                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7950                                 if (item->has_target_code) {
7951                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
7952                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7953                                 } else {
7954                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7955                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7956                                 }
7957
7958                                 if (fail_case) {
7959                                         amd64_patch (item->jmp_code, code);
7960                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
7961                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
7962                                         item->jmp_code = NULL;
7963                                 }
7964                         } else {
7965                                 /* enable the commented code to assert on wrong method */
7966 #if 0
7967                                 if (amd64_is_imm32 (item->key))
7968                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
7969                                 else {
7970                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
7971                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7972                                 }
7973                                 item->jmp_code = code;
7974                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7975                                 /* See the comment below about R10 */
7976                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7977                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7978                                 amd64_patch (item->jmp_code, code);
7979                                 amd64_breakpoint (code);
7980                                 item->jmp_code = NULL;
7981 #else
7982                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
7983                                    needs to be preserved.  R10 needs
7984                                    to be preserved for calls which
7985                                    require a runtime generic context,
7986                                    but interface calls don't. */
7987                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
7988                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
7989 #endif
7990                         }
7991                 } else {
7992                         if (amd64_use_imm32 ((gint64)item->key))
7993                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
7994                         else {
7995                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
7996                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
7997                         }
7998                         item->jmp_code = code;
7999                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8000                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8001                         else
8002                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8003                 }
8004                 g_assert (code - item->code_target <= item->chunk_size);
8005         }
8006         /* patch the branches to get to the target items */
8007         for (i = 0; i < count; ++i) {
8008                 MonoIMTCheckItem *item = imt_entries [i];
8009                 if (item->jmp_code) {
8010                         if (item->check_target_idx) {
8011                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8012                         }
8013                 }
8014         }
8015
8016         if (!fail_tramp)
8017                 mono_stats.imt_trampolines_size += code - start;
8018         g_assert (code - start <= size);
8019         g_assert_checked (mono_arch_unwindinfo_validate_size (unwind_ops, MONO_TRAMPOLINE_UNWINDINFO_SIZE(0)));
8020
8021         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8022
8023         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8024
8025         return start;
8026 }
8027
8028 MonoMethod*
8029 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8030 {
8031         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8032 }
8033
8034 MonoVTable*
8035 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8036 {
8037         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8038 }
8039
8040 GSList*
8041 mono_arch_get_cie_program (void)
8042 {
8043         GSList *l = NULL;
8044
8045         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8046         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8047
8048         return l;
8049 }
8050
8051 #ifndef DISABLE_JIT
8052
8053 MonoInst*
8054 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8055 {
8056         MonoInst *ins = NULL;
8057         int opcode = 0;
8058
8059         if (cmethod->klass == mono_defaults.math_class) {
8060                 if (strcmp (cmethod->name, "Sin") == 0) {
8061                         opcode = OP_SIN;
8062                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8063                         opcode = OP_COS;
8064                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8065                         opcode = OP_SQRT;
8066                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8067                         opcode = OP_ABS;
8068                 }
8069
8070                 if (opcode && fsig->param_count == 1) {
8071                         MONO_INST_NEW (cfg, ins, opcode);
8072                         ins->type = STACK_R8;
8073                         ins->dreg = mono_alloc_freg (cfg);
8074                         ins->sreg1 = args [0]->dreg;
8075                         MONO_ADD_INS (cfg->cbb, ins);
8076                 }
8077
8078                 opcode = 0;
8079                 if (cfg->opt & MONO_OPT_CMOV) {
8080                         if (strcmp (cmethod->name, "Min") == 0) {
8081                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8082                                         opcode = OP_IMIN;
8083                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8084                                         opcode = OP_IMIN_UN;
8085                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8086                                         opcode = OP_LMIN;
8087                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8088                                         opcode = OP_LMIN_UN;
8089                         } else if (strcmp (cmethod->name, "Max") == 0) {
8090                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8091                                         opcode = OP_IMAX;
8092                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8093                                         opcode = OP_IMAX_UN;
8094                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8095                                         opcode = OP_LMAX;
8096                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8097                                         opcode = OP_LMAX_UN;
8098                         }
8099                 }
8100
8101                 if (opcode && fsig->param_count == 2) {
8102                         MONO_INST_NEW (cfg, ins, opcode);
8103                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8104                         ins->dreg = mono_alloc_ireg (cfg);
8105                         ins->sreg1 = args [0]->dreg;
8106                         ins->sreg2 = args [1]->dreg;
8107                         MONO_ADD_INS (cfg->cbb, ins);
8108                 }
8109
8110 #if 0
8111                 /* OP_FREM is not IEEE compatible */
8112                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8113                         MONO_INST_NEW (cfg, ins, OP_FREM);
8114                         ins->inst_i0 = args [0];
8115                         ins->inst_i1 = args [1];
8116                 }
8117 #endif
8118         }
8119
8120         return ins;
8121 }
8122 #endif
8123
8124 gboolean
8125 mono_arch_print_tree (MonoInst *tree, int arity)
8126 {
8127         return 0;
8128 }
8129
8130 mgreg_t
8131 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8132 {
8133         return ctx->gregs [reg];
8134 }
8135
8136 void
8137 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8138 {
8139         ctx->gregs [reg] = val;
8140 }
8141
8142 gpointer
8143 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8144 {
8145         gpointer *sp, old_value;
8146         char *bp;
8147
8148         /*Load the spvar*/
8149         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8150         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8151
8152         old_value = *sp;
8153         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8154                 return old_value;
8155
8156         *sp = new_value;
8157
8158         return old_value;
8159 }
8160
8161 /*
8162  * mono_arch_emit_load_aotconst:
8163  *
8164  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8165  * TARGET from the mscorlib GOT in full-aot code.
8166  * On AMD64, the result is placed into R11.
8167  */
8168 guint8*
8169 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8170 {
8171         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8172         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8173
8174         return code;
8175 }
8176
8177 /*
8178  * mono_arch_get_trampolines:
8179  *
8180  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8181  * for AOT.
8182  */
8183 GSList *
8184 mono_arch_get_trampolines (gboolean aot)
8185 {
8186         return mono_amd64_get_exception_trampolines (aot);
8187 }
8188
8189 /* Soft Debug support */
8190 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8191
8192 /*
8193  * mono_arch_set_breakpoint:
8194  *
8195  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8196  * The location should contain code emitted by OP_SEQ_POINT.
8197  */
8198 void
8199 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8200 {
8201         guint8 *code = ip;
8202
8203         if (ji->from_aot) {
8204                 guint32 native_offset = ip - (guint8*)ji->code_start;
8205                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8206
8207                 g_assert (info->bp_addrs [native_offset] == 0);
8208                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8209         } else {
8210                 /* ip points to a mov r11, 0 */
8211                 g_assert (code [0] == 0x41);
8212                 g_assert (code [1] == 0xbb);
8213                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8214         }
8215 }
8216
8217 /*
8218  * mono_arch_clear_breakpoint:
8219  *
8220  *   Clear the breakpoint at IP.
8221  */
8222 void
8223 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8224 {
8225         guint8 *code = ip;
8226
8227         if (ji->from_aot) {
8228                 guint32 native_offset = ip - (guint8*)ji->code_start;
8229                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8230
8231                 info->bp_addrs [native_offset] = NULL;
8232         } else {
8233                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8234         }
8235 }
8236
8237 gboolean
8238 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8239 {
8240         /* We use soft breakpoints on amd64 */
8241         return FALSE;
8242 }
8243
8244 /*
8245  * mono_arch_skip_breakpoint:
8246  *
8247  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8248  * we resume, the instruction is not executed again.
8249  */
8250 void
8251 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8252 {
8253         g_assert_not_reached ();
8254 }
8255
8256 /*
8257  * mono_arch_start_single_stepping:
8258  *
8259  *   Start single stepping.
8260  */
8261 void
8262 mono_arch_start_single_stepping (void)
8263 {
8264         ss_trampoline = mini_get_single_step_trampoline ();
8265 }
8266
8267 /*
8268  * mono_arch_stop_single_stepping:
8269  *
8270  *   Stop single stepping.
8271  */
8272 void
8273 mono_arch_stop_single_stepping (void)
8274 {
8275         ss_trampoline = NULL;
8276 }
8277
8278 /*
8279  * mono_arch_is_single_step_event:
8280  *
8281  *   Return whenever the machine state in SIGCTX corresponds to a single
8282  * step event.
8283  */
8284 gboolean
8285 mono_arch_is_single_step_event (void *info, void *sigctx)
8286 {
8287         /* We use soft breakpoints on amd64 */
8288         return FALSE;
8289 }
8290
8291 /*
8292  * mono_arch_skip_single_step:
8293  *
8294  *   Modify CTX so the ip is placed after the single step trigger instruction,
8295  * we resume, the instruction is not executed again.
8296  */
8297 void
8298 mono_arch_skip_single_step (MonoContext *ctx)
8299 {
8300         g_assert_not_reached ();
8301 }
8302
8303 /*
8304  * mono_arch_create_seq_point_info:
8305  *
8306  *   Return a pointer to a data structure which is used by the sequence
8307  * point implementation in AOTed code.
8308  */
8309 gpointer
8310 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8311 {
8312         SeqPointInfo *info;
8313         MonoJitInfo *ji;
8314
8315         // FIXME: Add a free function
8316
8317         mono_domain_lock (domain);
8318         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8319                                                                 code);
8320         mono_domain_unlock (domain);
8321
8322         if (!info) {
8323                 ji = mono_jit_info_table_find (domain, (char*)code);
8324                 g_assert (ji);
8325
8326                 // FIXME: Optimize the size
8327                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8328
8329                 info->ss_tramp_addr = &ss_trampoline;
8330
8331                 mono_domain_lock (domain);
8332                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8333                                                          code, info);
8334                 mono_domain_unlock (domain);
8335         }
8336
8337         return info;
8338 }
8339
8340 void
8341 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8342 {
8343         ext->lmf.previous_lmf = prev_lmf;
8344         /* Mark that this is a MonoLMFExt */
8345         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8346         ext->lmf.rsp = (gssize)ext;
8347 }
8348
8349 #endif
8350
8351 gboolean
8352 mono_arch_opcode_supported (int opcode)
8353 {
8354         switch (opcode) {
8355         case OP_ATOMIC_ADD_I4:
8356         case OP_ATOMIC_ADD_I8:
8357         case OP_ATOMIC_EXCHANGE_I4:
8358         case OP_ATOMIC_EXCHANGE_I8:
8359         case OP_ATOMIC_CAS_I4:
8360         case OP_ATOMIC_CAS_I8:
8361         case OP_ATOMIC_LOAD_I1:
8362         case OP_ATOMIC_LOAD_I2:
8363         case OP_ATOMIC_LOAD_I4:
8364         case OP_ATOMIC_LOAD_I8:
8365         case OP_ATOMIC_LOAD_U1:
8366         case OP_ATOMIC_LOAD_U2:
8367         case OP_ATOMIC_LOAD_U4:
8368         case OP_ATOMIC_LOAD_U8:
8369         case OP_ATOMIC_LOAD_R4:
8370         case OP_ATOMIC_LOAD_R8:
8371         case OP_ATOMIC_STORE_I1:
8372         case OP_ATOMIC_STORE_I2:
8373         case OP_ATOMIC_STORE_I4:
8374         case OP_ATOMIC_STORE_I8:
8375         case OP_ATOMIC_STORE_U1:
8376         case OP_ATOMIC_STORE_U2:
8377         case OP_ATOMIC_STORE_U4:
8378         case OP_ATOMIC_STORE_U8:
8379         case OP_ATOMIC_STORE_R4:
8380         case OP_ATOMIC_STORE_R8:
8381                 return TRUE;
8382         default:
8383                 return FALSE;
8384         }
8385 }
8386
8387 CallInfo*
8388 mono_arch_get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
8389 {
8390         return get_call_info (mp, sig);
8391 }