mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16 #include <unistd.h>
  17 #include <sys/mman.h>
  18
  19 #include <mono/metadata/appdomain.h>
  20 #include <mono/metadata/debug-helpers.h>
  21 #include <mono/metadata/threads.h>
  22 #include <mono/metadata/profiler-private.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-amd64.h"
  27 #include "inssel.h"
  28 #include "cpu-amd64.h"
  29
  30 static gint lmf_tls_offset = -1;
  31 static gint appdomain_tls_offset = -1;
  32 static gint thread_tls_offset = -1;
  33
  34 /* Use SSE2 instructions for fp arithmetic */
  35 static gboolean use_sse2 = TRUE;
  36
  37 /* xmm15 is reserved for use by some opcodes */
  38 #define AMD64_CALLEE_FREGS 0xef
  39
  40 #define FPSTACK_SIZE 6
  41
  42 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  43
  44 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  45
  46 #ifdef PLATFORM_WIN32
  47 /* Under windows, the default pinvoke calling convention is stdcall */
  48 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  49 #else
  50 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  51 #endif
  52
  53 #define SIGNAL_STACK_SIZE (64 * 1024)
  54
  55 #define ARGS_OFFSET 16
  56 #define GP_SCRATCH_REG AMD64_R11
  57
  58 /*
  59  * AMD64 register usage:
  60  * - callee saved registers are used for global register allocation
  61  * - %r11 is used for materializing 64 bit constants in opcodes
  62  * - the rest is used for local allocation
  63  */
  64
  65 /*
  66  * Floating point comparison results:
  67  *                  ZF PF CF
  68  * A > B            0  0  0
  69  * A < B            0  0  1
  70  * A = B            1  0  0
  71  * A > B            0  0  0
  72  * UNORDERED        1  1  1
  73  */
  74
  75 #define NOT_IMPLEMENTED g_assert_not_reached ()
  76
  77 const char*
  78 mono_arch_regname (int reg) {
  79         switch (reg) {
  80         case AMD64_RAX: return "%rax";
  81         case AMD64_RBX: return "%rbx";
  82         case AMD64_RCX: return "%rcx";
  83         case AMD64_RDX: return "%rdx";
  84         case AMD64_RSP: return "%rsp";
  85         case AMD64_RBP: return "%rbp";
  86         case AMD64_RDI: return "%rdi";
  87         case AMD64_RSI: return "%rsi";
  88         case AMD64_R8: return "%r8";
  89         case AMD64_R9: return "%r9";
  90         case AMD64_R10: return "%r10";
  91         case AMD64_R11: return "%r11";
  92         case AMD64_R12: return "%r12";
  93         case AMD64_R13: return "%r13";
  94         case AMD64_R14: return "%r14";
  95         case AMD64_R15: return "%r15";
  96         }
  97         return "unknown";
  98 }
  99
 100 static const char * xmmregs [] = {
 101         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 102         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 103 };
 104
 105 static const char*
 106 mono_arch_fregname (int reg)
 107 {
 108         if (reg < AMD64_XMM_NREG)
 109                 return xmmregs [reg];
 110         else
 111                 return "unknown";
 112 }
 113
 114 static const char*
 115 mono_amd64_regname (int reg, gboolean fp)
 116 {
 117         if (fp)
 118                 return mono_arch_fregname (reg);
 119         else
 120                 return mono_arch_regname (reg);
 121 }
 122
 123 static inline void
 124 amd64_patch (unsigned char* code, gpointer target)
 125 {
 126         /* Skip REX */
 127         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 128                 code += 1;
 129
 130         if ((code [0] & 0xf8) == 0xb8) {
 131                 /* amd64_set_reg_template */
 132                 *(guint64*)(code + 1) = (guint64)target;
 133         }
 134         else if (code [0] == 0x8b) {
 135                 /* mov 0(%rip), %dreg */
 136                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 137         }
 138         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 139                 /* call *<OFFSET>(%rip) */
 140                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 141         }
 142         else
 143                 x86_patch (code, (unsigned char*)target);
 144 }
 145
 146 typedef enum {
 147         ArgInIReg,
 148         ArgInFloatSSEReg,
 149         ArgInDoubleSSEReg,
 150         ArgOnStack,
 151         ArgValuetypeInReg,
 152         ArgNone /* only in pair_storage */
 153 } ArgStorage;
 154
 155 typedef struct {
 156         gint16 offset;
 157         gint8  reg;
 158         ArgStorage storage;
 159
 160         /* Only if storage == ArgValuetypeInReg */
 161         ArgStorage pair_storage [2];
 162         gint8 pair_regs [2];
 163 } ArgInfo;
 164
 165 typedef struct {
 166         int nargs;
 167         guint32 stack_usage;
 168         guint32 reg_usage;
 169         guint32 freg_usage;
 170         gboolean need_stack_align;
 171         ArgInfo ret;
 172         ArgInfo sig_cookie;
 173         ArgInfo args [1];
 174 } CallInfo;
 175
 176 #define DEBUG(a) if (cfg->verbose_level > 1) a
 177
 178 #define NEW_ICONST(cfg,dest,val) do {   \
 179                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 180                 (dest)->opcode = OP_ICONST;     \
 181                 (dest)->inst_c0 = (val);        \
 182                 (dest)->type = STACK_I4;        \
 183         } while (0)
 184
 185 #define PARAM_REGS 6
 186
 187 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 188
 189 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 190
 191 static void inline
 192 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 193 {
 194     ainfo->offset = *stack_size;
 195
 196     if (*gr >= PARAM_REGS) {
 197                 ainfo->storage = ArgOnStack;
 198                 (*stack_size) += sizeof (gpointer);
 199     }
 200     else {
 201                 ainfo->storage = ArgInIReg;
 202                 ainfo->reg = param_regs [*gr];
 203                 (*gr) ++;
 204     }
 205 }
 206
 207 #define FLOAT_PARAM_REGS 8
 208
 209 static void inline
 210 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 211 {
 212     ainfo->offset = *stack_size;
 213
 214     if (*gr >= FLOAT_PARAM_REGS) {
 215                 ainfo->storage = ArgOnStack;
 216                 (*stack_size) += sizeof (gpointer);
 217     }
 218     else {
 219                 /* A double register */
 220                 if (is_double)
 221                         ainfo->storage = ArgInDoubleSSEReg;
 222                 else
 223                         ainfo->storage = ArgInFloatSSEReg;
 224                 ainfo->reg = *gr;
 225                 (*gr) += 1;
 226     }
 227 }
 228
 229 typedef enum ArgumentClass {
 230         ARG_CLASS_NO_CLASS,
 231         ARG_CLASS_MEMORY,
 232         ARG_CLASS_INTEGER,
 233         ARG_CLASS_SSE
 234 } ArgumentClass;
 235
 236 static ArgumentClass
 237 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 238 {
 239         ArgumentClass class2;
 240         MonoType *ptype;
 241
 242         ptype = mono_type_get_underlying_type (type);
 243         switch (ptype->type) {
 244         case MONO_TYPE_BOOLEAN:
 245         case MONO_TYPE_CHAR:
 246         case MONO_TYPE_I1:
 247         case MONO_TYPE_U1:
 248         case MONO_TYPE_I2:
 249         case MONO_TYPE_U2:
 250         case MONO_TYPE_I4:
 251         case MONO_TYPE_U4:
 252         case MONO_TYPE_I:
 253         case MONO_TYPE_U:
 254         case MONO_TYPE_STRING:
 255         case MONO_TYPE_OBJECT:
 256         case MONO_TYPE_CLASS:
 257         case MONO_TYPE_SZARRAY:
 258         case MONO_TYPE_PTR:
 259         case MONO_TYPE_FNPTR:
 260         case MONO_TYPE_ARRAY:
 261         case MONO_TYPE_I8:
 262         case MONO_TYPE_U8:
 263                 class2 = ARG_CLASS_INTEGER;
 264                 break;
 265         case MONO_TYPE_R4:
 266         case MONO_TYPE_R8:
 267                 class2 = ARG_CLASS_SSE;
 268                 break;
 269
 270         case MONO_TYPE_TYPEDBYREF:
 271                 g_assert_not_reached ();
 272
 273         case MONO_TYPE_VALUETYPE: {
 274                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 275                 int i;
 276
 277                 for (i = 0; i < info->num_fields; ++i) {
 278                         class2 = class1;
 279                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 280                 }
 281                 break;
 282         }
 283         default:
 284                 g_assert_not_reached ();
 285         }
 286
 287         /* Merge */
 288         if (class1 == class2)
 289                 ;
 290         else if (class1 == ARG_CLASS_NO_CLASS)
 291                 class1 = class2;
 292         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 293                 class1 = ARG_CLASS_MEMORY;
 294         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 295                 class1 = ARG_CLASS_INTEGER;
 296         else
 297                 class1 = ARG_CLASS_SSE;
 298
 299         return class1;
 300 }
 301
 302 static void
 303 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 304                gboolean is_return,
 305                guint32 *gr, guint32 *fr, guint32 *stack_size)
 306 {
 307         guint32 size, quad, nquads, i;
 308         ArgumentClass args [2];
 309         MonoMarshalType *info;
 310         MonoClass *klass;
 311
 312         klass = mono_class_from_mono_type (type);
 313         if (sig->pinvoke)
 314                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 315         else
 316                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 317
 318         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 319                 /* Allways pass in memory */
 320                 ainfo->offset = *stack_size;
 321                 *stack_size += ALIGN_TO (size, 8);
 322                 ainfo->storage = ArgOnStack;
 323
 324                 return;
 325         }
 326
 327         /* FIXME: Handle structs smaller than 8 bytes */
 328         //if ((size % 8) != 0)
 329         //      NOT_IMPLEMENTED;
 330
 331         if (size > 8)
 332                 nquads = 2;
 333         else
 334                 nquads = 1;
 335
 336         /*
 337          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 338          * The X87 and SSEUP stuff is left out since there are no such types in
 339          * the CLR.
 340          */
 341         info = mono_marshal_load_type_info (klass);
 342         g_assert (info);
 343         if (info->native_size > 16) {
 344                 ainfo->offset = *stack_size;
 345                 *stack_size += ALIGN_TO (info->native_size, 8);
 346                 ainfo->storage = ArgOnStack;
 347
 348                 return;
 349         }
 350
 351         for (quad = 0; quad < nquads; ++quad) {
 352                 int size, align;
 353                 ArgumentClass class1;
 354
 355                 class1 = ARG_CLASS_NO_CLASS;
 356                 for (i = 0; i < info->num_fields; ++i) {
 357                         size = mono_marshal_type_size (info->fields [i].field->type,
 358                                                                                    info->fields [i].mspec,
 359                                                                                    &align, TRUE, klass->unicode);
 360                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 361                                 /* Unaligned field */
 362                                 NOT_IMPLEMENTED;
 363                         }
 364
 365                         /* Skip fields in other quad */
 366                         if ((quad == 0) && (info->fields [i].offset >= 8))
 367                                 continue;
 368                         if ((quad == 1) && (info->fields [i].offset < 8))
 369                                 continue;
 370
 371                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 372                 }
 373                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 374                 args [quad] = class1;
 375         }
 376
 377         /* Post merger cleanup */
 378         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 379                 args [0] = args [1] = ARG_CLASS_MEMORY;
 380
 381         /* Allocate registers */
 382         {
 383                 int orig_gr = *gr;
 384                 int orig_fr = *fr;
 385
 386                 ainfo->storage = ArgValuetypeInReg;
 387                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 388                 for (quad = 0; quad < nquads; ++quad) {
 389                         switch (args [quad]) {
 390                         case ARG_CLASS_INTEGER:
 391                                 if (*gr >= PARAM_REGS)
 392                                         args [quad] = ARG_CLASS_MEMORY;
 393                                 else {
 394                                         ainfo->pair_storage [quad] = ArgInIReg;
 395                                         if (is_return)
 396                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 397                                         else
 398                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 399                                         (*gr) ++;
 400                                 }
 401                                 break;
 402                         case ARG_CLASS_SSE:
 403                                 if (*fr >= FLOAT_PARAM_REGS)
 404                                         args [quad] = ARG_CLASS_MEMORY;
 405                                 else {
 406                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 407                                         ainfo->pair_regs [quad] = *fr;
 408                                         (*fr) ++;
 409                                 }
 410                                 break;
 411                         case ARG_CLASS_MEMORY:
 412                                 break;
 413                         default:
 414                                 g_assert_not_reached ();
 415                         }
 416                 }
 417
 418                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 419                         /* Revert possible register assignments */
 420                         *gr = orig_gr;
 421                         *fr = orig_fr;
 422
 423                         ainfo->offset = *stack_size;
 424                         *stack_size += ALIGN_TO (info->native_size, 8);
 425                         ainfo->storage = ArgOnStack;
 426                 }
 427         }
 428 }
 429
 430 /*
 431  * get_call_info:
 432  *
 433  *  Obtain information about a call according to the calling convention.
 434  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 435  * Draft Version 0.23" document for more information.
 436  */
 437 static CallInfo*
 438 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 439 {
 440         guint32 i, gr, fr;
 441         MonoType *ret_type;
 442         int n = sig->hasthis + sig->param_count;
 443         guint32 stack_size = 0;
 444         CallInfo *cinfo;
 445
 446         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 447
 448         gr = 0;
 449         fr = 0;
 450
 451         /* return value */
 452         {
 453                 ret_type = mono_type_get_underlying_type (sig->ret);
 454                 switch (ret_type->type) {
 455                 case MONO_TYPE_BOOLEAN:
 456                 case MONO_TYPE_I1:
 457                 case MONO_TYPE_U1:
 458                 case MONO_TYPE_I2:
 459                 case MONO_TYPE_U2:
 460                 case MONO_TYPE_CHAR:
 461                 case MONO_TYPE_I4:
 462                 case MONO_TYPE_U4:
 463                 case MONO_TYPE_I:
 464                 case MONO_TYPE_U:
 465                 case MONO_TYPE_PTR:
 466                 case MONO_TYPE_FNPTR:
 467                 case MONO_TYPE_CLASS:
 468                 case MONO_TYPE_OBJECT:
 469                 case MONO_TYPE_SZARRAY:
 470                 case MONO_TYPE_ARRAY:
 471                 case MONO_TYPE_STRING:
 472                         cinfo->ret.storage = ArgInIReg;
 473                         cinfo->ret.reg = AMD64_RAX;
 474                         break;
 475                 case MONO_TYPE_U8:
 476                 case MONO_TYPE_I8:
 477                         cinfo->ret.storage = ArgInIReg;
 478                         cinfo->ret.reg = AMD64_RAX;
 479                         break;
 480                 case MONO_TYPE_R4:
 481                         cinfo->ret.storage = ArgInFloatSSEReg;
 482                         cinfo->ret.reg = AMD64_XMM0;
 483                         break;
 484                 case MONO_TYPE_R8:
 485                         cinfo->ret.storage = ArgInDoubleSSEReg;
 486                         cinfo->ret.reg = AMD64_XMM0;
 487                         break;
 488                 case MONO_TYPE_VALUETYPE: {
 489                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 490
 491                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 492                         if (cinfo->ret.storage == ArgOnStack)
 493                                 /* The caller passes the address where the value is stored */
 494                                 add_general (&gr, &stack_size, &cinfo->ret);
 495                         break;
 496                 }
 497                 case MONO_TYPE_TYPEDBYREF:
 498                         /* Same as a valuetype with size 24 */
 499                         add_general (&gr, &stack_size, &cinfo->ret);
 500                         ;
 501                         break;
 502                 case MONO_TYPE_VOID:
 503                         break;
 504                 default:
 505                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 506                 }
 507         }
 508
 509         /* this */
 510         if (sig->hasthis)
 511                 add_general (&gr, &stack_size, cinfo->args + 0);
 512
 513         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 514                 gr = PARAM_REGS;
 515                 fr = FLOAT_PARAM_REGS;
 516
 517                 /* Emit the signature cookie just before the implicit arguments */
 518                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 519         }
 520
 521         for (i = 0; i < sig->param_count; ++i) {
 522                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 523                 MonoType *ptype;
 524
 525                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 526                         /* We allways pass the sig cookie on the stack for simplicity */
 527                         /*
 528                          * Prevent implicit arguments + the sig cookie from being passed
 529                          * in registers.
 530                          */
 531                         gr = PARAM_REGS;
 532                         fr = FLOAT_PARAM_REGS;
 533
 534                         /* Emit the signature cookie just before the implicit arguments */
 535                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 536                 }
 537
 538                 if (sig->params [i]->byref) {
 539                         add_general (&gr, &stack_size, ainfo);
 540                         continue;
 541                 }
 542                 ptype = mono_type_get_underlying_type (sig->params [i]);
 543                 switch (ptype->type) {
 544                 case MONO_TYPE_BOOLEAN:
 545                 case MONO_TYPE_I1:
 546                 case MONO_TYPE_U1:
 547                         add_general (&gr, &stack_size, ainfo);
 548                         break;
 549                 case MONO_TYPE_I2:
 550                 case MONO_TYPE_U2:
 551                 case MONO_TYPE_CHAR:
 552                         add_general (&gr, &stack_size, ainfo);
 553                         break;
 554                 case MONO_TYPE_I4:
 555                 case MONO_TYPE_U4:
 556                         add_general (&gr, &stack_size, ainfo);
 557                         break;
 558                 case MONO_TYPE_I:
 559                 case MONO_TYPE_U:
 560                 case MONO_TYPE_PTR:
 561                 case MONO_TYPE_FNPTR:
 562                 case MONO_TYPE_CLASS:
 563                 case MONO_TYPE_OBJECT:
 564                 case MONO_TYPE_STRING:
 565                 case MONO_TYPE_SZARRAY:
 566                 case MONO_TYPE_ARRAY:
 567                         add_general (&gr, &stack_size, ainfo);
 568                         break;
 569                 case MONO_TYPE_VALUETYPE:
 570                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 571                         break;
 572                 case MONO_TYPE_TYPEDBYREF:
 573                         stack_size += sizeof (MonoTypedRef);
 574                         ainfo->storage = ArgOnStack;
 575                         break;
 576                 case MONO_TYPE_U8:
 577                 case MONO_TYPE_I8:
 578                         add_general (&gr, &stack_size, ainfo);
 579                         break;
 580                 case MONO_TYPE_R4:
 581                         add_float (&fr, &stack_size, ainfo, FALSE);
 582                         break;
 583                 case MONO_TYPE_R8:
 584                         add_float (&fr, &stack_size, ainfo, TRUE);
 585                         break;
 586                 default:
 587                         g_assert_not_reached ();
 588                 }
 589         }
 590
 591         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 592                 gr = PARAM_REGS;
 593                 fr = FLOAT_PARAM_REGS;
 594
 595                 /* Emit the signature cookie just before the implicit arguments */
 596                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 597         }
 598
 599         if (stack_size & 0x8) {
 600                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 601                 cinfo->need_stack_align = TRUE;
 602                 stack_size += 8;
 603         }
 604
 605         cinfo->stack_usage = stack_size;
 606         cinfo->reg_usage = gr;
 607         cinfo->freg_usage = fr;
 608         return cinfo;
 609 }
 610
 611 /*
 612  * mono_arch_get_argument_info:
 613  * @csig:  a method signature
 614  * @param_count: the number of parameters to consider
 615  * @arg_info: an array to store the result infos
 616  *
 617  * Gathers information on parameters such as size, alignment and
 618  * padding. arg_info should be large enought to hold param_count + 1 entries.
 619  *
 620  * Returns the size of the argument area on the stack.
 621  */
 622 int
 623 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 624 {
 625         int k;
 626         CallInfo *cinfo = get_call_info (csig, FALSE);
 627         guint32 args_size = cinfo->stack_usage;
 628
 629         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 630         if (csig->hasthis) {
 631                 arg_info [0].offset = 0;
 632         }
 633
 634         for (k = 0; k < param_count; k++) {
 635                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 636                 /* FIXME: */
 637                 arg_info [k + 1].size = 0;
 638         }
 639
 640         g_free (cinfo);
 641
 642         return args_size;
 643 }
 644
 645 static int
 646 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 647 {
 648         return 0;
 649 }
 650
 651 /*
 652  * Initialize the cpu to execute managed code.
 653  */
 654 void
 655 mono_arch_cpu_init (void)
 656 {
 657         guint16 fpcw;
 658
 659         /* spec compliance requires running with double precision */
 660         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 661         fpcw &= ~X86_FPCW_PRECC_MASK;
 662         fpcw |= X86_FPCW_PREC_DOUBLE;
 663         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 664         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 665 }
 666
 667 /*
 668  * This function returns the optimizations supported on this cpu.
 669  */
 670 guint32
 671 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 672 {
 673         int eax, ebx, ecx, edx;
 674         guint32 opts = 0;
 675
 676         /* FIXME: AMD64 */
 677
 678         *exclude_mask = 0;
 679         /* Feature Flags function, flags returned in EDX. */
 680         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 681                 if (edx & (1 << 15)) {
 682                         opts |= MONO_OPT_CMOV;
 683                         if (edx & 1)
 684                                 opts |= MONO_OPT_FCMOV;
 685                         else
 686                                 *exclude_mask |= MONO_OPT_FCMOV;
 687                 } else
 688                         *exclude_mask |= MONO_OPT_CMOV;
 689         }
 690         return opts;
 691 }
 692
 693 gboolean
 694 mono_amd64_is_sse2 (void)
 695 {
 696         return use_sse2;
 697 }
 698
 699 static gboolean
 700 is_regsize_var (MonoType *t) {
 701         if (t->byref)
 702                 return TRUE;
 703         t = mono_type_get_underlying_type (t);
 704         switch (t->type) {
 705         case MONO_TYPE_I4:
 706         case MONO_TYPE_U4:
 707         case MONO_TYPE_I:
 708         case MONO_TYPE_U:
 709         case MONO_TYPE_PTR:
 710         case MONO_TYPE_FNPTR:
 711                 return TRUE;
 712         case MONO_TYPE_OBJECT:
 713         case MONO_TYPE_STRING:
 714         case MONO_TYPE_CLASS:
 715         case MONO_TYPE_SZARRAY:
 716         case MONO_TYPE_ARRAY:
 717                 return TRUE;
 718         case MONO_TYPE_VALUETYPE:
 719                 return FALSE;
 720         }
 721         return FALSE;
 722 }
 723
 724 GList *
 725 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 726 {
 727         GList *vars = NULL;
 728         int i;
 729
 730         for (i = 0; i < cfg->num_varinfo; i++) {
 731                 MonoInst *ins = cfg->varinfo [i];
 732                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 733
 734                 /* unused vars */
 735                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 736                         continue;
 737
 738                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 739                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 740                         continue;
 741
 742                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 743                  * 8bit quantities in caller saved registers on x86 */
 744                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 745                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 746                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 747                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 748                         g_assert (i == vmv->idx);
 749                         vars = g_list_prepend (vars, vmv);
 750                 }
 751         }
 752
 753         vars = mono_varlist_sort (cfg, vars, 0);
 754
 755         return vars;
 756 }
 757
 758 GList *
 759 mono_arch_get_global_int_regs (MonoCompile *cfg)
 760 {
 761         GList *regs = NULL;
 762
 763         /* We use the callee saved registers for global allocation */
 764         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 765         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 766         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 767         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 768         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 769
 770         return regs;
 771 }
 772
 773 /*
 774  * mono_arch_regalloc_cost:
 775  *
 776  *  Return the cost, in number of memory references, of the action of
 777  * allocating the variable VMV into a register during global register
 778  * allocation.
 779  */
 780 guint32
 781 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 782 {
 783         MonoInst *ins = cfg->varinfo [vmv->idx];
 784
 785         if (cfg->method->save_lmf)
 786                 /* The register is already saved */
 787                 /* substract 1 for the invisible store in the prolog */
 788                 return (ins->opcode == OP_ARG) ? 0 : 1;
 789         else
 790                 /* push+pop */
 791                 return (ins->opcode == OP_ARG) ? 1 : 2;
 792 }
 793
 794 void
 795 mono_arch_allocate_vars (MonoCompile *m)
 796 {
 797         MonoMethodSignature *sig;
 798         MonoMethodHeader *header;
 799         MonoInst *inst;
 800         int i, offset;
 801         guint32 locals_stack_size, locals_stack_align;
 802         gint32 *offsets;
 803         CallInfo *cinfo;
 804
 805         header = mono_method_get_header (m->method);
 806
 807         sig = mono_method_signature (m->method);
 808
 809         cinfo = get_call_info (sig, FALSE);
 810
 811         /*
 812          * We use the ABI calling conventions for managed code as well.
 813          * Exception: valuetypes are never passed or returned in registers.
 814          */
 815
 816         /* Locals are allocated backwards from %fp */
 817         m->frame_reg = AMD64_RBP;
 818         offset = 0;
 819
 820         /* Reserve space for caller saved registers */
 821         for (i = 0; i < AMD64_NREG; ++i)
 822                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (m->used_int_regs & (1 << i))) {
 823                         offset += sizeof (gpointer);
 824                 }
 825
 826         if (m->method->save_lmf) {
 827                 /* Reserve stack space for saving LMF + argument regs */
 828                 offset += sizeof (MonoLMF);
 829                 if (lmf_tls_offset == -1)
 830                         /* Need to save argument regs too */
 831                         offset += (AMD64_NREG * 8) + (8 * 8);
 832                 m->arch.lmf_offset = offset;
 833         }
 834
 835         if (sig->ret->type != MONO_TYPE_VOID) {
 836                 switch (cinfo->ret.storage) {
 837                 case ArgInIReg:
 838                 case ArgInFloatSSEReg:
 839                 case ArgInDoubleSSEReg:
 840                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
 841                                 /* The register is volatile */
 842                                 m->ret->opcode = OP_REGOFFSET;
 843                                 m->ret->inst_basereg = AMD64_RBP;
 844                                 offset += 8;
 845                                 m->ret->inst_offset = - offset;
 846                         }
 847                         else {
 848                                 m->ret->opcode = OP_REGVAR;
 849                                 m->ret->inst_c0 = cinfo->ret.reg;
 850                         }
 851                         break;
 852                 case ArgValuetypeInReg:
 853                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
 854                         offset += 16;
 855                         m->ret->opcode = OP_REGOFFSET;
 856                         m->ret->inst_basereg = AMD64_RBP;
 857                         m->ret->inst_offset = - offset;
 858                         break;
 859                 default:
 860                         g_assert_not_reached ();
 861                 }
 862                 m->ret->dreg = m->ret->inst_c0;
 863         }
 864
 865         /* Allocate locals */
 866         offsets = mono_allocate_stack_slots (m, &locals_stack_size, &locals_stack_align);
 867         if (locals_stack_align) {
 868                 offset += (locals_stack_align - 1);
 869                 offset &= ~(locals_stack_align - 1);
 870         }
 871         for (i = m->locals_start; i < m->num_varinfo; i++) {
 872                 if (offsets [i] != -1) {
 873                         MonoInst *inst = m->varinfo [i];
 874                         inst->opcode = OP_REGOFFSET;
 875                         inst->inst_basereg = AMD64_RBP;
 876                         inst->inst_offset = - (offset + offsets [i]);
 877                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
 878                 }
 879         }
 880         g_free (offsets);
 881         offset += locals_stack_size;
 882
 883         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
 884                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
 885                 m->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
 886         }
 887
 888         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 889                 inst = m->varinfo [i];
 890                 if (inst->opcode != OP_REGVAR) {
 891                         ArgInfo *ainfo = &cinfo->args [i];
 892                         gboolean inreg = TRUE;
 893                         MonoType *arg_type;
 894
 895                         if (sig->hasthis && (i == 0))
 896                                 arg_type = &mono_defaults.object_class->byval_arg;
 897                         else
 898                                 arg_type = sig->params [i - sig->hasthis];
 899
 900                         /* FIXME: Allocate volatile arguments to registers */
 901                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
 902                                 inreg = FALSE;
 903
 904                         /*
 905                          * Under AMD64, all registers used to pass arguments to functions
 906                          * are volatile across calls.
 907                          * FIXME: Optimize this.
 908                          */
 909                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
 910                                 inreg = FALSE;
 911
 912                         inst->opcode = OP_REGOFFSET;
 913
 914                         switch (ainfo->storage) {
 915                         case ArgInIReg:
 916                         case ArgInFloatSSEReg:
 917                         case ArgInDoubleSSEReg:
 918                                 inst->opcode = OP_REGVAR;
 919                                 inst->dreg = ainfo->reg;
 920                                 break;
 921                         case ArgOnStack:
 922                                 inst->opcode = OP_REGOFFSET;
 923                                 inst->inst_basereg = AMD64_RBP;
 924                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
 925                                 break;
 926                         case ArgValuetypeInReg:
 927                                 break;
 928                         default:
 929                                 NOT_IMPLEMENTED;
 930                         }
 931
 932                         if (!inreg && (ainfo->storage != ArgOnStack)) {
 933                                 inst->opcode = OP_REGOFFSET;
 934                                 inst->inst_basereg = AMD64_RBP;
 935                                 /* These arguments are saved to the stack in the prolog */
 936                                 if (ainfo->storage == ArgValuetypeInReg)
 937                                         offset += 2 * sizeof (gpointer);
 938                                 else
 939                                         offset += sizeof (gpointer);
 940                                 inst->inst_offset = - offset;
 941                         }
 942                 }
 943         }
 944
 945         m->stack_offset = offset;
 946
 947         g_free (cinfo);
 948 }
 949
 950 void
 951 mono_arch_create_vars (MonoCompile *cfg)
 952 {
 953         MonoMethodSignature *sig;
 954         CallInfo *cinfo;
 955
 956         sig = mono_method_signature (cfg->method);
 957
 958         cinfo = get_call_info (sig, FALSE);
 959
 960         if (cinfo->ret.storage == ArgValuetypeInReg)
 961                 cfg->ret_var_is_local = TRUE;
 962
 963         g_free (cinfo);
 964 }
 965
 966 static void
 967 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
 968 {
 969         switch (storage) {
 970         case ArgInIReg:
 971                 arg->opcode = OP_OUTARG_REG;
 972                 arg->inst_left = tree;
 973                 arg->inst_right = (MonoInst*)call;
 974                 arg->unused = reg;
 975                 call->used_iregs |= 1 << reg;
 976                 break;
 977         case ArgInFloatSSEReg:
 978                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
 979                 arg->inst_left = tree;
 980                 arg->inst_right = (MonoInst*)call;
 981                 arg->unused = reg;
 982                 call->used_fregs |= 1 << reg;
 983                 break;
 984         case ArgInDoubleSSEReg:
 985                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
 986                 arg->inst_left = tree;
 987                 arg->inst_right = (MonoInst*)call;
 988                 arg->unused = reg;
 989                 call->used_fregs |= 1 << reg;
 990                 break;
 991         default:
 992                 g_assert_not_reached ();
 993         }
 994 }
 995
 996 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
 997  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
 998  */
 999
1000 static int
1001 arg_storage_to_ldind (ArgStorage storage)
1002 {
1003         switch (storage) {
1004         case ArgInIReg:
1005                 return CEE_LDIND_I;
1006         case ArgInDoubleSSEReg:
1007                 return CEE_LDIND_R8;
1008         case ArgInFloatSSEReg:
1009                 return CEE_LDIND_R4;
1010         default:
1011                 g_assert_not_reached ();
1012         }
1013
1014         return -1;
1015 }
1016
1017 /*
1018  * take the arguments and generate the arch-specific
1019  * instructions to properly call the function in call.
1020  * This includes pushing, moving arguments to the right register
1021  * etc.
1022  * Issue: who does the spilling if needed, and when?
1023  */
1024 MonoCallInst*
1025 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1026         MonoInst *arg, *in;
1027         MonoMethodSignature *sig;
1028         int i, n, stack_size;
1029         CallInfo *cinfo;
1030         ArgInfo *ainfo;
1031
1032         stack_size = 0;
1033
1034         sig = call->signature;
1035         n = sig->param_count + sig->hasthis;
1036
1037         cinfo = get_call_info (sig, sig->pinvoke);
1038
1039         for (i = 0; i < n; ++i) {
1040                 ainfo = cinfo->args + i;
1041
1042                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1043                         MonoMethodSignature *tmp_sig;
1044
1045                         /* Emit the signature cookie just before the implicit arguments */
1046                         MonoInst *sig_arg;
1047                         /* FIXME: Add support for signature tokens to AOT */
1048                         cfg->disable_aot = TRUE;
1049
1050                         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1051
1052                         /*
1053                          * mono_ArgIterator_Setup assumes the signature cookie is
1054                          * passed first and all the arguments which were before it are
1055                          * passed on the stack after the signature. So compensate by
1056                          * passing a different signature.
1057                          */
1058                         tmp_sig = mono_metadata_signature_dup (call->signature);
1059                         tmp_sig->param_count -= call->signature->sentinelpos;
1060                         tmp_sig->sentinelpos = 0;
1061                         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1062
1063                         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1064                         sig_arg->inst_p0 = tmp_sig;
1065
1066                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1067                         arg->inst_left = sig_arg;
1068                         arg->type = STACK_PTR;
1069
1070                         /* prepend, so they get reversed */
1071                         arg->next = call->out_args;
1072                         call->out_args = arg;
1073                 }
1074
1075                 if (is_virtual && i == 0) {
1076                         /* the argument will be attached to the call instruction */
1077                         in = call->args [i];
1078                 } else {
1079                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1080                         in = call->args [i];
1081                         arg->cil_code = in->cil_code;
1082                         arg->inst_left = in;
1083                         arg->type = in->type;
1084                         /* prepend, so they get reversed */
1085                         arg->next = call->out_args;
1086                         call->out_args = arg;
1087
1088                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1089                                 gint align;
1090                                 guint32 size;
1091
1092                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1093                                         size = sizeof (MonoTypedRef);
1094                                         align = sizeof (gpointer);
1095                                 }
1096                                 else
1097                                 if (sig->pinvoke)
1098                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1099                                 else
1100                                         size = mono_type_stack_size (&in->klass->byval_arg, &align);
1101                                 if (ainfo->storage == ArgValuetypeInReg) {
1102                                         if (ainfo->pair_storage [1] == ArgNone) {
1103                                                 MonoInst *load;
1104
1105                                                 /* Simpler case */
1106
1107                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1108                                                 load->inst_left = in;
1109
1110                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1111                                         }
1112                                         else {
1113                                                 /* Trees can't be shared so make a copy */
1114                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1115                                                 MonoInst *load, *load2, *offset_ins;
1116
1117                                                 /* Reg1 */
1118                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1119                                                 load->ssa_op = MONO_SSA_LOAD;
1120                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1121
1122                                                 NEW_ICONST (cfg, offset_ins, 0);
1123                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1124                                                 load2->inst_left = load;
1125                                                 load2->inst_right = offset_ins;
1126
1127                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1128                                                 load->inst_left = load2;
1129
1130                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1131
1132                                                 /* Reg2 */
1133                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1134                                                 load->ssa_op = MONO_SSA_LOAD;
1135                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1136
1137                                                 NEW_ICONST (cfg, offset_ins, 8);
1138                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1139                                                 load2->inst_left = load;
1140                                                 load2->inst_right = offset_ins;
1141
1142                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1143                                                 load->inst_left = load2;
1144
1145                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1146                                                 arg->cil_code = in->cil_code;
1147                                                 arg->type = in->type;
1148                                                 /* prepend, so they get reversed */
1149                                                 arg->next = call->out_args;
1150                                                 call->out_args = arg;
1151
1152                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1153
1154                                                 /* Prepend a copy inst */
1155                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1156                                                 arg->cil_code = in->cil_code;
1157                                                 arg->ssa_op = MONO_SSA_STORE;
1158                                                 arg->inst_left = vtaddr;
1159                                                 arg->inst_right = in;
1160                                                 arg->type = in->type;
1161
1162                                                 /* prepend, so they get reversed */
1163                                                 arg->next = call->out_args;
1164                                                 call->out_args = arg;
1165                                         }
1166                                 }
1167                                 else {
1168                                         arg->opcode = OP_OUTARG_VT;
1169                                         arg->klass = in->klass;
1170                                         arg->unused = sig->pinvoke;
1171                                         arg->inst_imm = size;
1172                                 }
1173                         }
1174                         else {
1175                                 switch (ainfo->storage) {
1176                                 case ArgInIReg:
1177                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1178                                         break;
1179                                 case ArgInFloatSSEReg:
1180                                 case ArgInDoubleSSEReg:
1181                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1182                                         break;
1183                                 case ArgOnStack:
1184                                         arg->opcode = OP_OUTARG;
1185                                         if (!sig->params [i - sig->hasthis]->byref) {
1186                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1187                                                         arg->opcode = OP_OUTARG_R4;
1188                                                 else
1189                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1190                                                                 arg->opcode = OP_OUTARG_R8;
1191                                         }
1192                                         break;
1193                                 default:
1194                                         g_assert_not_reached ();
1195                                 }
1196                         }
1197                 }
1198         }
1199
1200         if (cinfo->need_stack_align) {
1201                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1202                 /* prepend, so they get reversed */
1203                 arg->next = call->out_args;
1204                 call->out_args = arg;
1205         }
1206
1207         call->stack_usage = cinfo->stack_usage;
1208         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1209         cfg->flags |= MONO_CFG_HAS_CALLS;
1210
1211         g_free (cinfo);
1212
1213         return call;
1214 }
1215
1216 #define EMIT_COND_BRANCH(ins,cond,sign) \
1217 if (ins->flags & MONO_INST_BRLABEL) { \
1218         if (ins->inst_i0->inst_c0) { \
1219                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1220         } else { \
1221                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1222                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1223                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1224                         x86_branch8 (code, cond, 0, sign); \
1225                 else \
1226                         x86_branch32 (code, cond, 0, sign); \
1227         } \
1228 } else { \
1229         if (ins->inst_true_bb->native_offset) { \
1230                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1231         } else { \
1232                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1233                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1234                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1235                         x86_branch8 (code, cond, 0, sign); \
1236                 else \
1237                         x86_branch32 (code, cond, 0, sign); \
1238         } \
1239 }
1240
1241 /* emit an exception if condition is fail */
1242 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1243         do {                                                        \
1244                 mono_add_patch_info (cfg, code - cfg->native_code,   \
1245                                     MONO_PATCH_INFO_EXC, exc_name);  \
1246                 x86_branch32 (code, cond, 0, signed);               \
1247         } while (0);
1248
1249 #define EMIT_FPCOMPARE(code) do { \
1250         amd64_fcompp (code); \
1251         amd64_fnstsw (code); \
1252 } while (0);
1253
1254 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1255     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1256         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1257         amd64_ ##op (code); \
1258         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1259         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1260 } while (0);
1261
1262 static guint8*
1263 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1264 {
1265         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1266
1267         if (mono_compile_aot) {
1268                 amd64_call_membase (code, AMD64_RIP, 0);
1269         }
1270         else {
1271                 gboolean near_call = FALSE;
1272
1273                 /*
1274                  * Indirect calls are expensive so try to make a near call if possible.
1275                  * The caller memory is allocated by the code manager so it is
1276                  * guaranteed to be at a 32 bit offset.
1277                  */
1278
1279                 if (patch_type != MONO_PATCH_INFO_ABS) {
1280                         /* The target is in memory allocated using the code manager */
1281                         near_call = TRUE;
1282
1283                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1284                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1285                                         /* The callee might be an AOT method */
1286                                         near_call = FALSE;
1287                         }
1288                 }
1289                 else {
1290                         if (mono_find_class_init_trampoline_by_addr (data))
1291                                 near_call = TRUE;
1292                         else {
1293                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1294                                 if (info) {
1295                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1296                                                 strstr (cfg->method->name, info->name)) {
1297                                                 /* A call to the wrapped function */
1298                                                 if ((((guint64)data) >> 32) == 0)
1299                                                         near_call = TRUE;
1300                                         }
1301                                         else
1302                                                 near_call = TRUE;
1303                                 }
1304                                 else if ((((guint64)data) >> 32) == 0)
1305                                         near_call = TRUE;
1306                         }
1307                 }
1308
1309                 if (near_call) {
1310                         amd64_call_code (code, 0);
1311                 }
1312                 else {
1313                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1314                         amd64_call_reg (code, GP_SCRATCH_REG);
1315                 }
1316         }
1317
1318         return code;
1319 }
1320
1321 /* FIXME: Add more instructions */
1322 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) || ((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_SETREG) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
1323
1324 static void
1325 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1326 {
1327         MonoInst *ins, *last_ins = NULL;
1328         ins = bb->code;
1329
1330         while (ins) {
1331
1332                 switch (ins->opcode) {
1333                 case OP_ICONST:
1334                 case OP_I8CONST:
1335                         /* reg = 0 -> XOR (reg, reg) */
1336                         /* XOR sets cflags on x86, so we cant do it always */
1337                         if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next))) {
1338                                 ins->opcode = CEE_XOR;
1339                                 ins->sreg1 = ins->dreg;
1340                                 ins->sreg2 = ins->dreg;
1341                         }
1342                         break;
1343                 case OP_MUL_IMM:
1344                         /* remove unnecessary multiplication with 1 */
1345                         if (ins->inst_imm == 1) {
1346                                 if (ins->dreg != ins->sreg1) {
1347                                         ins->opcode = OP_MOVE;
1348                                 } else {
1349                                         last_ins->next = ins->next;
1350                                         ins = ins->next;
1351                                         continue;
1352                                 }
1353                         }
1354                         break;
1355                 case OP_COMPARE_IMM:
1356                         /* OP_COMPARE_IMM (reg, 0)
1357                          * -->
1358                          * OP_AMD64_TEST_NULL (reg)
1359                          */
1360                         if (!ins->inst_imm)
1361                                 ins->opcode = OP_AMD64_TEST_NULL;
1362                         break;
1363                 case OP_ICOMPARE_IMM:
1364                         if (!ins->inst_imm)
1365                                 ins->opcode = OP_X86_TEST_NULL;
1366                         break;
1367                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1368                         /*
1369                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1370                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1371                          * -->
1372                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1373                          * OP_COMPARE_IMM reg, imm
1374                          *
1375                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1376                          */
1377                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1378                             ins->inst_basereg == last_ins->inst_destbasereg &&
1379                             ins->inst_offset == last_ins->inst_offset) {
1380                                         ins->opcode = OP_ICOMPARE_IMM;
1381                                         ins->sreg1 = last_ins->sreg1;
1382
1383                                         /* check if we can remove cmp reg,0 with test null */
1384                                         if (!ins->inst_imm)
1385                                                 ins->opcode = OP_X86_TEST_NULL;
1386                                 }
1387
1388                         break;
1389                 case OP_LOAD_MEMBASE:
1390                 case OP_LOADI4_MEMBASE:
1391                         /*
1392                          * Note: if reg1 = reg2 the load op is removed
1393                          *
1394                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1395                          * OP_LOAD_MEMBASE offset(basereg), reg2
1396                          * -->
1397                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1398                          * OP_MOVE reg1, reg2
1399                          */
1400                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1401                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1402                             ins->inst_basereg == last_ins->inst_destbasereg &&
1403                             ins->inst_offset == last_ins->inst_offset) {
1404                                 if (ins->dreg == last_ins->sreg1) {
1405                                         last_ins->next = ins->next;
1406                                         ins = ins->next;
1407                                         continue;
1408                                 } else {
1409                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1410                                         ins->opcode = OP_MOVE;
1411                                         ins->sreg1 = last_ins->sreg1;
1412                                 }
1413
1414                         /*
1415                          * Note: reg1 must be different from the basereg in the second load
1416                          * Note: if reg1 = reg2 is equal then second load is removed
1417                          *
1418                          * OP_LOAD_MEMBASE offset(basereg), reg1
1419                          * OP_LOAD_MEMBASE offset(basereg), reg2
1420                          * -->
1421                          * OP_LOAD_MEMBASE offset(basereg), reg1
1422                          * OP_MOVE reg1, reg2
1423                          */
1424                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1425                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1426                               ins->inst_basereg != last_ins->dreg &&
1427                               ins->inst_basereg == last_ins->inst_basereg &&
1428                               ins->inst_offset == last_ins->inst_offset) {
1429
1430                                 if (ins->dreg == last_ins->dreg) {
1431                                         last_ins->next = ins->next;
1432                                         ins = ins->next;
1433                                         continue;
1434                                 } else {
1435                                         ins->opcode = OP_MOVE;
1436                                         ins->sreg1 = last_ins->dreg;
1437                                 }
1438
1439                                 //g_assert_not_reached ();
1440
1441 #if 0
1442                         /*
1443                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1444                          * OP_LOAD_MEMBASE offset(basereg), reg
1445                          * -->
1446                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1447                          * OP_ICONST reg, imm
1448                          */
1449                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1450                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1451                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1452                                    ins->inst_offset == last_ins->inst_offset) {
1453                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1454                                 ins->opcode = OP_ICONST;
1455                                 ins->inst_c0 = last_ins->inst_imm;
1456                                 g_assert_not_reached (); // check this rule
1457 #endif
1458                         }
1459                         break;
1460                 case OP_LOADU1_MEMBASE:
1461                 case OP_LOADI1_MEMBASE:
1462                         /*
1463                          * Note: if reg1 = reg2 the load op is removed
1464                          *
1465                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1466                          * OP_LOAD_MEMBASE offset(basereg), reg2
1467                          * -->
1468                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1469                          * OP_MOVE reg1, reg2
1470                          */
1471                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1472                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1473                                         ins->inst_offset == last_ins->inst_offset) {
1474                                 if (ins->dreg == last_ins->sreg1) {
1475                                         last_ins->next = ins->next;
1476                                         ins = ins->next;
1477                                         continue;
1478                                 } else {
1479                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1480                                         ins->opcode = OP_MOVE;
1481                                         ins->sreg1 = last_ins->sreg1;
1482                                 }
1483                         }
1484                         break;
1485                 case OP_LOADU2_MEMBASE:
1486                 case OP_LOADI2_MEMBASE:
1487                         /*
1488                          * Note: if reg1 = reg2 the load op is removed
1489                          *
1490                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1491                          * OP_LOAD_MEMBASE offset(basereg), reg2
1492                          * -->
1493                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1494                          * OP_MOVE reg1, reg2
1495                          */
1496                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1497                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1498                                         ins->inst_offset == last_ins->inst_offset) {
1499                                 if (ins->dreg == last_ins->sreg1) {
1500                                         last_ins->next = ins->next;
1501                                         ins = ins->next;
1502                                         continue;
1503                                 } else {
1504                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1505                                         ins->opcode = OP_MOVE;
1506                                         ins->sreg1 = last_ins->sreg1;
1507                                 }
1508                         }
1509                         break;
1510                 case CEE_CONV_I4:
1511                 case CEE_CONV_U4:
1512                 case OP_MOVE:
1513                         /*
1514                          * Removes:
1515                          *
1516                          * OP_MOVE reg, reg
1517                          */
1518                         if (ins->dreg == ins->sreg1) {
1519                                 if (last_ins)
1520                                         last_ins->next = ins->next;
1521                                 ins = ins->next;
1522                                 continue;
1523                         }
1524                         /*
1525                          * Removes:
1526                          *
1527                          * OP_MOVE sreg, dreg
1528                          * OP_MOVE dreg, sreg
1529                          */
1530                         if (last_ins && last_ins->opcode == OP_MOVE &&
1531                             ins->sreg1 == last_ins->dreg &&
1532                             ins->dreg == last_ins->sreg1) {
1533                                 last_ins->next = ins->next;
1534                                 ins = ins->next;
1535                                 continue;
1536                         }
1537                         break;
1538                 }
1539                 last_ins = ins;
1540                 ins = ins->next;
1541         }
1542         bb->last_ins = last_ins;
1543 }
1544
1545 static const int
1546 branch_cc_table [] = {
1547         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1548         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1549         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1550 };
1551
1552 static int
1553 opcode_to_x86_cond (int opcode)
1554 {
1555         switch (opcode) {
1556         case OP_IBEQ:
1557                 return X86_CC_EQ;
1558         case OP_IBNE_UN:
1559                 return X86_CC_NE;
1560         case OP_IBLT:
1561                 return X86_CC_LT;
1562         case OP_IBLT_UN:
1563                 return X86_CC_LT;
1564         case OP_IBGT:
1565                 return X86_CC_GT;
1566         case OP_IBGT_UN:
1567                 return X86_CC_GT;
1568         case OP_IBGE:
1569                 return X86_CC_GE;
1570         case OP_IBGE_UN:
1571                 return X86_CC_GE;
1572         case OP_IBLE:
1573                 return X86_CC_LE;
1574         case OP_IBLE_UN:
1575                 return X86_CC_LE;
1576         case OP_COND_EXC_IOV:
1577                 return X86_CC_O;
1578         case OP_COND_EXC_IC:
1579                 return X86_CC_C;
1580         default:
1581                 g_assert_not_reached ();
1582         }
1583
1584         return -1;
1585 }
1586
1587 /*
1588  * returns the offset used by spillvar. It allocates a new
1589  * spill variable if necessary.
1590  */
1591 static int
1592 mono_spillvar_offset (MonoCompile *cfg, int spillvar)
1593 {
1594         MonoSpillInfo **si, *info;
1595         int i = 0;
1596
1597         si = &cfg->spill_info;
1598
1599         while (i <= spillvar) {
1600
1601                 if (!*si) {
1602                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1603                         info->next = NULL;
1604                         cfg->stack_offset += sizeof (gpointer);
1605                         info->offset = - cfg->stack_offset;
1606                 }
1607
1608                 if (i == spillvar)
1609                         return (*si)->offset;
1610
1611                 i++;
1612                 si = &(*si)->next;
1613         }
1614
1615         g_assert_not_reached ();
1616         return 0;
1617 }
1618
1619 /*
1620  * returns the offset used by spillvar. It allocates a new
1621  * spill float variable if necessary.
1622  * (same as mono_spillvar_offset but for float)
1623  */
1624 static int
1625 mono_spillvar_offset_float (MonoCompile *cfg, int spillvar)
1626 {
1627         MonoSpillInfo **si, *info;
1628         int i = 0;
1629
1630         si = &cfg->spill_info_float;
1631
1632         while (i <= spillvar) {
1633
1634                 if (!*si) {
1635                         *si = info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo));
1636                         info->next = NULL;
1637                         cfg->stack_offset += sizeof (double);
1638                         info->offset = - cfg->stack_offset;
1639                 }
1640
1641                 if (i == spillvar)
1642                         return (*si)->offset;
1643
1644                 i++;
1645                 si = &(*si)->next;
1646         }
1647
1648         g_assert_not_reached ();
1649         return 0;
1650 }
1651
1652 /*
1653  * Creates a store for spilled floating point items
1654  */
1655 static MonoInst*
1656 create_spilled_store_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1657 {
1658         MonoInst *store;
1659         MONO_INST_NEW (cfg, store, OP_STORER8_MEMBASE_REG);
1660         store->sreg1 = reg;
1661         store->inst_destbasereg = AMD64_RBP;
1662         store->inst_offset = mono_spillvar_offset_float (cfg, spill);
1663
1664         DEBUG (g_print ("SPILLED FLOAT STORE (%d at 0x%08lx(%%sp)) (from %d)\n", spill, (long)store->inst_offset, reg));
1665         return store;
1666 }
1667
1668 /*
1669  * Creates a load for spilled floating point items
1670  */
1671 static MonoInst*
1672 create_spilled_load_float (MonoCompile *cfg, int spill, int reg, MonoInst *ins)
1673 {
1674         MonoInst *load;
1675         MONO_INST_NEW (cfg, load, OP_LOADR8_SPILL_MEMBASE);
1676         load->dreg = reg;
1677         load->inst_basereg = AMD64_RBP;
1678         load->inst_offset = mono_spillvar_offset_float (cfg, spill);
1679
1680         DEBUG (g_print ("SPILLED FLOAT LOAD (%d at 0x%08lx(%%sp)) (from %d)\n", spill, (long)load->inst_offset, reg));
1681         return load;
1682 }
1683
1684 #define is_global_ireg(r) ((r) >= 0 && (r) <= 15 && AMD64_IS_CALLEE_SAVED_REG ((r)))
1685 #define ireg_is_freeable(r) ((r) >= 0 && (r) <= 15 && AMD64_IS_CALLEE_REG ((r)))
1686 #define freg_is_freeable(r) ((r) >= 0 && (r) <= AMD64_XMM_NREG)
1687
1688 #define reg_is_freeable(r,fp) ((fp) ? freg_is_freeable ((r)) : ireg_is_freeable ((r)))
1689 #define reg_is_hard(r,fp) ((fp) ? ((r) < MONO_MAX_FREGS) : ((r) < MONO_MAX_IREGS))
1690 #define reg_is_soft(r,fp) (!reg_is_hard((r),(fp)))
1691 #define rassign(cfg,reg,fp) ((fp) ? (cfg)->rs->fassign [(reg)] : (cfg)->rs->iassign [(reg)])
1692 #define sreg1_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_SRC1] == 'f')
1693 #define sreg2_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_SRC2] == 'f')
1694 #define dreg_is_fp(ins)  (ins_spec [(ins)->opcode] [MONO_INST_DEST] == 'f')
1695
1696 typedef struct {
1697         int born_in;
1698         int killed_in;
1699         int last_use;
1700         int prev_use;
1701         int flags;              /* used to track fp spill/load */
1702 } RegTrack;
1703
1704 static const char*const * ins_spec = amd64_desc;
1705
1706 static void
1707 print_ins (int i, MonoInst *ins)
1708 {
1709         const char *spec = ins_spec [ins->opcode];
1710         g_print ("\t%-2d %s", i, mono_inst_name (ins->opcode));
1711         if (!spec)
1712                 g_error ("Unknown opcode: %s\n", mono_inst_name (ins->opcode));
1713         if (spec [MONO_INST_DEST]) {
1714                 gboolean fp = (spec [MONO_INST_DEST] == 'f');
1715                 if (reg_is_soft (ins->dreg, fp))
1716                         g_print (" R%d <-", ins->dreg);
1717                 else
1718                         g_print (" %s <-", mono_amd64_regname (ins->dreg, fp));
1719         }
1720         if (spec [MONO_INST_SRC1]) {
1721                 gboolean fp = (spec [MONO_INST_SRC1] == 'f');
1722                 if (reg_is_soft (ins->sreg1, fp))
1723                         g_print (" R%d", ins->sreg1);
1724                 else
1725                         g_print (" %s", mono_amd64_regname (ins->sreg1, fp));
1726         }
1727         if (spec [MONO_INST_SRC2]) {
1728                 gboolean fp = (spec [MONO_INST_SRC2] == 'f');
1729                 if (reg_is_soft (ins->sreg2, fp))
1730                         g_print (" R%d", ins->sreg2);
1731                 else
1732                         g_print (" %s", mono_amd64_regname (ins->sreg2, fp));
1733         }
1734         if (spec [MONO_INST_CLOB])
1735                 g_print (" clobbers: %c", spec [MONO_INST_CLOB]);
1736         g_print ("\n");
1737 }
1738
1739 static void
1740 print_regtrack (RegTrack *t, int num)
1741 {
1742         int i;
1743         char buf [32];
1744         const char *r;
1745
1746         for (i = 0; i < num; ++i) {
1747                 if (!t [i].born_in)
1748                         continue;
1749                 if (i >= MONO_MAX_IREGS) {
1750                         g_snprintf (buf, sizeof(buf), "R%d", i);
1751                         r = buf;
1752                 } else
1753                         r = mono_arch_regname (i);
1754                 g_print ("liveness: %s [%d - %d]\n", r, t [i].born_in, t[i].last_use);
1755         }
1756 }
1757
1758 typedef struct InstList InstList;
1759
1760 struct InstList {
1761         InstList *prev;
1762         InstList *next;
1763         MonoInst *data;
1764 };
1765
1766 static inline InstList*
1767 inst_list_prepend (MonoMemPool *pool, InstList *list, MonoInst *data)
1768 {
1769         InstList *item = mono_mempool_alloc (pool, sizeof (InstList));
1770         item->data = data;
1771         item->prev = NULL;
1772         item->next = list;
1773         if (list)
1774                 list->prev = item;
1775         return item;
1776 }
1777
1778 /*
1779  * Force the spilling of the variable in the symbolic register 'reg'.
1780  */
1781 static int
1782 get_register_force_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, int reg, gboolean fp)
1783 {
1784         MonoInst *load;
1785         int i, sel, spill;
1786         int *assign, *symbolic;
1787
1788         if (fp) {
1789                 assign = cfg->rs->fassign;
1790                 symbolic = cfg->rs->fsymbolic;
1791         }
1792         else {
1793                 assign = cfg->rs->iassign;
1794                 symbolic = cfg->rs->isymbolic;
1795         }
1796
1797         sel = assign [reg];
1798         /*i = cfg->rs->isymbolic [sel];
1799         g_assert (i == reg);*/
1800         i = reg;
1801         spill = ++cfg->spill_count;
1802         assign [i] = -spill - 1;
1803         if (fp)
1804                 mono_regstate_free_float (cfg->rs, sel);
1805         else
1806                 mono_regstate_free_int (cfg->rs, sel);
1807         /* we need to create a spill var and insert a load to sel after the current instruction */
1808         if (fp)
1809                 MONO_INST_NEW (cfg, load, OP_LOADR8_MEMBASE);
1810         else
1811                 MONO_INST_NEW (cfg, load, OP_LOAD_MEMBASE);
1812         load->dreg = sel;
1813         load->inst_basereg = AMD64_RBP;
1814         load->inst_offset = mono_spillvar_offset (cfg, spill);
1815         if (item->prev) {
1816                 while (ins->next != item->prev->data)
1817                         ins = ins->next;
1818         }
1819         load->next = ins->next;
1820         ins->next = load;
1821         DEBUG (g_print ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_amd64_regname (sel, fp)));
1822         if (fp)
1823                 i = mono_regstate_alloc_float (cfg->rs, 1 << sel);
1824         else
1825                 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1826         g_assert (i == sel);
1827
1828         return sel;
1829 }
1830
1831 static int
1832 get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins, guint32 regmask, int reg, gboolean fp)
1833 {
1834         MonoInst *load;
1835         int i, sel, spill;
1836         int *assign, *symbolic;
1837
1838         if (fp) {
1839                 assign = cfg->rs->fassign;
1840                 symbolic = cfg->rs->fsymbolic;
1841         }
1842         else {
1843                 assign = cfg->rs->iassign;
1844                 symbolic = cfg->rs->isymbolic;
1845         }
1846
1847         DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08x (R%d <- R%d R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
1848         /* exclude the registers in the current instruction */
1849         if ((sreg1_is_fp (ins) == fp) && (reg != ins->sreg1) && (reg_is_freeable (ins->sreg1, fp) || (reg_is_soft (ins->sreg1, fp) && rassign (cfg, ins->sreg1, fp) >= 0))) {
1850                 if (reg_is_soft (ins->sreg1, fp))
1851                         regmask &= ~ (1 << rassign (cfg, ins->sreg1, fp));
1852                 else
1853                         regmask &= ~ (1 << ins->sreg1);
1854                 DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_amd64_regname (ins->sreg1, fp)));
1855         }
1856         if ((sreg2_is_fp (ins) == fp) && (reg != ins->sreg2) && (reg_is_freeable (ins->sreg2, fp) || (reg_is_soft (ins->sreg2, fp) && rassign (cfg, ins->sreg2, fp) >= 0))) {
1857                 if (reg_is_soft (ins->sreg2, fp))
1858                         regmask &= ~ (1 << rassign (cfg, ins->sreg2, fp));
1859                 else
1860                         regmask &= ~ (1 << ins->sreg2);
1861                 DEBUG (g_print ("\t\texcluding sreg2 %s %d\n", mono_amd64_regname (ins->sreg2, fp), ins->sreg2));
1862         }
1863         if ((dreg_is_fp (ins) == fp) && (reg != ins->dreg) && reg_is_freeable (ins->dreg, fp)) {
1864                 regmask &= ~ (1 << ins->dreg);
1865                 DEBUG (g_print ("\t\texcluding dreg %s\n", mono_amd64_regname (ins->dreg, fp)));
1866         }
1867
1868         DEBUG (g_print ("\t\tavailable regmask: 0x%08x\n", regmask));
1869         g_assert (regmask); /* need at least a register we can free */
1870         sel = -1;
1871         /* we should track prev_use and spill the register that's farther */
1872         if (fp) {
1873                 for (i = 0; i < MONO_MAX_FREGS; ++i) {
1874                         if (regmask & (1 << i)) {
1875                                 sel = i;
1876                                 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_fregname (sel), cfg->rs->fassign [sel]));
1877                                 break;
1878                         }
1879                 }
1880
1881                 i = cfg->rs->fsymbolic [sel];
1882                 spill = ++cfg->spill_count;
1883                 cfg->rs->fassign [i] = -spill - 1;
1884                 mono_regstate_free_float (cfg->rs, sel);
1885         }
1886         else {
1887                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
1888                         if (regmask & (1 << i)) {
1889                                 sel = i;
1890                                 DEBUG (g_print ("\t\tselected register %s has assignment %d\n", mono_arch_regname (sel), cfg->rs->iassign [sel]));
1891                                 break;
1892                         }
1893                 }
1894
1895                 i = cfg->rs->isymbolic [sel];
1896                 spill = ++cfg->spill_count;
1897                 cfg->rs->iassign [i] = -spill - 1;
1898                 mono_regstate_free_int (cfg->rs, sel);
1899         }
1900
1901         /* we need to create a spill var and insert a load to sel after the current instruction */
1902         MONO_INST_NEW (cfg, load, fp ? OP_LOADR8_MEMBASE : OP_LOAD_MEMBASE);
1903         load->dreg = sel;
1904         load->inst_basereg = AMD64_RBP;
1905         load->inst_offset = mono_spillvar_offset (cfg, spill);
1906         if (item->prev) {
1907                 while (ins->next != item->prev->data)
1908                         ins = ins->next;
1909         }
1910         load->next = ins->next;
1911         ins->next = load;
1912         DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_amd64_regname (sel, fp)));
1913         if (fp)
1914                 i = mono_regstate_alloc_float (cfg->rs, 1 << sel);
1915         else
1916                 i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
1917         g_assert (i == sel);
1918
1919         return sel;
1920 }
1921
1922 static MonoInst*
1923 create_copy_ins (MonoCompile *cfg, int dest, int src, MonoInst *ins, gboolean fp)
1924 {
1925         MonoInst *copy;
1926
1927         if (fp)
1928                 MONO_INST_NEW (cfg, copy, OP_FMOVE);
1929         else
1930                 MONO_INST_NEW (cfg, copy, OP_MOVE);
1931
1932         copy->dreg = dest;
1933         copy->sreg1 = src;
1934         if (ins) {
1935                 copy->next = ins->next;
1936                 ins->next = copy;
1937         }
1938         DEBUG (g_print ("\tforced copy from %s to %s\n", mono_arch_regname (src), mono_arch_regname (dest)));
1939         return copy;
1940 }
1941
1942 static MonoInst*
1943 create_spilled_store (MonoCompile *cfg, int spill, int reg, int prev_reg, MonoInst *ins, gboolean fp)
1944 {
1945         MonoInst *store;
1946         MONO_INST_NEW (cfg, store, fp ? OP_STORER8_MEMBASE_REG : OP_STORE_MEMBASE_REG);
1947         store->sreg1 = reg;
1948         store->inst_destbasereg = AMD64_RBP;
1949         store->inst_offset = mono_spillvar_offset (cfg, spill);
1950         if (ins) {
1951                 store->next = ins->next;
1952                 ins->next = store;
1953         }
1954         DEBUG (g_print ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_amd64_regname (reg, fp)));
1955         return store;
1956 }
1957
1958 static void
1959 insert_before_ins (MonoInst *ins, InstList *item, MonoInst* to_insert)
1960 {
1961         MonoInst *prev;
1962         if (item->next) {
1963                 prev = item->next->data;
1964
1965                 while (prev->next != ins)
1966                         prev = prev->next;
1967                 to_insert->next = ins;
1968                 prev->next = to_insert;
1969         } else {
1970                 to_insert->next = ins;
1971         }
1972         /*
1973          * needed otherwise in the next instruction we can add an ins to the
1974          * end and that would get past this instruction.
1975          */
1976         item->data = to_insert;
1977 }
1978
1979 /* flags used in reginfo->flags */
1980 enum {
1981         MONO_X86_FP_NEEDS_LOAD_SPILL    = 1 << 0,
1982         MONO_X86_FP_NEEDS_SPILL                 = 1 << 1,
1983         MONO_X86_FP_NEEDS_LOAD                  = 1 << 2,
1984         MONO_X86_REG_NOT_ECX                    = 1 << 3,
1985         MONO_X86_REG_EAX                                = 1 << 4,
1986         MONO_X86_REG_EDX                                = 1 << 5,
1987         MONO_X86_REG_ECX                                = 1 << 6
1988 };
1989
1990 static int
1991 mono_amd64_alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg, int flags)
1992 {
1993         int val;
1994         int test_mask = dest_mask;
1995
1996         if (flags & MONO_X86_REG_EAX)
1997                 test_mask &= (1 << AMD64_RAX);
1998         else if (flags & MONO_X86_REG_EDX)
1999                 test_mask &= (1 << AMD64_RDX);
2000         else if (flags & MONO_X86_REG_ECX)
2001                 test_mask &= (1 << AMD64_RCX);
2002         else if (flags & MONO_X86_REG_NOT_ECX)
2003                 test_mask &= ~ (1 << AMD64_RCX);
2004
2005         val = mono_regstate_alloc_int (cfg->rs, test_mask);
2006         if (val >= 0 && test_mask != dest_mask)
2007                 DEBUG(g_print ("\tUsed flag to allocate reg %s for R%u\n", mono_arch_regname (val), sym_reg));
2008
2009         if (val < 0 && (flags & MONO_X86_REG_NOT_ECX)) {
2010                 DEBUG(g_print ("\tFailed to allocate flag suggested mask (%u) but exluding ECX\n", test_mask));
2011                 val = mono_regstate_alloc_int (cfg->rs, (dest_mask & (~1 << AMD64_RCX)));
2012         }
2013
2014         if (val < 0) {
2015                 val = mono_regstate_alloc_int (cfg->rs, dest_mask);
2016                 if (val < 0)
2017                         val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg, FALSE);
2018         }
2019
2020         return val;
2021 }
2022
2023 static int
2024 mono_amd64_alloc_float_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask, int sym_reg)
2025 {
2026         int val;
2027
2028         val = mono_regstate_alloc_float (cfg->rs, dest_mask);
2029
2030         if (val < 0) {
2031                 val = get_register_spilling (cfg, tmp, ins, dest_mask, sym_reg, TRUE);
2032         }
2033
2034         return val;
2035 }
2036
2037 static inline void
2038 assign_ireg (MonoRegState *rs, int reg, int hreg)
2039 {
2040         g_assert (reg >= MONO_MAX_IREGS);
2041         g_assert (hreg < MONO_MAX_IREGS);
2042         g_assert (! is_global_ireg (hreg));
2043
2044         rs->iassign [reg] = hreg;
2045         rs->isymbolic [hreg] = reg;
2046         rs->ifree_mask &= ~ (1 << hreg);
2047 }
2048
2049 /*#include "cprop.c"*/
2050
2051 /*
2052  * Local register allocation.
2053  * We first scan the list of instructions and we save the liveness info of
2054  * each register (when the register is first used, when it's value is set etc.).
2055  * We also reverse the list of instructions (in the InstList list) because assigning
2056  * registers backwards allows for more tricks to be used.
2057  */
2058 void
2059 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
2060 {
2061         MonoInst *ins;
2062         MonoRegState *rs = cfg->rs;
2063         int i, val, fpcount;
2064         RegTrack *reginfo, *reginfof;
2065         RegTrack *reginfo1, *reginfo2, *reginfod;
2066         InstList *tmp, *reversed = NULL;
2067         const char *spec;
2068         guint32 src1_mask, src2_mask, dest_mask;
2069         GList *fspill_list = NULL;
2070         int fspill = 0;
2071
2072         if (!bb->code)
2073                 return;
2074         rs->next_vireg = bb->max_ireg;
2075         rs->next_vfreg = bb->max_freg;
2076         mono_regstate_assign (rs);
2077         reginfo = g_malloc0 (sizeof (RegTrack) * rs->next_vireg);
2078         reginfof = g_malloc0 (sizeof (RegTrack) * rs->next_vfreg);
2079         rs->ifree_mask = AMD64_CALLEE_REGS;
2080         rs->ffree_mask = AMD64_CALLEE_FREGS;
2081
2082         if (!use_sse2)
2083                 /* The fp stack is 6 entries deep */
2084                 rs->ffree_mask = 0x3f;
2085
2086         ins = bb->code;
2087
2088         /*if (cfg->opt & MONO_OPT_COPYPROP)
2089                 local_copy_prop (cfg, ins);*/
2090
2091         i = 1;
2092         fpcount = 0;
2093         DEBUG (g_print ("LOCAL regalloc: basic block: %d\n", bb->block_num));
2094         /* forward pass on the instructions to collect register liveness info */
2095         while (ins) {
2096                 spec = ins_spec [ins->opcode];
2097
2098                 DEBUG (print_ins (i, ins));
2099
2100                 if (spec [MONO_INST_SRC1]) {
2101                         if (spec [MONO_INST_SRC1] == 'f') {
2102                                 reginfo1 = reginfof;
2103
2104                                 if (!use_sse2) {
2105                                         GList *spill;
2106
2107                                         spill = g_list_first (fspill_list);
2108                                         if (spill && fpcount < FPSTACK_SIZE) {
2109                                                 reginfo1 [ins->sreg1].flags |= MONO_X86_FP_NEEDS_LOAD;
2110                                                 fspill_list = g_list_remove (fspill_list, spill->data);
2111                                         } else
2112                                                 fpcount--;
2113                                 }
2114                         }
2115                         else
2116                                 reginfo1 = reginfo;
2117                         reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
2118                         reginfo1 [ins->sreg1].last_use = i;
2119                         if (spec [MONO_INST_SRC1] == 'L') {
2120                                 /* The virtual register is allocated sequentially */
2121                                 reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
2122                                 reginfo1 [ins->sreg1 + 1].last_use = i;
2123                                 if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
2124                                         reginfo1 [ins->sreg1 + 1].born_in = i;
2125
2126                                 reginfo1 [ins->sreg1].flags |= MONO_X86_REG_EAX;
2127                                 reginfo1 [ins->sreg1 + 1].flags |= MONO_X86_REG_EDX;
2128                         }
2129                 } else {
2130                         ins->sreg1 = -1;
2131                 }
2132                 if (spec [MONO_INST_SRC2]) {
2133                         if (spec [MONO_INST_SRC2] == 'f') {
2134                                 reginfo2 = reginfof;
2135
2136                                 if (!use_sse2) {
2137                                         GList *spill;
2138
2139                                         spill = g_list_first (fspill_list);
2140                                         if (spill) {
2141                                                 reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD;
2142                                                 fspill_list = g_list_remove (fspill_list, spill->data);
2143                                                 if (fpcount >= FPSTACK_SIZE) {
2144                                                         fspill++;
2145                                                         fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
2146                                                         reginfo2 [ins->sreg2].flags |= MONO_X86_FP_NEEDS_LOAD_SPILL;
2147                                                 }
2148                                         } else
2149                                                 fpcount--;
2150                                 }
2151                         }
2152                         else
2153                                 reginfo2 = reginfo;
2154                         reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
2155                         reginfo2 [ins->sreg2].last_use = i;
2156                         if (spec [MONO_INST_SRC2] == 'L') {
2157                                 /* The virtual register is allocated sequentially */
2158                                 reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
2159                                 reginfo2 [ins->sreg2 + 1].last_use = i;
2160                                 if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
2161                                         reginfo2 [ins->sreg2 + 1].born_in = i;
2162                         }
2163                         if (spec [MONO_INST_CLOB] == 's') {
2164                                 reginfo2 [ins->sreg1].flags |= MONO_X86_REG_NOT_ECX;
2165                                 reginfo2 [ins->sreg2].flags |= MONO_X86_REG_ECX;
2166                         }
2167                 } else {
2168                         ins->sreg2 = -1;
2169                 }
2170                 if (spec [MONO_INST_DEST]) {
2171                         if (spec [MONO_INST_DEST] == 'f') {
2172                                 reginfod = reginfof;
2173                                 if (!use_sse2 && (spec [MONO_INST_CLOB] != 'm')) {
2174                                         if (fpcount >= FPSTACK_SIZE) {
2175                                                 reginfod [ins->dreg].flags |= MONO_X86_FP_NEEDS_SPILL;
2176                                                 fspill++;
2177                                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
2178                                                 fpcount--;
2179                                         }
2180                                         fpcount++;
2181                                 }
2182                         }
2183                         else
2184                                 reginfod = reginfo;
2185                         if (spec [MONO_INST_DEST] != 'b') /* it's not just a base register */
2186                                 reginfod [ins->dreg].killed_in = i;
2187                         reginfod [ins->dreg].prev_use = reginfod [ins->dreg].last_use;
2188                         reginfod [ins->dreg].last_use = i;
2189                         if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
2190                                 reginfod [ins->dreg].born_in = i;
2191                         if (spec [MONO_INST_DEST] == 'l' || spec [MONO_INST_DEST] == 'L') {
2192                                 /* The virtual register is allocated sequentially */
2193                                 reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
2194                                 reginfod [ins->dreg + 1].last_use = i;
2195                                 if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
2196                                         reginfod [ins->dreg + 1].born_in = i;
2197
2198                                 reginfod [ins->dreg].flags |= MONO_X86_REG_EAX;
2199                                 reginfod [ins->dreg + 1].flags |= MONO_X86_REG_EDX;
2200                         }
2201                 } else {
2202                         ins->dreg = -1;
2203                 }
2204
2205                 if (spec [MONO_INST_CLOB] == 'c') {
2206                         /* A call instruction implicitly uses all registers in call->out_ireg_args */
2207
2208                         MonoCallInst *call = (MonoCallInst*)ins;
2209                         GSList *list;
2210
2211                         list = call->out_ireg_args;
2212                         if (list) {
2213                                 while (list) {
2214                                         guint64 regpair;
2215                                         int reg, hreg;
2216
2217                                         regpair = (guint64) (list->data);
2218                                         hreg = regpair >> 32;
2219                                         reg = regpair & 0xffffffff;
2220
2221                                         reginfo [reg].prev_use = reginfo [reg].last_use;
2222                                         reginfo [reg].last_use = i;
2223
2224                                         list = g_slist_next (list);
2225                                 }
2226                         }
2227
2228                         list = call->out_freg_args;
2229                         if (use_sse2 && list) {
2230                                 while (list) {
2231                                         guint64 regpair;
2232                                         int reg, hreg;
2233
2234                                         regpair = (guint64) (list->data);
2235                                         hreg = regpair >> 32;
2236                                         reg = regpair & 0xffffffff;
2237
2238                                         reginfof [reg].prev_use = reginfof [reg].last_use;
2239                                         reginfof [reg].last_use = i;
2240
2241                                         list = g_slist_next (list);
2242                                 }
2243                         }
2244                 }
2245
2246                 reversed = inst_list_prepend (cfg->mempool, reversed, ins);
2247                 ++i;
2248                 ins = ins->next;
2249         }
2250
2251         // todo: check if we have anything left on fp stack, in verify mode?
2252         fspill = 0;
2253
2254         DEBUG (print_regtrack (reginfo, rs->next_vireg));
2255         DEBUG (print_regtrack (reginfof, rs->next_vfreg));
2256         tmp = reversed;
2257         while (tmp) {
2258                 int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
2259                 dest_mask = src1_mask = src2_mask = AMD64_CALLEE_REGS;
2260                 --i;
2261                 ins = tmp->data;
2262                 spec = ins_spec [ins->opcode];
2263                 prev_dreg = -1;
2264                 clob_dreg = -1;
2265                 DEBUG (g_print ("processing:"));
2266                 DEBUG (print_ins (i, ins));
2267                 if (spec [MONO_INST_CLOB] == 's') {
2268                         /*
2269                          * Shift opcodes, SREG2 must be RCX
2270                          */
2271                         if (rs->ifree_mask & (1 << AMD64_RCX)) {
2272                                 if (ins->sreg2 < MONO_MAX_IREGS) {
2273                                         /* Argument already in hard reg, need to copy */
2274                                         MonoInst *copy = create_copy_ins (cfg, AMD64_RCX, ins->sreg2, NULL, FALSE);
2275                                         insert_before_ins (ins, tmp, copy);
2276                                 }
2277                                 else {
2278                                         DEBUG (g_print ("\tshortcut assignment of R%d to ECX\n", ins->sreg2));
2279                                         assign_ireg (rs, ins->sreg2, AMD64_RCX);
2280                                 }
2281                         } else {
2282                                 int need_ecx_spill = TRUE;
2283                                 /*
2284                                  * we first check if src1/dreg is already assigned a register
2285                                  * and then we force a spill of the var assigned to ECX.
2286                                  */
2287                                 /* the destination register can't be ECX */
2288                                 dest_mask &= ~ (1 << AMD64_RCX);
2289                                 src1_mask &= ~ (1 << AMD64_RCX);
2290                                 val = rs->iassign [ins->dreg];
2291                                 /*
2292                                  * the destination register is already assigned to ECX:
2293                                  * we need to allocate another register for it and then
2294                                  * copy from this to ECX.
2295                                  */
2296                                 if (val == AMD64_RCX && ins->dreg != ins->sreg2) {
2297                                         int new_dest;
2298                                         new_dest = mono_amd64_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
2299                                         g_assert (new_dest >= 0);
2300                                         DEBUG (g_print ("\tclob:s changing dreg R%d to %s from ECX\n", ins->dreg, mono_arch_regname (new_dest)));
2301
2302                                         rs->isymbolic [new_dest] = ins->dreg;
2303                                         rs->iassign [ins->dreg] = new_dest;
2304                                         clob_dreg = ins->dreg;
2305                                         ins->dreg = new_dest;
2306                                         create_copy_ins (cfg, AMD64_RCX, new_dest, ins, FALSE);
2307                                         need_ecx_spill = FALSE;
2308                                         /*DEBUG (g_print ("\tforced spill of R%d\n", ins->dreg));
2309                                         val = get_register_force_spilling (cfg, tmp, ins, ins->dreg);
2310                                         rs->iassign [ins->dreg] = val;
2311                                         rs->isymbolic [val] = prev_dreg;
2312                                         ins->dreg = val;*/
2313                                 }
2314                                 if (is_global_ireg (ins->sreg2)) {
2315                                         MonoInst *copy = create_copy_ins (cfg, AMD64_RCX, ins->sreg2, NULL, FALSE);
2316                                         insert_before_ins (ins, tmp, copy);
2317                                 }
2318                                 else {
2319                                         val = rs->iassign [ins->sreg2];
2320                                         if (val >= 0 && val != AMD64_RCX) {
2321                                                 MonoInst *move = create_copy_ins (cfg, AMD64_RCX, val, NULL, FALSE);
2322                                                 DEBUG (g_print ("\tmoved arg from R%d (%d) to ECX\n", val, ins->sreg2));
2323                                                 move->next = ins;
2324                                                 g_assert_not_reached ();
2325                                                 /* FIXME: where is move connected to the instruction list? */
2326                                                 //tmp->prev->data->next = move;
2327                                         }
2328                                         else {
2329                                                 if (val == AMD64_RCX)
2330                                                 need_ecx_spill = FALSE;
2331                                         }
2332                                 }
2333                                 if (need_ecx_spill && !(rs->ifree_mask & (1 << AMD64_RCX))) {
2334                                         DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [AMD64_RCX]));
2335                                         get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [AMD64_RCX], FALSE);
2336                                         mono_regstate_free_int (rs, AMD64_RCX);
2337                                 }
2338                                 if (!is_global_ireg (ins->sreg2))
2339                                         /* force-set sreg2 */
2340                                         assign_ireg (rs, ins->sreg2, AMD64_RCX);
2341                         }
2342                         ins->sreg2 = AMD64_RCX;
2343                 } else if (spec [MONO_INST_CLOB] == 'd') {
2344                         /*
2345                          * DIVISION/REMAINER
2346                          */
2347                         int dest_reg = AMD64_RAX;
2348                         int clob_reg = AMD64_RDX;
2349                         if (spec [MONO_INST_DEST] == 'd') {
2350                                 dest_reg = AMD64_RDX; /* reminder */
2351                                 clob_reg = AMD64_RAX;
2352                         }
2353                         if (is_global_ireg (ins->dreg))
2354                                 val = ins->dreg;
2355                         else
2356                                 val = rs->iassign [ins->dreg];
2357                         if (0 && val >= 0 && val != dest_reg && !(rs->ifree_mask & (1 << dest_reg))) {
2358                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
2359                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg], FALSE);
2360                                 mono_regstate_free_int (rs, dest_reg);
2361                         }
2362                         if (val < 0) {
2363                                 if (val < -1) {
2364                                         /* the register gets spilled after this inst */
2365                                         int spill = -val -1;
2366                                         dest_mask = 1 << clob_reg;
2367                                         prev_dreg = ins->dreg;
2368                                         val = mono_regstate_alloc_int (rs, dest_mask);
2369                                         if (val < 0)
2370                                                 val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg, FALSE);
2371                                         rs->iassign [ins->dreg] = val;
2372                                         if (spill)
2373                                                 create_spilled_store (cfg, spill, val, prev_dreg, ins, FALSE);
2374                                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
2375                                         rs->isymbolic [val] = prev_dreg;
2376                                         ins->dreg = val;
2377                                 } else {
2378                                         DEBUG (g_print ("\tshortcut assignment of R%d to %s\n", ins->dreg, mono_arch_regname (dest_reg)));
2379                                         prev_dreg = ins->dreg;
2380                                         assign_ireg (rs, ins->dreg, dest_reg);
2381                                         ins->dreg = dest_reg;
2382                                         val = dest_reg;
2383                                 }
2384                         }
2385
2386                         //DEBUG (g_print ("dest reg in div assigned: %s\n", mono_arch_regname (val)));
2387                         if (val != dest_reg) { /* force a copy */
2388                                 create_copy_ins (cfg, val, dest_reg, ins, FALSE);
2389                                 if (!(rs->ifree_mask & (1 << dest_reg)) && rs->isymbolic [dest_reg] >= MONO_MAX_IREGS) {
2390                                         DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [dest_reg]));
2391                                         get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [dest_reg], FALSE);
2392                                         mono_regstate_free_int (rs, dest_reg);
2393                                 }
2394                         }
2395                         if (!(rs->ifree_mask & (1 << clob_reg)) && (clob_reg != val) && (rs->isymbolic [clob_reg] >= MONO_MAX_IREGS)) {
2396                                 DEBUG (g_print ("\tforced spill of clobbered reg R%d\n", rs->isymbolic [clob_reg]));
2397                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [clob_reg], FALSE);
2398                                 mono_regstate_free_int (rs, clob_reg);
2399                         }
2400                         src1_mask = 1 << AMD64_RAX;
2401                         src2_mask = 1 << AMD64_RCX;
2402                 }
2403                 if (spec [MONO_INST_DEST] == 'l') {
2404                         int hreg;
2405                         val = rs->iassign [ins->dreg];
2406                         /* check special case when dreg have been moved from ecx (clob shift) */
2407                         if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
2408                                 hreg = clob_dreg + 1;
2409                         else
2410                                 hreg = ins->dreg + 1;
2411
2412                         /* base prev_dreg on fixed hreg, handle clob case */
2413                         val = hreg - 1;
2414
2415                         if (val != rs->isymbolic [AMD64_RAX] && !(rs->ifree_mask & (1 << AMD64_RAX))) {
2416                                 DEBUG (g_print ("\t(long-low) forced spill of R%d\n", rs->isymbolic [AMD64_RAX]));
2417                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [AMD64_RAX], FALSE);
2418                                 mono_regstate_free_int (rs, AMD64_RAX);
2419                         }
2420                         if (hreg != rs->isymbolic [AMD64_RDX] && !(rs->ifree_mask & (1 << AMD64_RDX))) {
2421                                 DEBUG (g_print ("\t(long-high) forced spill of R%d\n", rs->isymbolic [AMD64_RDX]));
2422                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [AMD64_RDX], FALSE);
2423                                 mono_regstate_free_int (rs, AMD64_RDX);
2424                         }
2425                 }
2426
2427                 /*
2428                  * TRACK DREG
2429                  */
2430                 if (spec [MONO_INST_DEST] == 'f') {
2431                         if (use_sse2) {
2432                                 /* Allocate an XMM reg the same way as an int reg */
2433                                 if (reg_is_soft (ins->dreg, TRUE)) {
2434                                         val = rs->fassign [ins->dreg];
2435                                         prev_dreg = ins->dreg;
2436
2437                                         if (val < 0) {
2438                                                 int spill = 0;
2439                                                 if (val < -1) {
2440                                                         /* the register gets spilled after this inst */
2441                                                         spill = -val -1;
2442                                                 }
2443                                                 val = mono_amd64_alloc_float_reg (cfg, tmp, ins, AMD64_CALLEE_FREGS, ins->dreg);
2444                                                 rs->fassign [ins->dreg] = val;
2445                                                 if (spill)
2446                                                         create_spilled_store (cfg, spill, val, prev_dreg, ins, TRUE);
2447                                         }
2448                                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_amd64_regname (val, TRUE), ins->dreg));
2449                                         rs->fsymbolic [val] = prev_dreg;
2450                                         ins->dreg = val;
2451                                 }
2452                         }
2453                         else if (spec [MONO_INST_CLOB] != 'm') {
2454                                 if (reginfof [ins->dreg].flags & MONO_X86_FP_NEEDS_SPILL) {
2455                                         GList *spill_node;
2456                                         MonoInst *store;
2457                                         spill_node = g_list_first (fspill_list);
2458                                         g_assert (spill_node);
2459
2460                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->dreg, ins);
2461                                         insert_before_ins (ins, tmp, store);
2462                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
2463                                         fspill--;
2464                                 }
2465                         }
2466                 } else if (spec [MONO_INST_DEST] == 'L') {
2467                         int hreg;
2468                         val = rs->iassign [ins->dreg];
2469                         /* check special case when dreg have been moved from ecx (clob shift) */
2470                         if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
2471                                 hreg = clob_dreg + 1;
2472                         else
2473                                 hreg = ins->dreg + 1;
2474
2475                         /* base prev_dreg on fixed hreg, handle clob case */
2476                         prev_dreg = hreg - 1;
2477
2478                         if (val < 0) {
2479                                 int spill = 0;
2480                                 if (val < -1) {
2481                                         /* the register gets spilled after this inst */
2482                                         spill = -val -1;
2483                                 }
2484                                 val = mono_amd64_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
2485                                 rs->iassign [ins->dreg] = val;
2486                                 if (spill)
2487                                         create_spilled_store (cfg, spill, val, prev_dreg, ins, FALSE);
2488                         }
2489
2490                         DEBUG (g_print ("\tassigned dreg (long) %s to dest R%d\n", mono_arch_regname (val), hreg - 1));
2491
2492                         rs->isymbolic [val] = hreg - 1;
2493                         ins->dreg = val;
2494
2495                         val = rs->iassign [hreg];
2496                         if (val < 0) {
2497                                 int spill = 0;
2498                                 if (val < -1) {
2499                                         /* the register gets spilled after this inst */
2500                                         spill = -val -1;
2501                                 }
2502                                 val = mono_amd64_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
2503                                 rs->iassign [hreg] = val;
2504                                 if (spill)
2505                                         create_spilled_store (cfg, spill, val, hreg, ins, FALSE);
2506                         }
2507
2508                         DEBUG (g_print ("\tassigned hreg (long-high) %s to dest R%d\n", mono_arch_regname (val), hreg));
2509                         rs->isymbolic [val] = hreg;
2510                         /* save reg allocating into unused */
2511                         ins->unused = val;
2512
2513                         /* check if we can free our long reg */
2514                         if (reg_is_freeable (val, FALSE) && hreg >= 0 && reginfo [hreg].born_in >= i) {
2515                                 DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (val), hreg, reginfo [hreg].born_in));
2516                                 mono_regstate_free_int (rs, val);
2517                         }
2518                 }
2519                 else if (ins->dreg >= MONO_MAX_IREGS) {
2520                         int hreg;
2521                         val = rs->iassign [ins->dreg];
2522                         if (spec [MONO_INST_DEST] == 'l') {
2523                                 /* check special case when dreg have been moved from ecx (clob shift) */
2524                                 if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
2525                                         hreg = clob_dreg + 1;
2526                                 else
2527                                         hreg = ins->dreg + 1;
2528
2529                                 /* base prev_dreg on fixed hreg, handle clob case */
2530                                 prev_dreg = hreg - 1;
2531                         } else
2532                                 prev_dreg = ins->dreg;
2533
2534                         if (val < 0) {
2535                                 int spill = 0;
2536                                 if (val < -1) {
2537                                         /* the register gets spilled after this inst */
2538                                         spill = -val -1;
2539                                 }
2540                                 val = mono_amd64_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->dreg, reginfo [ins->dreg].flags);
2541                                 rs->iassign [ins->dreg] = val;
2542                                 if (spill)
2543                                         create_spilled_store (cfg, spill, val, prev_dreg, ins, FALSE);
2544                         }
2545                         DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
2546                         rs->isymbolic [val] = prev_dreg;
2547                         ins->dreg = val;
2548                         /* handle cases where lreg needs to be eax:edx */
2549                         if (spec [MONO_INST_DEST] == 'l') {
2550                                 /* check special case when dreg have been moved from ecx (clob shift) */
2551                                 int hreg = prev_dreg + 1;
2552                                 val = rs->iassign [hreg];
2553                                 if (val < 0) {
2554                                         int spill = 0;
2555                                         if (val < -1) {
2556                                                 /* the register gets spilled after this inst */
2557                                                 spill = -val -1;
2558                                         }
2559                                         val = mono_amd64_alloc_int_reg (cfg, tmp, ins, dest_mask, hreg, reginfo [hreg].flags);
2560                                         rs->iassign [hreg] = val;
2561                                         if (spill)
2562                                                 create_spilled_store (cfg, spill, val, hreg, ins, FALSE);
2563                                 }
2564                                 DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
2565                                 rs->isymbolic [val] = hreg;
2566                                 if (ins->dreg == AMD64_RAX) {
2567                                         if (val != AMD64_RDX)
2568                                                 create_copy_ins (cfg, val, AMD64_RDX, ins, FALSE);
2569                                 } else if (ins->dreg == AMD64_RDX) {
2570                                         if (val == AMD64_RAX) {
2571                                                 /* swap */
2572                                                 g_assert_not_reached ();
2573                                         } else {
2574                                                 /* two forced copies */
2575                                                 create_copy_ins (cfg, val, AMD64_RDX, ins, FALSE);
2576                                                 create_copy_ins (cfg, ins->dreg, AMD64_RAX, ins, FALSE);
2577                                         }
2578                                 } else {
2579                                         if (val == AMD64_RDX) {
2580                                                 create_copy_ins (cfg, ins->dreg, AMD64_RAX, ins, FALSE);
2581                                         } else {
2582                                                 /* two forced copies */
2583                                                 create_copy_ins (cfg, val, AMD64_RDX, ins, FALSE);
2584                                                 create_copy_ins (cfg, ins->dreg, AMD64_RAX, ins, FALSE);
2585                                         }
2586                                 }
2587                                 if (reg_is_freeable (val, FALSE) && hreg >= 0 && reginfo [hreg].born_in >= i) {
2588                                         DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
2589                                         mono_regstate_free_int (rs, val);
2590                                 }
2591                         } else if (spec [MONO_INST_DEST] == 'a' && ins->dreg != AMD64_RAX && spec [MONO_INST_CLOB] != 'd') {
2592                                 /* this instruction only outputs to EAX, need to copy */
2593                                 create_copy_ins (cfg, ins->dreg, AMD64_RAX, ins, FALSE);
2594                         } else if (spec [MONO_INST_DEST] == 'd' && ins->dreg != AMD64_RDX && spec [MONO_INST_CLOB] != 'd') {
2595                                 create_copy_ins (cfg, ins->dreg, AMD64_RDX, ins, FALSE);
2596                         }
2597                 }
2598
2599                 if (use_sse2 && spec [MONO_INST_DEST] == 'f' && reg_is_freeable (ins->dreg, TRUE) && prev_dreg >= 0 && reginfof [prev_dreg].born_in >= i) {
2600                         DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_fregname (ins->dreg), prev_dreg, reginfof [prev_dreg].born_in));
2601                         mono_regstate_free_float (rs, ins->dreg);
2602                 }
2603                 if (spec [MONO_INST_DEST] != 'f' && reg_is_freeable (ins->dreg, FALSE) && prev_dreg >= 0 && reginfo [prev_dreg].born_in >= i) {
2604                         DEBUG (g_print ("\tfreeable %s (R%d) (born in %d)\n", mono_arch_regname (ins->dreg), prev_dreg, reginfo [prev_dreg].born_in));
2605                         mono_regstate_free_int (rs, ins->dreg);
2606                 }
2607
2608                 /* put src1 in EAX if it needs to be */
2609                 if (spec [MONO_INST_SRC1] == 'a') {
2610                         if (!(rs->ifree_mask & (1 << AMD64_RAX))) {
2611                                 DEBUG (g_print ("\tforced spill of R%d\n", rs->isymbolic [AMD64_RAX]));
2612                                 get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [AMD64_RAX], FALSE);
2613                                 mono_regstate_free_int (rs, AMD64_RAX);
2614                         }
2615                         if (ins->sreg1 < MONO_MAX_IREGS) {
2616                                 /* The argument is already in a hard reg, need to copy */
2617                                 MonoInst *copy = create_copy_ins (cfg, AMD64_RAX, ins->sreg1, NULL, FALSE);
2618                                 insert_before_ins (ins, tmp, copy);
2619                         }
2620                         else
2621                                 /* force-set sreg1 */
2622                                 assign_ireg (rs, ins->sreg1, AMD64_RAX);
2623                         ins->sreg1 = AMD64_RAX;
2624                 }
2625
2626                 /*
2627                  * TRACK SREG1
2628                  */
2629                 if (spec [MONO_INST_SRC1] == 'f') {
2630                         if (use_sse2) {
2631                                 if (reg_is_soft (ins->sreg1, TRUE)) {
2632                                         val = rs->fassign [ins->sreg1];
2633                                         prev_sreg1 = ins->sreg1;
2634                                         if (val < 0) {
2635                                                 int spill = 0;
2636                                                 if (val < -1) {
2637                                                         /* the register gets spilled after this inst */
2638                                                         spill = -val -1;
2639                                                 }
2640                                                 val = mono_amd64_alloc_float_reg (cfg, tmp, ins, AMD64_CALLEE_FREGS, ins->sreg1);
2641                                                 rs->fassign [ins->sreg1] = val;
2642                                                 DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_fregname (val), ins->sreg1));
2643                                                 if (spill) {
2644                                                         MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL, TRUE);
2645                                                         insert_before_ins (ins, tmp, store);
2646                                                 }
2647                                         }
2648                                         rs->fsymbolic [val] = prev_sreg1;
2649                                         ins->sreg1 = val;
2650                                 } else {
2651                                         prev_sreg1 = -1;
2652                                 }
2653                         }
2654                         else
2655                                 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD) {
2656                                 MonoInst *load;
2657                                 MonoInst *store = NULL;
2658
2659                                 if (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
2660                                         GList *spill_node;
2661                                         spill_node = g_list_first (fspill_list);
2662                                         g_assert (spill_node);
2663
2664                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg1, ins);
2665                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
2666                                 }
2667
2668                                 fspill++;
2669                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
2670                                 load = create_spilled_load_float (cfg, fspill, ins->sreg1, ins);
2671                                 insert_before_ins (ins, tmp, load);
2672                                 if (store)
2673                                         insert_before_ins (load, tmp, store);
2674                         }
2675                 } else if ((spec [MONO_INST_DEST] == 'L') && (spec [MONO_INST_SRC1] == 'L')) {
2676                         /* force source to be same as dest */
2677                         rs->iassign [ins->sreg1] = ins->dreg;
2678                         rs->iassign [ins->sreg1 + 1] = ins->unused;
2679
2680                         DEBUG (g_print ("\tassigned sreg1 (long) %s to sreg1 R%d\n", mono_arch_regname (ins->dreg), ins->sreg1));
2681                         DEBUG (g_print ("\tassigned sreg1 (long-high) %s to sreg1 R%d\n", mono_arch_regname (ins->unused), ins->sreg1 + 1));
2682
2683                         ins->sreg1 = ins->dreg;
2684                         /*
2685                          * No need for saving the reg, we know that src1=dest in this cases
2686                          * ins->inst_c0 = ins->unused;
2687                          */
2688
2689                         /* make sure that we remove them from free mask */
2690                         rs->ifree_mask &= ~ (1 << ins->dreg);
2691                         rs->ifree_mask &= ~ (1 << ins->unused);
2692                 }
2693                 else if (ins->sreg1 >= MONO_MAX_IREGS) {
2694                         val = rs->iassign [ins->sreg1];
2695                         prev_sreg1 = ins->sreg1;
2696                         if (val < 0) {
2697                                 int spill = 0;
2698                                 if (val < -1) {
2699                                         /* the register gets spilled after this inst */
2700                                         spill = -val -1;
2701                                 }
2702                                 if (0 && (ins->opcode == OP_MOVE)) {
2703                                         /*
2704                                          * small optimization: the dest register is already allocated
2705                                          * but the src one is not: we can simply assign the same register
2706                                          * here and peephole will get rid of the instruction later.
2707                                          * This optimization may interfere with the clobbering handling:
2708                                          * it removes a mov operation that will be added again to handle clobbering.
2709                                          * There are also some other issues that should with make testjit.
2710                                          */
2711                                         mono_regstate_alloc_int (rs, 1 << ins->dreg);
2712                                         val = rs->iassign [ins->sreg1] = ins->dreg;
2713                                         //g_assert (val >= 0);
2714                                         DEBUG (g_print ("\tfast assigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
2715                                 } else {
2716                                         //g_assert (val == -1); /* source cannot be spilled */
2717                                         val = mono_amd64_alloc_int_reg (cfg, tmp, ins, src1_mask, ins->sreg1, reginfo [ins->sreg1].flags);
2718                                         rs->iassign [ins->sreg1] = val;
2719                                         DEBUG (g_print ("\tassigned sreg1 %s to R%d\n", mono_arch_regname (val), ins->sreg1));
2720                                 }
2721                                 if (spill) {
2722                                         MonoInst *store = create_spilled_store (cfg, spill, val, prev_sreg1, NULL, FALSE);
2723                                         insert_before_ins (ins, tmp, store);
2724                                 }
2725                         }
2726                         rs->isymbolic [val] = prev_sreg1;
2727                         ins->sreg1 = val;
2728                 } else {
2729                         prev_sreg1 = -1;
2730                 }
2731
2732                 /* handle clobbering of sreg1 */
2733                 if (((spec [MONO_INST_DEST] == 'f' && spec [MONO_INST_SRC1] == 'f' && use_sse2) || spec [MONO_INST_CLOB] == '1' || spec [MONO_INST_CLOB] == 's') && ins->dreg != ins->sreg1) {
2734                         MonoInst *sreg2_copy = NULL;
2735                         MonoInst *copy;
2736                         gboolean fp = (spec [MONO_INST_SRC1] == 'f');
2737
2738                         if (ins->dreg == ins->sreg2) {
2739                                 /*
2740                                  * copying sreg1 to dreg could clobber sreg2, so allocate a new
2741                                  * register for it.
2742                                  */
2743                                 int reg2 = 0;
2744
2745                                 if (fp)
2746                                         reg2 = mono_amd64_alloc_float_reg (cfg, tmp, ins, AMD64_CALLEE_FREGS, ins->sreg2);
2747                                 else
2748                                         reg2 = mono_amd64_alloc_int_reg (cfg, tmp, ins, dest_mask, ins->sreg2, 0);
2749
2750                                 DEBUG (g_print ("\tneed to copy sreg2 %s to reg %s\n", mono_amd64_regname (ins->sreg2, fp), mono_amd64_regname (reg2, fp)));
2751                                 sreg2_copy = create_copy_ins (cfg, reg2, ins->sreg2, NULL, fp);
2752                                 prev_sreg2 = ins->sreg2 = reg2;
2753
2754                                 if (fp)
2755                                         mono_regstate_free_float (rs, reg2);
2756                                 else
2757                                         mono_regstate_free_int (rs, reg2);
2758                         }
2759
2760                         copy = create_copy_ins (cfg, ins->dreg, ins->sreg1, NULL, fp);
2761                         DEBUG (g_print ("\tneed to copy sreg1 %s to dreg %s\n", mono_amd64_regname (ins->sreg1, fp), mono_amd64_regname (ins->dreg, fp)));
2762                         insert_before_ins (ins, tmp, copy);
2763
2764                         if (sreg2_copy)
2765                                 insert_before_ins (copy, tmp, sreg2_copy);
2766
2767                         /*
2768                          * Need to prevent sreg2 to be allocated to sreg1, since that
2769                          * would screw up the previous copy.
2770                          */
2771                         src2_mask &= ~ (1 << ins->sreg1);
2772                         /* we set sreg1 to dest as well */
2773                         prev_sreg1 = ins->sreg1 = ins->dreg;
2774                         src2_mask &= ~ (1 << ins->dreg);
2775                 }
2776
2777                 /*
2778                  * TRACK SREG2
2779                  */
2780                 if (spec [MONO_INST_SRC2] == 'f') {
2781                         if (use_sse2) {
2782                                 if (reg_is_soft (ins->sreg2, TRUE)) {
2783                                         val = rs->fassign [ins->sreg2];
2784                                         prev_sreg2 = ins->sreg2;
2785                                         if (val < 0) {
2786                                                 int spill = 0;
2787                                                 if (val < -1) {
2788                                                         /* the register gets spilled after this inst */
2789                                                         spill = -val -1;
2790                                                 }
2791                                                 val = mono_amd64_alloc_float_reg (cfg, tmp, ins, AMD64_CALLEE_FREGS, ins->sreg2);
2792                                                 rs->fassign [ins->sreg2] = val;
2793                                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_fregname (val), ins->sreg2));
2794                                                 if (spill)
2795                                                         create_spilled_store (cfg, spill, val, prev_sreg2, ins, TRUE);
2796                                         }
2797                                         rs->fsymbolic [val] = prev_sreg2;
2798                                         ins->sreg2 = val;
2799                                 } else {
2800                                         prev_sreg2 = -1;
2801                                 }
2802                         }
2803                         else
2804                         if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD) {
2805                                 MonoInst *load;
2806                                 MonoInst *store = NULL;
2807
2808                                 if (reginfof [ins->sreg2].flags & MONO_X86_FP_NEEDS_LOAD_SPILL) {
2809                                         GList *spill_node;
2810
2811                                         spill_node = g_list_first (fspill_list);
2812                                         g_assert (spill_node);
2813                                         if (spec [MONO_INST_SRC1] == 'f' && (reginfof [ins->sreg1].flags & MONO_X86_FP_NEEDS_LOAD_SPILL))
2814                                                 spill_node = g_list_next (spill_node);
2815
2816                                         store = create_spilled_store_float (cfg, GPOINTER_TO_INT (spill_node->data), ins->sreg2, ins);
2817                                         fspill_list = g_list_remove (fspill_list, spill_node->data);
2818                                 }
2819
2820                                 fspill++;
2821                                 fspill_list = g_list_prepend (fspill_list, GINT_TO_POINTER(fspill));
2822                                 load = create_spilled_load_float (cfg, fspill, ins->sreg2, ins);
2823                                 insert_before_ins (ins, tmp, load);
2824                                 if (store)
2825                                         insert_before_ins (load, tmp, store);
2826                         }
2827                 }
2828                 else if (ins->sreg2 >= MONO_MAX_IREGS) {
2829                         val = rs->iassign [ins->sreg2];
2830                         prev_sreg2 = ins->sreg2;
2831                         if (val < 0) {
2832                                 int spill = 0;
2833                                 if (val < -1) {
2834                                         /* the register gets spilled after this inst */
2835                                         spill = -val -1;
2836                                 }
2837                                 val = mono_amd64_alloc_int_reg (cfg, tmp, ins, src2_mask, ins->sreg2, reginfo [ins->sreg2].flags);
2838                                 rs->iassign [ins->sreg2] = val;
2839                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d\n", mono_arch_regname (val), ins->sreg2));
2840                                 if (spill)
2841                                         create_spilled_store (cfg, spill, val, prev_sreg2, ins, FALSE);
2842                         }
2843                         rs->isymbolic [val] = prev_sreg2;
2844                         ins->sreg2 = val;
2845                         if (spec [MONO_INST_CLOB] == 's' && ins->sreg2 != AMD64_RCX) {
2846                                 DEBUG (g_print ("\tassigned sreg2 %s to R%d, but ECX is needed (R%d)\n", mono_arch_regname (val), ins->sreg2, rs->iassign [AMD64_RCX]));
2847                         }
2848                 } else {
2849                         prev_sreg2 = -1;
2850                 }
2851
2852                 if (spec [MONO_INST_CLOB] == 'c') {
2853                         int j, s;
2854                         MonoCallInst *call = (MonoCallInst*)ins;
2855                         GSList *list;
2856                         guint32 clob_mask = AMD64_CALLEE_REGS;
2857
2858                         for (j = 0; j < MONO_MAX_IREGS; ++j) {
2859                                 s = 1 << j;
2860                                 if ((clob_mask & s) && !(rs->ifree_mask & s) && j != ins->sreg1) {
2861                                         get_register_force_spilling (cfg, tmp, ins, rs->isymbolic [j], FALSE);
2862                                         mono_regstate_free_int (rs, j);
2863                                         //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
2864                                 }
2865                         }
2866
2867                         if (use_sse2) {
2868                                 clob_mask = AMD64_CALLEE_FREGS;
2869
2870                                 for (j = 0; j < MONO_MAX_FREGS; ++j) {
2871                                         s = 1 << j;
2872                                         if ((clob_mask & s) && !(rs->ffree_mask & s) && j != ins->sreg1) {
2873                                                 get_register_force_spilling (cfg, tmp, ins, rs->fsymbolic [j], TRUE);
2874                                                 mono_regstate_free_float (rs, j);
2875                                                 //g_warning ("register %s busy at call site\n", mono_arch_regname (j));
2876                                         }
2877                                 }
2878                         }
2879
2880                         /*
2881                          * Assign all registers in call->out_reg_args to the proper
2882                          * argument registers.
2883                          */
2884
2885                         list = call->out_ireg_args;
2886                         if (list) {
2887                                 while (list) {
2888                                         guint64 regpair;
2889                                         int reg, hreg;
2890
2891                                         regpair = (guint64) (list->data);
2892                                         hreg = regpair >> 32;
2893                                         reg = regpair & 0xffffffff;
2894
2895                                         assign_ireg (rs, reg, hreg);
2896
2897                                         DEBUG (g_print ("\tassigned arg reg %s to R%d\n", mono_arch_regname (hreg), reg));
2898
2899                                         list = g_slist_next (list);
2900                                 }
2901                                 g_slist_free (call->out_ireg_args);
2902                         }
2903
2904                         list = call->out_freg_args;
2905                         if (list && use_sse2) {
2906                                 while (list) {
2907                                         guint64 regpair;
2908                                         int reg, hreg;
2909
2910                                         regpair = (guint64) (list->data);
2911                                         hreg = regpair >> 32;
2912                                         reg = regpair & 0xffffffff;
2913
2914                                         rs->fassign [reg] = hreg;
2915                                         rs->fsymbolic [hreg] = reg;
2916                                         rs->ffree_mask &= ~ (1 << hreg);
2917
2918                                         list = g_slist_next (list);
2919                                 }
2920                         }
2921                         if (call->out_freg_args)
2922                                 g_slist_free (call->out_freg_args);
2923                 }
2924
2925                 /*if (reg_is_freeable (ins->sreg1) && prev_sreg1 >= 0 && reginfo [prev_sreg1].born_in >= i) {
2926                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg1)));
2927                         mono_regstate_free_int (rs, ins->sreg1);
2928                 }
2929                 if (reg_is_freeable (ins->sreg2) && prev_sreg2 >= 0 && reginfo [prev_sreg2].born_in >= i) {
2930                         DEBUG (g_print ("freeable %s\n", mono_arch_regname (ins->sreg2)));
2931                         mono_regstate_free_int (rs, ins->sreg2);
2932                 }*/
2933
2934                 DEBUG (print_ins (i, ins));
2935                 /* this may result from a insert_before call */
2936                 if (!tmp->next)
2937                         bb->code = tmp->data;
2938                 tmp = tmp->next;
2939         }
2940
2941         g_free (reginfo);
2942         g_free (reginfof);
2943         g_list_free (fspill_list);
2944 }
2945
2946 static unsigned char*
2947 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2948 {
2949         if (use_sse2) {
2950                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2951         }
2952         else {
2953                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
2954                 x86_fnstcw_membase(code, AMD64_RSP, 0);
2955                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
2956                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
2957                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
2958                 amd64_fldcw_membase (code, AMD64_RSP, 2);
2959                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
2960                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
2961                 amd64_pop_reg (code, dreg);
2962                 amd64_fldcw_membase (code, AMD64_RSP, 0);
2963                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
2964         }
2965
2966         if (size == 1)
2967                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2968         else if (size == 2)
2969                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2970         return code;
2971 }
2972
2973 static unsigned char*
2974 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2975 {
2976         int sreg = tree->sreg1;
2977         int need_touch = FALSE;
2978
2979 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2980         if (!tree->flags & MONO_INST_INIT)
2981                 need_touch = TRUE;
2982 #endif
2983
2984         if (need_touch) {
2985                 guint8* br[5];
2986
2987                 /*
2988                  * Under Windows:
2989                  * If requested stack size is larger than one page,
2990                  * perform stack-touch operation
2991                  */
2992                 /*
2993                  * Generate stack probe code.
2994                  * Under Windows, it is necessary to allocate one page at a time,
2995                  * "touching" stack after each successful sub-allocation. This is
2996                  * because of the way stack growth is implemented - there is a
2997                  * guard page before the lowest stack page that is currently commited.
2998                  * Stack normally grows sequentially so OS traps access to the
2999                  * guard page and commits more pages when needed.
3000                  */
3001                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3002                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3003
3004                 br[2] = code; /* loop */
3005                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3006                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3007                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3008                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3009                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3010                 amd64_patch (br[3], br[2]);
3011                 amd64_test_reg_reg (code, sreg, sreg);
3012                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3013                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3014
3015                 br[1] = code; x86_jump8 (code, 0);
3016
3017                 amd64_patch (br[0], code);
3018                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3019                 amd64_patch (br[1], code);
3020                 amd64_patch (br[4], code);
3021         }
3022         else
3023                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3024
3025         if (tree->flags & MONO_INST_INIT) {
3026                 int offset = 0;
3027                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3028                         amd64_push_reg (code, AMD64_RAX);
3029                         offset += 8;
3030                 }
3031                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3032                         amd64_push_reg (code, AMD64_RCX);
3033                         offset += 8;
3034                 }
3035                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3036                         amd64_push_reg (code, AMD64_RDI);
3037                         offset += 8;
3038                 }
3039
3040                 amd64_shift_reg_imm (code, X86_SHR, sreg, 4);
3041                 if (sreg != AMD64_RCX)
3042                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3043                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3044
3045                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3046                 amd64_cld (code);
3047                 amd64_prefix (code, X86_REP_PREFIX);
3048                 amd64_stosl (code);
3049
3050                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3051                         amd64_pop_reg (code, AMD64_RDI);
3052                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3053                         amd64_pop_reg (code, AMD64_RCX);
3054                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3055                         amd64_pop_reg (code, AMD64_RAX);
3056         }
3057         return code;
3058 }
3059
3060 static guint8*
3061 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3062 {
3063         CallInfo *cinfo;
3064         guint32 offset, quad;
3065
3066         /* Move return value to the target register */
3067         /* FIXME: do this in the local reg allocator */
3068         switch (ins->opcode) {
3069         case CEE_CALL:
3070         case OP_CALL_REG:
3071         case OP_CALL_MEMBASE:
3072         case OP_LCALL:
3073         case OP_LCALL_REG:
3074         case OP_LCALL_MEMBASE:
3075                 if (ins->dreg != AMD64_RAX)
3076                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, 8);
3077                 break;
3078         case OP_FCALL:
3079         case OP_FCALL_REG:
3080         case OP_FCALL_MEMBASE:
3081                 /* FIXME: optimize this */
3082                 offset = mono_spillvar_offset_float (cfg, 0);
3083                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3084                         if (use_sse2)
3085                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3086                         else {
3087                                 amd64_movss_membase_reg (code, AMD64_RBP, offset, AMD64_XMM0);
3088                                 amd64_fld_membase (code, AMD64_RBP, offset, FALSE);
3089                         }
3090                 }
3091                 else {
3092                         if (use_sse2) {
3093                                 if (ins->dreg != AMD64_XMM0)
3094                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3095                         }
3096                         else {
3097                                 amd64_movsd_membase_reg (code, AMD64_RBP, offset, AMD64_XMM0);
3098                                 amd64_fld_membase (code, AMD64_RBP, offset, TRUE);
3099                         }
3100                 }
3101                 break;
3102         case OP_VCALL:
3103         case OP_VCALL_REG:
3104         case OP_VCALL_MEMBASE:
3105                 cinfo = get_call_info (((MonoCallInst*)ins)->signature, FALSE);
3106                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3107                         /* Pop the destination address from the stack */
3108                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3109                         amd64_pop_reg (code, AMD64_RCX);
3110
3111                         for (quad = 0; quad < 2; quad ++) {
3112                                 switch (cinfo->ret.pair_storage [quad]) {
3113                                 case ArgInIReg:
3114                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3115                                         break;
3116                                 case ArgInFloatSSEReg:
3117                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3118                                         break;
3119                                 case ArgInDoubleSSEReg:
3120                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3121                                         break;
3122                                 case ArgNone:
3123                                         break;
3124                                 default:
3125                                         NOT_IMPLEMENTED;
3126                                 }
3127                         }
3128                 }
3129                 g_free (cinfo);
3130                 break;
3131         }
3132
3133         return code;
3134 }
3135
3136 /*
3137  * emit_load_volatile_arguments:
3138  *
3139  *  Load volatile arguments from the stack to the original input registers.
3140  * Required before a tail call.
3141  */
3142 static guint8*
3143 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
3144 {
3145         MonoMethod *method = cfg->method;
3146         MonoMethodSignature *sig;
3147         MonoInst *inst;
3148         CallInfo *cinfo;
3149         guint32 i;
3150
3151         /* FIXME: Generate intermediate code instead */
3152
3153         sig = mono_method_signature (method);
3154
3155         cinfo = get_call_info (sig, FALSE);
3156
3157         /* This is the opposite of the code in emit_prolog */
3158
3159         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
3160                 ArgInfo *ainfo = cinfo->args + i;
3161                 MonoType *arg_type;
3162                 inst = cfg->varinfo [i];
3163
3164                 if (sig->hasthis && (i == 0))
3165                         arg_type = &mono_defaults.object_class->byval_arg;
3166                 else
3167                         arg_type = sig->params [i - sig->hasthis];
3168
3169                 if (inst->opcode != OP_REGVAR) {
3170                         switch (ainfo->storage) {
3171                         case ArgInIReg: {
3172                                 guint32 size = 8;
3173
3174                                 /* FIXME: I1 etc */
3175                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
3176                                 break;
3177                         }
3178                         case ArgInFloatSSEReg:
3179                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3180                                 break;
3181                         case ArgInDoubleSSEReg:
3182                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
3183                                 break;
3184                         default:
3185                                 break;
3186                         }
3187                 }
3188         }
3189
3190         g_free (cinfo);
3191
3192         return code;
3193 }
3194
3195 #define REAL_PRINT_REG(text,reg) \
3196 mono_assert (reg >= 0); \
3197 amd64_push_reg (code, AMD64_RAX); \
3198 amd64_push_reg (code, AMD64_RDX); \
3199 amd64_push_reg (code, AMD64_RCX); \
3200 amd64_push_reg (code, reg); \
3201 amd64_push_imm (code, reg); \
3202 amd64_push_imm (code, text " %d %p\n"); \
3203 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3204 amd64_call_reg (code, AMD64_RAX); \
3205 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3206 amd64_pop_reg (code, AMD64_RCX); \
3207 amd64_pop_reg (code, AMD64_RDX); \
3208 amd64_pop_reg (code, AMD64_RAX);
3209
3210 /* benchmark and set based on cpu */
3211 #define LOOP_ALIGNMENT 8
3212 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3213
3214 void
3215 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3216 {
3217         MonoInst *ins;
3218         MonoCallInst *call;
3219         guint offset;
3220         guint8 *code = cfg->native_code + cfg->code_len;
3221         MonoInst *last_ins = NULL;
3222         guint last_offset = 0;
3223         int max_len, cpos;
3224
3225         if (cfg->opt & MONO_OPT_PEEPHOLE)
3226                 peephole_pass (cfg, bb);
3227
3228         if (cfg->opt & MONO_OPT_LOOP) {
3229                 int pad, align = LOOP_ALIGNMENT;
3230                 /* set alignment depending on cpu */
3231                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3232                         pad = align - pad;
3233                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3234                         amd64_padding (code, pad);
3235                         cfg->code_len += pad;
3236                         bb->native_offset = cfg->code_len;
3237                 }
3238         }
3239
3240         if (cfg->verbose_level > 2)
3241                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3242
3243         cpos = bb->max_offset;
3244
3245         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3246                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3247                 g_assert (!mono_compile_aot);
3248                 cpos += 6;
3249
3250                 cov->data [bb->dfn].cil_code = bb->cil_code;
3251                 /* this is not thread save, but good enough */
3252                 amd64_inc_mem (code, (guint64)&cov->data [bb->dfn].count);
3253         }
3254
3255         offset = code - cfg->native_code;
3256
3257         ins = bb->code;
3258         while (ins) {
3259                 offset = code - cfg->native_code;
3260
3261                 max_len = ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
3262
3263                 if (offset > (cfg->code_size - max_len - 16)) {
3264                         cfg->code_size *= 2;
3265                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3266                         code = cfg->native_code + offset;
3267                         mono_jit_stats.code_reallocs++;
3268                 }
3269
3270                 mono_debug_record_line_number (cfg, ins, offset);
3271
3272                 switch (ins->opcode) {
3273                 case OP_BIGMUL:
3274                         amd64_mul_reg (code, ins->sreg2, TRUE);
3275                         break;
3276                 case OP_BIGMUL_UN:
3277                         amd64_mul_reg (code, ins->sreg2, FALSE);
3278                         break;
3279                 case OP_X86_SETEQ_MEMBASE:
3280                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3281                         break;
3282                 case OP_STOREI1_MEMBASE_IMM:
3283                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3284                         break;
3285                 case OP_STOREI2_MEMBASE_IMM:
3286                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3287                         break;
3288                 case OP_STOREI4_MEMBASE_IMM:
3289                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3290                         break;
3291                 case OP_STOREI1_MEMBASE_REG:
3292                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3293                         break;
3294                 case OP_STOREI2_MEMBASE_REG:
3295                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3296                         break;
3297                 case OP_STORE_MEMBASE_REG:
3298                 case OP_STOREI8_MEMBASE_REG:
3299                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3300                         break;
3301                 case OP_STOREI4_MEMBASE_REG:
3302                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3303                         break;
3304                 case OP_STORE_MEMBASE_IMM:
3305                 case OP_STOREI8_MEMBASE_IMM:
3306                         if (amd64_is_imm32 (ins->inst_imm))
3307                                 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3308                         else {
3309                                 amd64_mov_reg_imm (code, GP_SCRATCH_REG, ins->inst_imm);
3310                                 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, GP_SCRATCH_REG, 8);
3311                         }
3312                         break;
3313                 case CEE_LDIND_I:
3314                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
3315                         break;
3316                 case CEE_LDIND_I4:
3317                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
3318                         break;
3319                 case CEE_LDIND_U4:
3320                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
3321                         break;
3322                 case OP_LOADU4_MEM:
3323                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
3324                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3325                         break;
3326                 case OP_LOAD_MEMBASE:
3327                 case OP_LOADI8_MEMBASE:
3328                         if (amd64_is_imm32 (ins->inst_offset)) {
3329                                 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3330                         }
3331                         else {
3332                                 amd64_mov_reg_imm_size (code, GP_SCRATCH_REG, ins->inst_offset, 8);
3333                                 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, GP_SCRATCH_REG, 0, 8);
3334                         }
3335                         break;
3336                 case OP_LOADI4_MEMBASE:
3337                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3338                         break;
3339                 case OP_LOADU4_MEMBASE:
3340                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3341                         break;
3342                 case OP_LOADU1_MEMBASE:
3343                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
3344                         break;
3345                 case OP_LOADI1_MEMBASE:
3346                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3347                         break;
3348                 case OP_LOADU2_MEMBASE:
3349                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
3350                         break;
3351                 case OP_LOADI2_MEMBASE:
3352                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3353                         break;
3354                 case CEE_CONV_I1:
3355                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3356                         break;
3357                 case CEE_CONV_I2:
3358                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3359                         break;
3360                 case CEE_CONV_U1:
3361                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3362                         break;
3363                 case CEE_CONV_U2:
3364                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3365                         break;
3366                 case CEE_CONV_U8:
3367                 case CEE_CONV_U:
3368                         /* Clean out the upper word */
3369                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3370                         break;
3371                 case CEE_CONV_I8:
3372                 case CEE_CONV_I:
3373                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3374                         break;
3375                 case OP_COMPARE:
3376                 case OP_LCOMPARE:
3377                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3378                         break;
3379                 case OP_COMPARE_IMM:
3380                         if (!amd64_is_imm32 (ins->inst_imm)) {
3381                                 amd64_mov_reg_imm (code, AMD64_R11, ins->inst_imm);
3382                                 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, AMD64_R11);
3383                         } else {
3384                                 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3385                         }
3386                         break;
3387                 case OP_X86_COMPARE_REG_MEMBASE:
3388                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3389                         break;
3390                 case OP_X86_TEST_NULL:
3391                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3392                         break;
3393                 case OP_AMD64_TEST_NULL:
3394                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3395                         break;
3396                 case OP_X86_ADD_MEMBASE_IMM:
3397                         /* FIXME: Make a 64 version too */
3398                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3399                         break;
3400                 case OP_X86_ADD_MEMBASE:
3401                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3402                         break;
3403                 case OP_X86_SUB_MEMBASE_IMM:
3404                         g_assert (amd64_is_imm32 (ins->inst_imm));
3405                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3406                         break;
3407                 case OP_X86_SUB_MEMBASE:
3408                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3409                         break;
3410                 case OP_X86_INC_MEMBASE:
3411                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3412                         break;
3413                 case OP_X86_INC_REG:
3414                         amd64_inc_reg_size (code, ins->dreg, 4);
3415                         break;
3416                 case OP_X86_DEC_MEMBASE:
3417                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3418                         break;
3419                 case OP_X86_DEC_REG:
3420                         amd64_dec_reg_size (code, ins->dreg, 4);
3421                         break;
3422                 case OP_X86_MUL_MEMBASE:
3423                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3424                         break;
3425                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3426                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3427                         break;
3428                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3429                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3430                         break;
3431                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3432                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3433                         break;
3434                 case CEE_BREAK:
3435                         amd64_breakpoint (code);
3436                         break;
3437                 case OP_ADDCC:
3438                 case CEE_ADD:
3439                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3440                         break;
3441                 case OP_ADC:
3442                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3443                         break;
3444                 case OP_ADD_IMM:
3445                         g_assert (amd64_is_imm32 (ins->inst_imm));
3446                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3447                         break;
3448                 case OP_ADC_IMM:
3449                         g_assert (amd64_is_imm32 (ins->inst_imm));
3450                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3451                         break;
3452                 case OP_SUBCC:
3453                 case CEE_SUB:
3454                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3455                         break;
3456                 case OP_SBB:
3457                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3458                         break;
3459                 case OP_SUB_IMM:
3460                         g_assert (amd64_is_imm32 (ins->inst_imm));
3461                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3462                         break;
3463                 case OP_SBB_IMM:
3464                         g_assert (amd64_is_imm32 (ins->inst_imm));
3465                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3466                         break;
3467                 case CEE_AND:
3468                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3469                         break;
3470                 case OP_AND_IMM:
3471                         g_assert (amd64_is_imm32 (ins->inst_imm));
3472                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3473                         break;
3474                 case CEE_MUL:
3475                 case OP_LMUL:
3476                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3477                         break;
3478                 case OP_MUL_IMM:
3479                 case OP_LMUL_IMM:
3480                         amd64_imul_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_imm);
3481                         break;
3482                 case CEE_DIV:
3483                 case OP_LDIV:
3484                         amd64_cdq (code);
3485                         amd64_div_reg (code, ins->sreg2, TRUE);
3486                         break;
3487                 case CEE_DIV_UN:
3488                 case OP_LDIV_UN:
3489                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3490                         amd64_div_reg (code, ins->sreg2, FALSE);
3491                         break;
3492                 case OP_DIV_IMM:
3493                         g_assert (amd64_is_imm32 (ins->inst_imm));
3494                         amd64_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
3495                         amd64_cdq (code);
3496                         amd64_div_reg (code, ins->sreg2, TRUE);
3497                         break;
3498                 case CEE_REM:
3499                 case OP_LREM:
3500                         amd64_cdq (code);
3501                         amd64_div_reg (code, ins->sreg2, TRUE);
3502                         break;
3503                 case CEE_REM_UN:
3504                 case OP_LREM_UN:
3505                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3506                         amd64_div_reg (code, ins->sreg2, FALSE);
3507                         break;
3508                 case OP_REM_IMM:
3509                         g_assert (amd64_is_imm32 (ins->inst_imm));
3510                         amd64_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
3511                         amd64_cdq (code);
3512                         amd64_div_reg (code, ins->sreg2, TRUE);
3513                         break;
3514                 case OP_LMUL_OVF:
3515                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3516                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3517                         break;
3518                 case CEE_OR:
3519                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3520                         break;
3521                 case OP_OR_IMM
3522 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
3523                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3524                         break;
3525                 case CEE_XOR:
3526                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3527                         break;
3528                 case OP_XOR_IMM:
3529                         g_assert (amd64_is_imm32 (ins->inst_imm));
3530                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3531                         break;
3532                 case CEE_SHL:
3533                 case OP_LSHL:
3534                         g_assert (ins->sreg2 == AMD64_RCX);
3535                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3536                         break;
3537                 case CEE_SHR:
3538                 case OP_LSHR:
3539                         g_assert (ins->sreg2 == AMD64_RCX);
3540                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3541                         break;
3542                 case OP_SHR_IMM:
3543                         g_assert (amd64_is_imm32 (ins->inst_imm));
3544                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3545                         break;
3546                 case OP_LSHR_IMM:
3547                         g_assert (amd64_is_imm32 (ins->inst_imm));
3548                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3549                         break;
3550                 case OP_SHR_UN_IMM:
3551                         g_assert (amd64_is_imm32 (ins->inst_imm));
3552                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3553                         break;
3554                 case OP_LSHR_UN_IMM:
3555                         g_assert (amd64_is_imm32 (ins->inst_imm));
3556                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3557                         break;
3558                 case CEE_SHR_UN:
3559                         g_assert (ins->sreg2 == AMD64_RCX);
3560                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3561                         break;
3562                 case OP_LSHR_UN:
3563                         g_assert (ins->sreg2 == AMD64_RCX);
3564                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3565                         break;
3566                 case OP_SHL_IMM:
3567                         g_assert (amd64_is_imm32 (ins->inst_imm));
3568                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3569                         break;
3570                 case OP_LSHL_IMM:
3571                         g_assert (amd64_is_imm32 (ins->inst_imm));
3572                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3573                         break;
3574
3575                 case OP_IADDCC:
3576                 case OP_IADD:
3577                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3578                         break;
3579                 case OP_IADC:
3580                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3581                         break;
3582                 case OP_IADD_IMM:
3583                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3584                         break;
3585                 case OP_IADC_IMM:
3586                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3587                         break;
3588                 case OP_ISUBCC:
3589                 case OP_ISUB:
3590                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3591                         break;
3592                 case OP_ISBB:
3593                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3594                         break;
3595                 case OP_ISUB_IMM:
3596                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3597                         break;
3598                 case OP_ISBB_IMM:
3599                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3600                         break;
3601                 case OP_IAND:
3602                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3603                         break;
3604                 case OP_IAND_IMM:
3605                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3606                         break;
3607                 case OP_IOR:
3608                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3609                         break;
3610                 case OP_IOR_IMM:
3611                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3612                         break;
3613                 case OP_IXOR:
3614                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3615                         break;
3616                 case OP_IXOR_IMM:
3617                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3618                         break;
3619                 case OP_INEG:
3620                         amd64_neg_reg_size (code, ins->sreg1, 4);
3621                         break;
3622                 case OP_INOT:
3623                         amd64_not_reg_size (code, ins->sreg1, 4);
3624                         break;
3625                 case OP_ISHL:
3626                         g_assert (ins->sreg2 == AMD64_RCX);
3627                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3628                         break;
3629                 case OP_ISHR:
3630                         g_assert (ins->sreg2 == AMD64_RCX);
3631                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3632                         break;
3633                 case OP_ISHR_IMM:
3634                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3635                         break;
3636                 case OP_ISHR_UN_IMM:
3637                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3638                         break;
3639                 case OP_ISHR_UN:
3640                         g_assert (ins->sreg2 == AMD64_RCX);
3641                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3642                         break;
3643                 case OP_ISHL_IMM:
3644                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3645                         break;
3646                 case OP_IMUL:
3647                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3648                         break;
3649                 case OP_IMUL_IMM:
3650                         amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, 4);
3651                         break;
3652                 case OP_IMUL_OVF:
3653                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3654                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3655                         break;
3656                 case OP_IMUL_OVF_UN:
3657                 case OP_LMUL_OVF_UN: {
3658                         /* the mul operation and the exception check should most likely be split */
3659                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3660                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3661                         /*g_assert (ins->sreg2 == X86_EAX);
3662                         g_assert (ins->dreg == X86_EAX);*/
3663                         if (ins->sreg2 == X86_EAX) {
3664                                 non_eax_reg = ins->sreg1;
3665                         } else if (ins->sreg1 == X86_EAX) {
3666                                 non_eax_reg = ins->sreg2;
3667                         } else {
3668                                 /* no need to save since we're going to store to it anyway */
3669                                 if (ins->dreg != X86_EAX) {
3670                                         saved_eax = TRUE;
3671                                         amd64_push_reg (code, X86_EAX);
3672                                 }
3673                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3674                                 non_eax_reg = ins->sreg2;
3675                         }
3676                         if (ins->dreg == X86_EDX) {
3677                                 if (!saved_eax) {
3678                                         saved_eax = TRUE;
3679                                         amd64_push_reg (code, X86_EAX);
3680                                 }
3681                         } else if (ins->dreg != X86_EAX) {
3682                                 saved_edx = TRUE;
3683                                 amd64_push_reg (code, X86_EDX);
3684                         }
3685                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3686                         /* save before the check since pop and mov don't change the flags */
3687                         if (ins->dreg != X86_EAX)
3688                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3689                         if (saved_edx)
3690                                 amd64_pop_reg (code, X86_EDX);
3691                         if (saved_eax)
3692                                 amd64_pop_reg (code, X86_EAX);
3693                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3694                         break;
3695                 }
3696                 case OP_IDIV:
3697                         amd64_cdq_size (code, 4);
3698                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3699                         break;
3700                 case OP_IDIV_UN:
3701                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3702                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3703                         break;
3704                 case OP_IDIV_IMM:
3705                         amd64_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
3706                         amd64_cdq_size (code, 4);
3707                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3708                         break;
3709                 case OP_IREM:
3710                         amd64_cdq_size (code, 4);
3711                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3712                         break;
3713                 case OP_IREM_UN:
3714                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3715                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3716                         break;
3717                 case OP_IREM_IMM:
3718                         amd64_mov_reg_imm (code, ins->sreg2, ins->inst_imm);
3719                         amd64_cdq_size (code, 4);
3720                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3721                         break;
3722
3723                 case OP_ICOMPARE:
3724                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3725                         break;
3726                 case OP_ICOMPARE_IMM:
3727                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3728                         break;
3729
3730                 case OP_IBEQ:
3731                 case OP_IBLT:
3732                 case OP_IBGT:
3733                 case OP_IBGE:
3734                 case OP_IBLE:
3735                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), TRUE);
3736                         break;
3737                 case OP_IBNE_UN:
3738                 case OP_IBLT_UN:
3739                 case OP_IBGT_UN:
3740                 case OP_IBGE_UN:
3741                 case OP_IBLE_UN:
3742                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), FALSE);
3743                         break;
3744                 case OP_COND_EXC_IOV:
3745                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
3746                                                                                 TRUE, ins->inst_p1);
3747                         break;
3748                 case OP_COND_EXC_IC:
3749                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
3750                                                                                 FALSE, ins->inst_p1);
3751                         break;
3752                 case CEE_NOT:
3753                         amd64_not_reg (code, ins->sreg1);
3754                         break;
3755                 case CEE_NEG:
3756                         amd64_neg_reg (code, ins->sreg1);
3757                         break;
3758                 case OP_SEXT_I1:
3759                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3760                         break;
3761                 case OP_SEXT_I2:
3762                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3763                         break;
3764                 case OP_ICONST:
3765                 case OP_I8CONST:
3766                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3767                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3768                         else
3769                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3770                         break;
3771                 case OP_AOTCONST:
3772                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3773                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3774                         break;
3775                 case CEE_CONV_I4:
3776                 case CEE_CONV_U4:
3777                 case OP_MOVE:
3778                 case OP_SETREG:
3779                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3780                         break;
3781                 case OP_AMD64_SET_XMMREG_R4: {
3782                         if (use_sse2) {
3783                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3784                         }
3785                         else {
3786                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
3787                                 /* ins->dreg is set to -1 by the reg allocator */
3788                                 amd64_movss_reg_membase (code, ins->unused, AMD64_RSP, -8);
3789                         }
3790                         break;
3791                 }
3792                 case OP_AMD64_SET_XMMREG_R8: {
3793                         if (use_sse2) {
3794                                 if (ins->dreg != ins->sreg1)
3795                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3796                         }
3797                         else {
3798                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
3799                                 /* ins->dreg is set to -1 by the reg allocator */
3800                                 amd64_movsd_reg_membase (code, ins->unused, AMD64_RSP, -8);
3801                         }
3802                         break;
3803                 }
3804                 case CEE_JMP: {
3805                         /*
3806                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3807                          * Keep in sync with the code in emit_epilog.
3808                          */
3809                         int pos = 0, i;
3810
3811                         /* FIXME: no tracing support... */
3812                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3813                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3814
3815                         g_assert (!cfg->method->save_lmf);
3816
3817                         code = emit_load_volatile_arguments (cfg, code);
3818
3819                         for (i = 0; i < AMD64_NREG; ++i)
3820                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3821                                         pos -= sizeof (gpointer);
3822
3823                         if (pos)
3824                                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3825
3826                         /* Pop registers in reverse order */
3827                         for (i = AMD64_NREG - 1; i > 0; --i)
3828                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3829                                         amd64_pop_reg (code, i);
3830                                 }
3831
3832                         amd64_leave (code);
3833                         offset = code - cfg->native_code;
3834                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3835                         if (mono_compile_aot)
3836                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3837                         else
3838                                 amd64_set_reg_template (code, AMD64_R11);
3839                         amd64_jump_reg (code, AMD64_R11);
3840                         break;
3841                 }
3842                 case OP_CHECK_THIS:
3843                         /* ensure ins->sreg1 is not NULL */
3844                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
3845                         break;
3846                 case OP_ARGLIST: {
3847                         amd64_lea_membase (code, AMD64_R11, AMD64_RBP, cfg->sig_cookie);
3848                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3849                         break;
3850                 }
3851                 case OP_FCALL:
3852                 case OP_LCALL:
3853                 case OP_VCALL:
3854                 case OP_VOIDCALL:
3855                 case CEE_CALL:
3856                         call = (MonoCallInst*)ins;
3857                         /*
3858                          * The AMD64 ABI forces callers to know about varargs.
3859                          */
3860                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3861                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3862                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3863                                 /*
3864                                  * Since the unmanaged calling convention doesn't contain a
3865                                  * 'vararg' entry, we have to treat every pinvoke call as a
3866                                  * potential vararg call.
3867                                  */
3868                                 guint32 nregs, i;
3869                                 nregs = 0;
3870                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3871                                         if (call->used_fregs & (1 << i))
3872                                                 nregs ++;
3873                                 if (!nregs)
3874                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3875                                 else
3876                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3877                         }
3878
3879                         if (ins->flags & MONO_INST_HAS_METHOD)
3880                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
3881                         else
3882                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
3883                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3884                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3885                         code = emit_move_return_value (cfg, ins, code);
3886                         break;
3887                 case OP_FCALL_REG:
3888                 case OP_LCALL_REG:
3889                 case OP_VCALL_REG:
3890                 case OP_VOIDCALL_REG:
3891                 case OP_CALL_REG:
3892                         call = (MonoCallInst*)ins;
3893
3894                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3895                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3896                                 ins->sreg1 = AMD64_R11;
3897                         }
3898
3899                         /*
3900                          * The AMD64 ABI forces callers to know about varargs.
3901                          */
3902                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3903                                 if (ins->sreg1 == AMD64_RAX) {
3904                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3905                                         ins->sreg1 = AMD64_R11;
3906                                 }
3907                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3908                         }
3909                         amd64_call_reg (code, ins->sreg1);
3910                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3911                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3912                         code = emit_move_return_value (cfg, ins, code);
3913                         break;
3914                 case OP_FCALL_MEMBASE:
3915                 case OP_LCALL_MEMBASE:
3916                 case OP_VCALL_MEMBASE:
3917                 case OP_VOIDCALL_MEMBASE:
3918                 case OP_CALL_MEMBASE:
3919                         call = (MonoCallInst*)ins;
3920
3921                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3922                                 /*
3923                                  * Can't use R11 because it is clobbered by the trampoline
3924                                  * code, and the reg value is needed by get_vcall_slot_addr.
3925                                  */
3926                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3927                                 ins->sreg1 = AMD64_RAX;
3928                         }
3929
3930                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3931                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3932                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3933                         code = emit_move_return_value (cfg, ins, code);
3934                         break;
3935                 case OP_OUTARG:
3936                 case OP_X86_PUSH:
3937                         amd64_push_reg (code, ins->sreg1);
3938                         break;
3939                 case OP_X86_PUSH_IMM:
3940                         g_assert (amd64_is_imm32 (ins->inst_imm));
3941                         amd64_push_imm (code, ins->inst_imm);
3942                         break;
3943                 case OP_X86_PUSH_MEMBASE:
3944                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3945                         break;
3946                 case OP_X86_PUSH_OBJ:
3947                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3948                         amd64_push_reg (code, AMD64_RDI);
3949                         amd64_push_reg (code, AMD64_RSI);
3950                         amd64_push_reg (code, AMD64_RCX);
3951                         if (ins->inst_offset)
3952                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3953                         else
3954                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3955                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3956                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3957                         amd64_cld (code);
3958                         amd64_prefix (code, X86_REP_PREFIX);
3959                         amd64_movsd (code);
3960                         amd64_pop_reg (code, AMD64_RCX);
3961                         amd64_pop_reg (code, AMD64_RSI);
3962                         amd64_pop_reg (code, AMD64_RDI);
3963                         break;
3964                 case OP_X86_LEA:
3965                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->unused);
3966                         break;
3967                 case OP_X86_LEA_MEMBASE:
3968                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3969                         break;
3970                 case OP_X86_XCHG:
3971                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3972                         break;
3973                 case OP_LOCALLOC:
3974                         /* keep alignment */
3975                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3976                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3977                         code = mono_emit_stack_alloc (code, ins);
3978                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3979                         break;
3980                 case CEE_RET:
3981                         amd64_ret (code);
3982                         break;
3983                 case CEE_THROW: {
3984                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3985                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3986                                              (gpointer)"mono_arch_throw_exception");
3987                         break;
3988                 }
3989                 case OP_RETHROW: {
3990                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3991                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3992                                              (gpointer)"mono_arch_rethrow_exception");
3993                         break;
3994                 }
3995                 case OP_CALL_HANDLER:
3996                         /* Align stack */
3997                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3998                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3999                         amd64_call_imm (code, 0);
4000                         /* Restore stack alignment */
4001                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4002                         break;
4003                 case OP_LABEL:
4004                         ins->inst_c0 = code - cfg->native_code;
4005                         break;
4006                 case CEE_BR:
4007                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4008                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4009                         //break;
4010                         if (ins->flags & MONO_INST_BRLABEL) {
4011                                 if (ins->inst_i0->inst_c0) {
4012                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
4013                                 } else {
4014                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
4015                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4016                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
4017                                                 x86_jump8 (code, 0);
4018                                         else
4019                                                 x86_jump32 (code, 0);
4020                                 }
4021                         } else {
4022                                 if (ins->inst_target_bb->native_offset) {
4023                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4024                                 } else {
4025                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4026                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4027                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
4028                                                 x86_jump8 (code, 0);
4029                                         else
4030                                                 x86_jump32 (code, 0);
4031                                 }
4032                         }
4033                         break;
4034                 case OP_BR_REG:
4035                         amd64_jump_reg (code, ins->sreg1);
4036                         break;
4037                 case OP_CEQ:
4038                 case OP_ICEQ:
4039                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4040                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4041                         break;
4042                 case OP_CLT:
4043                 case OP_ICLT:
4044                         amd64_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
4045                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4046                         break;
4047                 case OP_CLT_UN:
4048                 case OP_ICLT_UN:
4049                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4050                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4051                         break;
4052                 case OP_CGT:
4053                 case OP_ICGT:
4054                         amd64_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
4055                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4056                         break;
4057                 case OP_CGT_UN:
4058                 case OP_ICGT_UN:
4059                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4060                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4061                         break;
4062                 case OP_COND_EXC_EQ:
4063                 case OP_COND_EXC_NE_UN:
4064                 case OP_COND_EXC_LT:
4065                 case OP_COND_EXC_LT_UN:
4066                 case OP_COND_EXC_GT:
4067                 case OP_COND_EXC_GT_UN:
4068                 case OP_COND_EXC_GE:
4069                 case OP_COND_EXC_GE_UN:
4070                 case OP_COND_EXC_LE:
4071                 case OP_COND_EXC_LE_UN:
4072                 case OP_COND_EXC_OV:
4073                 case OP_COND_EXC_NO:
4074                 case OP_COND_EXC_C:
4075                 case OP_COND_EXC_NC:
4076                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4077                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4078                         break;
4079                 case CEE_BEQ:
4080                 case CEE_BNE_UN:
4081                 case CEE_BLT:
4082                 case CEE_BLT_UN:
4083                 case CEE_BGT:
4084                 case CEE_BGT_UN:
4085                 case CEE_BGE:
4086                 case CEE_BGE_UN:
4087                 case CEE_BLE:
4088                 case CEE_BLE_UN:
4089                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
4090                         break;
4091
4092                 /* floating point opcodes */
4093                 case OP_R8CONST: {
4094                         double d = *(double *)ins->inst_p0;
4095
4096                         if (use_sse2) {
4097                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4098                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4099                                 }
4100                                 else {
4101                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4102                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4103                                 }
4104                         }
4105                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
4106                                 amd64_fldz (code);
4107                         } else if (d == 1.0) {
4108                                 x86_fld1 (code);
4109                         } else {
4110                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4111                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
4112                         }
4113                         break;
4114                 }
4115                 case OP_R4CONST: {
4116                         float f = *(float *)ins->inst_p0;
4117
4118                         if (use_sse2) {
4119                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4120                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4121                                 }
4122                                 else {
4123                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4124                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4125                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4126                                 }
4127                         }
4128                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
4129                                 amd64_fldz (code);
4130                         } else if (f == 1.0) {
4131                                 x86_fld1 (code);
4132                         } else {
4133                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4134                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
4135                         }
4136                         break;
4137                 }
4138                 case OP_STORER8_MEMBASE_REG:
4139                         if (use_sse2)
4140                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4141                         else
4142                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
4143                         break;
4144                 case OP_LOADR8_SPILL_MEMBASE:
4145                         if (use_sse2)
4146                                 g_assert_not_reached ();
4147                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
4148                         amd64_fxch (code, 1);
4149                         break;
4150                 case OP_LOADR8_MEMBASE:
4151                         if (use_sse2)
4152                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4153                         else
4154                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
4155                         break;
4156                 case OP_STORER4_MEMBASE_REG:
4157                         if (use_sse2) {
4158                                 /* This requires a double->single conversion */
4159                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4160                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4161                         }
4162                         else
4163                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
4164                         break;
4165                 case OP_LOADR4_MEMBASE:
4166                         if (use_sse2) {
4167                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4168                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4169                         }
4170                         else
4171                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
4172                         break;
4173                 case CEE_CONV_R4: /* FIXME: change precision */
4174                 case CEE_CONV_R8:
4175                         if (use_sse2)
4176                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4177                         else {
4178                                 amd64_push_reg (code, ins->sreg1);
4179                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
4180                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4181                         }
4182                         break;
4183                 case CEE_CONV_R_UN:
4184                         /* Emulated */
4185                         g_assert_not_reached ();
4186                         break;
4187                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4188                 case OP_LCONV_TO_R8:
4189                         if (use_sse2)
4190                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4191                         else {
4192                                 amd64_push_reg (code, ins->sreg1);
4193                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
4194                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4195                         }
4196                         break;
4197                 case OP_X86_FP_LOAD_I8:
4198                         if (use_sse2)
4199                                 g_assert_not_reached ();
4200                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
4201                         break;
4202                 case OP_X86_FP_LOAD_I4:
4203                         if (use_sse2)
4204                                 g_assert_not_reached ();
4205                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
4206                         break;
4207                 case OP_FCONV_TO_I1:
4208                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4209                         break;
4210                 case OP_FCONV_TO_U1:
4211                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4212                         break;
4213                 case OP_FCONV_TO_I2:
4214                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4215                         break;
4216                 case OP_FCONV_TO_U2:
4217                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4218                         break;
4219                 case OP_FCONV_TO_I4:
4220                 case OP_FCONV_TO_I:
4221                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4222                         break;
4223                 case OP_FCONV_TO_I8:
4224                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4225                         break;
4226                 case OP_LCONV_TO_R_UN: {
4227                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
4228                         guint8 *br;
4229
4230                         if (use_sse2)
4231                                 g_assert_not_reached ();
4232
4233                         /* load 64bit integer to FP stack */
4234                         amd64_push_imm (code, 0);
4235                         amd64_push_reg (code, ins->sreg2);
4236                         amd64_push_reg (code, ins->sreg1);
4237                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
4238                         /* store as 80bit FP value */
4239                         x86_fst80_membase (code, AMD64_RSP, 0);
4240
4241                         /* test if lreg is negative */
4242                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
4243                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
4244
4245                         /* add correction constant mn */
4246                         x86_fld80_mem (code, mn);
4247                         x86_fld80_membase (code, AMD64_RSP, 0);
4248                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
4249                         x86_fst80_membase (code, AMD64_RSP, 0);
4250
4251                         amd64_patch (br, code);
4252
4253                         x86_fld80_membase (code, AMD64_RSP, 0);
4254                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
4255
4256                         break;
4257                 }
4258                 case OP_LCONV_TO_OVF_I: {
4259                         guint8 *br [3], *label [1];
4260
4261                         if (use_sse2)
4262                                 g_assert_not_reached ();
4263
4264                         /*
4265                          * Valid ints: 0xffffffff:8000000 to 00000000:0x7f000000
4266                          */
4267                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4268
4269                         /* If the low word top bit is set, see if we are negative */
4270                         br [0] = code; x86_branch8 (code, X86_CC_LT, 0, TRUE);
4271                         /* We are not negative (no top bit set, check for our top word to be zero */
4272                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
4273                         br [1] = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
4274                         label [0] = code;
4275
4276                         /* throw exception */
4277                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_EXC, "OverflowException");
4278                         x86_jump32 (code, 0);
4279
4280                         amd64_patch (br [0], code);
4281                         /* our top bit is set, check that top word is 0xfffffff */
4282                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0xffffffff);
4283
4284                         amd64_patch (br [1], code);
4285                         /* nope, emit exception */
4286                         br [2] = code; x86_branch8 (code, X86_CC_NE, 0, TRUE);
4287                         amd64_patch (br [2], label [0]);
4288
4289                         if (ins->dreg != ins->sreg1)
4290                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
4291                         break;
4292                 }
4293                 case CEE_CONV_OVF_U4:
4294                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4295                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4296                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4297                         break;
4298                 case CEE_CONV_OVF_I4_UN:
4299                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4300                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4301                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4302                         break;
4303                 case OP_FMOVE:
4304                         if (use_sse2 && (ins->dreg != ins->sreg1))
4305                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4306                         break;
4307                 case OP_FADD:
4308                         if (use_sse2)
4309                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4310                         else
4311                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
4312                         break;
4313                 case OP_FSUB:
4314                         if (use_sse2)
4315                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4316                         else
4317                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
4318                         break;
4319                 case OP_FMUL:
4320                         if (use_sse2)
4321                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4322                         else
4323                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
4324                         break;
4325                 case OP_FDIV:
4326                         if (use_sse2)
4327                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4328                         else
4329                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
4330                         break;
4331                 case OP_FNEG:
4332                         if (use_sse2) {
4333                                 amd64_mov_reg_imm_size (code, AMD64_R11, 0x8000000000000000, 8);
4334                                 amd64_push_reg (code, AMD64_R11);
4335                                 amd64_push_reg (code, AMD64_R11);
4336                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RSP, 0);
4337                         }
4338                         else
4339                                 amd64_fchs (code);
4340                         break;
4341                 case OP_SIN:
4342                         if (use_sse2) {
4343                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4344                         }
4345                         else {
4346                                 amd64_fsin (code);
4347                                 amd64_fldz (code);
4348                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
4349                         }
4350                         break;
4351                 case OP_COS:
4352                         if (use_sse2) {
4353                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4354                         }
4355                         else {
4356                                 amd64_fcos (code);
4357                                 amd64_fldz (code);
4358                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
4359                         }
4360                         break;
4361                 case OP_ABS:
4362                         if (use_sse2) {
4363                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
4364                         }
4365                         else
4366                                 amd64_fabs (code);
4367                         break;
4368                 case OP_TAN: {
4369                         /*
4370                          * it really doesn't make sense to inline all this code,
4371                          * it's here just to show that things may not be as simple
4372                          * as they appear.
4373                          */
4374                         guchar *check_pos, *end_tan, *pop_jump;
4375                         if (use_sse2)
4376                                 g_assert_not_reached ();
4377                         amd64_push_reg (code, AMD64_RAX);
4378                         amd64_fptan (code);
4379                         amd64_fnstsw (code);
4380                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
4381                         check_pos = code;
4382                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
4383                         amd64_fstp (code, 0); /* pop the 1.0 */
4384                         end_tan = code;
4385                         x86_jump8 (code, 0);
4386                         amd64_fldpi (code);
4387                         amd64_fp_op (code, X86_FADD, 0);
4388                         amd64_fxch (code, 1);
4389                         x86_fprem1 (code);
4390                         amd64_fstsw (code);
4391                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
4392                         pop_jump = code;
4393                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
4394                         amd64_fstp (code, 1);
4395                         amd64_fptan (code);
4396                         amd64_patch (pop_jump, code);
4397                         amd64_fstp (code, 0); /* pop the 1.0 */
4398                         amd64_patch (check_pos, code);
4399                         amd64_patch (end_tan, code);
4400                         amd64_fldz (code);
4401                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
4402                         amd64_pop_reg (code, AMD64_RAX);
4403                         break;
4404                 }
4405                 case OP_ATAN:
4406                         if (use_sse2)
4407                                 g_assert_not_reached ();
4408                         x86_fld1 (code);
4409                         amd64_fpatan (code);
4410                         amd64_fldz (code);
4411                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
4412                         break;
4413                 case OP_SQRT:
4414                         if (use_sse2) {
4415                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4416                         }
4417                         else
4418                                 amd64_fsqrt (code);
4419                         break;
4420                 case OP_X86_FPOP:
4421                         if (!use_sse2)
4422                                 amd64_fstp (code, 0);
4423                         break;
4424                 case OP_FREM: {
4425                         guint8 *l1, *l2;
4426
4427                         if (use_sse2)
4428                                 g_assert_not_reached ();
4429                         amd64_push_reg (code, AMD64_RAX);
4430                         /* we need to exchange ST(0) with ST(1) */
4431                         amd64_fxch (code, 1);
4432
4433                         /* this requires a loop, because fprem somtimes
4434                          * returns a partial remainder */
4435                         l1 = code;
4436                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
4437                         /* x86_fprem1 (code); */
4438                         amd64_fprem (code);
4439                         amd64_fnstsw (code);
4440                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
4441                         l2 = code + 2;
4442                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
4443
4444                         /* pop result */
4445                         amd64_fstp (code, 1);
4446
4447                         amd64_pop_reg (code, AMD64_RAX);
4448                         break;
4449                 }
4450                 case OP_FCOMPARE:
4451                         if (use_sse2) {
4452                                 /*
4453                                  * The two arguments are swapped because the fbranch instructions
4454                                  * depend on this for the non-sse case to work.
4455                                  */
4456                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4457                                 break;
4458                         }
4459                         if (cfg->opt & MONO_OPT_FCMOV) {
4460                                 amd64_fcomip (code, 1);
4461                                 amd64_fstp (code, 0);
4462                                 break;
4463                         }
4464                         /* this overwrites EAX */
4465                         EMIT_FPCOMPARE(code);
4466                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
4467                         break;
4468                 case OP_FCEQ:
4469                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4470                                 /* zeroing the register at the start results in
4471                                  * shorter and faster code (we can also remove the widening op)
4472                                  */
4473                                 guchar *unordered_check;
4474                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4475
4476                                 if (use_sse2)
4477                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4478                                 else {
4479                                         amd64_fcomip (code, 1);
4480                                         amd64_fstp (code, 0);
4481                                 }
4482                                 unordered_check = code;
4483                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4484                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4485                                 amd64_patch (unordered_check, code);
4486                                 break;
4487                         }
4488                         if (ins->dreg != AMD64_RAX)
4489                                 amd64_push_reg (code, AMD64_RAX);
4490
4491                         EMIT_FPCOMPARE(code);
4492                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
4493                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
4494                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4495                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4496
4497                         if (ins->dreg != AMD64_RAX)
4498                                 amd64_pop_reg (code, AMD64_RAX);
4499                         break;
4500                 case OP_FCLT:
4501                 case OP_FCLT_UN:
4502                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4503                                 /* zeroing the register at the start results in
4504                                  * shorter and faster code (we can also remove the widening op)
4505                                  */
4506                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4507                                 if (use_sse2)
4508                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4509                                 else {
4510                                         amd64_fcomip (code, 1);
4511                                         amd64_fstp (code, 0);
4512                                 }
4513                                 if (ins->opcode == OP_FCLT_UN) {
4514                                         guchar *unordered_check = code;
4515                                         guchar *jump_to_end;
4516                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4517                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4518                                         jump_to_end = code;
4519                                         x86_jump8 (code, 0);
4520                                         amd64_patch (unordered_check, code);
4521                                         amd64_inc_reg (code, ins->dreg);
4522                                         amd64_patch (jump_to_end, code);
4523                                 } else {
4524                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4525                                 }
4526                                 break;
4527                         }
4528                         if (ins->dreg != AMD64_RAX)
4529                                 amd64_push_reg (code, AMD64_RAX);
4530
4531                         EMIT_FPCOMPARE(code);
4532                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
4533                         if (ins->opcode == OP_FCLT_UN) {
4534                                 guchar *is_not_zero_check, *end_jump;
4535                                 is_not_zero_check = code;
4536                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4537                                 end_jump = code;
4538                                 x86_jump8 (code, 0);
4539                                 amd64_patch (is_not_zero_check, code);
4540                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4541
4542                                 amd64_patch (end_jump, code);
4543                         }
4544                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4545                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4546
4547                         if (ins->dreg != AMD64_RAX)
4548                                 amd64_pop_reg (code, AMD64_RAX);
4549                         break;
4550                 case OP_FCGT:
4551                 case OP_FCGT_UN:
4552                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4553                                 /* zeroing the register at the start results in
4554                                  * shorter and faster code (we can also remove the widening op)
4555                                  */
4556                                 guchar *unordered_check;
4557                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4558                                 if (use_sse2)
4559                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4560                                 else {
4561                                         amd64_fcomip (code, 1);
4562                                         amd64_fstp (code, 0);
4563                                 }
4564                                 if (ins->opcode == OP_FCGT) {
4565                                         unordered_check = code;
4566                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4567                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4568                                         amd64_patch (unordered_check, code);
4569                                 } else {
4570                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4571                                 }
4572                                 break;
4573                         }
4574                         if (ins->dreg != AMD64_RAX)
4575                                 amd64_push_reg (code, AMD64_RAX);
4576
4577                         EMIT_FPCOMPARE(code);
4578                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
4579                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4580                         if (ins->opcode == OP_FCGT_UN) {
4581                                 guchar *is_not_zero_check, *end_jump;
4582                                 is_not_zero_check = code;
4583                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4584                                 end_jump = code;
4585                                 x86_jump8 (code, 0);
4586                                 amd64_patch (is_not_zero_check, code);
4587                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4588
4589                                 amd64_patch (end_jump, code);
4590                         }
4591                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
4592                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4593
4594                         if (ins->dreg != AMD64_RAX)
4595                                 amd64_pop_reg (code, AMD64_RAX);
4596                         break;
4597                 case OP_FCLT_MEMBASE:
4598                 case OP_FCGT_MEMBASE:
4599                 case OP_FCLT_UN_MEMBASE:
4600                 case OP_FCGT_UN_MEMBASE:
4601                 case OP_FCEQ_MEMBASE: {
4602                         guchar *unordered_check, *jump_to_end;
4603                         int x86_cond;
4604                         g_assert (use_sse2);
4605
4606                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4607                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4608
4609                         switch (ins->opcode) {
4610                         case OP_FCEQ_MEMBASE:
4611                                 x86_cond = X86_CC_EQ;
4612                                 break;
4613                         case OP_FCLT_MEMBASE:
4614                         case OP_FCLT_UN_MEMBASE:
4615                                 x86_cond = X86_CC_LT;
4616                                 break;
4617                         case OP_FCGT_MEMBASE:
4618                         case OP_FCGT_UN_MEMBASE:
4619                                 x86_cond = X86_CC_GT;
4620                                 break;
4621                         default:
4622                                 g_assert_not_reached ();
4623                         }
4624
4625                         unordered_check = code;
4626                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4627                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4628
4629                         switch (ins->opcode) {
4630                         case OP_FCEQ_MEMBASE:
4631                         case OP_FCLT_MEMBASE:
4632                         case OP_FCGT_MEMBASE:
4633                                 amd64_patch (unordered_check, code);
4634                                 break;
4635                         case OP_FCLT_UN_MEMBASE:
4636                         case OP_FCGT_UN_MEMBASE:
4637                                 jump_to_end = code;
4638                                 x86_jump8 (code, 0);
4639                                 amd64_patch (unordered_check, code);
4640                                 amd64_inc_reg (code, ins->dreg);
4641                                 amd64_patch (jump_to_end, code);
4642                                 break;
4643                         default:
4644                                 break;
4645                         }
4646                         break;
4647                 }
4648                 case OP_FBEQ:
4649                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4650                                 guchar *jump = code;
4651                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
4652                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4653                                 amd64_patch (jump, code);
4654                                 break;
4655                         }
4656                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
4657                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
4658                         break;
4659                 case OP_FBNE_UN:
4660                         /* Branch if C013 != 100 */
4661                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4662                                 /* branch if !ZF or (PF|CF) */
4663                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4664                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4665                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4666                                 break;
4667                         }
4668                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
4669                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4670                         break;
4671                 case OP_FBLT:
4672                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4673                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4674                                 break;
4675                         }
4676                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4677                         break;
4678                 case OP_FBLT_UN:
4679                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4680                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4681                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4682                                 break;
4683                         }
4684                         if (ins->opcode == OP_FBLT_UN) {
4685                                 guchar *is_not_zero_check, *end_jump;
4686                                 is_not_zero_check = code;
4687                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4688                                 end_jump = code;
4689                                 x86_jump8 (code, 0);
4690                                 amd64_patch (is_not_zero_check, code);
4691                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4692
4693                                 amd64_patch (end_jump, code);
4694                         }
4695                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4696                         break;
4697                 case OP_FBGT:
4698                 case OP_FBGT_UN:
4699                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4700                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4701                                 break;
4702                         }
4703                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4704                         if (ins->opcode == OP_FBGT_UN) {
4705                                 guchar *is_not_zero_check, *end_jump;
4706                                 is_not_zero_check = code;
4707                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
4708                                 end_jump = code;
4709                                 x86_jump8 (code, 0);
4710                                 amd64_patch (is_not_zero_check, code);
4711                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
4712
4713                                 amd64_patch (end_jump, code);
4714                         }
4715                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4716                         break;
4717                 case OP_FBGE:
4718                         /* Branch if C013 == 100 or 001 */
4719                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4720                                 guchar *br1;
4721
4722                                 /* skip branch if C1=1 */
4723                                 br1 = code;
4724                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4725                                 /* branch if (C0 | C3) = 1 */
4726                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4727                                 amd64_patch (br1, code);
4728                                 break;
4729                         }
4730                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4731                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4732                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
4733                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4734                         break;
4735                 case OP_FBGE_UN:
4736                         /* Branch if C013 == 000 */
4737                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4738                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4739                                 break;
4740                         }
4741                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4742                         break;
4743                 case OP_FBLE:
4744                         /* Branch if C013=000 or 100 */
4745                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4746                                 guchar *br1;
4747
4748                                 /* skip branch if C1=1 */
4749                                 br1 = code;
4750                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4751                                 /* branch if C0=0 */
4752                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4753                                 amd64_patch (br1, code);
4754                                 break;
4755                         }
4756                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
4757                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4758                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4759                         break;
4760                 case OP_FBLE_UN:
4761                         /* Branch if C013 != 001 */
4762                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
4763                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4764                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4765                                 break;
4766                         }
4767                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4768                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4769                         break;
4770                 case CEE_CKFINITE: {
4771                         if (use_sse2) {
4772                                 /* Transfer value to the fp stack */
4773                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4774                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4775                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4776                         }
4777                         amd64_push_reg (code, AMD64_RAX);
4778                         amd64_fxam (code);
4779                         amd64_fnstsw (code);
4780                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4781                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4782                         amd64_pop_reg (code, AMD64_RAX);
4783                         if (use_sse2) {
4784                                 amd64_fstp (code, 0);
4785                         }
4786                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4787                         if (use_sse2)
4788                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4789                         break;
4790                 }
4791                 case OP_TLS_GET: {
4792                         x86_prefix (code, X86_FS_PREFIX);
4793                         amd64_mov_reg_mem (code, ins->dreg, ins->inst_offset, 8);
4794                         break;
4795                 }
4796                 case OP_ATOMIC_ADD_I4:
4797                 case OP_ATOMIC_ADD_I8: {
4798                         int dreg = ins->dreg;
4799                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4800
4801                         if (dreg == ins->inst_basereg)
4802                                 dreg = AMD64_R11;
4803
4804                         if (dreg != ins->sreg2)
4805                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4806
4807                         x86_prefix (code, X86_LOCK_PREFIX);
4808                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4809
4810                         if (dreg != ins->dreg)
4811                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4812
4813                         break;
4814                 }
4815                 case OP_ATOMIC_ADD_NEW_I4:
4816                 case OP_ATOMIC_ADD_NEW_I8: {
4817                         int dreg = ins->dreg;
4818                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4819
4820                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4821                                 dreg = AMD64_R11;
4822
4823                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4824                         amd64_prefix (code, X86_LOCK_PREFIX);
4825                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4826                         /* dreg contains the old value, add with sreg2 value */
4827                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4828
4829                         if (ins->dreg != dreg)
4830                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4831
4832                         break;
4833                 }
4834                 case OP_ATOMIC_EXCHANGE_I4:
4835                 case OP_ATOMIC_EXCHANGE_I8: {
4836                         guchar *br[2];
4837                         int sreg2 = ins->sreg2;
4838                         int breg = ins->inst_basereg;
4839                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
4840
4841                         /*
4842                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
4843                          * an explanation of how this works.
4844                          */
4845
4846                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4847                          * hack to overcome limits in x86 reg allocator
4848                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4849                          */
4850                         if (ins->dreg != AMD64_RAX)
4851                                 amd64_push_reg (code, AMD64_RAX);
4852
4853                         /* We need the EAX reg for the cmpxchg */
4854                         if (ins->sreg2 == AMD64_RAX) {
4855                                 amd64_push_reg (code, AMD64_RDX);
4856                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4857                                 sreg2 = AMD64_RDX;
4858                         }
4859
4860                         if (breg == AMD64_RAX) {
4861                                 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, size);
4862                                 breg = AMD64_R11;
4863                         }
4864
4865                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4866
4867                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4868                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4869                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4870                         amd64_patch (br [1], br [0]);
4871
4872                         if (ins->dreg != AMD64_RAX) {
4873                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4874                                 amd64_pop_reg (code, AMD64_RAX);
4875                         }
4876
4877                         if (ins->sreg2 != sreg2)
4878                                 amd64_pop_reg (code, AMD64_RDX);
4879
4880                         break;
4881                 }
4882                 default:
4883                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4884                         g_assert_not_reached ();
4885                 }
4886
4887                 if ((code - cfg->native_code - offset) > max_len) {
4888                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4889                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4890                         g_assert_not_reached ();
4891                 }
4892
4893                 cpos += max_len;
4894
4895                 last_ins = ins;
4896                 last_offset = offset;
4897
4898                 ins = ins->next;
4899         }
4900
4901         cfg->code_len = code - cfg->native_code;
4902 }
4903
4904 void
4905 mono_arch_register_lowlevel_calls (void)
4906 {
4907 }
4908
4909 void
4910 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4911 {
4912         MonoJumpInfo *patch_info;
4913
4914         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4915                 unsigned char *ip = patch_info->ip.i + code;
4916                 const unsigned char *target;
4917
4918                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4919
4920                 if (mono_compile_aot) {
4921                         switch (patch_info->type) {
4922                         case MONO_PATCH_INFO_BB:
4923                         case MONO_PATCH_INFO_LABEL:
4924                                 break;
4925                         default: {
4926                                 /* Just to make code run at aot time work */
4927                                 const unsigned char **tmp;
4928
4929                                 mono_domain_lock (domain);
4930                                 tmp = mono_code_manager_reserve (domain->code_mp, sizeof (gpointer));
4931                                 mono_domain_unlock (domain);
4932
4933                                 *tmp = target;
4934                                 target = (const unsigned char*)(guint64)((guint8*)tmp - (guint8*)ip);
4935                                 break;
4936                         }
4937                         }
4938                 }
4939
4940                 switch (patch_info->type) {
4941                 case MONO_PATCH_INFO_NONE:
4942                         continue;
4943                 case MONO_PATCH_INFO_CLASS_INIT: {
4944                         /* Might already been changed to a nop */
4945                         guint8* ip2 = ip;
4946                         if (mono_compile_aot)
4947                                 amd64_call_membase (ip2, AMD64_RIP, 0);
4948                         else {
4949                                 amd64_call_code (ip2, 0);
4950                         }
4951                         break;
4952                 }
4953                 case MONO_PATCH_INFO_METHOD_REL:
4954                 case MONO_PATCH_INFO_R8:
4955                 case MONO_PATCH_INFO_R4:
4956                         g_assert_not_reached ();
4957                         continue;
4958                 case MONO_PATCH_INFO_BB:
4959                         break;
4960                 default:
4961                         break;
4962                 }
4963                 amd64_patch (ip, (gpointer)target);
4964         }
4965 }
4966
4967 guint8 *
4968 mono_arch_emit_prolog (MonoCompile *cfg)
4969 {
4970         MonoMethod *method = cfg->method;
4971         MonoBasicBlock *bb;
4972         MonoMethodSignature *sig;
4973         MonoInst *inst;
4974         int alloc_size, pos, max_offset, i, quad;
4975         guint8 *code;
4976         CallInfo *cinfo;
4977
4978         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
4979         code = cfg->native_code = g_malloc (cfg->code_size);
4980
4981         amd64_push_reg (code, AMD64_RBP);
4982         amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4983
4984         /* Stack alignment check */
4985 #if 0
4986         {
4987                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4988                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4989                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4990                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4991                 amd64_breakpoint (code);
4992         }
4993 #endif
4994
4995         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4996         pos = 0;
4997
4998         if (method->save_lmf) {
4999                 gint32 lmf_offset;
5000
5001                 pos = ALIGN_TO (pos + sizeof (MonoLMF), 16);
5002
5003                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, pos);
5004
5005                 lmf_offset = - cfg->arch.lmf_offset;
5006
5007                 /* Save ip */
5008                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
5009                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
5010                 /* Save fp */
5011                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
5012                 /* Save method */
5013                 /* FIXME: add a relocation for this */
5014                 if (IS_IMM32 (cfg->method))
5015                         amd64_mov_membase_imm (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), (guint64)cfg->method, 8);
5016                 else {
5017                         amd64_mov_reg_imm (code, AMD64_R11, cfg->method);
5018                         amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, method), AMD64_R11, 8);
5019                 }
5020                 /* Save callee saved regs */
5021                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
5022                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
5023                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
5024                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
5025                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
5026         } else {
5027
5028                 for (i = 0; i < AMD64_NREG; ++i)
5029                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5030                                 amd64_push_reg (code, i);
5031                                 pos += sizeof (gpointer);
5032                         }
5033         }
5034
5035         alloc_size -= pos;
5036
5037         if (alloc_size) {
5038                 /* See mono_emit_stack_alloc */
5039 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5040                 guint32 remaining_size = alloc_size;
5041                 while (remaining_size >= 0x1000) {
5042                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5043                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5044                         remaining_size -= 0x1000;
5045                 }
5046                 if (remaining_size)
5047                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5048 #else
5049                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5050 #endif
5051         }
5052
5053         /* compute max_offset in order to use short forward jumps */
5054         max_offset = 0;
5055         if (cfg->opt & MONO_OPT_BRANCH) {
5056                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5057                         MonoInst *ins = bb->code;
5058                         bb->max_offset = max_offset;
5059
5060                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5061                                 max_offset += 6;
5062                         /* max alignment for loops */
5063                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5064                                 max_offset += LOOP_ALIGNMENT;
5065
5066                         while (ins) {
5067                                 if (ins->opcode == OP_LABEL)
5068                                         ins->inst_c1 = max_offset;
5069
5070                                 max_offset += ((guint8 *)ins_spec [ins->opcode])[MONO_INST_LEN];
5071                                 ins = ins->next;
5072                         }
5073                 }
5074         }
5075
5076         sig = mono_method_signature (method);
5077         pos = 0;
5078
5079         cinfo = get_call_info (sig, FALSE);
5080
5081         if (sig->ret->type != MONO_TYPE_VOID) {
5082                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
5083                         /* Save volatile arguments to the stack */
5084                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
5085                 }
5086         }
5087
5088         /* Keep this in sync with emit_load_volatile_arguments */
5089         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5090                 ArgInfo *ainfo = cinfo->args + i;
5091                 gint32 stack_offset;
5092                 MonoType *arg_type;
5093                 inst = cfg->varinfo [i];
5094
5095                 if (sig->hasthis && (i == 0))
5096                         arg_type = &mono_defaults.object_class->byval_arg;
5097                 else
5098                         arg_type = sig->params [i - sig->hasthis];
5099
5100                 stack_offset = ainfo->offset + ARGS_OFFSET;
5101
5102                 /* Save volatile arguments to the stack */
5103                 if (inst->opcode != OP_REGVAR) {
5104                         switch (ainfo->storage) {
5105                         case ArgInIReg: {
5106                                 guint32 size = 8;
5107
5108                                 /* FIXME: I1 etc */
5109                                 /*
5110                                 if (stack_offset & 0x1)
5111                                         size = 1;
5112                                 else if (stack_offset & 0x2)
5113                                         size = 2;
5114                                 else if (stack_offset & 0x4)
5115                                         size = 4;
5116                                 else
5117                                         size = 8;
5118                                 */
5119                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
5120                                 break;
5121                         }
5122                         case ArgInFloatSSEReg:
5123                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
5124                                 break;
5125                         case ArgInDoubleSSEReg:
5126                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
5127                                 break;
5128                         case ArgValuetypeInReg:
5129                                 for (quad = 0; quad < 2; quad ++) {
5130                                         switch (ainfo->pair_storage [quad]) {
5131                                         case ArgInIReg:
5132                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5133                                                 break;
5134                                         case ArgInFloatSSEReg:
5135                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5136                                                 break;
5137                                         case ArgInDoubleSSEReg:
5138                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5139                                                 break;
5140                                         case ArgNone:
5141                                                 break;
5142                                         default:
5143                                                 g_assert_not_reached ();
5144                                         }
5145                                 }
5146                                 break;
5147                         default:
5148                                 break;
5149                         }
5150                 }
5151
5152                 if (inst->opcode == OP_REGVAR) {
5153                         /* Argument allocated to (non-volatile) register */
5154                         switch (ainfo->storage) {
5155                         case ArgInIReg:
5156                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
5157                                 break;
5158                         case ArgOnStack:
5159                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5160                                 break;
5161                         default:
5162                                 g_assert_not_reached ();
5163                         }
5164                 }
5165         }
5166
5167         if (method->save_lmf) {
5168                 gint32 lmf_offset;
5169
5170                 if (lmf_tls_offset != -1) {
5171                         /* Load lmf quicky using the FS register */
5172                         x86_prefix (code, X86_FS_PREFIX);
5173                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5174                 }
5175                 else {
5176                         /*
5177                          * The call might clobber argument registers, but they are already
5178                          * saved to the stack/global regs.
5179                          */
5180
5181                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5182                                                                  (gpointer)"mono_get_lmf_addr");
5183                 }
5184
5185                 lmf_offset = - cfg->arch.lmf_offset;
5186
5187                 /* Save lmf_addr */
5188                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5189                 /* Save previous_lmf */
5190                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5191                 amd64_mov_membase_reg (code, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5192                 /* Set new lmf */
5193                 amd64_lea_membase (code, AMD64_R11, AMD64_RBP, lmf_offset);
5194                 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5195         }
5196
5197
5198         g_free (cinfo);
5199
5200         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5201                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5202
5203         cfg->code_len = code - cfg->native_code;
5204
5205         g_assert (cfg->code_len < cfg->code_size);
5206
5207         return code;
5208 }
5209
5210 void
5211 mono_arch_emit_epilog (MonoCompile *cfg)
5212 {
5213         MonoMethod *method = cfg->method;
5214         int quad, pos, i;
5215         guint8 *code;
5216         int max_epilog_size = 16;
5217         CallInfo *cinfo;
5218
5219         if (cfg->method->save_lmf)
5220                 max_epilog_size += 256;
5221
5222         if (mono_jit_trace_calls != NULL)
5223                 max_epilog_size += 50;
5224
5225         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5226                 max_epilog_size += 50;
5227
5228         max_epilog_size += (AMD64_NREG * 2);
5229
5230         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5231                 cfg->code_size *= 2;
5232                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5233                 mono_jit_stats.code_reallocs++;
5234         }
5235
5236         code = cfg->native_code + cfg->code_len;
5237
5238         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5239                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5240
5241         /* the code restoring the registers must be kept in sync with CEE_JMP */
5242         pos = 0;
5243
5244         if (method->save_lmf) {
5245                 gint32 lmf_offset = - cfg->arch.lmf_offset;
5246
5247                 /* Restore previous lmf */
5248                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5249                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5250                 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5251
5252                 /* Restore caller saved regs */
5253                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5254                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5255                 }
5256                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5257                         amd64_mov_reg_membase (code, AMD64_R12, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5258                 }
5259                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5260                         amd64_mov_reg_membase (code, AMD64_R13, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5261                 }
5262                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5263                         amd64_mov_reg_membase (code, AMD64_R14, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5264                 }
5265                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5266                         amd64_mov_reg_membase (code, AMD64_R15, AMD64_RBP, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5267                 }
5268         } else {
5269
5270                 for (i = 0; i < AMD64_NREG; ++i)
5271                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5272                                 pos -= sizeof (gpointer);
5273
5274                 if (pos) {
5275                         if (pos == - sizeof (gpointer)) {
5276                                 /* Only one register, so avoid lea */
5277                                 for (i = AMD64_NREG - 1; i > 0; --i)
5278                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5279                                                 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5280                                         }
5281                         }
5282                         else {
5283                                 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5284
5285                                 /* Pop registers in reverse order */
5286                                 for (i = AMD64_NREG - 1; i > 0; --i)
5287                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5288                                                 amd64_pop_reg (code, i);
5289                                         }
5290                         }
5291                 }
5292         }
5293
5294         /* Load returned vtypes into registers if needed */
5295         cinfo = get_call_info (mono_method_signature (method), FALSE);
5296         if (cinfo->ret.storage == ArgValuetypeInReg) {
5297                 ArgInfo *ainfo = &cinfo->ret;
5298                 MonoInst *inst = cfg->ret;
5299
5300                 for (quad = 0; quad < 2; quad ++) {
5301                         switch (ainfo->pair_storage [quad]) {
5302                         case ArgInIReg:
5303                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5304                                 break;
5305                         case ArgInFloatSSEReg:
5306                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5307                                 break;
5308                         case ArgInDoubleSSEReg:
5309                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5310                                 break;
5311                         case ArgNone:
5312                                 break;
5313                         default:
5314                                 g_assert_not_reached ();
5315                         }
5316                 }
5317         }
5318         g_free (cinfo);
5319
5320         amd64_leave (code);
5321         amd64_ret (code);
5322
5323         cfg->code_len = code - cfg->native_code;
5324
5325         g_assert (cfg->code_len < cfg->code_size);
5326
5327 }
5328
5329 void
5330 mono_arch_emit_exceptions (MonoCompile *cfg)
5331 {
5332         MonoJumpInfo *patch_info;
5333         int nthrows, i;
5334         guint8 *code;
5335         MonoClass *exc_classes [16];
5336         guint8 *exc_throw_start [16], *exc_throw_end [16];
5337         guint32 code_size = 0;
5338
5339         /* Compute needed space */
5340         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5341                 if (patch_info->type == MONO_PATCH_INFO_EXC)
5342                         code_size += 40;
5343                 if (patch_info->type == MONO_PATCH_INFO_R8)
5344                         code_size += 8 + 7; /* sizeof (double) + alignment */
5345                 if (patch_info->type == MONO_PATCH_INFO_R4)
5346                         code_size += 4 + 7; /* sizeof (float) + alignment */
5347         }
5348
5349         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5350                 cfg->code_size *= 2;
5351                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5352                 mono_jit_stats.code_reallocs++;
5353         }
5354
5355         code = cfg->native_code + cfg->code_len;
5356
5357         /* add code to raise exceptions */
5358         nthrows = 0;
5359         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5360                 switch (patch_info->type) {
5361                 case MONO_PATCH_INFO_EXC: {
5362                         MonoClass *exc_class;
5363                         guint8 *buf, *buf2;
5364                         guint32 throw_ip;
5365
5366                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
5367
5368                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5369                         g_assert (exc_class);
5370                         throw_ip = patch_info->ip.i;
5371
5372                         //x86_breakpoint (code);
5373                         /* Find a throw sequence for the same exception class */
5374                         for (i = 0; i < nthrows; ++i)
5375                                 if (exc_classes [i] == exc_class)
5376                                         break;
5377                         if (i < nthrows) {
5378                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5379                                 x86_jump_code (code, exc_throw_start [i]);
5380                                 patch_info->type = MONO_PATCH_INFO_NONE;
5381                         }
5382                         else {
5383                                 buf = code;
5384                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
5385                                 buf2 = code;
5386
5387                                 if (nthrows < 16) {
5388                                         exc_classes [nthrows] = exc_class;
5389                                         exc_throw_start [nthrows] = code;
5390                                 }
5391
5392                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
5393                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
5394                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
5395                                 patch_info->ip.i = code - cfg->native_code;
5396
5397                                 if (mono_compile_aot) {
5398                                         amd64_mov_reg_membase (code, GP_SCRATCH_REG, AMD64_RIP, 0, 8);
5399                                         amd64_call_reg (code, GP_SCRATCH_REG);
5400                                 } else {
5401                                         /* The callee is in memory allocated using the code manager */
5402                                         amd64_call_code (code, 0);
5403                                 }
5404
5405                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
5406                                 while (buf < buf2)
5407                                         x86_nop (buf);
5408
5409                                 if (nthrows < 16) {
5410                                         exc_throw_end [nthrows] = code;
5411                                         nthrows ++;
5412                                 }
5413                         }
5414                         break;
5415                 }
5416                 default:
5417                         /* do nothing */
5418                         break;
5419                 }
5420         }
5421
5422         /* Handle relocations with RIP relative addressing */
5423         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5424                 gboolean remove = FALSE;
5425
5426                 switch (patch_info->type) {
5427                 case MONO_PATCH_INFO_R8: {
5428                         guint8 *pos;
5429
5430                         code = (guint8*)ALIGN_TO (code, 8);
5431
5432                         pos = cfg->native_code + patch_info->ip.i;
5433
5434                         *(double*)code = *(double*)patch_info->data.target;
5435
5436                         if (use_sse2)
5437                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5438                         else
5439                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
5440                         code += 8;
5441
5442                         remove = TRUE;
5443                         break;
5444                 }
5445                 case MONO_PATCH_INFO_R4: {
5446                         guint8 *pos;
5447
5448                         code = (guint8*)ALIGN_TO (code, 8);
5449
5450                         pos = cfg->native_code + patch_info->ip.i;
5451
5452                         *(float*)code = *(float*)patch_info->data.target;
5453
5454                         if (use_sse2)
5455                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5456                         else
5457                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
5458                         code += 4;
5459
5460                         remove = TRUE;
5461                         break;
5462                 }
5463                 default:
5464                         break;
5465                 }
5466
5467                 if (remove) {
5468                         if (patch_info == cfg->patch_info)
5469                                 cfg->patch_info = patch_info->next;
5470                         else {
5471                                 MonoJumpInfo *tmp;
5472
5473                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5474                                         ;
5475                                 tmp->next = patch_info->next;
5476                         }
5477                 }
5478         }
5479
5480         cfg->code_len = code - cfg->native_code;
5481
5482         g_assert (cfg->code_len < cfg->code_size);
5483
5484 }
5485
5486 void*
5487 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5488 {
5489         guchar *code = p;
5490         CallInfo *cinfo;
5491         MonoMethodSignature *sig;
5492         MonoInst *inst;
5493         int i, n, stack_area = 0;
5494
5495         /* Keep this in sync with mono_arch_get_argument_info */
5496
5497         if (enable_arguments) {
5498                 /* Allocate a new area on the stack and save arguments there */
5499                 sig = mono_method_signature (cfg->method);
5500
5501                 cinfo = get_call_info (sig, FALSE);
5502
5503                 n = sig->param_count + sig->hasthis;
5504
5505                 stack_area = ALIGN_TO (n * 8, 16);
5506
5507                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5508
5509                 for (i = 0; i < n; ++i) {
5510                         inst = cfg->varinfo [i];
5511
5512                         if (inst->opcode == OP_REGVAR)
5513                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5514                         else {
5515                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5516                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5517                         }
5518                 }
5519         }
5520
5521         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5522         amd64_set_reg_template (code, AMD64_RDI);
5523         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
5524         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
5525
5526         if (enable_arguments) {
5527                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5528
5529                 g_free (cinfo);
5530         }
5531
5532         return code;
5533 }
5534
5535 enum {
5536         SAVE_NONE,
5537         SAVE_STRUCT,
5538         SAVE_EAX,
5539         SAVE_EAX_EDX,
5540         SAVE_XMM
5541 };
5542
5543 void*
5544 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5545 {
5546         guchar *code = p;
5547         int save_mode = SAVE_NONE;
5548         MonoMethod *method = cfg->method;
5549         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
5550
5551         switch (rtype) {
5552         case MONO_TYPE_VOID:
5553                 /* special case string .ctor icall */
5554                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5555                         save_mode = SAVE_EAX;
5556                 else
5557                         save_mode = SAVE_NONE;
5558                 break;
5559         case MONO_TYPE_I8:
5560         case MONO_TYPE_U8:
5561                 save_mode = SAVE_EAX;
5562                 break;
5563         case MONO_TYPE_R4:
5564         case MONO_TYPE_R8:
5565                 save_mode = SAVE_XMM;
5566                 break;
5567         case MONO_TYPE_VALUETYPE:
5568                 save_mode = SAVE_STRUCT;
5569                 break;
5570         default:
5571                 save_mode = SAVE_EAX;
5572                 break;
5573         }
5574
5575         /* Save the result and copy it into the proper argument register */
5576         switch (save_mode) {
5577         case SAVE_EAX:
5578                 amd64_push_reg (code, AMD64_RAX);
5579                 /* Align stack */
5580                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5581                 if (enable_arguments)
5582                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
5583                 break;
5584         case SAVE_STRUCT:
5585                 /* FIXME: */
5586                 if (enable_arguments)
5587                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
5588                 break;
5589         case SAVE_XMM:
5590                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5591                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5592                 /* Align stack */
5593                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5594                 /*
5595                  * The result is already in the proper argument register so no copying
5596                  * needed.
5597                  */
5598                 break;
5599         case SAVE_NONE:
5600                 break;
5601         default:
5602                 g_assert_not_reached ();
5603         }
5604
5605         /* Set %al since this is a varargs call */
5606         if (save_mode == SAVE_XMM)
5607                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5608         else
5609                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5610
5611         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5612         amd64_set_reg_template (code, AMD64_RDI);
5613         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
5614
5615         /* Restore result */
5616         switch (save_mode) {
5617         case SAVE_EAX:
5618                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5619                 amd64_pop_reg (code, AMD64_RAX);
5620                 break;
5621         case SAVE_STRUCT:
5622                 /* FIXME: */
5623                 break;
5624         case SAVE_XMM:
5625                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5626                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5627                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5628                 break;
5629         case SAVE_NONE:
5630                 break;
5631         default:
5632                 g_assert_not_reached ();
5633         }
5634
5635         return code;
5636 }
5637
5638 void
5639 mono_arch_flush_icache (guint8 *code, gint size)
5640 {
5641         /* Not needed */
5642 }
5643
5644 void
5645 mono_arch_flush_register_windows (void)
5646 {
5647 }
5648
5649 gboolean
5650 mono_arch_is_inst_imm (gint64 imm)
5651 {
5652         return amd64_is_imm32 (imm);
5653 }
5654
5655 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
5656
5657 static int reg_to_ucontext_reg [] = {
5658         REG_RAX, REG_RCX, REG_RDX, REG_RBX, REG_RSP, REG_RBP, REG_RSI, REG_RDI,
5659         REG_R8, REG_R9, REG_R10, REG_R11, REG_R12, REG_R13, REG_R14, REG_R15,
5660         REG_RIP
5661 };
5662
5663 /*
5664  * Determine whenever the trap whose info is in SIGINFO is caused by
5665  * integer overflow.
5666  */
5667 gboolean
5668 mono_arch_is_int_overflow (void *sigctx, void *info)
5669 {
5670         ucontext_t *ctx = (ucontext_t*)sigctx;
5671         guint8* rip;
5672         int reg;
5673
5674         rip = (guint8*)ctx->uc_mcontext.gregs [REG_RIP];
5675
5676         if (IS_REX (rip [0])) {
5677                 reg = amd64_rex_b (rip [0]);
5678                 rip ++;
5679         }
5680         else
5681                 reg = 0;
5682
5683         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5684                 /* idiv REG */
5685                 reg += x86_modrm_rm (rip [1]);
5686
5687                 if (ctx->uc_mcontext.gregs [reg_to_ucontext_reg [reg]] == -1)
5688                         return TRUE;
5689         }
5690
5691         return FALSE;
5692 }
5693
5694 guint32
5695 mono_arch_get_patch_offset (guint8 *code)
5696 {
5697         return 3;
5698 }
5699
5700 gpointer*
5701 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5702 {
5703         guint32 reg;
5704         guint32 disp;
5705         guint8 rex = 0;
5706
5707         /* go to the start of the call instruction
5708          *
5709          * address_byte = (m << 6) | (o << 3) | reg
5710          * call opcode: 0xff address_byte displacement
5711          * 0xff m=1,o=2 imm8
5712          * 0xff m=2,o=2 imm32
5713          */
5714         code -= 7;
5715
5716         /*
5717          * A given byte sequence can match more than case here, so we have to be
5718          * really careful about the ordering of the cases. Longer sequences
5719          * come first.
5720          */
5721         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5722                 /* call OFFSET(%rip) */
5723                 return NULL;
5724         }
5725         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5726                 /* call *[reg+disp32] */
5727                 if (IS_REX (code [0]))
5728                         rex = code [0];
5729                 reg = amd64_modrm_rm (code [2]);
5730                 disp = *(guint32*)(code + 3);
5731                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5732         }
5733         else if (code [2] == 0xe8) {
5734                 /* call <ADDR> */
5735                 return NULL;
5736         }
5737         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5738                 /* call *%reg */
5739                 return NULL;
5740         }
5741         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5742                 /* call *[reg+disp8] */
5743                 if (IS_REX (code [3]))
5744                         rex = code [3];
5745                 reg = amd64_modrm_rm (code [5]);
5746                 disp = *(guint8*)(code + 6);
5747                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5748         }
5749         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5750                         /*
5751                          * This is a interface call: should check the above code can't catch it earlier
5752                          * 8b 40 30   mov    0x30(%eax),%eax
5753                          * ff 10      call   *(%eax)
5754                          */
5755                 if (IS_REX (code [4]))
5756                         rex = code [4];
5757                 reg = amd64_modrm_rm (code [6]);
5758                 disp = 0;
5759         }
5760         else
5761                 g_assert_not_reached ();
5762
5763         reg += amd64_rex_b (rex);
5764
5765         /* R11 is clobbered by the trampoline code */
5766         g_assert (reg != AMD64_R11);
5767
5768         return (gpointer)(((guint64)(regs [reg])) + disp);
5769 }
5770
5771 gpointer*
5772 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
5773 {
5774         guint32 reg;
5775         guint32 disp;
5776
5777         code -= 10;
5778
5779         if (IS_REX (code [0]) && (code [1] == 0x8b) && (code [3] == 0x48) && (code [4] == 0x8b) && (code [5] == 0x40) && (code [7] == 0x48) && (code [8] == 0xff) && (code [9] == 0xd0)) {
5780                 /* mov REG, %rax; mov <OFFSET>(%rax), %rax; call *%rax */
5781                 reg = amd64_rex_b (code [0]) + amd64_modrm_rm (code [2]);
5782                 disp = code [6];
5783
5784                 if (reg == AMD64_RAX)
5785                         return NULL;
5786                 else
5787                         return (gpointer*)(((guint64)(regs [reg])) + disp);
5788         }
5789
5790         return NULL;
5791 }
5792
5793 /*
5794  * Support for fast access to the thread-local lmf structure using the GS
5795  * segment register on NPTL + kernel 2.6.x.
5796  */
5797
5798 static gboolean tls_offset_inited = FALSE;
5799
5800 /* code should be simply return <tls var>; */
5801 static int
5802 read_tls_offset_from_method (void* method)
5803 {
5804         guint8 *code = (guint8*)method;
5805
5806         /*
5807          * Determine the offset of mono_lfm_addr inside the TLS structures
5808          * by disassembling the function above.
5809          */
5810         /* This is generated by gcc 3.3.2 */
5811         if ((code [0] == 0x55) && (code [1] == 0x48) && (code [2] == 0x89) &&
5812                 (code [3] == 0xe5) && (code [4] == 0x64) && (code [5] == 0x48) &&
5813                 (code [6] == 0x8b) && (code [7] == 0x04) && (code [8] == 0x25) &&
5814                 (code [9] == 0x00) && (code [10] == 0x00) && (code [11] == 0x00) &&
5815                 (code [12] == 0x0) && (code [13] == 0x48) && (code [14] == 0x8b) &&
5816                 (code [15] == 0x80)) {
5817                 return *(gint32*)&(code [16]);
5818         } else if
5819                 /* This is generated by gcc-3.3.2 with -O=2 */
5820                 /* mov fs:0, %rax ; mov <offset>(%rax), %rax ; retq */
5821                 ((code [0] == 0x64) && (code [1] == 0x48) && (code [2] == 0x8b) &&
5822                  (code [3] == 0x04) && (code [4] == 0x25) &&
5823                  (code [9] == 0x48) && (code [10] == 0x8b) && (code [11] == 0x80) &&
5824                  (code [16] == 0xc3)) {
5825                         return *(gint32*)&(code [12]);
5826         } else if
5827                 /* This is generated by gcc-3.4.1 */
5828                 ((code [0] == 0x55) && (code [1] == 0x48) && (code [2] == 0x89) &&
5829                  (code [3] == 0xe5) && (code [4] == 0x64) && (code [5] == 0x48) &&
5830                  (code [6] == 0x8b) && (code [7] == 0x04) && (code [8] == 0x25) &&
5831                  (code [13] == 0xc9) && (code [14] == 0xc3)) {
5832                         return *(gint32*)&(code [9]);
5833         } else if
5834                 /* This is generated by gcc-3.4.1 with -O=2 */
5835                 ((code [0] == 0x64) && (code [1] == 0x48) && (code [2] == 0x8b) &&
5836                  (code [3] == 0x04) && (code [4] == 0x25)) {
5837                 return *(gint32*)&(code [5]);
5838         }
5839
5840         return -1;
5841 }
5842
5843 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
5844
5845 static void
5846 setup_stack (MonoJitTlsData *tls)
5847 {
5848         pthread_t self = pthread_self();
5849         pthread_attr_t attr;
5850         size_t stsize = 0;
5851         struct sigaltstack sa;
5852         guint8 *staddr = NULL;
5853         guint8 *current = (guint8*)&staddr;
5854
5855         if (mono_running_on_valgrind ())
5856                 return;
5857
5858         /* Determine stack boundaries */
5859 #ifdef HAVE_PTHREAD_GETATTR_NP
5860         pthread_getattr_np( self, &attr );
5861 #else
5862 #ifdef HAVE_PTHREAD_ATTR_GET_NP
5863         pthread_attr_get_np( self, &attr );
5864 #elif defined(sun)
5865         pthread_attr_init( &attr );
5866         pthread_attr_getstacksize( &attr, &stsize );
5867 #else
5868 #error "Not implemented"
5869 #endif
5870 #endif
5871 #ifndef sun
5872         pthread_attr_getstack( &attr, (void**)&staddr, &stsize );
5873 #endif
5874
5875         g_assert (staddr);
5876
5877         g_assert ((current > staddr) && (current < staddr + stsize));
5878
5879         tls->end_of_stack = staddr + stsize;
5880
5881         /*
5882          * threads created by nptl does not seem to have a guard page, and
5883          * since the main thread is not created by us, we can't even set one.
5884          * Increasing stsize fools the SIGSEGV signal handler into thinking this
5885          * is a stack overflow exception.
5886          */
5887         tls->stack_size = stsize + getpagesize ();
5888
5889         /* Setup an alternate signal stack */
5890         tls->signal_stack = mmap (0, SIGNAL_STACK_SIZE, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0);
5891         tls->signal_stack_size = SIGNAL_STACK_SIZE;
5892
5893         g_assert (tls->signal_stack);
5894
5895         sa.ss_sp = tls->signal_stack;
5896         sa.ss_size = SIGNAL_STACK_SIZE;
5897         sa.ss_flags = SS_ONSTACK;
5898         sigaltstack (&sa, NULL);
5899 }
5900
5901 #endif
5902
5903 void
5904 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5905 {
5906         if (!tls_offset_inited) {
5907                 tls_offset_inited = TRUE;
5908
5909                 lmf_tls_offset = read_tls_offset_from_method (mono_get_lmf_addr);
5910                 appdomain_tls_offset = read_tls_offset_from_method (mono_domain_get);
5911                 thread_tls_offset = read_tls_offset_from_method (mono_thread_current);
5912         }
5913
5914 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
5915         setup_stack (tls);
5916 #endif
5917 }
5918
5919 void
5920 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5921 {
5922 #ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
5923         struct sigaltstack sa;
5924
5925         sa.ss_sp = tls->signal_stack;
5926         sa.ss_size = SIGNAL_STACK_SIZE;
5927         sa.ss_flags = SS_DISABLE;
5928         sigaltstack  (&sa, NULL);
5929
5930         if (tls->signal_stack)
5931                 munmap (tls->signal_stack, SIGNAL_STACK_SIZE);
5932 #endif
5933 }
5934
5935 void
5936 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5937 {
5938         MonoCallInst *call = (MonoCallInst*)inst;
5939         int out_reg = param_regs [0];
5940         guint64 regpair;
5941
5942         if (vt_reg != -1) {
5943                 CallInfo * cinfo = get_call_info (inst->signature, FALSE);
5944                 MonoInst *vtarg;
5945
5946                 if (cinfo->ret.storage == ArgValuetypeInReg) {
5947                         /*
5948                          * The valuetype is in RAX:RDX after the call, need to be copied to
5949                          * the stack. Push the address here, so the call instruction can
5950                          * access it.
5951                          */
5952                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5953                         vtarg->sreg1 = vt_reg;
5954                         mono_bblock_add_inst (cfg->cbb, vtarg);
5955
5956                         /* Align stack */
5957                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5958                 }
5959                 else {
5960                         MONO_INST_NEW (cfg, vtarg, OP_SETREG);
5961                         vtarg->sreg1 = vt_reg;
5962                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
5963                         mono_bblock_add_inst (cfg->cbb, vtarg);
5964
5965                         regpair = (((guint64)out_reg) << 32) + vtarg->dreg;
5966                         call->out_ireg_args = g_slist_append (call->out_ireg_args, (gpointer)(regpair));
5967
5968                         out_reg = param_regs [1];
5969                 }
5970
5971                 g_free (cinfo);
5972         }
5973
5974         /* add the this argument */
5975         if (this_reg != -1) {
5976                 MonoInst *this;
5977                 MONO_INST_NEW (cfg, this, OP_SETREG);
5978                 this->type = this_type;
5979                 this->sreg1 = this_reg;
5980                 this->dreg = mono_regstate_next_int (cfg->rs);
5981                 mono_bblock_add_inst (cfg->cbb, this);
5982
5983                 regpair = (((guint64)out_reg) << 32) + this->dreg;
5984                 call->out_ireg_args = g_slist_append (call->out_ireg_args, (gpointer)(regpair));
5985         }
5986 }
5987
5988 MonoInst*
5989 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5990 {
5991         MonoInst *ins = NULL;
5992
5993         if (cmethod->klass == mono_defaults.math_class) {
5994                 if (strcmp (cmethod->name, "Sin") == 0) {
5995                         MONO_INST_NEW (cfg, ins, OP_SIN);
5996                         ins->inst_i0 = args [0];
5997                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5998                         MONO_INST_NEW (cfg, ins, OP_COS);
5999                         ins->inst_i0 = args [0];
6000                 } else if (strcmp (cmethod->name, "Tan") == 0) {
6001                         if (use_sse2)
6002                                 return ins;
6003                         MONO_INST_NEW (cfg, ins, OP_TAN);
6004                         ins->inst_i0 = args [0];
6005                 } else if (strcmp (cmethod->name, "Atan") == 0) {
6006                         if (use_sse2)
6007                                 return ins;
6008                         MONO_INST_NEW (cfg, ins, OP_ATAN);
6009                         ins->inst_i0 = args [0];
6010                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6011                         MONO_INST_NEW (cfg, ins, OP_SQRT);
6012                         ins->inst_i0 = args [0];
6013                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6014                         MONO_INST_NEW (cfg, ins, OP_ABS);
6015                         ins->inst_i0 = args [0];
6016                 }
6017 #if 0
6018                 /* OP_FREM is not IEEE compatible */
6019                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6020                         MONO_INST_NEW (cfg, ins, OP_FREM);
6021                         ins->inst_i0 = args [0];
6022                         ins->inst_i1 = args [1];
6023                 }
6024 #endif
6025         } else if(cmethod->klass->image == mono_defaults.corlib &&
6026                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
6027                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
6028
6029                 if (strcmp (cmethod->name, "Increment") == 0) {
6030                         MonoInst *ins_iconst;
6031                         guint32 opcode;
6032
6033                         if (fsig->params [0]->type == MONO_TYPE_I4)
6034                                 opcode = OP_ATOMIC_ADD_NEW_I4;
6035                         else if (fsig->params [0]->type == MONO_TYPE_I8)
6036                                 opcode = OP_ATOMIC_ADD_NEW_I8;
6037                         else
6038                                 g_assert_not_reached ();
6039                         MONO_INST_NEW (cfg, ins, opcode);
6040                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
6041                         ins_iconst->inst_c0 = 1;
6042
6043                         ins->inst_i0 = args [0];
6044                         ins->inst_i1 = ins_iconst;
6045                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
6046                         MonoInst *ins_iconst;
6047                         guint32 opcode;
6048
6049                         if (fsig->params [0]->type == MONO_TYPE_I4)
6050                                 opcode = OP_ATOMIC_ADD_NEW_I4;
6051                         else if (fsig->params [0]->type == MONO_TYPE_I8)
6052                                 opcode = OP_ATOMIC_ADD_NEW_I8;
6053                         else
6054                                 g_assert_not_reached ();
6055                         MONO_INST_NEW (cfg, ins, opcode);
6056                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
6057                         ins_iconst->inst_c0 = -1;
6058
6059                         ins->inst_i0 = args [0];
6060                         ins->inst_i1 = ins_iconst;
6061                 } else if (strcmp (cmethod->name, "Add") == 0) {
6062                         guint32 opcode;
6063
6064                         if (fsig->params [0]->type == MONO_TYPE_I4)
6065                                 opcode = OP_ATOMIC_ADD_I4;
6066                         else if (fsig->params [0]->type == MONO_TYPE_I8)
6067                                 opcode = OP_ATOMIC_ADD_I8;
6068                         else
6069                                 g_assert_not_reached ();
6070
6071                         MONO_INST_NEW (cfg, ins, opcode);
6072
6073                         ins->inst_i0 = args [0];
6074                         ins->inst_i1 = args [1];
6075                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
6076                         guint32 opcode;
6077
6078                         if (fsig->params [0]->type == MONO_TYPE_I4)
6079                                 opcode = OP_ATOMIC_EXCHANGE_I4;
6080                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
6081                                          (fsig->params [0]->type == MONO_TYPE_I) ||
6082                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
6083                                 opcode = OP_ATOMIC_EXCHANGE_I8;
6084                         else
6085                                 return NULL;
6086
6087                         MONO_INST_NEW (cfg, ins, opcode);
6088
6089                         ins->inst_i0 = args [0];
6090                         ins->inst_i1 = args [1];
6091                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
6092                         /* 64 bit reads are already atomic */
6093                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
6094                         ins->inst_i0 = args [0];
6095                 }
6096
6097                 /*
6098                  * Can't implement CompareExchange methods this way since they have
6099                  * three arguments.
6100                  */
6101         }
6102
6103         return ins;
6104 }
6105
6106 gboolean
6107 mono_arch_print_tree (MonoInst *tree, int arity)
6108 {
6109         return 0;
6110 }
6111
6112 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6113 {
6114         MonoInst* ins;
6115
6116         if (appdomain_tls_offset == -1)
6117                 return NULL;
6118
6119         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6120         ins->inst_offset = appdomain_tls_offset;
6121         return ins;
6122 }
6123
6124 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6125 {
6126         MonoInst* ins;
6127
6128         if (thread_tls_offset == -1)
6129                 return NULL;
6130
6131         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6132         ins->inst_offset = thread_tls_offset;
6133         return ins;
6134 }