mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27
  28 #include "trace.h"
  29 #include "ir-emit.h"
  30 #include "mini-amd64.h"
  31 #include "cpu-amd64.h"
  32
  33 /*
  34  * Can't define this in mini-amd64.h cause that would turn on the generic code in
  35  * method-to-ir.c.
  36  */
  37 #define MONO_ARCH_IMT_REG AMD64_R11
  38
  39 static gint lmf_tls_offset = -1;
  40 static gint lmf_addr_tls_offset = -1;
  41 static gint appdomain_tls_offset = -1;
  42
  43 #ifdef MONO_XEN_OPT
  44 static gboolean optimize_for_xen = TRUE;
  45 #else
  46 #define optimize_for_xen 0
  47 #endif
  48
  49 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  50
  51 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  52
  53 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  54
  55 #ifdef PLATFORM_WIN32
  56 /* Under windows, the calling convention is never stdcall */
  57 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  58 #else
  59 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  60 #endif
  61
  62 /* This mutex protects architecture specific caches */
  63 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  64 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  65 static CRITICAL_SECTION mini_arch_mutex;
  66
  67 MonoBreakpointInfo
  68 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  69
  70 #ifdef PLATFORM_WIN32
  71 /* On Win64 always reserve first 32 bytes for first four arguments */
  72 #define ARGS_OFFSET 48
  73 #else
  74 #define ARGS_OFFSET 16
  75 #endif
  76 #define GP_SCRATCH_REG AMD64_R11
  77
  78 /*
  79  * AMD64 register usage:
  80  * - callee saved registers are used for global register allocation
  81  * - %r11 is used for materializing 64 bit constants in opcodes
  82  * - the rest is used for local allocation
  83  */
  84
  85 /*
  86  * Floating point comparison results:
  87  *                  ZF PF CF
  88  * A > B            0  0  0
  89  * A < B            0  0  1
  90  * A = B            1  0  0
  91  * A > B            0  0  0
  92  * UNORDERED        1  1  1
  93  */
  94
  95 const char*
  96 mono_arch_regname (int reg)
  97 {
  98         switch (reg) {
  99         case AMD64_RAX: return "%rax";
 100         case AMD64_RBX: return "%rbx";
 101         case AMD64_RCX: return "%rcx";
 102         case AMD64_RDX: return "%rdx";
 103         case AMD64_RSP: return "%rsp";
 104         case AMD64_RBP: return "%rbp";
 105         case AMD64_RDI: return "%rdi";
 106         case AMD64_RSI: return "%rsi";
 107         case AMD64_R8: return "%r8";
 108         case AMD64_R9: return "%r9";
 109         case AMD64_R10: return "%r10";
 110         case AMD64_R11: return "%r11";
 111         case AMD64_R12: return "%r12";
 112         case AMD64_R13: return "%r13";
 113         case AMD64_R14: return "%r14";
 114         case AMD64_R15: return "%r15";
 115         }
 116         return "unknown";
 117 }
 118
 119 static const char * packed_xmmregs [] = {
 120         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 121         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 122 };
 123
 124 static const char * single_xmmregs [] = {
 125         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 126         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 127 };
 128
 129 const char*
 130 mono_arch_fregname (int reg)
 131 {
 132         if (reg < AMD64_XMM_NREG)
 133                 return single_xmmregs [reg];
 134         else
 135                 return "unknown";
 136 }
 137
 138 const char *
 139 mono_arch_xregname (int reg)
 140 {
 141         if (reg < AMD64_XMM_NREG)
 142                 return packed_xmmregs [reg];
 143         else
 144                 return "unknown";
 145 }
 146
 147 G_GNUC_UNUSED static void
 148 break_count (void)
 149 {
 150 }
 151
 152 G_GNUC_UNUSED static gboolean
 153 debug_count (void)
 154 {
 155         static int count = 0;
 156         count ++;
 157
 158         if (!getenv ("COUNT"))
 159                 return TRUE;
 160
 161         if (count == atoi (getenv ("COUNT"))) {
 162                 break_count ();
 163         }
 164
 165         if (count > atoi (getenv ("COUNT"))) {
 166                 return FALSE;
 167         }
 168
 169         return TRUE;
 170 }
 171
 172 static gboolean
 173 debug_omit_fp (void)
 174 {
 175 #if 0
 176         return debug_count ();
 177 #else
 178         return TRUE;
 179 #endif
 180 }
 181
 182 static inline gboolean
 183 amd64_is_near_call (guint8 *code)
 184 {
 185         /* Skip REX */
 186         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 187                 code += 1;
 188
 189         return code [0] == 0xe8;
 190 }
 191
 192 static inline void
 193 amd64_patch (unsigned char* code, gpointer target)
 194 {
 195         guint8 rex = 0;
 196
 197         /* Skip REX */
 198         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 199                 rex = code [0];
 200                 code += 1;
 201         }
 202
 203         if ((code [0] & 0xf8) == 0xb8) {
 204                 /* amd64_set_reg_template */
 205                 *(guint64*)(code + 1) = (guint64)target;
 206         }
 207         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 208                 /* mov 0(%rip), %dreg */
 209                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 210         }
 211         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 212                 /* call *<OFFSET>(%rip) */
 213                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 214         }
 215         else if ((code [0] == 0xe8)) {
 216                 /* call <DISP> */
 217                 gint64 disp = (guint8*)target - (guint8*)code;
 218                 g_assert (amd64_is_imm32 (disp));
 219                 x86_patch (code, (unsigned char*)target);
 220         }
 221         else
 222                 x86_patch (code, (unsigned char*)target);
 223 }
 224
 225 void
 226 mono_amd64_patch (unsigned char* code, gpointer target)
 227 {
 228         amd64_patch (code, target);
 229 }
 230
 231 typedef enum {
 232         ArgInIReg,
 233         ArgInFloatSSEReg,
 234         ArgInDoubleSSEReg,
 235         ArgOnStack,
 236         ArgValuetypeInReg,
 237         ArgValuetypeAddrInIReg,
 238         ArgNone /* only in pair_storage */
 239 } ArgStorage;
 240
 241 typedef struct {
 242         gint16 offset;
 243         gint8  reg;
 244         ArgStorage storage;
 245
 246         /* Only if storage == ArgValuetypeInReg */
 247         ArgStorage pair_storage [2];
 248         gint8 pair_regs [2];
 249 } ArgInfo;
 250
 251 typedef struct {
 252         int nargs;
 253         guint32 stack_usage;
 254         guint32 reg_usage;
 255         guint32 freg_usage;
 256         gboolean need_stack_align;
 257         gboolean vtype_retaddr;
 258         ArgInfo ret;
 259         ArgInfo sig_cookie;
 260         ArgInfo args [1];
 261 } CallInfo;
 262
 263 #define DEBUG(a) if (cfg->verbose_level > 1) a
 264
 265 #ifdef PLATFORM_WIN32
 266 #define PARAM_REGS 4
 267
 268 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 269
 270 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 271 #else
 272 #define PARAM_REGS 6
 273
 274 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 275
 276  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 277 #endif
 278
 279 static void inline
 280 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 281 {
 282     ainfo->offset = *stack_size;
 283
 284     if (*gr >= PARAM_REGS) {
 285                 ainfo->storage = ArgOnStack;
 286                 (*stack_size) += sizeof (gpointer);
 287     }
 288     else {
 289                 ainfo->storage = ArgInIReg;
 290                 ainfo->reg = param_regs [*gr];
 291                 (*gr) ++;
 292     }
 293 }
 294
 295 #ifdef PLATFORM_WIN32
 296 #define FLOAT_PARAM_REGS 4
 297 #else
 298 #define FLOAT_PARAM_REGS 8
 299 #endif
 300
 301 static void inline
 302 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 303 {
 304     ainfo->offset = *stack_size;
 305
 306     if (*gr >= FLOAT_PARAM_REGS) {
 307                 ainfo->storage = ArgOnStack;
 308                 (*stack_size) += sizeof (gpointer);
 309     }
 310     else {
 311                 /* A double register */
 312                 if (is_double)
 313                         ainfo->storage = ArgInDoubleSSEReg;
 314                 else
 315                         ainfo->storage = ArgInFloatSSEReg;
 316                 ainfo->reg = *gr;
 317                 (*gr) += 1;
 318     }
 319 }
 320
 321 typedef enum ArgumentClass {
 322         ARG_CLASS_NO_CLASS,
 323         ARG_CLASS_MEMORY,
 324         ARG_CLASS_INTEGER,
 325         ARG_CLASS_SSE
 326 } ArgumentClass;
 327
 328 static ArgumentClass
 329 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 330 {
 331         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 332         MonoType *ptype;
 333
 334         ptype = mini_type_get_underlying_type (NULL, type);
 335         switch (ptype->type) {
 336         case MONO_TYPE_BOOLEAN:
 337         case MONO_TYPE_CHAR:
 338         case MONO_TYPE_I1:
 339         case MONO_TYPE_U1:
 340         case MONO_TYPE_I2:
 341         case MONO_TYPE_U2:
 342         case MONO_TYPE_I4:
 343         case MONO_TYPE_U4:
 344         case MONO_TYPE_I:
 345         case MONO_TYPE_U:
 346         case MONO_TYPE_STRING:
 347         case MONO_TYPE_OBJECT:
 348         case MONO_TYPE_CLASS:
 349         case MONO_TYPE_SZARRAY:
 350         case MONO_TYPE_PTR:
 351         case MONO_TYPE_FNPTR:
 352         case MONO_TYPE_ARRAY:
 353         case MONO_TYPE_I8:
 354         case MONO_TYPE_U8:
 355                 class2 = ARG_CLASS_INTEGER;
 356                 break;
 357         case MONO_TYPE_R4:
 358         case MONO_TYPE_R8:
 359 #ifdef PLATFORM_WIN32
 360                 class2 = ARG_CLASS_INTEGER;
 361 #else
 362                 class2 = ARG_CLASS_SSE;
 363 #endif
 364                 break;
 365
 366         case MONO_TYPE_TYPEDBYREF:
 367                 g_assert_not_reached ();
 368
 369         case MONO_TYPE_GENERICINST:
 370                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 371                         class2 = ARG_CLASS_INTEGER;
 372                         break;
 373                 }
 374                 /* fall through */
 375         case MONO_TYPE_VALUETYPE: {
 376                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 377                 int i;
 378
 379                 for (i = 0; i < info->num_fields; ++i) {
 380                         class2 = class1;
 381                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 382                 }
 383                 break;
 384         }
 385         default:
 386                 g_assert_not_reached ();
 387         }
 388
 389         /* Merge */
 390         if (class1 == class2)
 391                 ;
 392         else if (class1 == ARG_CLASS_NO_CLASS)
 393                 class1 = class2;
 394         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 395                 class1 = ARG_CLASS_MEMORY;
 396         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 397                 class1 = ARG_CLASS_INTEGER;
 398         else
 399                 class1 = ARG_CLASS_SSE;
 400
 401         return class1;
 402 }
 403
 404 static void
 405 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 406                            gboolean is_return,
 407                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 408 {
 409         guint32 size, quad, nquads, i;
 410         ArgumentClass args [2];
 411         MonoMarshalType *info = NULL;
 412         MonoClass *klass;
 413         MonoGenericSharingContext tmp_gsctx;
 414         gboolean pass_on_stack = FALSE;
 415
 416         /*
 417          * The gsctx currently contains no data, it is only used for checking whenever
 418          * open types are allowed, some callers like mono_arch_get_argument_info ()
 419          * don't pass it to us, so work around that.
 420          */
 421         if (!gsctx)
 422                 gsctx = &tmp_gsctx;
 423
 424         klass = mono_class_from_mono_type (type);
 425         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 426 #ifndef PLATFORM_WIN32
 427         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 428                 /* We pass and return vtypes of size 8 in a register */
 429         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 430                 pass_on_stack = TRUE;
 431         }
 432 #else
 433         if (!sig->pinvoke) {
 434                 pass_on_stack = TRUE;
 435         }
 436 #endif
 437
 438         if (pass_on_stack) {
 439                 /* Allways pass in memory */
 440                 ainfo->offset = *stack_size;
 441                 *stack_size += ALIGN_TO (size, 8);
 442                 ainfo->storage = ArgOnStack;
 443
 444                 return;
 445         }
 446
 447         /* FIXME: Handle structs smaller than 8 bytes */
 448         //if ((size % 8) != 0)
 449         //      NOT_IMPLEMENTED;
 450
 451         if (size > 8)
 452                 nquads = 2;
 453         else
 454                 nquads = 1;
 455
 456         if (!sig->pinvoke) {
 457                 /* Always pass in 1 or 2 integer registers */
 458                 args [0] = ARG_CLASS_INTEGER;
 459                 args [1] = ARG_CLASS_INTEGER;
 460                 /* Only the simplest cases are supported */
 461                 if (is_return && nquads != 1) {
 462                         args [0] = ARG_CLASS_MEMORY;
 463                         args [1] = ARG_CLASS_MEMORY;
 464                 }
 465         } else {
 466                 /*
 467                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 468                  * The X87 and SSEUP stuff is left out since there are no such types in
 469                  * the CLR.
 470                  */
 471                 info = mono_marshal_load_type_info (klass);
 472                 g_assert (info);
 473
 474 #ifndef PLATFORM_WIN32
 475                 if (info->native_size > 16) {
 476                         ainfo->offset = *stack_size;
 477                         *stack_size += ALIGN_TO (info->native_size, 8);
 478                         ainfo->storage = ArgOnStack;
 479
 480                         return;
 481                 }
 482 #else
 483                 switch (info->native_size) {
 484                 case 1: case 2: case 4: case 8:
 485                         break;
 486                 default:
 487                         if (is_return) {
 488                                 ainfo->storage = ArgOnStack;
 489                                 ainfo->offset = *stack_size;
 490                                 *stack_size += ALIGN_TO (info->native_size, 8);
 491                         }
 492                         else {
 493                                 ainfo->storage = ArgValuetypeAddrInIReg;
 494
 495                                 if (*gr < PARAM_REGS) {
 496                                         ainfo->pair_storage [0] = ArgInIReg;
 497                                         ainfo->pair_regs [0] = param_regs [*gr];
 498                                         (*gr) ++;
 499                                 }
 500                                 else {
 501                                         ainfo->pair_storage [0] = ArgOnStack;
 502                                         ainfo->offset = *stack_size;
 503                                         *stack_size += 8;
 504                                 }
 505                         }
 506
 507                         return;
 508                 }
 509 #endif
 510
 511                 args [0] = ARG_CLASS_NO_CLASS;
 512                 args [1] = ARG_CLASS_NO_CLASS;
 513                 for (quad = 0; quad < nquads; ++quad) {
 514                         int size;
 515                         guint32 align;
 516                         ArgumentClass class1;
 517
 518                         if (info->num_fields == 0)
 519                                 class1 = ARG_CLASS_MEMORY;
 520                         else
 521                                 class1 = ARG_CLASS_NO_CLASS;
 522                         for (i = 0; i < info->num_fields; ++i) {
 523                                 size = mono_marshal_type_size (info->fields [i].field->type,
 524                                                                                            info->fields [i].mspec,
 525                                                                                            &align, TRUE, klass->unicode);
 526                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 527                                         /* Unaligned field */
 528                                         NOT_IMPLEMENTED;
 529                                 }
 530
 531                                 /* Skip fields in other quad */
 532                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 533                                         continue;
 534                                 if ((quad == 1) && (info->fields [i].offset < 8))
 535                                         continue;
 536
 537                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 538                         }
 539                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 540                         args [quad] = class1;
 541                 }
 542         }
 543
 544         /* Post merger cleanup */
 545         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 546                 args [0] = args [1] = ARG_CLASS_MEMORY;
 547
 548         /* Allocate registers */
 549         {
 550                 int orig_gr = *gr;
 551                 int orig_fr = *fr;
 552
 553                 ainfo->storage = ArgValuetypeInReg;
 554                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 555                 for (quad = 0; quad < nquads; ++quad) {
 556                         switch (args [quad]) {
 557                         case ARG_CLASS_INTEGER:
 558                                 if (*gr >= PARAM_REGS)
 559                                         args [quad] = ARG_CLASS_MEMORY;
 560                                 else {
 561                                         ainfo->pair_storage [quad] = ArgInIReg;
 562                                         if (is_return)
 563                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 564                                         else
 565                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 566                                         (*gr) ++;
 567                                 }
 568                                 break;
 569                         case ARG_CLASS_SSE:
 570                                 if (*fr >= FLOAT_PARAM_REGS)
 571                                         args [quad] = ARG_CLASS_MEMORY;
 572                                 else {
 573                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 574                                         ainfo->pair_regs [quad] = *fr;
 575                                         (*fr) ++;
 576                                 }
 577                                 break;
 578                         case ARG_CLASS_MEMORY:
 579                                 break;
 580                         default:
 581                                 g_assert_not_reached ();
 582                         }
 583                 }
 584
 585                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 586                         /* Revert possible register assignments */
 587                         *gr = orig_gr;
 588                         *fr = orig_fr;
 589
 590                         ainfo->offset = *stack_size;
 591                         if (sig->pinvoke)
 592                                 *stack_size += ALIGN_TO (info->native_size, 8);
 593                         else
 594                                 *stack_size += nquads * sizeof (gpointer);
 595                         ainfo->storage = ArgOnStack;
 596                 }
 597         }
 598 }
 599
 600 /*
 601  * get_call_info:
 602  *
 603  *  Obtain information about a call according to the calling convention.
 604  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 605  * Draft Version 0.23" document for more information.
 606  */
 607 static CallInfo*
 608 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 609 {
 610         guint32 i, gr, fr;
 611         MonoType *ret_type;
 612         int n = sig->hasthis + sig->param_count;
 613         guint32 stack_size = 0;
 614         CallInfo *cinfo;
 615
 616         if (mp)
 617                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 618         else
 619                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 620
 621         cinfo->nargs = n;
 622
 623         gr = 0;
 624         fr = 0;
 625
 626         /* return value */
 627         {
 628                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 629                 switch (ret_type->type) {
 630                 case MONO_TYPE_BOOLEAN:
 631                 case MONO_TYPE_I1:
 632                 case MONO_TYPE_U1:
 633                 case MONO_TYPE_I2:
 634                 case MONO_TYPE_U2:
 635                 case MONO_TYPE_CHAR:
 636                 case MONO_TYPE_I4:
 637                 case MONO_TYPE_U4:
 638                 case MONO_TYPE_I:
 639                 case MONO_TYPE_U:
 640                 case MONO_TYPE_PTR:
 641                 case MONO_TYPE_FNPTR:
 642                 case MONO_TYPE_CLASS:
 643                 case MONO_TYPE_OBJECT:
 644                 case MONO_TYPE_SZARRAY:
 645                 case MONO_TYPE_ARRAY:
 646                 case MONO_TYPE_STRING:
 647                         cinfo->ret.storage = ArgInIReg;
 648                         cinfo->ret.reg = AMD64_RAX;
 649                         break;
 650                 case MONO_TYPE_U8:
 651                 case MONO_TYPE_I8:
 652                         cinfo->ret.storage = ArgInIReg;
 653                         cinfo->ret.reg = AMD64_RAX;
 654                         break;
 655                 case MONO_TYPE_R4:
 656                         cinfo->ret.storage = ArgInFloatSSEReg;
 657                         cinfo->ret.reg = AMD64_XMM0;
 658                         break;
 659                 case MONO_TYPE_R8:
 660                         cinfo->ret.storage = ArgInDoubleSSEReg;
 661                         cinfo->ret.reg = AMD64_XMM0;
 662                         break;
 663                 case MONO_TYPE_GENERICINST:
 664                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 665                                 cinfo->ret.storage = ArgInIReg;
 666                                 cinfo->ret.reg = AMD64_RAX;
 667                                 break;
 668                         }
 669                         /* fall through */
 670                 case MONO_TYPE_VALUETYPE: {
 671                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 672
 673                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 674                         if (cinfo->ret.storage == ArgOnStack) {
 675                                 cinfo->vtype_retaddr = TRUE;
 676                                 /* The caller passes the address where the value is stored */
 677                                 add_general (&gr, &stack_size, &cinfo->ret);
 678                         }
 679                         break;
 680                 }
 681                 case MONO_TYPE_TYPEDBYREF:
 682                         /* Same as a valuetype with size 24 */
 683                         add_general (&gr, &stack_size, &cinfo->ret);
 684                         ;
 685                         break;
 686                 case MONO_TYPE_VOID:
 687                         break;
 688                 default:
 689                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 690                 }
 691         }
 692
 693         /* this */
 694         if (sig->hasthis)
 695                 add_general (&gr, &stack_size, cinfo->args + 0);
 696
 697         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 698                 gr = PARAM_REGS;
 699                 fr = FLOAT_PARAM_REGS;
 700
 701                 /* Emit the signature cookie just before the implicit arguments */
 702                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 703         }
 704
 705         for (i = 0; i < sig->param_count; ++i) {
 706                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 707                 MonoType *ptype;
 708
 709 #ifdef PLATFORM_WIN32
 710                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 711                 if (gr > fr)
 712                         fr = gr;
 713                 else if (fr > gr)
 714                         gr = fr;
 715 #endif
 716
 717                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 718                         /* We allways pass the sig cookie on the stack for simplicity */
 719                         /*
 720                          * Prevent implicit arguments + the sig cookie from being passed
 721                          * in registers.
 722                          */
 723                         gr = PARAM_REGS;
 724                         fr = FLOAT_PARAM_REGS;
 725
 726                         /* Emit the signature cookie just before the implicit arguments */
 727                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 728                 }
 729
 730                 if (sig->params [i]->byref) {
 731                         add_general (&gr, &stack_size, ainfo);
 732                         continue;
 733                 }
 734                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 735                 switch (ptype->type) {
 736                 case MONO_TYPE_BOOLEAN:
 737                 case MONO_TYPE_I1:
 738                 case MONO_TYPE_U1:
 739                         add_general (&gr, &stack_size, ainfo);
 740                         break;
 741                 case MONO_TYPE_I2:
 742                 case MONO_TYPE_U2:
 743                 case MONO_TYPE_CHAR:
 744                         add_general (&gr, &stack_size, ainfo);
 745                         break;
 746                 case MONO_TYPE_I4:
 747                 case MONO_TYPE_U4:
 748                         add_general (&gr, &stack_size, ainfo);
 749                         break;
 750                 case MONO_TYPE_I:
 751                 case MONO_TYPE_U:
 752                 case MONO_TYPE_PTR:
 753                 case MONO_TYPE_FNPTR:
 754                 case MONO_TYPE_CLASS:
 755                 case MONO_TYPE_OBJECT:
 756                 case MONO_TYPE_STRING:
 757                 case MONO_TYPE_SZARRAY:
 758                 case MONO_TYPE_ARRAY:
 759                         add_general (&gr, &stack_size, ainfo);
 760                         break;
 761                 case MONO_TYPE_GENERICINST:
 762                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 763                                 add_general (&gr, &stack_size, ainfo);
 764                                 break;
 765                         }
 766                         /* fall through */
 767                 case MONO_TYPE_VALUETYPE:
 768                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 769                         break;
 770                 case MONO_TYPE_TYPEDBYREF:
 771 #ifdef PLATFORM_WIN32
 772                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 773 #else
 774                         stack_size += sizeof (MonoTypedRef);
 775                         ainfo->storage = ArgOnStack;
 776 #endif
 777                         break;
 778                 case MONO_TYPE_U8:
 779                 case MONO_TYPE_I8:
 780                         add_general (&gr, &stack_size, ainfo);
 781                         break;
 782                 case MONO_TYPE_R4:
 783                         add_float (&fr, &stack_size, ainfo, FALSE);
 784                         break;
 785                 case MONO_TYPE_R8:
 786                         add_float (&fr, &stack_size, ainfo, TRUE);
 787                         break;
 788                 default:
 789                         g_assert_not_reached ();
 790                 }
 791         }
 792
 793         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 794                 gr = PARAM_REGS;
 795                 fr = FLOAT_PARAM_REGS;
 796
 797                 /* Emit the signature cookie just before the implicit arguments */
 798                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 799         }
 800
 801 #ifdef PLATFORM_WIN32
 802         // There always is 32 bytes reserved on the stack when calling on Winx64
 803         stack_size += 0x20;
 804 #endif
 805
 806         if (stack_size & 0x8) {
 807                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 808                 cinfo->need_stack_align = TRUE;
 809                 stack_size += 8;
 810         }
 811
 812         cinfo->stack_usage = stack_size;
 813         cinfo->reg_usage = gr;
 814         cinfo->freg_usage = fr;
 815         return cinfo;
 816 }
 817
 818 /*
 819  * mono_arch_get_argument_info:
 820  * @csig:  a method signature
 821  * @param_count: the number of parameters to consider
 822  * @arg_info: an array to store the result infos
 823  *
 824  * Gathers information on parameters such as size, alignment and
 825  * padding. arg_info should be large enought to hold param_count + 1 entries.
 826  *
 827  * Returns the size of the argument area on the stack.
 828  */
 829 int
 830 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 831 {
 832         int k;
 833         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 834         guint32 args_size = cinfo->stack_usage;
 835
 836         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 837         if (csig->hasthis) {
 838                 arg_info [0].offset = 0;
 839         }
 840
 841         for (k = 0; k < param_count; k++) {
 842                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 843                 /* FIXME: */
 844                 arg_info [k + 1].size = 0;
 845         }
 846
 847         g_free (cinfo);
 848
 849         return args_size;
 850 }
 851
 852 static int
 853 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 854 {
 855 #ifndef _MSC_VER
 856         __asm__ __volatile__ ("cpuid"
 857                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 858                 : "a" (id));
 859 #else
 860         int info[4];
 861         __cpuid(info, id);
 862         *p_eax = info[0];
 863         *p_ebx = info[1];
 864         *p_ecx = info[2];
 865         *p_edx = info[3];
 866 #endif
 867         return 1;
 868 }
 869
 870 /*
 871  * Initialize the cpu to execute managed code.
 872  */
 873 void
 874 mono_arch_cpu_init (void)
 875 {
 876 #ifndef _MSC_VER
 877         guint16 fpcw;
 878
 879         /* spec compliance requires running with double precision */
 880         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 881         fpcw &= ~X86_FPCW_PRECC_MASK;
 882         fpcw |= X86_FPCW_PREC_DOUBLE;
 883         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 884         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 885 #else
 886         /* TODO: This is crashing on Win64 right now.
 887         * _control87 (_PC_53, MCW_PC);
 888         */
 889 #endif
 890 }
 891
 892 /*
 893  * Initialize architecture specific code.
 894  */
 895 void
 896 mono_arch_init (void)
 897 {
 898         InitializeCriticalSection (&mini_arch_mutex);
 899 }
 900
 901 /*
 902  * Cleanup architecture specific code.
 903  */
 904 void
 905 mono_arch_cleanup (void)
 906 {
 907         DeleteCriticalSection (&mini_arch_mutex);
 908 }
 909
 910 /*
 911  * This function returns the optimizations supported on this cpu.
 912  */
 913 guint32
 914 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 915 {
 916         int eax, ebx, ecx, edx;
 917         guint32 opts = 0;
 918
 919         /* FIXME: AMD64 */
 920
 921         *exclude_mask = 0;
 922         /* Feature Flags function, flags returned in EDX. */
 923         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 924                 if (edx & (1 << 15)) {
 925                         opts |= MONO_OPT_CMOV;
 926                         if (edx & 1)
 927                                 opts |= MONO_OPT_FCMOV;
 928                         else
 929                                 *exclude_mask |= MONO_OPT_FCMOV;
 930                 } else
 931                         *exclude_mask |= MONO_OPT_CMOV;
 932         }
 933
 934         return opts;
 935 }
 936
 937 /*
 938  * This function test for all SSE functions supported.
 939  *
 940  * Returns a bitmask corresponding to all supported versions.
 941  *
 942  * TODO detect other versions like SSE4a.
 943  */
 944 guint32
 945 mono_arch_cpu_enumerate_simd_versions (void)
 946 {
 947         int eax, ebx, ecx, edx;
 948         guint32 sse_opts = 0;
 949
 950         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 951                 if (edx & (1 << 25))
 952                         sse_opts |= 1 << SIMD_VERSION_SSE1;
 953                 if (edx & (1 << 26))
 954                         sse_opts |= 1 << SIMD_VERSION_SSE2;
 955                 if (ecx & (1 << 0))
 956                         sse_opts |= 1 << SIMD_VERSION_SSE3;
 957                 if (ecx & (1 << 9))
 958                         sse_opts |= 1 << SIMD_VERSION_SSSE3;
 959                 if (ecx & (1 << 19))
 960                         sse_opts |= 1 << SIMD_VERSION_SSE41;
 961                 if (ecx & (1 << 20))
 962                         sse_opts |= 1 << SIMD_VERSION_SSE42;
 963         }
 964         return sse_opts;
 965 }
 966
 967 GList *
 968 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 969 {
 970         GList *vars = NULL;
 971         int i;
 972
 973         for (i = 0; i < cfg->num_varinfo; i++) {
 974                 MonoInst *ins = cfg->varinfo [i];
 975                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 976
 977                 /* unused vars */
 978                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 979                         continue;
 980
 981                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 982                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 983                         continue;
 984
 985                 if (mono_is_regsize_var (ins->inst_vtype)) {
 986                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 987                         g_assert (i == vmv->idx);
 988                         vars = g_list_prepend (vars, vmv);
 989                 }
 990         }
 991
 992         vars = mono_varlist_sort (cfg, vars, 0);
 993
 994         return vars;
 995 }
 996
 997 /**
 998  * mono_arch_compute_omit_fp:
 999  *
1000  *   Determine whenever the frame pointer can be eliminated.
1001  */
1002 static void
1003 mono_arch_compute_omit_fp (MonoCompile *cfg)
1004 {
1005         MonoMethodSignature *sig;
1006         MonoMethodHeader *header;
1007         int i, locals_size;
1008         CallInfo *cinfo;
1009
1010         if (cfg->arch.omit_fp_computed)
1011                 return;
1012
1013         header = mono_method_get_header (cfg->method);
1014
1015         sig = mono_method_signature (cfg->method);
1016
1017         if (!cfg->arch.cinfo)
1018                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1019         cinfo = cfg->arch.cinfo;
1020
1021         /*
1022          * FIXME: Remove some of the restrictions.
1023          */
1024         cfg->arch.omit_fp = TRUE;
1025         cfg->arch.omit_fp_computed = TRUE;
1026
1027         if (cfg->disable_omit_fp)
1028                 cfg->arch.omit_fp = FALSE;
1029
1030         if (!debug_omit_fp ())
1031                 cfg->arch.omit_fp = FALSE;
1032         /*
1033         if (cfg->method->save_lmf)
1034                 cfg->arch.omit_fp = FALSE;
1035         */
1036         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1037                 cfg->arch.omit_fp = FALSE;
1038         if (header->num_clauses)
1039                 cfg->arch.omit_fp = FALSE;
1040         if (cfg->param_area)
1041                 cfg->arch.omit_fp = FALSE;
1042         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1043                 cfg->arch.omit_fp = FALSE;
1044         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1045                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1046                 cfg->arch.omit_fp = FALSE;
1047         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1048                 ArgInfo *ainfo = &cinfo->args [i];
1049
1050                 if (ainfo->storage == ArgOnStack) {
1051                         /*
1052                          * The stack offset can only be determined when the frame
1053                          * size is known.
1054                          */
1055                         cfg->arch.omit_fp = FALSE;
1056                 }
1057         }
1058
1059         locals_size = 0;
1060         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1061                 MonoInst *ins = cfg->varinfo [i];
1062                 int ialign;
1063
1064                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1065         }
1066 }
1067
1068 GList *
1069 mono_arch_get_global_int_regs (MonoCompile *cfg)
1070 {
1071         GList *regs = NULL;
1072
1073         mono_arch_compute_omit_fp (cfg);
1074
1075         if (cfg->globalra) {
1076                 if (cfg->arch.omit_fp)
1077                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1078
1079                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1080                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1081                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1082                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1083                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1084
1085                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1086                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1087                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1088                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1089                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1090                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1091                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1092                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1093         } else {
1094                 if (cfg->arch.omit_fp)
1095                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1096
1097                 /* We use the callee saved registers for global allocation */
1098                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1099                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1100                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1101                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1102                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1103 #ifdef PLATFORM_WIN32
1104                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1105                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1106 #endif
1107         }
1108
1109         return regs;
1110 }
1111
1112 GList*
1113 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1114 {
1115         GList *regs = NULL;
1116         int i;
1117
1118         /* All XMM registers */
1119         for (i = 0; i < 16; ++i)
1120                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1121
1122         return regs;
1123 }
1124
1125 GList*
1126 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1127 {
1128         static GList *r = NULL;
1129
1130         if (r == NULL) {
1131                 GList *regs = NULL;
1132
1133                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1134                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1135                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1136                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1137                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1138                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1139
1140                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1141                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1142                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1143                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1144                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1145                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1146                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1147                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1148
1149                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1150         }
1151
1152         return r;
1153 }
1154
1155 GList*
1156 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1157 {
1158         int i;
1159         static GList *r = NULL;
1160
1161         if (r == NULL) {
1162                 GList *regs = NULL;
1163
1164                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1165                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1166
1167                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1168         }
1169
1170         return r;
1171 }
1172
1173 /*
1174  * mono_arch_regalloc_cost:
1175  *
1176  *  Return the cost, in number of memory references, of the action of
1177  * allocating the variable VMV into a register during global register
1178  * allocation.
1179  */
1180 guint32
1181 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1182 {
1183         MonoInst *ins = cfg->varinfo [vmv->idx];
1184
1185         if (cfg->method->save_lmf)
1186                 /* The register is already saved */
1187                 /* substract 1 for the invisible store in the prolog */
1188                 return (ins->opcode == OP_ARG) ? 0 : 1;
1189         else
1190                 /* push+pop */
1191                 return (ins->opcode == OP_ARG) ? 1 : 2;
1192 }
1193
1194 /*
1195  * mono_arch_fill_argument_info:
1196  *
1197  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1198  * of the method.
1199  */
1200 void
1201 mono_arch_fill_argument_info (MonoCompile *cfg)
1202 {
1203         MonoMethodSignature *sig;
1204         MonoMethodHeader *header;
1205         MonoInst *ins;
1206         int i;
1207         CallInfo *cinfo;
1208
1209         header = mono_method_get_header (cfg->method);
1210
1211         sig = mono_method_signature (cfg->method);
1212
1213         cinfo = cfg->arch.cinfo;
1214
1215         /*
1216          * Contrary to mono_arch_allocate_vars (), the information should describe
1217          * where the arguments are at the beginning of the method, not where they can be
1218          * accessed during the execution of the method. The later makes no sense for the
1219          * global register allocator, since a variable can be in more than one location.
1220          */
1221         if (sig->ret->type != MONO_TYPE_VOID) {
1222                 switch (cinfo->ret.storage) {
1223                 case ArgInIReg:
1224                 case ArgInFloatSSEReg:
1225                 case ArgInDoubleSSEReg:
1226                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1227                                 cfg->vret_addr->opcode = OP_REGVAR;
1228                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1229                         }
1230                         else {
1231                                 cfg->ret->opcode = OP_REGVAR;
1232                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1233                         }
1234                         break;
1235                 case ArgValuetypeInReg:
1236                         cfg->ret->opcode = OP_REGOFFSET;
1237                         cfg->ret->inst_basereg = -1;
1238                         cfg->ret->inst_offset = -1;
1239                         break;
1240                 default:
1241                         g_assert_not_reached ();
1242                 }
1243         }
1244
1245         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1246                 ArgInfo *ainfo = &cinfo->args [i];
1247                 MonoType *arg_type;
1248
1249                 ins = cfg->args [i];
1250
1251                 if (sig->hasthis && (i == 0))
1252                         arg_type = &mono_defaults.object_class->byval_arg;
1253                 else
1254                         arg_type = sig->params [i - sig->hasthis];
1255
1256                 switch (ainfo->storage) {
1257                 case ArgInIReg:
1258                 case ArgInFloatSSEReg:
1259                 case ArgInDoubleSSEReg:
1260                         ins->opcode = OP_REGVAR;
1261                         ins->inst_c0 = ainfo->reg;
1262                         break;
1263                 case ArgOnStack:
1264                         ins->opcode = OP_REGOFFSET;
1265                         ins->inst_basereg = -1;
1266                         ins->inst_offset = -1;
1267                         break;
1268                 case ArgValuetypeInReg:
1269                         /* Dummy */
1270                         ins->opcode = OP_NOP;
1271                         break;
1272                 default:
1273                         g_assert_not_reached ();
1274                 }
1275         }
1276 }
1277
1278 void
1279 mono_arch_allocate_vars (MonoCompile *cfg)
1280 {
1281         MonoMethodSignature *sig;
1282         MonoMethodHeader *header;
1283         MonoInst *ins;
1284         int i, offset;
1285         guint32 locals_stack_size, locals_stack_align;
1286         gint32 *offsets;
1287         CallInfo *cinfo;
1288
1289         header = mono_method_get_header (cfg->method);
1290
1291         sig = mono_method_signature (cfg->method);
1292
1293         cinfo = cfg->arch.cinfo;
1294
1295         mono_arch_compute_omit_fp (cfg);
1296
1297         /*
1298          * We use the ABI calling conventions for managed code as well.
1299          * Exception: valuetypes are only sometimes passed or returned in registers.
1300          */
1301
1302         /*
1303          * The stack looks like this:
1304          * <incoming arguments passed on the stack>
1305          * <return value>
1306          * <lmf/caller saved registers>
1307          * <locals>
1308          * <spill area>
1309          * <localloc area>  -> grows dynamically
1310          * <params area>
1311          */
1312
1313         if (cfg->arch.omit_fp) {
1314                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1315                 cfg->frame_reg = AMD64_RSP;
1316                 offset = 0;
1317         } else {
1318                 /* Locals are allocated backwards from %fp */
1319                 cfg->frame_reg = AMD64_RBP;
1320                 offset = 0;
1321         }
1322
1323         if (cfg->method->save_lmf) {
1324                 /* Reserve stack space for saving LMF */
1325                 if (cfg->arch.omit_fp) {
1326                         cfg->arch.lmf_offset = offset;
1327                         offset += sizeof (MonoLMF);
1328                 }
1329                 else {
1330                         offset += sizeof (MonoLMF);
1331                         cfg->arch.lmf_offset = -offset;
1332                 }
1333         } else {
1334                 if (cfg->arch.omit_fp)
1335                         cfg->arch.reg_save_area_offset = offset;
1336                 /* Reserve space for caller saved registers */
1337                 for (i = 0; i < AMD64_NREG; ++i)
1338                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1339                                 offset += sizeof (gpointer);
1340                         }
1341         }
1342
1343         if (sig->ret->type != MONO_TYPE_VOID) {
1344                 switch (cinfo->ret.storage) {
1345                 case ArgInIReg:
1346                 case ArgInFloatSSEReg:
1347                 case ArgInDoubleSSEReg:
1348                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1349                                 if (cfg->globalra) {
1350                                         cfg->vret_addr->opcode = OP_REGVAR;
1351                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1352                                 } else {
1353                                         /* The register is volatile */
1354                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1355                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1356                                         if (cfg->arch.omit_fp) {
1357                                                 cfg->vret_addr->inst_offset = offset;
1358                                                 offset += 8;
1359                                         } else {
1360                                                 offset += 8;
1361                                                 cfg->vret_addr->inst_offset = -offset;
1362                                         }
1363                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1364                                                 printf ("vret_addr =");
1365                                                 mono_print_ins (cfg->vret_addr);
1366                                         }
1367                                 }
1368                         }
1369                         else {
1370                                 cfg->ret->opcode = OP_REGVAR;
1371                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1372                         }
1373                         break;
1374                 case ArgValuetypeInReg:
1375                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1376                         cfg->ret->opcode = OP_REGOFFSET;
1377                         cfg->ret->inst_basereg = cfg->frame_reg;
1378                         if (cfg->arch.omit_fp) {
1379                                 cfg->ret->inst_offset = offset;
1380                                 offset += 16;
1381                         } else {
1382                                 offset += 16;
1383                                 cfg->ret->inst_offset = - offset;
1384                         }
1385                         break;
1386                 default:
1387                         g_assert_not_reached ();
1388                 }
1389                 if (!cfg->globalra)
1390                         cfg->ret->dreg = cfg->ret->inst_c0;
1391         }
1392
1393         /* Allocate locals */
1394         if (!cfg->globalra) {
1395                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1396                 if (locals_stack_align) {
1397                         offset += (locals_stack_align - 1);
1398                         offset &= ~(locals_stack_align - 1);
1399                 }
1400                 if (cfg->arch.omit_fp) {
1401                         cfg->locals_min_stack_offset = offset;
1402                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1403                 } else {
1404                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1405                         cfg->locals_max_stack_offset = - offset;
1406                 }
1407
1408                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1409                         if (offsets [i] != -1) {
1410                                 MonoInst *ins = cfg->varinfo [i];
1411                                 ins->opcode = OP_REGOFFSET;
1412                                 ins->inst_basereg = cfg->frame_reg;
1413                                 if (cfg->arch.omit_fp)
1414                                         ins->inst_offset = (offset + offsets [i]);
1415                                 else
1416                                         ins->inst_offset = - (offset + offsets [i]);
1417                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1418                         }
1419                 }
1420                 offset += locals_stack_size;
1421         }
1422
1423         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1424                 g_assert (!cfg->arch.omit_fp);
1425                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1426                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1427         }
1428
1429         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1430                 ins = cfg->args [i];
1431                 if (ins->opcode != OP_REGVAR) {
1432                         ArgInfo *ainfo = &cinfo->args [i];
1433                         gboolean inreg = TRUE;
1434                         MonoType *arg_type;
1435
1436                         if (sig->hasthis && (i == 0))
1437                                 arg_type = &mono_defaults.object_class->byval_arg;
1438                         else
1439                                 arg_type = sig->params [i - sig->hasthis];
1440
1441                         if (cfg->globalra) {
1442                                 /* The new allocator needs info about the original locations of the arguments */
1443                                 switch (ainfo->storage) {
1444                                 case ArgInIReg:
1445                                 case ArgInFloatSSEReg:
1446                                 case ArgInDoubleSSEReg:
1447                                         ins->opcode = OP_REGVAR;
1448                                         ins->inst_c0 = ainfo->reg;
1449                                         break;
1450                                 case ArgOnStack:
1451                                         g_assert (!cfg->arch.omit_fp);
1452                                         ins->opcode = OP_REGOFFSET;
1453                                         ins->inst_basereg = cfg->frame_reg;
1454                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1455                                         break;
1456                                 case ArgValuetypeInReg:
1457                                         ins->opcode = OP_REGOFFSET;
1458                                         ins->inst_basereg = cfg->frame_reg;
1459                                         /* These arguments are saved to the stack in the prolog */
1460                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1461                                         if (cfg->arch.omit_fp) {
1462                                                 ins->inst_offset = offset;
1463                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1464                                         } else {
1465                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1466                                                 ins->inst_offset = - offset;
1467                                         }
1468                                         break;
1469                                 default:
1470                                         g_assert_not_reached ();
1471                                 }
1472
1473                                 continue;
1474                         }
1475
1476                         /* FIXME: Allocate volatile arguments to registers */
1477                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1478                                 inreg = FALSE;
1479
1480                         /*
1481                          * Under AMD64, all registers used to pass arguments to functions
1482                          * are volatile across calls.
1483                          * FIXME: Optimize this.
1484                          */
1485                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1486                                 inreg = FALSE;
1487
1488                         ins->opcode = OP_REGOFFSET;
1489
1490                         switch (ainfo->storage) {
1491                         case ArgInIReg:
1492                         case ArgInFloatSSEReg:
1493                         case ArgInDoubleSSEReg:
1494                                 if (inreg) {
1495                                         ins->opcode = OP_REGVAR;
1496                                         ins->dreg = ainfo->reg;
1497                                 }
1498                                 break;
1499                         case ArgOnStack:
1500                                 g_assert (!cfg->arch.omit_fp);
1501                                 ins->opcode = OP_REGOFFSET;
1502                                 ins->inst_basereg = cfg->frame_reg;
1503                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1504                                 break;
1505                         case ArgValuetypeInReg:
1506                                 break;
1507                         case ArgValuetypeAddrInIReg: {
1508                                 MonoInst *indir;
1509                                 g_assert (!cfg->arch.omit_fp);
1510
1511                                 MONO_INST_NEW (cfg, indir, 0);
1512                                 indir->opcode = OP_REGOFFSET;
1513                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1514                                         indir->inst_basereg = cfg->frame_reg;
1515                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1516                                         offset += (sizeof (gpointer));
1517                                         indir->inst_offset = - offset;
1518                                 }
1519                                 else {
1520                                         indir->inst_basereg = cfg->frame_reg;
1521                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1522                                 }
1523
1524                                 ins->opcode = OP_VTARG_ADDR;
1525                                 ins->inst_left = indir;
1526
1527                                 break;
1528                         }
1529                         default:
1530                                 NOT_IMPLEMENTED;
1531                         }
1532
1533                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1534                                 ins->opcode = OP_REGOFFSET;
1535                                 ins->inst_basereg = cfg->frame_reg;
1536                                 /* These arguments are saved to the stack in the prolog */
1537                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1538                                 if (cfg->arch.omit_fp) {
1539                                         ins->inst_offset = offset;
1540                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1541                                 } else {
1542                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1543                                         ins->inst_offset = - offset;
1544                                 }
1545                         }
1546                 }
1547         }
1548
1549         cfg->stack_offset = offset;
1550 }
1551
1552 void
1553 mono_arch_create_vars (MonoCompile *cfg)
1554 {
1555         MonoMethodSignature *sig;
1556         CallInfo *cinfo;
1557
1558         sig = mono_method_signature (cfg->method);
1559
1560         if (!cfg->arch.cinfo)
1561                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1562         cinfo = cfg->arch.cinfo;
1563
1564         if (cinfo->ret.storage == ArgValuetypeInReg)
1565                 cfg->ret_var_is_local = TRUE;
1566
1567         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1568                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1569                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1570                         printf ("vret_addr = ");
1571                         mono_print_ins (cfg->vret_addr);
1572                 }
1573         }
1574
1575 #ifdef MONO_AMD64_NO_PUSHES
1576         /*
1577          * When this is set, we pass arguments on the stack by moves, and by allocating
1578          * a bigger stack frame, instead of pushes.
1579          * Pushes complicate exception handling because the arguments on the stack have
1580          * to be popped each time a frame is unwound. They also make fp elimination
1581          * impossible.
1582          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1583          * on a new frame which doesn't include a param area.
1584          */
1585         cfg->arch.no_pushes = TRUE;
1586 #endif
1587 }
1588
1589 static void
1590 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1591 {
1592         MonoInst *ins;
1593
1594         switch (storage) {
1595         case ArgInIReg:
1596                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1597                 ins->dreg = mono_alloc_ireg (cfg);
1598                 ins->sreg1 = tree->dreg;
1599                 MONO_ADD_INS (cfg->cbb, ins);
1600                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1601                 break;
1602         case ArgInFloatSSEReg:
1603                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1604                 ins->dreg = mono_alloc_freg (cfg);
1605                 ins->sreg1 = tree->dreg;
1606                 MONO_ADD_INS (cfg->cbb, ins);
1607
1608                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1609                 break;
1610         case ArgInDoubleSSEReg:
1611                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1612                 ins->dreg = mono_alloc_freg (cfg);
1613                 ins->sreg1 = tree->dreg;
1614                 MONO_ADD_INS (cfg->cbb, ins);
1615
1616                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1617
1618                 break;
1619         default:
1620                 g_assert_not_reached ();
1621         }
1622 }
1623
1624 static int
1625 arg_storage_to_load_membase (ArgStorage storage)
1626 {
1627         switch (storage) {
1628         case ArgInIReg:
1629                 return OP_LOAD_MEMBASE;
1630         case ArgInDoubleSSEReg:
1631                 return OP_LOADR8_MEMBASE;
1632         case ArgInFloatSSEReg:
1633                 return OP_LOADR4_MEMBASE;
1634         default:
1635                 g_assert_not_reached ();
1636         }
1637
1638         return -1;
1639 }
1640
1641 static void
1642 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1643 {
1644         MonoInst *arg;
1645         MonoMethodSignature *tmp_sig;
1646         MonoInst *sig_arg;
1647
1648         if (call->tail_call)
1649                 NOT_IMPLEMENTED;
1650
1651         /* FIXME: Add support for signature tokens to AOT */
1652         cfg->disable_aot = TRUE;
1653
1654         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1655
1656         /*
1657          * mono_ArgIterator_Setup assumes the signature cookie is
1658          * passed first and all the arguments which were before it are
1659          * passed on the stack after the signature. So compensate by
1660          * passing a different signature.
1661          */
1662         tmp_sig = mono_metadata_signature_dup (call->signature);
1663         tmp_sig->param_count -= call->signature->sentinelpos;
1664         tmp_sig->sentinelpos = 0;
1665         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1666
1667         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1668         sig_arg->dreg = mono_alloc_ireg (cfg);
1669         sig_arg->inst_p0 = tmp_sig;
1670         MONO_ADD_INS (cfg->cbb, sig_arg);
1671
1672         if (cfg->arch.no_pushes) {
1673                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1674         } else {
1675                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1676                 arg->sreg1 = sig_arg->dreg;
1677                 MONO_ADD_INS (cfg->cbb, arg);
1678         }
1679 }
1680
1681 static inline LLVMArgStorage
1682 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1683 {
1684         switch (storage) {
1685         case ArgInIReg:
1686                 return LLVMArgInIReg;
1687         case ArgNone:
1688                 return LLVMArgNone;
1689         default:
1690                 g_assert_not_reached ();
1691                 return LLVMArgNone;
1692         }
1693 }
1694
1695 #ifdef ENABLE_LLVM
1696 LLVMCallInfo*
1697 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1698 {
1699         int i, n;
1700         CallInfo *cinfo;
1701         ArgInfo *ainfo;
1702         int j;
1703         LLVMCallInfo *linfo;
1704
1705         n = sig->param_count + sig->hasthis;
1706
1707         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1708
1709         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1710
1711         /*
1712          * LLVM always uses the native ABI while we use our own ABI, the
1713          * only difference is the handling of vtypes:
1714          * - we only pass/receive them in registers in some cases, and only
1715          *   in 1 or 2 integer registers.
1716          */
1717         if (cinfo->ret.storage == ArgValuetypeInReg) {
1718                 if (sig->pinvoke) {
1719                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1720                         cfg->disable_llvm = TRUE;
1721                         return linfo;
1722                 }
1723
1724                 linfo->ret.storage = LLVMArgVtypeInReg;
1725                 for (j = 0; j < 2; ++j)
1726                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1727         }
1728
1729         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1730                 /* Vtype returned using a hidden argument */
1731                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1732         }
1733
1734         for (i = 0; i < n; ++i) {
1735                 ainfo = cinfo->args + i;
1736
1737                 linfo->args [i].storage = LLVMArgNone;
1738
1739                 switch (ainfo->storage) {
1740                 case ArgInIReg:
1741                         linfo->args [i].storage = LLVMArgInIReg;
1742                         break;
1743                 case ArgInDoubleSSEReg:
1744                 case ArgInFloatSSEReg:
1745                         linfo->args [i].storage = LLVMArgInFPReg;
1746                         break;
1747                 case ArgOnStack:
1748                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1749                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1750                         } else {
1751                                 linfo->args [i].storage = LLVMArgInIReg;
1752                                 if (!sig->params [i - sig->hasthis]->byref) {
1753                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1754                                                 linfo->args [i].storage = LLVMArgInFPReg;
1755                                         } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1756                                                 linfo->args [i].storage = LLVMArgInFPReg;
1757                                         }
1758                                 }
1759                         }
1760                         break;
1761                 case ArgValuetypeInReg:
1762                         if (sig->pinvoke) {
1763                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1764                                 cfg->disable_llvm = TRUE;
1765                                 return linfo;
1766                         }
1767
1768                         linfo->args [i].storage = LLVMArgVtypeInReg;
1769                         for (j = 0; j < 2; ++j)
1770                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1771                         break;
1772                 default:
1773                         cfg->exception_message = g_strdup ("ainfo->storage");
1774                         cfg->disable_llvm = TRUE;
1775                         break;
1776                 }
1777         }
1778
1779         return linfo;
1780 }
1781 #endif
1782
1783 void
1784 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1785 {
1786         MonoInst *arg, *in;
1787         MonoMethodSignature *sig;
1788         int i, n, stack_size;
1789         CallInfo *cinfo;
1790         ArgInfo *ainfo;
1791
1792         stack_size = 0;
1793
1794         sig = call->signature;
1795         n = sig->param_count + sig->hasthis;
1796
1797         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1798
1799         if (COMPILE_LLVM (cfg)) {
1800                 /* We shouldn't be called in the llvm case */
1801                 cfg->disable_llvm = TRUE;
1802                 return;
1803         }
1804
1805         if (cinfo->need_stack_align) {
1806                 if (!cfg->arch.no_pushes)
1807                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1808         }
1809
1810         /*
1811          * Emit all arguments which are passed on the stack to prevent register
1812          * allocation problems.
1813          */
1814         if (cfg->arch.no_pushes) {
1815                 for (i = 0; i < n; ++i) {
1816                         MonoType *t;
1817                         ainfo = cinfo->args + i;
1818
1819                         in = call->args [i];
1820
1821                         if (sig->hasthis && i == 0)
1822                                 t = &mono_defaults.object_class->byval_arg;
1823                         else
1824                                 t = sig->params [i - sig->hasthis];
1825
1826                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1827                                 if (!t->byref) {
1828                                         if (t->type == MONO_TYPE_R4)
1829                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1830                                         else if (t->type == MONO_TYPE_R8)
1831                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1832                                         else
1833                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1834                                 } else {
1835                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1836                                 }
1837                         }
1838                 }
1839         }
1840
1841         /*
1842          * Emit all parameters passed in registers in non-reverse order for better readability
1843          * and to help the optimization in emit_prolog ().
1844          */
1845         for (i = 0; i < n; ++i) {
1846                 ainfo = cinfo->args + i;
1847
1848                 in = call->args [i];
1849
1850                 if (ainfo->storage == ArgInIReg)
1851                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1852         }
1853
1854         for (i = n - 1; i >= 0; --i) {
1855                 ainfo = cinfo->args + i;
1856
1857                 in = call->args [i];
1858
1859                 switch (ainfo->storage) {
1860                 case ArgInIReg:
1861                         /* Already done */
1862                         break;
1863                 case ArgInFloatSSEReg:
1864                 case ArgInDoubleSSEReg:
1865                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1866                         break;
1867                 case ArgOnStack:
1868                 case ArgValuetypeInReg:
1869                 case ArgValuetypeAddrInIReg:
1870                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1871                                 MonoInst *call_inst = (MonoInst*)call;
1872                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1873                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1874                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1875                                 guint32 align;
1876                                 guint32 size;
1877
1878                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1879                                         size = sizeof (MonoTypedRef);
1880                                         align = sizeof (gpointer);
1881                                 }
1882                                 else {
1883                                         if (sig->pinvoke)
1884                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1885                                         else {
1886                                                 /*
1887                                                  * Other backends use mono_type_stack_size (), but that
1888                                                  * aligns the size to 8, which is larger than the size of
1889                                                  * the source, leading to reads of invalid memory if the
1890                                                  * source is at the end of address space.
1891                                                  */
1892                                                 size = mono_class_value_size (in->klass, &align);
1893                                         }
1894                                 }
1895                                 g_assert (in->klass);
1896
1897                                 if (size > 0) {
1898                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
1899                                         arg->sreg1 = in->dreg;
1900                                         arg->klass = in->klass;
1901                                         arg->backend.size = size;
1902                                         arg->inst_p0 = call;
1903                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
1904                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
1905
1906                                         MONO_ADD_INS (cfg->cbb, arg);
1907                                 }
1908                         } else {
1909                                 if (cfg->arch.no_pushes) {
1910                                         /* Already done */
1911                                 } else {
1912                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1913                                         arg->sreg1 = in->dreg;
1914                                         if (!sig->params [i - sig->hasthis]->byref) {
1915                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
1916                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1917                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
1918                                                         arg->inst_destbasereg = X86_ESP;
1919                                                         arg->inst_offset = 0;
1920                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
1921                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1922                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
1923                                                         arg->inst_destbasereg = X86_ESP;
1924                                                         arg->inst_offset = 0;
1925                                                 }
1926                                         }
1927                                         MONO_ADD_INS (cfg->cbb, arg);
1928                                 }
1929                         }
1930                         break;
1931                 default:
1932                         g_assert_not_reached ();
1933                 }
1934
1935                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
1936                         /* Emit the signature cookie just before the implicit arguments */
1937                         emit_sig_cookie (cfg, call, cinfo);
1938         }
1939
1940         /* Handle the case where there are no implicit arguments */
1941         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
1942                 emit_sig_cookie (cfg, call, cinfo);
1943
1944         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
1945                 MonoInst *vtarg;
1946
1947                 if (cinfo->ret.storage == ArgValuetypeInReg) {
1948                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
1949                                 /*
1950                                  * Tell the JIT to use a more efficient calling convention: call using
1951                                  * OP_CALL, compute the result location after the call, and save the
1952                                  * result there.
1953                                  */
1954                                 call->vret_in_reg = TRUE;
1955                                 /*
1956                                  * Nullify the instruction computing the vret addr to enable
1957                                  * future optimizations.
1958                                  */
1959                                 if (call->vret_var)
1960                                         NULLIFY_INS (call->vret_var);
1961                         } else {
1962                                 if (call->tail_call)
1963                                         NOT_IMPLEMENTED;
1964                                 /*
1965                                  * The valuetype is in RAX:RDX after the call, need to be copied to
1966                                  * the stack. Push the address here, so the call instruction can
1967                                  * access it.
1968                                  */
1969                                 if (!cfg->arch.vret_addr_loc) {
1970                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1971                                         /* Prevent it from being register allocated or optimized away */
1972                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1973                                 }
1974
1975                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
1976                         }
1977                 }
1978                 else {
1979                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
1980                         vtarg->sreg1 = call->vret_var->dreg;
1981                         vtarg->dreg = mono_alloc_preg (cfg);
1982                         MONO_ADD_INS (cfg->cbb, vtarg);
1983
1984                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
1985                 }
1986         }
1987
1988 #ifdef PLATFORM_WIN32
1989         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
1990                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
1991         }
1992 #endif
1993
1994         if (cfg->method->save_lmf) {
1995                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1996                 MONO_ADD_INS (cfg->cbb, arg);
1997         }
1998
1999         call->stack_usage = cinfo->stack_usage;
2000 }
2001
2002 void
2003 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2004 {
2005         MonoInst *arg;
2006         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2007         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2008         int size = ins->backend.size;
2009
2010         if (ainfo->storage == ArgValuetypeInReg) {
2011                 MonoInst *load;
2012                 int part;
2013
2014                 for (part = 0; part < 2; ++part) {
2015                         if (ainfo->pair_storage [part] == ArgNone)
2016                                 continue;
2017
2018                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2019                         load->inst_basereg = src->dreg;
2020                         load->inst_offset = part * sizeof (gpointer);
2021
2022                         switch (ainfo->pair_storage [part]) {
2023                         case ArgInIReg:
2024                                 load->dreg = mono_alloc_ireg (cfg);
2025                                 break;
2026                         case ArgInDoubleSSEReg:
2027                         case ArgInFloatSSEReg:
2028                                 load->dreg = mono_alloc_freg (cfg);
2029                                 break;
2030                         default:
2031                                 g_assert_not_reached ();
2032                         }
2033                         MONO_ADD_INS (cfg->cbb, load);
2034
2035                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2036                 }
2037         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2038                 MonoInst *vtaddr, *load;
2039                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2040
2041                 g_assert (!cfg->arch.no_pushes);
2042
2043                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2044                 load->inst_p0 = vtaddr;
2045                 vtaddr->flags |= MONO_INST_INDIRECT;
2046                 load->type = STACK_MP;
2047                 load->klass = vtaddr->klass;
2048                 load->dreg = mono_alloc_ireg (cfg);
2049                 MONO_ADD_INS (cfg->cbb, load);
2050                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2051
2052                 if (ainfo->pair_storage [0] == ArgInIReg) {
2053                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2054                         arg->dreg = mono_alloc_ireg (cfg);
2055                         arg->sreg1 = load->dreg;
2056                         arg->inst_imm = 0;
2057                         MONO_ADD_INS (cfg->cbb, arg);
2058                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2059                 } else {
2060                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2061                         arg->sreg1 = load->dreg;
2062                         MONO_ADD_INS (cfg->cbb, arg);
2063                 }
2064         } else {
2065                 if (size == 8) {
2066                         if (cfg->arch.no_pushes) {
2067                                 int dreg = mono_alloc_ireg (cfg);
2068
2069                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2070                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2071                         } else {
2072                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2073                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2074                                 arg->inst_basereg = src->dreg;
2075                                 arg->inst_offset = 0;
2076                                 MONO_ADD_INS (cfg->cbb, arg);
2077                         }
2078                 } else if (size <= 40) {
2079                         if (cfg->arch.no_pushes) {
2080                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2081                         } else {
2082                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2083                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2084                         }
2085                 } else {
2086                         if (cfg->arch.no_pushes) {
2087                                 // FIXME: Code growth
2088                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2089                         } else {
2090                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2091                                 arg->inst_basereg = src->dreg;
2092                                 arg->inst_offset = 0;
2093                                 arg->inst_imm = size;
2094                                 MONO_ADD_INS (cfg->cbb, arg);
2095                         }
2096                 }
2097         }
2098 }
2099
2100 void
2101 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2102 {
2103         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2104
2105         if (!ret->byref) {
2106                 if (ret->type == MONO_TYPE_R4) {
2107                         if (COMPILE_LLVM (cfg))
2108                                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2109                         else
2110                                 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2111                         return;
2112                 } else if (ret->type == MONO_TYPE_R8) {
2113                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2114                         return;
2115                 }
2116         }
2117
2118         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2119 }
2120
2121 #define EMIT_COND_BRANCH(ins,cond,sign) \
2122         if (ins->inst_true_bb->native_offset) { \
2123                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2124         } else { \
2125                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2126                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2127             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2128                         x86_branch8 (code, cond, 0, sign); \
2129                 else \
2130                         x86_branch32 (code, cond, 0, sign); \
2131 }
2132
2133 typedef struct {
2134         MonoMethodSignature *sig;
2135         CallInfo *cinfo;
2136 } ArchDynCallInfo;
2137
2138 typedef struct {
2139         mgreg_t regs [PARAM_REGS];
2140         mgreg_t res;
2141         guint8 *ret;
2142 } DynCallArgs;
2143
2144 static gboolean
2145 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2146 {
2147         int i;
2148
2149 #ifdef PLATFORM_WIN32
2150         return FALSE;
2151 #endif
2152
2153         switch (cinfo->ret.storage) {
2154         case ArgNone:
2155         case ArgInIReg:
2156                 break;
2157         case ArgValuetypeInReg: {
2158                 ArgInfo *ainfo = &cinfo->ret;
2159
2160                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2161                         return FALSE;
2162                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2163                         return FALSE;
2164                 break;
2165         }
2166         default:
2167                 return FALSE;
2168         }
2169
2170         for (i = 0; i < cinfo->nargs; ++i) {
2171                 ArgInfo *ainfo = &cinfo->args [i];
2172                 switch (ainfo->storage) {
2173                 case ArgInIReg:
2174                         break;
2175                 case ArgValuetypeInReg:
2176                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2177                                 return FALSE;
2178                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2179                                 return FALSE;
2180                         break;
2181                 default:
2182                         return FALSE;
2183                 }
2184         }
2185
2186         return TRUE;
2187 }
2188
2189 /*
2190  * mono_arch_dyn_call_prepare:
2191  *
2192  *   Return a pointer to an arch-specific structure which contains information
2193  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2194  * supported for SIG.
2195  * This function is equivalent to ffi_prep_cif in libffi.
2196  */
2197 MonoDynCallInfo*
2198 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2199 {
2200         ArchDynCallInfo *info;
2201         CallInfo *cinfo;
2202
2203         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2204
2205         if (!dyn_call_supported (sig, cinfo)) {
2206                 g_free (cinfo);
2207                 return NULL;
2208         }
2209
2210         info = g_new0 (ArchDynCallInfo, 1);
2211         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2212         info->sig = sig;
2213         info->cinfo = cinfo;
2214
2215         return (MonoDynCallInfo*)info;
2216 }
2217
2218 /*
2219  * mono_arch_dyn_call_free:
2220  *
2221  *   Free a MonoDynCallInfo structure.
2222  */
2223 void
2224 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2225 {
2226         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2227
2228         g_free (ainfo->cinfo);
2229         g_free (ainfo);
2230 }
2231
2232 /*
2233  * mono_arch_get_start_dyn_call:
2234  *
2235  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2236  * store the result into BUF.
2237  * ARGS should be an array of pointers pointing to the arguments.
2238  * RET should point to a memory buffer large enought to hold the result of the
2239  * call.
2240  * This function should be as fast as possible, any work which does not depend
2241  * on the actual values of the arguments should be done in
2242  * mono_arch_dyn_call_prepare ().
2243  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2244  * libffi.
2245  */
2246 void
2247 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2248 {
2249         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2250         DynCallArgs *p = (DynCallArgs*)buf;
2251         int arg_index, greg, i;
2252         MonoMethodSignature *sig = dinfo->sig;
2253
2254         g_assert (buf_len >= sizeof (DynCallArgs));
2255
2256         p->res = 0;
2257         p->ret = ret;
2258
2259         arg_index = 0;
2260         greg = 0;
2261
2262         if (dinfo->cinfo->vtype_retaddr)
2263                 p->regs [greg ++] = (mgreg_t)ret;
2264
2265         if (sig->hasthis) {
2266                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2267         }
2268
2269         for (i = 0; i < sig->param_count; i++) {
2270                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2271                 gpointer *arg = args [arg_index ++];
2272
2273                 if (t->byref) {
2274                         p->regs [greg ++] = (mgreg_t)*(arg);
2275                         continue;
2276                 }
2277
2278                 switch (t->type) {
2279                 case MONO_TYPE_STRING:
2280                 case MONO_TYPE_CLASS:
2281                 case MONO_TYPE_ARRAY:
2282                 case MONO_TYPE_SZARRAY:
2283                 case MONO_TYPE_OBJECT:
2284                 case MONO_TYPE_PTR:
2285                 case MONO_TYPE_I:
2286                 case MONO_TYPE_U:
2287                 case MONO_TYPE_I8:
2288                 case MONO_TYPE_U8:
2289                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2290                         p->regs [greg ++] = (mgreg_t)*(arg);
2291                         break;
2292                 case MONO_TYPE_BOOLEAN:
2293                 case MONO_TYPE_U1:
2294                         p->regs [greg ++] = *(guint8*)(arg);
2295                         break;
2296                 case MONO_TYPE_I1:
2297                         p->regs [greg ++] = *(gint8*)(arg);
2298                         break;
2299                 case MONO_TYPE_I2:
2300                         p->regs [greg ++] = *(gint16*)(arg);
2301                         break;
2302                 case MONO_TYPE_U2:
2303                 case MONO_TYPE_CHAR:
2304                         p->regs [greg ++] = *(guint16*)(arg);
2305                         break;
2306                 case MONO_TYPE_I4:
2307                         p->regs [greg ++] = *(gint32*)(arg);
2308                         break;
2309                 case MONO_TYPE_U4:
2310                         p->regs [greg ++] = *(guint32*)(arg);
2311                         break;
2312                 case MONO_TYPE_GENERICINST:
2313                     if (MONO_TYPE_IS_REFERENCE (t)) {
2314                                 p->regs [greg ++] = (mgreg_t)*(arg);
2315                                 break;
2316                         } else {
2317                                 /* Fall through */
2318                         }
2319                 case MONO_TYPE_VALUETYPE: {
2320                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2321
2322                         g_assert (ainfo->storage == ArgValuetypeInReg);
2323                         if (ainfo->pair_storage [0] != ArgNone) {
2324                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2325                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2326                         }
2327                         if (ainfo->pair_storage [1] != ArgNone) {
2328                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2329                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2330                         }
2331                         break;
2332                 }
2333                 default:
2334                         g_assert_not_reached ();
2335                 }
2336         }
2337
2338         g_assert (greg <= PARAM_REGS);
2339 }
2340
2341 /*
2342  * mono_arch_finish_dyn_call:
2343  *
2344  *   Store the result of a dyn call into the return value buffer passed to
2345  * start_dyn_call ().
2346  * This function should be as fast as possible, any work which does not depend
2347  * on the actual values of the arguments should be done in
2348  * mono_arch_dyn_call_prepare ().
2349  */
2350 void
2351 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2352 {
2353         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2354         MonoMethodSignature *sig = dinfo->sig;
2355         guint8 *ret = ((DynCallArgs*)buf)->ret;
2356         mgreg_t res = ((DynCallArgs*)buf)->res;
2357
2358         switch (mono_type_get_underlying_type (sig->ret)->type) {
2359         case MONO_TYPE_VOID:
2360                 *(gpointer*)ret = NULL;
2361                 break;
2362         case MONO_TYPE_STRING:
2363         case MONO_TYPE_CLASS:
2364         case MONO_TYPE_ARRAY:
2365         case MONO_TYPE_SZARRAY:
2366         case MONO_TYPE_OBJECT:
2367         case MONO_TYPE_I:
2368         case MONO_TYPE_U:
2369         case MONO_TYPE_PTR:
2370                 *(gpointer*)ret = (gpointer)res;
2371                 break;
2372         case MONO_TYPE_I1:
2373                 *(gint8*)ret = res;
2374                 break;
2375         case MONO_TYPE_U1:
2376         case MONO_TYPE_BOOLEAN:
2377                 *(guint8*)ret = res;
2378                 break;
2379         case MONO_TYPE_I2:
2380                 *(gint16*)ret = res;
2381                 break;
2382         case MONO_TYPE_U2:
2383         case MONO_TYPE_CHAR:
2384                 *(guint16*)ret = res;
2385                 break;
2386         case MONO_TYPE_I4:
2387                 *(gint32*)ret = res;
2388                 break;
2389         case MONO_TYPE_U4:
2390                 *(guint32*)ret = res;
2391                 break;
2392         case MONO_TYPE_I8:
2393                 *(gint64*)ret = res;
2394                 break;
2395         case MONO_TYPE_U8:
2396                 *(guint64*)ret = res;
2397                 break;
2398         case MONO_TYPE_GENERICINST:
2399                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2400                         *(gpointer*)ret = (gpointer)res;
2401                         break;
2402                 } else {
2403                         /* Fall through */
2404                 }
2405         case MONO_TYPE_VALUETYPE:
2406                 if (dinfo->cinfo->vtype_retaddr) {
2407                         /* Nothing to do */
2408                 } else {
2409                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2410
2411                         g_assert (ainfo->storage == ArgValuetypeInReg);
2412
2413                         if (ainfo->pair_storage [0] != ArgNone) {
2414                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2415                                 ((mgreg_t*)ret)[0] = res;
2416                         }
2417
2418                         g_assert (ainfo->pair_storage [1] == ArgNone);
2419                 }
2420                 break;
2421         default:
2422                 g_assert_not_reached ();
2423         }
2424 }
2425
2426 /* emit an exception if condition is fail */
2427 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2428         do {                                                        \
2429                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2430                 if (tins == NULL) {                                                                             \
2431                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2432                                         MONO_PATCH_INFO_EXC, exc_name);  \
2433                         x86_branch32 (code, cond, 0, signed);               \
2434                 } else {        \
2435                         EMIT_COND_BRANCH (tins, cond, signed);  \
2436                 }                       \
2437         } while (0);
2438
2439 #define EMIT_FPCOMPARE(code) do { \
2440         amd64_fcompp (code); \
2441         amd64_fnstsw (code); \
2442 } while (0);
2443
2444 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2445     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2446         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2447         amd64_ ##op (code); \
2448         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2449         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2450 } while (0);
2451
2452 static guint8*
2453 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2454 {
2455         gboolean no_patch = FALSE;
2456
2457         /*
2458          * FIXME: Add support for thunks
2459          */
2460         {
2461                 gboolean near_call = FALSE;
2462
2463                 /*
2464                  * Indirect calls are expensive so try to make a near call if possible.
2465                  * The caller memory is allocated by the code manager so it is
2466                  * guaranteed to be at a 32 bit offset.
2467                  */
2468
2469                 if (patch_type != MONO_PATCH_INFO_ABS) {
2470                         /* The target is in memory allocated using the code manager */
2471                         near_call = TRUE;
2472
2473                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2474                                 if (((MonoMethod*)data)->klass->image->aot_module)
2475                                         /* The callee might be an AOT method */
2476                                         near_call = FALSE;
2477                                 if (((MonoMethod*)data)->dynamic)
2478                                         /* The target is in malloc-ed memory */
2479                                         near_call = FALSE;
2480                         }
2481
2482                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2483                                 /*
2484                                  * The call might go directly to a native function without
2485                                  * the wrapper.
2486                                  */
2487                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2488                                 if (mi) {
2489                                         gconstpointer target = mono_icall_get_wrapper (mi);
2490                                         if ((((guint64)target) >> 32) != 0)
2491                                                 near_call = FALSE;
2492                                 }
2493                         }
2494                 }
2495                 else {
2496                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2497                                 /*
2498                                  * This is not really an optimization, but required because the
2499                                  * generic class init trampolines use R11 to pass the vtable.
2500                                  */
2501                                 near_call = TRUE;
2502                         } else {
2503                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2504                                 if (info) {
2505                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2506                                                 strstr (cfg->method->name, info->name)) {
2507                                                 /* A call to the wrapped function */
2508                                                 if ((((guint64)data) >> 32) == 0)
2509                                                         near_call = TRUE;
2510                                                 no_patch = TRUE;
2511                                         }
2512                                         else if (info->func == info->wrapper) {
2513                                                 /* No wrapper */
2514                                                 if ((((guint64)info->func) >> 32) == 0)
2515                                                         near_call = TRUE;
2516                                         }
2517                                         else {
2518                                                 /* See the comment in mono_codegen () */
2519                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2520                                                         near_call = TRUE;
2521                                         }
2522                                 }
2523                                 else if ((((guint64)data) >> 32) == 0) {
2524                                         near_call = TRUE;
2525                                         no_patch = TRUE;
2526                                 }
2527                         }
2528                 }
2529
2530                 if (cfg->method->dynamic)
2531                         /* These methods are allocated using malloc */
2532                         near_call = FALSE;
2533
2534                 if (cfg->compile_aot) {
2535                         near_call = TRUE;
2536                         no_patch = TRUE;
2537                 }
2538
2539 #ifdef MONO_ARCH_NOMAP32BIT
2540                 near_call = FALSE;
2541 #endif
2542
2543                 if (near_call) {
2544                         /*
2545                          * Align the call displacement to an address divisible by 4 so it does
2546                          * not span cache lines. This is required for code patching to work on SMP
2547                          * systems.
2548                          */
2549                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2550                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2551                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2552                         amd64_call_code (code, 0);
2553                 }
2554                 else {
2555                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2556                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2557                         amd64_call_reg (code, GP_SCRATCH_REG);
2558                 }
2559         }
2560
2561         return code;
2562 }
2563
2564 static inline guint8*
2565 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2566 {
2567 #ifdef PLATFORM_WIN32
2568         if (win64_adjust_stack)
2569                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2570 #endif
2571         code = emit_call_body (cfg, code, patch_type, data);
2572 #ifdef PLATFORM_WIN32
2573         if (win64_adjust_stack)
2574                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2575 #endif
2576
2577         return code;
2578 }
2579
2580 static inline int
2581 store_membase_imm_to_store_membase_reg (int opcode)
2582 {
2583         switch (opcode) {
2584         case OP_STORE_MEMBASE_IMM:
2585                 return OP_STORE_MEMBASE_REG;
2586         case OP_STOREI4_MEMBASE_IMM:
2587                 return OP_STOREI4_MEMBASE_REG;
2588         case OP_STOREI8_MEMBASE_IMM:
2589                 return OP_STOREI8_MEMBASE_REG;
2590         }
2591
2592         return -1;
2593 }
2594
2595 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2596
2597 /*
2598  * mono_arch_peephole_pass_1:
2599  *
2600  *   Perform peephole opts which should/can be performed before local regalloc
2601  */
2602 void
2603 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2604 {
2605         MonoInst *ins, *n;
2606
2607         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2608                 MonoInst *last_ins = ins->prev;
2609
2610                 switch (ins->opcode) {
2611                 case OP_ADD_IMM:
2612                 case OP_IADD_IMM:
2613                 case OP_LADD_IMM:
2614                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2615                                 /*
2616                                  * X86_LEA is like ADD, but doesn't have the
2617                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2618                                  * its operand to 64 bit.
2619                                  */
2620                                 ins->opcode = OP_X86_LEA_MEMBASE;
2621                                 ins->inst_basereg = ins->sreg1;
2622                         }
2623                         break;
2624                 case OP_LXOR:
2625                 case OP_IXOR:
2626                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2627                                 MonoInst *ins2;
2628
2629                                 /*
2630                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2631                                  * the latter has length 2-3 instead of 6 (reverse constant
2632                                  * propagation). These instruction sequences are very common
2633                                  * in the initlocals bblock.
2634                                  */
2635                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2636                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2637                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2638                                                 ins2->sreg1 = ins->dreg;
2639                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2640                                                 /* Continue */
2641                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2642                                                 NULLIFY_INS (ins2);
2643                                                 /* Continue */
2644                                         } else {
2645                                                 break;
2646                                         }
2647                                 }
2648                         }
2649                         break;
2650                 case OP_COMPARE_IMM:
2651                 case OP_LCOMPARE_IMM:
2652                         /* OP_COMPARE_IMM (reg, 0)
2653                          * -->
2654                          * OP_AMD64_TEST_NULL (reg)
2655                          */
2656                         if (!ins->inst_imm)
2657                                 ins->opcode = OP_AMD64_TEST_NULL;
2658                         break;
2659                 case OP_ICOMPARE_IMM:
2660                         if (!ins->inst_imm)
2661                                 ins->opcode = OP_X86_TEST_NULL;
2662                         break;
2663                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2664                         /*
2665                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2666                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2667                          * -->
2668                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2669                          * OP_COMPARE_IMM reg, imm
2670                          *
2671                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2672                          */
2673                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2674                             ins->inst_basereg == last_ins->inst_destbasereg &&
2675                             ins->inst_offset == last_ins->inst_offset) {
2676                                         ins->opcode = OP_ICOMPARE_IMM;
2677                                         ins->sreg1 = last_ins->sreg1;
2678
2679                                         /* check if we can remove cmp reg,0 with test null */
2680                                         if (!ins->inst_imm)
2681                                                 ins->opcode = OP_X86_TEST_NULL;
2682                                 }
2683
2684                         break;
2685                 }
2686
2687                 mono_peephole_ins (bb, ins);
2688         }
2689 }
2690
2691 void
2692 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2693 {
2694         MonoInst *ins, *n;
2695
2696         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2697                 switch (ins->opcode) {
2698                 case OP_ICONST:
2699                 case OP_I8CONST: {
2700                         /* reg = 0 -> XOR (reg, reg) */
2701                         /* XOR sets cflags on x86, so we cant do it always */
2702                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2703                                 ins->opcode = OP_LXOR;
2704                                 ins->sreg1 = ins->dreg;
2705                                 ins->sreg2 = ins->dreg;
2706                                 /* Fall through */
2707                         } else {
2708                                 break;
2709                         }
2710                 }
2711                 case OP_LXOR:
2712                         /*
2713                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2714                          * 0 result into 64 bits.
2715                          */
2716                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2717                                 ins->opcode = OP_IXOR;
2718                         }
2719                         /* Fall through */
2720                 case OP_IXOR:
2721                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2722                                 MonoInst *ins2;
2723
2724                                 /*
2725                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2726                                  * the latter has length 2-3 instead of 6 (reverse constant
2727                                  * propagation). These instruction sequences are very common
2728                                  * in the initlocals bblock.
2729                                  */
2730                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2731                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2732                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2733                                                 ins2->sreg1 = ins->dreg;
2734                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2735                                                 /* Continue */
2736                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2737                                                 NULLIFY_INS (ins2);
2738                                                 /* Continue */
2739                                         } else {
2740                                                 break;
2741                                         }
2742                                 }
2743                         }
2744                         break;
2745                 case OP_IADD_IMM:
2746                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2747                                 ins->opcode = OP_X86_INC_REG;
2748                         break;
2749                 case OP_ISUB_IMM:
2750                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2751                                 ins->opcode = OP_X86_DEC_REG;
2752                         break;
2753                 }
2754
2755                 mono_peephole_ins (bb, ins);
2756         }
2757 }
2758
2759 #define NEW_INS(cfg,ins,dest,op) do {   \
2760                 MONO_INST_NEW ((cfg), (dest), (op)); \
2761         (dest)->cil_code = (ins)->cil_code; \
2762         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2763         } while (0)
2764
2765 /*
2766  * mono_arch_lowering_pass:
2767  *
2768  *  Converts complex opcodes into simpler ones so that each IR instruction
2769  * corresponds to one machine instruction.
2770  */
2771 void
2772 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2773 {
2774         MonoInst *ins, *n, *temp;
2775
2776         /*
2777          * FIXME: Need to add more instructions, but the current machine
2778          * description can't model some parts of the composite instructions like
2779          * cdq.
2780          */
2781         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2782                 switch (ins->opcode) {
2783                 case OP_DIV_IMM:
2784                 case OP_REM_IMM:
2785                 case OP_IDIV_IMM:
2786                 case OP_IDIV_UN_IMM:
2787                 case OP_IREM_UN_IMM:
2788                         mono_decompose_op_imm (cfg, bb, ins);
2789                         break;
2790                 case OP_IREM_IMM:
2791                         /* Keep the opcode if we can implement it efficiently */
2792                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2793                                 mono_decompose_op_imm (cfg, bb, ins);
2794                         break;
2795                 case OP_COMPARE_IMM:
2796                 case OP_LCOMPARE_IMM:
2797                         if (!amd64_is_imm32 (ins->inst_imm)) {
2798                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2799                                 temp->inst_c0 = ins->inst_imm;
2800                                 temp->dreg = mono_alloc_ireg (cfg);
2801                                 ins->opcode = OP_COMPARE;
2802                                 ins->sreg2 = temp->dreg;
2803                         }
2804                         break;
2805                 case OP_LOAD_MEMBASE:
2806                 case OP_LOADI8_MEMBASE:
2807                         if (!amd64_is_imm32 (ins->inst_offset)) {
2808                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2809                                 temp->inst_c0 = ins->inst_offset;
2810                                 temp->dreg = mono_alloc_ireg (cfg);
2811                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2812                                 ins->inst_indexreg = temp->dreg;
2813                         }
2814                         break;
2815                 case OP_STORE_MEMBASE_IMM:
2816                 case OP_STOREI8_MEMBASE_IMM:
2817                         if (!amd64_is_imm32 (ins->inst_imm)) {
2818                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2819                                 temp->inst_c0 = ins->inst_imm;
2820                                 temp->dreg = mono_alloc_ireg (cfg);
2821                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2822                                 ins->sreg1 = temp->dreg;
2823                         }
2824                         break;
2825 #ifdef MONO_ARCH_SIMD_INTRINSICS
2826                 case OP_EXPAND_I1: {
2827                                 int temp_reg1 = mono_alloc_ireg (cfg);
2828                                 int temp_reg2 = mono_alloc_ireg (cfg);
2829                                 int original_reg = ins->sreg1;
2830
2831                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2832                                 temp->sreg1 = original_reg;
2833                                 temp->dreg = temp_reg1;
2834
2835                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2836                                 temp->sreg1 = temp_reg1;
2837                                 temp->dreg = temp_reg2;
2838                                 temp->inst_imm = 8;
2839
2840                                 NEW_INS (cfg, ins, temp, OP_LOR);
2841                                 temp->sreg1 = temp->dreg = temp_reg2;
2842                                 temp->sreg2 = temp_reg1;
2843
2844                                 ins->opcode = OP_EXPAND_I2;
2845                                 ins->sreg1 = temp_reg2;
2846                         }
2847                         break;
2848 #endif
2849                 default:
2850                         break;
2851                 }
2852         }
2853
2854         bb->max_vreg = cfg->next_vreg;
2855 }
2856
2857 static const int
2858 branch_cc_table [] = {
2859         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2860         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2861         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2862 };
2863
2864 /* Maps CMP_... constants to X86_CC_... constants */
2865 static const int
2866 cc_table [] = {
2867         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2868         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2869 };
2870
2871 static const int
2872 cc_signed_table [] = {
2873         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2874         FALSE, FALSE, FALSE, FALSE
2875 };
2876
2877 /*#include "cprop.c"*/
2878
2879 static unsigned char*
2880 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2881 {
2882         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2883
2884         if (size == 1)
2885                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2886         else if (size == 2)
2887                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2888         return code;
2889 }
2890
2891 static unsigned char*
2892 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
2893 {
2894         int sreg = tree->sreg1;
2895         int need_touch = FALSE;
2896
2897 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2898         if (!tree->flags & MONO_INST_INIT)
2899                 need_touch = TRUE;
2900 #endif
2901
2902         if (need_touch) {
2903                 guint8* br[5];
2904
2905                 /*
2906                  * Under Windows:
2907                  * If requested stack size is larger than one page,
2908                  * perform stack-touch operation
2909                  */
2910                 /*
2911                  * Generate stack probe code.
2912                  * Under Windows, it is necessary to allocate one page at a time,
2913                  * "touching" stack after each successful sub-allocation. This is
2914                  * because of the way stack growth is implemented - there is a
2915                  * guard page before the lowest stack page that is currently commited.
2916                  * Stack normally grows sequentially so OS traps access to the
2917                  * guard page and commits more pages when needed.
2918                  */
2919                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2920                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2921
2922                 br[2] = code; /* loop */
2923                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2924                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2925                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2926                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2927                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2928                 amd64_patch (br[3], br[2]);
2929                 amd64_test_reg_reg (code, sreg, sreg);
2930                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2931                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2932
2933                 br[1] = code; x86_jump8 (code, 0);
2934
2935                 amd64_patch (br[0], code);
2936                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2937                 amd64_patch (br[1], code);
2938                 amd64_patch (br[4], code);
2939         }
2940         else
2941                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2942
2943         if (tree->flags & MONO_INST_INIT) {
2944                 int offset = 0;
2945                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2946                         amd64_push_reg (code, AMD64_RAX);
2947                         offset += 8;
2948                 }
2949                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2950                         amd64_push_reg (code, AMD64_RCX);
2951                         offset += 8;
2952                 }
2953                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2954                         amd64_push_reg (code, AMD64_RDI);
2955                         offset += 8;
2956                 }
2957
2958                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2959                 if (sreg != AMD64_RCX)
2960                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2961                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2962
2963                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2964                 if (cfg->param_area && cfg->arch.no_pushes)
2965                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
2966                 amd64_cld (code);
2967                 amd64_prefix (code, X86_REP_PREFIX);
2968                 amd64_stosl (code);
2969
2970                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2971                         amd64_pop_reg (code, AMD64_RDI);
2972                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2973                         amd64_pop_reg (code, AMD64_RCX);
2974                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2975                         amd64_pop_reg (code, AMD64_RAX);
2976         }
2977         return code;
2978 }
2979
2980 static guint8*
2981 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2982 {
2983         CallInfo *cinfo;
2984         guint32 quad;
2985
2986         /* Move return value to the target register */
2987         /* FIXME: do this in the local reg allocator */
2988         switch (ins->opcode) {
2989         case OP_CALL:
2990         case OP_CALL_REG:
2991         case OP_CALL_MEMBASE:
2992         case OP_LCALL:
2993         case OP_LCALL_REG:
2994         case OP_LCALL_MEMBASE:
2995                 g_assert (ins->dreg == AMD64_RAX);
2996                 break;
2997         case OP_FCALL:
2998         case OP_FCALL_REG:
2999         case OP_FCALL_MEMBASE:
3000                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3001                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3002                 }
3003                 else {
3004                         if (ins->dreg != AMD64_XMM0)
3005                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3006                 }
3007                 break;
3008         case OP_VCALL:
3009         case OP_VCALL_REG:
3010         case OP_VCALL_MEMBASE:
3011         case OP_VCALL2:
3012         case OP_VCALL2_REG:
3013         case OP_VCALL2_MEMBASE:
3014                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3015                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3016                         MonoInst *loc = cfg->arch.vret_addr_loc;
3017
3018                         /* Load the destination address */
3019                         g_assert (loc->opcode == OP_REGOFFSET);
3020                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3021
3022                         for (quad = 0; quad < 2; quad ++) {
3023                                 switch (cinfo->ret.pair_storage [quad]) {
3024                                 case ArgInIReg:
3025                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3026                                         break;
3027                                 case ArgInFloatSSEReg:
3028                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3029                                         break;
3030                                 case ArgInDoubleSSEReg:
3031                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3032                                         break;
3033                                 case ArgNone:
3034                                         break;
3035                                 default:
3036                                         NOT_IMPLEMENTED;
3037                                 }
3038                         }
3039                 }
3040                 break;
3041         }
3042
3043         return code;
3044 }
3045
3046 /*
3047  * mono_amd64_emit_tls_get:
3048  * @code: buffer to store code to
3049  * @dreg: hard register where to place the result
3050  * @tls_offset: offset info
3051  *
3052  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3053  * the dreg register the item in the thread local storage identified
3054  * by tls_offset.
3055  *
3056  * Returns: a pointer to the end of the stored code
3057  */
3058 guint8*
3059 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3060 {
3061 #ifdef PLATFORM_WIN32
3062         g_assert (tls_offset < 64);
3063         x86_prefix (code, X86_GS_PREFIX);
3064         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3065 #else
3066         if (optimize_for_xen) {
3067                 x86_prefix (code, X86_FS_PREFIX);
3068                 amd64_mov_reg_mem (code, dreg, 0, 8);
3069                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3070         } else {
3071                 x86_prefix (code, X86_FS_PREFIX);
3072                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3073         }
3074 #endif
3075         return code;
3076 }
3077
3078 #define REAL_PRINT_REG(text,reg) \
3079 mono_assert (reg >= 0); \
3080 amd64_push_reg (code, AMD64_RAX); \
3081 amd64_push_reg (code, AMD64_RDX); \
3082 amd64_push_reg (code, AMD64_RCX); \
3083 amd64_push_reg (code, reg); \
3084 amd64_push_imm (code, reg); \
3085 amd64_push_imm (code, text " %d %p\n"); \
3086 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3087 amd64_call_reg (code, AMD64_RAX); \
3088 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3089 amd64_pop_reg (code, AMD64_RCX); \
3090 amd64_pop_reg (code, AMD64_RDX); \
3091 amd64_pop_reg (code, AMD64_RAX);
3092
3093 /* benchmark and set based on cpu */
3094 #define LOOP_ALIGNMENT 8
3095 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3096
3097 #ifndef DISABLE_JIT
3098
3099 void
3100 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3101 {
3102         MonoInst *ins;
3103         MonoCallInst *call;
3104         guint offset;
3105         guint8 *code = cfg->native_code + cfg->code_len;
3106         MonoInst *last_ins = NULL;
3107         guint last_offset = 0;
3108         int max_len;
3109
3110         /* Fix max_offset estimate for each successor bb */
3111         if (cfg->opt & MONO_OPT_BRANCH) {
3112                 int current_offset = cfg->code_len;
3113                 MonoBasicBlock *current_bb;
3114                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3115                         current_bb->max_offset = current_offset;
3116                         current_offset += current_bb->max_length;
3117                 }
3118         }
3119
3120         if (cfg->opt & MONO_OPT_LOOP) {
3121                 int pad, align = LOOP_ALIGNMENT;
3122                 /* set alignment depending on cpu */
3123                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3124                         pad = align - pad;
3125                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3126                         amd64_padding (code, pad);
3127                         cfg->code_len += pad;
3128                         bb->native_offset = cfg->code_len;
3129                 }
3130         }
3131
3132         if (cfg->verbose_level > 2)
3133                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3134
3135         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3136                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3137                 g_assert (!cfg->compile_aot);
3138
3139                 cov->data [bb->dfn].cil_code = bb->cil_code;
3140                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3141                 /* this is not thread save, but good enough */
3142                 amd64_inc_membase (code, AMD64_R11, 0);
3143         }
3144
3145         offset = code - cfg->native_code;
3146
3147         mono_debug_open_block (cfg, bb, offset);
3148
3149     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3150                 x86_breakpoint (code);
3151
3152         MONO_BB_FOR_EACH_INS (bb, ins) {
3153                 offset = code - cfg->native_code;
3154
3155                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3156
3157                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3158                         cfg->code_size *= 2;
3159                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3160                         code = cfg->native_code + offset;
3161                         mono_jit_stats.code_reallocs++;
3162                 }
3163
3164                 if (cfg->debug_info)
3165                         mono_debug_record_line_number (cfg, ins, offset);
3166
3167                 switch (ins->opcode) {
3168                 case OP_BIGMUL:
3169                         amd64_mul_reg (code, ins->sreg2, TRUE);
3170                         break;
3171                 case OP_BIGMUL_UN:
3172                         amd64_mul_reg (code, ins->sreg2, FALSE);
3173                         break;
3174                 case OP_X86_SETEQ_MEMBASE:
3175                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3176                         break;
3177                 case OP_STOREI1_MEMBASE_IMM:
3178                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3179                         break;
3180                 case OP_STOREI2_MEMBASE_IMM:
3181                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3182                         break;
3183                 case OP_STOREI4_MEMBASE_IMM:
3184                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3185                         break;
3186                 case OP_STOREI1_MEMBASE_REG:
3187                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3188                         break;
3189                 case OP_STOREI2_MEMBASE_REG:
3190                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3191                         break;
3192                 case OP_STORE_MEMBASE_REG:
3193                 case OP_STOREI8_MEMBASE_REG:
3194                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3195                         break;
3196                 case OP_STOREI4_MEMBASE_REG:
3197                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3198                         break;
3199                 case OP_STORE_MEMBASE_IMM:
3200                 case OP_STOREI8_MEMBASE_IMM:
3201                         g_assert (amd64_is_imm32 (ins->inst_imm));
3202                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3203                         break;
3204                 case OP_LOAD_MEM:
3205                 case OP_LOADI8_MEM:
3206                         // FIXME: Decompose this earlier
3207                         if (amd64_is_imm32 (ins->inst_imm))
3208                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3209                         else {
3210                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3211                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3212                         }
3213                         break;
3214                 case OP_LOADI4_MEM:
3215                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3216                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3217                         break;
3218                 case OP_LOADU4_MEM:
3219                         // FIXME: Decompose this earlier
3220                         if (amd64_is_imm32 (ins->inst_imm))
3221                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3222                         else {
3223                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3224                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3225                         }
3226                         break;
3227                 case OP_LOADU1_MEM:
3228                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3229                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3230                         break;
3231                 case OP_LOADU2_MEM:
3232                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3233                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3234                         break;
3235                 case OP_LOAD_MEMBASE:
3236                 case OP_LOADI8_MEMBASE:
3237                         g_assert (amd64_is_imm32 (ins->inst_offset));
3238                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3239                         break;
3240                 case OP_LOADI4_MEMBASE:
3241                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3242                         break;
3243                 case OP_LOADU4_MEMBASE:
3244                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3245                         break;
3246                 case OP_LOADU1_MEMBASE:
3247                         /* The cpu zero extends the result into 64 bits */
3248                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3249                         break;
3250                 case OP_LOADI1_MEMBASE:
3251                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3252                         break;
3253                 case OP_LOADU2_MEMBASE:
3254                         /* The cpu zero extends the result into 64 bits */
3255                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3256                         break;
3257                 case OP_LOADI2_MEMBASE:
3258                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3259                         break;
3260                 case OP_AMD64_LOADI8_MEMINDEX:
3261                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3262                         break;
3263                 case OP_LCONV_TO_I1:
3264                 case OP_ICONV_TO_I1:
3265                 case OP_SEXT_I1:
3266                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3267                         break;
3268                 case OP_LCONV_TO_I2:
3269                 case OP_ICONV_TO_I2:
3270                 case OP_SEXT_I2:
3271                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3272                         break;
3273                 case OP_LCONV_TO_U1:
3274                 case OP_ICONV_TO_U1:
3275                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3276                         break;
3277                 case OP_LCONV_TO_U2:
3278                 case OP_ICONV_TO_U2:
3279                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3280                         break;
3281                 case OP_ZEXT_I4:
3282                         /* Clean out the upper word */
3283                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3284                         break;
3285                 case OP_SEXT_I4:
3286                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3287                         break;
3288                 case OP_COMPARE:
3289                 case OP_LCOMPARE:
3290                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3291                         break;
3292                 case OP_COMPARE_IMM:
3293                 case OP_LCOMPARE_IMM:
3294                         g_assert (amd64_is_imm32 (ins->inst_imm));
3295                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3296                         break;
3297                 case OP_X86_COMPARE_REG_MEMBASE:
3298                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3299                         break;
3300                 case OP_X86_TEST_NULL:
3301                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3302                         break;
3303                 case OP_AMD64_TEST_NULL:
3304                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3305                         break;
3306
3307                 case OP_X86_ADD_REG_MEMBASE:
3308                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3309                         break;
3310                 case OP_X86_SUB_REG_MEMBASE:
3311                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3312                         break;
3313                 case OP_X86_AND_REG_MEMBASE:
3314                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3315                         break;
3316                 case OP_X86_OR_REG_MEMBASE:
3317                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3318                         break;
3319                 case OP_X86_XOR_REG_MEMBASE:
3320                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3321                         break;
3322
3323                 case OP_X86_ADD_MEMBASE_IMM:
3324                         /* FIXME: Make a 64 version too */
3325                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3326                         break;
3327                 case OP_X86_SUB_MEMBASE_IMM:
3328                         g_assert (amd64_is_imm32 (ins->inst_imm));
3329                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3330                         break;
3331                 case OP_X86_AND_MEMBASE_IMM:
3332                         g_assert (amd64_is_imm32 (ins->inst_imm));
3333                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3334                         break;
3335                 case OP_X86_OR_MEMBASE_IMM:
3336                         g_assert (amd64_is_imm32 (ins->inst_imm));
3337                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3338                         break;
3339                 case OP_X86_XOR_MEMBASE_IMM:
3340                         g_assert (amd64_is_imm32 (ins->inst_imm));
3341                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3342                         break;
3343                 case OP_X86_ADD_MEMBASE_REG:
3344                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3345                         break;
3346                 case OP_X86_SUB_MEMBASE_REG:
3347                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3348                         break;
3349                 case OP_X86_AND_MEMBASE_REG:
3350                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3351                         break;
3352                 case OP_X86_OR_MEMBASE_REG:
3353                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3354                         break;
3355                 case OP_X86_XOR_MEMBASE_REG:
3356                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3357                         break;
3358                 case OP_X86_INC_MEMBASE:
3359                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3360                         break;
3361                 case OP_X86_INC_REG:
3362                         amd64_inc_reg_size (code, ins->dreg, 4);
3363                         break;
3364                 case OP_X86_DEC_MEMBASE:
3365                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3366                         break;
3367                 case OP_X86_DEC_REG:
3368                         amd64_dec_reg_size (code, ins->dreg, 4);
3369                         break;
3370                 case OP_X86_MUL_REG_MEMBASE:
3371                 case OP_X86_MUL_MEMBASE_REG:
3372                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3373                         break;
3374                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3375                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3376                         break;
3377                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3378                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3379                         break;
3380                 case OP_AMD64_COMPARE_MEMBASE_REG:
3381                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3382                         break;
3383                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3384                         g_assert (amd64_is_imm32 (ins->inst_imm));
3385                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3386                         break;
3387                 case OP_X86_COMPARE_MEMBASE8_IMM:
3388                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3389                         break;
3390                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3391                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3392                         break;
3393                 case OP_AMD64_COMPARE_REG_MEMBASE:
3394                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3395                         break;
3396
3397                 case OP_AMD64_ADD_REG_MEMBASE:
3398                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3399                         break;
3400                 case OP_AMD64_SUB_REG_MEMBASE:
3401                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3402                         break;
3403                 case OP_AMD64_AND_REG_MEMBASE:
3404                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3405                         break;
3406                 case OP_AMD64_OR_REG_MEMBASE:
3407                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3408                         break;
3409                 case OP_AMD64_XOR_REG_MEMBASE:
3410                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3411                         break;
3412
3413                 case OP_AMD64_ADD_MEMBASE_REG:
3414                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3415                         break;
3416                 case OP_AMD64_SUB_MEMBASE_REG:
3417                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3418                         break;
3419                 case OP_AMD64_AND_MEMBASE_REG:
3420                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3421                         break;
3422                 case OP_AMD64_OR_MEMBASE_REG:
3423                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3424                         break;
3425                 case OP_AMD64_XOR_MEMBASE_REG:
3426                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3427                         break;
3428
3429                 case OP_AMD64_ADD_MEMBASE_IMM:
3430                         g_assert (amd64_is_imm32 (ins->inst_imm));
3431                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3432                         break;
3433                 case OP_AMD64_SUB_MEMBASE_IMM:
3434                         g_assert (amd64_is_imm32 (ins->inst_imm));
3435                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3436                         break;
3437                 case OP_AMD64_AND_MEMBASE_IMM:
3438                         g_assert (amd64_is_imm32 (ins->inst_imm));
3439                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3440                         break;
3441                 case OP_AMD64_OR_MEMBASE_IMM:
3442                         g_assert (amd64_is_imm32 (ins->inst_imm));
3443                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3444                         break;
3445                 case OP_AMD64_XOR_MEMBASE_IMM:
3446                         g_assert (amd64_is_imm32 (ins->inst_imm));
3447                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3448                         break;
3449
3450                 case OP_BREAK:
3451                         amd64_breakpoint (code);
3452                         break;
3453                 case OP_RELAXED_NOP:
3454                         x86_prefix (code, X86_REP_PREFIX);
3455                         x86_nop (code);
3456                         break;
3457                 case OP_HARD_NOP:
3458                         x86_nop (code);
3459                         break;
3460                 case OP_NOP:
3461                 case OP_DUMMY_USE:
3462                 case OP_DUMMY_STORE:
3463                 case OP_NOT_REACHED:
3464                 case OP_NOT_NULL:
3465                         break;
3466                 case OP_ADDCC:
3467                 case OP_LADD:
3468                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3469                         break;
3470                 case OP_ADC:
3471                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3472                         break;
3473                 case OP_ADD_IMM:
3474                 case OP_LADD_IMM:
3475                         g_assert (amd64_is_imm32 (ins->inst_imm));
3476                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3477                         break;
3478                 case OP_ADC_IMM:
3479                         g_assert (amd64_is_imm32 (ins->inst_imm));
3480                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3481                         break;
3482                 case OP_SUBCC:
3483                 case OP_LSUB:
3484                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3485                         break;
3486                 case OP_SBB:
3487                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3488                         break;
3489                 case OP_SUB_IMM:
3490                 case OP_LSUB_IMM:
3491                         g_assert (amd64_is_imm32 (ins->inst_imm));
3492                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3493                         break;
3494                 case OP_SBB_IMM:
3495                         g_assert (amd64_is_imm32 (ins->inst_imm));
3496                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3497                         break;
3498                 case OP_LAND:
3499                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3500                         break;
3501                 case OP_AND_IMM:
3502                 case OP_LAND_IMM:
3503                         g_assert (amd64_is_imm32 (ins->inst_imm));
3504                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3505                         break;
3506                 case OP_LMUL:
3507                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3508                         break;
3509                 case OP_MUL_IMM:
3510                 case OP_LMUL_IMM:
3511                 case OP_IMUL_IMM: {
3512                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3513
3514                         switch (ins->inst_imm) {
3515                         case 2:
3516                                 /* MOV r1, r2 */
3517                                 /* ADD r1, r1 */
3518                                 if (ins->dreg != ins->sreg1)
3519                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3520                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3521                                 break;
3522                         case 3:
3523                                 /* LEA r1, [r2 + r2*2] */
3524                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3525                                 break;
3526                         case 5:
3527                                 /* LEA r1, [r2 + r2*4] */
3528                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3529                                 break;
3530                         case 6:
3531                                 /* LEA r1, [r2 + r2*2] */
3532                                 /* ADD r1, r1          */
3533                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3534                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3535                                 break;
3536                         case 9:
3537                                 /* LEA r1, [r2 + r2*8] */
3538                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3539                                 break;
3540                         case 10:
3541                                 /* LEA r1, [r2 + r2*4] */
3542                                 /* ADD r1, r1          */
3543                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3544                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3545                                 break;
3546                         case 12:
3547                                 /* LEA r1, [r2 + r2*2] */
3548                                 /* SHL r1, 2           */
3549                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3550                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3551                                 break;
3552                         case 25:
3553                                 /* LEA r1, [r2 + r2*4] */
3554                                 /* LEA r1, [r1 + r1*4] */
3555                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3556                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3557                                 break;
3558                         case 100:
3559                                 /* LEA r1, [r2 + r2*4] */
3560                                 /* SHL r1, 2           */
3561                                 /* LEA r1, [r1 + r1*4] */
3562                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3563                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3564                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3565                                 break;
3566                         default:
3567                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3568                                 break;
3569                         }
3570                         break;
3571                 }
3572                 case OP_LDIV:
3573                 case OP_LREM:
3574                         /* Regalloc magic makes the div/rem cases the same */
3575                         if (ins->sreg2 == AMD64_RDX) {
3576                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3577                                 amd64_cdq (code);
3578                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3579                         } else {
3580                                 amd64_cdq (code);
3581                                 amd64_div_reg (code, ins->sreg2, TRUE);
3582                         }
3583                         break;
3584                 case OP_LDIV_UN:
3585                 case OP_LREM_UN:
3586                         if (ins->sreg2 == AMD64_RDX) {
3587                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3588                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3589                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3590                         } else {
3591                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3592                                 amd64_div_reg (code, ins->sreg2, FALSE);
3593                         }
3594                         break;
3595                 case OP_IDIV:
3596                 case OP_IREM:
3597                         if (ins->sreg2 == AMD64_RDX) {
3598                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3599                                 amd64_cdq_size (code, 4);
3600                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3601                         } else {
3602                                 amd64_cdq_size (code, 4);
3603                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3604                         }
3605                         break;
3606                 case OP_IDIV_UN:
3607                 case OP_IREM_UN:
3608                         if (ins->sreg2 == AMD64_RDX) {
3609                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3610                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3611                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3612                         } else {
3613                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3614                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3615                         }
3616                         break;
3617                 case OP_IREM_IMM: {
3618                         int power = mono_is_power_of_two (ins->inst_imm);
3619
3620                         g_assert (ins->sreg1 == X86_EAX);
3621                         g_assert (ins->dreg == X86_EAX);
3622                         g_assert (power >= 0);
3623
3624                         if (power == 0) {
3625                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3626                                 break;
3627                         }
3628
3629                         /* Based on gcc code */
3630
3631                         /* Add compensation for negative dividents */
3632                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3633                         if (power > 1)
3634                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3635                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3636                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3637                         /* Compute remainder */
3638                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3639                         /* Remove compensation */
3640                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3641                         break;
3642                 }
3643                 case OP_LMUL_OVF:
3644                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3645                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3646                         break;
3647                 case OP_LOR:
3648                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3649                         break;
3650                 case OP_OR_IMM:
3651                 case OP_LOR_IMM:
3652                         g_assert (amd64_is_imm32 (ins->inst_imm));
3653                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3654                         break;
3655                 case OP_LXOR:
3656                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3657                         break;
3658                 case OP_XOR_IMM:
3659                 case OP_LXOR_IMM:
3660                         g_assert (amd64_is_imm32 (ins->inst_imm));
3661                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3662                         break;
3663                 case OP_LSHL:
3664                         g_assert (ins->sreg2 == AMD64_RCX);
3665                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3666                         break;
3667                 case OP_LSHR:
3668                         g_assert (ins->sreg2 == AMD64_RCX);
3669                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3670                         break;
3671                 case OP_SHR_IMM:
3672                         g_assert (amd64_is_imm32 (ins->inst_imm));
3673                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3674                         break;
3675                 case OP_LSHR_IMM:
3676                         g_assert (amd64_is_imm32 (ins->inst_imm));
3677                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3678                         break;
3679                 case OP_SHR_UN_IMM:
3680                         g_assert (amd64_is_imm32 (ins->inst_imm));
3681                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3682                         break;
3683                 case OP_LSHR_UN_IMM:
3684                         g_assert (amd64_is_imm32 (ins->inst_imm));
3685                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3686                         break;
3687                 case OP_LSHR_UN:
3688                         g_assert (ins->sreg2 == AMD64_RCX);
3689                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3690                         break;
3691                 case OP_SHL_IMM:
3692                         g_assert (amd64_is_imm32 (ins->inst_imm));
3693                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3694                         break;
3695                 case OP_LSHL_IMM:
3696                         g_assert (amd64_is_imm32 (ins->inst_imm));
3697                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3698                         break;
3699
3700                 case OP_IADDCC:
3701                 case OP_IADD:
3702                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3703                         break;
3704                 case OP_IADC:
3705                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3706                         break;
3707                 case OP_IADD_IMM:
3708                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3709                         break;
3710                 case OP_IADC_IMM:
3711                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3712                         break;
3713                 case OP_ISUBCC:
3714                 case OP_ISUB:
3715                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3716                         break;
3717                 case OP_ISBB:
3718                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3719                         break;
3720                 case OP_ISUB_IMM:
3721                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3722                         break;
3723                 case OP_ISBB_IMM:
3724                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3725                         break;
3726                 case OP_IAND:
3727                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3728                         break;
3729                 case OP_IAND_IMM:
3730                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3731                         break;
3732                 case OP_IOR:
3733                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3734                         break;
3735                 case OP_IOR_IMM:
3736                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3737                         break;
3738                 case OP_IXOR:
3739                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3740                         break;
3741                 case OP_IXOR_IMM:
3742                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3743                         break;
3744                 case OP_INEG:
3745                         amd64_neg_reg_size (code, ins->sreg1, 4);
3746                         break;
3747                 case OP_INOT:
3748                         amd64_not_reg_size (code, ins->sreg1, 4);
3749                         break;
3750                 case OP_ISHL:
3751                         g_assert (ins->sreg2 == AMD64_RCX);
3752                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3753                         break;
3754                 case OP_ISHR:
3755                         g_assert (ins->sreg2 == AMD64_RCX);
3756                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3757                         break;
3758                 case OP_ISHR_IMM:
3759                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3760                         break;
3761                 case OP_ISHR_UN_IMM:
3762                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3763                         break;
3764                 case OP_ISHR_UN:
3765                         g_assert (ins->sreg2 == AMD64_RCX);
3766                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3767                         break;
3768                 case OP_ISHL_IMM:
3769                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3770                         break;
3771                 case OP_IMUL:
3772                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3773                         break;
3774                 case OP_IMUL_OVF:
3775                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3776                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3777                         break;
3778                 case OP_IMUL_OVF_UN:
3779                 case OP_LMUL_OVF_UN: {
3780                         /* the mul operation and the exception check should most likely be split */
3781                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3782                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3783                         /*g_assert (ins->sreg2 == X86_EAX);
3784                         g_assert (ins->dreg == X86_EAX);*/
3785                         if (ins->sreg2 == X86_EAX) {
3786                                 non_eax_reg = ins->sreg1;
3787                         } else if (ins->sreg1 == X86_EAX) {
3788                                 non_eax_reg = ins->sreg2;
3789                         } else {
3790                                 /* no need to save since we're going to store to it anyway */
3791                                 if (ins->dreg != X86_EAX) {
3792                                         saved_eax = TRUE;
3793                                         amd64_push_reg (code, X86_EAX);
3794                                 }
3795                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3796                                 non_eax_reg = ins->sreg2;
3797                         }
3798                         if (ins->dreg == X86_EDX) {
3799                                 if (!saved_eax) {
3800                                         saved_eax = TRUE;
3801                                         amd64_push_reg (code, X86_EAX);
3802                                 }
3803                         } else {
3804                                 saved_edx = TRUE;
3805                                 amd64_push_reg (code, X86_EDX);
3806                         }
3807                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3808                         /* save before the check since pop and mov don't change the flags */
3809                         if (ins->dreg != X86_EAX)
3810                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3811                         if (saved_edx)
3812                                 amd64_pop_reg (code, X86_EDX);
3813                         if (saved_eax)
3814                                 amd64_pop_reg (code, X86_EAX);
3815                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3816                         break;
3817                 }
3818                 case OP_ICOMPARE:
3819                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3820                         break;
3821                 case OP_ICOMPARE_IMM:
3822                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3823                         break;
3824                 case OP_IBEQ:
3825                 case OP_IBLT:
3826                 case OP_IBGT:
3827                 case OP_IBGE:
3828                 case OP_IBLE:
3829                 case OP_LBEQ:
3830                 case OP_LBLT:
3831                 case OP_LBGT:
3832                 case OP_LBGE:
3833                 case OP_LBLE:
3834                 case OP_IBNE_UN:
3835                 case OP_IBLT_UN:
3836                 case OP_IBGT_UN:
3837                 case OP_IBGE_UN:
3838                 case OP_IBLE_UN:
3839                 case OP_LBNE_UN:
3840                 case OP_LBLT_UN:
3841                 case OP_LBGT_UN:
3842                 case OP_LBGE_UN:
3843                 case OP_LBLE_UN:
3844                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3845                         break;
3846
3847                 case OP_CMOV_IEQ:
3848                 case OP_CMOV_IGE:
3849                 case OP_CMOV_IGT:
3850                 case OP_CMOV_ILE:
3851                 case OP_CMOV_ILT:
3852                 case OP_CMOV_INE_UN:
3853                 case OP_CMOV_IGE_UN:
3854                 case OP_CMOV_IGT_UN:
3855                 case OP_CMOV_ILE_UN:
3856                 case OP_CMOV_ILT_UN:
3857                 case OP_CMOV_LEQ:
3858                 case OP_CMOV_LGE:
3859                 case OP_CMOV_LGT:
3860                 case OP_CMOV_LLE:
3861                 case OP_CMOV_LLT:
3862                 case OP_CMOV_LNE_UN:
3863                 case OP_CMOV_LGE_UN:
3864                 case OP_CMOV_LGT_UN:
3865                 case OP_CMOV_LLE_UN:
3866                 case OP_CMOV_LLT_UN:
3867                         g_assert (ins->dreg == ins->sreg1);
3868                         /* This needs to operate on 64 bit values */
3869                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3870                         break;
3871
3872                 case OP_LNOT:
3873                         amd64_not_reg (code, ins->sreg1);
3874                         break;
3875                 case OP_LNEG:
3876                         amd64_neg_reg (code, ins->sreg1);
3877                         break;
3878
3879                 case OP_ICONST:
3880                 case OP_I8CONST:
3881                         if ((((guint64)ins->inst_c0) >> 32) == 0)
3882                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3883                         else
3884                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3885                         break;
3886                 case OP_AOTCONST:
3887                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3888                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3889                         break;
3890                 case OP_JUMP_TABLE:
3891                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3892                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3893                         break;
3894                 case OP_MOVE:
3895                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3896                         break;
3897                 case OP_AMD64_SET_XMMREG_R4: {
3898                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3899                         break;
3900                 }
3901                 case OP_AMD64_SET_XMMREG_R8: {
3902                         if (ins->dreg != ins->sreg1)
3903                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3904                         break;
3905                 }
3906                 case OP_TAILCALL: {
3907                         /*
3908                          * Note: this 'frame destruction' logic is useful for tail calls, too.
3909                          * Keep in sync with the code in emit_epilog.
3910                          */
3911                         int pos = 0, i;
3912
3913                         /* FIXME: no tracing support... */
3914                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3915                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
3916
3917                         g_assert (!cfg->method->save_lmf);
3918
3919                         if (cfg->arch.omit_fp) {
3920                                 guint32 save_offset = 0;
3921                                 /* Pop callee-saved registers */
3922                                 for (i = 0; i < AMD64_NREG; ++i)
3923                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3924                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3925                                                 save_offset += 8;
3926                                         }
3927                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3928                         }
3929                         else {
3930                                 for (i = 0; i < AMD64_NREG; ++i)
3931                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3932                                                 pos -= sizeof (gpointer);
3933
3934                                 if (pos)
3935                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3936
3937                                 /* Pop registers in reverse order */
3938                                 for (i = AMD64_NREG - 1; i > 0; --i)
3939                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3940                                                 amd64_pop_reg (code, i);
3941                                         }
3942
3943                                 amd64_leave (code);
3944                         }
3945
3946                         offset = code - cfg->native_code;
3947                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3948                         if (cfg->compile_aot)
3949                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3950                         else
3951                                 amd64_set_reg_template (code, AMD64_R11);
3952                         amd64_jump_reg (code, AMD64_R11);
3953                         break;
3954                 }
3955                 case OP_CHECK_THIS:
3956                         /* ensure ins->sreg1 is not NULL */
3957                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3958                         break;
3959                 case OP_ARGLIST: {
3960                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3961                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3962                         break;
3963                 }
3964                 case OP_CALL:
3965                 case OP_FCALL:
3966                 case OP_LCALL:
3967                 case OP_VCALL:
3968                 case OP_VCALL2:
3969                 case OP_VOIDCALL:
3970                         call = (MonoCallInst*)ins;
3971                         /*
3972                          * The AMD64 ABI forces callers to know about varargs.
3973                          */
3974                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3975                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3976                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3977                                 /*
3978                                  * Since the unmanaged calling convention doesn't contain a
3979                                  * 'vararg' entry, we have to treat every pinvoke call as a
3980                                  * potential vararg call.
3981                                  */
3982                                 guint32 nregs, i;
3983                                 nregs = 0;
3984                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
3985                                         if (call->used_fregs & (1 << i))
3986                                                 nregs ++;
3987                                 if (!nregs)
3988                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3989                                 else
3990                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3991                         }
3992
3993                         if (ins->flags & MONO_INST_HAS_METHOD)
3994                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3995                         else
3996                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3997                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
3998                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3999                         code = emit_move_return_value (cfg, ins, code);
4000                         break;
4001                 case OP_FCALL_REG:
4002                 case OP_LCALL_REG:
4003                 case OP_VCALL_REG:
4004                 case OP_VCALL2_REG:
4005                 case OP_VOIDCALL_REG:
4006                 case OP_CALL_REG:
4007                         call = (MonoCallInst*)ins;
4008
4009                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4010                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4011                                 ins->sreg1 = AMD64_R11;
4012                         }
4013
4014                         /*
4015                          * The AMD64 ABI forces callers to know about varargs.
4016                          */
4017                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4018                                 if (ins->sreg1 == AMD64_RAX) {
4019                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4020                                         ins->sreg1 = AMD64_R11;
4021                                 }
4022                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4023                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4024                                 /*
4025                                  * Since the unmanaged calling convention doesn't contain a
4026                                  * 'vararg' entry, we have to treat every pinvoke call as a
4027                                  * potential vararg call.
4028                                  */
4029                                 guint32 nregs, i;
4030                                 nregs = 0;
4031                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4032                                         if (call->used_fregs & (1 << i))
4033                                                 nregs ++;
4034                                 if (ins->sreg1 == AMD64_RAX) {
4035                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4036                                         ins->sreg1 = AMD64_R11;
4037                                 }
4038                                 if (!nregs)
4039                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4040                                 else
4041                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4042                         }
4043
4044                         amd64_call_reg (code, ins->sreg1);
4045                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4046                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4047                         code = emit_move_return_value (cfg, ins, code);
4048                         break;
4049                 case OP_FCALL_MEMBASE:
4050                 case OP_LCALL_MEMBASE:
4051                 case OP_VCALL_MEMBASE:
4052                 case OP_VCALL2_MEMBASE:
4053                 case OP_VOIDCALL_MEMBASE:
4054                 case OP_CALL_MEMBASE:
4055                         call = (MonoCallInst*)ins;
4056
4057                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4058                                 /*
4059                                  * Can't use R11 because it is clobbered by the trampoline
4060                                  * code, and the reg value is needed by get_vcall_slot_addr.
4061                                  */
4062                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4063                                 ins->sreg1 = AMD64_RAX;
4064                         }
4065
4066                         /*
4067                          * Emit a few nops to simplify get_vcall_slot ().
4068                          */
4069                         amd64_nop (code);
4070                         amd64_nop (code);
4071                         amd64_nop (code);
4072
4073                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4074                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4075                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4076                         code = emit_move_return_value (cfg, ins, code);
4077                         break;
4078                 case OP_DYN_CALL: {
4079                         int i;
4080                         MonoInst *var = cfg->dyn_call_var;
4081
4082                         g_assert (var->opcode == OP_REGOFFSET);
4083
4084                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4085                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4086                         /* r10 = ftn */
4087                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4088
4089                         /* Save args buffer */
4090                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4091
4092                         /* Set argument registers */
4093                         for (i = 0; i < PARAM_REGS; ++i)
4094                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4095
4096                         /* Make the call */
4097                         amd64_call_reg (code, AMD64_R10);
4098
4099                         /* Save result */
4100                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4101                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4102                         break;
4103                 }
4104                 case OP_AMD64_SAVE_SP_TO_LMF:
4105                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4106                         break;
4107                 case OP_X86_PUSH:
4108                         g_assert (!cfg->arch.no_pushes);
4109                         amd64_push_reg (code, ins->sreg1);
4110                         break;
4111                 case OP_X86_PUSH_IMM:
4112                         g_assert (!cfg->arch.no_pushes);
4113                         g_assert (amd64_is_imm32 (ins->inst_imm));
4114                         amd64_push_imm (code, ins->inst_imm);
4115                         break;
4116                 case OP_X86_PUSH_MEMBASE:
4117                         g_assert (!cfg->arch.no_pushes);
4118                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4119                         break;
4120                 case OP_X86_PUSH_OBJ: {
4121                         int size = ALIGN_TO (ins->inst_imm, 8);
4122
4123                         g_assert (!cfg->arch.no_pushes);
4124
4125                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4126                         amd64_push_reg (code, AMD64_RDI);
4127                         amd64_push_reg (code, AMD64_RSI);
4128                         amd64_push_reg (code, AMD64_RCX);
4129                         if (ins->inst_offset)
4130                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4131                         else
4132                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4133                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4134                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4135                         amd64_cld (code);
4136                         amd64_prefix (code, X86_REP_PREFIX);
4137                         amd64_movsd (code);
4138                         amd64_pop_reg (code, AMD64_RCX);
4139                         amd64_pop_reg (code, AMD64_RSI);
4140                         amd64_pop_reg (code, AMD64_RDI);
4141                         break;
4142                 }
4143                 case OP_X86_LEA:
4144                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4145                         break;
4146                 case OP_X86_LEA_MEMBASE:
4147                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4148                         break;
4149                 case OP_X86_XCHG:
4150                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4151                         break;
4152                 case OP_LOCALLOC:
4153                         /* keep alignment */
4154                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4155                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4156                         code = mono_emit_stack_alloc (cfg, code, ins);
4157                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4158                         if (cfg->param_area && cfg->arch.no_pushes)
4159                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4160                         break;
4161                 case OP_LOCALLOC_IMM: {
4162                         guint32 size = ins->inst_imm;
4163                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4164
4165                         if (ins->flags & MONO_INST_INIT) {
4166                                 if (size < 64) {
4167                                         int i;
4168
4169                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4170                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4171
4172                                         for (i = 0; i < size; i += 8)
4173                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4174                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4175                                 } else {
4176                                         amd64_mov_reg_imm (code, ins->dreg, size);
4177                                         ins->sreg1 = ins->dreg;
4178
4179                                         code = mono_emit_stack_alloc (cfg, code, ins);
4180                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4181                                 }
4182                         } else {
4183                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4184                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4185                         }
4186                         if (cfg->param_area && cfg->arch.no_pushes)
4187                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4188                         break;
4189                 }
4190                 case OP_THROW: {
4191                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4192                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4193                                              (gpointer)"mono_arch_throw_exception", FALSE);
4194                         break;
4195                 }
4196                 case OP_RETHROW: {
4197                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4198                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4199                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4200                         break;
4201                 }
4202                 case OP_CALL_HANDLER:
4203                         /* Align stack */
4204                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4205                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4206                         amd64_call_imm (code, 0);
4207                         /* Restore stack alignment */
4208                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4209                         break;
4210                 case OP_START_HANDLER: {
4211                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4212                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4213
4214                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4215                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4216                                 cfg->param_area && cfg->arch.no_pushes) {
4217                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4218                         }
4219                         break;
4220                 }
4221                 case OP_ENDFINALLY: {
4222                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4223                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4224                         amd64_ret (code);
4225                         break;
4226                 }
4227                 case OP_ENDFILTER: {
4228                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4229                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4230                         /* The local allocator will put the result into RAX */
4231                         amd64_ret (code);
4232                         break;
4233                 }
4234
4235                 case OP_LABEL:
4236                         ins->inst_c0 = code - cfg->native_code;
4237                         break;
4238                 case OP_BR:
4239                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4240                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4241                         //break;
4242                                 if (ins->inst_target_bb->native_offset) {
4243                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4244                                 } else {
4245                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4246                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4247                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4248                                                 x86_jump8 (code, 0);
4249                                         else
4250                                                 x86_jump32 (code, 0);
4251                         }
4252                         break;
4253                 case OP_BR_REG:
4254                         amd64_jump_reg (code, ins->sreg1);
4255                         break;
4256                 case OP_CEQ:
4257                 case OP_LCEQ:
4258                 case OP_ICEQ:
4259                 case OP_CLT:
4260                 case OP_LCLT:
4261                 case OP_ICLT:
4262                 case OP_CGT:
4263                 case OP_ICGT:
4264                 case OP_LCGT:
4265                 case OP_CLT_UN:
4266                 case OP_LCLT_UN:
4267                 case OP_ICLT_UN:
4268                 case OP_CGT_UN:
4269                 case OP_LCGT_UN:
4270                 case OP_ICGT_UN:
4271                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4272                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4273                         break;
4274                 case OP_COND_EXC_EQ:
4275                 case OP_COND_EXC_NE_UN:
4276                 case OP_COND_EXC_LT:
4277                 case OP_COND_EXC_LT_UN:
4278                 case OP_COND_EXC_GT:
4279                 case OP_COND_EXC_GT_UN:
4280                 case OP_COND_EXC_GE:
4281                 case OP_COND_EXC_GE_UN:
4282                 case OP_COND_EXC_LE:
4283                 case OP_COND_EXC_LE_UN:
4284                 case OP_COND_EXC_IEQ:
4285                 case OP_COND_EXC_INE_UN:
4286                 case OP_COND_EXC_ILT:
4287                 case OP_COND_EXC_ILT_UN:
4288                 case OP_COND_EXC_IGT:
4289                 case OP_COND_EXC_IGT_UN:
4290                 case OP_COND_EXC_IGE:
4291                 case OP_COND_EXC_IGE_UN:
4292                 case OP_COND_EXC_ILE:
4293                 case OP_COND_EXC_ILE_UN:
4294                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4295                         break;
4296                 case OP_COND_EXC_OV:
4297                 case OP_COND_EXC_NO:
4298                 case OP_COND_EXC_C:
4299                 case OP_COND_EXC_NC:
4300                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4301                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4302                         break;
4303                 case OP_COND_EXC_IOV:
4304                 case OP_COND_EXC_INO:
4305                 case OP_COND_EXC_IC:
4306                 case OP_COND_EXC_INC:
4307                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4308                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4309                         break;
4310
4311                 /* floating point opcodes */
4312                 case OP_R8CONST: {
4313                         double d = *(double *)ins->inst_p0;
4314
4315                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4316                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4317                         }
4318                         else {
4319                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4320                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4321                         }
4322                         break;
4323                 }
4324                 case OP_R4CONST: {
4325                         float f = *(float *)ins->inst_p0;
4326
4327                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4328                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4329                         }
4330                         else {
4331                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4332                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4333                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4334                         }
4335                         break;
4336                 }
4337                 case OP_STORER8_MEMBASE_REG:
4338                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4339                         break;
4340                 case OP_LOADR8_MEMBASE:
4341                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4342                         break;
4343                 case OP_STORER4_MEMBASE_REG:
4344                         /* This requires a double->single conversion */
4345                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4346                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4347                         break;
4348                 case OP_LOADR4_MEMBASE:
4349                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4350                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4351                         break;
4352                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4353                 case OP_ICONV_TO_R8:
4354                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4355                         break;
4356                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4357                 case OP_LCONV_TO_R8:
4358                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4359                         break;
4360                 case OP_FCONV_TO_R4:
4361                         /* FIXME: nothing to do ?? */
4362                         break;
4363                 case OP_FCONV_TO_I1:
4364                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4365                         break;
4366                 case OP_FCONV_TO_U1:
4367                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4368                         break;
4369                 case OP_FCONV_TO_I2:
4370                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4371                         break;
4372                 case OP_FCONV_TO_U2:
4373                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4374                         break;
4375                 case OP_FCONV_TO_U4:
4376                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4377                         break;
4378                 case OP_FCONV_TO_I4:
4379                 case OP_FCONV_TO_I:
4380                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4381                         break;
4382                 case OP_FCONV_TO_I8:
4383                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4384                         break;
4385                 case OP_LCONV_TO_R_UN: {
4386                         guint8 *br [2];
4387
4388                         /* Based on gcc code */
4389                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4390                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4391
4392                         /* Positive case */
4393                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4394                         br [1] = code; x86_jump8 (code, 0);
4395                         amd64_patch (br [0], code);
4396
4397                         /* Negative case */
4398                         /* Save to the red zone */
4399                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4400                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4401                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4402                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4403                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4404                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4405                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4406                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4407                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4408                         /* Restore */
4409                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4410                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4411                         amd64_patch (br [1], code);
4412                         break;
4413                 }
4414                 case OP_LCONV_TO_OVF_U4:
4415                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4416                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4417                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4418                         break;
4419                 case OP_LCONV_TO_OVF_I4_UN:
4420                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4421                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4422                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4423                         break;
4424                 case OP_FMOVE:
4425                         if (ins->dreg != ins->sreg1)
4426                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4427                         break;
4428                 case OP_FADD:
4429                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4430                         break;
4431                 case OP_FSUB:
4432                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4433                         break;
4434                 case OP_FMUL:
4435                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4436                         break;
4437                 case OP_FDIV:
4438                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4439                         break;
4440                 case OP_FNEG: {
4441                         static double r8_0 = -0.0;
4442
4443                         g_assert (ins->sreg1 == ins->dreg);
4444
4445                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4446                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4447                         break;
4448                 }
4449                 case OP_SIN:
4450                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4451                         break;
4452                 case OP_COS:
4453                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4454                         break;
4455                 case OP_ABS: {
4456                         static guint64 d = 0x7fffffffffffffffUL;
4457
4458                         g_assert (ins->sreg1 == ins->dreg);
4459
4460                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4461                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4462                         break;
4463                 }
4464                 case OP_SQRT:
4465                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4466                         break;
4467                 case OP_IMIN:
4468                         g_assert (cfg->opt & MONO_OPT_CMOV);
4469                         g_assert (ins->dreg == ins->sreg1);
4470                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4471                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4472                         break;
4473                 case OP_IMIN_UN:
4474                         g_assert (cfg->opt & MONO_OPT_CMOV);
4475                         g_assert (ins->dreg == ins->sreg1);
4476                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4477                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4478                         break;
4479                 case OP_IMAX:
4480                         g_assert (cfg->opt & MONO_OPT_CMOV);
4481                         g_assert (ins->dreg == ins->sreg1);
4482                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4483                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4484                         break;
4485                 case OP_IMAX_UN:
4486                         g_assert (cfg->opt & MONO_OPT_CMOV);
4487                         g_assert (ins->dreg == ins->sreg1);
4488                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4489                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4490                         break;
4491                 case OP_LMIN:
4492                         g_assert (cfg->opt & MONO_OPT_CMOV);
4493                         g_assert (ins->dreg == ins->sreg1);
4494                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4495                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4496                         break;
4497                 case OP_LMIN_UN:
4498                         g_assert (cfg->opt & MONO_OPT_CMOV);
4499                         g_assert (ins->dreg == ins->sreg1);
4500                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4501                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4502                         break;
4503                 case OP_LMAX:
4504                         g_assert (cfg->opt & MONO_OPT_CMOV);
4505                         g_assert (ins->dreg == ins->sreg1);
4506                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4507                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4508                         break;
4509                 case OP_LMAX_UN:
4510                         g_assert (cfg->opt & MONO_OPT_CMOV);
4511                         g_assert (ins->dreg == ins->sreg1);
4512                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4513                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4514                         break;
4515                 case OP_X86_FPOP:
4516                         break;
4517                 case OP_FCOMPARE:
4518                         /*
4519                          * The two arguments are swapped because the fbranch instructions
4520                          * depend on this for the non-sse case to work.
4521                          */
4522                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4523                         break;
4524                 case OP_FCEQ: {
4525                         /* zeroing the register at the start results in
4526                          * shorter and faster code (we can also remove the widening op)
4527                          */
4528                         guchar *unordered_check;
4529                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4530                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4531                         unordered_check = code;
4532                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4533                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4534                         amd64_patch (unordered_check, code);
4535                         break;
4536                 }
4537                 case OP_FCLT:
4538                 case OP_FCLT_UN:
4539                         /* zeroing the register at the start results in
4540                          * shorter and faster code (we can also remove the widening op)
4541                          */
4542                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4543                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4544                         if (ins->opcode == OP_FCLT_UN) {
4545                                 guchar *unordered_check = code;
4546                                 guchar *jump_to_end;
4547                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4548                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4549                                 jump_to_end = code;
4550                                 x86_jump8 (code, 0);
4551                                 amd64_patch (unordered_check, code);
4552                                 amd64_inc_reg (code, ins->dreg);
4553                                 amd64_patch (jump_to_end, code);
4554                         } else {
4555                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4556                         }
4557                         break;
4558                 case OP_FCGT:
4559                 case OP_FCGT_UN: {
4560                         /* zeroing the register at the start results in
4561                          * shorter and faster code (we can also remove the widening op)
4562                          */
4563                         guchar *unordered_check;
4564                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4565                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4566                         if (ins->opcode == OP_FCGT) {
4567                                 unordered_check = code;
4568                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4569                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4570                                 amd64_patch (unordered_check, code);
4571                         } else {
4572                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4573                         }
4574                         break;
4575                 }
4576                 case OP_FCLT_MEMBASE:
4577                 case OP_FCGT_MEMBASE:
4578                 case OP_FCLT_UN_MEMBASE:
4579                 case OP_FCGT_UN_MEMBASE:
4580                 case OP_FCEQ_MEMBASE: {
4581                         guchar *unordered_check, *jump_to_end;
4582                         int x86_cond;
4583
4584                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4585                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4586
4587                         switch (ins->opcode) {
4588                         case OP_FCEQ_MEMBASE:
4589                                 x86_cond = X86_CC_EQ;
4590                                 break;
4591                         case OP_FCLT_MEMBASE:
4592                         case OP_FCLT_UN_MEMBASE:
4593                                 x86_cond = X86_CC_LT;
4594                                 break;
4595                         case OP_FCGT_MEMBASE:
4596                         case OP_FCGT_UN_MEMBASE:
4597                                 x86_cond = X86_CC_GT;
4598                                 break;
4599                         default:
4600                                 g_assert_not_reached ();
4601                         }
4602
4603                         unordered_check = code;
4604                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4605                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4606
4607                         switch (ins->opcode) {
4608                         case OP_FCEQ_MEMBASE:
4609                         case OP_FCLT_MEMBASE:
4610                         case OP_FCGT_MEMBASE:
4611                                 amd64_patch (unordered_check, code);
4612                                 break;
4613                         case OP_FCLT_UN_MEMBASE:
4614                         case OP_FCGT_UN_MEMBASE:
4615                                 jump_to_end = code;
4616                                 x86_jump8 (code, 0);
4617                                 amd64_patch (unordered_check, code);
4618                                 amd64_inc_reg (code, ins->dreg);
4619                                 amd64_patch (jump_to_end, code);
4620                                 break;
4621                         default:
4622                                 break;
4623                         }
4624                         break;
4625                 }
4626                 case OP_FBEQ: {
4627                         guchar *jump = code;
4628                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4629                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4630                         amd64_patch (jump, code);
4631                         break;
4632                 }
4633                 case OP_FBNE_UN:
4634                         /* Branch if C013 != 100 */
4635                         /* branch if !ZF or (PF|CF) */
4636                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4637                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4638                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4639                         break;
4640                 case OP_FBLT:
4641                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4642                         break;
4643                 case OP_FBLT_UN:
4644                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4645                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4646                         break;
4647                 case OP_FBGT:
4648                 case OP_FBGT_UN:
4649                         if (ins->opcode == OP_FBGT) {
4650                                 guchar *br1;
4651
4652                                 /* skip branch if C1=1 */
4653                                 br1 = code;
4654                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4655                                 /* branch if (C0 | C3) = 1 */
4656                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4657                                 amd64_patch (br1, code);
4658                                 break;
4659                         } else {
4660                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4661                         }
4662                         break;
4663                 case OP_FBGE: {
4664                         /* Branch if C013 == 100 or 001 */
4665                         guchar *br1;
4666
4667                         /* skip branch if C1=1 */
4668                         br1 = code;
4669                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4670                         /* branch if (C0 | C3) = 1 */
4671                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4672                         amd64_patch (br1, code);
4673                         break;
4674                 }
4675                 case OP_FBGE_UN:
4676                         /* Branch if C013 == 000 */
4677                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4678                         break;
4679                 case OP_FBLE: {
4680                         /* Branch if C013=000 or 100 */
4681                         guchar *br1;
4682
4683                         /* skip branch if C1=1 */
4684                         br1 = code;
4685                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4686                         /* branch if C0=0 */
4687                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4688                         amd64_patch (br1, code);
4689                         break;
4690                 }
4691                 case OP_FBLE_UN:
4692                         /* Branch if C013 != 001 */
4693                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4694                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4695                         break;
4696                 case OP_CKFINITE:
4697                         /* Transfer value to the fp stack */
4698                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4699                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4700                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4701
4702                         amd64_push_reg (code, AMD64_RAX);
4703                         amd64_fxam (code);
4704                         amd64_fnstsw (code);
4705                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4706                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4707                         amd64_pop_reg (code, AMD64_RAX);
4708                         amd64_fstp (code, 0);
4709                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4710                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4711                         break;
4712                 case OP_TLS_GET: {
4713                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4714                         break;
4715                 }
4716                 case OP_MEMORY_BARRIER: {
4717                         /* Not needed on amd64 */
4718                         break;
4719                 }
4720                 case OP_ATOMIC_ADD_I4:
4721                 case OP_ATOMIC_ADD_I8: {
4722                         int dreg = ins->dreg;
4723                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4724
4725                         if (dreg == ins->inst_basereg)
4726                                 dreg = AMD64_R11;
4727
4728                         if (dreg != ins->sreg2)
4729                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4730
4731                         x86_prefix (code, X86_LOCK_PREFIX);
4732                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4733
4734                         if (dreg != ins->dreg)
4735                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4736
4737                         break;
4738                 }
4739                 case OP_ATOMIC_ADD_NEW_I4:
4740                 case OP_ATOMIC_ADD_NEW_I8: {
4741                         int dreg = ins->dreg;
4742                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4743
4744                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4745                                 dreg = AMD64_R11;
4746
4747                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4748                         amd64_prefix (code, X86_LOCK_PREFIX);
4749                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4750                         /* dreg contains the old value, add with sreg2 value */
4751                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4752
4753                         if (ins->dreg != dreg)
4754                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4755
4756                         break;
4757                 }
4758                 case OP_ATOMIC_EXCHANGE_I4:
4759                 case OP_ATOMIC_EXCHANGE_I8: {
4760                         guchar *br[2];
4761                         int sreg2 = ins->sreg2;
4762                         int breg = ins->inst_basereg;
4763                         guint32 size;
4764                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4765
4766                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4767                                 size = 8;
4768                         else
4769                                 size = 4;
4770
4771                         /*
4772                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4773                          * an explanation of how this works.
4774                          */
4775
4776                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4777                          * hack to overcome limits in x86 reg allocator
4778                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4779                          */
4780                         g_assert (ins->dreg == AMD64_RAX);
4781
4782                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4783                                 /* Highly unlikely, but possible */
4784                                 need_push = TRUE;
4785
4786                         /* The pushes invalidate rsp */
4787                         if ((breg == AMD64_RAX) || need_push) {
4788                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4789                                 breg = AMD64_R11;
4790                         }
4791
4792                         /* We need the EAX reg for the comparand */
4793                         if (ins->sreg2 == AMD64_RAX) {
4794                                 if (breg != AMD64_R11) {
4795                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4796                                         sreg2 = AMD64_R11;
4797                                 } else {
4798                                         g_assert (need_push);
4799                                         amd64_push_reg (code, AMD64_RDX);
4800                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4801                                         sreg2 = AMD64_RDX;
4802                                         rdx_pushed = TRUE;
4803                                 }
4804                         }
4805
4806                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4807
4808                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4809                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4810                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4811                         amd64_patch (br [1], br [0]);
4812
4813                         if (rdx_pushed)
4814                                 amd64_pop_reg (code, AMD64_RDX);
4815
4816                         break;
4817                 }
4818                 case OP_ATOMIC_CAS_I4:
4819                 case OP_ATOMIC_CAS_I8: {
4820                         guint32 size;
4821
4822                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4823                                 size = 8;
4824                         else
4825                                 size = 4;
4826
4827                         /*
4828                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4829                          * an explanation of how this works.
4830                          */
4831                         g_assert (ins->sreg3 == AMD64_RAX);
4832                         g_assert (ins->sreg1 != AMD64_RAX);
4833                         g_assert (ins->sreg1 != ins->sreg2);
4834
4835                         amd64_prefix (code, X86_LOCK_PREFIX);
4836                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4837
4838                         if (ins->dreg != AMD64_RAX)
4839                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4840                         break;
4841                 }
4842 #ifdef MONO_ARCH_SIMD_INTRINSICS
4843                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4844                 case OP_ADDPS:
4845                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4846                         break;
4847                 case OP_DIVPS:
4848                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4849                         break;
4850                 case OP_MULPS:
4851                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4852                         break;
4853                 case OP_SUBPS:
4854                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4855                         break;
4856                 case OP_MAXPS:
4857                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4858                         break;
4859                 case OP_MINPS:
4860                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4861                         break;
4862                 case OP_COMPPS:
4863                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4864                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4865                         break;
4866                 case OP_ANDPS:
4867                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
4868                         break;
4869                 case OP_ANDNPS:
4870                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
4871                         break;
4872                 case OP_ORPS:
4873                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
4874                         break;
4875                 case OP_XORPS:
4876                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
4877                         break;
4878                 case OP_SQRTPS:
4879                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4880                         break;
4881                 case OP_RSQRTPS:
4882                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
4883                         break;
4884                 case OP_RCPPS:
4885                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
4886                         break;
4887                 case OP_ADDSUBPS:
4888                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4889                         break;
4890                 case OP_HADDPS:
4891                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
4892                         break;
4893                 case OP_HSUBPS:
4894                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
4895                         break;
4896                 case OP_DUPPS_HIGH:
4897                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
4898                         break;
4899                 case OP_DUPPS_LOW:
4900                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
4901                         break;
4902
4903                 case OP_PSHUFLEW_HIGH:
4904                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4905                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4906                         break;
4907                 case OP_PSHUFLEW_LOW:
4908                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4909                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4910                         break;
4911                 case OP_PSHUFLED:
4912                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
4913                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
4914                         break;
4915
4916                 case OP_ADDPD:
4917                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
4918                         break;
4919                 case OP_DIVPD:
4920                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
4921                         break;
4922                 case OP_MULPD:
4923                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
4924                         break;
4925                 case OP_SUBPD:
4926                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
4927                         break;
4928                 case OP_MAXPD:
4929                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
4930                         break;
4931                 case OP_MINPD:
4932                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
4933                         break;
4934                 case OP_COMPPD:
4935                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4936                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4937                         break;
4938                 case OP_ANDPD:
4939                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
4940                         break;
4941                 case OP_ANDNPD:
4942                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
4943                         break;
4944                 case OP_ORPD:
4945                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
4946                         break;
4947                 case OP_XORPD:
4948                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
4949                         break;
4950                 case OP_SQRTPD:
4951                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
4952                         break;
4953                 case OP_ADDSUBPD:
4954                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
4955                         break;
4956                 case OP_HADDPD:
4957                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
4958                         break;
4959                 case OP_HSUBPD:
4960                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
4961                         break;
4962                 case OP_DUPPD:
4963                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
4964                         break;
4965
4966                 case OP_EXTRACT_MASK:
4967                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
4968                         break;
4969
4970                 case OP_PAND:
4971                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
4972                         break;
4973                 case OP_POR:
4974                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
4975                         break;
4976                 case OP_PXOR:
4977                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
4978                         break;
4979
4980                 case OP_PADDB:
4981                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
4982                         break;
4983                 case OP_PADDW:
4984                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
4985                         break;
4986                 case OP_PADDD:
4987                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
4988                         break;
4989                 case OP_PADDQ:
4990                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
4991                         break;
4992
4993                 case OP_PSUBB:
4994                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
4995                         break;
4996                 case OP_PSUBW:
4997                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
4998                         break;
4999                 case OP_PSUBD:
5000                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5001                         break;
5002                 case OP_PSUBQ:
5003                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5004                         break;
5005
5006                 case OP_PMAXB_UN:
5007                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5008                         break;
5009                 case OP_PMAXW_UN:
5010                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5011                         break;
5012                 case OP_PMAXD_UN:
5013                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5014                         break;
5015
5016                 case OP_PMAXB:
5017                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5018                         break;
5019                 case OP_PMAXW:
5020                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5021                         break;
5022                 case OP_PMAXD:
5023                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5024                         break;
5025
5026                 case OP_PAVGB_UN:
5027                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5028                         break;
5029                 case OP_PAVGW_UN:
5030                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5031                         break;
5032
5033                 case OP_PMINB_UN:
5034                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5035                         break;
5036                 case OP_PMINW_UN:
5037                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5038                         break;
5039                 case OP_PMIND_UN:
5040                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5041                         break;
5042
5043                 case OP_PMINB:
5044                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5045                         break;
5046                 case OP_PMINW:
5047                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5048                         break;
5049                 case OP_PMIND:
5050                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5051                         break;
5052
5053                 case OP_PCMPEQB:
5054                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5055                         break;
5056                 case OP_PCMPEQW:
5057                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5058                         break;
5059                 case OP_PCMPEQD:
5060                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5061                         break;
5062                 case OP_PCMPEQQ:
5063                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5064                         break;
5065
5066                 case OP_PCMPGTB:
5067                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5068                         break;
5069                 case OP_PCMPGTW:
5070                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5071                         break;
5072                 case OP_PCMPGTD:
5073                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5074                         break;
5075                 case OP_PCMPGTQ:
5076                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5077                         break;
5078
5079                 case OP_PSUM_ABS_DIFF:
5080                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5081                         break;
5082
5083                 case OP_UNPACK_LOWB:
5084                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5085                         break;
5086                 case OP_UNPACK_LOWW:
5087                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5088                         break;
5089                 case OP_UNPACK_LOWD:
5090                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5091                         break;
5092                 case OP_UNPACK_LOWQ:
5093                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5094                         break;
5095                 case OP_UNPACK_LOWPS:
5096                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5097                         break;
5098                 case OP_UNPACK_LOWPD:
5099                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5100                         break;
5101
5102                 case OP_UNPACK_HIGHB:
5103                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5104                         break;
5105                 case OP_UNPACK_HIGHW:
5106                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5107                         break;
5108                 case OP_UNPACK_HIGHD:
5109                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5110                         break;
5111                 case OP_UNPACK_HIGHQ:
5112                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5113                         break;
5114                 case OP_UNPACK_HIGHPS:
5115                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5116                         break;
5117                 case OP_UNPACK_HIGHPD:
5118                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5119                         break;
5120
5121                 case OP_PACKW:
5122                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5123                         break;
5124                 case OP_PACKD:
5125                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5126                         break;
5127                 case OP_PACKW_UN:
5128                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5129                         break;
5130                 case OP_PACKD_UN:
5131                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5132                         break;
5133
5134                 case OP_PADDB_SAT_UN:
5135                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5136                         break;
5137                 case OP_PSUBB_SAT_UN:
5138                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5139                         break;
5140                 case OP_PADDW_SAT_UN:
5141                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5142                         break;
5143                 case OP_PSUBW_SAT_UN:
5144                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5145                         break;
5146
5147                 case OP_PADDB_SAT:
5148                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5149                         break;
5150                 case OP_PSUBB_SAT:
5151                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5152                         break;
5153                 case OP_PADDW_SAT:
5154                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5155                         break;
5156                 case OP_PSUBW_SAT:
5157                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5158                         break;
5159
5160                 case OP_PMULW:
5161                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5162                         break;
5163                 case OP_PMULD:
5164                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5165                         break;
5166                 case OP_PMULQ:
5167                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5168                         break;
5169                 case OP_PMULW_HIGH_UN:
5170                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5171                         break;
5172                 case OP_PMULW_HIGH:
5173                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5174                         break;
5175
5176                 case OP_PSHRW:
5177                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5178                         break;
5179                 case OP_PSHRW_REG:
5180                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5181                         break;
5182
5183                 case OP_PSARW:
5184                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5185                         break;
5186                 case OP_PSARW_REG:
5187                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5188                         break;
5189
5190                 case OP_PSHLW:
5191                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5192                         break;
5193                 case OP_PSHLW_REG:
5194                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5195                         break;
5196
5197                 case OP_PSHRD:
5198                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5199                         break;
5200                 case OP_PSHRD_REG:
5201                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5202                         break;
5203
5204                 case OP_PSARD:
5205                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5206                         break;
5207                 case OP_PSARD_REG:
5208                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5209                         break;
5210
5211                 case OP_PSHLD:
5212                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5213                         break;
5214                 case OP_PSHLD_REG:
5215                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5216                         break;
5217
5218                 case OP_PSHRQ:
5219                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5220                         break;
5221                 case OP_PSHRQ_REG:
5222                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5223                         break;
5224
5225                 /*TODO: This is appart of the sse spec but not added
5226                 case OP_PSARQ:
5227                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5228                         break;
5229                 case OP_PSARQ_REG:
5230                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5231                         break;
5232                 */
5233
5234                 case OP_PSHLQ:
5235                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5236                         break;
5237                 case OP_PSHLQ_REG:
5238                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5239                         break;
5240
5241                 case OP_ICONV_TO_X:
5242                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5243                         break;
5244                 case OP_EXTRACT_I4:
5245                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5246                         break;
5247                 case OP_EXTRACT_I8:
5248                         if (ins->inst_c0) {
5249                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5250                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5251                         } else {
5252                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5253                         }
5254                         break;
5255                 case OP_EXTRACT_I1:
5256                 case OP_EXTRACT_U1:
5257                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5258                         if (ins->inst_c0)
5259                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5260                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5261                         break;
5262                 case OP_EXTRACT_I2:
5263                 case OP_EXTRACT_U2:
5264                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5265                         if (ins->inst_c0)
5266                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5267                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5268                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5269                         break;
5270                 case OP_EXTRACT_R8:
5271                         if (ins->inst_c0)
5272                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5273                         else
5274                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5275                         break;
5276                 case OP_INSERT_I2:
5277                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5278                         break;
5279                 case OP_EXTRACTX_U2:
5280                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5281                         break;
5282                 case OP_INSERTX_U1_SLOW:
5283                         /*sreg1 is the extracted ireg (scratch)
5284                         /sreg2 is the to be inserted ireg (scratch)
5285                         /dreg is the xreg to receive the value*/
5286
5287                         /*clear the bits from the extracted word*/
5288                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5289                         /*shift the value to insert if needed*/
5290                         if (ins->inst_c0 & 1)
5291                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5292                         /*join them together*/
5293                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5294                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5295                         break;
5296                 case OP_INSERTX_I4_SLOW:
5297                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5298                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5299                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5300                         break;
5301                 case OP_INSERTX_I8_SLOW:
5302                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5303                         if (ins->inst_c0)
5304                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5305                         else
5306                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5307                         break;
5308
5309                 case OP_INSERTX_R4_SLOW:
5310                         switch (ins->inst_c0) {
5311                         case 0:
5312                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5313                                 break;
5314                         case 1:
5315                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5316                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5317                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5318                                 break;
5319                         case 2:
5320                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5321                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5322                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5323                                 break;
5324                         case 3:
5325                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5326                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5327                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5328                                 break;
5329                         }
5330                         break;
5331                 case OP_INSERTX_R8_SLOW:
5332                         if (ins->inst_c0)
5333                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5334                         else
5335                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5336                         break;
5337                 case OP_STOREX_MEMBASE_REG:
5338                 case OP_STOREX_MEMBASE:
5339                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5340                         break;
5341                 case OP_LOADX_MEMBASE:
5342                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5343                         break;
5344                 case OP_LOADX_ALIGNED_MEMBASE:
5345                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5346                         break;
5347                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5348                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5349                         break;
5350                 case OP_STOREX_NTA_MEMBASE_REG:
5351                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5352                         break;
5353                 case OP_PREFETCH_MEMBASE:
5354                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5355                         break;
5356
5357                 case OP_XMOVE:
5358                         /*FIXME the peephole pass should have killed this*/
5359                         if (ins->dreg != ins->sreg1)
5360                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5361                         break;
5362                 case OP_XZERO:
5363                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5364                         break;
5365                 case OP_ICONV_TO_R8_RAW:
5366                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5367                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5368                         break;
5369
5370                 case OP_FCONV_TO_R8_X:
5371                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5372                         break;
5373
5374                 case OP_XCONV_R8_TO_I4:
5375                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5376                         switch (ins->backend.source_opcode) {
5377                         case OP_FCONV_TO_I1:
5378                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5379                                 break;
5380                         case OP_FCONV_TO_U1:
5381                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5382                                 break;
5383                         case OP_FCONV_TO_I2:
5384                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5385                                 break;
5386                         case OP_FCONV_TO_U2:
5387                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5388                                 break;
5389                         }
5390                         break;
5391
5392                 case OP_EXPAND_I2:
5393                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5394                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5395                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5396                         break;
5397                 case OP_EXPAND_I4:
5398                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5399                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5400                         break;
5401                 case OP_EXPAND_I8:
5402                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5403                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5404                         break;
5405                 case OP_EXPAND_R4:
5406                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5407                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5408                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5409                         break;
5410                 case OP_EXPAND_R8:
5411                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5412                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5413                         break;
5414 #endif
5415                 case OP_LIVERANGE_START: {
5416                         if (cfg->verbose_level > 1)
5417                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5418                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5419                         break;
5420                 }
5421                 case OP_LIVERANGE_END: {
5422                         if (cfg->verbose_level > 1)
5423                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5424                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5425                         break;
5426                 }
5427                 default:
5428                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5429                         g_assert_not_reached ();
5430                 }
5431
5432                 if ((code - cfg->native_code - offset) > max_len) {
5433                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5434                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5435                         g_assert_not_reached ();
5436                 }
5437
5438                 last_ins = ins;
5439                 last_offset = offset;
5440         }
5441
5442         cfg->code_len = code - cfg->native_code;
5443 }
5444
5445 #endif /* DISABLE_JIT */
5446
5447 void
5448 mono_arch_register_lowlevel_calls (void)
5449 {
5450         /* The signature doesn't matter */
5451         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5452 }
5453
5454 void
5455 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5456 {
5457         MonoJumpInfo *patch_info;
5458         gboolean compile_aot = !run_cctors;
5459
5460         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5461                 unsigned char *ip = patch_info->ip.i + code;
5462                 unsigned char *target;
5463
5464                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5465
5466                 if (compile_aot) {
5467                         switch (patch_info->type) {
5468                         case MONO_PATCH_INFO_BB:
5469                         case MONO_PATCH_INFO_LABEL:
5470                                 break;
5471                         default:
5472                                 /* No need to patch these */
5473                                 continue;
5474                         }
5475                 }
5476
5477                 switch (patch_info->type) {
5478                 case MONO_PATCH_INFO_NONE:
5479                         continue;
5480                 case MONO_PATCH_INFO_METHOD_REL:
5481                 case MONO_PATCH_INFO_R8:
5482                 case MONO_PATCH_INFO_R4:
5483                         g_assert_not_reached ();
5484                         continue;
5485                 case MONO_PATCH_INFO_BB:
5486                         break;
5487                 default:
5488                         break;
5489                 }
5490
5491                 /*
5492                  * Debug code to help track down problems where the target of a near call is
5493                  * is not valid.
5494                  */
5495                 if (amd64_is_near_call (ip)) {
5496                         gint64 disp = (guint8*)target - (guint8*)ip;
5497
5498                         if (!amd64_is_imm32 (disp)) {
5499                                 printf ("TYPE: %d\n", patch_info->type);
5500                                 switch (patch_info->type) {
5501                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5502                                         printf ("V: %s\n", patch_info->data.name);
5503                                         break;
5504                                 case MONO_PATCH_INFO_METHOD_JUMP:
5505                                 case MONO_PATCH_INFO_METHOD:
5506                                         printf ("V: %s\n", patch_info->data.method->name);
5507                                         break;
5508                                 default:
5509                                         break;
5510                                 }
5511                         }
5512                 }
5513
5514                 amd64_patch (ip, (gpointer)target);
5515         }
5516 }
5517
5518 static int
5519 get_max_epilog_size (MonoCompile *cfg)
5520 {
5521         int max_epilog_size = 16;
5522
5523         if (cfg->method->save_lmf)
5524                 max_epilog_size += 256;
5525
5526         if (mono_jit_trace_calls != NULL)
5527                 max_epilog_size += 50;
5528
5529         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5530                 max_epilog_size += 50;
5531
5532         max_epilog_size += (AMD64_NREG * 2);
5533
5534         return max_epilog_size;
5535 }
5536
5537 /*
5538  * This macro is used for testing whenever the unwinder works correctly at every point
5539  * where an async exception can happen.
5540  */
5541 /* This will generate a SIGSEGV at the given point in the code */
5542 #define async_exc_point(code) do { \
5543     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5544          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5545              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5546          cfg->arch.async_point_count ++; \
5547     } \
5548 } while (0)
5549
5550 guint8 *
5551 mono_arch_emit_prolog (MonoCompile *cfg)
5552 {
5553         MonoMethod *method = cfg->method;
5554         MonoBasicBlock *bb;
5555         MonoMethodSignature *sig;
5556         MonoInst *ins;
5557         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5558         guint8 *code;
5559         CallInfo *cinfo;
5560         gint32 lmf_offset = cfg->arch.lmf_offset;
5561         gboolean args_clobbered = FALSE;
5562         gboolean trace = FALSE;
5563
5564         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
5565
5566         code = cfg->native_code = g_malloc (cfg->code_size);
5567
5568         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5569                 trace = TRUE;
5570
5571         /* Amount of stack space allocated by register saving code */
5572         pos = 0;
5573
5574         /* Offset between RSP and the CFA */
5575         cfa_offset = 0;
5576
5577         /*
5578          * The prolog consists of the following parts:
5579          * FP present:
5580          * - push rbp, mov rbp, rsp
5581          * - save callee saved regs using pushes
5582          * - allocate frame
5583          * - save rgctx if needed
5584          * - save lmf if needed
5585          * FP not present:
5586          * - allocate frame
5587          * - save rgctx if needed
5588          * - save lmf if needed
5589          * - save callee saved regs using moves
5590          */
5591
5592         // CFA = sp + 8
5593         cfa_offset = 8;
5594         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5595         // IP saved at CFA - 8
5596         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5597         async_exc_point (code);
5598
5599         if (!cfg->arch.omit_fp) {
5600                 amd64_push_reg (code, AMD64_RBP);
5601                 cfa_offset += 8;
5602                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5603                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5604                 async_exc_point (code);
5605 #ifdef PLATFORM_WIN32
5606                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5607 #endif
5608
5609                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5610                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5611                 async_exc_point (code);
5612 #ifdef PLATFORM_WIN32
5613                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5614 #endif
5615         }
5616
5617         /* Save callee saved registers */
5618         if (!cfg->arch.omit_fp && !method->save_lmf) {
5619                 int offset = cfa_offset;
5620
5621                 for (i = 0; i < AMD64_NREG; ++i)
5622                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5623                                 amd64_push_reg (code, i);
5624                                 pos += sizeof (gpointer);
5625                                 offset += 8;
5626                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5627                                 async_exc_point (code);
5628                         }
5629         }
5630
5631         /* The param area is always at offset 0 from sp */
5632         /* This needs to be allocated here, since it has to come after the spill area */
5633         if (cfg->arch.no_pushes && cfg->param_area) {
5634                 if (cfg->arch.omit_fp)
5635                         // FIXME:
5636                         g_assert_not_reached ();
5637                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5638         }
5639
5640         if (cfg->arch.omit_fp) {
5641                 /*
5642                  * On enter, the stack is misaligned by the the pushing of the return
5643                  * address. It is either made aligned by the pushing of %rbp, or by
5644                  * this.
5645                  */
5646                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5647                 if ((alloc_size % 16) == 0)
5648                         alloc_size += 8;
5649         } else {
5650                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5651
5652                 alloc_size -= pos;
5653         }
5654
5655         cfg->arch.stack_alloc_size = alloc_size;
5656
5657         /* Allocate stack frame */
5658         if (alloc_size) {
5659                 /* See mono_emit_stack_alloc */
5660 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5661                 guint32 remaining_size = alloc_size;
5662                 while (remaining_size >= 0x1000) {
5663                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5664                         if (cfg->arch.omit_fp) {
5665                                 cfa_offset += 0x1000;
5666                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5667                         }
5668                         async_exc_point (code);
5669 #ifdef PLATFORM_WIN32
5670                         if (cfg->arch.omit_fp)
5671                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5672 #endif
5673
5674                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5675                         remaining_size -= 0x1000;
5676                 }
5677                 if (remaining_size) {
5678                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5679                         if (cfg->arch.omit_fp) {
5680                                 cfa_offset += remaining_size;
5681                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5682                                 async_exc_point (code);
5683                         }
5684 #ifdef PLATFORM_WIN32
5685                         if (cfg->arch.omit_fp)
5686                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5687 #endif
5688                 }
5689 #else
5690                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5691                 if (cfg->arch.omit_fp) {
5692                         cfa_offset += alloc_size;
5693                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5694                         async_exc_point (code);
5695                 }
5696 #endif
5697         }
5698
5699         /* Stack alignment check */
5700 #if 0
5701         {
5702                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5703                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5704                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5705                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5706                 amd64_breakpoint (code);
5707         }
5708 #endif
5709
5710         /* Save LMF */
5711         if (method->save_lmf) {
5712                 /*
5713                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5714                  */
5715                 /* sp is saved right before calls */
5716                 /* Skip method (only needed for trampoline LMF frames) */
5717                 /* Save callee saved regs */
5718                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5719                         int offset;
5720
5721                         switch (i) {
5722                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5723                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5724                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5725                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5726                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5727                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5728 #ifdef PLATFORM_WIN32
5729                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5730                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5731 #endif
5732                         default:
5733                                 offset = -1;
5734                                 break;
5735                         }
5736
5737                         if (offset != -1) {
5738                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5739                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5740                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5741                         }
5742                 }
5743         }
5744
5745         /* Save callee saved registers */
5746         if (cfg->arch.omit_fp && !method->save_lmf) {
5747                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5748
5749                 /* Save caller saved registers after sp is adjusted */
5750                 /* The registers are saved at the bottom of the frame */
5751                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5752                 for (i = 0; i < AMD64_NREG; ++i)
5753                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5754                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5755                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5756                                 save_area_offset += 8;
5757                                 async_exc_point (code);
5758                         }
5759         }
5760
5761         /* store runtime generic context */
5762         if (cfg->rgctx_var) {
5763                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5764                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5765
5766                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5767         }
5768
5769         /* compute max_length in order to use short forward jumps */
5770         max_epilog_size = get_max_epilog_size (cfg);
5771         if (cfg->opt & MONO_OPT_BRANCH) {
5772                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5773                         MonoInst *ins;
5774                         int max_length = 0;
5775
5776                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5777                                 max_length += 6;
5778                         /* max alignment for loops */
5779                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5780                                 max_length += LOOP_ALIGNMENT;
5781
5782                         MONO_BB_FOR_EACH_INS (bb, ins) {
5783                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5784                         }
5785
5786                         /* Take prolog and epilog instrumentation into account */
5787                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5788                                 max_length += max_epilog_size;
5789
5790                         bb->max_length = max_length;
5791                 }
5792         }
5793
5794         sig = mono_method_signature (method);
5795         pos = 0;
5796
5797         cinfo = cfg->arch.cinfo;
5798
5799         if (sig->ret->type != MONO_TYPE_VOID) {
5800                 /* Save volatile arguments to the stack */
5801                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5802                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5803         }
5804
5805         /* Keep this in sync with emit_load_volatile_arguments */
5806         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5807                 ArgInfo *ainfo = cinfo->args + i;
5808                 gint32 stack_offset;
5809                 MonoType *arg_type;
5810
5811                 ins = cfg->args [i];
5812
5813                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5814                         /* Unused arguments */
5815                         continue;
5816
5817                 if (sig->hasthis && (i == 0))
5818                         arg_type = &mono_defaults.object_class->byval_arg;
5819                 else
5820                         arg_type = sig->params [i - sig->hasthis];
5821
5822                 stack_offset = ainfo->offset + ARGS_OFFSET;
5823
5824                 if (cfg->globalra) {
5825                         /* All the other moves are done by the register allocator */
5826                         switch (ainfo->storage) {
5827                         case ArgInFloatSSEReg:
5828                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5829                                 break;
5830                         case ArgValuetypeInReg:
5831                                 for (quad = 0; quad < 2; quad ++) {
5832                                         switch (ainfo->pair_storage [quad]) {
5833                                         case ArgInIReg:
5834                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5835                                                 break;
5836                                         case ArgInFloatSSEReg:
5837                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5838                                                 break;
5839                                         case ArgInDoubleSSEReg:
5840                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5841                                                 break;
5842                                         case ArgNone:
5843                                                 break;
5844                                         default:
5845                                                 g_assert_not_reached ();
5846                                         }
5847                                 }
5848                                 break;
5849                         default:
5850                                 break;
5851                         }
5852
5853                         continue;
5854                 }
5855
5856                 /* Save volatile arguments to the stack */
5857                 if (ins->opcode != OP_REGVAR) {
5858                         switch (ainfo->storage) {
5859                         case ArgInIReg: {
5860                                 guint32 size = 8;
5861
5862                                 /* FIXME: I1 etc */
5863                                 /*
5864                                 if (stack_offset & 0x1)
5865                                         size = 1;
5866                                 else if (stack_offset & 0x2)
5867                                         size = 2;
5868                                 else if (stack_offset & 0x4)
5869                                         size = 4;
5870                                 else
5871                                         size = 8;
5872                                 */
5873                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5874                                 break;
5875                         }
5876                         case ArgInFloatSSEReg:
5877                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5878                                 break;
5879                         case ArgInDoubleSSEReg:
5880                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5881                                 break;
5882                         case ArgValuetypeInReg:
5883                                 for (quad = 0; quad < 2; quad ++) {
5884                                         switch (ainfo->pair_storage [quad]) {
5885                                         case ArgInIReg:
5886                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5887                                                 break;
5888                                         case ArgInFloatSSEReg:
5889                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5890                                                 break;
5891                                         case ArgInDoubleSSEReg:
5892                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5893                                                 break;
5894                                         case ArgNone:
5895                                                 break;
5896                                         default:
5897                                                 g_assert_not_reached ();
5898                                         }
5899                                 }
5900                                 break;
5901                         case ArgValuetypeAddrInIReg:
5902                                 if (ainfo->pair_storage [0] == ArgInIReg)
5903                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
5904                                 break;
5905                         default:
5906                                 break;
5907                         }
5908                 } else {
5909                         /* Argument allocated to (non-volatile) register */
5910                         switch (ainfo->storage) {
5911                         case ArgInIReg:
5912                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5913                                 break;
5914                         case ArgOnStack:
5915                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5916                                 break;
5917                         default:
5918                                 g_assert_not_reached ();
5919                         }
5920                 }
5921         }
5922
5923         /* Might need to attach the thread to the JIT  or change the domain for the callback */
5924         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5925                 guint64 domain = (guint64)cfg->domain;
5926
5927                 args_clobbered = TRUE;
5928
5929                 /*
5930                  * The call might clobber argument registers, but they are already
5931                  * saved to the stack/global regs.
5932                  */
5933                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5934                         guint8 *buf, *no_domain_branch;
5935
5936                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5937                         if (cfg->compile_aot) {
5938                                 /* AOT code is only used in the root domain */
5939                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
5940                         } else {
5941                                 if ((domain >> 32) == 0)
5942                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5943                                 else
5944                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5945                         }
5946                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5947                         no_domain_branch = code;
5948                         x86_branch8 (code, X86_CC_NE, 0, 0);
5949                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5950                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5951                         buf = code;
5952                         x86_branch8 (code, X86_CC_NE, 0, 0);
5953                         amd64_patch (no_domain_branch, code);
5954                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5955                                           (gpointer)"mono_jit_thread_attach", TRUE);
5956                         amd64_patch (buf, code);
5957 #ifdef PLATFORM_WIN32
5958                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5959                         /* FIXME: Add a separate key for LMF to avoid this */
5960                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5961 #endif
5962                 } else {
5963                         g_assert (!cfg->compile_aot);
5964                         if (cfg->compile_aot) {
5965                                 /* AOT code is only used in the root domain */
5966                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
5967                         } else {
5968                                 if ((domain >> 32) == 0)
5969                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5970                                 else
5971                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5972                         }
5973                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5974                                           (gpointer)"mono_jit_thread_attach", TRUE);
5975                 }
5976         }
5977
5978         if (method->save_lmf) {
5979                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5980                         /*
5981                          * Optimized version which uses the mono_lmf TLS variable instead of
5982                          * indirection through the mono_lmf_addr TLS variable.
5983                          */
5984                         /* %rax = previous_lmf */
5985                         x86_prefix (code, X86_FS_PREFIX);
5986                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5987
5988                         /* Save previous_lmf */
5989                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5990                         /* Set new lmf */
5991                         if (lmf_offset == 0) {
5992                                 x86_prefix (code, X86_FS_PREFIX);
5993                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5994                         } else {
5995                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5996                                 x86_prefix (code, X86_FS_PREFIX);
5997                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5998                         }
5999                 } else {
6000                         if (lmf_addr_tls_offset != -1) {
6001                                 /* Load lmf quicky using the FS register */
6002                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6003 #ifdef PLATFORM_WIN32
6004                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6005                                 /* FIXME: Add a separate key for LMF to avoid this */
6006                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6007 #endif
6008                         }
6009                         else {
6010                                 /*
6011                                  * The call might clobber argument registers, but they are already
6012                                  * saved to the stack/global regs.
6013                                  */
6014                                 args_clobbered = TRUE;
6015                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6016                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6017                         }
6018
6019                         /* Save lmf_addr */
6020                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6021                         /* Save previous_lmf */
6022                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6023                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6024                         /* Set new lmf */
6025                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6026                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6027                 }
6028         }
6029
6030         if (trace) {
6031                 args_clobbered = TRUE;
6032                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6033         }
6034
6035         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6036                 args_clobbered = TRUE;
6037
6038         /*
6039          * Optimize the common case of the first bblock making a call with the same
6040          * arguments as the method. This works because the arguments are still in their
6041          * original argument registers.
6042          * FIXME: Generalize this
6043          */
6044         if (!args_clobbered) {
6045                 MonoBasicBlock *first_bb = cfg->bb_entry;
6046                 MonoInst *next;
6047
6048                 next = mono_bb_first_ins (first_bb);
6049                 if (!next && first_bb->next_bb) {
6050                         first_bb = first_bb->next_bb;
6051                         next = mono_bb_first_ins (first_bb);
6052                 }
6053
6054                 if (first_bb->in_count > 1)
6055                         next = NULL;
6056
6057                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6058                         ArgInfo *ainfo = cinfo->args + i;
6059                         gboolean match = FALSE;
6060
6061                         ins = cfg->args [i];
6062                         if (ins->opcode != OP_REGVAR) {
6063                                 switch (ainfo->storage) {
6064                                 case ArgInIReg: {
6065                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6066                                                 if (next->dreg == ainfo->reg) {
6067                                                         NULLIFY_INS (next);
6068                                                         match = TRUE;
6069                                                 } else {
6070                                                         next->opcode = OP_MOVE;
6071                                                         next->sreg1 = ainfo->reg;
6072                                                         /* Only continue if the instruction doesn't change argument regs */
6073                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6074                                                                 match = TRUE;
6075                                                 }
6076                                         }
6077                                         break;
6078                                 }
6079                                 default:
6080                                         break;
6081                                 }
6082                         } else {
6083                                 /* Argument allocated to (non-volatile) register */
6084                                 switch (ainfo->storage) {
6085                                 case ArgInIReg:
6086                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6087                                                 NULLIFY_INS (next);
6088                                                 match = TRUE;
6089                                         }
6090                                         break;
6091                                 default:
6092                                         break;
6093                                 }
6094                         }
6095
6096                         if (match) {
6097                                 next = next->next;
6098                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6099                                 if (!next)
6100                                         break;
6101                         }
6102                 }
6103         }
6104
6105         cfg->code_len = code - cfg->native_code;
6106
6107         g_assert (cfg->code_len < cfg->code_size);
6108
6109         return code;
6110 }
6111
6112 void
6113 mono_arch_emit_epilog (MonoCompile *cfg)
6114 {
6115         MonoMethod *method = cfg->method;
6116         int quad, pos, i;
6117         guint8 *code;
6118         int max_epilog_size;
6119         CallInfo *cinfo;
6120         gint32 lmf_offset = cfg->arch.lmf_offset;
6121
6122         max_epilog_size = get_max_epilog_size (cfg);
6123
6124         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6125                 cfg->code_size *= 2;
6126                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6127                 mono_jit_stats.code_reallocs++;
6128         }
6129
6130         code = cfg->native_code + cfg->code_len;
6131
6132         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6133                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6134
6135         /* the code restoring the registers must be kept in sync with OP_JMP */
6136         pos = 0;
6137
6138         if (method->save_lmf) {
6139                 /* check if we need to restore protection of the stack after a stack overflow */
6140                 if (mono_get_jit_tls_offset () != -1) {
6141                         guint8 *patch;
6142                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6143                         /* we load the value in a separate instruction: this mechanism may be
6144                          * used later as a safer way to do thread interruption
6145                          */
6146                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6147                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6148                         patch = code;
6149                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6150                         /* note that the call trampoline will preserve eax/edx */
6151                         x86_call_reg (code, X86_ECX);
6152                         x86_patch (patch, code);
6153                 } else {
6154                         /* FIXME: maybe save the jit tls in the prolog */
6155                 }
6156                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6157                         /*
6158                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6159                          * through the mono_lmf_addr TLS variable.
6160                          */
6161                         /* reg = previous_lmf */
6162                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6163                         x86_prefix (code, X86_FS_PREFIX);
6164                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6165                 } else {
6166                         /* Restore previous lmf */
6167                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6168                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6169                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6170                 }
6171
6172                 /* Restore caller saved regs */
6173                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6174                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6175                 }
6176                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6177                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6178                 }
6179                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6180                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6181                 }
6182                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6183                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6184                 }
6185                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6186                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6187                 }
6188                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6189                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6190                 }
6191 #ifdef PLATFORM_WIN32
6192                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6193                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6194                 }
6195                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6196                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6197                 }
6198 #endif
6199         } else {
6200
6201                 if (cfg->arch.omit_fp) {
6202                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6203
6204                         for (i = 0; i < AMD64_NREG; ++i)
6205                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6206                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6207                                         save_area_offset += 8;
6208                                 }
6209                 }
6210                 else {
6211                         for (i = 0; i < AMD64_NREG; ++i)
6212                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6213                                         pos -= sizeof (gpointer);
6214
6215                         if (pos) {
6216                                 if (pos == - sizeof (gpointer)) {
6217                                         /* Only one register, so avoid lea */
6218                                         for (i = AMD64_NREG - 1; i > 0; --i)
6219                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6220                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6221                                                 }
6222                                 }
6223                                 else {
6224                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6225
6226                                         /* Pop registers in reverse order */
6227                                         for (i = AMD64_NREG - 1; i > 0; --i)
6228                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6229                                                         amd64_pop_reg (code, i);
6230                                                 }
6231                                 }
6232                         }
6233                 }
6234         }
6235
6236         /* Load returned vtypes into registers if needed */
6237         cinfo = cfg->arch.cinfo;
6238         if (cinfo->ret.storage == ArgValuetypeInReg) {
6239                 ArgInfo *ainfo = &cinfo->ret;
6240                 MonoInst *inst = cfg->ret;
6241
6242                 for (quad = 0; quad < 2; quad ++) {
6243                         switch (ainfo->pair_storage [quad]) {
6244                         case ArgInIReg:
6245                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6246                                 break;
6247                         case ArgInFloatSSEReg:
6248                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6249                                 break;
6250                         case ArgInDoubleSSEReg:
6251                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6252                                 break;
6253                         case ArgNone:
6254                                 break;
6255                         default:
6256                                 g_assert_not_reached ();
6257                         }
6258                 }
6259         }
6260
6261         if (cfg->arch.omit_fp) {
6262                 if (cfg->arch.stack_alloc_size)
6263                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6264         } else {
6265                 amd64_leave (code);
6266         }
6267         async_exc_point (code);
6268         amd64_ret (code);
6269
6270         cfg->code_len = code - cfg->native_code;
6271
6272         g_assert (cfg->code_len < cfg->code_size);
6273 }
6274
6275 void
6276 mono_arch_emit_exceptions (MonoCompile *cfg)
6277 {
6278         MonoJumpInfo *patch_info;
6279         int nthrows, i;
6280         guint8 *code;
6281         MonoClass *exc_classes [16];
6282         guint8 *exc_throw_start [16], *exc_throw_end [16];
6283         guint32 code_size = 0;
6284
6285         /* Compute needed space */
6286         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6287                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6288                         code_size += 40;
6289                 if (patch_info->type == MONO_PATCH_INFO_R8)
6290                         code_size += 8 + 15; /* sizeof (double) + alignment */
6291                 if (patch_info->type == MONO_PATCH_INFO_R4)
6292                         code_size += 4 + 15; /* sizeof (float) + alignment */
6293         }
6294
6295         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6296                 cfg->code_size *= 2;
6297                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6298                 mono_jit_stats.code_reallocs++;
6299         }
6300
6301         code = cfg->native_code + cfg->code_len;
6302
6303         /* add code to raise exceptions */
6304         nthrows = 0;
6305         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6306                 switch (patch_info->type) {
6307                 case MONO_PATCH_INFO_EXC: {
6308                         MonoClass *exc_class;
6309                         guint8 *buf, *buf2;
6310                         guint32 throw_ip;
6311
6312                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6313
6314                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6315                         g_assert (exc_class);
6316                         throw_ip = patch_info->ip.i;
6317
6318                         //x86_breakpoint (code);
6319                         /* Find a throw sequence for the same exception class */
6320                         for (i = 0; i < nthrows; ++i)
6321                                 if (exc_classes [i] == exc_class)
6322                                         break;
6323                         if (i < nthrows) {
6324                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6325                                 x86_jump_code (code, exc_throw_start [i]);
6326                                 patch_info->type = MONO_PATCH_INFO_NONE;
6327                         }
6328                         else {
6329                                 buf = code;
6330                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6331                                 buf2 = code;
6332
6333                                 if (nthrows < 16) {
6334                                         exc_classes [nthrows] = exc_class;
6335                                         exc_throw_start [nthrows] = code;
6336                                 }
6337                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
6338
6339                                 patch_info->type = MONO_PATCH_INFO_NONE;
6340
6341                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6342
6343                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6344                                 while (buf < buf2)
6345                                         x86_nop (buf);
6346
6347                                 if (nthrows < 16) {
6348                                         exc_throw_end [nthrows] = code;
6349                                         nthrows ++;
6350                                 }
6351                         }
6352                         break;
6353                 }
6354                 default:
6355                         /* do nothing */
6356                         break;
6357                 }
6358         }
6359
6360         /* Handle relocations with RIP relative addressing */
6361         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6362                 gboolean remove = FALSE;
6363
6364                 switch (patch_info->type) {
6365                 case MONO_PATCH_INFO_R8:
6366                 case MONO_PATCH_INFO_R4: {
6367                         guint8 *pos;
6368
6369                         /* The SSE opcodes require a 16 byte alignment */
6370                         code = (guint8*)ALIGN_TO (code, 16);
6371
6372                         pos = cfg->native_code + patch_info->ip.i;
6373
6374                         if (IS_REX (pos [1]))
6375                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6376                         else
6377                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6378
6379                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6380                                 *(double*)code = *(double*)patch_info->data.target;
6381                                 code += sizeof (double);
6382                         } else {
6383                                 *(float*)code = *(float*)patch_info->data.target;
6384                                 code += sizeof (float);
6385                         }
6386
6387                         remove = TRUE;
6388                         break;
6389                 }
6390                 default:
6391                         break;
6392                 }
6393
6394                 if (remove) {
6395                         if (patch_info == cfg->patch_info)
6396                                 cfg->patch_info = patch_info->next;
6397                         else {
6398                                 MonoJumpInfo *tmp;
6399
6400                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6401                                         ;
6402                                 tmp->next = patch_info->next;
6403                         }
6404                 }
6405         }
6406
6407         cfg->code_len = code - cfg->native_code;
6408
6409         g_assert (cfg->code_len < cfg->code_size);
6410
6411 }
6412
6413 void*
6414 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6415 {
6416         guchar *code = p;
6417         CallInfo *cinfo = NULL;
6418         MonoMethodSignature *sig;
6419         MonoInst *inst;
6420         int i, n, stack_area = 0;
6421
6422         /* Keep this in sync with mono_arch_get_argument_info */
6423
6424         if (enable_arguments) {
6425                 /* Allocate a new area on the stack and save arguments there */
6426                 sig = mono_method_signature (cfg->method);
6427
6428                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6429
6430                 n = sig->param_count + sig->hasthis;
6431
6432                 stack_area = ALIGN_TO (n * 8, 16);
6433
6434                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6435
6436                 for (i = 0; i < n; ++i) {
6437                         inst = cfg->args [i];
6438
6439                         if (inst->opcode == OP_REGVAR)
6440                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6441                         else {
6442                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6443                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6444                         }
6445                 }
6446         }
6447
6448         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6449         amd64_set_reg_template (code, AMD64_ARG_REG1);
6450         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6451         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6452
6453         if (enable_arguments)
6454                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6455
6456         return code;
6457 }
6458
6459 enum {
6460         SAVE_NONE,
6461         SAVE_STRUCT,
6462         SAVE_EAX,
6463         SAVE_EAX_EDX,
6464         SAVE_XMM
6465 };
6466
6467 void*
6468 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6469 {
6470         guchar *code = p;
6471         int save_mode = SAVE_NONE;
6472         MonoMethod *method = cfg->method;
6473         int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
6474
6475         switch (rtype) {
6476         case MONO_TYPE_VOID:
6477                 /* special case string .ctor icall */
6478                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6479                         save_mode = SAVE_EAX;
6480                 else
6481                         save_mode = SAVE_NONE;
6482                 break;
6483         case MONO_TYPE_I8:
6484         case MONO_TYPE_U8:
6485                 save_mode = SAVE_EAX;
6486                 break;
6487         case MONO_TYPE_R4:
6488         case MONO_TYPE_R8:
6489                 save_mode = SAVE_XMM;
6490                 break;
6491         case MONO_TYPE_GENERICINST:
6492                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
6493                         save_mode = SAVE_EAX;
6494                         break;
6495                 }
6496                 /* Fall through */
6497         case MONO_TYPE_VALUETYPE:
6498                 save_mode = SAVE_STRUCT;
6499                 break;
6500         default:
6501                 save_mode = SAVE_EAX;
6502                 break;
6503         }
6504
6505         /* Save the result and copy it into the proper argument register */
6506         switch (save_mode) {
6507         case SAVE_EAX:
6508                 amd64_push_reg (code, AMD64_RAX);
6509                 /* Align stack */
6510                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6511                 if (enable_arguments)
6512                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6513                 break;
6514         case SAVE_STRUCT:
6515                 /* FIXME: */
6516                 if (enable_arguments)
6517                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6518                 break;
6519         case SAVE_XMM:
6520                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6521                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6522                 /* Align stack */
6523                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6524                 /*
6525                  * The result is already in the proper argument register so no copying
6526                  * needed.
6527                  */
6528                 break;
6529         case SAVE_NONE:
6530                 break;
6531         default:
6532                 g_assert_not_reached ();
6533         }
6534
6535         /* Set %al since this is a varargs call */
6536         if (save_mode == SAVE_XMM)
6537                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6538         else
6539                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6540
6541         if (preserve_argument_registers) {
6542                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6543                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6544         }
6545
6546         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6547         amd64_set_reg_template (code, AMD64_ARG_REG1);
6548         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6549
6550         if (preserve_argument_registers) {
6551                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6552                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6553         }
6554
6555         /* Restore result */
6556         switch (save_mode) {
6557         case SAVE_EAX:
6558                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6559                 amd64_pop_reg (code, AMD64_RAX);
6560                 break;
6561         case SAVE_STRUCT:
6562                 /* FIXME: */
6563                 break;
6564         case SAVE_XMM:
6565                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6566                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6567                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6568                 break;
6569         case SAVE_NONE:
6570                 break;
6571         default:
6572                 g_assert_not_reached ();
6573         }
6574
6575         return code;
6576 }
6577
6578 void
6579 mono_arch_flush_icache (guint8 *code, gint size)
6580 {
6581         /* Not needed */
6582 }
6583
6584 void
6585 mono_arch_flush_register_windows (void)
6586 {
6587 }
6588
6589 gboolean
6590 mono_arch_is_inst_imm (gint64 imm)
6591 {
6592         return amd64_is_imm32 (imm);
6593 }
6594
6595 /*
6596  * Determine whenever the trap whose info is in SIGINFO is caused by
6597  * integer overflow.
6598  */
6599 gboolean
6600 mono_arch_is_int_overflow (void *sigctx, void *info)
6601 {
6602         MonoContext ctx;
6603         guint8* rip;
6604         int reg;
6605         gint64 value;
6606
6607         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6608
6609         rip = (guint8*)ctx.rip;
6610
6611         if (IS_REX (rip [0])) {
6612                 reg = amd64_rex_b (rip [0]);
6613                 rip ++;
6614         }
6615         else
6616                 reg = 0;
6617
6618         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6619                 /* idiv REG */
6620                 reg += x86_modrm_rm (rip [1]);
6621
6622                 switch (reg) {
6623                 case AMD64_RAX:
6624                         value = ctx.rax;
6625                         break;
6626                 case AMD64_RBX:
6627                         value = ctx.rbx;
6628                         break;
6629                 case AMD64_RCX:
6630                         value = ctx.rcx;
6631                         break;
6632                 case AMD64_RDX:
6633                         value = ctx.rdx;
6634                         break;
6635                 case AMD64_RBP:
6636                         value = ctx.rbp;
6637                         break;
6638                 case AMD64_RSP:
6639                         value = ctx.rsp;
6640                         break;
6641                 case AMD64_RSI:
6642                         value = ctx.rsi;
6643                         break;
6644                 case AMD64_RDI:
6645                         value = ctx.rdi;
6646                         break;
6647                 case AMD64_R12:
6648                         value = ctx.r12;
6649                         break;
6650                 case AMD64_R13:
6651                         value = ctx.r13;
6652                         break;
6653                 case AMD64_R14:
6654                         value = ctx.r14;
6655                         break;
6656                 case AMD64_R15:
6657                         value = ctx.r15;
6658                         break;
6659                 default:
6660                         g_assert_not_reached ();
6661                         reg = -1;
6662                 }
6663
6664                 if (value == -1)
6665                         return TRUE;
6666         }
6667
6668         return FALSE;
6669 }
6670
6671 guint32
6672 mono_arch_get_patch_offset (guint8 *code)
6673 {
6674         return 3;
6675 }
6676
6677 /**
6678  * mono_breakpoint_clean_code:
6679  *
6680  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6681  * breakpoints in the original code, they are removed in the copy.
6682  *
6683  * Returns TRUE if no sw breakpoint was present.
6684  */
6685 gboolean
6686 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6687 {
6688         int i;
6689         gboolean can_write = TRUE;
6690         /*
6691          * If method_start is non-NULL we need to perform bound checks, since we access memory
6692          * at code - offset we could go before the start of the method and end up in a different
6693          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6694          * instead.
6695          */
6696         if (!method_start || code - offset >= method_start) {
6697                 memcpy (buf, code - offset, size);
6698         } else {
6699                 int diff = code - method_start;
6700                 memset (buf, 0, size);
6701                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6702         }
6703         code -= offset;
6704         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6705                 int idx = mono_breakpoint_info_index [i];
6706                 guint8 *ptr;
6707                 if (idx < 1)
6708                         continue;
6709                 ptr = mono_breakpoint_info [idx].address;
6710                 if (ptr >= code && ptr < code + size) {
6711                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6712                         can_write = FALSE;
6713                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6714                         buf [ptr - code] = saved_byte;
6715                 }
6716         }
6717         return can_write;
6718 }
6719
6720 gpointer
6721 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6722 {
6723         guint8 buf [10];
6724         guint32 reg;
6725         gint32 disp;
6726         guint8 rex = 0;
6727         MonoJitInfo *ji = NULL;
6728
6729 #ifdef ENABLE_LLVM
6730         /* code - 9 might be before the start of the method */
6731         /* FIXME: Avoid this expensive call somehow */
6732         ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6733 #endif
6734
6735         mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6736         code = buf + 9;
6737
6738         *displacement = 0;
6739
6740         code -= 7;
6741
6742         /*
6743          * A given byte sequence can match more than case here, so we have to be
6744          * really careful about the ordering of the cases. Longer sequences
6745          * come first.
6746          * There are two types of calls:
6747          * - direct calls: 0xff address_byte 8/32 bits displacement
6748          * - indirect calls: nop nop nop <call>
6749          * The nops make sure we don't confuse the instruction preceeding an indirect
6750          * call with a direct call.
6751          */
6752         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6753                 /* call OFFSET(%rip) */
6754                 disp = *(guint32*)(code + 3);
6755                 return (gpointer*)(code + disp + 7);
6756         } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_sib_index (code [2]) == 4) && (amd64_sib_scale (code [2]) == 0)) {
6757                 /* call *[reg+disp32] using indexed addressing */
6758                 /* The LLVM JIT emits this, and we emit it too for %r12 */
6759                 if (IS_REX (code [-1])) {
6760                         rex = code [-1];
6761                         g_assert (amd64_rex_x (rex) == 0);
6762                 }
6763                 reg = amd64_sib_base (code [2]);
6764                 disp = *(gint32*)(code + 3);
6765         } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
6766                 /* call *[reg+disp32] */
6767                 if (IS_REX (code [0]))
6768                         rex = code [0];
6769                 reg = amd64_modrm_rm (code [2]);
6770                 disp = *(gint32*)(code + 3);
6771                 /* R10 is clobbered by the IMT thunk code */
6772                 g_assert (reg != AMD64_R10);
6773         } else if (code [2] == 0xe8) {
6774                 /* call <ADDR> */
6775                 return NULL;
6776         } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_sib_index (code [5]) == 4) && (amd64_sib_scale (code [5]) == 0)) {
6777                 /* call *[r12+disp8] using indexed addressing */
6778                 if (IS_REX (code [2]))
6779                         rex = code [2];
6780                 reg = amd64_sib_base (code [5]);
6781                 disp = *(gint8*)(code + 6);
6782         } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
6783                 /* call *%reg */
6784                 return NULL;
6785         } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
6786                 /* call *[reg+disp8] */
6787                 if (IS_REX (code [3]))
6788                         rex = code [3];
6789                 reg = amd64_modrm_rm (code [5]);
6790                 disp = *(gint8*)(code + 6);
6791                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
6792         }
6793         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
6794                 /* call *%reg */
6795                 if (IS_REX (code [4]))
6796                         rex = code [4];
6797                 reg = amd64_modrm_rm (code [6]);
6798                 disp = 0;
6799         }
6800         else
6801                 g_assert_not_reached ();
6802
6803         reg += amd64_rex_b (rex);
6804
6805         /* R11 is clobbered by the trampoline code */
6806         g_assert (reg != AMD64_R11);
6807
6808         *displacement = disp;
6809         return (gpointer)regs [reg];
6810 }
6811
6812 int
6813 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6814 {
6815         int this_reg = AMD64_ARG_REG1;
6816
6817         if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6818                 CallInfo *cinfo;
6819
6820                 if (!gsctx && code)
6821                         gsctx = mono_get_generic_context_from_code (code);
6822
6823                 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6824
6825                 if (cinfo->ret.storage != ArgValuetypeInReg)
6826                         this_reg = AMD64_ARG_REG2;
6827                 g_free (cinfo);
6828         }
6829
6830         return this_reg;
6831 }
6832
6833 gpointer
6834 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
6835 {
6836         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6837 }
6838
6839 #define MAX_ARCH_DELEGATE_PARAMS 10
6840
6841 static gpointer
6842 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6843 {
6844         guint8 *code, *start;
6845         int i;
6846
6847         if (has_target) {
6848                 start = code = mono_global_codeman_reserve (64);
6849
6850                 /* Replace the this argument with the target */
6851                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6852                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6853                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6854
6855                 g_assert ((code - start) < 64);
6856         } else {
6857                 start = code = mono_global_codeman_reserve (64);
6858
6859                 if (param_count == 0) {
6860                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6861                 } else {
6862                         /* We have to shift the arguments left */
6863                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6864                         for (i = 0; i < param_count; ++i) {
6865 #ifdef PLATFORM_WIN32
6866                                 if (i < 3)
6867                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6868                                 else
6869                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6870 #else
6871                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6872 #endif
6873                         }
6874
6875                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6876                 }
6877                 g_assert ((code - start) < 64);
6878         }
6879
6880         mono_debug_add_delegate_trampoline (start, code - start);
6881
6882         if (code_len)
6883                 *code_len = code - start;
6884
6885         return start;
6886 }
6887
6888 /*
6889  * mono_arch_get_delegate_invoke_impls:
6890  *
6891  *   Return a list of MonoAotTrampInfo structures for the delegate invoke impl
6892  * trampolines.
6893  */
6894 GSList*
6895 mono_arch_get_delegate_invoke_impls (void)
6896 {
6897         GSList *res = NULL;
6898         guint8 *code;
6899         guint32 code_len;
6900         int i;
6901
6902         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
6903         res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len));
6904
6905         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
6906                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
6907                 res = g_slist_prepend (res, mono_aot_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len));
6908         }
6909
6910         return res;
6911 }
6912
6913 gpointer
6914 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6915 {
6916         guint8 *code, *start;
6917         int i;
6918
6919         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6920                 return NULL;
6921
6922         /* FIXME: Support more cases */
6923         if (MONO_TYPE_ISSTRUCT (sig->ret))
6924                 return NULL;
6925
6926         if (has_target) {
6927                 static guint8* cached = NULL;
6928
6929                 if (cached)
6930                         return cached;
6931
6932                 if (mono_aot_only)
6933                         start = mono_aot_get_named_code ("delegate_invoke_impl_has_target");
6934                 else
6935                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
6936
6937                 mono_memory_barrier ();
6938
6939                 cached = start;
6940         } else {
6941                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6942                 for (i = 0; i < sig->param_count; ++i)
6943                         if (!mono_is_regsize_var (sig->params [i]))
6944                                 return NULL;
6945                 if (sig->param_count > 4)
6946                         return NULL;
6947
6948                 code = cache [sig->param_count];
6949                 if (code)
6950                         return code;
6951
6952                 if (mono_aot_only) {
6953                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
6954                         start = mono_aot_get_named_code (name);
6955                         g_free (name);
6956                 } else {
6957                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
6958                 }
6959
6960                 mono_memory_barrier ();
6961
6962                 cache [sig->param_count] = start;
6963         }
6964
6965         return start;
6966 }
6967
6968 /*
6969  * Support for fast access to the thread-local lmf structure using the GS
6970  * segment register on NPTL + kernel 2.6.x.
6971  */
6972
6973 static gboolean tls_offset_inited = FALSE;
6974
6975 void
6976 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6977 {
6978         if (!tls_offset_inited) {
6979 #ifdef PLATFORM_WIN32
6980                 /*
6981                  * We need to init this multiple times, since when we are first called, the key might not
6982                  * be initialized yet.
6983                  */
6984                 appdomain_tls_offset = mono_domain_get_tls_key ();
6985                 lmf_tls_offset = mono_get_jit_tls_key ();
6986                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6987
6988                 /* Only 64 tls entries can be accessed using inline code */
6989                 if (appdomain_tls_offset >= 64)
6990                         appdomain_tls_offset = -1;
6991                 if (lmf_tls_offset >= 64)
6992                         lmf_tls_offset = -1;
6993 #else
6994                 tls_offset_inited = TRUE;
6995 #ifdef MONO_XEN_OPT
6996                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6997 #endif
6998                 appdomain_tls_offset = mono_domain_get_tls_offset ();
6999                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7000                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7001 #endif
7002         }
7003 }
7004
7005 void
7006 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7007 {
7008 }
7009
7010 #ifdef MONO_ARCH_HAVE_IMT
7011
7012 #define CMP_SIZE (6 + 1)
7013 #define CMP_REG_REG_SIZE (4 + 1)
7014 #define BR_SMALL_SIZE 2
7015 #define BR_LARGE_SIZE 6
7016 #define MOV_REG_IMM_SIZE 10
7017 #define MOV_REG_IMM_32BIT_SIZE 6
7018 #define JUMP_REG_SIZE (2 + 1)
7019
7020 static int
7021 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7022 {
7023         int i, distance = 0;
7024         for (i = start; i < target; ++i)
7025                 distance += imt_entries [i]->chunk_size;
7026         return distance;
7027 }
7028
7029 /*
7030  * LOCKING: called with the domain lock held
7031  */
7032 gpointer
7033 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7034         gpointer fail_tramp)
7035 {
7036         int i;
7037         int size = 0;
7038         guint8 *code, *start;
7039         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7040
7041         for (i = 0; i < count; ++i) {
7042                 MonoIMTCheckItem *item = imt_entries [i];
7043                 if (item->is_equals) {
7044                         if (item->check_target_idx) {
7045                                 if (!item->compare_done) {
7046                                         if (amd64_is_imm32 (item->key))
7047                                                 item->chunk_size += CMP_SIZE;
7048                                         else
7049                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7050                                 }
7051                                 if (item->has_target_code) {
7052                                         item->chunk_size += MOV_REG_IMM_SIZE;
7053                                 } else {
7054                                         if (vtable_is_32bit)
7055                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7056                                         else
7057                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7058                                 }
7059                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7060                         } else {
7061                                 if (fail_tramp) {
7062                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7063                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7064                                 } else {
7065                                         if (vtable_is_32bit)
7066                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7067                                         else
7068                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7069                                         item->chunk_size += JUMP_REG_SIZE;
7070                                         /* with assert below:
7071                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7072                                          */
7073                                 }
7074                         }
7075                 } else {
7076                         if (amd64_is_imm32 (item->key))
7077                                 item->chunk_size += CMP_SIZE;
7078                         else
7079                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7080                         item->chunk_size += BR_LARGE_SIZE;
7081                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7082                 }
7083                 size += item->chunk_size;
7084         }
7085         if (fail_tramp)
7086                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7087         else
7088                 code = mono_domain_code_reserve (domain, size);
7089         start = code;
7090         for (i = 0; i < count; ++i) {
7091                 MonoIMTCheckItem *item = imt_entries [i];
7092                 item->code_target = code;
7093                 if (item->is_equals) {
7094                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7095
7096                         if (item->check_target_idx || fail_case) {
7097                                 if (!item->compare_done || fail_case) {
7098                                         if (amd64_is_imm32 (item->key))
7099                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7100                                         else {
7101                                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7102                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7103                                         }
7104                                 }
7105                                 item->jmp_code = code;
7106                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7107                                 /* See the comment below about R10 */
7108                                 if (item->has_target_code) {
7109                                         amd64_mov_reg_imm (code, AMD64_R10, item->value.target_code);
7110                                         amd64_jump_reg (code, AMD64_R10);
7111                                 } else {
7112                                         amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7113                                         amd64_jump_membase (code, AMD64_R10, 0);
7114                                 }
7115
7116                                 if (fail_case) {
7117                                         amd64_patch (item->jmp_code, code);
7118                                         amd64_mov_reg_imm (code, AMD64_R10, fail_tramp);
7119                                         amd64_jump_reg (code, AMD64_R10);
7120                                         item->jmp_code = NULL;
7121                                 }
7122                         } else {
7123                                 /* enable the commented code to assert on wrong method */
7124 #if 0
7125                                 if (amd64_is_imm32 (item->key))
7126                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7127                                 else {
7128                                         amd64_mov_reg_imm (code, AMD64_R10, item->key);
7129                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7130                                 }
7131                                 item->jmp_code = code;
7132                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7133                                 /* See the comment below about R10 */
7134                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7135                                 amd64_jump_membase (code, AMD64_R10, 0);
7136                                 amd64_patch (item->jmp_code, code);
7137                                 amd64_breakpoint (code);
7138                                 item->jmp_code = NULL;
7139 #else
7140                                 /* We're using R10 here because R11
7141                                    needs to be preserved.  R10 needs
7142                                    to be preserved for calls which
7143                                    require a runtime generic context,
7144                                    but interface calls don't. */
7145                                 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->value.vtable_slot]));
7146                                 amd64_jump_membase (code, AMD64_R10, 0);
7147 #endif
7148                         }
7149                 } else {
7150                         if (amd64_is_imm32 (item->key))
7151                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7152                         else {
7153                                 amd64_mov_reg_imm (code, AMD64_R10, item->key);
7154                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
7155                         }
7156                         item->jmp_code = code;
7157                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7158                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7159                         else
7160                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7161                 }
7162                 g_assert (code - item->code_target <= item->chunk_size);
7163         }
7164         /* patch the branches to get to the target items */
7165         for (i = 0; i < count; ++i) {
7166                 MonoIMTCheckItem *item = imt_entries [i];
7167                 if (item->jmp_code) {
7168                         if (item->check_target_idx) {
7169                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7170                         }
7171                 }
7172         }
7173
7174         if (!fail_tramp)
7175                 mono_stats.imt_thunks_size += code - start;
7176         g_assert (code - start <= size);
7177
7178         return start;
7179 }
7180
7181 MonoMethod*
7182 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7183 {
7184         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7185 }
7186
7187 MonoObject*
7188 mono_arch_find_this_argument (mgreg_t *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
7189 {
7190         return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), regs, NULL);
7191 }
7192 #endif
7193
7194 MonoVTable*
7195 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7196 {
7197         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7198 }
7199
7200 MonoInst*
7201 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7202 {
7203         MonoInst *ins = NULL;
7204         int opcode = 0;
7205
7206         if (cmethod->klass == mono_defaults.math_class) {
7207                 if (strcmp (cmethod->name, "Sin") == 0) {
7208                         opcode = OP_SIN;
7209                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7210                         opcode = OP_COS;
7211                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7212                         opcode = OP_SQRT;
7213                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7214                         opcode = OP_ABS;
7215                 }
7216
7217                 if (opcode) {
7218                         MONO_INST_NEW (cfg, ins, opcode);
7219                         ins->type = STACK_R8;
7220                         ins->dreg = mono_alloc_freg (cfg);
7221                         ins->sreg1 = args [0]->dreg;
7222                         MONO_ADD_INS (cfg->cbb, ins);
7223                 }
7224
7225                 opcode = 0;
7226                 if (cfg->opt & MONO_OPT_CMOV) {
7227                         if (strcmp (cmethod->name, "Min") == 0) {
7228                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7229                                         opcode = OP_IMIN;
7230                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7231                                         opcode = OP_IMIN_UN;
7232                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7233                                         opcode = OP_LMIN;
7234                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7235                                         opcode = OP_LMIN_UN;
7236                         } else if (strcmp (cmethod->name, "Max") == 0) {
7237                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7238                                         opcode = OP_IMAX;
7239                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7240                                         opcode = OP_IMAX_UN;
7241                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7242                                         opcode = OP_LMAX;
7243                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7244                                         opcode = OP_LMAX_UN;
7245                         }
7246                 }
7247
7248                 if (opcode) {
7249                         MONO_INST_NEW (cfg, ins, opcode);
7250                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7251                         ins->dreg = mono_alloc_ireg (cfg);
7252                         ins->sreg1 = args [0]->dreg;
7253                         ins->sreg2 = args [1]->dreg;
7254                         MONO_ADD_INS (cfg->cbb, ins);
7255                 }
7256
7257 #if 0
7258                 /* OP_FREM is not IEEE compatible */
7259                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7260                         MONO_INST_NEW (cfg, ins, OP_FREM);
7261                         ins->inst_i0 = args [0];
7262                         ins->inst_i1 = args [1];
7263                 }
7264 #endif
7265         }
7266
7267         /*
7268          * Can't implement CompareExchange methods this way since they have
7269          * three arguments.
7270          */
7271
7272         return ins;
7273 }
7274
7275 gboolean
7276 mono_arch_print_tree (MonoInst *tree, int arity)
7277 {
7278         return 0;
7279 }
7280
7281 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7282 {
7283         MonoInst* ins;
7284
7285         if (appdomain_tls_offset == -1)
7286                 return NULL;
7287
7288         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7289         ins->inst_offset = appdomain_tls_offset;
7290         return ins;
7291 }
7292
7293 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7294
7295 gpointer
7296 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7297 {
7298         switch (reg) {
7299         case AMD64_RCX: return (gpointer)ctx->rcx;
7300         case AMD64_RDX: return (gpointer)ctx->rdx;
7301         case AMD64_RBX: return (gpointer)ctx->rbx;
7302         case AMD64_RBP: return (gpointer)ctx->rbp;
7303         case AMD64_RSP: return (gpointer)ctx->rsp;
7304         default:
7305                 if (reg < 8)
7306                         return _CTX_REG (ctx, rax, reg);
7307                 else if (reg >= 12)
7308                         return _CTX_REG (ctx, r12, reg - 12);
7309                 else
7310                         g_assert_not_reached ();
7311         }
7312 }