mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *
  11  * (C) 2003 Ximian, Inc.
  12  */
  13 #include "mini.h"
  14 #include <string.h>
  15 #include <math.h>
  16 #include <unistd.h>
  17
  18 #include <mono/metadata/appdomain.h>
  19 #include <mono/metadata/debug-helpers.h>
  20 #include <mono/metadata/threads.h>
  21 #include <mono/metadata/profiler-private.h>
  22 #include <mono/metadata/mono-debug.h>
  23 #include <mono/utils/mono-math.h>
  24
  25 #include "trace.h"
  26 #include "mini-amd64.h"
  27 #include "inssel.h"
  28 #include "cpu-amd64.h"
  29
  30 static gint lmf_tls_offset = -1;
  31 static gint lmf_addr_tls_offset = -1;
  32 static gint appdomain_tls_offset = -1;
  33 static gint thread_tls_offset = -1;
  34
  35 #ifdef MONO_XEN_OPT
  36 static gboolean optimize_for_xen = TRUE;
  37 #else
  38 #define optimize_for_xen 0
  39 #endif
  40
  41 static gboolean use_sse2 = !MONO_ARCH_USE_FPSTACK;
  42
  43 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  44
  45 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  46
  47 #ifdef PLATFORM_WIN32
  48 /* Under windows, the default pinvoke calling convention is stdcall */
  49 #define CALLCONV_IS_STDCALL(call_conv) (((call_conv) == MONO_CALL_STDCALL) || ((call_conv) == MONO_CALL_DEFAULT))
  50 #else
  51 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  52 #endif
  53
  54 #define ARGS_OFFSET 16
  55 #define GP_SCRATCH_REG AMD64_R11
  56
  57 /*
  58  * AMD64 register usage:
  59  * - callee saved registers are used for global register allocation
  60  * - %r11 is used for materializing 64 bit constants in opcodes
  61  * - the rest is used for local allocation
  62  */
  63
  64 /*
  65  * Floating point comparison results:
  66  *                  ZF PF CF
  67  * A > B            0  0  0
  68  * A < B            0  0  1
  69  * A = B            1  0  0
  70  * A > B            0  0  0
  71  * UNORDERED        1  1  1
  72  */
  73
  74 #define NOT_IMPLEMENTED g_assert_not_reached ()
  75
  76 const char*
  77 mono_arch_regname (int reg) {
  78         switch (reg) {
  79         case AMD64_RAX: return "%rax";
  80         case AMD64_RBX: return "%rbx";
  81         case AMD64_RCX: return "%rcx";
  82         case AMD64_RDX: return "%rdx";
  83         case AMD64_RSP: return "%rsp";
  84         case AMD64_RBP: return "%rbp";
  85         case AMD64_RDI: return "%rdi";
  86         case AMD64_RSI: return "%rsi";
  87         case AMD64_R8: return "%r8";
  88         case AMD64_R9: return "%r9";
  89         case AMD64_R10: return "%r10";
  90         case AMD64_R11: return "%r11";
  91         case AMD64_R12: return "%r12";
  92         case AMD64_R13: return "%r13";
  93         case AMD64_R14: return "%r14";
  94         case AMD64_R15: return "%r15";
  95         }
  96         return "unknown";
  97 }
  98
  99 static const char * xmmregs [] = {
 100         "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
 101         "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
 102 };
 103
 104 const char*
 105 mono_arch_fregname (int reg)
 106 {
 107         if (reg < AMD64_XMM_NREG)
 108                 return xmmregs [reg];
 109         else
 110                 return "unknown";
 111 }
 112
 113 G_GNUC_UNUSED static void
 114 break_count (void)
 115 {
 116 }
 117
 118 G_GNUC_UNUSED static gboolean
 119 debug_count (void)
 120 {
 121         static int count = 0;
 122         count ++;
 123
 124         if (!getenv ("COUNT"))
 125                 return TRUE;
 126
 127         if (count == atoi (getenv ("COUNT"))) {
 128                 break_count ();
 129         }
 130
 131         if (count > atoi (getenv ("COUNT"))) {
 132                 return FALSE;
 133         }
 134
 135         return TRUE;
 136 }
 137
 138 static gboolean
 139 debug_omit_fp (void)
 140 {
 141 #if 0
 142         return debug_count ();
 143 #else
 144         return TRUE;
 145 #endif
 146 }
 147
 148 static inline gboolean
 149 amd64_is_near_call (guint8 *code)
 150 {
 151         /* Skip REX */
 152         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 153                 code += 1;
 154
 155         return code [0] == 0xe8;
 156 }
 157
 158 static inline void
 159 amd64_patch (unsigned char* code, gpointer target)
 160 {
 161         /* Skip REX */
 162         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 163                 code += 1;
 164
 165         if ((code [0] & 0xf8) == 0xb8) {
 166                 /* amd64_set_reg_template */
 167                 *(guint64*)(code + 1) = (guint64)target;
 168         }
 169         else if (code [0] == 0x8b) {
 170                 /* mov 0(%rip), %dreg */
 171                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 172         }
 173         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 174                 /* call *<OFFSET>(%rip) */
 175                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 176         }
 177         else if ((code [0] == 0xe8)) {
 178                 /* call <DISP> */
 179                 gint64 disp = (guint8*)target - (guint8*)code;
 180                 g_assert (amd64_is_imm32 (disp));
 181                 x86_patch (code, (unsigned char*)target);
 182         }
 183         else
 184                 x86_patch (code, (unsigned char*)target);
 185 }
 186
 187 typedef enum {
 188         ArgInIReg,
 189         ArgInFloatSSEReg,
 190         ArgInDoubleSSEReg,
 191         ArgOnStack,
 192         ArgValuetypeInReg,
 193         ArgNone /* only in pair_storage */
 194 } ArgStorage;
 195
 196 typedef struct {
 197         gint16 offset;
 198         gint8  reg;
 199         ArgStorage storage;
 200
 201         /* Only if storage == ArgValuetypeInReg */
 202         ArgStorage pair_storage [2];
 203         gint8 pair_regs [2];
 204 } ArgInfo;
 205
 206 typedef struct {
 207         int nargs;
 208         guint32 stack_usage;
 209         guint32 reg_usage;
 210         guint32 freg_usage;
 211         gboolean need_stack_align;
 212         ArgInfo ret;
 213         ArgInfo sig_cookie;
 214         ArgInfo args [1];
 215 } CallInfo;
 216
 217 #define DEBUG(a) if (cfg->verbose_level > 1) a
 218
 219 #define NEW_ICONST(cfg,dest,val) do {   \
 220                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
 221                 (dest)->opcode = OP_ICONST;     \
 222                 (dest)->inst_c0 = (val);        \
 223                 (dest)->type = STACK_I4;        \
 224         } while (0)
 225
 226 #define PARAM_REGS 6
 227
 228 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 229
 230 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 231
 232 static void inline
 233 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 234 {
 235     ainfo->offset = *stack_size;
 236
 237     if (*gr >= PARAM_REGS) {
 238                 ainfo->storage = ArgOnStack;
 239                 (*stack_size) += sizeof (gpointer);
 240     }
 241     else {
 242                 ainfo->storage = ArgInIReg;
 243                 ainfo->reg = param_regs [*gr];
 244                 (*gr) ++;
 245     }
 246 }
 247
 248 #define FLOAT_PARAM_REGS 8
 249
 250 static void inline
 251 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 252 {
 253     ainfo->offset = *stack_size;
 254
 255     if (*gr >= FLOAT_PARAM_REGS) {
 256                 ainfo->storage = ArgOnStack;
 257                 (*stack_size) += sizeof (gpointer);
 258     }
 259     else {
 260                 /* A double register */
 261                 if (is_double)
 262                         ainfo->storage = ArgInDoubleSSEReg;
 263                 else
 264                         ainfo->storage = ArgInFloatSSEReg;
 265                 ainfo->reg = *gr;
 266                 (*gr) += 1;
 267     }
 268 }
 269
 270 typedef enum ArgumentClass {
 271         ARG_CLASS_NO_CLASS,
 272         ARG_CLASS_MEMORY,
 273         ARG_CLASS_INTEGER,
 274         ARG_CLASS_SSE
 275 } ArgumentClass;
 276
 277 static ArgumentClass
 278 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 279 {
 280         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 281         MonoType *ptype;
 282
 283         ptype = mono_type_get_underlying_type (type);
 284         switch (ptype->type) {
 285         case MONO_TYPE_BOOLEAN:
 286         case MONO_TYPE_CHAR:
 287         case MONO_TYPE_I1:
 288         case MONO_TYPE_U1:
 289         case MONO_TYPE_I2:
 290         case MONO_TYPE_U2:
 291         case MONO_TYPE_I4:
 292         case MONO_TYPE_U4:
 293         case MONO_TYPE_I:
 294         case MONO_TYPE_U:
 295         case MONO_TYPE_STRING:
 296         case MONO_TYPE_OBJECT:
 297         case MONO_TYPE_CLASS:
 298         case MONO_TYPE_SZARRAY:
 299         case MONO_TYPE_PTR:
 300         case MONO_TYPE_FNPTR:
 301         case MONO_TYPE_ARRAY:
 302         case MONO_TYPE_I8:
 303         case MONO_TYPE_U8:
 304                 class2 = ARG_CLASS_INTEGER;
 305                 break;
 306         case MONO_TYPE_R4:
 307         case MONO_TYPE_R8:
 308                 class2 = ARG_CLASS_SSE;
 309                 break;
 310
 311         case MONO_TYPE_TYPEDBYREF:
 312                 g_assert_not_reached ();
 313
 314         case MONO_TYPE_GENERICINST:
 315                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 316                         class2 = ARG_CLASS_INTEGER;
 317                         break;
 318                 }
 319                 /* fall through */
 320         case MONO_TYPE_VALUETYPE: {
 321                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 322                 int i;
 323
 324                 for (i = 0; i < info->num_fields; ++i) {
 325                         class2 = class1;
 326                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 327                 }
 328                 break;
 329         }
 330         default:
 331                 g_assert_not_reached ();
 332         }
 333
 334         /* Merge */
 335         if (class1 == class2)
 336                 ;
 337         else if (class1 == ARG_CLASS_NO_CLASS)
 338                 class1 = class2;
 339         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 340                 class1 = ARG_CLASS_MEMORY;
 341         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 342                 class1 = ARG_CLASS_INTEGER;
 343         else
 344                 class1 = ARG_CLASS_SSE;
 345
 346         return class1;
 347 }
 348
 349 static void
 350 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 351                gboolean is_return,
 352                guint32 *gr, guint32 *fr, guint32 *stack_size)
 353 {
 354         guint32 size, quad, nquads, i;
 355         ArgumentClass args [2];
 356         MonoMarshalType *info;
 357         MonoClass *klass;
 358
 359         klass = mono_class_from_mono_type (type);
 360         if (sig->pinvoke)
 361                 size = mono_type_native_stack_size (&klass->byval_arg, NULL);
 362         else
 363                 size = mono_type_stack_size (&klass->byval_arg, NULL);
 364
 365         if (!sig->pinvoke || (size == 0) || (size > 16)) {
 366                 /* Allways pass in memory */
 367                 ainfo->offset = *stack_size;
 368                 *stack_size += ALIGN_TO (size, 8);
 369                 ainfo->storage = ArgOnStack;
 370
 371                 return;
 372         }
 373
 374         /* FIXME: Handle structs smaller than 8 bytes */
 375         //if ((size % 8) != 0)
 376         //      NOT_IMPLEMENTED;
 377
 378         if (size > 8)
 379                 nquads = 2;
 380         else
 381                 nquads = 1;
 382
 383         /*
 384          * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 385          * The X87 and SSEUP stuff is left out since there are no such types in
 386          * the CLR.
 387          */
 388         info = mono_marshal_load_type_info (klass);
 389         g_assert (info);
 390         if (info->native_size > 16) {
 391                 ainfo->offset = *stack_size;
 392                 *stack_size += ALIGN_TO (info->native_size, 8);
 393                 ainfo->storage = ArgOnStack;
 394
 395                 return;
 396         }
 397
 398         args [0] = ARG_CLASS_NO_CLASS;
 399         args [1] = ARG_CLASS_NO_CLASS;
 400         for (quad = 0; quad < nquads; ++quad) {
 401                 int size;
 402                 guint32 align;
 403                 ArgumentClass class1;
 404
 405                 class1 = ARG_CLASS_NO_CLASS;
 406                 for (i = 0; i < info->num_fields; ++i) {
 407                         size = mono_marshal_type_size (info->fields [i].field->type,
 408                                                                                    info->fields [i].mspec,
 409                                                                                    &align, TRUE, klass->unicode);
 410                         if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 411                                 /* Unaligned field */
 412                                 NOT_IMPLEMENTED;
 413                         }
 414
 415                         /* Skip fields in other quad */
 416                         if ((quad == 0) && (info->fields [i].offset >= 8))
 417                                 continue;
 418                         if ((quad == 1) && (info->fields [i].offset < 8))
 419                                 continue;
 420
 421                         class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 422                 }
 423                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 424                 args [quad] = class1;
 425         }
 426
 427         /* Post merger cleanup */
 428         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 429                 args [0] = args [1] = ARG_CLASS_MEMORY;
 430
 431         /* Allocate registers */
 432         {
 433                 int orig_gr = *gr;
 434                 int orig_fr = *fr;
 435
 436                 ainfo->storage = ArgValuetypeInReg;
 437                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 438                 for (quad = 0; quad < nquads; ++quad) {
 439                         switch (args [quad]) {
 440                         case ARG_CLASS_INTEGER:
 441                                 if (*gr >= PARAM_REGS)
 442                                         args [quad] = ARG_CLASS_MEMORY;
 443                                 else {
 444                                         ainfo->pair_storage [quad] = ArgInIReg;
 445                                         if (is_return)
 446                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 447                                         else
 448                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 449                                         (*gr) ++;
 450                                 }
 451                                 break;
 452                         case ARG_CLASS_SSE:
 453                                 if (*fr >= FLOAT_PARAM_REGS)
 454                                         args [quad] = ARG_CLASS_MEMORY;
 455                                 else {
 456                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 457                                         ainfo->pair_regs [quad] = *fr;
 458                                         (*fr) ++;
 459                                 }
 460                                 break;
 461                         case ARG_CLASS_MEMORY:
 462                                 break;
 463                         default:
 464                                 g_assert_not_reached ();
 465                         }
 466                 }
 467
 468                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 469                         /* Revert possible register assignments */
 470                         *gr = orig_gr;
 471                         *fr = orig_fr;
 472
 473                         ainfo->offset = *stack_size;
 474                         *stack_size += ALIGN_TO (info->native_size, 8);
 475                         ainfo->storage = ArgOnStack;
 476                 }
 477         }
 478 }
 479
 480 /*
 481  * get_call_info:
 482  *
 483  *  Obtain information about a call according to the calling convention.
 484  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 485  * Draft Version 0.23" document for more information.
 486  */
 487 static CallInfo*
 488 get_call_info (MonoMethodSignature *sig, gboolean is_pinvoke)
 489 {
 490         guint32 i, gr, fr;
 491         MonoType *ret_type;
 492         int n = sig->hasthis + sig->param_count;
 493         guint32 stack_size = 0;
 494         CallInfo *cinfo;
 495
 496         cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 497
 498         gr = 0;
 499         fr = 0;
 500
 501         /* return value */
 502         {
 503                 ret_type = mono_type_get_underlying_type (sig->ret);
 504                 switch (ret_type->type) {
 505                 case MONO_TYPE_BOOLEAN:
 506                 case MONO_TYPE_I1:
 507                 case MONO_TYPE_U1:
 508                 case MONO_TYPE_I2:
 509                 case MONO_TYPE_U2:
 510                 case MONO_TYPE_CHAR:
 511                 case MONO_TYPE_I4:
 512                 case MONO_TYPE_U4:
 513                 case MONO_TYPE_I:
 514                 case MONO_TYPE_U:
 515                 case MONO_TYPE_PTR:
 516                 case MONO_TYPE_FNPTR:
 517                 case MONO_TYPE_CLASS:
 518                 case MONO_TYPE_OBJECT:
 519                 case MONO_TYPE_SZARRAY:
 520                 case MONO_TYPE_ARRAY:
 521                 case MONO_TYPE_STRING:
 522                         cinfo->ret.storage = ArgInIReg;
 523                         cinfo->ret.reg = AMD64_RAX;
 524                         break;
 525                 case MONO_TYPE_U8:
 526                 case MONO_TYPE_I8:
 527                         cinfo->ret.storage = ArgInIReg;
 528                         cinfo->ret.reg = AMD64_RAX;
 529                         break;
 530                 case MONO_TYPE_R4:
 531                         cinfo->ret.storage = ArgInFloatSSEReg;
 532                         cinfo->ret.reg = AMD64_XMM0;
 533                         break;
 534                 case MONO_TYPE_R8:
 535                         cinfo->ret.storage = ArgInDoubleSSEReg;
 536                         cinfo->ret.reg = AMD64_XMM0;
 537                         break;
 538                 case MONO_TYPE_GENERICINST:
 539                         if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
 540                                 cinfo->ret.storage = ArgInIReg;
 541                                 cinfo->ret.reg = AMD64_RAX;
 542                                 break;
 543                         }
 544                         /* fall through */
 545                 case MONO_TYPE_VALUETYPE: {
 546                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 547
 548                         add_valuetype (sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 549                         if (cinfo->ret.storage == ArgOnStack)
 550                                 /* The caller passes the address where the value is stored */
 551                                 add_general (&gr, &stack_size, &cinfo->ret);
 552                         break;
 553                 }
 554                 case MONO_TYPE_TYPEDBYREF:
 555                         /* Same as a valuetype with size 24 */
 556                         add_general (&gr, &stack_size, &cinfo->ret);
 557                         ;
 558                         break;
 559                 case MONO_TYPE_VOID:
 560                         break;
 561                 default:
 562                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 563                 }
 564         }
 565
 566         /* this */
 567         if (sig->hasthis)
 568                 add_general (&gr, &stack_size, cinfo->args + 0);
 569
 570         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 571                 gr = PARAM_REGS;
 572                 fr = FLOAT_PARAM_REGS;
 573
 574                 /* Emit the signature cookie just before the implicit arguments */
 575                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 576         }
 577
 578         for (i = 0; i < sig->param_count; ++i) {
 579                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 580                 MonoType *ptype;
 581
 582                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 583                         /* We allways pass the sig cookie on the stack for simplicity */
 584                         /*
 585                          * Prevent implicit arguments + the sig cookie from being passed
 586                          * in registers.
 587                          */
 588                         gr = PARAM_REGS;
 589                         fr = FLOAT_PARAM_REGS;
 590
 591                         /* Emit the signature cookie just before the implicit arguments */
 592                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 593                 }
 594
 595                 if (sig->params [i]->byref) {
 596                         add_general (&gr, &stack_size, ainfo);
 597                         continue;
 598                 }
 599                 ptype = mono_type_get_underlying_type (sig->params [i]);
 600                 switch (ptype->type) {
 601                 case MONO_TYPE_BOOLEAN:
 602                 case MONO_TYPE_I1:
 603                 case MONO_TYPE_U1:
 604                         add_general (&gr, &stack_size, ainfo);
 605                         break;
 606                 case MONO_TYPE_I2:
 607                 case MONO_TYPE_U2:
 608                 case MONO_TYPE_CHAR:
 609                         add_general (&gr, &stack_size, ainfo);
 610                         break;
 611                 case MONO_TYPE_I4:
 612                 case MONO_TYPE_U4:
 613                         add_general (&gr, &stack_size, ainfo);
 614                         break;
 615                 case MONO_TYPE_I:
 616                 case MONO_TYPE_U:
 617                 case MONO_TYPE_PTR:
 618                 case MONO_TYPE_FNPTR:
 619                 case MONO_TYPE_CLASS:
 620                 case MONO_TYPE_OBJECT:
 621                 case MONO_TYPE_STRING:
 622                 case MONO_TYPE_SZARRAY:
 623                 case MONO_TYPE_ARRAY:
 624                         add_general (&gr, &stack_size, ainfo);
 625                         break;
 626                 case MONO_TYPE_GENERICINST:
 627                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 628                                 add_general (&gr, &stack_size, ainfo);
 629                                 break;
 630                         }
 631                         /* fall through */
 632                 case MONO_TYPE_VALUETYPE:
 633                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 634                         break;
 635                 case MONO_TYPE_TYPEDBYREF:
 636                         stack_size += sizeof (MonoTypedRef);
 637                         ainfo->storage = ArgOnStack;
 638                         break;
 639                 case MONO_TYPE_U8:
 640                 case MONO_TYPE_I8:
 641                         add_general (&gr, &stack_size, ainfo);
 642                         break;
 643                 case MONO_TYPE_R4:
 644                         add_float (&fr, &stack_size, ainfo, FALSE);
 645                         break;
 646                 case MONO_TYPE_R8:
 647                         add_float (&fr, &stack_size, ainfo, TRUE);
 648                         break;
 649                 default:
 650                         g_assert_not_reached ();
 651                 }
 652         }
 653
 654         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 655                 gr = PARAM_REGS;
 656                 fr = FLOAT_PARAM_REGS;
 657
 658                 /* Emit the signature cookie just before the implicit arguments */
 659                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 660         }
 661
 662         if (stack_size & 0x8) {
 663                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 664                 cinfo->need_stack_align = TRUE;
 665                 stack_size += 8;
 666         }
 667
 668         cinfo->stack_usage = stack_size;
 669         cinfo->reg_usage = gr;
 670         cinfo->freg_usage = fr;
 671         return cinfo;
 672 }
 673
 674 /*
 675  * mono_arch_get_argument_info:
 676  * @csig:  a method signature
 677  * @param_count: the number of parameters to consider
 678  * @arg_info: an array to store the result infos
 679  *
 680  * Gathers information on parameters such as size, alignment and
 681  * padding. arg_info should be large enought to hold param_count + 1 entries.
 682  *
 683  * Returns the size of the argument area on the stack.
 684  */
 685 int
 686 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 687 {
 688         int k;
 689         CallInfo *cinfo = get_call_info (csig, FALSE);
 690         guint32 args_size = cinfo->stack_usage;
 691
 692         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 693         if (csig->hasthis) {
 694                 arg_info [0].offset = 0;
 695         }
 696
 697         for (k = 0; k < param_count; k++) {
 698                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 699                 /* FIXME: */
 700                 arg_info [k + 1].size = 0;
 701         }
 702
 703         g_free (cinfo);
 704
 705         return args_size;
 706 }
 707
 708 static int
 709 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 710 {
 711         return 0;
 712 }
 713
 714 /*
 715  * Initialize the cpu to execute managed code.
 716  */
 717 void
 718 mono_arch_cpu_init (void)
 719 {
 720         guint16 fpcw;
 721
 722         /* spec compliance requires running with double precision */
 723         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 724         fpcw &= ~X86_FPCW_PRECC_MASK;
 725         fpcw |= X86_FPCW_PREC_DOUBLE;
 726         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 727         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 728 }
 729
 730 /*
 731  * This function returns the optimizations supported on this cpu.
 732  */
 733 guint32
 734 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 735 {
 736         int eax, ebx, ecx, edx;
 737         guint32 opts = 0;
 738
 739         /* FIXME: AMD64 */
 740
 741         *exclude_mask = 0;
 742         /* Feature Flags function, flags returned in EDX. */
 743         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 744                 if (edx & (1 << 15)) {
 745                         opts |= MONO_OPT_CMOV;
 746                         if (edx & 1)
 747                                 opts |= MONO_OPT_FCMOV;
 748                         else
 749                                 *exclude_mask |= MONO_OPT_FCMOV;
 750                 } else
 751                         *exclude_mask |= MONO_OPT_CMOV;
 752         }
 753         return opts;
 754 }
 755
 756 gboolean
 757 mono_amd64_is_sse2 (void)
 758 {
 759         return use_sse2;
 760 }
 761
 762 static gboolean
 763 is_regsize_var (MonoType *t) {
 764         if (t->byref)
 765                 return TRUE;
 766         t = mono_type_get_underlying_type (t);
 767         switch (t->type) {
 768         case MONO_TYPE_I4:
 769         case MONO_TYPE_U4:
 770         case MONO_TYPE_I:
 771         case MONO_TYPE_U:
 772         case MONO_TYPE_PTR:
 773         case MONO_TYPE_FNPTR:
 774                 return TRUE;
 775         case MONO_TYPE_OBJECT:
 776         case MONO_TYPE_STRING:
 777         case MONO_TYPE_CLASS:
 778         case MONO_TYPE_SZARRAY:
 779         case MONO_TYPE_ARRAY:
 780                 return TRUE;
 781         case MONO_TYPE_GENERICINST:
 782                 if (!mono_type_generic_inst_is_valuetype (t))
 783                         return TRUE;
 784                 return FALSE;
 785         case MONO_TYPE_VALUETYPE:
 786                 return FALSE;
 787         }
 788         return FALSE;
 789 }
 790
 791 GList *
 792 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
 793 {
 794         GList *vars = NULL;
 795         int i;
 796
 797         for (i = 0; i < cfg->num_varinfo; i++) {
 798                 MonoInst *ins = cfg->varinfo [i];
 799                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
 800
 801                 /* unused vars */
 802                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
 803                         continue;
 804
 805                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
 806                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
 807                         continue;
 808
 809                 /* we dont allocate I1 to registers because there is no simply way to sign extend
 810                  * 8bit quantities in caller saved registers on x86 */
 811                 if (is_regsize_var (ins->inst_vtype) || (ins->inst_vtype->type == MONO_TYPE_BOOLEAN) ||
 812                     (ins->inst_vtype->type == MONO_TYPE_U1) || (ins->inst_vtype->type == MONO_TYPE_U2)||
 813                     (ins->inst_vtype->type == MONO_TYPE_I2) || (ins->inst_vtype->type == MONO_TYPE_CHAR)) {
 814                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
 815                         g_assert (i == vmv->idx);
 816                         vars = g_list_prepend (vars, vmv);
 817                 }
 818         }
 819
 820         vars = mono_varlist_sort (cfg, vars, 0);
 821
 822         return vars;
 823 }
 824
 825 /**
 826  * mono_arch_compute_omit_fp:
 827  *
 828  *   Determine whenever the frame pointer can be eliminated.
 829  */
 830 static void
 831 mono_arch_compute_omit_fp (MonoCompile *cfg)
 832 {
 833         MonoMethodSignature *sig;
 834         MonoMethodHeader *header;
 835         int i;
 836         CallInfo *cinfo;
 837
 838         if (cfg->arch.omit_fp_computed)
 839                 return;
 840
 841         header = mono_method_get_header (cfg->method);
 842
 843         sig = mono_method_signature (cfg->method);
 844
 845         cinfo = get_call_info (sig, FALSE);
 846
 847         /*
 848          * FIXME: Remove some of the restrictions.
 849          */
 850         cfg->arch.omit_fp = TRUE;
 851         cfg->arch.omit_fp_computed = TRUE;
 852
 853         /* Temporarily disable this when running in the debugger until we have support
 854          * for this in the debugger. */
 855         if (mono_debug_using_mono_debugger ())
 856                 cfg->arch.omit_fp = FALSE;
 857
 858         if (!debug_omit_fp ())
 859                 cfg->arch.omit_fp = FALSE;
 860         /*
 861         if (cfg->method->save_lmf)
 862                 cfg->arch.omit_fp = FALSE;
 863         */
 864         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
 865                 cfg->arch.omit_fp = FALSE;
 866         if (header->num_clauses)
 867                 cfg->arch.omit_fp = FALSE;
 868         if (cfg->param_area)
 869                 cfg->arch.omit_fp = FALSE;
 870         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
 871                 cfg->arch.omit_fp = FALSE;
 872         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
 873                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
 874                 cfg->arch.omit_fp = FALSE;
 875         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
 876                 ArgInfo *ainfo = &cinfo->args [i];
 877
 878                 if (ainfo->storage == ArgOnStack) {
 879                         /*
 880                          * The stack offset can only be determined when the frame
 881                          * size is known.
 882                          */
 883                         cfg->arch.omit_fp = FALSE;
 884                 }
 885         }
 886
 887         if (cfg->num_varinfo > 10000) {
 888                 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
 889                 cfg->arch.omit_fp = FALSE;
 890         }
 891
 892         g_free (cinfo);
 893 }
 894
 895 GList *
 896 mono_arch_get_global_int_regs (MonoCompile *cfg)
 897 {
 898         GList *regs = NULL;
 899
 900         mono_arch_compute_omit_fp (cfg);
 901
 902         if (cfg->arch.omit_fp)
 903                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
 904
 905         /* We use the callee saved registers for global allocation */
 906         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
 907         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
 908         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
 909         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
 910         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
 911
 912         return regs;
 913 }
 914
 915 /*
 916  * mono_arch_regalloc_cost:
 917  *
 918  *  Return the cost, in number of memory references, of the action of
 919  * allocating the variable VMV into a register during global register
 920  * allocation.
 921  */
 922 guint32
 923 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
 924 {
 925         MonoInst *ins = cfg->varinfo [vmv->idx];
 926
 927         if (cfg->method->save_lmf)
 928                 /* The register is already saved */
 929                 /* substract 1 for the invisible store in the prolog */
 930                 return (ins->opcode == OP_ARG) ? 0 : 1;
 931         else
 932                 /* push+pop */
 933                 return (ins->opcode == OP_ARG) ? 1 : 2;
 934 }
 935
 936 void
 937 mono_arch_allocate_vars (MonoCompile *cfg)
 938 {
 939         MonoMethodSignature *sig;
 940         MonoMethodHeader *header;
 941         MonoInst *inst;
 942         int i, offset;
 943         guint32 locals_stack_size, locals_stack_align;
 944         gint32 *offsets;
 945         CallInfo *cinfo;
 946
 947         header = mono_method_get_header (cfg->method);
 948
 949         sig = mono_method_signature (cfg->method);
 950
 951         cinfo = get_call_info (sig, FALSE);
 952
 953         mono_arch_compute_omit_fp (cfg);
 954
 955         /*
 956          * We use the ABI calling conventions for managed code as well.
 957          * Exception: valuetypes are never passed or returned in registers.
 958          */
 959
 960         if (cfg->arch.omit_fp) {
 961                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
 962                 cfg->frame_reg = AMD64_RSP;
 963                 offset = 0;
 964         } else {
 965                 /* Locals are allocated backwards from %fp */
 966                 cfg->frame_reg = AMD64_RBP;
 967                 offset = 0;
 968         }
 969
 970         cfg->arch.reg_save_area_offset = offset;
 971
 972         /* Reserve space for caller saved registers */
 973         for (i = 0; i < AMD64_NREG; ++i)
 974                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
 975                         offset += sizeof (gpointer);
 976                 }
 977
 978         if (cfg->method->save_lmf) {
 979                 /* Reserve stack space for saving LMF + argument regs */
 980                 guint32 size = sizeof (MonoLMF);
 981
 982                 if (lmf_addr_tls_offset == -1)
 983                         /* Need to save argument regs too */
 984                         size += (AMD64_NREG * 8) + (8 * 8);
 985
 986                 if (cfg->arch.omit_fp) {
 987                         cfg->arch.lmf_offset = offset;
 988                         offset += size;
 989                 }
 990                 else {
 991                         offset += size;
 992                         cfg->arch.lmf_offset = -offset;
 993                 }
 994         }
 995
 996         if (sig->ret->type != MONO_TYPE_VOID) {
 997                 switch (cinfo->ret.storage) {
 998                 case ArgInIReg:
 999                 case ArgInFloatSSEReg:
1000                 case ArgInDoubleSSEReg:
1001                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1002                                 /* The register is volatile */
1003                                 cfg->ret->opcode = OP_REGOFFSET;
1004                                 cfg->ret->inst_basereg = cfg->frame_reg;
1005                                 if (cfg->arch.omit_fp) {
1006                                         cfg->ret->inst_offset = offset;
1007                                         offset += 8;
1008                                 } else {
1009                                         offset += 8;
1010                                         cfg->ret->inst_offset = -offset;
1011                                 }
1012                         }
1013                         else {
1014                                 cfg->ret->opcode = OP_REGVAR;
1015                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1016                         }
1017                         break;
1018                 case ArgValuetypeInReg:
1019                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1020                         g_assert (!cfg->arch.omit_fp);
1021                         offset += 16;
1022                         cfg->ret->opcode = OP_REGOFFSET;
1023                         cfg->ret->inst_basereg = cfg->frame_reg;
1024                         cfg->ret->inst_offset = - offset;
1025                         break;
1026                 default:
1027                         g_assert_not_reached ();
1028                 }
1029                 cfg->ret->dreg = cfg->ret->inst_c0;
1030         }
1031
1032         /* Allocate locals */
1033         offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1034         if (locals_stack_align) {
1035                 offset += (locals_stack_align - 1);
1036                 offset &= ~(locals_stack_align - 1);
1037         }
1038         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1039                 if (offsets [i] != -1) {
1040                         MonoInst *inst = cfg->varinfo [i];
1041                         inst->opcode = OP_REGOFFSET;
1042                         inst->inst_basereg = cfg->frame_reg;
1043                         if (cfg->arch.omit_fp)
1044                                 inst->inst_offset = (offset + offsets [i]);
1045                         else
1046                                 inst->inst_offset = - (offset + offsets [i]);
1047                         //printf ("allocated local %d to ", i); mono_print_tree_nl (inst);
1048                 }
1049         }
1050         offset += locals_stack_size;
1051
1052         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1053                 g_assert (!cfg->arch.omit_fp);
1054                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1055                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1056         }
1057
1058         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1059                 inst = cfg->varinfo [i];
1060                 if (inst->opcode != OP_REGVAR) {
1061                         ArgInfo *ainfo = &cinfo->args [i];
1062                         gboolean inreg = TRUE;
1063                         MonoType *arg_type;
1064
1065                         if (sig->hasthis && (i == 0))
1066                                 arg_type = &mono_defaults.object_class->byval_arg;
1067                         else
1068                                 arg_type = sig->params [i - sig->hasthis];
1069
1070                         /* FIXME: Allocate volatile arguments to registers */
1071                         if (inst->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1072                                 inreg = FALSE;
1073
1074                         /*
1075                          * Under AMD64, all registers used to pass arguments to functions
1076                          * are volatile across calls.
1077                          * FIXME: Optimize this.
1078                          */
1079                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1080                                 inreg = FALSE;
1081
1082                         inst->opcode = OP_REGOFFSET;
1083
1084                         switch (ainfo->storage) {
1085                         case ArgInIReg:
1086                         case ArgInFloatSSEReg:
1087                         case ArgInDoubleSSEReg:
1088                                 inst->opcode = OP_REGVAR;
1089                                 inst->dreg = ainfo->reg;
1090                                 break;
1091                         case ArgOnStack:
1092                                 g_assert (!cfg->arch.omit_fp);
1093                                 inst->opcode = OP_REGOFFSET;
1094                                 inst->inst_basereg = cfg->frame_reg;
1095                                 inst->inst_offset = ainfo->offset + ARGS_OFFSET;
1096                                 break;
1097                         case ArgValuetypeInReg:
1098                                 break;
1099                         default:
1100                                 NOT_IMPLEMENTED;
1101                         }
1102
1103                         if (!inreg && (ainfo->storage != ArgOnStack)) {
1104                                 inst->opcode = OP_REGOFFSET;
1105                                 inst->inst_basereg = cfg->frame_reg;
1106                                 /* These arguments are saved to the stack in the prolog */
1107                                 if (cfg->arch.omit_fp) {
1108                                         inst->inst_offset = offset;
1109                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1110                                 } else {
1111                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1112                                         inst->inst_offset = - offset;
1113                                 }
1114                         }
1115                 }
1116         }
1117
1118         cfg->stack_offset = offset;
1119
1120         g_free (cinfo);
1121 }
1122
1123 void
1124 mono_arch_create_vars (MonoCompile *cfg)
1125 {
1126         MonoMethodSignature *sig;
1127         CallInfo *cinfo;
1128
1129         sig = mono_method_signature (cfg->method);
1130
1131         cinfo = get_call_info (sig, FALSE);
1132
1133         if (cinfo->ret.storage == ArgValuetypeInReg)
1134                 cfg->ret_var_is_local = TRUE;
1135
1136         g_free (cinfo);
1137 }
1138
1139 static void
1140 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1141 {
1142         switch (storage) {
1143         case ArgInIReg:
1144                 arg->opcode = OP_OUTARG_REG;
1145                 arg->inst_left = tree;
1146                 arg->inst_call = call;
1147                 arg->backend.reg3 = reg;
1148                 break;
1149         case ArgInFloatSSEReg:
1150                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1151                 arg->inst_left = tree;
1152                 arg->inst_call = call;
1153                 arg->backend.reg3 = reg;
1154                 break;
1155         case ArgInDoubleSSEReg:
1156                 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1157                 arg->inst_left = tree;
1158                 arg->inst_call = call;
1159                 arg->backend.reg3 = reg;
1160                 break;
1161         default:
1162                 g_assert_not_reached ();
1163         }
1164 }
1165
1166 /* Fixme: we need an alignment solution for enter_method and mono_arch_call_opcode,
1167  * currently alignment in mono_arch_call_opcode is computed without arch_get_argument_info
1168  */
1169
1170 static int
1171 arg_storage_to_ldind (ArgStorage storage)
1172 {
1173         switch (storage) {
1174         case ArgInIReg:
1175                 return CEE_LDIND_I;
1176         case ArgInDoubleSSEReg:
1177                 return CEE_LDIND_R8;
1178         case ArgInFloatSSEReg:
1179                 return CEE_LDIND_R4;
1180         default:
1181                 g_assert_not_reached ();
1182         }
1183
1184         return -1;
1185 }
1186
1187 static void
1188 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1189 {
1190         MonoInst *arg;
1191         MonoMethodSignature *tmp_sig;
1192         MonoInst *sig_arg;
1193
1194         /* FIXME: Add support for signature tokens to AOT */
1195         cfg->disable_aot = TRUE;
1196
1197         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1198
1199         /*
1200          * mono_ArgIterator_Setup assumes the signature cookie is
1201          * passed first and all the arguments which were before it are
1202          * passed on the stack after the signature. So compensate by
1203          * passing a different signature.
1204          */
1205         tmp_sig = mono_metadata_signature_dup (call->signature);
1206         tmp_sig->param_count -= call->signature->sentinelpos;
1207         tmp_sig->sentinelpos = 0;
1208         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1209
1210         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1211         sig_arg->inst_p0 = tmp_sig;
1212
1213         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1214         arg->inst_left = sig_arg;
1215         arg->type = STACK_PTR;
1216
1217         /* prepend, so they get reversed */
1218         arg->next = call->out_args;
1219         call->out_args = arg;
1220 }
1221
1222 /*
1223  * take the arguments and generate the arch-specific
1224  * instructions to properly call the function in call.
1225  * This includes pushing, moving arguments to the right register
1226  * etc.
1227  * Issue: who does the spilling if needed, and when?
1228  */
1229 MonoCallInst*
1230 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1231         MonoInst *arg, *in;
1232         MonoMethodSignature *sig;
1233         int i, n, stack_size;
1234         CallInfo *cinfo;
1235         ArgInfo *ainfo;
1236
1237         stack_size = 0;
1238
1239         sig = call->signature;
1240         n = sig->param_count + sig->hasthis;
1241
1242         cinfo = get_call_info (sig, sig->pinvoke);
1243
1244         for (i = 0; i < n; ++i) {
1245                 ainfo = cinfo->args + i;
1246
1247                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1248                         /* Emit the signature cookie just before the implicit arguments */
1249                         emit_sig_cookie (cfg, call, cinfo);
1250                 }
1251
1252                 if (is_virtual && i == 0) {
1253                         /* the argument will be attached to the call instruction */
1254                         in = call->args [i];
1255                 } else {
1256                         MONO_INST_NEW (cfg, arg, OP_OUTARG);
1257                         in = call->args [i];
1258                         arg->cil_code = in->cil_code;
1259                         arg->inst_left = in;
1260                         arg->type = in->type;
1261                         /* prepend, so they get reversed */
1262                         arg->next = call->out_args;
1263                         call->out_args = arg;
1264
1265                         if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1266                                 guint32 align;
1267                                 guint32 size;
1268
1269                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1270                                         size = sizeof (MonoTypedRef);
1271                                         align = sizeof (gpointer);
1272                                 }
1273                                 else
1274                                 if (sig->pinvoke)
1275                                         size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1276                                 else {
1277                                         /*
1278                                          * Other backends use mono_type_stack_size (), but that
1279                                          * aligns the size to 8, which is larger than the size of
1280                                          * the source, leading to reads of invalid memory if the
1281                                          * source is at the end of address space.
1282                                          */
1283                                         size = mono_class_value_size (in->klass, &align);
1284                                 }
1285                                 if (ainfo->storage == ArgValuetypeInReg) {
1286                                         if (ainfo->pair_storage [1] == ArgNone) {
1287                                                 MonoInst *load;
1288
1289                                                 /* Simpler case */
1290
1291                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1292                                                 load->inst_left = in;
1293
1294                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1295                                         }
1296                                         else {
1297                                                 /* Trees can't be shared so make a copy */
1298                                                 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1299                                                 MonoInst *load, *load2, *offset_ins;
1300
1301                                                 /* Reg1 */
1302                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1303                                                 load->ssa_op = MONO_SSA_LOAD;
1304                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1305
1306                                                 NEW_ICONST (cfg, offset_ins, 0);
1307                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1308                                                 load2->inst_left = load;
1309                                                 load2->inst_right = offset_ins;
1310
1311                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1312                                                 load->inst_left = load2;
1313
1314                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1315
1316                                                 /* Reg2 */
1317                                                 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1318                                                 load->ssa_op = MONO_SSA_LOAD;
1319                                                 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1320
1321                                                 NEW_ICONST (cfg, offset_ins, 8);
1322                                                 MONO_INST_NEW (cfg, load2, CEE_ADD);
1323                                                 load2->inst_left = load;
1324                                                 load2->inst_right = offset_ins;
1325
1326                                                 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1327                                                 load->inst_left = load2;
1328
1329                                                 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1330                                                 arg->cil_code = in->cil_code;
1331                                                 arg->type = in->type;
1332                                                 /* prepend, so they get reversed */
1333                                                 arg->next = call->out_args;
1334                                                 call->out_args = arg;
1335
1336                                                 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1337
1338                                                 /* Prepend a copy inst */
1339                                                 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1340                                                 arg->cil_code = in->cil_code;
1341                                                 arg->ssa_op = MONO_SSA_STORE;
1342                                                 arg->inst_left = vtaddr;
1343                                                 arg->inst_right = in;
1344                                                 arg->type = in->type;
1345
1346                                                 /* prepend, so they get reversed */
1347                                                 arg->next = call->out_args;
1348                                                 call->out_args = arg;
1349                                         }
1350                                 }
1351                                 else {
1352                                         arg->opcode = OP_OUTARG_VT;
1353                                         arg->klass = in->klass;
1354                                         arg->backend.is_pinvoke = sig->pinvoke;
1355                                         arg->inst_imm = size;
1356                                 }
1357                         }
1358                         else {
1359                                 switch (ainfo->storage) {
1360                                 case ArgInIReg:
1361                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1362                                         break;
1363                                 case ArgInFloatSSEReg:
1364                                 case ArgInDoubleSSEReg:
1365                                         add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1366                                         break;
1367                                 case ArgOnStack:
1368                                         arg->opcode = OP_OUTARG;
1369                                         if (!sig->params [i - sig->hasthis]->byref) {
1370                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1371                                                         arg->opcode = OP_OUTARG_R4;
1372                                                 else
1373                                                         if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1374                                                                 arg->opcode = OP_OUTARG_R8;
1375                                         }
1376                                         break;
1377                                 default:
1378                                         g_assert_not_reached ();
1379                                 }
1380                         }
1381                 }
1382         }
1383
1384         /* Handle the case where there are no implicit arguments */
1385         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1386                 emit_sig_cookie (cfg, call, cinfo);
1387         }
1388
1389         if (cinfo->need_stack_align) {
1390                 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1391                 /* prepend, so they get reversed */
1392                 arg->next = call->out_args;
1393                 call->out_args = arg;
1394         }
1395
1396         call->stack_usage = cinfo->stack_usage;
1397         cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1398         cfg->flags |= MONO_CFG_HAS_CALLS;
1399
1400         g_free (cinfo);
1401
1402         return call;
1403 }
1404
1405 #define EMIT_COND_BRANCH(ins,cond,sign) \
1406 if (ins->flags & MONO_INST_BRLABEL) { \
1407         if (ins->inst_i0->inst_c0) { \
1408                 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
1409         } else { \
1410                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
1411                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1412                     x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
1413                         x86_branch8 (code, cond, 0, sign); \
1414                 else \
1415                         x86_branch32 (code, cond, 0, sign); \
1416         } \
1417 } else { \
1418         if (ins->inst_true_bb->native_offset) { \
1419                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
1420         } else { \
1421                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
1422                 if ((cfg->opt & MONO_OPT_BRANCH) && \
1423                     x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
1424                         x86_branch8 (code, cond, 0, sign); \
1425                 else \
1426                         x86_branch32 (code, cond, 0, sign); \
1427         } \
1428 }
1429
1430 /* emit an exception if condition is fail */
1431 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
1432         do {                                                        \
1433                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
1434                 if (tins == NULL) {                                                                             \
1435                         mono_add_patch_info (cfg, code - cfg->native_code,   \
1436                                         MONO_PATCH_INFO_EXC, exc_name);  \
1437                         x86_branch32 (code, cond, 0, signed);               \
1438                 } else {        \
1439                         EMIT_COND_BRANCH (tins, cond, signed);  \
1440                 }                       \
1441         } while (0);
1442
1443 #define EMIT_FPCOMPARE(code) do { \
1444         amd64_fcompp (code); \
1445         amd64_fnstsw (code); \
1446 } while (0);
1447
1448 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
1449     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
1450         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
1451         amd64_ ##op (code); \
1452         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
1453         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
1454 } while (0);
1455
1456 static guint8*
1457 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1458 {
1459         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1460
1461         /*
1462          * FIXME: Add support for thunks
1463          */
1464         {
1465                 gboolean near_call = FALSE;
1466
1467                 /*
1468                  * Indirect calls are expensive so try to make a near call if possible.
1469                  * The caller memory is allocated by the code manager so it is
1470                  * guaranteed to be at a 32 bit offset.
1471                  */
1472
1473                 if (patch_type != MONO_PATCH_INFO_ABS) {
1474                         /* The target is in memory allocated using the code manager */
1475                         near_call = TRUE;
1476
1477                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
1478                                 if (((MonoMethod*)data)->klass->image->assembly->aot_module)
1479                                         /* The callee might be an AOT method */
1480                                         near_call = FALSE;
1481                         }
1482
1483                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
1484                                 /*
1485                                  * The call might go directly to a native function without
1486                                  * the wrapper.
1487                                  */
1488                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
1489                                 if (mi) {
1490                                         gconstpointer target = mono_icall_get_wrapper (mi);
1491                                         if ((((guint64)target) >> 32) != 0)
1492                                                 near_call = FALSE;
1493                                 }
1494                         }
1495                 }
1496                 else {
1497                         if (mono_find_class_init_trampoline_by_addr (data))
1498                                 near_call = TRUE;
1499                         else {
1500                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
1501                                 if (info) {
1502                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
1503                                                 strstr (cfg->method->name, info->name)) {
1504                                                 /* A call to the wrapped function */
1505                                                 if ((((guint64)data) >> 32) == 0)
1506                                                         near_call = TRUE;
1507                                         }
1508                                         else if (info->func == info->wrapper) {
1509                                                 /* No wrapper */
1510                                                 if ((((guint64)info->func) >> 32) == 0)
1511                                                         near_call = TRUE;
1512                                         }
1513                                         else {
1514                                                 /* See the comment in mono_codegen () */
1515                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
1516                                                         near_call = TRUE;
1517                                         }
1518                                 }
1519                                 else if ((((guint64)data) >> 32) == 0)
1520                                         near_call = TRUE;
1521                         }
1522                 }
1523
1524                 if (cfg->method->dynamic)
1525                         /* These methods are allocated using malloc */
1526                         near_call = FALSE;
1527
1528                 if (cfg->compile_aot)
1529                         near_call = TRUE;
1530
1531 #ifdef MONO_ARCH_NOMAP32BIT
1532                 near_call = FALSE;
1533 #endif
1534
1535                 if (near_call) {
1536                         amd64_call_code (code, 0);
1537                 }
1538                 else {
1539                         amd64_set_reg_template (code, GP_SCRATCH_REG);
1540                         amd64_call_reg (code, GP_SCRATCH_REG);
1541                 }
1542         }
1543
1544         return code;
1545 }
1546
1547 static inline guint8*
1548 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
1549 {
1550         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
1551
1552         return emit_call_body (cfg, code, patch_type, data);
1553 }
1554
1555 /* FIXME: Add more instructions */
1556 #define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode == OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) || ((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
1557
1558 static void
1559 peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1560 {
1561         MonoInst *ins, *last_ins = NULL;
1562         ins = bb->code;
1563
1564         while (ins) {
1565
1566                 switch (ins->opcode) {
1567                 case OP_ICONST:
1568                 case OP_I8CONST:
1569                         /* reg = 0 -> XOR (reg, reg) */
1570                         /* XOR sets cflags on x86, so we cant do it always */
1571                         if (ins->inst_c0 == 0 && (ins->next && INST_IGNORES_CFLAGS (ins->next))) {
1572                                 ins->opcode = CEE_XOR;
1573                                 ins->sreg1 = ins->dreg;
1574                                 ins->sreg2 = ins->dreg;
1575                         }
1576                         break;
1577                 case OP_MUL_IMM:
1578                         /* remove unnecessary multiplication with 1 */
1579                         if (ins->inst_imm == 1) {
1580                                 if (ins->dreg != ins->sreg1) {
1581                                         ins->opcode = OP_MOVE;
1582                                 } else {
1583                                         last_ins->next = ins->next;
1584                                         ins = ins->next;
1585                                         continue;
1586                                 }
1587                         }
1588                         break;
1589                 case OP_COMPARE_IMM:
1590                         /* OP_COMPARE_IMM (reg, 0)
1591                          * -->
1592                          * OP_AMD64_TEST_NULL (reg)
1593                          */
1594                         if (!ins->inst_imm)
1595                                 ins->opcode = OP_AMD64_TEST_NULL;
1596                         break;
1597                 case OP_ICOMPARE_IMM:
1598                         if (!ins->inst_imm)
1599                                 ins->opcode = OP_X86_TEST_NULL;
1600                         break;
1601                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
1602                         /*
1603                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1604                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
1605                          * -->
1606                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
1607                          * OP_COMPARE_IMM reg, imm
1608                          *
1609                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
1610                          */
1611                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
1612                             ins->inst_basereg == last_ins->inst_destbasereg &&
1613                             ins->inst_offset == last_ins->inst_offset) {
1614                                         ins->opcode = OP_ICOMPARE_IMM;
1615                                         ins->sreg1 = last_ins->sreg1;
1616
1617                                         /* check if we can remove cmp reg,0 with test null */
1618                                         if (!ins->inst_imm)
1619                                                 ins->opcode = OP_X86_TEST_NULL;
1620                                 }
1621
1622                         break;
1623                 case OP_LOAD_MEMBASE:
1624                 case OP_LOADI4_MEMBASE:
1625                         /*
1626                          * Note: if reg1 = reg2 the load op is removed
1627                          *
1628                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1629                          * OP_LOAD_MEMBASE offset(basereg), reg2
1630                          * -->
1631                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1632                          * OP_MOVE reg1, reg2
1633                          */
1634                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
1635                                          || last_ins->opcode == OP_STORE_MEMBASE_REG) &&
1636                             ins->inst_basereg == last_ins->inst_destbasereg &&
1637                             ins->inst_offset == last_ins->inst_offset) {
1638                                 if (ins->dreg == last_ins->sreg1) {
1639                                         last_ins->next = ins->next;
1640                                         ins = ins->next;
1641                                         continue;
1642                                 } else {
1643                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1644                                         ins->opcode = OP_MOVE;
1645                                         ins->sreg1 = last_ins->sreg1;
1646                                 }
1647
1648                         /*
1649                          * Note: reg1 must be different from the basereg in the second load
1650                          * Note: if reg1 = reg2 is equal then second load is removed
1651                          *
1652                          * OP_LOAD_MEMBASE offset(basereg), reg1
1653                          * OP_LOAD_MEMBASE offset(basereg), reg2
1654                          * -->
1655                          * OP_LOAD_MEMBASE offset(basereg), reg1
1656                          * OP_MOVE reg1, reg2
1657                          */
1658                         } if (last_ins && (last_ins->opcode == OP_LOADI4_MEMBASE
1659                                            || last_ins->opcode == OP_LOAD_MEMBASE) &&
1660                               ins->inst_basereg != last_ins->dreg &&
1661                               ins->inst_basereg == last_ins->inst_basereg &&
1662                               ins->inst_offset == last_ins->inst_offset) {
1663
1664                                 if (ins->dreg == last_ins->dreg) {
1665                                         last_ins->next = ins->next;
1666                                         ins = ins->next;
1667                                         continue;
1668                                 } else {
1669                                         ins->opcode = OP_MOVE;
1670                                         ins->sreg1 = last_ins->dreg;
1671                                 }
1672
1673                                 //g_assert_not_reached ();
1674
1675 #if 0
1676                         /*
1677                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1678                          * OP_LOAD_MEMBASE offset(basereg), reg
1679                          * -->
1680                          * OP_STORE_MEMBASE_IMM imm, offset(basereg)
1681                          * OP_ICONST reg, imm
1682                          */
1683                         } else if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_IMM
1684                                                 || last_ins->opcode == OP_STORE_MEMBASE_IMM) &&
1685                                    ins->inst_basereg == last_ins->inst_destbasereg &&
1686                                    ins->inst_offset == last_ins->inst_offset) {
1687                                 //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1688                                 ins->opcode = OP_ICONST;
1689                                 ins->inst_c0 = last_ins->inst_imm;
1690                                 g_assert_not_reached (); // check this rule
1691 #endif
1692                         }
1693                         break;
1694                 case OP_LOADU1_MEMBASE:
1695                 case OP_LOADI1_MEMBASE:
1696                         /*
1697                          * Note: if reg1 = reg2 the load op is removed
1698                          *
1699                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1700                          * OP_LOAD_MEMBASE offset(basereg), reg2
1701                          * -->
1702                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1703                          * OP_MOVE reg1, reg2
1704                          */
1705                         if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
1706                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1707                                         ins->inst_offset == last_ins->inst_offset) {
1708                                 if (ins->dreg == last_ins->sreg1) {
1709                                         last_ins->next = ins->next;
1710                                         ins = ins->next;
1711                                         continue;
1712                                 } else {
1713                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1714                                         ins->opcode = OP_MOVE;
1715                                         ins->sreg1 = last_ins->sreg1;
1716                                 }
1717                         }
1718                         break;
1719                 case OP_LOADU2_MEMBASE:
1720                 case OP_LOADI2_MEMBASE:
1721                         /*
1722                          * Note: if reg1 = reg2 the load op is removed
1723                          *
1724                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1725                          * OP_LOAD_MEMBASE offset(basereg), reg2
1726                          * -->
1727                          * OP_STORE_MEMBASE_REG reg1, offset(basereg)
1728                          * OP_MOVE reg1, reg2
1729                          */
1730                         if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
1731                                         ins->inst_basereg == last_ins->inst_destbasereg &&
1732                                         ins->inst_offset == last_ins->inst_offset) {
1733                                 if (ins->dreg == last_ins->sreg1) {
1734                                         last_ins->next = ins->next;
1735                                         ins = ins->next;
1736                                         continue;
1737                                 } else {
1738                                         //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
1739                                         ins->opcode = OP_MOVE;
1740                                         ins->sreg1 = last_ins->sreg1;
1741                                 }
1742                         }
1743                         break;
1744                 case CEE_CONV_I4:
1745                 case CEE_CONV_U4:
1746                 case OP_MOVE:
1747                         /*
1748                          * Removes:
1749                          *
1750                          * OP_MOVE reg, reg
1751                          */
1752                         if (ins->dreg == ins->sreg1) {
1753                                 if (last_ins)
1754                                         last_ins->next = ins->next;
1755                                 ins = ins->next;
1756                                 continue;
1757                         }
1758                         /*
1759                          * Removes:
1760                          *
1761                          * OP_MOVE sreg, dreg
1762                          * OP_MOVE dreg, sreg
1763                          */
1764                         if (last_ins && last_ins->opcode == OP_MOVE &&
1765                             ins->sreg1 == last_ins->dreg &&
1766                             ins->dreg == last_ins->sreg1) {
1767                                 last_ins->next = ins->next;
1768                                 ins = ins->next;
1769                                 continue;
1770                         }
1771                         break;
1772                 }
1773                 last_ins = ins;
1774                 ins = ins->next;
1775         }
1776         bb->last_ins = last_ins;
1777 }
1778
1779 static void
1780 insert_after_ins (MonoBasicBlock *bb, MonoInst *ins, MonoInst *to_insert)
1781 {
1782         if (ins == NULL) {
1783                 ins = bb->code;
1784                 bb->code = to_insert;
1785                 to_insert->next = ins;
1786         }
1787         else {
1788                 to_insert->next = ins->next;
1789                 ins->next = to_insert;
1790         }
1791 }
1792
1793 #define NEW_INS(cfg,dest,op) do {       \
1794                 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst));       \
1795                 (dest)->opcode = (op);  \
1796         insert_after_ins (bb, last_ins, (dest)); \
1797         } while (0)
1798
1799 /*
1800  * mono_arch_lowering_pass:
1801  *
1802  *  Converts complex opcodes into simpler ones so that each IR instruction
1803  * corresponds to one machine instruction.
1804  */
1805 static void
1806 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
1807 {
1808         MonoInst *ins, *temp, *last_ins = NULL;
1809         ins = bb->code;
1810
1811         if (bb->max_ireg > cfg->rs->next_vireg)
1812                 cfg->rs->next_vireg = bb->max_ireg;
1813         if (bb->max_freg > cfg->rs->next_vfreg)
1814                 cfg->rs->next_vfreg = bb->max_freg;
1815
1816         /*
1817          * FIXME: Need to add more instructions, but the current machine
1818          * description can't model some parts of the composite instructions like
1819          * cdq.
1820          */
1821         while (ins) {
1822                 switch (ins->opcode) {
1823                 case OP_DIV_IMM:
1824                 case OP_REM_IMM:
1825                 case OP_IDIV_IMM:
1826                 case OP_IREM_IMM:
1827                         NEW_INS (cfg, temp, OP_ICONST);
1828                         temp->inst_c0 = ins->inst_imm;
1829                         temp->dreg = mono_regstate_next_int (cfg->rs);
1830                         switch (ins->opcode) {
1831                         case OP_DIV_IMM:
1832                                 ins->opcode = OP_LDIV;
1833                                 break;
1834                         case OP_REM_IMM:
1835                                 ins->opcode = OP_LREM;
1836                                 break;
1837                         case OP_IDIV_IMM:
1838                                 ins->opcode = OP_IDIV;
1839                                 break;
1840                         case OP_IREM_IMM:
1841                                 ins->opcode = OP_IREM;
1842                                 break;
1843                         }
1844                         ins->sreg2 = temp->dreg;
1845                         break;
1846                 case OP_COMPARE_IMM:
1847                         if (!amd64_is_imm32 (ins->inst_imm)) {
1848                                 NEW_INS (cfg, temp, OP_I8CONST);
1849                                 temp->inst_c0 = ins->inst_imm;
1850                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1851                                 ins->opcode = OP_COMPARE;
1852                                 ins->sreg2 = temp->dreg;
1853                         }
1854                         break;
1855                 case OP_LOAD_MEMBASE:
1856                 case OP_LOADI8_MEMBASE:
1857                         if (!amd64_is_imm32 (ins->inst_offset)) {
1858                                 NEW_INS (cfg, temp, OP_I8CONST);
1859                                 temp->inst_c0 = ins->inst_offset;
1860                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1861                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
1862                                 ins->inst_indexreg = temp->dreg;
1863                         }
1864                         break;
1865                 case OP_STORE_MEMBASE_IMM:
1866                 case OP_STOREI8_MEMBASE_IMM:
1867                         if (!amd64_is_imm32 (ins->inst_imm)) {
1868                                 NEW_INS (cfg, temp, OP_I8CONST);
1869                                 temp->inst_c0 = ins->inst_imm;
1870                                 temp->dreg = mono_regstate_next_int (cfg->rs);
1871                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
1872                                 ins->sreg1 = temp->dreg;
1873                         }
1874                         break;
1875                 default:
1876                         break;
1877                 }
1878                 last_ins = ins;
1879                 ins = ins->next;
1880         }
1881         bb->last_ins = last_ins;
1882
1883         bb->max_ireg = cfg->rs->next_vireg;
1884         bb->max_freg = cfg->rs->next_vfreg;
1885 }
1886
1887 static const int
1888 branch_cc_table [] = {
1889         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1890         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
1891         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
1892 };
1893
1894 static int
1895 opcode_to_x86_cond (int opcode)
1896 {
1897         switch (opcode) {
1898         case OP_IBEQ:
1899                 return X86_CC_EQ;
1900         case OP_IBNE_UN:
1901                 return X86_CC_NE;
1902         case OP_IBLT:
1903                 return X86_CC_LT;
1904         case OP_IBLT_UN:
1905                 return X86_CC_LT;
1906         case OP_IBGT:
1907                 return X86_CC_GT;
1908         case OP_IBGT_UN:
1909                 return X86_CC_GT;
1910         case OP_IBGE:
1911                 return X86_CC_GE;
1912         case OP_IBGE_UN:
1913                 return X86_CC_GE;
1914         case OP_IBLE:
1915                 return X86_CC_LE;
1916         case OP_IBLE_UN:
1917                 return X86_CC_LE;
1918         case OP_COND_EXC_IOV:
1919                 return X86_CC_O;
1920         case OP_COND_EXC_IC:
1921                 return X86_CC_C;
1922         default:
1923                 g_assert_not_reached ();
1924         }
1925
1926         return -1;
1927 }
1928
1929 /*#include "cprop.c"*/
1930
1931 /*
1932  * Local register allocation.
1933  * We first scan the list of instructions and we save the liveness info of
1934  * each register (when the register is first used, when it's value is set etc.).
1935  * We also reverse the list of instructions (in the InstList list) because assigning
1936  * registers backwards allows for more tricks to be used.
1937  */
1938 void
1939 mono_arch_local_regalloc (MonoCompile *cfg, MonoBasicBlock *bb)
1940 {
1941         if (!bb->code)
1942                 return;
1943
1944         mono_arch_lowering_pass (cfg, bb);
1945
1946         mono_local_regalloc (cfg, bb);
1947 }
1948
1949 static unsigned char*
1950 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
1951 {
1952         if (use_sse2) {
1953                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
1954         }
1955         else {
1956                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
1957                 x86_fnstcw_membase(code, AMD64_RSP, 0);
1958                 amd64_mov_reg_membase (code, dreg, AMD64_RSP, 0, 2);
1959                 amd64_alu_reg_imm (code, X86_OR, dreg, 0xc00);
1960                 amd64_mov_membase_reg (code, AMD64_RSP, 2, dreg, 2);
1961                 amd64_fldcw_membase (code, AMD64_RSP, 2);
1962                 amd64_push_reg (code, AMD64_RAX); // SP = SP - 8
1963                 amd64_fist_pop_membase (code, AMD64_RSP, 0, size == 8);
1964                 amd64_pop_reg (code, dreg);
1965                 amd64_fldcw_membase (code, AMD64_RSP, 0);
1966                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
1967         }
1968
1969         if (size == 1)
1970                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
1971         else if (size == 2)
1972                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
1973         return code;
1974 }
1975
1976 static unsigned char*
1977 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
1978 {
1979         int sreg = tree->sreg1;
1980         int need_touch = FALSE;
1981
1982 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
1983         if (!tree->flags & MONO_INST_INIT)
1984                 need_touch = TRUE;
1985 #endif
1986
1987         if (need_touch) {
1988                 guint8* br[5];
1989
1990                 /*
1991                  * Under Windows:
1992                  * If requested stack size is larger than one page,
1993                  * perform stack-touch operation
1994                  */
1995                 /*
1996                  * Generate stack probe code.
1997                  * Under Windows, it is necessary to allocate one page at a time,
1998                  * "touching" stack after each successful sub-allocation. This is
1999                  * because of the way stack growth is implemented - there is a
2000                  * guard page before the lowest stack page that is currently commited.
2001                  * Stack normally grows sequentially so OS traps access to the
2002                  * guard page and commits more pages when needed.
2003                  */
2004                 amd64_test_reg_imm (code, sreg, ~0xFFF);
2005                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2006
2007                 br[2] = code; /* loop */
2008                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2009                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2010                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2011                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2012                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2013                 amd64_patch (br[3], br[2]);
2014                 amd64_test_reg_reg (code, sreg, sreg);
2015                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2016                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2017
2018                 br[1] = code; x86_jump8 (code, 0);
2019
2020                 amd64_patch (br[0], code);
2021                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2022                 amd64_patch (br[1], code);
2023                 amd64_patch (br[4], code);
2024         }
2025         else
2026                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2027
2028         if (tree->flags & MONO_INST_INIT) {
2029                 int offset = 0;
2030                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2031                         amd64_push_reg (code, AMD64_RAX);
2032                         offset += 8;
2033                 }
2034                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2035                         amd64_push_reg (code, AMD64_RCX);
2036                         offset += 8;
2037                 }
2038                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2039                         amd64_push_reg (code, AMD64_RDI);
2040                         offset += 8;
2041                 }
2042
2043                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2044                 if (sreg != AMD64_RCX)
2045                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2046                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2047
2048                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2049                 amd64_cld (code);
2050                 amd64_prefix (code, X86_REP_PREFIX);
2051                 amd64_stosl (code);
2052
2053                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2054                         amd64_pop_reg (code, AMD64_RDI);
2055                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2056                         amd64_pop_reg (code, AMD64_RCX);
2057                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2058                         amd64_pop_reg (code, AMD64_RAX);
2059         }
2060         return code;
2061 }
2062
2063 static guint8*
2064 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2065 {
2066         CallInfo *cinfo;
2067         guint32 quad;
2068
2069         /* Move return value to the target register */
2070         /* FIXME: do this in the local reg allocator */
2071         switch (ins->opcode) {
2072         case CEE_CALL:
2073         case OP_CALL_REG:
2074         case OP_CALL_MEMBASE:
2075         case OP_LCALL:
2076         case OP_LCALL_REG:
2077         case OP_LCALL_MEMBASE:
2078                 g_assert (ins->dreg == AMD64_RAX);
2079                 break;
2080         case OP_FCALL:
2081         case OP_FCALL_REG:
2082         case OP_FCALL_MEMBASE:
2083                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2084                         if (use_sse2)
2085                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2086                         else {
2087                                 /* FIXME: optimize this */
2088                                 amd64_movss_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2089                                 amd64_fld_membase (code, AMD64_RSP, -8, FALSE);
2090                         }
2091                 }
2092                 else {
2093                         if (use_sse2) {
2094                                 if (ins->dreg != AMD64_XMM0)
2095                                         amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2096                         }
2097                         else {
2098                                 /* FIXME: optimize this */
2099                                 amd64_movsd_membase_reg (code, AMD64_RSP, -8, AMD64_XMM0);
2100                                 amd64_fld_membase (code, AMD64_RSP, -8, TRUE);
2101                         }
2102                 }
2103                 break;
2104         case OP_VCALL:
2105         case OP_VCALL_REG:
2106         case OP_VCALL_MEMBASE:
2107                 cinfo = get_call_info (((MonoCallInst*)ins)->signature, FALSE);
2108                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2109                         /* Pop the destination address from the stack */
2110                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
2111                         amd64_pop_reg (code, AMD64_RCX);
2112
2113                         for (quad = 0; quad < 2; quad ++) {
2114                                 switch (cinfo->ret.pair_storage [quad]) {
2115                                 case ArgInIReg:
2116                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2117                                         break;
2118                                 case ArgInFloatSSEReg:
2119                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2120                                         break;
2121                                 case ArgInDoubleSSEReg:
2122                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2123                                         break;
2124                                 case ArgNone:
2125                                         break;
2126                                 default:
2127                                         NOT_IMPLEMENTED;
2128                                 }
2129                         }
2130                 }
2131                 g_free (cinfo);
2132                 break;
2133         }
2134
2135         return code;
2136 }
2137
2138 /*
2139  * emit_tls_get:
2140  * @code: buffer to store code to
2141  * @dreg: hard register where to place the result
2142  * @tls_offset: offset info
2143  *
2144  * emit_tls_get emits in @code the native code that puts in the dreg register
2145  * the item in the thread local storage identified by tls_offset.
2146  *
2147  * Returns: a pointer to the end of the stored code
2148  */
2149 static guint8*
2150 emit_tls_get (guint8* code, int dreg, int tls_offset)
2151 {
2152         if (optimize_for_xen) {
2153                 x86_prefix (code, X86_FS_PREFIX);
2154                 amd64_mov_reg_mem (code, dreg, 0, 8);
2155                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2156         } else {
2157                 x86_prefix (code, X86_FS_PREFIX);
2158                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2159         }
2160         return code;
2161 }
2162
2163 /*
2164  * emit_load_volatile_arguments:
2165  *
2166  *  Load volatile arguments from the stack to the original input registers.
2167  * Required before a tail call.
2168  */
2169 static guint8*
2170 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2171 {
2172         MonoMethod *method = cfg->method;
2173         MonoMethodSignature *sig;
2174         MonoInst *inst;
2175         CallInfo *cinfo;
2176         guint32 i;
2177
2178         /* FIXME: Generate intermediate code instead */
2179
2180         sig = mono_method_signature (method);
2181
2182         cinfo = get_call_info (sig, FALSE);
2183
2184         /* This is the opposite of the code in emit_prolog */
2185
2186         if (sig->ret->type != MONO_TYPE_VOID) {
2187                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
2188                         amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->ret->inst_basereg, cfg->ret->inst_offset, 8);
2189                 }
2190         }
2191
2192         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2193                 ArgInfo *ainfo = cinfo->args + i;
2194                 MonoType *arg_type;
2195                 inst = cfg->varinfo [i];
2196
2197                 if (sig->hasthis && (i == 0))
2198                         arg_type = &mono_defaults.object_class->byval_arg;
2199                 else
2200                         arg_type = sig->params [i - sig->hasthis];
2201
2202                 if (inst->opcode != OP_REGVAR) {
2203                         switch (ainfo->storage) {
2204                         case ArgInIReg: {
2205                                 guint32 size = 8;
2206
2207                                 /* FIXME: I1 etc */
2208                                 amd64_mov_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset, size);
2209                                 break;
2210                         }
2211                         case ArgInFloatSSEReg:
2212                                 amd64_movss_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2213                                 break;
2214                         case ArgInDoubleSSEReg:
2215                                 amd64_movsd_reg_membase (code, ainfo->reg, inst->inst_basereg, inst->inst_offset);
2216                                 break;
2217                         default:
2218                                 break;
2219                         }
2220                 }
2221                 else {
2222                         g_assert (ainfo->storage == ArgInIReg);
2223
2224                         amd64_mov_reg_reg (code, ainfo->reg, inst->dreg, 8);
2225                 }
2226         }
2227
2228         g_free (cinfo);
2229
2230         return code;
2231 }
2232
2233 #define REAL_PRINT_REG(text,reg) \
2234 mono_assert (reg >= 0); \
2235 amd64_push_reg (code, AMD64_RAX); \
2236 amd64_push_reg (code, AMD64_RDX); \
2237 amd64_push_reg (code, AMD64_RCX); \
2238 amd64_push_reg (code, reg); \
2239 amd64_push_imm (code, reg); \
2240 amd64_push_imm (code, text " %d %p\n"); \
2241 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2242 amd64_call_reg (code, AMD64_RAX); \
2243 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2244 amd64_pop_reg (code, AMD64_RCX); \
2245 amd64_pop_reg (code, AMD64_RDX); \
2246 amd64_pop_reg (code, AMD64_RAX);
2247
2248 /* benchmark and set based on cpu */
2249 #define LOOP_ALIGNMENT 8
2250 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2251
2252 void
2253 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2254 {
2255         MonoInst *ins;
2256         MonoCallInst *call;
2257         guint offset;
2258         guint8 *code = cfg->native_code + cfg->code_len;
2259         MonoInst *last_ins = NULL;
2260         guint last_offset = 0;
2261         int max_len, cpos;
2262
2263         if (cfg->opt & MONO_OPT_PEEPHOLE)
2264                 peephole_pass (cfg, bb);
2265
2266         if (cfg->opt & MONO_OPT_LOOP) {
2267                 int pad, align = LOOP_ALIGNMENT;
2268                 /* set alignment depending on cpu */
2269                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2270                         pad = align - pad;
2271                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2272                         amd64_padding (code, pad);
2273                         cfg->code_len += pad;
2274                         bb->native_offset = cfg->code_len;
2275                 }
2276         }
2277
2278         if (cfg->verbose_level > 2)
2279                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
2280
2281         cpos = bb->max_offset;
2282
2283         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
2284                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
2285                 g_assert (!cfg->compile_aot);
2286                 cpos += 6;
2287
2288                 cov->data [bb->dfn].cil_code = bb->cil_code;
2289                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
2290                 /* this is not thread save, but good enough */
2291                 amd64_inc_membase (code, AMD64_R11, 0);
2292         }
2293
2294         offset = code - cfg->native_code;
2295
2296         mono_debug_open_block (cfg, bb, offset);
2297
2298         ins = bb->code;
2299         while (ins) {
2300                 offset = code - cfg->native_code;
2301
2302                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
2303
2304                 if (offset > (cfg->code_size - max_len - 16)) {
2305                         cfg->code_size *= 2;
2306                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
2307                         code = cfg->native_code + offset;
2308                         mono_jit_stats.code_reallocs++;
2309                 }
2310
2311                 mono_debug_record_line_number (cfg, ins, offset);
2312
2313                 switch (ins->opcode) {
2314                 case OP_BIGMUL:
2315                         amd64_mul_reg (code, ins->sreg2, TRUE);
2316                         break;
2317                 case OP_BIGMUL_UN:
2318                         amd64_mul_reg (code, ins->sreg2, FALSE);
2319                         break;
2320                 case OP_X86_SETEQ_MEMBASE:
2321                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
2322                         break;
2323                 case OP_STOREI1_MEMBASE_IMM:
2324                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
2325                         break;
2326                 case OP_STOREI2_MEMBASE_IMM:
2327                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
2328                         break;
2329                 case OP_STOREI4_MEMBASE_IMM:
2330                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
2331                         break;
2332                 case OP_STOREI1_MEMBASE_REG:
2333                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
2334                         break;
2335                 case OP_STOREI2_MEMBASE_REG:
2336                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
2337                         break;
2338                 case OP_STORE_MEMBASE_REG:
2339                 case OP_STOREI8_MEMBASE_REG:
2340                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
2341                         break;
2342                 case OP_STOREI4_MEMBASE_REG:
2343                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
2344                         break;
2345                 case OP_STORE_MEMBASE_IMM:
2346                 case OP_STOREI8_MEMBASE_IMM:
2347                         g_assert (amd64_is_imm32 (ins->inst_imm));
2348                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
2349                         break;
2350                 case CEE_LDIND_I:
2351                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, sizeof (gpointer));
2352                         break;
2353                 case CEE_LDIND_I4:
2354                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2355                         break;
2356                 case CEE_LDIND_U4:
2357                         amd64_mov_reg_mem (code, ins->dreg, (gssize)ins->inst_p0, 4);
2358                         break;
2359                 case OP_LOADU4_MEM:
2360                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
2361                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
2362                         break;
2363                 case OP_LOAD_MEMBASE:
2364                 case OP_LOADI8_MEMBASE:
2365                         g_assert (amd64_is_imm32 (ins->inst_offset));
2366                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
2367                         break;
2368                 case OP_LOADI4_MEMBASE:
2369                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
2370                         break;
2371                 case OP_LOADU4_MEMBASE:
2372                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
2373                         break;
2374                 case OP_LOADU1_MEMBASE:
2375                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
2376                         break;
2377                 case OP_LOADI1_MEMBASE:
2378                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
2379                         break;
2380                 case OP_LOADU2_MEMBASE:
2381                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
2382                         break;
2383                 case OP_LOADI2_MEMBASE:
2384                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
2385                         break;
2386                 case OP_AMD64_LOADI8_MEMINDEX:
2387                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
2388                         break;
2389                 case CEE_CONV_I1:
2390                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2391                         break;
2392                 case CEE_CONV_I2:
2393                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2394                         break;
2395                 case CEE_CONV_U1:
2396                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
2397                         break;
2398                 case CEE_CONV_U2:
2399                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
2400                         break;
2401                 case CEE_CONV_U8:
2402                 case CEE_CONV_U:
2403                         /* Clean out the upper word */
2404                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
2405                         break;
2406                 case CEE_CONV_I8:
2407                 case CEE_CONV_I:
2408                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2409                         break;
2410                 case OP_COMPARE:
2411                 case OP_LCOMPARE:
2412                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
2413                         break;
2414                 case OP_COMPARE_IMM:
2415                         g_assert (amd64_is_imm32 (ins->inst_imm));
2416                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
2417                         break;
2418                 case OP_X86_COMPARE_REG_MEMBASE:
2419                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
2420                         break;
2421                 case OP_X86_TEST_NULL:
2422                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
2423                         break;
2424                 case OP_AMD64_TEST_NULL:
2425                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
2426                         break;
2427                 case OP_X86_ADD_MEMBASE_IMM:
2428                         /* FIXME: Make a 64 version too */
2429                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2430                         break;
2431                 case OP_X86_ADD_MEMBASE:
2432                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2433                         break;
2434                 case OP_X86_SUB_MEMBASE_IMM:
2435                         g_assert (amd64_is_imm32 (ins->inst_imm));
2436                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2437                         break;
2438                 case OP_X86_SUB_MEMBASE:
2439                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2440                         break;
2441                 case OP_X86_INC_MEMBASE:
2442                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2443                         break;
2444                 case OP_X86_INC_REG:
2445                         amd64_inc_reg_size (code, ins->dreg, 4);
2446                         break;
2447                 case OP_X86_DEC_MEMBASE:
2448                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
2449                         break;
2450                 case OP_X86_DEC_REG:
2451                         amd64_dec_reg_size (code, ins->dreg, 4);
2452                         break;
2453                 case OP_X86_MUL_MEMBASE:
2454                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2455                         break;
2456                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
2457                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
2458                         break;
2459                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2460                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
2461                         break;
2462                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
2463                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
2464                         break;
2465                 case CEE_BREAK:
2466                         amd64_breakpoint (code);
2467                         break;
2468                 case OP_ADDCC:
2469                 case CEE_ADD:
2470                 case OP_LADD:
2471                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
2472                         break;
2473                 case OP_ADC:
2474                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
2475                         break;
2476                 case OP_ADD_IMM:
2477                         g_assert (amd64_is_imm32 (ins->inst_imm));
2478                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
2479                         break;
2480                 case OP_ADC_IMM:
2481                         g_assert (amd64_is_imm32 (ins->inst_imm));
2482                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
2483                         break;
2484                 case OP_SUBCC:
2485                 case CEE_SUB:
2486                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
2487                         break;
2488                 case OP_SBB:
2489                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
2490                         break;
2491                 case OP_SUB_IMM:
2492                         g_assert (amd64_is_imm32 (ins->inst_imm));
2493                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
2494                         break;
2495                 case OP_SBB_IMM:
2496                         g_assert (amd64_is_imm32 (ins->inst_imm));
2497                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
2498                         break;
2499                 case CEE_AND:
2500                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
2501                         break;
2502                 case OP_AND_IMM:
2503                         g_assert (amd64_is_imm32 (ins->inst_imm));
2504                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
2505                         break;
2506                 case CEE_MUL:
2507                 case OP_LMUL:
2508                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2509                         break;
2510                 case OP_MUL_IMM:
2511                 case OP_LMUL_IMM:
2512                 case OP_IMUL_IMM: {
2513                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
2514
2515                         switch (ins->inst_imm) {
2516                         case 2:
2517                                 /* MOV r1, r2 */
2518                                 /* ADD r1, r1 */
2519                                 if (ins->dreg != ins->sreg1)
2520                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
2521                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2522                                 break;
2523                         case 3:
2524                                 /* LEA r1, [r2 + r2*2] */
2525                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2526                                 break;
2527                         case 5:
2528                                 /* LEA r1, [r2 + r2*4] */
2529                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2530                                 break;
2531                         case 6:
2532                                 /* LEA r1, [r2 + r2*2] */
2533                                 /* ADD r1, r1          */
2534                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2535                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2536                                 break;
2537                         case 9:
2538                                 /* LEA r1, [r2 + r2*8] */
2539                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
2540                                 break;
2541                         case 10:
2542                                 /* LEA r1, [r2 + r2*4] */
2543                                 /* ADD r1, r1          */
2544                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2545                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
2546                                 break;
2547                         case 12:
2548                                 /* LEA r1, [r2 + r2*2] */
2549                                 /* SHL r1, 2           */
2550                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
2551                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2552                                 break;
2553                         case 25:
2554                                 /* LEA r1, [r2 + r2*4] */
2555                                 /* LEA r1, [r1 + r1*4] */
2556                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2557                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2558                                 break;
2559                         case 100:
2560                                 /* LEA r1, [r2 + r2*4] */
2561                                 /* SHL r1, 2           */
2562                                 /* LEA r1, [r1 + r1*4] */
2563                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
2564                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
2565                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
2566                                 break;
2567                         default:
2568                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
2569                                 break;
2570                         }
2571                         break;
2572                 }
2573                 case CEE_DIV:
2574                 case OP_LDIV:
2575                         amd64_cdq (code);
2576                         amd64_div_reg (code, ins->sreg2, TRUE);
2577                         break;
2578                 case CEE_DIV_UN:
2579                 case OP_LDIV_UN:
2580                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2581                         amd64_div_reg (code, ins->sreg2, FALSE);
2582                         break;
2583                 case CEE_REM:
2584                 case OP_LREM:
2585                         amd64_cdq (code);
2586                         amd64_div_reg (code, ins->sreg2, TRUE);
2587                         break;
2588                 case CEE_REM_UN:
2589                 case OP_LREM_UN:
2590                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2591                         amd64_div_reg (code, ins->sreg2, FALSE);
2592                         break;
2593                 case OP_LMUL_OVF:
2594                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
2595                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2596                         break;
2597                 case CEE_OR:
2598                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
2599                         break;
2600                 case OP_OR_IMM
2601 :                       g_assert (amd64_is_imm32 (ins->inst_imm));
2602                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
2603                         break;
2604                 case CEE_XOR:
2605                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
2606                         break;
2607                 case OP_XOR_IMM:
2608                         g_assert (amd64_is_imm32 (ins->inst_imm));
2609                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
2610                         break;
2611                 case CEE_SHL:
2612                 case OP_LSHL:
2613                         g_assert (ins->sreg2 == AMD64_RCX);
2614                         amd64_shift_reg (code, X86_SHL, ins->dreg);
2615                         break;
2616                 case CEE_SHR:
2617                 case OP_LSHR:
2618                         g_assert (ins->sreg2 == AMD64_RCX);
2619                         amd64_shift_reg (code, X86_SAR, ins->dreg);
2620                         break;
2621                 case OP_SHR_IMM:
2622                         g_assert (amd64_is_imm32 (ins->inst_imm));
2623                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2624                         break;
2625                 case OP_LSHR_IMM:
2626                         g_assert (amd64_is_imm32 (ins->inst_imm));
2627                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
2628                         break;
2629                 case OP_SHR_UN_IMM:
2630                         g_assert (amd64_is_imm32 (ins->inst_imm));
2631                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2632                         break;
2633                 case OP_LSHR_UN_IMM:
2634                         g_assert (amd64_is_imm32 (ins->inst_imm));
2635                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
2636                         break;
2637                 case CEE_SHR_UN:
2638                         g_assert (ins->sreg2 == AMD64_RCX);
2639                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2640                         break;
2641                 case OP_LSHR_UN:
2642                         g_assert (ins->sreg2 == AMD64_RCX);
2643                         amd64_shift_reg (code, X86_SHR, ins->dreg);
2644                         break;
2645                 case OP_SHL_IMM:
2646                         g_assert (amd64_is_imm32 (ins->inst_imm));
2647                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2648                         break;
2649                 case OP_LSHL_IMM:
2650                         g_assert (amd64_is_imm32 (ins->inst_imm));
2651                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
2652                         break;
2653
2654                 case OP_IADDCC:
2655                 case OP_IADD:
2656                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
2657                         break;
2658                 case OP_IADC:
2659                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
2660                         break;
2661                 case OP_IADD_IMM:
2662                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
2663                         break;
2664                 case OP_IADC_IMM:
2665                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
2666                         break;
2667                 case OP_ISUBCC:
2668                 case OP_ISUB:
2669                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
2670                         break;
2671                 case OP_ISBB:
2672                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
2673                         break;
2674                 case OP_ISUB_IMM:
2675                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
2676                         break;
2677                 case OP_ISBB_IMM:
2678                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
2679                         break;
2680                 case OP_IAND:
2681                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
2682                         break;
2683                 case OP_IAND_IMM:
2684                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
2685                         break;
2686                 case OP_IOR:
2687                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
2688                         break;
2689                 case OP_IOR_IMM:
2690                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
2691                         break;
2692                 case OP_IXOR:
2693                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
2694                         break;
2695                 case OP_IXOR_IMM:
2696                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
2697                         break;
2698                 case OP_INEG:
2699                         amd64_neg_reg_size (code, ins->sreg1, 4);
2700                         break;
2701                 case OP_INOT:
2702                         amd64_not_reg_size (code, ins->sreg1, 4);
2703                         break;
2704                 case OP_ISHL:
2705                         g_assert (ins->sreg2 == AMD64_RCX);
2706                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
2707                         break;
2708                 case OP_ISHR:
2709                         g_assert (ins->sreg2 == AMD64_RCX);
2710                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
2711                         break;
2712                 case OP_ISHR_IMM:
2713                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
2714                         break;
2715                 case OP_ISHR_UN_IMM:
2716                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
2717                         break;
2718                 case OP_ISHR_UN:
2719                         g_assert (ins->sreg2 == AMD64_RCX);
2720                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
2721                         break;
2722                 case OP_ISHL_IMM:
2723                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
2724                         break;
2725                 case OP_IMUL:
2726                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2727                         break;
2728                 case OP_IMUL_OVF:
2729                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
2730                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2731                         break;
2732                 case OP_IMUL_OVF_UN:
2733                 case OP_LMUL_OVF_UN: {
2734                         /* the mul operation and the exception check should most likely be split */
2735                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
2736                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
2737                         /*g_assert (ins->sreg2 == X86_EAX);
2738                         g_assert (ins->dreg == X86_EAX);*/
2739                         if (ins->sreg2 == X86_EAX) {
2740                                 non_eax_reg = ins->sreg1;
2741                         } else if (ins->sreg1 == X86_EAX) {
2742                                 non_eax_reg = ins->sreg2;
2743                         } else {
2744                                 /* no need to save since we're going to store to it anyway */
2745                                 if (ins->dreg != X86_EAX) {
2746                                         saved_eax = TRUE;
2747                                         amd64_push_reg (code, X86_EAX);
2748                                 }
2749                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
2750                                 non_eax_reg = ins->sreg2;
2751                         }
2752                         if (ins->dreg == X86_EDX) {
2753                                 if (!saved_eax) {
2754                                         saved_eax = TRUE;
2755                                         amd64_push_reg (code, X86_EAX);
2756                                 }
2757                         } else {
2758                                 saved_edx = TRUE;
2759                                 amd64_push_reg (code, X86_EDX);
2760                         }
2761                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
2762                         /* save before the check since pop and mov don't change the flags */
2763                         if (ins->dreg != X86_EAX)
2764                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
2765                         if (saved_edx)
2766                                 amd64_pop_reg (code, X86_EDX);
2767                         if (saved_eax)
2768                                 amd64_pop_reg (code, X86_EAX);
2769                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
2770                         break;
2771                 }
2772                 case OP_IDIV:
2773                         amd64_cdq_size (code, 4);
2774                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2775                         break;
2776                 case OP_IDIV_UN:
2777                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2778                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2779                         break;
2780                 case OP_IREM:
2781                         amd64_cdq_size (code, 4);
2782                         amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
2783                         break;
2784                 case OP_IREM_UN:
2785                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
2786                         amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
2787                         break;
2788                 case OP_ICOMPARE:
2789                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
2790                         break;
2791                 case OP_ICOMPARE_IMM:
2792                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
2793                         break;
2794                 case OP_IBEQ:
2795                 case OP_IBLT:
2796                 case OP_IBGT:
2797                 case OP_IBGE:
2798                 case OP_IBLE:
2799                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), TRUE);
2800                         break;
2801                 case OP_IBNE_UN:
2802                 case OP_IBLT_UN:
2803                 case OP_IBGT_UN:
2804                 case OP_IBGE_UN:
2805                 case OP_IBLE_UN:
2806                         EMIT_COND_BRANCH (ins, opcode_to_x86_cond (ins->opcode), FALSE);
2807                         break;
2808                 case OP_COND_EXC_IOV:
2809                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2810                                                                                 TRUE, ins->inst_p1);
2811                         break;
2812                 case OP_COND_EXC_IC:
2813                         EMIT_COND_SYSTEM_EXCEPTION (opcode_to_x86_cond (ins->opcode),
2814                                                                                 FALSE, ins->inst_p1);
2815                         break;
2816                 case CEE_NOT:
2817                         amd64_not_reg (code, ins->sreg1);
2818                         break;
2819                 case CEE_NEG:
2820                         amd64_neg_reg (code, ins->sreg1);
2821                         break;
2822                 case OP_SEXT_I1:
2823                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
2824                         break;
2825                 case OP_SEXT_I2:
2826                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
2827                         break;
2828                 case OP_SEXT_I4:
2829                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
2830                         break;
2831                 case OP_ICONST:
2832                 case OP_I8CONST:
2833                         if ((((guint64)ins->inst_c0) >> 32) == 0)
2834                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
2835                         else
2836                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
2837                         break;
2838                 case OP_AOTCONST:
2839                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
2840                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
2841                         break;
2842                 case CEE_CONV_I4:
2843                 case CEE_CONV_U4:
2844                 case OP_MOVE:
2845                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
2846                         break;
2847                 case OP_AMD64_SET_XMMREG_R4: {
2848                         if (use_sse2) {
2849                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
2850                         }
2851                         else {
2852                                 amd64_fst_membase (code, AMD64_RSP, -8, FALSE, TRUE);
2853                                 /* ins->dreg is set to -1 by the reg allocator */
2854                                 amd64_movss_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
2855                         }
2856                         break;
2857                 }
2858                 case OP_AMD64_SET_XMMREG_R8: {
2859                         if (use_sse2) {
2860                                 if (ins->dreg != ins->sreg1)
2861                                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
2862                         }
2863                         else {
2864                                 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE);
2865                                 /* ins->dreg is set to -1 by the reg allocator */
2866                                 amd64_movsd_reg_membase (code, ins->backend.reg3, AMD64_RSP, -8);
2867                         }
2868                         break;
2869                 }
2870                 case CEE_JMP: {
2871                         /*
2872                          * Note: this 'frame destruction' logic is useful for tail calls, too.
2873                          * Keep in sync with the code in emit_epilog.
2874                          */
2875                         int pos = 0, i;
2876
2877                         /* FIXME: no tracing support... */
2878                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
2879                                 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
2880
2881                         g_assert (!cfg->method->save_lmf);
2882
2883                         code = emit_load_volatile_arguments (cfg, code);
2884
2885                         if (cfg->arch.omit_fp) {
2886                                 guint32 save_offset = 0;
2887                                 /* Pop callee-saved registers */
2888                                 for (i = 0; i < AMD64_NREG; ++i)
2889                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2890                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
2891                                                 save_offset += 8;
2892                                         }
2893                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
2894                         }
2895                         else {
2896                                 for (i = 0; i < AMD64_NREG; ++i)
2897                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
2898                                                 pos -= sizeof (gpointer);
2899
2900                                 if (pos)
2901                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
2902
2903                                 /* Pop registers in reverse order */
2904                                 for (i = AMD64_NREG - 1; i > 0; --i)
2905                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
2906                                                 amd64_pop_reg (code, i);
2907                                         }
2908
2909                                 amd64_leave (code);
2910                         }
2911
2912                         offset = code - cfg->native_code;
2913                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
2914                         if (cfg->compile_aot)
2915                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
2916                         else
2917                                 amd64_set_reg_template (code, AMD64_R11);
2918                         amd64_jump_reg (code, AMD64_R11);
2919                         break;
2920                 }
2921                 case OP_CHECK_THIS:
2922                         /* ensure ins->sreg1 is not NULL */
2923                         amd64_alu_membase_imm (code, X86_CMP, ins->sreg1, 0, 0);
2924                         break;
2925                 case OP_ARGLIST: {
2926                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
2927                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
2928                         break;
2929                 }
2930                 case OP_FCALL:
2931                 case OP_LCALL:
2932                 case OP_VCALL:
2933                 case OP_VOIDCALL:
2934                 case CEE_CALL:
2935                         call = (MonoCallInst*)ins;
2936                         /*
2937                          * The AMD64 ABI forces callers to know about varargs.
2938                          */
2939                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
2940                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2941                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
2942                                 /*
2943                                  * Since the unmanaged calling convention doesn't contain a
2944                                  * 'vararg' entry, we have to treat every pinvoke call as a
2945                                  * potential vararg call.
2946                                  */
2947                                 guint32 nregs, i;
2948                                 nregs = 0;
2949                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
2950                                         if (call->used_fregs & (1 << i))
2951                                                 nregs ++;
2952                                 if (!nregs)
2953                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2954                                 else
2955                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
2956                         }
2957
2958                         if (ins->flags & MONO_INST_HAS_METHOD)
2959                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method);
2960                         else
2961                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr);
2962                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2963                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2964                         code = emit_move_return_value (cfg, ins, code);
2965                         break;
2966                 case OP_FCALL_REG:
2967                 case OP_LCALL_REG:
2968                 case OP_VCALL_REG:
2969                 case OP_VOIDCALL_REG:
2970                 case OP_CALL_REG:
2971                         call = (MonoCallInst*)ins;
2972
2973                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
2974                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
2975                                 ins->sreg1 = AMD64_R11;
2976                         }
2977
2978                         /*
2979                          * The AMD64 ABI forces callers to know about varargs.
2980                          */
2981                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
2982                                 if (ins->sreg1 == AMD64_RAX) {
2983                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
2984                                         ins->sreg1 = AMD64_R11;
2985                                 }
2986                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2987                         }
2988                         amd64_call_reg (code, ins->sreg1);
2989                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
2990                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
2991                         code = emit_move_return_value (cfg, ins, code);
2992                         break;
2993                 case OP_FCALL_MEMBASE:
2994                 case OP_LCALL_MEMBASE:
2995                 case OP_VCALL_MEMBASE:
2996                 case OP_VOIDCALL_MEMBASE:
2997                 case OP_CALL_MEMBASE:
2998                         call = (MonoCallInst*)ins;
2999
3000                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3001                                 /*
3002                                  * Can't use R11 because it is clobbered by the trampoline
3003                                  * code, and the reg value is needed by get_vcall_slot_addr.
3004                                  */
3005                                 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3006                                 ins->sreg1 = AMD64_RAX;
3007                         }
3008
3009                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3010                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3011                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3012                         code = emit_move_return_value (cfg, ins, code);
3013                         break;
3014                 case OP_OUTARG:
3015                 case OP_X86_PUSH:
3016                         amd64_push_reg (code, ins->sreg1);
3017                         break;
3018                 case OP_X86_PUSH_IMM:
3019                         g_assert (amd64_is_imm32 (ins->inst_imm));
3020                         amd64_push_imm (code, ins->inst_imm);
3021                         break;
3022                 case OP_X86_PUSH_MEMBASE:
3023                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3024                         break;
3025                 case OP_X86_PUSH_OBJ:
3026                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ins->inst_imm);
3027                         amd64_push_reg (code, AMD64_RDI);
3028                         amd64_push_reg (code, AMD64_RSI);
3029                         amd64_push_reg (code, AMD64_RCX);
3030                         if (ins->inst_offset)
3031                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3032                         else
3033                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3034                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, 3 * 8);
3035                         amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3036                         amd64_cld (code);
3037                         amd64_prefix (code, X86_REP_PREFIX);
3038                         amd64_movsd (code);
3039                         amd64_pop_reg (code, AMD64_RCX);
3040                         amd64_pop_reg (code, AMD64_RSI);
3041                         amd64_pop_reg (code, AMD64_RDI);
3042                         break;
3043                 case OP_X86_LEA:
3044                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3045                         break;
3046                 case OP_X86_LEA_MEMBASE:
3047                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3048                         break;
3049                 case OP_X86_XCHG:
3050                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3051                         break;
3052                 case OP_LOCALLOC:
3053                         /* keep alignment */
3054                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3055                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3056                         code = mono_emit_stack_alloc (code, ins);
3057                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3058                         break;
3059                 case CEE_RET:
3060                         amd64_ret (code);
3061                         break;
3062                 case CEE_THROW: {
3063                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3064                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3065                                              (gpointer)"mono_arch_throw_exception");
3066                         break;
3067                 }
3068                 case OP_RETHROW: {
3069                         amd64_mov_reg_reg (code, AMD64_RDI, ins->sreg1, 8);
3070                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
3071                                              (gpointer)"mono_arch_rethrow_exception");
3072                         break;
3073                 }
3074                 case OP_CALL_HANDLER:
3075                         /* Align stack */
3076                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
3077                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3078                         amd64_call_imm (code, 0);
3079                         /* Restore stack alignment */
3080                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3081                         break;
3082                 case OP_LABEL:
3083                         ins->inst_c0 = code - cfg->native_code;
3084                         break;
3085                 case CEE_BR:
3086                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
3087                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
3088                         //break;
3089                         if (ins->flags & MONO_INST_BRLABEL) {
3090                                 if (ins->inst_i0->inst_c0) {
3091                                         amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
3092                                 } else {
3093                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
3094                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3095                                             x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
3096                                                 x86_jump8 (code, 0);
3097                                         else
3098                                                 x86_jump32 (code, 0);
3099                                 }
3100                         } else {
3101                                 if (ins->inst_target_bb->native_offset) {
3102                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
3103                                 } else {
3104                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
3105                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
3106                                             x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
3107                                                 x86_jump8 (code, 0);
3108                                         else
3109                                                 x86_jump32 (code, 0);
3110                                 }
3111                         }
3112                         break;
3113                 case OP_BR_REG:
3114                         amd64_jump_reg (code, ins->sreg1);
3115                         break;
3116                 case OP_CEQ:
3117                 case OP_ICEQ:
3118                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3119                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3120                         break;
3121                 case OP_CLT:
3122                 case OP_ICLT:
3123                         amd64_set_reg (code, X86_CC_LT, ins->dreg, TRUE);
3124                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3125                         break;
3126                 case OP_CLT_UN:
3127                 case OP_ICLT_UN:
3128                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3129                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3130                         break;
3131                 case OP_CGT:
3132                 case OP_ICGT:
3133                         amd64_set_reg (code, X86_CC_GT, ins->dreg, TRUE);
3134                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3135                         break;
3136                 case OP_CGT_UN:
3137                 case OP_ICGT_UN:
3138                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3139                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3140                         break;
3141                 case OP_COND_EXC_EQ:
3142                 case OP_COND_EXC_NE_UN:
3143                 case OP_COND_EXC_LT:
3144                 case OP_COND_EXC_LT_UN:
3145                 case OP_COND_EXC_GT:
3146                 case OP_COND_EXC_GT_UN:
3147                 case OP_COND_EXC_GE:
3148                 case OP_COND_EXC_GE_UN:
3149                 case OP_COND_EXC_LE:
3150                 case OP_COND_EXC_LE_UN:
3151                 case OP_COND_EXC_OV:
3152                 case OP_COND_EXC_NO:
3153                 case OP_COND_EXC_C:
3154                 case OP_COND_EXC_NC:
3155                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
3156                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
3157                         break;
3158                 case CEE_BEQ:
3159                 case CEE_BNE_UN:
3160                 case CEE_BLT:
3161                 case CEE_BLT_UN:
3162                 case CEE_BGT:
3163                 case CEE_BGT_UN:
3164                 case CEE_BGE:
3165                 case CEE_BGE_UN:
3166                 case CEE_BLE:
3167                 case CEE_BLE_UN:
3168                         EMIT_COND_BRANCH (ins, branch_cc_table [ins->opcode - CEE_BEQ], (ins->opcode < CEE_BNE_UN));
3169                         break;
3170
3171                 /* floating point opcodes */
3172                 case OP_R8CONST: {
3173                         double d = *(double *)ins->inst_p0;
3174
3175                         if (use_sse2) {
3176                                 if ((d == 0.0) && (mono_signbit (d) == 0)) {
3177                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3178                                 }
3179                                 else {
3180                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3181                                         amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3182                                 }
3183                         }
3184                         else if ((d == 0.0) && (mono_signbit (d) == 0)) {
3185                                 amd64_fldz (code);
3186                         } else if (d == 1.0) {
3187                                 x86_fld1 (code);
3188                         } else {
3189                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
3190                                 amd64_fld_membase (code, AMD64_RIP, 0, TRUE);
3191                         }
3192                         break;
3193                 }
3194                 case OP_R4CONST: {
3195                         float f = *(float *)ins->inst_p0;
3196
3197                         if (use_sse2) {
3198                                 if ((f == 0.0) && (mono_signbit (f) == 0)) {
3199                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
3200                                 }
3201                                 else {
3202                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3203                                         amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3204                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3205                                 }
3206                         }
3207                         else if ((f == 0.0) && (mono_signbit (f) == 0)) {
3208                                 amd64_fldz (code);
3209                         } else if (f == 1.0) {
3210                                 x86_fld1 (code);
3211                         } else {
3212                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
3213                                 amd64_fld_membase (code, AMD64_RIP, 0, FALSE);
3214                         }
3215                         break;
3216                 }
3217                 case OP_STORER8_MEMBASE_REG:
3218                         if (use_sse2)
3219                                 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
3220                         else
3221                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, TRUE, TRUE);
3222                         break;
3223                 case OP_LOADR8_SPILL_MEMBASE:
3224                         if (use_sse2)
3225                                 g_assert_not_reached ();
3226                         amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3227                         amd64_fxch (code, 1);
3228                         break;
3229                 case OP_LOADR8_MEMBASE:
3230                         if (use_sse2)
3231                                 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3232                         else
3233                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3234                         break;
3235                 case OP_STORER4_MEMBASE_REG:
3236                         if (use_sse2) {
3237                                 /* This requires a double->single conversion */
3238                                 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
3239                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
3240                         }
3241                         else
3242                                 amd64_fst_membase (code, ins->inst_destbasereg, ins->inst_offset, FALSE, TRUE);
3243                         break;
3244                 case OP_LOADR4_MEMBASE:
3245                         if (use_sse2) {
3246                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3247                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
3248                         }
3249                         else
3250                                 amd64_fld_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3251                         break;
3252                 case CEE_CONV_R4: /* FIXME: change precision */
3253                 case CEE_CONV_R8:
3254                         if (use_sse2)
3255                                 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3256                         else {
3257                                 amd64_push_reg (code, ins->sreg1);
3258                                 amd64_fild_membase (code, AMD64_RSP, 0, FALSE);
3259                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3260                         }
3261                         break;
3262                 case CEE_CONV_R_UN:
3263                         /* Emulated */
3264                         g_assert_not_reached ();
3265                         break;
3266                 case OP_LCONV_TO_R4: /* FIXME: change precision */
3267                 case OP_LCONV_TO_R8:
3268                         if (use_sse2)
3269                                 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
3270                         else {
3271                                 amd64_push_reg (code, ins->sreg1);
3272                                 amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3273                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
3274                         }
3275                         break;
3276                 case OP_X86_FP_LOAD_I8:
3277                         if (use_sse2)
3278                                 g_assert_not_reached ();
3279                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, TRUE);
3280                         break;
3281                 case OP_X86_FP_LOAD_I4:
3282                         if (use_sse2)
3283                                 g_assert_not_reached ();
3284                         amd64_fild_membase (code, ins->inst_basereg, ins->inst_offset, FALSE);
3285                         break;
3286                 case OP_FCONV_TO_I1:
3287                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
3288                         break;
3289                 case OP_FCONV_TO_U1:
3290                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
3291                         break;
3292                 case OP_FCONV_TO_I2:
3293                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
3294                         break;
3295                 case OP_FCONV_TO_U2:
3296                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
3297                         break;
3298                 case OP_FCONV_TO_I4:
3299                 case OP_FCONV_TO_I:
3300                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
3301                         break;
3302                 case OP_FCONV_TO_I8:
3303                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
3304                         break;
3305                 case OP_LCONV_TO_R_UN: {
3306                         static guint8 mn[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x40 };
3307                         guint8 *br;
3308
3309                         if (use_sse2)
3310                                 g_assert_not_reached ();
3311
3312                         /* load 64bit integer to FP stack */
3313                         amd64_push_imm (code, 0);
3314                         amd64_push_reg (code, ins->sreg2);
3315                         amd64_push_reg (code, ins->sreg1);
3316                         amd64_fild_membase (code, AMD64_RSP, 0, TRUE);
3317                         /* store as 80bit FP value */
3318                         x86_fst80_membase (code, AMD64_RSP, 0);
3319
3320                         /* test if lreg is negative */
3321                         amd64_test_reg_reg (code, ins->sreg2, ins->sreg2);
3322                         br = code; x86_branch8 (code, X86_CC_GEZ, 0, TRUE);
3323
3324                         /* add correction constant mn */
3325                         x86_fld80_mem (code, mn);
3326                         x86_fld80_membase (code, AMD64_RSP, 0);
3327                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3328                         x86_fst80_membase (code, AMD64_RSP, 0);
3329
3330                         amd64_patch (br, code);
3331
3332                         x86_fld80_membase (code, AMD64_RSP, 0);
3333                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 12);
3334
3335                         break;
3336                 }
3337                 case CEE_CONV_OVF_U4:
3338                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
3339                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
3340                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3341                         break;
3342                 case CEE_CONV_OVF_I4_UN:
3343                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
3344                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
3345                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
3346                         break;
3347                 case OP_FMOVE:
3348                         if (use_sse2 && (ins->dreg != ins->sreg1))
3349                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3350                         break;
3351                 case OP_FADD:
3352                         if (use_sse2)
3353                                 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
3354                         else
3355                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3356                         break;
3357                 case OP_FSUB:
3358                         if (use_sse2)
3359                                 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
3360                         else
3361                                 amd64_fp_op_reg (code, X86_FSUB, 1, TRUE);
3362                         break;
3363                 case OP_FMUL:
3364                         if (use_sse2)
3365                                 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
3366                         else
3367                                 amd64_fp_op_reg (code, X86_FMUL, 1, TRUE);
3368                         break;
3369                 case OP_FDIV:
3370                         if (use_sse2)
3371                                 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
3372                         else
3373                                 amd64_fp_op_reg (code, X86_FDIV, 1, TRUE);
3374                         break;
3375                 case OP_FNEG:
3376                         if (use_sse2) {
3377                                 static double r8_0 = -0.0;
3378
3379                                 g_assert (ins->sreg1 == ins->dreg);
3380
3381                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
3382                                 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
3383                         }
3384                         else
3385                                 amd64_fchs (code);
3386                         break;
3387                 case OP_SIN:
3388                         if (use_sse2) {
3389                                 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
3390                         }
3391                         else {
3392                                 amd64_fsin (code);
3393                                 amd64_fldz (code);
3394                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3395                         }
3396                         break;
3397                 case OP_COS:
3398                         if (use_sse2) {
3399                                 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
3400                         }
3401                         else {
3402                                 amd64_fcos (code);
3403                                 amd64_fldz (code);
3404                                 amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3405                         }
3406                         break;
3407                 case OP_ABS:
3408                         if (use_sse2) {
3409                                 EMIT_SSE2_FPFUNC (code, fabs, ins->dreg, ins->sreg1);
3410                         }
3411                         else
3412                                 amd64_fabs (code);
3413                         break;
3414                 case OP_TAN: {
3415                         /*
3416                          * it really doesn't make sense to inline all this code,
3417                          * it's here just to show that things may not be as simple
3418                          * as they appear.
3419                          */
3420                         guchar *check_pos, *end_tan, *pop_jump;
3421                         if (use_sse2)
3422                                 g_assert_not_reached ();
3423                         amd64_push_reg (code, AMD64_RAX);
3424                         amd64_fptan (code);
3425                         amd64_fnstsw (code);
3426                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3427                         check_pos = code;
3428                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3429                         amd64_fstp (code, 0); /* pop the 1.0 */
3430                         end_tan = code;
3431                         x86_jump8 (code, 0);
3432                         amd64_fldpi (code);
3433                         amd64_fp_op (code, X86_FADD, 0);
3434                         amd64_fxch (code, 1);
3435                         x86_fprem1 (code);
3436                         amd64_fstsw (code);
3437                         amd64_test_reg_imm (code, AMD64_RAX, X86_FP_C2);
3438                         pop_jump = code;
3439                         x86_branch8 (code, X86_CC_NE, 0, FALSE);
3440                         amd64_fstp (code, 1);
3441                         amd64_fptan (code);
3442                         amd64_patch (pop_jump, code);
3443                         amd64_fstp (code, 0); /* pop the 1.0 */
3444                         amd64_patch (check_pos, code);
3445                         amd64_patch (end_tan, code);
3446                         amd64_fldz (code);
3447                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3448                         amd64_pop_reg (code, AMD64_RAX);
3449                         break;
3450                 }
3451                 case OP_ATAN:
3452                         if (use_sse2)
3453                                 g_assert_not_reached ();
3454                         x86_fld1 (code);
3455                         amd64_fpatan (code);
3456                         amd64_fldz (code);
3457                         amd64_fp_op_reg (code, X86_FADD, 1, TRUE);
3458                         break;
3459                 case OP_SQRT:
3460                         if (use_sse2) {
3461                                 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
3462                         }
3463                         else
3464                                 amd64_fsqrt (code);
3465                         break;
3466                 case OP_X86_FPOP:
3467                         if (!use_sse2)
3468                                 amd64_fstp (code, 0);
3469                         break;
3470                 case OP_FREM: {
3471                         guint8 *l1, *l2;
3472
3473                         if (use_sse2)
3474                                 g_assert_not_reached ();
3475                         amd64_push_reg (code, AMD64_RAX);
3476                         /* we need to exchange ST(0) with ST(1) */
3477                         amd64_fxch (code, 1);
3478
3479                         /* this requires a loop, because fprem somtimes
3480                          * returns a partial remainder */
3481                         l1 = code;
3482                         /* looks like MS is using fprem instead of the IEEE compatible fprem1 */
3483                         /* x86_fprem1 (code); */
3484                         amd64_fprem (code);
3485                         amd64_fnstsw (code);
3486                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_C2);
3487                         l2 = code + 2;
3488                         x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
3489
3490                         /* pop result */
3491                         amd64_fstp (code, 1);
3492
3493                         amd64_pop_reg (code, AMD64_RAX);
3494                         break;
3495                 }
3496                 case OP_FCOMPARE:
3497                         if (use_sse2) {
3498                                 /*
3499                                  * The two arguments are swapped because the fbranch instructions
3500                                  * depend on this for the non-sse case to work.
3501                                  */
3502                                 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3503                                 break;
3504                         }
3505                         if (cfg->opt & MONO_OPT_FCMOV) {
3506                                 amd64_fcomip (code, 1);
3507                                 amd64_fstp (code, 0);
3508                                 break;
3509                         }
3510                         /* this overwrites EAX */
3511                         EMIT_FPCOMPARE(code);
3512                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3513                         break;
3514                 case OP_FCEQ:
3515                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3516                                 /* zeroing the register at the start results in
3517                                  * shorter and faster code (we can also remove the widening op)
3518                                  */
3519                                 guchar *unordered_check;
3520                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3521
3522                                 if (use_sse2)
3523                                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
3524                                 else {
3525                                         amd64_fcomip (code, 1);
3526                                         amd64_fstp (code, 0);
3527                                 }
3528                                 unordered_check = code;
3529                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3530                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
3531                                 amd64_patch (unordered_check, code);
3532                                 break;
3533                         }
3534                         if (ins->dreg != AMD64_RAX)
3535                                 amd64_push_reg (code, AMD64_RAX);
3536
3537                         EMIT_FPCOMPARE(code);
3538                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3539                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3540                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3541                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3542
3543                         if (ins->dreg != AMD64_RAX)
3544                                 amd64_pop_reg (code, AMD64_RAX);
3545                         break;
3546                 case OP_FCLT:
3547                 case OP_FCLT_UN:
3548                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3549                                 /* zeroing the register at the start results in
3550                                  * shorter and faster code (we can also remove the widening op)
3551                                  */
3552                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3553                                 if (use_sse2)
3554                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3555                                 else {
3556                                         amd64_fcomip (code, 1);
3557                                         amd64_fstp (code, 0);
3558                                 }
3559                                 if (ins->opcode == OP_FCLT_UN) {
3560                                         guchar *unordered_check = code;
3561                                         guchar *jump_to_end;
3562                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3563                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3564                                         jump_to_end = code;
3565                                         x86_jump8 (code, 0);
3566                                         amd64_patch (unordered_check, code);
3567                                         amd64_inc_reg (code, ins->dreg);
3568                                         amd64_patch (jump_to_end, code);
3569                                 } else {
3570                                         amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
3571                                 }
3572                                 break;
3573                         }
3574                         if (ins->dreg != AMD64_RAX)
3575                                 amd64_push_reg (code, AMD64_RAX);
3576
3577                         EMIT_FPCOMPARE(code);
3578                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3579                         if (ins->opcode == OP_FCLT_UN) {
3580                                 guchar *is_not_zero_check, *end_jump;
3581                                 is_not_zero_check = code;
3582                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3583                                 end_jump = code;
3584                                 x86_jump8 (code, 0);
3585                                 amd64_patch (is_not_zero_check, code);
3586                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3587
3588                                 amd64_patch (end_jump, code);
3589                         }
3590                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3591                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3592
3593                         if (ins->dreg != AMD64_RAX)
3594                                 amd64_pop_reg (code, AMD64_RAX);
3595                         break;
3596                 case OP_FCGT:
3597                 case OP_FCGT_UN:
3598                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3599                                 /* zeroing the register at the start results in
3600                                  * shorter and faster code (we can also remove the widening op)
3601                                  */
3602                                 guchar *unordered_check;
3603                                 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3604                                 if (use_sse2)
3605                                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
3606                                 else {
3607                                         amd64_fcomip (code, 1);
3608                                         amd64_fstp (code, 0);
3609                                 }
3610                                 if (ins->opcode == OP_FCGT) {
3611                                         unordered_check = code;
3612                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3613                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3614                                         amd64_patch (unordered_check, code);
3615                                 } else {
3616                                         amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
3617                                 }
3618                                 break;
3619                         }
3620                         if (ins->dreg != AMD64_RAX)
3621                                 amd64_push_reg (code, AMD64_RAX);
3622
3623                         EMIT_FPCOMPARE(code);
3624                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, X86_FP_CC_MASK);
3625                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3626                         if (ins->opcode == OP_FCGT_UN) {
3627                                 guchar *is_not_zero_check, *end_jump;
3628                                 is_not_zero_check = code;
3629                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3630                                 end_jump = code;
3631                                 x86_jump8 (code, 0);
3632                                 amd64_patch (is_not_zero_check, code);
3633                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3634
3635                                 amd64_patch (end_jump, code);
3636                         }
3637                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
3638                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
3639
3640                         if (ins->dreg != AMD64_RAX)
3641                                 amd64_pop_reg (code, AMD64_RAX);
3642                         break;
3643                 case OP_FCLT_MEMBASE:
3644                 case OP_FCGT_MEMBASE:
3645                 case OP_FCLT_UN_MEMBASE:
3646                 case OP_FCGT_UN_MEMBASE:
3647                 case OP_FCEQ_MEMBASE: {
3648                         guchar *unordered_check, *jump_to_end;
3649                         int x86_cond;
3650                         g_assert (use_sse2);
3651
3652                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
3653                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
3654
3655                         switch (ins->opcode) {
3656                         case OP_FCEQ_MEMBASE:
3657                                 x86_cond = X86_CC_EQ;
3658                                 break;
3659                         case OP_FCLT_MEMBASE:
3660                         case OP_FCLT_UN_MEMBASE:
3661                                 x86_cond = X86_CC_LT;
3662                                 break;
3663                         case OP_FCGT_MEMBASE:
3664                         case OP_FCGT_UN_MEMBASE:
3665                                 x86_cond = X86_CC_GT;
3666                                 break;
3667                         default:
3668                                 g_assert_not_reached ();
3669                         }
3670
3671                         unordered_check = code;
3672                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3673                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
3674
3675                         switch (ins->opcode) {
3676                         case OP_FCEQ_MEMBASE:
3677                         case OP_FCLT_MEMBASE:
3678                         case OP_FCGT_MEMBASE:
3679                                 amd64_patch (unordered_check, code);
3680                                 break;
3681                         case OP_FCLT_UN_MEMBASE:
3682                         case OP_FCGT_UN_MEMBASE:
3683                                 jump_to_end = code;
3684                                 x86_jump8 (code, 0);
3685                                 amd64_patch (unordered_check, code);
3686                                 amd64_inc_reg (code, ins->dreg);
3687                                 amd64_patch (jump_to_end, code);
3688                                 break;
3689                         default:
3690                                 break;
3691                         }
3692                         break;
3693                 }
3694                 case OP_FBEQ:
3695                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3696                                 guchar *jump = code;
3697                                 x86_branch8 (code, X86_CC_P, 0, TRUE);
3698                                 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3699                                 amd64_patch (jump, code);
3700                                 break;
3701                         }
3702                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0x4000);
3703                         EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
3704                         break;
3705                 case OP_FBNE_UN:
3706                         /* Branch if C013 != 100 */
3707                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3708                                 /* branch if !ZF or (PF|CF) */
3709                                 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3710                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3711                                 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
3712                                 break;
3713                         }
3714                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3715                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3716                         break;
3717                 case OP_FBLT:
3718                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3719                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3720                                 break;
3721                         }
3722                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3723                         break;
3724                 case OP_FBLT_UN:
3725                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3726                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3727                                 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
3728                                 break;
3729                         }
3730                         if (ins->opcode == OP_FBLT_UN) {
3731                                 guchar *is_not_zero_check, *end_jump;
3732                                 is_not_zero_check = code;
3733                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3734                                 end_jump = code;
3735                                 x86_jump8 (code, 0);
3736                                 amd64_patch (is_not_zero_check, code);
3737                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3738
3739                                 amd64_patch (end_jump, code);
3740                         }
3741                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3742                         break;
3743                 case OP_FBGT:
3744                 case OP_FBGT_UN:
3745                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3746                                 if (ins->opcode == OP_FBGT) {
3747                                         guchar *br1;
3748
3749                                         /* skip branch if C1=1 */
3750                                         br1 = code;
3751                                         x86_branch8 (code, X86_CC_P, 0, FALSE);
3752                                         /* branch if (C0 | C3) = 1 */
3753                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3754                                         amd64_patch (br1, code);
3755                                         break;
3756                                 } else {
3757                                         EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
3758                                 }
3759                                 break;
3760                         }
3761                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3762                         if (ins->opcode == OP_FBGT_UN) {
3763                                 guchar *is_not_zero_check, *end_jump;
3764                                 is_not_zero_check = code;
3765                                 x86_branch8 (code, X86_CC_NZ, 0, TRUE);
3766                                 end_jump = code;
3767                                 x86_jump8 (code, 0);
3768                                 amd64_patch (is_not_zero_check, code);
3769                                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_CC_MASK);
3770
3771                                 amd64_patch (end_jump, code);
3772                         }
3773                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3774                         break;
3775                 case OP_FBGE:
3776                         /* Branch if C013 == 100 or 001 */
3777                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3778                                 guchar *br1;
3779
3780                                 /* skip branch if C1=1 */
3781                                 br1 = code;
3782                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3783                                 /* branch if (C0 | C3) = 1 */
3784                                 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
3785                                 amd64_patch (br1, code);
3786                                 break;
3787                         }
3788                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3789                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3790                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C3);
3791                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3792                         break;
3793                 case OP_FBGE_UN:
3794                         /* Branch if C013 == 000 */
3795                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3796                                 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
3797                                 break;
3798                         }
3799                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3800                         break;
3801                 case OP_FBLE:
3802                         /* Branch if C013=000 or 100 */
3803                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3804                                 guchar *br1;
3805
3806                                 /* skip branch if C1=1 */
3807                                 br1 = code;
3808                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
3809                                 /* branch if C0=0 */
3810                                 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
3811                                 amd64_patch (br1, code);
3812                                 break;
3813                         }
3814                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, (X86_FP_C0|X86_FP_C1));
3815                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
3816                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
3817                         break;
3818                 case OP_FBLE_UN:
3819                         /* Branch if C013 != 001 */
3820                         if (use_sse2 || (cfg->opt & MONO_OPT_FCMOV)) {
3821                                 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
3822                                 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
3823                                 break;
3824                         }
3825                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3826                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
3827                         break;
3828                 case CEE_CKFINITE: {
3829                         if (use_sse2) {
3830                                 /* Transfer value to the fp stack */
3831                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
3832                                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
3833                                 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
3834                         }
3835                         amd64_push_reg (code, AMD64_RAX);
3836                         amd64_fxam (code);
3837                         amd64_fnstsw (code);
3838                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
3839                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
3840                         amd64_pop_reg (code, AMD64_RAX);
3841                         if (use_sse2) {
3842                                 amd64_fstp (code, 0);
3843                         }
3844                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
3845                         if (use_sse2)
3846                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
3847                         break;
3848                 }
3849                 case OP_TLS_GET: {
3850                         code = emit_tls_get (code, ins->dreg, ins->inst_offset);
3851                         break;
3852                 }
3853                 case OP_MEMORY_BARRIER: {
3854                         /* Not needed on amd64 */
3855                         break;
3856                 }
3857                 case OP_ATOMIC_ADD_I4:
3858                 case OP_ATOMIC_ADD_I8: {
3859                         int dreg = ins->dreg;
3860                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
3861
3862                         if (dreg == ins->inst_basereg)
3863                                 dreg = AMD64_R11;
3864
3865                         if (dreg != ins->sreg2)
3866                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
3867
3868                         x86_prefix (code, X86_LOCK_PREFIX);
3869                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3870
3871                         if (dreg != ins->dreg)
3872                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3873
3874                         break;
3875                 }
3876                 case OP_ATOMIC_ADD_NEW_I4:
3877                 case OP_ATOMIC_ADD_NEW_I8: {
3878                         int dreg = ins->dreg;
3879                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
3880
3881                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
3882                                 dreg = AMD64_R11;
3883
3884                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
3885                         amd64_prefix (code, X86_LOCK_PREFIX);
3886                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
3887                         /* dreg contains the old value, add with sreg2 value */
3888                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
3889
3890                         if (ins->dreg != dreg)
3891                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
3892
3893                         break;
3894                 }
3895                 case OP_ATOMIC_EXCHANGE_I4:
3896                 case OP_ATOMIC_EXCHANGE_I8: {
3897                         guchar *br[2];
3898                         int sreg2 = ins->sreg2;
3899                         int breg = ins->inst_basereg;
3900                         guint32 size = (ins->opcode == OP_ATOMIC_EXCHANGE_I4) ? 4 : 8;
3901
3902                         /*
3903                          * See http://msdn.microsoft.com/msdnmag/issues/0700/Win32/ for
3904                          * an explanation of how this works.
3905                          */
3906
3907                         /* cmpxchg uses eax as comperand, need to make sure we can use it
3908                          * hack to overcome limits in x86 reg allocator
3909                          * (req: dreg == eax and sreg2 != eax and breg != eax)
3910                          */
3911                         if (ins->dreg != AMD64_RAX)
3912                                 amd64_push_reg (code, AMD64_RAX);
3913
3914                         /* We need the EAX reg for the cmpxchg */
3915                         if (ins->sreg2 == AMD64_RAX) {
3916                                 amd64_push_reg (code, AMD64_RDX);
3917                                 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
3918                                 sreg2 = AMD64_RDX;
3919                         }
3920
3921                         if (breg == AMD64_RAX) {
3922                                 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3923                                 breg = AMD64_R11;
3924                         }
3925
3926                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
3927
3928                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
3929                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
3930                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
3931                         amd64_patch (br [1], br [0]);
3932
3933                         if (ins->dreg != AMD64_RAX) {
3934                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
3935                                 amd64_pop_reg (code, AMD64_RAX);
3936                         }
3937
3938                         if (ins->sreg2 != sreg2)
3939                                 amd64_pop_reg (code, AMD64_RDX);
3940
3941                         break;
3942                 }
3943                 default:
3944                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
3945                         g_assert_not_reached ();
3946                 }
3947
3948                 if ((code - cfg->native_code - offset) > max_len) {
3949                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
3950                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
3951                         g_assert_not_reached ();
3952                 }
3953
3954                 cpos += max_len;
3955
3956                 last_ins = ins;
3957                 last_offset = offset;
3958
3959                 ins = ins->next;
3960         }
3961
3962         cfg->code_len = code - cfg->native_code;
3963 }
3964
3965 void
3966 mono_arch_register_lowlevel_calls (void)
3967 {
3968 }
3969
3970 void
3971 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
3972 {
3973         MonoJumpInfo *patch_info;
3974         gboolean compile_aot = !run_cctors;
3975
3976         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
3977                 unsigned char *ip = patch_info->ip.i + code;
3978                 const unsigned char *target;
3979
3980                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
3981
3982                 if (compile_aot) {
3983                         switch (patch_info->type) {
3984                         case MONO_PATCH_INFO_BB:
3985                         case MONO_PATCH_INFO_LABEL:
3986                                 break;
3987                         default:
3988                                 /* No need to patch these */
3989                                 continue;
3990                         }
3991                 }
3992
3993                 switch (patch_info->type) {
3994                 case MONO_PATCH_INFO_NONE:
3995                         continue;
3996                 case MONO_PATCH_INFO_METHOD_REL:
3997                 case MONO_PATCH_INFO_R8:
3998                 case MONO_PATCH_INFO_R4:
3999                         g_assert_not_reached ();
4000                         continue;
4001                 case MONO_PATCH_INFO_BB:
4002                         break;
4003                 default:
4004                         break;
4005                 }
4006
4007                 /*
4008                  * Debug code to help track down problems where the target of a near call is
4009                  * is not valid.
4010                  */
4011                 if (amd64_is_near_call (ip)) {
4012                         gint64 disp = (guint8*)target - (guint8*)ip;
4013
4014                         if (!amd64_is_imm32 (disp)) {
4015                                 printf ("TYPE: %d\n", patch_info->type);
4016                                 switch (patch_info->type) {
4017                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
4018                                         printf ("V: %s\n", patch_info->data.name);
4019                                         break;
4020                                 case MONO_PATCH_INFO_METHOD_JUMP:
4021                                 case MONO_PATCH_INFO_METHOD:
4022                                         printf ("V: %s\n", patch_info->data.method->name);
4023                                         break;
4024                                 default:
4025                                         break;
4026                                 }
4027                         }
4028                 }
4029
4030                 amd64_patch (ip, (gpointer)target);
4031         }
4032 }
4033
4034 guint8 *
4035 mono_arch_emit_prolog (MonoCompile *cfg)
4036 {
4037         MonoMethod *method = cfg->method;
4038         MonoBasicBlock *bb;
4039         MonoMethodSignature *sig;
4040         MonoInst *inst;
4041         int alloc_size, pos, max_offset, i, quad;
4042         guint8 *code;
4043         CallInfo *cinfo;
4044         gint32 lmf_offset = cfg->arch.lmf_offset;
4045
4046         cfg->code_size =  MAX (((MonoMethodNormal *)method)->header->code_size * 4, 512);
4047         code = cfg->native_code = g_malloc (cfg->code_size);
4048
4049         /* Amount of stack space allocated by register saving code */
4050         pos = 0;
4051
4052         /*
4053          * The prolog consists of the following parts:
4054          * FP present:
4055          * - push rbp, mov rbp, rsp
4056          * - save callee saved regs using pushes
4057          * - allocate frame
4058          * - save lmf if needed
4059          * FP not present:
4060          * - allocate frame
4061          * - save lmf if needed
4062          * - save callee saved regs using moves
4063          */
4064
4065         if (!cfg->arch.omit_fp) {
4066                 amd64_push_reg (code, AMD64_RBP);
4067                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4068         }
4069
4070         /* Save callee saved registers */
4071         if (!cfg->arch.omit_fp && !method->save_lmf) {
4072                 for (i = 0; i < AMD64_NREG; ++i)
4073                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4074                                 amd64_push_reg (code, i);
4075                                 pos += sizeof (gpointer);
4076                         }
4077         }
4078
4079         alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4080
4081         alloc_size -= pos;
4082
4083         if (cfg->arch.omit_fp)
4084                 /*
4085                  * On enter, the stack is misaligned by the the pushing of the return
4086                  * address. It is either made aligned by the pushing of %rbp, or by
4087                  * this.
4088                  */
4089                 alloc_size += 8;
4090
4091         cfg->arch.stack_alloc_size = alloc_size;
4092
4093         /* Allocate stack frame */
4094         if (alloc_size) {
4095                 /* See mono_emit_stack_alloc */
4096 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4097                 guint32 remaining_size = alloc_size;
4098                 while (remaining_size >= 0x1000) {
4099                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4100                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4101                         remaining_size -= 0x1000;
4102                 }
4103                 if (remaining_size)
4104                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4105 #else
4106                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4107 #endif
4108         }
4109
4110         /* Stack alignment check */
4111 #if 0
4112         {
4113                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4114                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4115                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4116                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4117                 amd64_breakpoint (code);
4118         }
4119 #endif
4120
4121         /* Save LMF */
4122         if (method->save_lmf) {
4123                 /* Save ip */
4124                 amd64_lea_membase (code, AMD64_R11, AMD64_RIP, 0);
4125                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rip), AMD64_R11, 8);
4126                 /* Save fp */
4127                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), AMD64_RBP, 8);
4128                 /* Save sp */
4129                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4130                 /* Skip method (only needed for trampoline LMF frames) */
4131                 /* Save callee saved regs */
4132                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4133                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4134                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4135                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4136                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4137         }
4138
4139         /* Save callee saved registers */
4140         if (cfg->arch.omit_fp && !method->save_lmf) {
4141                 gint32 save_area_offset = 0;
4142
4143                 /* Save caller saved registers after sp is adjusted */
4144                 /* The registers are saved at the bottom of the frame */
4145                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4146                 for (i = 0; i < AMD64_NREG; ++i)
4147                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4148                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4149                                 save_area_offset += 8;
4150                         }
4151         }
4152
4153         /* compute max_offset in order to use short forward jumps */
4154         max_offset = 0;
4155         if (cfg->opt & MONO_OPT_BRANCH) {
4156                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4157                         MonoInst *ins = bb->code;
4158                         bb->max_offset = max_offset;
4159
4160                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4161                                 max_offset += 6;
4162                         /* max alignment for loops */
4163                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4164                                 max_offset += LOOP_ALIGNMENT;
4165
4166                         while (ins) {
4167                                 if (ins->opcode == OP_LABEL)
4168                                         ins->inst_c1 = max_offset;
4169
4170                                 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4171                                 ins = ins->next;
4172                         }
4173                 }
4174         }
4175
4176         sig = mono_method_signature (method);
4177         pos = 0;
4178
4179         cinfo = get_call_info (sig, FALSE);
4180
4181         if (sig->ret->type != MONO_TYPE_VOID) {
4182                 if ((cinfo->ret.storage == ArgInIReg) && (cfg->ret->opcode != OP_REGVAR)) {
4183                         /* Save volatile arguments to the stack */
4184                         amd64_mov_membase_reg (code, cfg->ret->inst_basereg, cfg->ret->inst_offset, cinfo->ret.reg, 8);
4185                 }
4186         }
4187
4188         /* Keep this in sync with emit_load_volatile_arguments */
4189         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4190                 ArgInfo *ainfo = cinfo->args + i;
4191                 gint32 stack_offset;
4192                 MonoType *arg_type;
4193                 inst = cfg->varinfo [i];
4194
4195                 if (sig->hasthis && (i == 0))
4196                         arg_type = &mono_defaults.object_class->byval_arg;
4197                 else
4198                         arg_type = sig->params [i - sig->hasthis];
4199
4200                 stack_offset = ainfo->offset + ARGS_OFFSET;
4201
4202                 /* Save volatile arguments to the stack */
4203                 if (inst->opcode != OP_REGVAR) {
4204                         switch (ainfo->storage) {
4205                         case ArgInIReg: {
4206                                 guint32 size = 8;
4207
4208                                 /* FIXME: I1 etc */
4209                                 /*
4210                                 if (stack_offset & 0x1)
4211                                         size = 1;
4212                                 else if (stack_offset & 0x2)
4213                                         size = 2;
4214                                 else if (stack_offset & 0x4)
4215                                         size = 4;
4216                                 else
4217                                         size = 8;
4218                                 */
4219                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg, size);
4220                                 break;
4221                         }
4222                         case ArgInFloatSSEReg:
4223                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4224                                 break;
4225                         case ArgInDoubleSSEReg:
4226                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset, ainfo->reg);
4227                                 break;
4228                         case ArgValuetypeInReg:
4229                                 for (quad = 0; quad < 2; quad ++) {
4230                                         switch (ainfo->pair_storage [quad]) {
4231                                         case ArgInIReg:
4232                                                 amd64_mov_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
4233                                                 break;
4234                                         case ArgInFloatSSEReg:
4235                                                 amd64_movss_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4236                                                 break;
4237                                         case ArgInDoubleSSEReg:
4238                                                 amd64_movsd_membase_reg (code, inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
4239                                                 break;
4240                                         case ArgNone:
4241                                                 break;
4242                                         default:
4243                                                 g_assert_not_reached ();
4244                                         }
4245                                 }
4246                                 break;
4247                         default:
4248                                 break;
4249                         }
4250                 }
4251
4252                 if (inst->opcode == OP_REGVAR) {
4253                         /* Argument allocated to (non-volatile) register */
4254                         switch (ainfo->storage) {
4255                         case ArgInIReg:
4256                                 amd64_mov_reg_reg (code, inst->dreg, ainfo->reg, 8);
4257                                 break;
4258                         case ArgOnStack:
4259                                 amd64_mov_reg_membase (code, inst->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
4260                                 break;
4261                         default:
4262                                 g_assert_not_reached ();
4263                         }
4264                 }
4265         }
4266
4267         /* Might need to attach the thread to the JIT */
4268         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
4269                 guint64 domain = (guint64)cfg->domain;
4270
4271                 /*
4272                  * The call might clobber argument registers, but they are already
4273                  * saved to the stack/global regs.
4274                  */
4275                 if (lmf_addr_tls_offset != -1) {
4276                         guint8 *buf;
4277
4278                         code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
4279                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
4280                         buf = code;
4281                         x86_branch8 (code, X86_CC_NE, 0, 0);
4282                         if ((domain >> 32) == 0)
4283                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4284                         else
4285                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4286                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4287                         amd64_patch (buf, code);
4288                 } else {
4289                         g_assert (!cfg->compile_aot);
4290                         if ((domain >> 32) == 0)
4291                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 4);
4292                         else
4293                                 amd64_mov_reg_imm_size (code, AMD64_RDI, domain, 8);
4294                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, (gpointer)"mono_jit_thread_attach");
4295                 }
4296         }
4297
4298         if (method->save_lmf) {
4299                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4300                         /*
4301                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4302                          * through the mono_lmf_addr TLS variable.
4303                          */
4304                         /* %rax = previous_lmf */
4305                         x86_prefix (code, X86_FS_PREFIX);
4306                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
4307
4308                         /* Save previous_lmf */
4309                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
4310                         /* Set new lmf */
4311                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4312                         x86_prefix (code, X86_FS_PREFIX);
4313                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4314                 } else {
4315                         if (lmf_addr_tls_offset != -1) {
4316                                 /* Load lmf quicky using the FS register */
4317                                 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
4318                         }
4319                         else {
4320                                 /*
4321                                  * The call might clobber argument registers, but they are already
4322                                  * saved to the stack/global regs.
4323                                  */
4324                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4325                                                                   (gpointer)"mono_get_lmf_addr");
4326                         }
4327
4328                         /* Save lmf_addr */
4329                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
4330                         /* Save previous_lmf */
4331                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
4332                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
4333                         /* Set new lmf */
4334                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
4335                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
4336                 }
4337         }
4338
4339
4340         g_free (cinfo);
4341
4342         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4343                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
4344
4345         cfg->code_len = code - cfg->native_code;
4346
4347         g_assert (cfg->code_len < cfg->code_size);
4348
4349         return code;
4350 }
4351
4352 void
4353 mono_arch_emit_epilog (MonoCompile *cfg)
4354 {
4355         MonoMethod *method = cfg->method;
4356         int quad, pos, i;
4357         guint8 *code;
4358         int max_epilog_size = 16;
4359         CallInfo *cinfo;
4360         gint32 lmf_offset = cfg->arch.lmf_offset;
4361
4362         if (cfg->method->save_lmf)
4363                 max_epilog_size += 256;
4364
4365         if (mono_jit_trace_calls != NULL)
4366                 max_epilog_size += 50;
4367
4368         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4369                 max_epilog_size += 50;
4370
4371         max_epilog_size += (AMD64_NREG * 2);
4372
4373         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
4374                 cfg->code_size *= 2;
4375                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4376                 mono_jit_stats.code_reallocs++;
4377         }
4378
4379         code = cfg->native_code + cfg->code_len;
4380
4381         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4382                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
4383
4384         /* the code restoring the registers must be kept in sync with CEE_JMP */
4385         pos = 0;
4386
4387         if (method->save_lmf) {
4388                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
4389                         /*
4390                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
4391                          * through the mono_lmf_addr TLS variable.
4392                          */
4393                         /* reg = previous_lmf */
4394                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4395                         x86_prefix (code, X86_FS_PREFIX);
4396                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
4397                 } else {
4398                         /* Restore previous lmf */
4399                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
4400                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
4401                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
4402                 }
4403
4404                 /* Restore caller saved regs */
4405                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
4406                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, ebp), 8);
4407                 }
4408                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
4409                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
4410                 }
4411                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
4412                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
4413                 }
4414                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
4415                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
4416                 }
4417                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
4418                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
4419                 }
4420                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
4421                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
4422                 }
4423         } else {
4424
4425                 if (cfg->arch.omit_fp) {
4426                         gint32 save_area_offset = 0;
4427
4428                         for (i = 0; i < AMD64_NREG; ++i)
4429                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4430                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
4431                                         save_area_offset += 8;
4432                                 }
4433                 }
4434                 else {
4435                         for (i = 0; i < AMD64_NREG; ++i)
4436                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4437                                         pos -= sizeof (gpointer);
4438
4439                         if (pos) {
4440                                 if (pos == - sizeof (gpointer)) {
4441                                         /* Only one register, so avoid lea */
4442                                         for (i = AMD64_NREG - 1; i > 0; --i)
4443                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4444                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
4445                                                 }
4446                                 }
4447                                 else {
4448                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4449
4450                                         /* Pop registers in reverse order */
4451                                         for (i = AMD64_NREG - 1; i > 0; --i)
4452                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4453                                                         amd64_pop_reg (code, i);
4454                                                 }
4455                                 }
4456                         }
4457                 }
4458         }
4459
4460         /* Load returned vtypes into registers if needed */
4461         cinfo = get_call_info (mono_method_signature (method), FALSE);
4462         if (cinfo->ret.storage == ArgValuetypeInReg) {
4463                 ArgInfo *ainfo = &cinfo->ret;
4464                 MonoInst *inst = cfg->ret;
4465
4466                 for (quad = 0; quad < 2; quad ++) {
4467                         switch (ainfo->pair_storage [quad]) {
4468                         case ArgInIReg:
4469                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
4470                                 break;
4471                         case ArgInFloatSSEReg:
4472                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4473                                 break;
4474                         case ArgInDoubleSSEReg:
4475                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
4476                                 break;
4477                         case ArgNone:
4478                                 break;
4479                         default:
4480                                 g_assert_not_reached ();
4481                         }
4482                 }
4483         }
4484         g_free (cinfo);
4485
4486         if (cfg->arch.omit_fp) {
4487                 if (cfg->arch.stack_alloc_size)
4488                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4489         } else {
4490                 amd64_leave (code);
4491         }
4492         amd64_ret (code);
4493
4494         cfg->code_len = code - cfg->native_code;
4495
4496         g_assert (cfg->code_len < cfg->code_size);
4497
4498         if (cfg->arch.omit_fp) {
4499                 /*
4500                  * Encode the stack size into used_int_regs so the exception handler
4501                  * can access it.
4502                  */
4503                 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
4504                 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
4505         }
4506 }
4507
4508 void
4509 mono_arch_emit_exceptions (MonoCompile *cfg)
4510 {
4511         MonoJumpInfo *patch_info;
4512         int nthrows, i;
4513         guint8 *code;
4514         MonoClass *exc_classes [16];
4515         guint8 *exc_throw_start [16], *exc_throw_end [16];
4516         guint32 code_size = 0;
4517
4518         /* Compute needed space */
4519         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4520                 if (patch_info->type == MONO_PATCH_INFO_EXC)
4521                         code_size += 40;
4522                 if (patch_info->type == MONO_PATCH_INFO_R8)
4523                         code_size += 8 + 15; /* sizeof (double) + alignment */
4524                 if (patch_info->type == MONO_PATCH_INFO_R4)
4525                         code_size += 4 + 15; /* sizeof (float) + alignment */
4526         }
4527
4528         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
4529                 cfg->code_size *= 2;
4530                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
4531                 mono_jit_stats.code_reallocs++;
4532         }
4533
4534         code = cfg->native_code + cfg->code_len;
4535
4536         /* add code to raise exceptions */
4537         nthrows = 0;
4538         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4539                 switch (patch_info->type) {
4540                 case MONO_PATCH_INFO_EXC: {
4541                         MonoClass *exc_class;
4542                         guint8 *buf, *buf2;
4543                         guint32 throw_ip;
4544
4545                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
4546
4547                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
4548                         g_assert (exc_class);
4549                         throw_ip = patch_info->ip.i;
4550
4551                         //x86_breakpoint (code);
4552                         /* Find a throw sequence for the same exception class */
4553                         for (i = 0; i < nthrows; ++i)
4554                                 if (exc_classes [i] == exc_class)
4555                                         break;
4556                         if (i < nthrows) {
4557                                 amd64_mov_reg_imm (code, AMD64_RSI, (exc_throw_end [i] - cfg->native_code) - throw_ip);
4558                                 x86_jump_code (code, exc_throw_start [i]);
4559                                 patch_info->type = MONO_PATCH_INFO_NONE;
4560                         }
4561                         else {
4562                                 buf = code;
4563                                 amd64_mov_reg_imm_size (code, AMD64_RSI, 0xf0f0f0f0, 4);
4564                                 buf2 = code;
4565
4566                                 if (nthrows < 16) {
4567                                         exc_classes [nthrows] = exc_class;
4568                                         exc_throw_start [nthrows] = code;
4569                                 }
4570
4571                                 amd64_mov_reg_imm (code, AMD64_RDI, exc_class->type_token);
4572                                 patch_info->data.name = "mono_arch_throw_corlib_exception";
4573                                 patch_info->type = MONO_PATCH_INFO_INTERNAL_METHOD;
4574                                 patch_info->ip.i = code - cfg->native_code;
4575
4576                                 code = emit_call_body (cfg, code, patch_info->type, patch_info->data.name);
4577
4578                                 amd64_mov_reg_imm (buf, AMD64_RSI, (code - cfg->native_code) - throw_ip);
4579                                 while (buf < buf2)
4580                                         x86_nop (buf);
4581
4582                                 if (nthrows < 16) {
4583                                         exc_throw_end [nthrows] = code;
4584                                         nthrows ++;
4585                                 }
4586                         }
4587                         break;
4588                 }
4589                 default:
4590                         /* do nothing */
4591                         break;
4592                 }
4593         }
4594
4595         /* Handle relocations with RIP relative addressing */
4596         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
4597                 gboolean remove = FALSE;
4598
4599                 switch (patch_info->type) {
4600                 case MONO_PATCH_INFO_R8:
4601                 case MONO_PATCH_INFO_R4: {
4602                         guint8 *pos;
4603
4604                         if (use_sse2) {
4605                                 /* The SSE opcodes require a 16 byte alignment */
4606                                 code = (guint8*)ALIGN_TO (code, 16);
4607                         } else {
4608                                 code = (guint8*)ALIGN_TO (code, 8);
4609                         }
4610
4611                         pos = cfg->native_code + patch_info->ip.i;
4612
4613                         if (use_sse2)
4614                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
4615                         else
4616                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
4617
4618                         if (patch_info->type == MONO_PATCH_INFO_R8) {
4619                                 *(double*)code = *(double*)patch_info->data.target;
4620                                 code += sizeof (double);
4621                         } else {
4622                                 *(float*)code = *(float*)patch_info->data.target;
4623                                 code += sizeof (float);
4624                         }
4625
4626                         remove = TRUE;
4627                         break;
4628                 }
4629                 default:
4630                         break;
4631                 }
4632
4633                 if (remove) {
4634                         if (patch_info == cfg->patch_info)
4635                                 cfg->patch_info = patch_info->next;
4636                         else {
4637                                 MonoJumpInfo *tmp;
4638
4639                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
4640                                         ;
4641                                 tmp->next = patch_info->next;
4642                         }
4643                 }
4644         }
4645
4646         cfg->code_len = code - cfg->native_code;
4647
4648         g_assert (cfg->code_len < cfg->code_size);
4649
4650 }
4651
4652 void*
4653 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4654 {
4655         guchar *code = p;
4656         CallInfo *cinfo = NULL;
4657         MonoMethodSignature *sig;
4658         MonoInst *inst;
4659         int i, n, stack_area = 0;
4660
4661         /* Keep this in sync with mono_arch_get_argument_info */
4662
4663         if (enable_arguments) {
4664                 /* Allocate a new area on the stack and save arguments there */
4665                 sig = mono_method_signature (cfg->method);
4666
4667                 cinfo = get_call_info (sig, FALSE);
4668
4669                 n = sig->param_count + sig->hasthis;
4670
4671                 stack_area = ALIGN_TO (n * 8, 16);
4672
4673                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
4674
4675                 for (i = 0; i < n; ++i) {
4676                         inst = cfg->varinfo [i];
4677
4678                         if (inst->opcode == OP_REGVAR)
4679                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
4680                         else {
4681                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
4682                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
4683                         }
4684                 }
4685         }
4686
4687         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
4688         amd64_set_reg_template (code, AMD64_RDI);
4689         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RSP, 8);
4690         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4691
4692         if (enable_arguments) {
4693                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
4694
4695                 g_free (cinfo);
4696         }
4697
4698         return code;
4699 }
4700
4701 enum {
4702         SAVE_NONE,
4703         SAVE_STRUCT,
4704         SAVE_EAX,
4705         SAVE_EAX_EDX,
4706         SAVE_XMM
4707 };
4708
4709 void*
4710 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
4711 {
4712         guchar *code = p;
4713         int save_mode = SAVE_NONE;
4714         MonoMethod *method = cfg->method;
4715         int rtype = mono_type_get_underlying_type (mono_method_signature (method)->ret)->type;
4716
4717         switch (rtype) {
4718         case MONO_TYPE_VOID:
4719                 /* special case string .ctor icall */
4720                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
4721                         save_mode = SAVE_EAX;
4722                 else
4723                         save_mode = SAVE_NONE;
4724                 break;
4725         case MONO_TYPE_I8:
4726         case MONO_TYPE_U8:
4727                 save_mode = SAVE_EAX;
4728                 break;
4729         case MONO_TYPE_R4:
4730         case MONO_TYPE_R8:
4731                 save_mode = SAVE_XMM;
4732                 break;
4733         case MONO_TYPE_GENERICINST:
4734                 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
4735                         save_mode = SAVE_EAX;
4736                         break;
4737                 }
4738                 /* Fall through */
4739         case MONO_TYPE_VALUETYPE:
4740                 save_mode = SAVE_STRUCT;
4741                 break;
4742         default:
4743                 save_mode = SAVE_EAX;
4744                 break;
4745         }
4746
4747         /* Save the result and copy it into the proper argument register */
4748         switch (save_mode) {
4749         case SAVE_EAX:
4750                 amd64_push_reg (code, AMD64_RAX);
4751                 /* Align stack */
4752                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4753                 if (enable_arguments)
4754                         amd64_mov_reg_reg (code, AMD64_RSI, AMD64_RAX, 8);
4755                 break;
4756         case SAVE_STRUCT:
4757                 /* FIXME: */
4758                 if (enable_arguments)
4759                         amd64_mov_reg_imm (code, AMD64_RSI, 0);
4760                 break;
4761         case SAVE_XMM:
4762                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4763                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
4764                 /* Align stack */
4765                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4766                 /*
4767                  * The result is already in the proper argument register so no copying
4768                  * needed.
4769                  */
4770                 break;
4771         case SAVE_NONE:
4772                 break;
4773         default:
4774                 g_assert_not_reached ();
4775         }
4776
4777         /* Set %al since this is a varargs call */
4778         if (save_mode == SAVE_XMM)
4779                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
4780         else
4781                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
4782
4783         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
4784         amd64_set_reg_template (code, AMD64_RDI);
4785         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func);
4786
4787         /* Restore result */
4788         switch (save_mode) {
4789         case SAVE_EAX:
4790                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4791                 amd64_pop_reg (code, AMD64_RAX);
4792                 break;
4793         case SAVE_STRUCT:
4794                 /* FIXME: */
4795                 break;
4796         case SAVE_XMM:
4797                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4798                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
4799                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4800                 break;
4801         case SAVE_NONE:
4802                 break;
4803         default:
4804                 g_assert_not_reached ();
4805         }
4806
4807         return code;
4808 }
4809
4810 void
4811 mono_arch_flush_icache (guint8 *code, gint size)
4812 {
4813         /* Not needed */
4814 }
4815
4816 void
4817 mono_arch_flush_register_windows (void)
4818 {
4819 }
4820
4821 gboolean
4822 mono_arch_is_inst_imm (gint64 imm)
4823 {
4824         return amd64_is_imm32 (imm);
4825 }
4826
4827 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
4828
4829 /*
4830  * Determine whenever the trap whose info is in SIGINFO is caused by
4831  * integer overflow.
4832  */
4833 gboolean
4834 mono_arch_is_int_overflow (void *sigctx, void *info)
4835 {
4836         MonoContext ctx;
4837         guint8* rip;
4838         int reg;
4839         gint64 value;
4840
4841         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
4842
4843         rip = (guint8*)ctx.rip;
4844
4845         if (IS_REX (rip [0])) {
4846                 reg = amd64_rex_b (rip [0]);
4847                 rip ++;
4848         }
4849         else
4850                 reg = 0;
4851
4852         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
4853                 /* idiv REG */
4854                 reg += x86_modrm_rm (rip [1]);
4855
4856                 switch (reg) {
4857                 case AMD64_RAX:
4858                         value = ctx.rax;
4859                         break;
4860                 case AMD64_RBX:
4861                         value = ctx.rbx;
4862                         break;
4863                 case AMD64_RCX:
4864                         value = ctx.rcx;
4865                         break;
4866                 case AMD64_RDX:
4867                         value = ctx.rdx;
4868                         break;
4869                 case AMD64_RBP:
4870                         value = ctx.rbp;
4871                         break;
4872                 case AMD64_RSP:
4873                         value = ctx.rsp;
4874                         break;
4875                 case AMD64_RSI:
4876                         value = ctx.rsi;
4877                         break;
4878                 case AMD64_RDI:
4879                         value = ctx.rdi;
4880                         break;
4881                 case AMD64_R12:
4882                         value = ctx.r12;
4883                         break;
4884                 case AMD64_R13:
4885                         value = ctx.r13;
4886                         break;
4887                 case AMD64_R14:
4888                         value = ctx.r14;
4889                         break;
4890                 case AMD64_R15:
4891                         value = ctx.r15;
4892                         break;
4893                 default:
4894                         g_assert_not_reached ();
4895                         reg = -1;
4896                 }
4897
4898                 if (value == -1)
4899                         return TRUE;
4900         }
4901
4902         return FALSE;
4903 }
4904
4905 guint32
4906 mono_arch_get_patch_offset (guint8 *code)
4907 {
4908         return 3;
4909 }
4910
4911 gpointer*
4912 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
4913 {
4914         guint32 reg;
4915         guint32 disp;
4916         guint8 rex = 0;
4917
4918         /* go to the start of the call instruction
4919          *
4920          * address_byte = (m << 6) | (o << 3) | reg
4921          * call opcode: 0xff address_byte displacement
4922          * 0xff m=1,o=2 imm8
4923          * 0xff m=2,o=2 imm32
4924          */
4925         code -= 7;
4926
4927         /*
4928          * A given byte sequence can match more than case here, so we have to be
4929          * really careful about the ordering of the cases. Longer sequences
4930          * come first.
4931          */
4932         if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4933                         /*
4934                          * This is a interface call
4935                          * 48 8b 80 f0 e8 ff ff   mov    0xffffffffffffe8f0(%rax),%rax
4936                          * ff 10                  callq  *(%rax)
4937                          */
4938                 if (IS_REX (code [4]))
4939                         rex = code [4];
4940                 reg = amd64_modrm_rm (code [6]);
4941                 disp = 0;
4942         }
4943         else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
4944                 /* call OFFSET(%rip) */
4945                 disp = *(guint32*)(code + 3);
4946                 return (gpointer*)(code + disp + 7);
4947         }
4948         else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
4949                 /* call *[reg+disp32] */
4950                 if (IS_REX (code [0]))
4951                         rex = code [0];
4952                 reg = amd64_modrm_rm (code [2]);
4953                 disp = *(guint32*)(code + 3);
4954                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4955         }
4956         else if (code [2] == 0xe8) {
4957                 /* call <ADDR> */
4958                 return NULL;
4959         }
4960         else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
4961                 /* call *%reg */
4962                 return NULL;
4963         }
4964         else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
4965                 /* call *[reg+disp8] */
4966                 if (IS_REX (code [3]))
4967                         rex = code [3];
4968                 reg = amd64_modrm_rm (code [5]);
4969                 disp = *(guint8*)(code + 6);
4970                 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
4971         }
4972         else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
4973                         /*
4974                          * This is a interface call: should check the above code can't catch it earlier
4975                          * 8b 40 30   mov    0x30(%eax),%eax
4976                          * ff 10      call   *(%eax)
4977                          */
4978                 if (IS_REX (code [4]))
4979                         rex = code [4];
4980                 reg = amd64_modrm_rm (code [6]);
4981                 disp = 0;
4982         }
4983         else
4984                 g_assert_not_reached ();
4985
4986         reg += amd64_rex_b (rex);
4987
4988         /* R11 is clobbered by the trampoline code */
4989         g_assert (reg != AMD64_R11);
4990
4991         return (gpointer)(((guint64)(regs [reg])) + disp);
4992 }
4993
4994 gpointer*
4995 mono_arch_get_delegate_method_ptr_addr (guint8* code, gpointer *regs)
4996 {
4997         guint32 reg;
4998         guint32 disp;
4999
5000         code -= 10;
5001
5002         if (IS_REX (code [0]) && (code [1] == 0x8b) && (code [3] == 0x48) && (code [4] == 0x8b) && (code [5] == 0x40) && (code [7] == 0x48) && (code [8] == 0xff) && (code [9] == 0xd0)) {
5003                 /* mov REG, %rax; mov <OFFSET>(%rax), %rax; call *%rax */
5004                 reg = amd64_rex_b (code [0]) + amd64_modrm_rm (code [2]);
5005                 disp = code [6];
5006
5007                 if (reg == AMD64_RAX)
5008                         return NULL;
5009                 else
5010                         return (gpointer*)(((guint64)(regs [reg])) + disp);
5011         }
5012
5013         return NULL;
5014 }
5015
5016 /*
5017  * Support for fast access to the thread-local lmf structure using the GS
5018  * segment register on NPTL + kernel 2.6.x.
5019  */
5020
5021 static gboolean tls_offset_inited = FALSE;
5022
5023 void
5024 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
5025 {
5026         if (!tls_offset_inited) {
5027                 tls_offset_inited = TRUE;
5028 #ifdef MONO_XEN_OPT
5029                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
5030 #endif
5031                 appdomain_tls_offset = mono_domain_get_tls_offset ();
5032                 lmf_tls_offset = mono_get_lmf_tls_offset ();
5033                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
5034                 thread_tls_offset = mono_thread_get_tls_offset ();
5035         }
5036 }
5037
5038 void
5039 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
5040 {
5041 }
5042
5043 void
5044 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
5045 {
5046         MonoCallInst *call = (MonoCallInst*)inst;
5047         CallInfo * cinfo = get_call_info (inst->signature, FALSE);
5048
5049         if (vt_reg != -1) {
5050                 MonoInst *vtarg;
5051
5052                 if (cinfo->ret.storage == ArgValuetypeInReg) {
5053                         /*
5054                          * The valuetype is in RAX:RDX after the call, need to be copied to
5055                          * the stack. Push the address here, so the call instruction can
5056                          * access it.
5057                          */
5058                         MONO_INST_NEW (cfg, vtarg, OP_X86_PUSH);
5059                         vtarg->sreg1 = vt_reg;
5060                         mono_bblock_add_inst (cfg->cbb, vtarg);
5061
5062                         /* Align stack */
5063                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
5064                 }
5065                 else {
5066                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
5067                         vtarg->sreg1 = vt_reg;
5068                         vtarg->dreg = mono_regstate_next_int (cfg->rs);
5069                         mono_bblock_add_inst (cfg->cbb, vtarg);
5070
5071                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
5072                 }
5073         }
5074
5075         /* add the this argument */
5076         if (this_reg != -1) {
5077                 MonoInst *this;
5078                 MONO_INST_NEW (cfg, this, OP_MOVE);
5079                 this->type = this_type;
5080                 this->sreg1 = this_reg;
5081                 this->dreg = mono_regstate_next_int (cfg->rs);
5082                 mono_bblock_add_inst (cfg->cbb, this);
5083
5084                 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
5085         }
5086
5087         g_free (cinfo);
5088 }
5089
5090 MonoInst*
5091 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
5092 {
5093         MonoInst *ins = NULL;
5094
5095         if (cmethod->klass == mono_defaults.math_class) {
5096                 if (strcmp (cmethod->name, "Sin") == 0) {
5097                         MONO_INST_NEW (cfg, ins, OP_SIN);
5098                         ins->inst_i0 = args [0];
5099                 } else if (strcmp (cmethod->name, "Cos") == 0) {
5100                         MONO_INST_NEW (cfg, ins, OP_COS);
5101                         ins->inst_i0 = args [0];
5102                 } else if (strcmp (cmethod->name, "Tan") == 0) {
5103                         if (use_sse2)
5104                                 return ins;
5105                         MONO_INST_NEW (cfg, ins, OP_TAN);
5106                         ins->inst_i0 = args [0];
5107                 } else if (strcmp (cmethod->name, "Atan") == 0) {
5108                         if (use_sse2)
5109                                 return ins;
5110                         MONO_INST_NEW (cfg, ins, OP_ATAN);
5111                         ins->inst_i0 = args [0];
5112                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
5113                         MONO_INST_NEW (cfg, ins, OP_SQRT);
5114                         ins->inst_i0 = args [0];
5115                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
5116                         MONO_INST_NEW (cfg, ins, OP_ABS);
5117                         ins->inst_i0 = args [0];
5118                 }
5119 #if 0
5120                 /* OP_FREM is not IEEE compatible */
5121                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
5122                         MONO_INST_NEW (cfg, ins, OP_FREM);
5123                         ins->inst_i0 = args [0];
5124                         ins->inst_i1 = args [1];
5125                 }
5126 #endif
5127         } else if (cmethod->klass == mono_defaults.thread_class &&
5128                            strcmp (cmethod->name, "MemoryBarrier") == 0) {
5129                 MONO_INST_NEW (cfg, ins, OP_MEMORY_BARRIER);
5130         } else if(cmethod->klass->image == mono_defaults.corlib &&
5131                            (strcmp (cmethod->klass->name_space, "System.Threading") == 0) &&
5132                            (strcmp (cmethod->klass->name, "Interlocked") == 0)) {
5133
5134                 if (strcmp (cmethod->name, "Increment") == 0) {
5135                         MonoInst *ins_iconst;
5136                         guint32 opcode;
5137
5138                         if (fsig->params [0]->type == MONO_TYPE_I4)
5139                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5140                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5141                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5142                         else
5143                                 g_assert_not_reached ();
5144                         MONO_INST_NEW (cfg, ins, opcode);
5145                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5146                         ins_iconst->inst_c0 = 1;
5147
5148                         ins->inst_i0 = args [0];
5149                         ins->inst_i1 = ins_iconst;
5150                 } else if (strcmp (cmethod->name, "Decrement") == 0) {
5151                         MonoInst *ins_iconst;
5152                         guint32 opcode;
5153
5154                         if (fsig->params [0]->type == MONO_TYPE_I4)
5155                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5156                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5157                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5158                         else
5159                                 g_assert_not_reached ();
5160                         MONO_INST_NEW (cfg, ins, opcode);
5161                         MONO_INST_NEW (cfg, ins_iconst, OP_ICONST);
5162                         ins_iconst->inst_c0 = -1;
5163
5164                         ins->inst_i0 = args [0];
5165                         ins->inst_i1 = ins_iconst;
5166                 } else if (strcmp (cmethod->name, "Add") == 0) {
5167                         guint32 opcode;
5168
5169                         if (fsig->params [0]->type == MONO_TYPE_I4)
5170                                 opcode = OP_ATOMIC_ADD_NEW_I4;
5171                         else if (fsig->params [0]->type == MONO_TYPE_I8)
5172                                 opcode = OP_ATOMIC_ADD_NEW_I8;
5173                         else
5174                                 g_assert_not_reached ();
5175
5176                         MONO_INST_NEW (cfg, ins, opcode);
5177
5178                         ins->inst_i0 = args [0];
5179                         ins->inst_i1 = args [1];
5180                 } else if (strcmp (cmethod->name, "Exchange") == 0) {
5181                         guint32 opcode;
5182
5183                         if (fsig->params [0]->type == MONO_TYPE_I4)
5184                                 opcode = OP_ATOMIC_EXCHANGE_I4;
5185                         else if ((fsig->params [0]->type == MONO_TYPE_I8) ||
5186                                          (fsig->params [0]->type == MONO_TYPE_I) ||
5187                                          (fsig->params [0]->type == MONO_TYPE_OBJECT))
5188                                 opcode = OP_ATOMIC_EXCHANGE_I8;
5189                         else
5190                                 return NULL;
5191
5192                         MONO_INST_NEW (cfg, ins, opcode);
5193
5194                         ins->inst_i0 = args [0];
5195                         ins->inst_i1 = args [1];
5196                 } else if (strcmp (cmethod->name, "Read") == 0 && (fsig->params [0]->type == MONO_TYPE_I8)) {
5197                         /* 64 bit reads are already atomic */
5198                         MONO_INST_NEW (cfg, ins, CEE_LDIND_I8);
5199                         ins->inst_i0 = args [0];
5200                 }
5201
5202                 /*
5203                  * Can't implement CompareExchange methods this way since they have
5204                  * three arguments.
5205                  */
5206         }
5207
5208         return ins;
5209 }
5210
5211 gboolean
5212 mono_arch_print_tree (MonoInst *tree, int arity)
5213 {
5214         return 0;
5215 }
5216
5217 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
5218 {
5219         MonoInst* ins;
5220
5221         if (appdomain_tls_offset == -1)
5222                 return NULL;
5223
5224         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5225         ins->inst_offset = appdomain_tls_offset;
5226         return ins;
5227 }
5228
5229 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
5230 {
5231         MonoInst* ins;
5232
5233         if (thread_tls_offset == -1)
5234                 return NULL;
5235
5236         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
5237         ins->inst_offset = thread_tls_offset;
5238         return ins;
5239 }