mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internals.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /* The single step trampoline */
  69 static gpointer ss_trampoline;
  70
  71 /* The breakpoint trampoline */
  72 static gpointer bp_trampoline;
  73
  74 /* Offset between fp and the first argument in the callee */
  75 #define ARGS_OFFSET 16
  76 #define GP_SCRATCH_REG AMD64_R11
  77
  78 /*
  79  * AMD64 register usage:
  80  * - callee saved registers are used for global register allocation
  81  * - %r11 is used for materializing 64 bit constants in opcodes
  82  * - the rest is used for local allocation
  83  */
  84
  85 /*
  86  * Floating point comparison results:
  87  *                  ZF PF CF
  88  * A > B            0  0  0
  89  * A < B            0  0  1
  90  * A = B            1  0  0
  91  * A > B            0  0  0
  92  * UNORDERED        1  1  1
  93  */
  94
  95 const char*
  96 mono_arch_regname (int reg)
  97 {
  98         switch (reg) {
  99         case AMD64_RAX: return "%rax";
 100         case AMD64_RBX: return "%rbx";
 101         case AMD64_RCX: return "%rcx";
 102         case AMD64_RDX: return "%rdx";
 103         case AMD64_RSP: return "%rsp";
 104         case AMD64_RBP: return "%rbp";
 105         case AMD64_RDI: return "%rdi";
 106         case AMD64_RSI: return "%rsi";
 107         case AMD64_R8: return "%r8";
 108         case AMD64_R9: return "%r9";
 109         case AMD64_R10: return "%r10";
 110         case AMD64_R11: return "%r11";
 111         case AMD64_R12: return "%r12";
 112         case AMD64_R13: return "%r13";
 113         case AMD64_R14: return "%r14";
 114         case AMD64_R15: return "%r15";
 115         }
 116         return "unknown";
 117 }
 118
 119 static const char * packed_xmmregs [] = {
 120         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 121         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 122 };
 123
 124 static const char * single_xmmregs [] = {
 125         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 126         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 127 };
 128
 129 const char*
 130 mono_arch_fregname (int reg)
 131 {
 132         if (reg < AMD64_XMM_NREG)
 133                 return single_xmmregs [reg];
 134         else
 135                 return "unknown";
 136 }
 137
 138 const char *
 139 mono_arch_xregname (int reg)
 140 {
 141         if (reg < AMD64_XMM_NREG)
 142                 return packed_xmmregs [reg];
 143         else
 144                 return "unknown";
 145 }
 146
 147 static gboolean
 148 debug_omit_fp (void)
 149 {
 150 #if 0
 151         return mono_debug_count ();
 152 #else
 153         return TRUE;
 154 #endif
 155 }
 156
 157 static inline gboolean
 158 amd64_is_near_call (guint8 *code)
 159 {
 160         /* Skip REX */
 161         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 162                 code += 1;
 163
 164         return code [0] == 0xe8;
 165 }
 166
 167 static inline gboolean
 168 amd64_use_imm32 (gint64 val)
 169 {
 170         if (mini_get_debug_options()->single_imm_size)
 171                 return FALSE;
 172
 173         return amd64_is_imm32 (val);
 174 }
 175
 176 #ifdef __native_client_codegen__
 177
 178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 179 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 181 /* We only want to force bundle alignment for the top level instruction,    */
 182 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 183 static MonoNativeTlsKey nacl_instruction_depth;
 184
 185 static MonoNativeTlsKey nacl_rex_tag;
 186 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 187
 188 void
 189 amd64_nacl_clear_legacy_prefix_tag ()
 190 {
 191         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 192 }
 193
 194 void
 195 amd64_nacl_tag_legacy_prefix (guint8* code)
 196 {
 197         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 198                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 199 }
 200
 201 void
 202 amd64_nacl_tag_rex (guint8* code)
 203 {
 204         mono_native_tls_set_value (nacl_rex_tag, code);
 205 }
 206
 207 guint8*
 208 amd64_nacl_get_legacy_prefix_tag ()
 209 {
 210         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 211 }
 212
 213 guint8*
 214 amd64_nacl_get_rex_tag ()
 215 {
 216         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 217 }
 218
 219 /* Increment the instruction "depth" described above */
 220 void
 221 amd64_nacl_instruction_pre ()
 222 {
 223         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 224         depth++;
 225         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 226 }
 227
 228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 229 /* alignment if depth == 0 (top level instruction)                          */
 230 /* IN: start, end    pointers to instruction beginning and end              */
 231 /* OUT: start, end   pointers to beginning and end after possible alignment */
 232 /* GLOBALS: nacl_instruction_depth     defined above                        */
 233 void
 234 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 235 {
 236         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 237         depth--;
 238         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 239
 240         g_assert ( depth >= 0 );
 241         if (depth == 0) {
 242                 uintptr_t space_in_block;
 243                 uintptr_t instlen;
 244                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 245                 /* if legacy prefix is present, and if it was emitted before */
 246                 /* the start of the instruction sequence, adjust the start   */
 247                 if (prefix != NULL && prefix < *start) {
 248                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 249                         *start = prefix;
 250                 }
 251                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 252                 instlen = (uintptr_t)(*end - *start);
 253                 /* Only check for instructions which are less than        */
 254                 /* kNaClAlignment. The only instructions that should ever */
 255                 /* be that long are call sequences, which are already     */
 256                 /* padded out to align the return to the next bundle.     */
 257                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 258                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 259                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 260                         const size_t length = (size_t)((*end)-(*start));
 261                         g_assert (length < MAX_NACL_INST_LENGTH);
 262
 263                         memcpy (copy_of_instruction, *start, length);
 264                         *start = mono_arch_nacl_pad (*start, space_in_block);
 265                         memcpy (*start, copy_of_instruction, length);
 266                         *end = *start + length;
 267                 }
 268                 amd64_nacl_clear_legacy_prefix_tag ();
 269                 amd64_nacl_tag_rex (NULL);
 270         }
 271 }
 272
 273 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 274 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 275 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 276 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 277 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 278 /* IN:      code                                                            */
 279 /*             pointer to current instruction stream (in the                */
 280 /*             middle of an instruction, after opcode is emitted)           */
 281 /*          basereg/offset/dreg                                             */
 282 /*             operands of normal membase address                           */
 283 /* OUT:     code                                                            */
 284 /*             pointer to the end of the membase/memindex emit              */
 285 /* GLOBALS: nacl_rex_tag                                                    */
 286 /*             position in instruction stream that rex prefix was emitted   */
 287 /*          nacl_legacy_prefix_tag                                          */
 288 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 289 void
 290 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 291 {
 292         gint8 true_basereg = basereg;
 293
 294         /* Cache these values, they might change  */
 295         /* as new instructions are emitted below. */
 296         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 297         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 298
 299         /* 'basereg' is given masked to 0x7 at this point, so check */
 300         /* the rex prefix to see if this is an extended register.   */
 301         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 302                 true_basereg |= 0x8;
 303         }
 304
 305 #define X86_LEA_OPCODE (0x8D)
 306
 307         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 308                 guint8* old_instruction_start;
 309
 310                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 311                 /* 32-bits of the old base register (new index register)     */
 312                 guint8 buf[32];
 313                 guint8* buf_ptr = buf;
 314                 size_t insert_len;
 315
 316                 g_assert (rex_tag != NULL);
 317
 318                 if (IS_REX(*rex_tag)) {
 319                         /* The old rex.B should be the new rex.X */
 320                         if (*rex_tag & AMD64_REX_B) {
 321                                 *rex_tag |= AMD64_REX_X;
 322                         }
 323                         /* Since our new base is %r15 set rex.B */
 324                         *rex_tag |= AMD64_REX_B;
 325                 } else {
 326                         /* Shift the instruction by one byte  */
 327                         /* so we can insert a rex prefix      */
 328                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 329                         *code += 1;
 330                         /* New rex prefix only needs rex.B for %r15 base */
 331                         *rex_tag = AMD64_REX(AMD64_REX_B);
 332                 }
 333
 334                 if (legacy_prefix_tag) {
 335                         old_instruction_start = legacy_prefix_tag;
 336                 } else {
 337                         old_instruction_start = rex_tag;
 338                 }
 339
 340                 /* Clears the upper 32-bits of the previous base register */
 341                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 342                 insert_len = buf_ptr - buf;
 343
 344                 /* Move the old instruction forward to make */
 345                 /* room for 'mov' stored in 'buf_ptr'       */
 346                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 347                 *code += insert_len;
 348                 memcpy (old_instruction_start, buf, insert_len);
 349
 350                 /* Sandboxed replacement for the normal membase_emit */
 351                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 352
 353         } else {
 354                 /* Normal default behavior, emit membase memory location */
 355                 x86_membase_emit_body (*code, dreg, basereg, offset);
 356         }
 357 }
 358
 359
 360 static inline unsigned char*
 361 amd64_skip_nops (unsigned char* code)
 362 {
 363         guint8 in_nop;
 364         do {
 365                 in_nop = 0;
 366                 if (   code[0] == 0x90) {
 367                         in_nop = 1;
 368                         code += 1;
 369                 }
 370                 if (   code[0] == 0x66 && code[1] == 0x90) {
 371                         in_nop = 1;
 372                         code += 2;
 373                 }
 374                 if (code[0] == 0x0f && code[1] == 0x1f
 375                  && code[2] == 0x00) {
 376                         in_nop = 1;
 377                         code += 3;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x40 && code[3] == 0x00) {
 381                         in_nop = 1;
 382                         code += 4;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x44 && code[3] == 0x00
 386                  && code[4] == 0x00) {
 387                         in_nop = 1;
 388                         code += 5;
 389                 }
 390                 if (code[0] == 0x66 && code[1] == 0x0f
 391                  && code[2] == 0x1f && code[3] == 0x44
 392                  && code[4] == 0x00 && code[5] == 0x00) {
 393                         in_nop = 1;
 394                         code += 6;
 395                 }
 396                 if (code[0] == 0x0f && code[1] == 0x1f
 397                  && code[2] == 0x80 && code[3] == 0x00
 398                  && code[4] == 0x00 && code[5] == 0x00
 399                  && code[6] == 0x00) {
 400                         in_nop = 1;
 401                         code += 7;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x84 && code[3] == 0x00
 405                  && code[4] == 0x00 && code[5] == 0x00
 406                  && code[6] == 0x00 && code[7] == 0x00) {
 407                         in_nop = 1;
 408                         code += 8;
 409                 }
 410         } while ( in_nop );
 411         return code;
 412 }
 413
 414 guint8*
 415 mono_arch_nacl_skip_nops (guint8* code)
 416 {
 417   return amd64_skip_nops(code);
 418 }
 419
 420 #endif /*__native_client_codegen__*/
 421
 422 static void
 423 amd64_patch (unsigned char* code, gpointer target)
 424 {
 425         guint8 rex = 0;
 426
 427 #ifdef __native_client_codegen__
 428         code = amd64_skip_nops (code);
 429 #endif
 430 #if defined(__native_client_codegen__) && defined(__native_client__)
 431         if (nacl_is_code_address (code)) {
 432                 /* For tail calls, code is patched after being installed */
 433                 /* but not through the normal "patch callsite" method.   */
 434                 unsigned char buf[kNaClAlignment];
 435                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 436                 int ret;
 437                 memcpy (buf, aligned_code, kNaClAlignment);
 438                 /* Patch a temp buffer of bundle size, */
 439                 /* then install to actual location.    */
 440                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 441                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 442                 g_assert (ret == 0);
 443                 return;
 444         }
 445         target = nacl_modify_patch_target (target);
 446 #endif
 447
 448         /* Skip REX */
 449         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 450                 rex = code [0];
 451                 code += 1;
 452         }
 453
 454         if ((code [0] & 0xf8) == 0xb8) {
 455                 /* amd64_set_reg_template */
 456                 *(guint64*)(code + 1) = (guint64)target;
 457         }
 458         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 459                 /* mov 0(%rip), %dreg */
 460                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 461         }
 462         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 463                 /* call *<OFFSET>(%rip) */
 464                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 465         }
 466         else if (code [0] == 0xe8) {
 467                 /* call <DISP> */
 468                 gint64 disp = (guint8*)target - (guint8*)code;
 469                 g_assert (amd64_is_imm32 (disp));
 470                 x86_patch (code, (unsigned char*)target);
 471         }
 472         else
 473                 x86_patch (code, (unsigned char*)target);
 474 }
 475
 476 void
 477 mono_amd64_patch (unsigned char* code, gpointer target)
 478 {
 479         amd64_patch (code, target);
 480 }
 481
 482 typedef enum {
 483         ArgInIReg,
 484         ArgInFloatSSEReg,
 485         ArgInDoubleSSEReg,
 486         ArgOnStack,
 487         ArgValuetypeInReg,
 488         ArgValuetypeAddrInIReg,
 489         /* gsharedvt argument passed by addr */
 490         ArgGSharedVtInReg,
 491         ArgGSharedVtOnStack,
 492         ArgNone /* only in pair_storage */
 493 } ArgStorage;
 494
 495 typedef struct {
 496         gint16 offset;
 497         gint8  reg;
 498         ArgStorage storage;
 499
 500         /* Only if storage == ArgValuetypeInReg */
 501         ArgStorage pair_storage [2];
 502         gint8 pair_regs [2];
 503         /* The size of each pair */
 504         int pair_size [2];
 505         int nregs;
 506 } ArgInfo;
 507
 508 typedef struct {
 509         int nargs;
 510         guint32 stack_usage;
 511         guint32 reg_usage;
 512         guint32 freg_usage;
 513         gboolean need_stack_align;
 514         /* The index of the vret arg in the argument list */
 515         int vret_arg_index;
 516         ArgInfo ret;
 517         ArgInfo sig_cookie;
 518         ArgInfo args [1];
 519 } CallInfo;
 520
 521 #define DEBUG(a) if (cfg->verbose_level > 1) a
 522
 523 #ifdef TARGET_WIN32
 524 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 525
 526 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 527 #else
 528 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 529
 530  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 531 #endif
 532
 533 static void inline
 534 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 535 {
 536     ainfo->offset = *stack_size;
 537
 538     if (*gr >= PARAM_REGS) {
 539                 ainfo->storage = ArgOnStack;
 540                 /* Since the same stack slot size is used for all arg */
 541                 /*  types, it needs to be big enough to hold them all */
 542                 (*stack_size) += sizeof(mgreg_t);
 543     }
 544     else {
 545                 ainfo->storage = ArgInIReg;
 546                 ainfo->reg = param_regs [*gr];
 547                 (*gr) ++;
 548     }
 549 }
 550
 551 #ifdef TARGET_WIN32
 552 #define FLOAT_PARAM_REGS 4
 553 #else
 554 #define FLOAT_PARAM_REGS 8
 555 #endif
 556
 557 static void inline
 558 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 559 {
 560     ainfo->offset = *stack_size;
 561
 562     if (*gr >= FLOAT_PARAM_REGS) {
 563                 ainfo->storage = ArgOnStack;
 564                 /* Since the same stack slot size is used for both float */
 565                 /*  types, it needs to be big enough to hold them both */
 566                 (*stack_size) += sizeof(mgreg_t);
 567     }
 568     else {
 569                 /* A double register */
 570                 if (is_double)
 571                         ainfo->storage = ArgInDoubleSSEReg;
 572                 else
 573                         ainfo->storage = ArgInFloatSSEReg;
 574                 ainfo->reg = *gr;
 575                 (*gr) += 1;
 576     }
 577 }
 578
 579 typedef enum ArgumentClass {
 580         ARG_CLASS_NO_CLASS,
 581         ARG_CLASS_MEMORY,
 582         ARG_CLASS_INTEGER,
 583         ARG_CLASS_SSE
 584 } ArgumentClass;
 585
 586 static ArgumentClass
 587 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 588 {
 589         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 590         MonoType *ptype;
 591
 592         ptype = mini_get_underlying_type (type);
 593         switch (ptype->type) {
 594         case MONO_TYPE_I1:
 595         case MONO_TYPE_U1:
 596         case MONO_TYPE_I2:
 597         case MONO_TYPE_U2:
 598         case MONO_TYPE_I4:
 599         case MONO_TYPE_U4:
 600         case MONO_TYPE_I:
 601         case MONO_TYPE_U:
 602         case MONO_TYPE_STRING:
 603         case MONO_TYPE_OBJECT:
 604         case MONO_TYPE_CLASS:
 605         case MONO_TYPE_SZARRAY:
 606         case MONO_TYPE_PTR:
 607         case MONO_TYPE_FNPTR:
 608         case MONO_TYPE_ARRAY:
 609         case MONO_TYPE_I8:
 610         case MONO_TYPE_U8:
 611                 class2 = ARG_CLASS_INTEGER;
 612                 break;
 613         case MONO_TYPE_R4:
 614         case MONO_TYPE_R8:
 615 #ifdef TARGET_WIN32
 616                 class2 = ARG_CLASS_INTEGER;
 617 #else
 618                 class2 = ARG_CLASS_SSE;
 619 #endif
 620                 break;
 621
 622         case MONO_TYPE_TYPEDBYREF:
 623                 g_assert_not_reached ();
 624
 625         case MONO_TYPE_GENERICINST:
 626                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 627                         class2 = ARG_CLASS_INTEGER;
 628                         break;
 629                 }
 630                 /* fall through */
 631         case MONO_TYPE_VALUETYPE: {
 632                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 633                 int i;
 634
 635                 for (i = 0; i < info->num_fields; ++i) {
 636                         class2 = class1;
 637                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 638                 }
 639                 break;
 640         }
 641         default:
 642                 g_assert_not_reached ();
 643         }
 644
 645         /* Merge */
 646         if (class1 == class2)
 647                 ;
 648         else if (class1 == ARG_CLASS_NO_CLASS)
 649                 class1 = class2;
 650         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 651                 class1 = ARG_CLASS_MEMORY;
 652         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 653                 class1 = ARG_CLASS_INTEGER;
 654         else
 655                 class1 = ARG_CLASS_SSE;
 656
 657         return class1;
 658 }
 659 #ifdef __native_client_codegen__
 660
 661 /* Default alignment for Native Client is 32-byte. */
 662 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 663
 664 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 665 /* Check that alignment doesn't cross an alignment boundary.             */
 666 guint8*
 667 mono_arch_nacl_pad(guint8 *code, int pad)
 668 {
 669         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 670
 671         if (pad == 0) return code;
 672         /* assertion: alignment cannot cross a block boundary */
 673         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 674                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 675         while (pad >= kMaxPadding) {
 676                 amd64_padding (code, kMaxPadding);
 677                 pad -= kMaxPadding;
 678         }
 679         if (pad != 0) amd64_padding (code, pad);
 680         return code;
 681 }
 682 #endif
 683
 684 static int
 685 count_fields_nested (MonoClass *klass)
 686 {
 687         MonoMarshalType *info;
 688         int i, count;
 689
 690         info = mono_marshal_load_type_info (klass);
 691         g_assert(info);
 692         count = 0;
 693         for (i = 0; i < info->num_fields; ++i) {
 694                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 695                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 696                 else
 697                         count ++;
 698         }
 699         return count;
 700 }
 701
 702 static int
 703 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 704 {
 705         MonoMarshalType *info;
 706         int i;
 707
 708         info = mono_marshal_load_type_info (klass);
 709         g_assert(info);
 710         for (i = 0; i < info->num_fields; ++i) {
 711                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 712                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 713                 } else {
 714                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 715                         fields [index].offset += offset;
 716                         index ++;
 717                 }
 718         }
 719         return index;
 720 }
 721
 722 #ifdef TARGET_WIN32
 723 static void
 724 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 725                                          gboolean is_return,
 726                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 727 {
 728         guint32 size, i, nfields;
 729         guint32 argsize = 8;
 730         ArgumentClass arg_class;
 731         MonoMarshalType *info = NULL;
 732         MonoMarshalField *fields = NULL;
 733         MonoClass *klass;
 734         gboolean pass_on_stack = FALSE;
 735
 736         klass = mono_class_from_mono_type (type);
 737         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 738         if (!sig->pinvoke)
 739                 pass_on_stack = TRUE;
 740
 741         /* If this struct can't be split up naturally into 8-byte */
 742         /* chunks (registers), pass it on the stack.              */
 743         if (sig->pinvoke && !pass_on_stack) {
 744                 guint32 align;
 745                 guint32 field_size;
 746
 747                 info = mono_marshal_load_type_info (klass);
 748                 g_assert (info);
 749
 750                 /*
 751                  * Collect field information recursively to be able to
 752                  * handle nested structures.
 753                  */
 754                 nfields = count_fields_nested (klass);
 755                 fields = g_new0 (MonoMarshalField, nfields);
 756                 collect_field_info_nested (klass, fields, 0, 0);
 757
 758                 for (i = 0; i < nfields; ++i) {
 759                         field_size = mono_marshal_type_size (fields [i].field->type,
 760                                                            fields [i].mspec,
 761                                                            &align, TRUE, klass->unicode);
 762                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 763                                 pass_on_stack = TRUE;
 764                                 break;
 765                         }
 766                 }
 767         }
 768
 769         if (pass_on_stack) {
 770                 /* Allways pass in memory */
 771                 ainfo->offset = *stack_size;
 772                 *stack_size += ALIGN_TO (size, 8);
 773                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 774
 775                 g_free (fields);
 776                 return;
 777         }
 778
 779         if (!sig->pinvoke) {
 780                 int n = mono_class_value_size (klass, NULL);
 781
 782                 argsize = n;
 783
 784                 if (n > 8)
 785                         arg_class = ARG_CLASS_MEMORY;
 786                 else
 787                         /* Always pass in 1 integer register */
 788                         arg_class = ARG_CLASS_INTEGER;
 789         } else {
 790                 g_assert (info);
 791
 792                 if (!fields) {
 793                         ainfo->storage = ArgValuetypeInReg;
 794                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 795                         return;
 796                 }
 797
 798                 switch (info->native_size) {
 799                 case 1: case 2: case 4: case 8:
 800                         break;
 801                 default:
 802                         if (is_return) {
 803                                 ainfo->storage = ArgValuetypeAddrInIReg;
 804                                 ainfo->offset = *stack_size;
 805                                 *stack_size += ALIGN_TO (info->native_size, 8);
 806                         }
 807                         else {
 808                                 ainfo->storage = ArgValuetypeAddrInIReg;
 809
 810                                 if (*gr < PARAM_REGS) {
 811                                         ainfo->pair_storage [0] = ArgInIReg;
 812                                         ainfo->pair_regs [0] = param_regs [*gr];
 813                                         (*gr) ++;
 814                                 }
 815                                 else {
 816                                         ainfo->pair_storage [0] = ArgOnStack;
 817                                         ainfo->offset = *stack_size;
 818                                         *stack_size += 8;
 819                                 }
 820                         }
 821
 822                         g_free (fields);
 823                         return;
 824                 }
 825
 826                 int size;
 827                 guint32 align;
 828                 ArgumentClass class1;
 829
 830                 if (nfields == 0)
 831                         class1 = ARG_CLASS_MEMORY;
 832                 else
 833                         class1 = ARG_CLASS_NO_CLASS;
 834                 for (i = 0; i < nfields; ++i) {
 835                         size = mono_marshal_type_size (fields [i].field->type,
 836                                                                                    fields [i].mspec,
 837                                                                                    &align, TRUE, klass->unicode);
 838                         /* How far into this quad this data extends.*/
 839                         /* (8 is size of quad) */
 840                         argsize = fields [i].offset + size;
 841
 842                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 843                 }
 844                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 845                 arg_class = class1;
 846         }
 847
 848         g_free (fields);
 849
 850         /* Allocate registers */
 851         {
 852                 int orig_gr = *gr;
 853                 int orig_fr = *fr;
 854
 855                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 856                         argsize ++;
 857
 858                 ainfo->storage = ArgValuetypeInReg;
 859                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 860                 ainfo->pair_size [0] = argsize;
 861                 ainfo->pair_size [1] = 0;
 862                 ainfo->nregs = 1;
 863                 switch (arg_class) {
 864                 case ARG_CLASS_INTEGER:
 865                         if (*gr >= PARAM_REGS)
 866                                 arg_class = ARG_CLASS_MEMORY;
 867                         else {
 868                                 ainfo->pair_storage [0] = ArgInIReg;
 869                                 if (is_return)
 870                                         ainfo->pair_regs [0] = return_regs [*gr];
 871                                 else
 872                                         ainfo->pair_regs [0] = param_regs [*gr];
 873                                 (*gr) ++;
 874                         }
 875                         break;
 876                 case ARG_CLASS_SSE:
 877                         if (*fr >= FLOAT_PARAM_REGS)
 878                                 arg_class = ARG_CLASS_MEMORY;
 879                         else {
 880                                 if (argsize <= 4)
 881                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 882                                 else
 883                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 884                                 ainfo->pair_regs [0] = *fr;
 885                                 (*fr) ++;
 886                         }
 887                         break;
 888                 case ARG_CLASS_MEMORY:
 889                         break;
 890                 default:
 891                         g_assert_not_reached ();
 892                 }
 893
 894                 if (arg_class == ARG_CLASS_MEMORY) {
 895                         /* Revert possible register assignments */
 896                         *gr = orig_gr;
 897                         *fr = orig_fr;
 898
 899                         ainfo->offset = *stack_size;
 900                         *stack_size += sizeof (mgreg_t);
 901                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 902                 }
 903         }
 904 }
 905 #endif /* TARGET_WIN32 */
 906
 907 static void
 908 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 909                            gboolean is_return,
 910                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 911 {
 912 #ifdef TARGET_WIN32
 913         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 914 #else
 915         guint32 size, quad, nquads, i, nfields;
 916         /* Keep track of the size used in each quad so we can */
 917         /* use the right size when copying args/return vars.  */
 918         guint32 quadsize [2] = {8, 8};
 919         ArgumentClass args [2];
 920         MonoMarshalType *info = NULL;
 921         MonoMarshalField *fields = NULL;
 922         MonoClass *klass;
 923         gboolean pass_on_stack = FALSE;
 924
 925         klass = mono_class_from_mono_type (type);
 926         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 927         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 928                 /* We pass and return vtypes of size 8 in a register */
 929         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 930                 pass_on_stack = TRUE;
 931         }
 932
 933         /* If this struct can't be split up naturally into 8-byte */
 934         /* chunks (registers), pass it on the stack.              */
 935         if (sig->pinvoke && !pass_on_stack) {
 936                 guint32 align;
 937                 guint32 field_size;
 938
 939                 info = mono_marshal_load_type_info (klass);
 940                 g_assert (info);
 941
 942                 /*
 943                  * Collect field information recursively to be able to
 944                  * handle nested structures.
 945                  */
 946                 nfields = count_fields_nested (klass);
 947                 fields = g_new0 (MonoMarshalField, nfields);
 948                 collect_field_info_nested (klass, fields, 0, 0);
 949
 950                 for (i = 0; i < nfields; ++i) {
 951                         field_size = mono_marshal_type_size (fields [i].field->type,
 952                                                            fields [i].mspec,
 953                                                            &align, TRUE, klass->unicode);
 954                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 955                                 pass_on_stack = TRUE;
 956                                 break;
 957                         }
 958                 }
 959         }
 960
 961         if (size == 0) {
 962                 ainfo->storage = ArgValuetypeInReg;
 963                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 964                 return;
 965         }
 966
 967         if (pass_on_stack) {
 968                 /* Allways pass in memory */
 969                 ainfo->offset = *stack_size;
 970                 *stack_size += ALIGN_TO (size, 8);
 971                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 972
 973                 g_free (fields);
 974                 return;
 975         }
 976
 977         if (size > 8)
 978                 nquads = 2;
 979         else
 980                 nquads = 1;
 981
 982         if (!sig->pinvoke) {
 983                 int n = mono_class_value_size (klass, NULL);
 984
 985                 quadsize [0] = n >= 8 ? 8 : n;
 986                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 987
 988                 /* Always pass in 1 or 2 integer registers */
 989                 args [0] = ARG_CLASS_INTEGER;
 990                 args [1] = ARG_CLASS_INTEGER;
 991                 /* Only the simplest cases are supported */
 992                 if (is_return && nquads != 1) {
 993                         args [0] = ARG_CLASS_MEMORY;
 994                         args [1] = ARG_CLASS_MEMORY;
 995                 }
 996         } else {
 997                 /*
 998                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 999                  * The X87 and SSEUP stuff is left out since there are no such types in
1000                  * the CLR.
1001                  */
1002                 g_assert (info);
1003
1004                 if (!fields) {
1005                         ainfo->storage = ArgValuetypeInReg;
1006                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1007                         return;
1008                 }
1009
1010                 if (info->native_size > 16) {
1011                         ainfo->offset = *stack_size;
1012                         *stack_size += ALIGN_TO (info->native_size, 8);
1013                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1014
1015                         g_free (fields);
1016                         return;
1017                 }
1018
1019                 args [0] = ARG_CLASS_NO_CLASS;
1020                 args [1] = ARG_CLASS_NO_CLASS;
1021                 for (quad = 0; quad < nquads; ++quad) {
1022                         int size;
1023                         guint32 align;
1024                         ArgumentClass class1;
1025
1026                         if (nfields == 0)
1027                                 class1 = ARG_CLASS_MEMORY;
1028                         else
1029                                 class1 = ARG_CLASS_NO_CLASS;
1030                         for (i = 0; i < nfields; ++i) {
1031                                 size = mono_marshal_type_size (fields [i].field->type,
1032                                                                                            fields [i].mspec,
1033                                                                                            &align, TRUE, klass->unicode);
1034                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
1035                                         /* Unaligned field */
1036                                         NOT_IMPLEMENTED;
1037                                 }
1038
1039                                 /* Skip fields in other quad */
1040                                 if ((quad == 0) && (fields [i].offset >= 8))
1041                                         continue;
1042                                 if ((quad == 1) && (fields [i].offset < 8))
1043                                         continue;
1044
1045                                 /* How far into this quad this data extends.*/
1046                                 /* (8 is size of quad) */
1047                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
1048
1049                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1050                         }
1051                         g_assert (class1 != ARG_CLASS_NO_CLASS);
1052                         args [quad] = class1;
1053                 }
1054         }
1055
1056         g_free (fields);
1057
1058         /* Post merger cleanup */
1059         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1060                 args [0] = args [1] = ARG_CLASS_MEMORY;
1061
1062         /* Allocate registers */
1063         {
1064                 int orig_gr = *gr;
1065                 int orig_fr = *fr;
1066
1067                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1068                         quadsize [0] ++;
1069                 while (quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1070                         quadsize [1] ++;
1071
1072                 ainfo->storage = ArgValuetypeInReg;
1073                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1074                 g_assert (quadsize [0] <= 8);
1075                 g_assert (quadsize [1] <= 8);
1076                 ainfo->pair_size [0] = quadsize [0];
1077                 ainfo->pair_size [1] = quadsize [1];
1078                 ainfo->nregs = nquads;
1079                 for (quad = 0; quad < nquads; ++quad) {
1080                         switch (args [quad]) {
1081                         case ARG_CLASS_INTEGER:
1082                                 if (*gr >= PARAM_REGS)
1083                                         args [quad] = ARG_CLASS_MEMORY;
1084                                 else {
1085                                         ainfo->pair_storage [quad] = ArgInIReg;
1086                                         if (is_return)
1087                                                 ainfo->pair_regs [quad] = return_regs [*gr];
1088                                         else
1089                                                 ainfo->pair_regs [quad] = param_regs [*gr];
1090                                         (*gr) ++;
1091                                 }
1092                                 break;
1093                         case ARG_CLASS_SSE:
1094                                 if (*fr >= FLOAT_PARAM_REGS)
1095                                         args [quad] = ARG_CLASS_MEMORY;
1096                                 else {
1097                                         if (quadsize[quad] <= 4)
1098                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1099                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1100                                         ainfo->pair_regs [quad] = *fr;
1101                                         (*fr) ++;
1102                                 }
1103                                 break;
1104                         case ARG_CLASS_MEMORY:
1105                                 break;
1106                         default:
1107                                 g_assert_not_reached ();
1108                         }
1109                 }
1110
1111                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1112                         /* Revert possible register assignments */
1113                         *gr = orig_gr;
1114                         *fr = orig_fr;
1115
1116                         ainfo->offset = *stack_size;
1117                         if (sig->pinvoke)
1118                                 *stack_size += ALIGN_TO (info->native_size, 8);
1119                         else
1120                                 *stack_size += nquads * sizeof(mgreg_t);
1121                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1122                 }
1123         }
1124 #endif /* !TARGET_WIN32 */
1125 }
1126
1127 /*
1128  * get_call_info:
1129  *
1130  *  Obtain information about a call according to the calling convention.
1131  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1132  * Draft Version 0.23" document for more information.
1133  */
1134 static CallInfo*
1135 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1136 {
1137         guint32 i, gr, fr, pstart;
1138         MonoType *ret_type;
1139         int n = sig->hasthis + sig->param_count;
1140         guint32 stack_size = 0;
1141         CallInfo *cinfo;
1142         gboolean is_pinvoke = sig->pinvoke;
1143
1144         if (mp)
1145                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1146         else
1147                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1148
1149         cinfo->nargs = n;
1150
1151         gr = 0;
1152         fr = 0;
1153
1154 #ifdef TARGET_WIN32
1155         /* Reserve space where the callee can save the argument registers */
1156         stack_size = 4 * sizeof (mgreg_t);
1157 #endif
1158
1159         /* return value */
1160         ret_type = mini_get_underlying_type (sig->ret);
1161         switch (ret_type->type) {
1162         case MONO_TYPE_I1:
1163         case MONO_TYPE_U1:
1164         case MONO_TYPE_I2:
1165         case MONO_TYPE_U2:
1166         case MONO_TYPE_I4:
1167         case MONO_TYPE_U4:
1168         case MONO_TYPE_I:
1169         case MONO_TYPE_U:
1170         case MONO_TYPE_PTR:
1171         case MONO_TYPE_FNPTR:
1172         case MONO_TYPE_CLASS:
1173         case MONO_TYPE_OBJECT:
1174         case MONO_TYPE_SZARRAY:
1175         case MONO_TYPE_ARRAY:
1176         case MONO_TYPE_STRING:
1177                 cinfo->ret.storage = ArgInIReg;
1178                 cinfo->ret.reg = AMD64_RAX;
1179                 break;
1180         case MONO_TYPE_U8:
1181         case MONO_TYPE_I8:
1182                 cinfo->ret.storage = ArgInIReg;
1183                 cinfo->ret.reg = AMD64_RAX;
1184                 break;
1185         case MONO_TYPE_R4:
1186                 cinfo->ret.storage = ArgInFloatSSEReg;
1187                 cinfo->ret.reg = AMD64_XMM0;
1188                 break;
1189         case MONO_TYPE_R8:
1190                 cinfo->ret.storage = ArgInDoubleSSEReg;
1191                 cinfo->ret.reg = AMD64_XMM0;
1192                 break;
1193         case MONO_TYPE_GENERICINST:
1194                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1195                         cinfo->ret.storage = ArgInIReg;
1196                         cinfo->ret.reg = AMD64_RAX;
1197                         break;
1198                 }
1199                 if (mini_is_gsharedvt_type (ret_type)) {
1200                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1201                         break;
1202                 }
1203                 /* fall through */
1204         case MONO_TYPE_VALUETYPE:
1205         case MONO_TYPE_TYPEDBYREF: {
1206                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1207
1208                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1209                 g_assert (cinfo->ret.storage != ArgInIReg);
1210                 break;
1211         }
1212         case MONO_TYPE_VAR:
1213         case MONO_TYPE_MVAR:
1214                 g_assert (mini_is_gsharedvt_type (ret_type));
1215                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1216                 break;
1217         case MONO_TYPE_VOID:
1218                 break;
1219         default:
1220                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1221         }
1222
1223         pstart = 0;
1224         /*
1225          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1226          * the first argument, allowing 'this' to be always passed in the first arg reg.
1227          * Also do this if the first argument is a reference type, since virtual calls
1228          * are sometimes made using calli without sig->hasthis set, like in the delegate
1229          * invoke wrappers.
1230          */
1231         if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1232                 if (sig->hasthis) {
1233                         add_general (&gr, &stack_size, cinfo->args + 0);
1234                 } else {
1235                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1236                         pstart = 1;
1237                 }
1238                 add_general (&gr, &stack_size, &cinfo->ret);
1239                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1240                 cinfo->vret_arg_index = 1;
1241         } else {
1242                 /* this */
1243                 if (sig->hasthis)
1244                         add_general (&gr, &stack_size, cinfo->args + 0);
1245
1246                 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1247                         add_general (&gr, &stack_size, &cinfo->ret);
1248                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1249                 }
1250         }
1251
1252         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1253                 gr = PARAM_REGS;
1254                 fr = FLOAT_PARAM_REGS;
1255
1256                 /* Emit the signature cookie just before the implicit arguments */
1257                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1258         }
1259
1260         for (i = pstart; i < sig->param_count; ++i) {
1261                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1262                 MonoType *ptype;
1263
1264 #ifdef TARGET_WIN32
1265                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1266                 if (gr > fr)
1267                         fr = gr;
1268                 else if (fr > gr)
1269                         gr = fr;
1270 #endif
1271
1272                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1273                         /* We allways pass the sig cookie on the stack for simplicity */
1274                         /*
1275                          * Prevent implicit arguments + the sig cookie from being passed
1276                          * in registers.
1277                          */
1278                         gr = PARAM_REGS;
1279                         fr = FLOAT_PARAM_REGS;
1280
1281                         /* Emit the signature cookie just before the implicit arguments */
1282                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1283                 }
1284
1285                 ptype = mini_get_underlying_type (sig->params [i]);
1286                 switch (ptype->type) {
1287                 case MONO_TYPE_I1:
1288                 case MONO_TYPE_U1:
1289                         add_general (&gr, &stack_size, ainfo);
1290                         break;
1291                 case MONO_TYPE_I2:
1292                 case MONO_TYPE_U2:
1293                         add_general (&gr, &stack_size, ainfo);
1294                         break;
1295                 case MONO_TYPE_I4:
1296                 case MONO_TYPE_U4:
1297                         add_general (&gr, &stack_size, ainfo);
1298                         break;
1299                 case MONO_TYPE_I:
1300                 case MONO_TYPE_U:
1301                 case MONO_TYPE_PTR:
1302                 case MONO_TYPE_FNPTR:
1303                 case MONO_TYPE_CLASS:
1304                 case MONO_TYPE_OBJECT:
1305                 case MONO_TYPE_STRING:
1306                 case MONO_TYPE_SZARRAY:
1307                 case MONO_TYPE_ARRAY:
1308                         add_general (&gr, &stack_size, ainfo);
1309                         break;
1310                 case MONO_TYPE_GENERICINST:
1311                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1312                                 add_general (&gr, &stack_size, ainfo);
1313                                 break;
1314                         }
1315                         if (mini_is_gsharedvt_type (ptype)) {
1316                                 /* gsharedvt arguments are passed by ref */
1317                                 add_general (&gr, &stack_size, ainfo);
1318                                 if (ainfo->storage == ArgInIReg)
1319                                         ainfo->storage = ArgGSharedVtInReg;
1320                                 else
1321                                         ainfo->storage = ArgGSharedVtOnStack;
1322                                 break;
1323                         }
1324                         /* fall through */
1325                 case MONO_TYPE_VALUETYPE:
1326                 case MONO_TYPE_TYPEDBYREF:
1327                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1328                         break;
1329                 case MONO_TYPE_U8:
1330
1331                 case MONO_TYPE_I8:
1332                         add_general (&gr, &stack_size, ainfo);
1333                         break;
1334                 case MONO_TYPE_R4:
1335                         add_float (&fr, &stack_size, ainfo, FALSE);
1336                         break;
1337                 case MONO_TYPE_R8:
1338                         add_float (&fr, &stack_size, ainfo, TRUE);
1339                         break;
1340                 case MONO_TYPE_VAR:
1341                 case MONO_TYPE_MVAR:
1342                         /* gsharedvt arguments are passed by ref */
1343                         g_assert (mini_is_gsharedvt_type (ptype));
1344                         add_general (&gr, &stack_size, ainfo);
1345                         if (ainfo->storage == ArgInIReg)
1346                                 ainfo->storage = ArgGSharedVtInReg;
1347                         else
1348                                 ainfo->storage = ArgGSharedVtOnStack;
1349                         break;
1350                 default:
1351                         g_assert_not_reached ();
1352                 }
1353         }
1354
1355         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1356                 gr = PARAM_REGS;
1357                 fr = FLOAT_PARAM_REGS;
1358
1359                 /* Emit the signature cookie just before the implicit arguments */
1360                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1361         }
1362
1363         cinfo->stack_usage = stack_size;
1364         cinfo->reg_usage = gr;
1365         cinfo->freg_usage = fr;
1366         return cinfo;
1367 }
1368
1369 /*
1370  * mono_arch_get_argument_info:
1371  * @csig:  a method signature
1372  * @param_count: the number of parameters to consider
1373  * @arg_info: an array to store the result infos
1374  *
1375  * Gathers information on parameters such as size, alignment and
1376  * padding. arg_info should be large enought to hold param_count + 1 entries.
1377  *
1378  * Returns the size of the argument area on the stack.
1379  */
1380 int
1381 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1382 {
1383         int k;
1384         CallInfo *cinfo = get_call_info (NULL, csig);
1385         guint32 args_size = cinfo->stack_usage;
1386
1387         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1388         if (csig->hasthis) {
1389                 arg_info [0].offset = 0;
1390         }
1391
1392         for (k = 0; k < param_count; k++) {
1393                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1394                 /* FIXME: */
1395                 arg_info [k + 1].size = 0;
1396         }
1397
1398         g_free (cinfo);
1399
1400         return args_size;
1401 }
1402
1403 gboolean
1404 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1405 {
1406         CallInfo *c1, *c2;
1407         gboolean res;
1408         MonoType *callee_ret;
1409
1410         c1 = get_call_info (NULL, caller_sig);
1411         c2 = get_call_info (NULL, callee_sig);
1412         res = c1->stack_usage >= c2->stack_usage;
1413         callee_ret = mini_get_underlying_type (callee_sig->ret);
1414         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1415                 /* An address on the callee's stack is passed as the first argument */
1416                 res = FALSE;
1417
1418         g_free (c1);
1419         g_free (c2);
1420
1421         return res;
1422 }
1423
1424 /*
1425  * Initialize the cpu to execute managed code.
1426  */
1427 void
1428 mono_arch_cpu_init (void)
1429 {
1430 #ifndef _MSC_VER
1431         guint16 fpcw;
1432
1433         /* spec compliance requires running with double precision */
1434         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1435         fpcw &= ~X86_FPCW_PRECC_MASK;
1436         fpcw |= X86_FPCW_PREC_DOUBLE;
1437         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1438         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1439 #else
1440         /* TODO: This is crashing on Win64 right now.
1441         * _control87 (_PC_53, MCW_PC);
1442         */
1443 #endif
1444 }
1445
1446 /*
1447  * Initialize architecture specific code.
1448  */
1449 void
1450 mono_arch_init (void)
1451 {
1452         mono_os_mutex_init_recursive (&mini_arch_mutex);
1453 #if defined(__native_client_codegen__)
1454         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1455         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1456         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1457         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1458 #endif
1459
1460         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1461         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1462         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1463         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1464
1465         if (!mono_aot_only)
1466                 bp_trampoline = mini_get_breakpoint_trampoline ();
1467 }
1468
1469 /*
1470  * Cleanup architecture specific code.
1471  */
1472 void
1473 mono_arch_cleanup (void)
1474 {
1475         mono_os_mutex_destroy (&mini_arch_mutex);
1476 #if defined(__native_client_codegen__)
1477         mono_native_tls_free (nacl_instruction_depth);
1478         mono_native_tls_free (nacl_rex_tag);
1479         mono_native_tls_free (nacl_legacy_prefix_tag);
1480 #endif
1481 }
1482
1483 /*
1484  * This function returns the optimizations supported on this cpu.
1485  */
1486 guint32
1487 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1488 {
1489         guint32 opts = 0;
1490
1491         *exclude_mask = 0;
1492
1493         if (mono_hwcap_x86_has_cmov) {
1494                 opts |= MONO_OPT_CMOV;
1495
1496                 if (mono_hwcap_x86_has_fcmov)
1497                         opts |= MONO_OPT_FCMOV;
1498                 else
1499                         *exclude_mask |= MONO_OPT_FCMOV;
1500         } else {
1501                 *exclude_mask |= MONO_OPT_CMOV;
1502         }
1503
1504         return opts;
1505 }
1506
1507 /*
1508  * This function test for all SSE functions supported.
1509  *
1510  * Returns a bitmask corresponding to all supported versions.
1511  *
1512  */
1513 guint32
1514 mono_arch_cpu_enumerate_simd_versions (void)
1515 {
1516         guint32 sse_opts = 0;
1517
1518         if (mono_hwcap_x86_has_sse1)
1519                 sse_opts |= SIMD_VERSION_SSE1;
1520
1521         if (mono_hwcap_x86_has_sse2)
1522                 sse_opts |= SIMD_VERSION_SSE2;
1523
1524         if (mono_hwcap_x86_has_sse3)
1525                 sse_opts |= SIMD_VERSION_SSE3;
1526
1527         if (mono_hwcap_x86_has_ssse3)
1528                 sse_opts |= SIMD_VERSION_SSSE3;
1529
1530         if (mono_hwcap_x86_has_sse41)
1531                 sse_opts |= SIMD_VERSION_SSE41;
1532
1533         if (mono_hwcap_x86_has_sse42)
1534                 sse_opts |= SIMD_VERSION_SSE42;
1535
1536         if (mono_hwcap_x86_has_sse4a)
1537                 sse_opts |= SIMD_VERSION_SSE4a;
1538
1539         return sse_opts;
1540 }
1541
1542 #ifndef DISABLE_JIT
1543
1544 GList *
1545 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1546 {
1547         GList *vars = NULL;
1548         int i;
1549
1550         for (i = 0; i < cfg->num_varinfo; i++) {
1551                 MonoInst *ins = cfg->varinfo [i];
1552                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1553
1554                 /* unused vars */
1555                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1556                         continue;
1557
1558                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1559                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1560                         continue;
1561
1562                 if (mono_is_regsize_var (ins->inst_vtype)) {
1563                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1564                         g_assert (i == vmv->idx);
1565                         vars = g_list_prepend (vars, vmv);
1566                 }
1567         }
1568
1569         vars = mono_varlist_sort (cfg, vars, 0);
1570
1571         return vars;
1572 }
1573
1574 /**
1575  * mono_arch_compute_omit_fp:
1576  *
1577  *   Determine whenever the frame pointer can be eliminated.
1578  */
1579 static void
1580 mono_arch_compute_omit_fp (MonoCompile *cfg)
1581 {
1582         MonoMethodSignature *sig;
1583         MonoMethodHeader *header;
1584         int i, locals_size;
1585         CallInfo *cinfo;
1586
1587         if (cfg->arch.omit_fp_computed)
1588                 return;
1589
1590         header = cfg->header;
1591
1592         sig = mono_method_signature (cfg->method);
1593
1594         if (!cfg->arch.cinfo)
1595                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1596         cinfo = (CallInfo *)cfg->arch.cinfo;
1597
1598         /*
1599          * FIXME: Remove some of the restrictions.
1600          */
1601         cfg->arch.omit_fp = TRUE;
1602         cfg->arch.omit_fp_computed = TRUE;
1603
1604 #ifdef __native_client_codegen__
1605         /* NaCl modules may not change the value of RBP, so it cannot be */
1606         /* used as a normal register, but it can be used as a frame pointer*/
1607         cfg->disable_omit_fp = TRUE;
1608         cfg->arch.omit_fp = FALSE;
1609 #endif
1610
1611         if (cfg->disable_omit_fp)
1612                 cfg->arch.omit_fp = FALSE;
1613
1614         if (!debug_omit_fp ())
1615                 cfg->arch.omit_fp = FALSE;
1616         /*
1617         if (cfg->method->save_lmf)
1618                 cfg->arch.omit_fp = FALSE;
1619         */
1620         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1621                 cfg->arch.omit_fp = FALSE;
1622         if (header->num_clauses)
1623                 cfg->arch.omit_fp = FALSE;
1624         if (cfg->param_area)
1625                 cfg->arch.omit_fp = FALSE;
1626         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1627                 cfg->arch.omit_fp = FALSE;
1628         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1629                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1630                 cfg->arch.omit_fp = FALSE;
1631         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1632                 ArgInfo *ainfo = &cinfo->args [i];
1633
1634                 if (ainfo->storage == ArgOnStack) {
1635                         /*
1636                          * The stack offset can only be determined when the frame
1637                          * size is known.
1638                          */
1639                         cfg->arch.omit_fp = FALSE;
1640                 }
1641         }
1642
1643         locals_size = 0;
1644         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1645                 MonoInst *ins = cfg->varinfo [i];
1646                 int ialign;
1647
1648                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1649         }
1650 }
1651
1652 GList *
1653 mono_arch_get_global_int_regs (MonoCompile *cfg)
1654 {
1655         GList *regs = NULL;
1656
1657         mono_arch_compute_omit_fp (cfg);
1658
1659         if (cfg->arch.omit_fp)
1660                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1661
1662         /* We use the callee saved registers for global allocation */
1663         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1664         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1665         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1666         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1667 #ifndef __native_client_codegen__
1668         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1669 #endif
1670 #ifdef TARGET_WIN32
1671         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1672         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1673 #endif
1674
1675         return regs;
1676 }
1677
1678 GList*
1679 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1680 {
1681         GList *regs = NULL;
1682         int i;
1683
1684         /* All XMM registers */
1685         for (i = 0; i < 16; ++i)
1686                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1687
1688         return regs;
1689 }
1690
1691 GList*
1692 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1693 {
1694         static GList *r = NULL;
1695
1696         if (r == NULL) {
1697                 GList *regs = NULL;
1698
1699                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1700                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1701                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1702                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1703                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1704 #ifndef __native_client_codegen__
1705                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1706 #endif
1707
1708                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1709                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1710                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1711                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1712                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1713                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1714                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1715                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1716
1717                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1718         }
1719
1720         return r;
1721 }
1722
1723 GList*
1724 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1725 {
1726         int i;
1727         static GList *r = NULL;
1728
1729         if (r == NULL) {
1730                 GList *regs = NULL;
1731
1732                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1733                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1734
1735                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1736         }
1737
1738         return r;
1739 }
1740
1741 /*
1742  * mono_arch_regalloc_cost:
1743  *
1744  *  Return the cost, in number of memory references, of the action of
1745  * allocating the variable VMV into a register during global register
1746  * allocation.
1747  */
1748 guint32
1749 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1750 {
1751         MonoInst *ins = cfg->varinfo [vmv->idx];
1752
1753         if (cfg->method->save_lmf)
1754                 /* The register is already saved */
1755                 /* substract 1 for the invisible store in the prolog */
1756                 return (ins->opcode == OP_ARG) ? 0 : 1;
1757         else
1758                 /* push+pop */
1759                 return (ins->opcode == OP_ARG) ? 1 : 2;
1760 }
1761
1762 /*
1763  * mono_arch_fill_argument_info:
1764  *
1765  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1766  * of the method.
1767  */
1768 void
1769 mono_arch_fill_argument_info (MonoCompile *cfg)
1770 {
1771         MonoType *sig_ret;
1772         MonoMethodSignature *sig;
1773         MonoInst *ins;
1774         int i;
1775         CallInfo *cinfo;
1776
1777         sig = mono_method_signature (cfg->method);
1778
1779         cinfo = (CallInfo *)cfg->arch.cinfo;
1780         sig_ret = mini_get_underlying_type (sig->ret);
1781
1782         /*
1783          * Contrary to mono_arch_allocate_vars (), the information should describe
1784          * where the arguments are at the beginning of the method, not where they can be
1785          * accessed during the execution of the method. The later makes no sense for the
1786          * global register allocator, since a variable can be in more than one location.
1787          */
1788         switch (cinfo->ret.storage) {
1789         case ArgInIReg:
1790         case ArgInFloatSSEReg:
1791         case ArgInDoubleSSEReg:
1792                 cfg->ret->opcode = OP_REGVAR;
1793                 cfg->ret->inst_c0 = cinfo->ret.reg;
1794                 break;
1795         case ArgValuetypeInReg:
1796                 cfg->ret->opcode = OP_REGOFFSET;
1797                 cfg->ret->inst_basereg = -1;
1798                 cfg->ret->inst_offset = -1;
1799                 break;
1800         case ArgNone:
1801                 break;
1802         default:
1803                 g_assert_not_reached ();
1804         }
1805
1806         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1807                 ArgInfo *ainfo = &cinfo->args [i];
1808
1809                 ins = cfg->args [i];
1810
1811                 switch (ainfo->storage) {
1812                 case ArgInIReg:
1813                 case ArgInFloatSSEReg:
1814                 case ArgInDoubleSSEReg:
1815                         ins->opcode = OP_REGVAR;
1816                         ins->inst_c0 = ainfo->reg;
1817                         break;
1818                 case ArgOnStack:
1819                         ins->opcode = OP_REGOFFSET;
1820                         ins->inst_basereg = -1;
1821                         ins->inst_offset = -1;
1822                         break;
1823                 case ArgValuetypeInReg:
1824                         /* Dummy */
1825                         ins->opcode = OP_NOP;
1826                         break;
1827                 default:
1828                         g_assert_not_reached ();
1829                 }
1830         }
1831 }
1832
1833 void
1834 mono_arch_allocate_vars (MonoCompile *cfg)
1835 {
1836         MonoType *sig_ret;
1837         MonoMethodSignature *sig;
1838         MonoInst *ins;
1839         int i, offset;
1840         guint32 locals_stack_size, locals_stack_align;
1841         gint32 *offsets;
1842         CallInfo *cinfo;
1843
1844         sig = mono_method_signature (cfg->method);
1845
1846         cinfo = (CallInfo *)cfg->arch.cinfo;
1847         sig_ret = mini_get_underlying_type (sig->ret);
1848
1849         mono_arch_compute_omit_fp (cfg);
1850
1851         /*
1852          * We use the ABI calling conventions for managed code as well.
1853          * Exception: valuetypes are only sometimes passed or returned in registers.
1854          */
1855
1856         /*
1857          * The stack looks like this:
1858          * <incoming arguments passed on the stack>
1859          * <return value>
1860          * <lmf/caller saved registers>
1861          * <locals>
1862          * <spill area>
1863          * <localloc area>  -> grows dynamically
1864          * <params area>
1865          */
1866
1867         if (cfg->arch.omit_fp) {
1868                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1869                 cfg->frame_reg = AMD64_RSP;
1870                 offset = 0;
1871         } else {
1872                 /* Locals are allocated backwards from %fp */
1873                 cfg->frame_reg = AMD64_RBP;
1874                 offset = 0;
1875         }
1876
1877         cfg->arch.saved_iregs = cfg->used_int_regs;
1878         if (cfg->method->save_lmf)
1879                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1880                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1881
1882         if (cfg->arch.omit_fp)
1883                 cfg->arch.reg_save_area_offset = offset;
1884         /* Reserve space for callee saved registers */
1885         for (i = 0; i < AMD64_NREG; ++i)
1886                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1887                         offset += sizeof(mgreg_t);
1888                 }
1889         if (!cfg->arch.omit_fp)
1890                 cfg->arch.reg_save_area_offset = -offset;
1891
1892         if (sig_ret->type != MONO_TYPE_VOID) {
1893                 switch (cinfo->ret.storage) {
1894                 case ArgInIReg:
1895                 case ArgInFloatSSEReg:
1896                 case ArgInDoubleSSEReg:
1897                         cfg->ret->opcode = OP_REGVAR;
1898                         cfg->ret->inst_c0 = cinfo->ret.reg;
1899                         break;
1900                 case ArgValuetypeAddrInIReg:
1901                         /* The register is volatile */
1902                         cfg->vret_addr->opcode = OP_REGOFFSET;
1903                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1904                         if (cfg->arch.omit_fp) {
1905                                 cfg->vret_addr->inst_offset = offset;
1906                                 offset += 8;
1907                         } else {
1908                                 offset += 8;
1909                                 cfg->vret_addr->inst_offset = -offset;
1910                         }
1911                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1912                                 printf ("vret_addr =");
1913                                 mono_print_ins (cfg->vret_addr);
1914                         }
1915                         break;
1916                 case ArgValuetypeInReg:
1917                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1918                         cfg->ret->opcode = OP_REGOFFSET;
1919                         cfg->ret->inst_basereg = cfg->frame_reg;
1920                         if (cfg->arch.omit_fp) {
1921                                 cfg->ret->inst_offset = offset;
1922                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1923                         } else {
1924                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1925                                 cfg->ret->inst_offset = - offset;
1926                         }
1927                         break;
1928                 default:
1929                         g_assert_not_reached ();
1930                 }
1931                 cfg->ret->dreg = cfg->ret->inst_c0;
1932         }
1933
1934         /* Allocate locals */
1935         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1936         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1937                 char *mname = mono_method_full_name (cfg->method, TRUE);
1938                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1939                 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1940                 g_free (mname);
1941                 return;
1942         }
1943
1944         if (locals_stack_align) {
1945                 offset += (locals_stack_align - 1);
1946                 offset &= ~(locals_stack_align - 1);
1947         }
1948         if (cfg->arch.omit_fp) {
1949                 cfg->locals_min_stack_offset = offset;
1950                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1951         } else {
1952                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1953                 cfg->locals_max_stack_offset = - offset;
1954         }
1955
1956         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1957                 if (offsets [i] != -1) {
1958                         MonoInst *ins = cfg->varinfo [i];
1959                         ins->opcode = OP_REGOFFSET;
1960                         ins->inst_basereg = cfg->frame_reg;
1961                         if (cfg->arch.omit_fp)
1962                                 ins->inst_offset = (offset + offsets [i]);
1963                         else
1964                                 ins->inst_offset = - (offset + offsets [i]);
1965                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1966                 }
1967         }
1968         offset += locals_stack_size;
1969
1970         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1971                 g_assert (!cfg->arch.omit_fp);
1972                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1973                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1974         }
1975
1976         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1977                 ins = cfg->args [i];
1978                 if (ins->opcode != OP_REGVAR) {
1979                         ArgInfo *ainfo = &cinfo->args [i];
1980                         gboolean inreg = TRUE;
1981
1982                         /* FIXME: Allocate volatile arguments to registers */
1983                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1984                                 inreg = FALSE;
1985
1986                         /*
1987                          * Under AMD64, all registers used to pass arguments to functions
1988                          * are volatile across calls.
1989                          * FIXME: Optimize this.
1990                          */
1991                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
1992                                 inreg = FALSE;
1993
1994                         ins->opcode = OP_REGOFFSET;
1995
1996                         switch (ainfo->storage) {
1997                         case ArgInIReg:
1998                         case ArgInFloatSSEReg:
1999                         case ArgInDoubleSSEReg:
2000                         case ArgGSharedVtInReg:
2001                                 if (inreg) {
2002                                         ins->opcode = OP_REGVAR;
2003                                         ins->dreg = ainfo->reg;
2004                                 }
2005                                 break;
2006                         case ArgOnStack:
2007                         case ArgGSharedVtOnStack:
2008                                 g_assert (!cfg->arch.omit_fp);
2009                                 ins->opcode = OP_REGOFFSET;
2010                                 ins->inst_basereg = cfg->frame_reg;
2011                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
2012                                 break;
2013                         case ArgValuetypeInReg:
2014                                 break;
2015                         case ArgValuetypeAddrInIReg: {
2016                                 MonoInst *indir;
2017                                 g_assert (!cfg->arch.omit_fp);
2018
2019                                 MONO_INST_NEW (cfg, indir, 0);
2020                                 indir->opcode = OP_REGOFFSET;
2021                                 if (ainfo->pair_storage [0] == ArgInIReg) {
2022                                         indir->inst_basereg = cfg->frame_reg;
2023                                         offset = ALIGN_TO (offset, sizeof (gpointer));
2024                                         offset += (sizeof (gpointer));
2025                                         indir->inst_offset = - offset;
2026                                 }
2027                                 else {
2028                                         indir->inst_basereg = cfg->frame_reg;
2029                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
2030                                 }
2031
2032                                 ins->opcode = OP_VTARG_ADDR;
2033                                 ins->inst_left = indir;
2034
2035                                 break;
2036                         }
2037                         default:
2038                                 NOT_IMPLEMENTED;
2039                         }
2040
2041                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
2042                                 ins->opcode = OP_REGOFFSET;
2043                                 ins->inst_basereg = cfg->frame_reg;
2044                                 /* These arguments are saved to the stack in the prolog */
2045                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2046                                 if (cfg->arch.omit_fp) {
2047                                         ins->inst_offset = offset;
2048                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2049                                         // Arguments are yet supported by the stack map creation code
2050                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2051                                 } else {
2052                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2053                                         ins->inst_offset = - offset;
2054                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2055                                 }
2056                         }
2057                 }
2058         }
2059
2060         cfg->stack_offset = offset;
2061 }
2062
2063 void
2064 mono_arch_create_vars (MonoCompile *cfg)
2065 {
2066         MonoMethodSignature *sig;
2067         CallInfo *cinfo;
2068         MonoType *sig_ret;
2069
2070         sig = mono_method_signature (cfg->method);
2071
2072         if (!cfg->arch.cinfo)
2073                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2074         cinfo = (CallInfo *)cfg->arch.cinfo;
2075
2076         if (cinfo->ret.storage == ArgValuetypeInReg)
2077                 cfg->ret_var_is_local = TRUE;
2078
2079         sig_ret = mini_get_underlying_type (sig->ret);
2080         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2081                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2082                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2083                         printf ("vret_addr = ");
2084                         mono_print_ins (cfg->vret_addr);
2085                 }
2086         }
2087
2088         if (cfg->gen_sdb_seq_points) {
2089                 MonoInst *ins;
2090
2091                 if (cfg->compile_aot) {
2092                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2093                         ins->flags |= MONO_INST_VOLATILE;
2094                         cfg->arch.seq_point_info_var = ins;
2095                 }
2096                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2097                 ins->flags |= MONO_INST_VOLATILE;
2098                 cfg->arch.ss_tramp_var = ins;
2099
2100                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2101                 ins->flags |= MONO_INST_VOLATILE;
2102                 cfg->arch.bp_tramp_var = ins;
2103         }
2104
2105         if (cfg->method->save_lmf)
2106                 cfg->create_lmf_var = TRUE;
2107
2108         if (cfg->method->save_lmf) {
2109                 cfg->lmf_ir = TRUE;
2110 #if !defined(TARGET_WIN32)
2111                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2112                         cfg->lmf_ir_mono_lmf = TRUE;
2113 #endif
2114         }
2115 }
2116
2117 static void
2118 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2119 {
2120         MonoInst *ins;
2121
2122         switch (storage) {
2123         case ArgInIReg:
2124                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2125                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2126                 ins->sreg1 = tree->dreg;
2127                 MONO_ADD_INS (cfg->cbb, ins);
2128                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2129                 break;
2130         case ArgInFloatSSEReg:
2131                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2132                 ins->dreg = mono_alloc_freg (cfg);
2133                 ins->sreg1 = tree->dreg;
2134                 MONO_ADD_INS (cfg->cbb, ins);
2135
2136                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2137                 break;
2138         case ArgInDoubleSSEReg:
2139                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2140                 ins->dreg = mono_alloc_freg (cfg);
2141                 ins->sreg1 = tree->dreg;
2142                 MONO_ADD_INS (cfg->cbb, ins);
2143
2144                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2145
2146                 break;
2147         default:
2148                 g_assert_not_reached ();
2149         }
2150 }
2151
2152 static int
2153 arg_storage_to_load_membase (ArgStorage storage)
2154 {
2155         switch (storage) {
2156         case ArgInIReg:
2157 #if defined(__mono_ilp32__)
2158                 return OP_LOADI8_MEMBASE;
2159 #else
2160                 return OP_LOAD_MEMBASE;
2161 #endif
2162         case ArgInDoubleSSEReg:
2163                 return OP_LOADR8_MEMBASE;
2164         case ArgInFloatSSEReg:
2165                 return OP_LOADR4_MEMBASE;
2166         default:
2167                 g_assert_not_reached ();
2168         }
2169
2170         return -1;
2171 }
2172
2173 static void
2174 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2175 {
2176         MonoMethodSignature *tmp_sig;
2177         int sig_reg;
2178
2179         if (call->tail_call)
2180                 NOT_IMPLEMENTED;
2181
2182         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2183
2184         /*
2185          * mono_ArgIterator_Setup assumes the signature cookie is
2186          * passed first and all the arguments which were before it are
2187          * passed on the stack after the signature. So compensate by
2188          * passing a different signature.
2189          */
2190         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2191         tmp_sig->param_count -= call->signature->sentinelpos;
2192         tmp_sig->sentinelpos = 0;
2193         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2194
2195         sig_reg = mono_alloc_ireg (cfg);
2196         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2197
2198         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2199 }
2200
2201 #ifdef ENABLE_LLVM
2202 static inline LLVMArgStorage
2203 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2204 {
2205         switch (storage) {
2206         case ArgInIReg:
2207                 return LLVMArgInIReg;
2208         case ArgNone:
2209                 return LLVMArgNone;
2210         case ArgGSharedVtInReg:
2211         case ArgGSharedVtOnStack:
2212                 return LLVMArgGSharedVt;
2213         default:
2214                 g_assert_not_reached ();
2215                 return LLVMArgNone;
2216         }
2217 }
2218
2219 LLVMCallInfo*
2220 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2221 {
2222         int i, n;
2223         CallInfo *cinfo;
2224         ArgInfo *ainfo;
2225         int j;
2226         LLVMCallInfo *linfo;
2227         MonoType *t, *sig_ret;
2228
2229         n = sig->param_count + sig->hasthis;
2230         sig_ret = mini_get_underlying_type (sig->ret);
2231
2232         cinfo = get_call_info (cfg->mempool, sig);
2233
2234         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2235
2236         /*
2237          * LLVM always uses the native ABI while we use our own ABI, the
2238          * only difference is the handling of vtypes:
2239          * - we only pass/receive them in registers in some cases, and only
2240          *   in 1 or 2 integer registers.
2241          */
2242         switch (cinfo->ret.storage) {
2243         case ArgNone:
2244                 linfo->ret.storage = LLVMArgNone;
2245                 break;
2246         case ArgInIReg:
2247         case ArgInFloatSSEReg:
2248         case ArgInDoubleSSEReg:
2249                 linfo->ret.storage = LLVMArgNormal;
2250                 break;
2251         case ArgValuetypeInReg:
2252                 if (sig->pinvoke) {
2253                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
2254                         cfg->disable_llvm = TRUE;
2255                         return linfo;
2256                 }
2257
2258                 linfo->ret.storage = LLVMArgVtypeInReg;
2259                 for (j = 0; j < 2; ++j)
2260                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
2261                 break;
2262         case ArgValuetypeAddrInIReg:
2263                 /* Vtype returned using a hidden argument */
2264                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2265                 linfo->vret_arg_index = cinfo->vret_arg_index;
2266                 break;
2267         default:
2268                 g_assert_not_reached ();
2269                 break;
2270         }
2271
2272         for (i = 0; i < n; ++i) {
2273                 ainfo = cinfo->args + i;
2274
2275                 if (i >= sig->hasthis)
2276                         t = sig->params [i - sig->hasthis];
2277                 else
2278                         t = &mono_defaults.int_class->byval_arg;
2279
2280                 linfo->args [i].storage = LLVMArgNone;
2281
2282                 switch (ainfo->storage) {
2283                 case ArgInIReg:
2284                         linfo->args [i].storage = LLVMArgNormal;
2285                         break;
2286                 case ArgInDoubleSSEReg:
2287                 case ArgInFloatSSEReg:
2288                         linfo->args [i].storage = LLVMArgNormal;
2289                         break;
2290                 case ArgOnStack:
2291                         if (MONO_TYPE_ISSTRUCT (t))
2292                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2293                         else
2294                                 linfo->args [i].storage = LLVMArgNormal;
2295                         break;
2296                 case ArgValuetypeInReg:
2297                         if (sig->pinvoke) {
2298                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2299                                 cfg->disable_llvm = TRUE;
2300                                 return linfo;
2301                         }
2302
2303                         linfo->args [i].storage = LLVMArgVtypeInReg;
2304                         for (j = 0; j < 2; ++j)
2305                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2306                         break;
2307                 case ArgGSharedVtInReg:
2308                 case ArgGSharedVtOnStack:
2309                         linfo->args [i].storage = LLVMArgGSharedVt;
2310                         break;
2311                 default:
2312                         cfg->exception_message = g_strdup ("ainfo->storage");
2313                         cfg->disable_llvm = TRUE;
2314                         break;
2315                 }
2316         }
2317
2318         return linfo;
2319 }
2320 #endif
2321
2322 void
2323 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2324 {
2325         MonoInst *arg, *in;
2326         MonoMethodSignature *sig;
2327         MonoType *sig_ret;
2328         int i, n;
2329         CallInfo *cinfo;
2330         ArgInfo *ainfo;
2331
2332         sig = call->signature;
2333         n = sig->param_count + sig->hasthis;
2334
2335         cinfo = get_call_info (cfg->mempool, sig);
2336
2337         sig_ret = sig->ret;
2338
2339         if (COMPILE_LLVM (cfg)) {
2340                 /* We shouldn't be called in the llvm case */
2341                 cfg->disable_llvm = TRUE;
2342                 return;
2343         }
2344
2345         /*
2346          * Emit all arguments which are passed on the stack to prevent register
2347          * allocation problems.
2348          */
2349         for (i = 0; i < n; ++i) {
2350                 MonoType *t;
2351                 ainfo = cinfo->args + i;
2352
2353                 in = call->args [i];
2354
2355                 if (sig->hasthis && i == 0)
2356                         t = &mono_defaults.object_class->byval_arg;
2357                 else
2358                         t = sig->params [i - sig->hasthis];
2359
2360                 t = mini_get_underlying_type (t);
2361                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2362                         if (!t->byref) {
2363                                 if (t->type == MONO_TYPE_R4)
2364                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2365                                 else if (t->type == MONO_TYPE_R8)
2366                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2367                                 else
2368                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2369                         } else {
2370                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2371                         }
2372                         if (cfg->compute_gc_maps) {
2373                                 MonoInst *def;
2374
2375                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2376                         }
2377                 }
2378         }
2379
2380         /*
2381          * Emit all parameters passed in registers in non-reverse order for better readability
2382          * and to help the optimization in emit_prolog ().
2383          */
2384         for (i = 0; i < n; ++i) {
2385                 ainfo = cinfo->args + i;
2386
2387                 in = call->args [i];
2388
2389                 if (ainfo->storage == ArgInIReg)
2390                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2391         }
2392
2393         for (i = n - 1; i >= 0; --i) {
2394                 MonoType *t;
2395
2396                 ainfo = cinfo->args + i;
2397
2398                 in = call->args [i];
2399
2400                 if (sig->hasthis && i == 0)
2401                         t = &mono_defaults.object_class->byval_arg;
2402                 else
2403                         t = sig->params [i - sig->hasthis];
2404                 t = mini_get_underlying_type (t);
2405
2406                 switch (ainfo->storage) {
2407                 case ArgInIReg:
2408                         /* Already done */
2409                         break;
2410                 case ArgInFloatSSEReg:
2411                 case ArgInDoubleSSEReg:
2412                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2413                         break;
2414                 case ArgOnStack:
2415                 case ArgValuetypeInReg:
2416                 case ArgValuetypeAddrInIReg:
2417                 case ArgGSharedVtInReg:
2418                 case ArgGSharedVtOnStack: {
2419                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2420                                 /* Already emitted above */
2421                                 break;
2422                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2423                                 MonoInst *call_inst = (MonoInst*)call;
2424                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2425                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2426                                 break;
2427                         }
2428
2429                         guint32 align;
2430                         guint32 size;
2431
2432                         if (sig->pinvoke)
2433                                 size = mono_type_native_stack_size (t, &align);
2434                         else {
2435                                 /*
2436                                  * Other backends use mono_type_stack_size (), but that
2437                                  * aligns the size to 8, which is larger than the size of
2438                                  * the source, leading to reads of invalid memory if the
2439                                  * source is at the end of address space.
2440                                  */
2441                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2442                         }
2443
2444                         if (size >= 10000) {
2445                                 /* Avoid asserts in emit_memcpy () */
2446                                 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2447                                 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2448                                 /* Continue normally */
2449                         }
2450
2451                         if (size > 0) {
2452                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2453                                 arg->sreg1 = in->dreg;
2454                                 arg->klass = mono_class_from_mono_type (t);
2455                                 arg->backend.size = size;
2456                                 arg->inst_p0 = call;
2457                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2458                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2459
2460                                 MONO_ADD_INS (cfg->cbb, arg);
2461                         }
2462                         break;
2463                 }
2464                 default:
2465                         g_assert_not_reached ();
2466                 }
2467
2468                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2469                         /* Emit the signature cookie just before the implicit arguments */
2470                         emit_sig_cookie (cfg, call, cinfo);
2471         }
2472
2473         /* Handle the case where there are no implicit arguments */
2474         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2475                 emit_sig_cookie (cfg, call, cinfo);
2476
2477         switch (cinfo->ret.storage) {
2478         case ArgValuetypeInReg:
2479                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2480                         /*
2481                          * Tell the JIT to use a more efficient calling convention: call using
2482                          * OP_CALL, compute the result location after the call, and save the
2483                          * result there.
2484                          */
2485                         call->vret_in_reg = TRUE;
2486                         /*
2487                          * Nullify the instruction computing the vret addr to enable
2488                          * future optimizations.
2489                          */
2490                         if (call->vret_var)
2491                                 NULLIFY_INS (call->vret_var);
2492                 } else {
2493                         if (call->tail_call)
2494                                 NOT_IMPLEMENTED;
2495                         /*
2496                          * The valuetype is in RAX:RDX after the call, need to be copied to
2497                          * the stack. Push the address here, so the call instruction can
2498                          * access it.
2499                          */
2500                         if (!cfg->arch.vret_addr_loc) {
2501                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2502                                 /* Prevent it from being register allocated or optimized away */
2503                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2504                         }
2505
2506                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2507                 }
2508                 break;
2509         case ArgValuetypeAddrInIReg: {
2510                 MonoInst *vtarg;
2511                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2512                 vtarg->sreg1 = call->vret_var->dreg;
2513                 vtarg->dreg = mono_alloc_preg (cfg);
2514                 MONO_ADD_INS (cfg->cbb, vtarg);
2515
2516                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2517                 break;
2518         }
2519         default:
2520                 break;
2521         }
2522
2523         if (cfg->method->save_lmf) {
2524                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2525                 MONO_ADD_INS (cfg->cbb, arg);
2526         }
2527
2528         call->stack_usage = cinfo->stack_usage;
2529 }
2530
2531 void
2532 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2533 {
2534         MonoInst *arg;
2535         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2536         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2537         int size = ins->backend.size;
2538
2539         switch (ainfo->storage) {
2540         case ArgValuetypeInReg: {
2541                 MonoInst *load;
2542                 int part;
2543
2544                 for (part = 0; part < 2; ++part) {
2545                         if (ainfo->pair_storage [part] == ArgNone)
2546                                 continue;
2547
2548                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2549                         load->inst_basereg = src->dreg;
2550                         load->inst_offset = part * sizeof(mgreg_t);
2551
2552                         switch (ainfo->pair_storage [part]) {
2553                         case ArgInIReg:
2554                                 load->dreg = mono_alloc_ireg (cfg);
2555                                 break;
2556                         case ArgInDoubleSSEReg:
2557                         case ArgInFloatSSEReg:
2558                                 load->dreg = mono_alloc_freg (cfg);
2559                                 break;
2560                         default:
2561                                 g_assert_not_reached ();
2562                         }
2563                         MONO_ADD_INS (cfg->cbb, load);
2564
2565                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2566                 }
2567                 break;
2568         }
2569         case ArgValuetypeAddrInIReg: {
2570                 MonoInst *vtaddr, *load;
2571                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2572
2573                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2574                 cfg->has_indirection = TRUE;
2575                 load->inst_p0 = vtaddr;
2576                 vtaddr->flags |= MONO_INST_INDIRECT;
2577                 load->type = STACK_MP;
2578                 load->klass = vtaddr->klass;
2579                 load->dreg = mono_alloc_ireg (cfg);
2580                 MONO_ADD_INS (cfg->cbb, load);
2581                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2582
2583                 if (ainfo->pair_storage [0] == ArgInIReg) {
2584                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2585                         arg->dreg = mono_alloc_ireg (cfg);
2586                         arg->sreg1 = load->dreg;
2587                         arg->inst_imm = 0;
2588                         MONO_ADD_INS (cfg->cbb, arg);
2589                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2590                 } else {
2591                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2592                 }
2593                 break;
2594         }
2595         case ArgGSharedVtInReg:
2596                 /* Pass by addr */
2597                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2598                 break;
2599         case ArgGSharedVtOnStack:
2600                 g_assert_not_reached ();
2601                 break;
2602         default:
2603                 if (size == 8) {
2604                         int dreg = mono_alloc_ireg (cfg);
2605
2606                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2607                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2608                 } else if (size <= 40) {
2609                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2610                 } else {
2611                         // FIXME: Code growth
2612                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2613                 }
2614
2615                 if (cfg->compute_gc_maps) {
2616                         MonoInst *def;
2617                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2618                 }
2619         }
2620 }
2621
2622 void
2623 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2624 {
2625         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2626
2627         if (ret->type == MONO_TYPE_R4) {
2628                 if (COMPILE_LLVM (cfg))
2629                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2630                 else
2631                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2632                 return;
2633         } else if (ret->type == MONO_TYPE_R8) {
2634                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2635                 return;
2636         }
2637
2638         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2639 }
2640
2641 #endif /* DISABLE_JIT */
2642
2643 #define EMIT_COND_BRANCH(ins,cond,sign) \
2644         if (ins->inst_true_bb->native_offset) { \
2645                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2646         } else { \
2647                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2648                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2649             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2650                         x86_branch8 (code, cond, 0, sign); \
2651                 else \
2652                         x86_branch32 (code, cond, 0, sign); \
2653 }
2654
2655 typedef struct {
2656         MonoMethodSignature *sig;
2657         CallInfo *cinfo;
2658 } ArchDynCallInfo;
2659
2660 static gboolean
2661 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2662 {
2663         int i;
2664
2665 #ifdef HOST_WIN32
2666         return FALSE;
2667 #endif
2668
2669         switch (cinfo->ret.storage) {
2670         case ArgNone:
2671         case ArgInIReg:
2672                 break;
2673         case ArgValuetypeInReg: {
2674                 ArgInfo *ainfo = &cinfo->ret;
2675
2676                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2677                         return FALSE;
2678                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2679                         return FALSE;
2680                 break;
2681         }
2682         default:
2683                 return FALSE;
2684         }
2685
2686         for (i = 0; i < cinfo->nargs; ++i) {
2687                 ArgInfo *ainfo = &cinfo->args [i];
2688                 switch (ainfo->storage) {
2689                 case ArgInIReg:
2690                         break;
2691                 case ArgValuetypeInReg:
2692                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2693                                 return FALSE;
2694                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2695                                 return FALSE;
2696                         break;
2697                 default:
2698                         return FALSE;
2699                 }
2700         }
2701
2702         return TRUE;
2703 }
2704
2705 /*
2706  * mono_arch_dyn_call_prepare:
2707  *
2708  *   Return a pointer to an arch-specific structure which contains information
2709  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2710  * supported for SIG.
2711  * This function is equivalent to ffi_prep_cif in libffi.
2712  */
2713 MonoDynCallInfo*
2714 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2715 {
2716         ArchDynCallInfo *info;
2717         CallInfo *cinfo;
2718
2719         cinfo = get_call_info (NULL, sig);
2720
2721         if (!dyn_call_supported (sig, cinfo)) {
2722                 g_free (cinfo);
2723                 return NULL;
2724         }
2725
2726         info = g_new0 (ArchDynCallInfo, 1);
2727         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2728         info->sig = sig;
2729         info->cinfo = cinfo;
2730
2731         return (MonoDynCallInfo*)info;
2732 }
2733
2734 /*
2735  * mono_arch_dyn_call_free:
2736  *
2737  *   Free a MonoDynCallInfo structure.
2738  */
2739 void
2740 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2741 {
2742         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2743
2744         g_free (ainfo->cinfo);
2745         g_free (ainfo);
2746 }
2747
2748 #if !defined(__native_client__)
2749 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2750 #define GREG_TO_PTR(greg) (gpointer)(greg)
2751 #else
2752 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2753 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2754 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2755 #endif
2756
2757 /*
2758  * mono_arch_get_start_dyn_call:
2759  *
2760  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2761  * store the result into BUF.
2762  * ARGS should be an array of pointers pointing to the arguments.
2763  * RET should point to a memory buffer large enought to hold the result of the
2764  * call.
2765  * This function should be as fast as possible, any work which does not depend
2766  * on the actual values of the arguments should be done in
2767  * mono_arch_dyn_call_prepare ().
2768  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2769  * libffi.
2770  */
2771 void
2772 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2773 {
2774         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2775         DynCallArgs *p = (DynCallArgs*)buf;
2776         int arg_index, greg, i, pindex;
2777         MonoMethodSignature *sig = dinfo->sig;
2778         int buffer_offset = 0;
2779
2780         g_assert (buf_len >= sizeof (DynCallArgs));
2781
2782         p->res = 0;
2783         p->ret = ret;
2784
2785         arg_index = 0;
2786         greg = 0;
2787         pindex = 0;
2788
2789         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2790                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2791                 if (!sig->hasthis)
2792                         pindex = 1;
2793         }
2794
2795         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2796                 p->regs [greg ++] = PTR_TO_GREG(ret);
2797
2798         for (i = pindex; i < sig->param_count; i++) {
2799                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2800                 gpointer *arg = args [arg_index ++];
2801
2802                 if (t->byref) {
2803                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2804                         continue;
2805                 }
2806
2807                 switch (t->type) {
2808                 case MONO_TYPE_STRING:
2809                 case MONO_TYPE_CLASS:
2810                 case MONO_TYPE_ARRAY:
2811                 case MONO_TYPE_SZARRAY:
2812                 case MONO_TYPE_OBJECT:
2813                 case MONO_TYPE_PTR:
2814                 case MONO_TYPE_I:
2815                 case MONO_TYPE_U:
2816 #if !defined(__mono_ilp32__)
2817                 case MONO_TYPE_I8:
2818                 case MONO_TYPE_U8:
2819 #endif
2820                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2821                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2822                         break;
2823 #if defined(__mono_ilp32__)
2824                 case MONO_TYPE_I8:
2825                 case MONO_TYPE_U8:
2826                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2827                         p->regs [greg ++] = *(guint64*)(arg);
2828                         break;
2829 #endif
2830                 case MONO_TYPE_U1:
2831                         p->regs [greg ++] = *(guint8*)(arg);
2832                         break;
2833                 case MONO_TYPE_I1:
2834                         p->regs [greg ++] = *(gint8*)(arg);
2835                         break;
2836                 case MONO_TYPE_I2:
2837                         p->regs [greg ++] = *(gint16*)(arg);
2838                         break;
2839                 case MONO_TYPE_U2:
2840                         p->regs [greg ++] = *(guint16*)(arg);
2841                         break;
2842                 case MONO_TYPE_I4:
2843                         p->regs [greg ++] = *(gint32*)(arg);
2844                         break;
2845                 case MONO_TYPE_U4:
2846                         p->regs [greg ++] = *(guint32*)(arg);
2847                         break;
2848                 case MONO_TYPE_GENERICINST:
2849                     if (MONO_TYPE_IS_REFERENCE (t)) {
2850                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2851                                 break;
2852                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2853                                         MonoClass *klass = mono_class_from_mono_type (t);
2854                                         guint8 *nullable_buf;
2855                                         int size;
2856
2857                                         size = mono_class_value_size (klass, NULL);
2858                                         nullable_buf = p->buffer + buffer_offset;
2859                                         buffer_offset += size;
2860                                         g_assert (buffer_offset <= 256);
2861
2862                                         /* The argument pointed to by arg is either a boxed vtype or null */
2863                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2864
2865                                         arg = (gpointer*)nullable_buf;
2866                                         /* Fall though */
2867
2868                         } else {
2869                                 /* Fall through */
2870                         }
2871                 case MONO_TYPE_VALUETYPE: {
2872                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2873
2874                         g_assert (ainfo->storage == ArgValuetypeInReg);
2875                         if (ainfo->pair_storage [0] != ArgNone) {
2876                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2877                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2878                         }
2879                         if (ainfo->pair_storage [1] != ArgNone) {
2880                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2881                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2882                         }
2883                         break;
2884                 }
2885                 default:
2886                         g_assert_not_reached ();
2887                 }
2888         }
2889
2890         g_assert (greg <= PARAM_REGS);
2891 }
2892
2893 /*
2894  * mono_arch_finish_dyn_call:
2895  *
2896  *   Store the result of a dyn call into the return value buffer passed to
2897  * start_dyn_call ().
2898  * This function should be as fast as possible, any work which does not depend
2899  * on the actual values of the arguments should be done in
2900  * mono_arch_dyn_call_prepare ().
2901  */
2902 void
2903 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2904 {
2905         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2906         MonoMethodSignature *sig = dinfo->sig;
2907         guint8 *ret = ((DynCallArgs*)buf)->ret;
2908         mgreg_t res = ((DynCallArgs*)buf)->res;
2909         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2910
2911         switch (sig_ret->type) {
2912         case MONO_TYPE_VOID:
2913                 *(gpointer*)ret = NULL;
2914                 break;
2915         case MONO_TYPE_STRING:
2916         case MONO_TYPE_CLASS:
2917         case MONO_TYPE_ARRAY:
2918         case MONO_TYPE_SZARRAY:
2919         case MONO_TYPE_OBJECT:
2920         case MONO_TYPE_I:
2921         case MONO_TYPE_U:
2922         case MONO_TYPE_PTR:
2923                 *(gpointer*)ret = GREG_TO_PTR(res);
2924                 break;
2925         case MONO_TYPE_I1:
2926                 *(gint8*)ret = res;
2927                 break;
2928         case MONO_TYPE_U1:
2929                 *(guint8*)ret = res;
2930                 break;
2931         case MONO_TYPE_I2:
2932                 *(gint16*)ret = res;
2933                 break;
2934         case MONO_TYPE_U2:
2935                 *(guint16*)ret = res;
2936                 break;
2937         case MONO_TYPE_I4:
2938                 *(gint32*)ret = res;
2939                 break;
2940         case MONO_TYPE_U4:
2941                 *(guint32*)ret = res;
2942                 break;
2943         case MONO_TYPE_I8:
2944                 *(gint64*)ret = res;
2945                 break;
2946         case MONO_TYPE_U8:
2947                 *(guint64*)ret = res;
2948                 break;
2949         case MONO_TYPE_GENERICINST:
2950                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2951                         *(gpointer*)ret = GREG_TO_PTR(res);
2952                         break;
2953                 } else {
2954                         /* Fall through */
2955                 }
2956         case MONO_TYPE_VALUETYPE:
2957                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2958                         /* Nothing to do */
2959                 } else {
2960                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2961
2962                         g_assert (ainfo->storage == ArgValuetypeInReg);
2963
2964                         if (ainfo->pair_storage [0] != ArgNone) {
2965                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2966                                 ((mgreg_t*)ret)[0] = res;
2967                         }
2968
2969                         g_assert (ainfo->pair_storage [1] == ArgNone);
2970                 }
2971                 break;
2972         default:
2973                 g_assert_not_reached ();
2974         }
2975 }
2976
2977 /* emit an exception if condition is fail */
2978 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2979         do {                                                        \
2980                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2981                 if (tins == NULL) {                                                                             \
2982                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2983                                         MONO_PATCH_INFO_EXC, exc_name);  \
2984                         x86_branch32 (code, cond, 0, signed);               \
2985                 } else {        \
2986                         EMIT_COND_BRANCH (tins, cond, signed);  \
2987                 }                       \
2988         } while (0);
2989
2990 #define EMIT_FPCOMPARE(code) do { \
2991         amd64_fcompp (code); \
2992         amd64_fnstsw (code); \
2993 } while (0);
2994
2995 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2996     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2997         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2998         amd64_ ##op (code); \
2999         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3000         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3001 } while (0);
3002
3003 static guint8*
3004 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3005 {
3006         gboolean no_patch = FALSE;
3007
3008         /*
3009          * FIXME: Add support for thunks
3010          */
3011         {
3012                 gboolean near_call = FALSE;
3013
3014                 /*
3015                  * Indirect calls are expensive so try to make a near call if possible.
3016                  * The caller memory is allocated by the code manager so it is
3017                  * guaranteed to be at a 32 bit offset.
3018                  */
3019
3020                 if (patch_type != MONO_PATCH_INFO_ABS) {
3021                         /* The target is in memory allocated using the code manager */
3022                         near_call = TRUE;
3023
3024                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3025                                 if (((MonoMethod*)data)->klass->image->aot_module)
3026                                         /* The callee might be an AOT method */
3027                                         near_call = FALSE;
3028                                 if (((MonoMethod*)data)->dynamic)
3029                                         /* The target is in malloc-ed memory */
3030                                         near_call = FALSE;
3031                         }
3032
3033                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3034                                 /*
3035                                  * The call might go directly to a native function without
3036                                  * the wrapper.
3037                                  */
3038                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
3039                                 if (mi) {
3040                                         gconstpointer target = mono_icall_get_wrapper (mi);
3041                                         if ((((guint64)target) >> 32) != 0)
3042                                                 near_call = FALSE;
3043                                 }
3044                         }
3045                 }
3046                 else {
3047                         MonoJumpInfo *jinfo = NULL;
3048
3049                         if (cfg->abs_patches)
3050                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
3051                         if (jinfo) {
3052                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3053                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3054                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3055                                                 near_call = TRUE;
3056                                         no_patch = TRUE;
3057                                 } else {
3058                                         /*
3059                                          * This is not really an optimization, but required because the
3060                                          * generic class init trampolines use R11 to pass the vtable.
3061                                          */
3062                                         near_call = TRUE;
3063                                 }
3064                         } else {
3065                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3066                                 if (info) {
3067                                         if (info->func == info->wrapper) {
3068                                                 /* No wrapper */
3069                                                 if ((((guint64)info->func) >> 32) == 0)
3070                                                         near_call = TRUE;
3071                                         }
3072                                         else {
3073                                                 /* See the comment in mono_codegen () */
3074                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3075                                                         near_call = TRUE;
3076                                         }
3077                                 }
3078                                 else if ((((guint64)data) >> 32) == 0) {
3079                                         near_call = TRUE;
3080                                         no_patch = TRUE;
3081                                 }
3082                         }
3083                 }
3084
3085                 if (cfg->method->dynamic)
3086                         /* These methods are allocated using malloc */
3087                         near_call = FALSE;
3088
3089 #ifdef MONO_ARCH_NOMAP32BIT
3090                 near_call = FALSE;
3091 #endif
3092 #if defined(__native_client__)
3093                 /* Always use near_call == TRUE for Native Client */
3094                 near_call = TRUE;
3095 #endif
3096                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3097                 if (optimize_for_xen)
3098                         near_call = FALSE;
3099
3100                 if (cfg->compile_aot) {
3101                         near_call = TRUE;
3102                         no_patch = TRUE;
3103                 }
3104
3105                 if (near_call) {
3106                         /*
3107                          * Align the call displacement to an address divisible by 4 so it does
3108                          * not span cache lines. This is required for code patching to work on SMP
3109                          * systems.
3110                          */
3111                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3112                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3113                                 amd64_padding (code, pad_size);
3114                         }
3115                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3116                         amd64_call_code (code, 0);
3117                 }
3118                 else {
3119                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3120                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3121                         amd64_call_reg (code, GP_SCRATCH_REG);
3122                 }
3123         }
3124
3125         return code;
3126 }
3127
3128 static inline guint8*
3129 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3130 {
3131 #ifdef TARGET_WIN32
3132         if (win64_adjust_stack)
3133                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3134 #endif
3135         code = emit_call_body (cfg, code, patch_type, data);
3136 #ifdef TARGET_WIN32
3137         if (win64_adjust_stack)
3138                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3139 #endif
3140
3141         return code;
3142 }
3143
3144 static inline int
3145 store_membase_imm_to_store_membase_reg (int opcode)
3146 {
3147         switch (opcode) {
3148         case OP_STORE_MEMBASE_IMM:
3149                 return OP_STORE_MEMBASE_REG;
3150         case OP_STOREI4_MEMBASE_IMM:
3151                 return OP_STOREI4_MEMBASE_REG;
3152         case OP_STOREI8_MEMBASE_IMM:
3153                 return OP_STOREI8_MEMBASE_REG;
3154         }
3155
3156         return -1;
3157 }
3158
3159 #ifndef DISABLE_JIT
3160
3161 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3162
3163 /*
3164  * mono_arch_peephole_pass_1:
3165  *
3166  *   Perform peephole opts which should/can be performed before local regalloc
3167  */
3168 void
3169 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3170 {
3171         MonoInst *ins, *n;
3172
3173         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3174                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3175
3176                 switch (ins->opcode) {
3177                 case OP_ADD_IMM:
3178                 case OP_IADD_IMM:
3179                 case OP_LADD_IMM:
3180                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3181                                 /*
3182                                  * X86_LEA is like ADD, but doesn't have the
3183                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3184                                  * its operand to 64 bit.
3185                                  */
3186                                 ins->opcode = OP_X86_LEA_MEMBASE;
3187                                 ins->inst_basereg = ins->sreg1;
3188                         }
3189                         break;
3190                 case OP_LXOR:
3191                 case OP_IXOR:
3192                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3193                                 MonoInst *ins2;
3194
3195                                 /*
3196                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3197                                  * the latter has length 2-3 instead of 6 (reverse constant
3198                                  * propagation). These instruction sequences are very common
3199                                  * in the initlocals bblock.
3200                                  */
3201                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3202                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3203                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3204                                                 ins2->sreg1 = ins->dreg;
3205                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3206                                                 /* Continue */
3207                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3208                                                 NULLIFY_INS (ins2);
3209                                                 /* Continue */
3210                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3211                                                 /* Continue */
3212                                         } else {
3213                                                 break;
3214                                         }
3215                                 }
3216                         }
3217                         break;
3218                 case OP_COMPARE_IMM:
3219                 case OP_LCOMPARE_IMM:
3220                         /* OP_COMPARE_IMM (reg, 0)
3221                          * -->
3222                          * OP_AMD64_TEST_NULL (reg)
3223                          */
3224                         if (!ins->inst_imm)
3225                                 ins->opcode = OP_AMD64_TEST_NULL;
3226                         break;
3227                 case OP_ICOMPARE_IMM:
3228                         if (!ins->inst_imm)
3229                                 ins->opcode = OP_X86_TEST_NULL;
3230                         break;
3231                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3232                         /*
3233                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3234                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3235                          * -->
3236                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3237                          * OP_COMPARE_IMM reg, imm
3238                          *
3239                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3240                          */
3241                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3242                             ins->inst_basereg == last_ins->inst_destbasereg &&
3243                             ins->inst_offset == last_ins->inst_offset) {
3244                                         ins->opcode = OP_ICOMPARE_IMM;
3245                                         ins->sreg1 = last_ins->sreg1;
3246
3247                                         /* check if we can remove cmp reg,0 with test null */
3248                                         if (!ins->inst_imm)
3249                                                 ins->opcode = OP_X86_TEST_NULL;
3250                                 }
3251
3252                         break;
3253                 }
3254
3255                 mono_peephole_ins (bb, ins);
3256         }
3257 }
3258
3259 void
3260 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3261 {
3262         MonoInst *ins, *n;
3263
3264         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3265                 switch (ins->opcode) {
3266                 case OP_ICONST:
3267                 case OP_I8CONST: {
3268                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3269                         /* reg = 0 -> XOR (reg, reg) */
3270                         /* XOR sets cflags on x86, so we cant do it always */
3271                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3272                                 ins->opcode = OP_LXOR;
3273                                 ins->sreg1 = ins->dreg;
3274                                 ins->sreg2 = ins->dreg;
3275                                 /* Fall through */
3276                         } else {
3277                                 break;
3278                         }
3279                 }
3280                 case OP_LXOR:
3281                         /*
3282                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3283                          * 0 result into 64 bits.
3284                          */
3285                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3286                                 ins->opcode = OP_IXOR;
3287                         }
3288                         /* Fall through */
3289                 case OP_IXOR:
3290                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3291                                 MonoInst *ins2;
3292
3293                                 /*
3294                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3295                                  * the latter has length 2-3 instead of 6 (reverse constant
3296                                  * propagation). These instruction sequences are very common
3297                                  * in the initlocals bblock.
3298                                  */
3299                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3300                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3301                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3302                                                 ins2->sreg1 = ins->dreg;
3303                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3304                                                 /* Continue */
3305                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3306                                                 NULLIFY_INS (ins2);
3307                                                 /* Continue */
3308                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3309                                                 /* Continue */
3310                                         } else {
3311                                                 break;
3312                                         }
3313                                 }
3314                         }
3315                         break;
3316                 case OP_IADD_IMM:
3317                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3318                                 ins->opcode = OP_X86_INC_REG;
3319                         break;
3320                 case OP_ISUB_IMM:
3321                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3322                                 ins->opcode = OP_X86_DEC_REG;
3323                         break;
3324                 }
3325
3326                 mono_peephole_ins (bb, ins);
3327         }
3328 }
3329
3330 #define NEW_INS(cfg,ins,dest,op) do {   \
3331                 MONO_INST_NEW ((cfg), (dest), (op)); \
3332         (dest)->cil_code = (ins)->cil_code; \
3333         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3334         } while (0)
3335
3336 /*
3337  * mono_arch_lowering_pass:
3338  *
3339  *  Converts complex opcodes into simpler ones so that each IR instruction
3340  * corresponds to one machine instruction.
3341  */
3342 void
3343 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3344 {
3345         MonoInst *ins, *n, *temp;
3346
3347         /*
3348          * FIXME: Need to add more instructions, but the current machine
3349          * description can't model some parts of the composite instructions like
3350          * cdq.
3351          */
3352         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3353                 switch (ins->opcode) {
3354                 case OP_DIV_IMM:
3355                 case OP_REM_IMM:
3356                 case OP_IDIV_IMM:
3357                 case OP_IDIV_UN_IMM:
3358                 case OP_IREM_UN_IMM:
3359                 case OP_LREM_IMM:
3360                 case OP_IREM_IMM:
3361                         mono_decompose_op_imm (cfg, bb, ins);
3362                         break;
3363                 case OP_COMPARE_IMM:
3364                 case OP_LCOMPARE_IMM:
3365                         if (!amd64_use_imm32 (ins->inst_imm)) {
3366                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3367                                 temp->inst_c0 = ins->inst_imm;
3368                                 temp->dreg = mono_alloc_ireg (cfg);
3369                                 ins->opcode = OP_COMPARE;
3370                                 ins->sreg2 = temp->dreg;
3371                         }
3372                         break;
3373 #ifndef __mono_ilp32__
3374                 case OP_LOAD_MEMBASE:
3375 #endif
3376                 case OP_LOADI8_MEMBASE:
3377 #ifndef __native_client_codegen__
3378                 /*  Don't generate memindex opcodes (to simplify */
3379                 /*  read sandboxing) */
3380                         if (!amd64_use_imm32 (ins->inst_offset)) {
3381                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3382                                 temp->inst_c0 = ins->inst_offset;
3383                                 temp->dreg = mono_alloc_ireg (cfg);
3384                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3385                                 ins->inst_indexreg = temp->dreg;
3386                         }
3387 #endif
3388                         break;
3389 #ifndef __mono_ilp32__
3390                 case OP_STORE_MEMBASE_IMM:
3391 #endif
3392                 case OP_STOREI8_MEMBASE_IMM:
3393                         if (!amd64_use_imm32 (ins->inst_imm)) {
3394                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3395                                 temp->inst_c0 = ins->inst_imm;
3396                                 temp->dreg = mono_alloc_ireg (cfg);
3397                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3398                                 ins->sreg1 = temp->dreg;
3399                         }
3400                         break;
3401 #ifdef MONO_ARCH_SIMD_INTRINSICS
3402                 case OP_EXPAND_I1: {
3403                                 int temp_reg1 = mono_alloc_ireg (cfg);
3404                                 int temp_reg2 = mono_alloc_ireg (cfg);
3405                                 int original_reg = ins->sreg1;
3406
3407                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3408                                 temp->sreg1 = original_reg;
3409                                 temp->dreg = temp_reg1;
3410
3411                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3412                                 temp->sreg1 = temp_reg1;
3413                                 temp->dreg = temp_reg2;
3414                                 temp->inst_imm = 8;
3415
3416                                 NEW_INS (cfg, ins, temp, OP_LOR);
3417                                 temp->sreg1 = temp->dreg = temp_reg2;
3418                                 temp->sreg2 = temp_reg1;
3419
3420                                 ins->opcode = OP_EXPAND_I2;
3421                                 ins->sreg1 = temp_reg2;
3422                         }
3423                         break;
3424 #endif
3425                 default:
3426                         break;
3427                 }
3428         }
3429
3430         bb->max_vreg = cfg->next_vreg;
3431 }
3432
3433 static const int
3434 branch_cc_table [] = {
3435         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3436         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3437         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3438 };
3439
3440 /* Maps CMP_... constants to X86_CC_... constants */
3441 static const int
3442 cc_table [] = {
3443         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3444         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3445 };
3446
3447 static const int
3448 cc_signed_table [] = {
3449         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3450         FALSE, FALSE, FALSE, FALSE
3451 };
3452
3453 /*#include "cprop.c"*/
3454
3455 static unsigned char*
3456 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3457 {
3458         if (size == 8)
3459                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3460         else
3461                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3462
3463         if (size == 1)
3464                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3465         else if (size == 2)
3466                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3467         return code;
3468 }
3469
3470 static unsigned char*
3471 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3472 {
3473         int sreg = tree->sreg1;
3474         int need_touch = FALSE;
3475
3476 #if defined(TARGET_WIN32)
3477         need_touch = TRUE;
3478 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3479         if (!tree->flags & MONO_INST_INIT)
3480                 need_touch = TRUE;
3481 #endif
3482
3483         if (need_touch) {
3484                 guint8* br[5];
3485
3486                 /*
3487                  * Under Windows:
3488                  * If requested stack size is larger than one page,
3489                  * perform stack-touch operation
3490                  */
3491                 /*
3492                  * Generate stack probe code.
3493                  * Under Windows, it is necessary to allocate one page at a time,
3494                  * "touching" stack after each successful sub-allocation. This is
3495                  * because of the way stack growth is implemented - there is a
3496                  * guard page before the lowest stack page that is currently commited.
3497                  * Stack normally grows sequentially so OS traps access to the
3498                  * guard page and commits more pages when needed.
3499                  */
3500                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3501                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3502
3503                 br[2] = code; /* loop */
3504                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3505                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3506                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3507                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3508                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3509                 amd64_patch (br[3], br[2]);
3510                 amd64_test_reg_reg (code, sreg, sreg);
3511                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3512                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3513
3514                 br[1] = code; x86_jump8 (code, 0);
3515
3516                 amd64_patch (br[0], code);
3517                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3518                 amd64_patch (br[1], code);
3519                 amd64_patch (br[4], code);
3520         }
3521         else
3522                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3523
3524         if (tree->flags & MONO_INST_INIT) {
3525                 int offset = 0;
3526                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3527                         amd64_push_reg (code, AMD64_RAX);
3528                         offset += 8;
3529                 }
3530                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3531                         amd64_push_reg (code, AMD64_RCX);
3532                         offset += 8;
3533                 }
3534                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3535                         amd64_push_reg (code, AMD64_RDI);
3536                         offset += 8;
3537                 }
3538
3539                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3540                 if (sreg != AMD64_RCX)
3541                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3542                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3543
3544                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3545                 if (cfg->param_area)
3546                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3547                 amd64_cld (code);
3548 #if defined(__default_codegen__)
3549                 amd64_prefix (code, X86_REP_PREFIX);
3550                 amd64_stosl (code);
3551 #elif defined(__native_client_codegen__)
3552                 /* NaCl stos pseudo-instruction */
3553                 amd64_codegen_pre(code);
3554                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3555                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3556                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3557                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3558                 amd64_prefix (code, X86_REP_PREFIX);
3559                 amd64_stosl (code);
3560                 amd64_codegen_post(code);
3561 #endif /* __native_client_codegen__ */
3562
3563                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3564                         amd64_pop_reg (code, AMD64_RDI);
3565                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3566                         amd64_pop_reg (code, AMD64_RCX);
3567                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3568                         amd64_pop_reg (code, AMD64_RAX);
3569         }
3570         return code;
3571 }
3572
3573 static guint8*
3574 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3575 {
3576         CallInfo *cinfo;
3577         guint32 quad;
3578
3579         /* Move return value to the target register */
3580         /* FIXME: do this in the local reg allocator */
3581         switch (ins->opcode) {
3582         case OP_CALL:
3583         case OP_CALL_REG:
3584         case OP_CALL_MEMBASE:
3585         case OP_LCALL:
3586         case OP_LCALL_REG:
3587         case OP_LCALL_MEMBASE:
3588                 g_assert (ins->dreg == AMD64_RAX);
3589                 break;
3590         case OP_FCALL:
3591         case OP_FCALL_REG:
3592         case OP_FCALL_MEMBASE: {
3593                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3594                 if (rtype->type == MONO_TYPE_R4) {
3595                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3596                 }
3597                 else {
3598                         if (ins->dreg != AMD64_XMM0)
3599                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3600                 }
3601                 break;
3602         }
3603         case OP_RCALL:
3604         case OP_RCALL_REG:
3605         case OP_RCALL_MEMBASE:
3606                 if (ins->dreg != AMD64_XMM0)
3607                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3608                 break;
3609         case OP_VCALL:
3610         case OP_VCALL_REG:
3611         case OP_VCALL_MEMBASE:
3612         case OP_VCALL2:
3613         case OP_VCALL2_REG:
3614         case OP_VCALL2_MEMBASE:
3615                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3616                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3617                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3618
3619                         /* Load the destination address */
3620                         g_assert (loc->opcode == OP_REGOFFSET);
3621                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3622
3623                         for (quad = 0; quad < 2; quad ++) {
3624                                 switch (cinfo->ret.pair_storage [quad]) {
3625                                 case ArgInIReg:
3626                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3627                                         break;
3628                                 case ArgInFloatSSEReg:
3629                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3630                                         break;
3631                                 case ArgInDoubleSSEReg:
3632                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3633                                         break;
3634                                 case ArgNone:
3635                                         break;
3636                                 default:
3637                                         NOT_IMPLEMENTED;
3638                                 }
3639                         }
3640                 }
3641                 break;
3642         }
3643
3644         return code;
3645 }
3646
3647 #endif /* DISABLE_JIT */
3648
3649 #ifdef __APPLE__
3650 static int tls_gs_offset;
3651 #endif
3652
3653 gboolean
3654 mono_amd64_have_tls_get (void)
3655 {
3656 #ifdef TARGET_MACH
3657         static gboolean have_tls_get = FALSE;
3658         static gboolean inited = FALSE;
3659
3660         if (inited)
3661                 return have_tls_get;
3662
3663 #if MONO_HAVE_FAST_TLS
3664         guint8 *ins = (guint8*)pthread_getspecific;
3665
3666         /*
3667          * We're looking for these two instructions:
3668          *
3669          * mov    %gs:[offset](,%rdi,8),%rax
3670          * retq
3671          */
3672         have_tls_get = ins [0] == 0x65 &&
3673                        ins [1] == 0x48 &&
3674                        ins [2] == 0x8b &&
3675                        ins [3] == 0x04 &&
3676                        ins [4] == 0xfd &&
3677                        ins [6] == 0x00 &&
3678                        ins [7] == 0x00 &&
3679                        ins [8] == 0x00 &&
3680                        ins [9] == 0xc3;
3681
3682         tls_gs_offset = ins[5];
3683
3684         /*
3685          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3686          * For that version we're looking for these instructions:
3687          *
3688          * pushq  %rbp
3689          * movq   %rsp, %rbp
3690          * mov    %gs:[offset](,%rdi,8),%rax
3691          * popq   %rbp
3692          * retq
3693          */
3694         if (!have_tls_get) {
3695                 have_tls_get = ins [0] == 0x55 &&
3696                                ins [1] == 0x48 &&
3697                                ins [2] == 0x89 &&
3698                                ins [3] == 0xe5 &&
3699                                ins [4] == 0x65 &&
3700                                ins [5] == 0x48 &&
3701                                ins [6] == 0x8b &&
3702                                ins [7] == 0x04 &&
3703                                ins [8] == 0xfd &&
3704                                ins [10] == 0x00 &&
3705                                ins [11] == 0x00 &&
3706                                ins [12] == 0x00 &&
3707                                ins [13] == 0x5d &&
3708                                ins [14] == 0xc3;
3709
3710                 tls_gs_offset = ins[9];
3711         }
3712 #endif
3713
3714         inited = TRUE;
3715
3716         return have_tls_get;
3717 #elif defined(TARGET_ANDROID)
3718         return FALSE;
3719 #else
3720         return TRUE;
3721 #endif
3722 }
3723
3724 int
3725 mono_amd64_get_tls_gs_offset (void)
3726 {
3727 #ifdef TARGET_OSX
3728         return tls_gs_offset;
3729 #else
3730         g_assert_not_reached ();
3731         return -1;
3732 #endif
3733 }
3734
3735 /*
3736  * mono_amd64_emit_tls_get:
3737  * @code: buffer to store code to
3738  * @dreg: hard register where to place the result
3739  * @tls_offset: offset info
3740  *
3741  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3742  * the dreg register the item in the thread local storage identified
3743  * by tls_offset.
3744  *
3745  * Returns: a pointer to the end of the stored code
3746  */
3747 guint8*
3748 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3749 {
3750 #ifdef TARGET_WIN32
3751         if (tls_offset < 64) {
3752                 x86_prefix (code, X86_GS_PREFIX);
3753                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3754         } else {
3755                 guint8 *buf [16];
3756
3757                 g_assert (tls_offset < 0x440);
3758                 /* Load TEB->TlsExpansionSlots */
3759                 x86_prefix (code, X86_GS_PREFIX);
3760                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3761                 amd64_test_reg_reg (code, dreg, dreg);
3762                 buf [0] = code;
3763                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3764                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3765                 amd64_patch (buf [0], code);
3766         }
3767 #elif defined(__APPLE__)
3768         x86_prefix (code, X86_GS_PREFIX);
3769         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3770 #else
3771         if (optimize_for_xen) {
3772                 x86_prefix (code, X86_FS_PREFIX);
3773                 amd64_mov_reg_mem (code, dreg, 0, 8);
3774                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3775         } else {
3776                 x86_prefix (code, X86_FS_PREFIX);
3777                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3778         }
3779 #endif
3780         return code;
3781 }
3782
3783 static guint8*
3784 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3785 {
3786         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3787 #ifdef TARGET_OSX
3788         if (dreg != offset_reg)
3789                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3790         amd64_prefix (code, X86_GS_PREFIX);
3791         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3792 #elif defined(__linux__)
3793         int tmpreg = -1;
3794
3795         if (dreg == offset_reg) {
3796                 /* Use a temporary reg by saving it to the redzone */
3797                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3798                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3799                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3800                 offset_reg = tmpreg;
3801         }
3802         x86_prefix (code, X86_FS_PREFIX);
3803         amd64_mov_reg_mem (code, dreg, 0, 8);
3804         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3805         if (tmpreg != -1)
3806                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3807 #else
3808         g_assert_not_reached ();
3809 #endif
3810         return code;
3811 }
3812
3813 static guint8*
3814 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3815 {
3816 #ifdef TARGET_WIN32
3817         g_assert_not_reached ();
3818 #elif defined(__APPLE__)
3819         x86_prefix (code, X86_GS_PREFIX);
3820         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3821 #else
3822         g_assert (!optimize_for_xen);
3823         x86_prefix (code, X86_FS_PREFIX);
3824         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3825 #endif
3826         return code;
3827 }
3828
3829 static guint8*
3830 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3831 {
3832         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3833 #ifdef TARGET_WIN32
3834         g_assert_not_reached ();
3835 #elif defined(__APPLE__)
3836         x86_prefix (code, X86_GS_PREFIX);
3837         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3838 #else
3839         x86_prefix (code, X86_FS_PREFIX);
3840         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3841 #endif
3842         return code;
3843 }
3844
3845  /*
3846  * mono_arch_translate_tls_offset:
3847  *
3848  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3849  */
3850 int
3851 mono_arch_translate_tls_offset (int offset)
3852 {
3853 #ifdef __APPLE__
3854         return tls_gs_offset + (offset * 8);
3855 #else
3856         return offset;
3857 #endif
3858 }
3859
3860 /*
3861  * emit_setup_lmf:
3862  *
3863  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3864  */
3865 static guint8*
3866 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3867 {
3868         /*
3869          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3870          */
3871         /*
3872          * sp is saved right before calls but we need to save it here too so
3873          * async stack walks would work.
3874          */
3875         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3876         /* Save rbp */
3877         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3878         if (cfg->arch.omit_fp && cfa_offset != -1)
3879                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3880
3881         /* These can't contain refs */
3882         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3883         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3884         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3885         /* These are handled automatically by the stack marking code */
3886         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3887
3888         return code;
3889 }
3890
3891 #define REAL_PRINT_REG(text,reg) \
3892 mono_assert (reg >= 0); \
3893 amd64_push_reg (code, AMD64_RAX); \
3894 amd64_push_reg (code, AMD64_RDX); \
3895 amd64_push_reg (code, AMD64_RCX); \
3896 amd64_push_reg (code, reg); \
3897 amd64_push_imm (code, reg); \
3898 amd64_push_imm (code, text " %d %p\n"); \
3899 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3900 amd64_call_reg (code, AMD64_RAX); \
3901 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3902 amd64_pop_reg (code, AMD64_RCX); \
3903 amd64_pop_reg (code, AMD64_RDX); \
3904 amd64_pop_reg (code, AMD64_RAX);
3905
3906 /* benchmark and set based on cpu */
3907 #define LOOP_ALIGNMENT 8
3908 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3909
3910 #ifndef DISABLE_JIT
3911 void
3912 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3913 {
3914         MonoInst *ins;
3915         MonoCallInst *call;
3916         guint offset;
3917         guint8 *code = cfg->native_code + cfg->code_len;
3918         int max_len;
3919
3920         /* Fix max_offset estimate for each successor bb */
3921         if (cfg->opt & MONO_OPT_BRANCH) {
3922                 int current_offset = cfg->code_len;
3923                 MonoBasicBlock *current_bb;
3924                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3925                         current_bb->max_offset = current_offset;
3926                         current_offset += current_bb->max_length;
3927                 }
3928         }
3929
3930         if (cfg->opt & MONO_OPT_LOOP) {
3931                 int pad, align = LOOP_ALIGNMENT;
3932                 /* set alignment depending on cpu */
3933                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3934                         pad = align - pad;
3935                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3936                         amd64_padding (code, pad);
3937                         cfg->code_len += pad;
3938                         bb->native_offset = cfg->code_len;
3939                 }
3940         }
3941
3942 #if defined(__native_client_codegen__)
3943         /* For Native Client, all indirect call/jump targets must be */
3944         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3945         /* indirectly as well.                                       */
3946         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3947                                       (bb->flags & BB_EXCEPTION_HANDLER);
3948
3949         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3950                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3951                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3952                 cfg->code_len += pad;
3953                 bb->native_offset = cfg->code_len;
3954         }
3955 #endif  /*__native_client_codegen__*/
3956
3957         if (cfg->verbose_level > 2)
3958                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3959
3960         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3961                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3962                 g_assert (!cfg->compile_aot);
3963
3964                 cov->data [bb->dfn].cil_code = bb->cil_code;
3965                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3966                 /* this is not thread save, but good enough */
3967                 amd64_inc_membase (code, AMD64_R11, 0);
3968         }
3969
3970         offset = code - cfg->native_code;
3971
3972         mono_debug_open_block (cfg, bb, offset);
3973
3974     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3975                 x86_breakpoint (code);
3976
3977         MONO_BB_FOR_EACH_INS (bb, ins) {
3978                 offset = code - cfg->native_code;
3979
3980                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3981
3982 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
3983
3984                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
3985                         cfg->code_size *= 2;
3986                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
3987                         code = cfg->native_code + offset;
3988                         cfg->stat_code_reallocs++;
3989                 }
3990
3991                 if (cfg->debug_info)
3992                         mono_debug_record_line_number (cfg, ins, offset);
3993
3994                 switch (ins->opcode) {
3995                 case OP_BIGMUL:
3996                         amd64_mul_reg (code, ins->sreg2, TRUE);
3997                         break;
3998                 case OP_BIGMUL_UN:
3999                         amd64_mul_reg (code, ins->sreg2, FALSE);
4000                         break;
4001                 case OP_X86_SETEQ_MEMBASE:
4002                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
4003                         break;
4004                 case OP_STOREI1_MEMBASE_IMM:
4005                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
4006                         break;
4007                 case OP_STOREI2_MEMBASE_IMM:
4008                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
4009                         break;
4010                 case OP_STOREI4_MEMBASE_IMM:
4011                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
4012                         break;
4013                 case OP_STOREI1_MEMBASE_REG:
4014                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4015                         break;
4016                 case OP_STOREI2_MEMBASE_REG:
4017                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4018                         break;
4019                 /* In AMD64 NaCl, pointers are 4 bytes, */
4020                 /*  so STORE_* != STOREI8_*. Likewise below. */
4021                 case OP_STORE_MEMBASE_REG:
4022                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4023                         break;
4024                 case OP_STOREI8_MEMBASE_REG:
4025                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4026                         break;
4027                 case OP_STOREI4_MEMBASE_REG:
4028                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4029                         break;
4030                 case OP_STORE_MEMBASE_IMM:
4031 #ifndef __native_client_codegen__
4032                         /* In NaCl, this could be a PCONST type, which could */
4033                         /* mean a pointer type was copied directly into the  */
4034                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4035                         /* the value would be 0x00000000FFFFFFFF which is    */
4036                         /* not proper for an imm32 unless you cast it.       */
4037                         g_assert (amd64_is_imm32 (ins->inst_imm));
4038 #endif
4039                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4040                         break;
4041                 case OP_STOREI8_MEMBASE_IMM:
4042                         g_assert (amd64_is_imm32 (ins->inst_imm));
4043                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4044                         break;
4045                 case OP_LOAD_MEM:
4046 #ifdef __mono_ilp32__
4047                         /* In ILP32, pointers are 4 bytes, so separate these */
4048                         /* cases, use literal 8 below where we really want 8 */
4049                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4050                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4051                         break;
4052 #endif
4053                 case OP_LOADI8_MEM:
4054                         // FIXME: Decompose this earlier
4055                         if (amd64_use_imm32 (ins->inst_imm))
4056                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4057                         else {
4058                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4059                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4060                         }
4061                         break;
4062                 case OP_LOADI4_MEM:
4063                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4064                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4065                         break;
4066                 case OP_LOADU4_MEM:
4067                         // FIXME: Decompose this earlier
4068                         if (amd64_use_imm32 (ins->inst_imm))
4069                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4070                         else {
4071                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4072                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4073                         }
4074                         break;
4075                 case OP_LOADU1_MEM:
4076                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4077                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4078                         break;
4079                 case OP_LOADU2_MEM:
4080                         /* For NaCl, pointers are 4 bytes, so separate these */
4081                         /* cases, use literal 8 below where we really want 8 */
4082                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4083                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4084                         break;
4085                 case OP_LOAD_MEMBASE:
4086                         g_assert (amd64_is_imm32 (ins->inst_offset));
4087                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4088                         break;
4089                 case OP_LOADI8_MEMBASE:
4090                         /* Use literal 8 instead of sizeof pointer or */
4091                         /* register, we really want 8 for this opcode */
4092                         g_assert (amd64_is_imm32 (ins->inst_offset));
4093                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4094                         break;
4095                 case OP_LOADI4_MEMBASE:
4096                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4097                         break;
4098                 case OP_LOADU4_MEMBASE:
4099                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4100                         break;
4101                 case OP_LOADU1_MEMBASE:
4102                         /* The cpu zero extends the result into 64 bits */
4103                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4104                         break;
4105                 case OP_LOADI1_MEMBASE:
4106                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4107                         break;
4108                 case OP_LOADU2_MEMBASE:
4109                         /* The cpu zero extends the result into 64 bits */
4110                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4111                         break;
4112                 case OP_LOADI2_MEMBASE:
4113                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4114                         break;
4115                 case OP_AMD64_LOADI8_MEMINDEX:
4116                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4117                         break;
4118                 case OP_LCONV_TO_I1:
4119                 case OP_ICONV_TO_I1:
4120                 case OP_SEXT_I1:
4121                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4122                         break;
4123                 case OP_LCONV_TO_I2:
4124                 case OP_ICONV_TO_I2:
4125                 case OP_SEXT_I2:
4126                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4127                         break;
4128                 case OP_LCONV_TO_U1:
4129                 case OP_ICONV_TO_U1:
4130                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4131                         break;
4132                 case OP_LCONV_TO_U2:
4133                 case OP_ICONV_TO_U2:
4134                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4135                         break;
4136                 case OP_ZEXT_I4:
4137                         /* Clean out the upper word */
4138                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4139                         break;
4140                 case OP_SEXT_I4:
4141                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4142                         break;
4143                 case OP_COMPARE:
4144                 case OP_LCOMPARE:
4145                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4146                         break;
4147                 case OP_COMPARE_IMM:
4148 #if defined(__mono_ilp32__)
4149                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4150                         g_assert (amd64_is_imm32 (ins->inst_imm));
4151                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4152                         break;
4153 #endif
4154                 case OP_LCOMPARE_IMM:
4155                         g_assert (amd64_is_imm32 (ins->inst_imm));
4156                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4157                         break;
4158                 case OP_X86_COMPARE_REG_MEMBASE:
4159                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4160                         break;
4161                 case OP_X86_TEST_NULL:
4162                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4163                         break;
4164                 case OP_AMD64_TEST_NULL:
4165                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4166                         break;
4167
4168                 case OP_X86_ADD_REG_MEMBASE:
4169                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4170                         break;
4171                 case OP_X86_SUB_REG_MEMBASE:
4172                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4173                         break;
4174                 case OP_X86_AND_REG_MEMBASE:
4175                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4176                         break;
4177                 case OP_X86_OR_REG_MEMBASE:
4178                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4179                         break;
4180                 case OP_X86_XOR_REG_MEMBASE:
4181                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4182                         break;
4183
4184                 case OP_X86_ADD_MEMBASE_IMM:
4185                         /* FIXME: Make a 64 version too */
4186                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4187                         break;
4188                 case OP_X86_SUB_MEMBASE_IMM:
4189                         g_assert (amd64_is_imm32 (ins->inst_imm));
4190                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4191                         break;
4192                 case OP_X86_AND_MEMBASE_IMM:
4193                         g_assert (amd64_is_imm32 (ins->inst_imm));
4194                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4195                         break;
4196                 case OP_X86_OR_MEMBASE_IMM:
4197                         g_assert (amd64_is_imm32 (ins->inst_imm));
4198                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4199                         break;
4200                 case OP_X86_XOR_MEMBASE_IMM:
4201                         g_assert (amd64_is_imm32 (ins->inst_imm));
4202                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4203                         break;
4204                 case OP_X86_ADD_MEMBASE_REG:
4205                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4206                         break;
4207                 case OP_X86_SUB_MEMBASE_REG:
4208                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4209                         break;
4210                 case OP_X86_AND_MEMBASE_REG:
4211                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4212                         break;
4213                 case OP_X86_OR_MEMBASE_REG:
4214                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4215                         break;
4216                 case OP_X86_XOR_MEMBASE_REG:
4217                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4218                         break;
4219                 case OP_X86_INC_MEMBASE:
4220                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4221                         break;
4222                 case OP_X86_INC_REG:
4223                         amd64_inc_reg_size (code, ins->dreg, 4);
4224                         break;
4225                 case OP_X86_DEC_MEMBASE:
4226                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4227                         break;
4228                 case OP_X86_DEC_REG:
4229                         amd64_dec_reg_size (code, ins->dreg, 4);
4230                         break;
4231                 case OP_X86_MUL_REG_MEMBASE:
4232                 case OP_X86_MUL_MEMBASE_REG:
4233                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4234                         break;
4235                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4236                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4237                         break;
4238                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4239                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4240                         break;
4241                 case OP_AMD64_COMPARE_MEMBASE_REG:
4242                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4243                         break;
4244                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4245                         g_assert (amd64_is_imm32 (ins->inst_imm));
4246                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4247                         break;
4248                 case OP_X86_COMPARE_MEMBASE8_IMM:
4249                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4250                         break;
4251                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4252                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4253                         break;
4254                 case OP_AMD64_COMPARE_REG_MEMBASE:
4255                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4256                         break;
4257
4258                 case OP_AMD64_ADD_REG_MEMBASE:
4259                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4260                         break;
4261                 case OP_AMD64_SUB_REG_MEMBASE:
4262                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4263                         break;
4264                 case OP_AMD64_AND_REG_MEMBASE:
4265                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4266                         break;
4267                 case OP_AMD64_OR_REG_MEMBASE:
4268                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4269                         break;
4270                 case OP_AMD64_XOR_REG_MEMBASE:
4271                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4272                         break;
4273
4274                 case OP_AMD64_ADD_MEMBASE_REG:
4275                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4276                         break;
4277                 case OP_AMD64_SUB_MEMBASE_REG:
4278                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4279                         break;
4280                 case OP_AMD64_AND_MEMBASE_REG:
4281                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4282                         break;
4283                 case OP_AMD64_OR_MEMBASE_REG:
4284                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4285                         break;
4286                 case OP_AMD64_XOR_MEMBASE_REG:
4287                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4288                         break;
4289
4290                 case OP_AMD64_ADD_MEMBASE_IMM:
4291                         g_assert (amd64_is_imm32 (ins->inst_imm));
4292                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4293                         break;
4294                 case OP_AMD64_SUB_MEMBASE_IMM:
4295                         g_assert (amd64_is_imm32 (ins->inst_imm));
4296                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4297                         break;
4298                 case OP_AMD64_AND_MEMBASE_IMM:
4299                         g_assert (amd64_is_imm32 (ins->inst_imm));
4300                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4301                         break;
4302                 case OP_AMD64_OR_MEMBASE_IMM:
4303                         g_assert (amd64_is_imm32 (ins->inst_imm));
4304                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4305                         break;
4306                 case OP_AMD64_XOR_MEMBASE_IMM:
4307                         g_assert (amd64_is_imm32 (ins->inst_imm));
4308                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4309                         break;
4310
4311                 case OP_BREAK:
4312                         amd64_breakpoint (code);
4313                         break;
4314                 case OP_RELAXED_NOP:
4315                         x86_prefix (code, X86_REP_PREFIX);
4316                         x86_nop (code);
4317                         break;
4318                 case OP_HARD_NOP:
4319                         x86_nop (code);
4320                         break;
4321                 case OP_NOP:
4322                 case OP_DUMMY_USE:
4323                 case OP_DUMMY_STORE:
4324                 case OP_DUMMY_ICONST:
4325                 case OP_DUMMY_R8CONST:
4326                 case OP_NOT_REACHED:
4327                 case OP_NOT_NULL:
4328                         break;
4329                 case OP_IL_SEQ_POINT:
4330                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4331                         break;
4332                 case OP_SEQ_POINT: {
4333                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4334                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4335                                 guint8 *label;
4336
4337                                 /* Load ss_tramp_var */
4338                                 /* This is equal to &ss_trampoline */
4339                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4340                                 /* Load the trampoline address */
4341                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4342                                 /* Call it if it is non-null */
4343                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4344                                 label = code;
4345                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4346                                 amd64_call_reg (code, AMD64_R11);
4347                                 amd64_patch (label, code);
4348                         }
4349
4350                         /*
4351                          * This is the address which is saved in seq points,
4352                          */
4353                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4354
4355                         if (cfg->compile_aot) {
4356                                 guint32 offset = code - cfg->native_code;
4357                                 guint32 val;
4358                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4359                                 guint8 *label;
4360
4361                                 /* Load info var */
4362                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4363                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4364                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4365                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4366                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4367                                 label = code;
4368                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4369                                 /* Call the trampoline */
4370                                 amd64_call_reg (code, AMD64_R11);
4371                                 amd64_patch (label, code);
4372                         } else {
4373                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4374                                 guint8 *label;
4375
4376                                 /*
4377                                  * Emit a test+branch against a constant, the constant will be overwritten
4378                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4379                                  */
4380                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4381                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4382                                 label = code;
4383                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4384
4385                                 g_assert (var);
4386                                 g_assert (var->opcode == OP_REGOFFSET);
4387                                 /* Load bp_tramp_var */
4388                                 /* This is equal to &bp_trampoline */
4389                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4390                                 /* Call the trampoline */
4391                                 amd64_call_membase (code, AMD64_R11, 0);
4392                                 amd64_patch (label, code);
4393                         }
4394                         /*
4395                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4396                          * to another IL offset.
4397                          */
4398                         x86_nop (code);
4399                         break;
4400                 }
4401                 case OP_ADDCC:
4402                 case OP_LADDCC:
4403                 case OP_LADD:
4404                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4405                         break;
4406                 case OP_ADC:
4407                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4408                         break;
4409                 case OP_ADD_IMM:
4410                 case OP_LADD_IMM:
4411                         g_assert (amd64_is_imm32 (ins->inst_imm));
4412                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4413                         break;
4414                 case OP_ADC_IMM:
4415                         g_assert (amd64_is_imm32 (ins->inst_imm));
4416                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4417                         break;
4418                 case OP_SUBCC:
4419                 case OP_LSUBCC:
4420                 case OP_LSUB:
4421                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4422                         break;
4423                 case OP_SBB:
4424                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4425                         break;
4426                 case OP_SUB_IMM:
4427                 case OP_LSUB_IMM:
4428                         g_assert (amd64_is_imm32 (ins->inst_imm));
4429                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4430                         break;
4431                 case OP_SBB_IMM:
4432                         g_assert (amd64_is_imm32 (ins->inst_imm));
4433                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4434                         break;
4435                 case OP_LAND:
4436                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4437                         break;
4438                 case OP_AND_IMM:
4439                 case OP_LAND_IMM:
4440                         g_assert (amd64_is_imm32 (ins->inst_imm));
4441                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4442                         break;
4443                 case OP_LMUL:
4444                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4445                         break;
4446                 case OP_MUL_IMM:
4447                 case OP_LMUL_IMM:
4448                 case OP_IMUL_IMM: {
4449                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4450
4451                         switch (ins->inst_imm) {
4452                         case 2:
4453                                 /* MOV r1, r2 */
4454                                 /* ADD r1, r1 */
4455                                 if (ins->dreg != ins->sreg1)
4456                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4457                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4458                                 break;
4459                         case 3:
4460                                 /* LEA r1, [r2 + r2*2] */
4461                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4462                                 break;
4463                         case 5:
4464                                 /* LEA r1, [r2 + r2*4] */
4465                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4466                                 break;
4467                         case 6:
4468                                 /* LEA r1, [r2 + r2*2] */
4469                                 /* ADD r1, r1          */
4470                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4471                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4472                                 break;
4473                         case 9:
4474                                 /* LEA r1, [r2 + r2*8] */
4475                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4476                                 break;
4477                         case 10:
4478                                 /* LEA r1, [r2 + r2*4] */
4479                                 /* ADD r1, r1          */
4480                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4481                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4482                                 break;
4483                         case 12:
4484                                 /* LEA r1, [r2 + r2*2] */
4485                                 /* SHL r1, 2           */
4486                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4487                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4488                                 break;
4489                         case 25:
4490                                 /* LEA r1, [r2 + r2*4] */
4491                                 /* LEA r1, [r1 + r1*4] */
4492                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4493                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4494                                 break;
4495                         case 100:
4496                                 /* LEA r1, [r2 + r2*4] */
4497                                 /* SHL r1, 2           */
4498                                 /* LEA r1, [r1 + r1*4] */
4499                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4500                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4501                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4502                                 break;
4503                         default:
4504                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4505                                 break;
4506                         }
4507                         break;
4508                 }
4509                 case OP_LDIV:
4510                 case OP_LREM:
4511 #if defined( __native_client_codegen__ )
4512                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4513                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4514 #endif
4515                         /* Regalloc magic makes the div/rem cases the same */
4516                         if (ins->sreg2 == AMD64_RDX) {
4517                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4518                                 amd64_cdq (code);
4519                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4520                         } else {
4521                                 amd64_cdq (code);
4522                                 amd64_div_reg (code, ins->sreg2, TRUE);
4523                         }
4524                         break;
4525                 case OP_LDIV_UN:
4526                 case OP_LREM_UN:
4527 #if defined( __native_client_codegen__ )
4528                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4529                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4530 #endif
4531                         if (ins->sreg2 == AMD64_RDX) {
4532                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4533                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4534                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4535                         } else {
4536                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4537                                 amd64_div_reg (code, ins->sreg2, FALSE);
4538                         }
4539                         break;
4540                 case OP_IDIV:
4541                 case OP_IREM:
4542 #if defined( __native_client_codegen__ )
4543                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4544                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4545 #endif
4546                         if (ins->sreg2 == AMD64_RDX) {
4547                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4548                                 amd64_cdq_size (code, 4);
4549                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4550                         } else {
4551                                 amd64_cdq_size (code, 4);
4552                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4553                         }
4554                         break;
4555                 case OP_IDIV_UN:
4556                 case OP_IREM_UN:
4557 #if defined( __native_client_codegen__ )
4558                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4559                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4560 #endif
4561                         if (ins->sreg2 == AMD64_RDX) {
4562                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4563                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4564                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4565                         } else {
4566                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4567                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4568                         }
4569                         break;
4570                 case OP_LMUL_OVF:
4571                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4572                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4573                         break;
4574                 case OP_LOR:
4575                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4576                         break;
4577                 case OP_OR_IMM:
4578                 case OP_LOR_IMM:
4579                         g_assert (amd64_is_imm32 (ins->inst_imm));
4580                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4581                         break;
4582                 case OP_LXOR:
4583                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4584                         break;
4585                 case OP_XOR_IMM:
4586                 case OP_LXOR_IMM:
4587                         g_assert (amd64_is_imm32 (ins->inst_imm));
4588                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4589                         break;
4590                 case OP_LSHL:
4591                         g_assert (ins->sreg2 == AMD64_RCX);
4592                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4593                         break;
4594                 case OP_LSHR:
4595                         g_assert (ins->sreg2 == AMD64_RCX);
4596                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4597                         break;
4598                 case OP_SHR_IMM:
4599                 case OP_LSHR_IMM:
4600                         g_assert (amd64_is_imm32 (ins->inst_imm));
4601                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4602                         break;
4603                 case OP_SHR_UN_IMM:
4604                         g_assert (amd64_is_imm32 (ins->inst_imm));
4605                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4606                         break;
4607                 case OP_LSHR_UN_IMM:
4608                         g_assert (amd64_is_imm32 (ins->inst_imm));
4609                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4610                         break;
4611                 case OP_LSHR_UN:
4612                         g_assert (ins->sreg2 == AMD64_RCX);
4613                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4614                         break;
4615                 case OP_SHL_IMM:
4616                 case OP_LSHL_IMM:
4617                         g_assert (amd64_is_imm32 (ins->inst_imm));
4618                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4619                         break;
4620
4621                 case OP_IADDCC:
4622                 case OP_IADD:
4623                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4624                         break;
4625                 case OP_IADC:
4626                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4627                         break;
4628                 case OP_IADD_IMM:
4629                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4630                         break;
4631                 case OP_IADC_IMM:
4632                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4633                         break;
4634                 case OP_ISUBCC:
4635                 case OP_ISUB:
4636                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4637                         break;
4638                 case OP_ISBB:
4639                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4640                         break;
4641                 case OP_ISUB_IMM:
4642                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4643                         break;
4644                 case OP_ISBB_IMM:
4645                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4646                         break;
4647                 case OP_IAND:
4648                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4649                         break;
4650                 case OP_IAND_IMM:
4651                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4652                         break;
4653                 case OP_IOR:
4654                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4655                         break;
4656                 case OP_IOR_IMM:
4657                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4658                         break;
4659                 case OP_IXOR:
4660                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4661                         break;
4662                 case OP_IXOR_IMM:
4663                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4664                         break;
4665                 case OP_INEG:
4666                         amd64_neg_reg_size (code, ins->sreg1, 4);
4667                         break;
4668                 case OP_INOT:
4669                         amd64_not_reg_size (code, ins->sreg1, 4);
4670                         break;
4671                 case OP_ISHL:
4672                         g_assert (ins->sreg2 == AMD64_RCX);
4673                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4674                         break;
4675                 case OP_ISHR:
4676                         g_assert (ins->sreg2 == AMD64_RCX);
4677                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4678                         break;
4679                 case OP_ISHR_IMM:
4680                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4681                         break;
4682                 case OP_ISHR_UN_IMM:
4683                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4684                         break;
4685                 case OP_ISHR_UN:
4686                         g_assert (ins->sreg2 == AMD64_RCX);
4687                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4688                         break;
4689                 case OP_ISHL_IMM:
4690                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4691                         break;
4692                 case OP_IMUL:
4693                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4694                         break;
4695                 case OP_IMUL_OVF:
4696                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4697                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4698                         break;
4699                 case OP_IMUL_OVF_UN:
4700                 case OP_LMUL_OVF_UN: {
4701                         /* the mul operation and the exception check should most likely be split */
4702                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4703                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4704                         /*g_assert (ins->sreg2 == X86_EAX);
4705                         g_assert (ins->dreg == X86_EAX);*/
4706                         if (ins->sreg2 == X86_EAX) {
4707                                 non_eax_reg = ins->sreg1;
4708                         } else if (ins->sreg1 == X86_EAX) {
4709                                 non_eax_reg = ins->sreg2;
4710                         } else {
4711                                 /* no need to save since we're going to store to it anyway */
4712                                 if (ins->dreg != X86_EAX) {
4713                                         saved_eax = TRUE;
4714                                         amd64_push_reg (code, X86_EAX);
4715                                 }
4716                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4717                                 non_eax_reg = ins->sreg2;
4718                         }
4719                         if (ins->dreg == X86_EDX) {
4720                                 if (!saved_eax) {
4721                                         saved_eax = TRUE;
4722                                         amd64_push_reg (code, X86_EAX);
4723                                 }
4724                         } else {
4725                                 saved_edx = TRUE;
4726                                 amd64_push_reg (code, X86_EDX);
4727                         }
4728                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4729                         /* save before the check since pop and mov don't change the flags */
4730                         if (ins->dreg != X86_EAX)
4731                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4732                         if (saved_edx)
4733                                 amd64_pop_reg (code, X86_EDX);
4734                         if (saved_eax)
4735                                 amd64_pop_reg (code, X86_EAX);
4736                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4737                         break;
4738                 }
4739                 case OP_ICOMPARE:
4740                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4741                         break;
4742                 case OP_ICOMPARE_IMM:
4743                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4744                         break;
4745                 case OP_IBEQ:
4746                 case OP_IBLT:
4747                 case OP_IBGT:
4748                 case OP_IBGE:
4749                 case OP_IBLE:
4750                 case OP_LBEQ:
4751                 case OP_LBLT:
4752                 case OP_LBGT:
4753                 case OP_LBGE:
4754                 case OP_LBLE:
4755                 case OP_IBNE_UN:
4756                 case OP_IBLT_UN:
4757                 case OP_IBGT_UN:
4758                 case OP_IBGE_UN:
4759                 case OP_IBLE_UN:
4760                 case OP_LBNE_UN:
4761                 case OP_LBLT_UN:
4762                 case OP_LBGT_UN:
4763                 case OP_LBGE_UN:
4764                 case OP_LBLE_UN:
4765                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4766                         break;
4767
4768                 case OP_CMOV_IEQ:
4769                 case OP_CMOV_IGE:
4770                 case OP_CMOV_IGT:
4771                 case OP_CMOV_ILE:
4772                 case OP_CMOV_ILT:
4773                 case OP_CMOV_INE_UN:
4774                 case OP_CMOV_IGE_UN:
4775                 case OP_CMOV_IGT_UN:
4776                 case OP_CMOV_ILE_UN:
4777                 case OP_CMOV_ILT_UN:
4778                 case OP_CMOV_LEQ:
4779                 case OP_CMOV_LGE:
4780                 case OP_CMOV_LGT:
4781                 case OP_CMOV_LLE:
4782                 case OP_CMOV_LLT:
4783                 case OP_CMOV_LNE_UN:
4784                 case OP_CMOV_LGE_UN:
4785                 case OP_CMOV_LGT_UN:
4786                 case OP_CMOV_LLE_UN:
4787                 case OP_CMOV_LLT_UN:
4788                         g_assert (ins->dreg == ins->sreg1);
4789                         /* This needs to operate on 64 bit values */
4790                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4791                         break;
4792
4793                 case OP_LNOT:
4794                         amd64_not_reg (code, ins->sreg1);
4795                         break;
4796                 case OP_LNEG:
4797                         amd64_neg_reg (code, ins->sreg1);
4798                         break;
4799
4800                 case OP_ICONST:
4801                 case OP_I8CONST:
4802                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4803                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4804                         else
4805                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4806                         break;
4807                 case OP_AOTCONST:
4808                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4809                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4810                         break;
4811                 case OP_JUMP_TABLE:
4812                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4813                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4814                         break;
4815                 case OP_MOVE:
4816                         if (ins->dreg != ins->sreg1)
4817                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4818                         break;
4819                 case OP_AMD64_SET_XMMREG_R4: {
4820                         if (cfg->r4fp) {
4821                                 if (ins->dreg != ins->sreg1)
4822                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4823                         } else {
4824                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4825                         }
4826                         break;
4827                 }
4828                 case OP_AMD64_SET_XMMREG_R8: {
4829                         if (ins->dreg != ins->sreg1)
4830                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4831                         break;
4832                 }
4833                 case OP_TAILCALL: {
4834                         MonoCallInst *call = (MonoCallInst*)ins;
4835                         int i, save_area_offset;
4836
4837                         g_assert (!cfg->method->save_lmf);
4838
4839                         /* Restore callee saved registers */
4840                         save_area_offset = cfg->arch.reg_save_area_offset;
4841                         for (i = 0; i < AMD64_NREG; ++i)
4842                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4843                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4844                                         save_area_offset += 8;
4845                                 }
4846
4847                         if (cfg->arch.omit_fp) {
4848                                 if (cfg->arch.stack_alloc_size)
4849                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4850                                 // FIXME:
4851                                 if (call->stack_usage)
4852                                         NOT_IMPLEMENTED;
4853                         } else {
4854                                 /* Copy arguments on the stack to our argument area */
4855                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4856                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4857                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4858                                 }
4859
4860                                 amd64_leave (code);
4861                         }
4862
4863                         offset = code - cfg->native_code;
4864                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4865                         if (cfg->compile_aot)
4866                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4867                         else
4868                                 amd64_set_reg_template (code, AMD64_R11);
4869                         amd64_jump_reg (code, AMD64_R11);
4870                         ins->flags |= MONO_INST_GC_CALLSITE;
4871                         ins->backend.pc_offset = code - cfg->native_code;
4872                         break;
4873                 }
4874                 case OP_CHECK_THIS:
4875                         /* ensure ins->sreg1 is not NULL */
4876                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4877                         break;
4878                 case OP_ARGLIST: {
4879                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4880                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4881                         break;
4882                 }
4883                 case OP_CALL:
4884                 case OP_FCALL:
4885                 case OP_RCALL:
4886                 case OP_LCALL:
4887                 case OP_VCALL:
4888                 case OP_VCALL2:
4889                 case OP_VOIDCALL:
4890                         call = (MonoCallInst*)ins;
4891                         /*
4892                          * The AMD64 ABI forces callers to know about varargs.
4893                          */
4894                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4895                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4896                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4897                                 /*
4898                                  * Since the unmanaged calling convention doesn't contain a
4899                                  * 'vararg' entry, we have to treat every pinvoke call as a
4900                                  * potential vararg call.
4901                                  */
4902                                 guint32 nregs, i;
4903                                 nregs = 0;
4904                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4905                                         if (call->used_fregs & (1 << i))
4906                                                 nregs ++;
4907                                 if (!nregs)
4908                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4909                                 else
4910                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4911                         }
4912
4913                         if (ins->flags & MONO_INST_HAS_METHOD)
4914                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4915                         else
4916                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4917                         ins->flags |= MONO_INST_GC_CALLSITE;
4918                         ins->backend.pc_offset = code - cfg->native_code;
4919                         code = emit_move_return_value (cfg, ins, code);
4920                         break;
4921                 case OP_FCALL_REG:
4922                 case OP_RCALL_REG:
4923                 case OP_LCALL_REG:
4924                 case OP_VCALL_REG:
4925                 case OP_VCALL2_REG:
4926                 case OP_VOIDCALL_REG:
4927                 case OP_CALL_REG:
4928                         call = (MonoCallInst*)ins;
4929
4930                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4931                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4932                                 ins->sreg1 = AMD64_R11;
4933                         }
4934
4935                         /*
4936                          * The AMD64 ABI forces callers to know about varargs.
4937                          */
4938                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4939                                 if (ins->sreg1 == AMD64_RAX) {
4940                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4941                                         ins->sreg1 = AMD64_R11;
4942                                 }
4943                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4944                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4945                                 /*
4946                                  * Since the unmanaged calling convention doesn't contain a
4947                                  * 'vararg' entry, we have to treat every pinvoke call as a
4948                                  * potential vararg call.
4949                                  */
4950                                 guint32 nregs, i;
4951                                 nregs = 0;
4952                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4953                                         if (call->used_fregs & (1 << i))
4954                                                 nregs ++;
4955                                 if (ins->sreg1 == AMD64_RAX) {
4956                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4957                                         ins->sreg1 = AMD64_R11;
4958                                 }
4959                                 if (!nregs)
4960                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4961                                 else
4962                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4963                         }
4964
4965                         amd64_call_reg (code, ins->sreg1);
4966                         ins->flags |= MONO_INST_GC_CALLSITE;
4967                         ins->backend.pc_offset = code - cfg->native_code;
4968                         code = emit_move_return_value (cfg, ins, code);
4969                         break;
4970                 case OP_FCALL_MEMBASE:
4971                 case OP_RCALL_MEMBASE:
4972                 case OP_LCALL_MEMBASE:
4973                 case OP_VCALL_MEMBASE:
4974                 case OP_VCALL2_MEMBASE:
4975                 case OP_VOIDCALL_MEMBASE:
4976                 case OP_CALL_MEMBASE:
4977                         call = (MonoCallInst*)ins;
4978
4979                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4980                         ins->flags |= MONO_INST_GC_CALLSITE;
4981                         ins->backend.pc_offset = code - cfg->native_code;
4982                         code = emit_move_return_value (cfg, ins, code);
4983                         break;
4984                 case OP_DYN_CALL: {
4985                         int i;
4986                         MonoInst *var = cfg->dyn_call_var;
4987
4988                         g_assert (var->opcode == OP_REGOFFSET);
4989
4990                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4991                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4992                         /* r10 = ftn */
4993                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4994
4995                         /* Save args buffer */
4996                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4997
4998                         /* Set argument registers */
4999                         for (i = 0; i < PARAM_REGS; ++i)
5000                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
5001
5002                         /* Make the call */
5003                         amd64_call_reg (code, AMD64_R10);
5004
5005                         ins->flags |= MONO_INST_GC_CALLSITE;
5006                         ins->backend.pc_offset = code - cfg->native_code;
5007
5008                         /* Save result */
5009                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5010                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5011                         break;
5012                 }
5013                 case OP_AMD64_SAVE_SP_TO_LMF: {
5014                         MonoInst *lmf_var = cfg->lmf_var;
5015                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5016                         break;
5017                 }
5018                 case OP_X86_PUSH:
5019                         g_assert_not_reached ();
5020                         amd64_push_reg (code, ins->sreg1);
5021                         break;
5022                 case OP_X86_PUSH_IMM:
5023                         g_assert_not_reached ();
5024                         g_assert (amd64_is_imm32 (ins->inst_imm));
5025                         amd64_push_imm (code, ins->inst_imm);
5026                         break;
5027                 case OP_X86_PUSH_MEMBASE:
5028                         g_assert_not_reached ();
5029                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5030                         break;
5031                 case OP_X86_PUSH_OBJ: {
5032                         int size = ALIGN_TO (ins->inst_imm, 8);
5033
5034                         g_assert_not_reached ();
5035
5036                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5037                         amd64_push_reg (code, AMD64_RDI);
5038                         amd64_push_reg (code, AMD64_RSI);
5039                         amd64_push_reg (code, AMD64_RCX);
5040                         if (ins->inst_offset)
5041                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5042                         else
5043                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5044                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5045                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5046                         amd64_cld (code);
5047                         amd64_prefix (code, X86_REP_PREFIX);
5048                         amd64_movsd (code);
5049                         amd64_pop_reg (code, AMD64_RCX);
5050                         amd64_pop_reg (code, AMD64_RSI);
5051                         amd64_pop_reg (code, AMD64_RDI);
5052                         break;
5053                 }
5054                 case OP_GENERIC_CLASS_INIT: {
5055                         static int byte_offset = -1;
5056                         static guint8 bitmask;
5057                         guint8 *jump;
5058
5059                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5060
5061                         if (byte_offset < 0)
5062                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5063
5064                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5065                         jump = code;
5066                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
5067
5068                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5069                         ins->flags |= MONO_INST_GC_CALLSITE;
5070                         ins->backend.pc_offset = code - cfg->native_code;
5071
5072                         x86_patch (jump, code);
5073                         break;
5074                 }
5075
5076                 case OP_X86_LEA:
5077                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5078                         break;
5079                 case OP_X86_LEA_MEMBASE:
5080                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5081                         break;
5082                 case OP_X86_XCHG:
5083                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5084                         break;
5085                 case OP_LOCALLOC:
5086                         /* keep alignment */
5087                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5088                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5089                         code = mono_emit_stack_alloc (cfg, code, ins);
5090                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5091                         if (cfg->param_area)
5092                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5093                         break;
5094                 case OP_LOCALLOC_IMM: {
5095                         guint32 size = ins->inst_imm;
5096                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5097
5098                         if (ins->flags & MONO_INST_INIT) {
5099                                 if (size < 64) {
5100                                         int i;
5101
5102                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5103                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5104
5105                                         for (i = 0; i < size; i += 8)
5106                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5107                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5108                                 } else {
5109                                         amd64_mov_reg_imm (code, ins->dreg, size);
5110                                         ins->sreg1 = ins->dreg;
5111
5112                                         code = mono_emit_stack_alloc (cfg, code, ins);
5113                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5114                                 }
5115                         } else {
5116                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5117                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5118                         }
5119                         if (cfg->param_area)
5120                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5121                         break;
5122                 }
5123                 case OP_THROW: {
5124                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5125                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5126                                              (gpointer)"mono_arch_throw_exception", FALSE);
5127                         ins->flags |= MONO_INST_GC_CALLSITE;
5128                         ins->backend.pc_offset = code - cfg->native_code;
5129                         break;
5130                 }
5131                 case OP_RETHROW: {
5132                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5133                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5134                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5135                         ins->flags |= MONO_INST_GC_CALLSITE;
5136                         ins->backend.pc_offset = code - cfg->native_code;
5137                         break;
5138                 }
5139                 case OP_CALL_HANDLER:
5140                         /* Align stack */
5141                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5142                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5143                         amd64_call_imm (code, 0);
5144                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5145                         /* Restore stack alignment */
5146                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5147                         break;
5148                 case OP_START_HANDLER: {
5149                         /* Even though we're saving RSP, use sizeof */
5150                         /* gpointer because spvar is of type IntPtr */
5151                         /* see: mono_create_spvar_for_region */
5152                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5153                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5154
5155                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5156                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5157                                 cfg->param_area) {
5158                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5159                         }
5160                         break;
5161                 }
5162                 case OP_ENDFINALLY: {
5163                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5164                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5165                         amd64_ret (code);
5166                         break;
5167                 }
5168                 case OP_ENDFILTER: {
5169                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5170                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5171                         /* The local allocator will put the result into RAX */
5172                         amd64_ret (code);
5173                         break;
5174                 }
5175                 case OP_GET_EX_OBJ:
5176                         if (ins->dreg != AMD64_RAX)
5177                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5178                         break;
5179                 case OP_LABEL:
5180                         ins->inst_c0 = code - cfg->native_code;
5181                         break;
5182                 case OP_BR:
5183                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5184                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5185                         //break;
5186                                 if (ins->inst_target_bb->native_offset) {
5187                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5188                                 } else {
5189                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5190                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5191                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5192                                                 x86_jump8 (code, 0);
5193                                         else
5194                                                 x86_jump32 (code, 0);
5195                         }
5196                         break;
5197                 case OP_BR_REG:
5198                         amd64_jump_reg (code, ins->sreg1);
5199                         break;
5200                 case OP_ICNEQ:
5201                 case OP_ICGE:
5202                 case OP_ICLE:
5203                 case OP_ICGE_UN:
5204                 case OP_ICLE_UN:
5205
5206                 case OP_CEQ:
5207                 case OP_LCEQ:
5208                 case OP_ICEQ:
5209                 case OP_CLT:
5210                 case OP_LCLT:
5211                 case OP_ICLT:
5212                 case OP_CGT:
5213                 case OP_ICGT:
5214                 case OP_LCGT:
5215                 case OP_CLT_UN:
5216                 case OP_LCLT_UN:
5217                 case OP_ICLT_UN:
5218                 case OP_CGT_UN:
5219                 case OP_LCGT_UN:
5220                 case OP_ICGT_UN:
5221                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5222                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5223                         break;
5224                 case OP_COND_EXC_EQ:
5225                 case OP_COND_EXC_NE_UN:
5226                 case OP_COND_EXC_LT:
5227                 case OP_COND_EXC_LT_UN:
5228                 case OP_COND_EXC_GT:
5229                 case OP_COND_EXC_GT_UN:
5230                 case OP_COND_EXC_GE:
5231                 case OP_COND_EXC_GE_UN:
5232                 case OP_COND_EXC_LE:
5233                 case OP_COND_EXC_LE_UN:
5234                 case OP_COND_EXC_IEQ:
5235                 case OP_COND_EXC_INE_UN:
5236                 case OP_COND_EXC_ILT:
5237                 case OP_COND_EXC_ILT_UN:
5238                 case OP_COND_EXC_IGT:
5239                 case OP_COND_EXC_IGT_UN:
5240                 case OP_COND_EXC_IGE:
5241                 case OP_COND_EXC_IGE_UN:
5242                 case OP_COND_EXC_ILE:
5243                 case OP_COND_EXC_ILE_UN:
5244                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5245                         break;
5246                 case OP_COND_EXC_OV:
5247                 case OP_COND_EXC_NO:
5248                 case OP_COND_EXC_C:
5249                 case OP_COND_EXC_NC:
5250                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5251                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5252                         break;
5253                 case OP_COND_EXC_IOV:
5254                 case OP_COND_EXC_INO:
5255                 case OP_COND_EXC_IC:
5256                 case OP_COND_EXC_INC:
5257                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5258                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5259                         break;
5260
5261                 /* floating point opcodes */
5262                 case OP_R8CONST: {
5263                         double d = *(double *)ins->inst_p0;
5264
5265                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5266                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5267                         }
5268                         else {
5269                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5270                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5271                         }
5272                         break;
5273                 }
5274                 case OP_R4CONST: {
5275                         float f = *(float *)ins->inst_p0;
5276
5277                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5278                                 if (cfg->r4fp)
5279                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5280                                 else
5281                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5282                         }
5283                         else {
5284                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5285                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5286                                 if (!cfg->r4fp)
5287                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5288                         }
5289                         break;
5290                 }
5291                 case OP_STORER8_MEMBASE_REG:
5292                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5293                         break;
5294                 case OP_LOADR8_MEMBASE:
5295                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5296                         break;
5297                 case OP_STORER4_MEMBASE_REG:
5298                         if (cfg->r4fp) {
5299                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5300                         } else {
5301                                 /* This requires a double->single conversion */
5302                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5303                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5304                         }
5305                         break;
5306                 case OP_LOADR4_MEMBASE:
5307                         if (cfg->r4fp) {
5308                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5309                         } else {
5310                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5311                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5312                         }
5313                         break;
5314                 case OP_ICONV_TO_R4:
5315                         if (cfg->r4fp) {
5316                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5317                         } else {
5318                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5319                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5320                         }
5321                         break;
5322                 case OP_ICONV_TO_R8:
5323                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5324                         break;
5325                 case OP_LCONV_TO_R4:
5326                         if (cfg->r4fp) {
5327                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5328                         } else {
5329                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5330                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5331                         }
5332                         break;
5333                 case OP_LCONV_TO_R8:
5334                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5335                         break;
5336                 case OP_FCONV_TO_R4:
5337                         if (cfg->r4fp) {
5338                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5339                         } else {
5340                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5341                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5342                         }
5343                         break;
5344                 case OP_FCONV_TO_I1:
5345                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5346                         break;
5347                 case OP_FCONV_TO_U1:
5348                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5349                         break;
5350                 case OP_FCONV_TO_I2:
5351                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5352                         break;
5353                 case OP_FCONV_TO_U2:
5354                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5355                         break;
5356                 case OP_FCONV_TO_U4:
5357                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5358                         break;
5359                 case OP_FCONV_TO_I4:
5360                 case OP_FCONV_TO_I:
5361                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5362                         break;
5363                 case OP_FCONV_TO_I8:
5364                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5365                         break;
5366
5367                 case OP_RCONV_TO_I1:
5368                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5369                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5370                         break;
5371                 case OP_RCONV_TO_U1:
5372                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5373                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5374                         break;
5375                 case OP_RCONV_TO_I2:
5376                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5377                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5378                         break;
5379                 case OP_RCONV_TO_U2:
5380                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5381                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5382                         break;
5383                 case OP_RCONV_TO_I4:
5384                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5385                         break;
5386                 case OP_RCONV_TO_U4:
5387                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5388                         break;
5389                 case OP_RCONV_TO_I8:
5390                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5391                         break;
5392                 case OP_RCONV_TO_R8:
5393                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5394                         break;
5395                 case OP_RCONV_TO_R4:
5396                         if (ins->dreg != ins->sreg1)
5397                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5398                         break;
5399
5400                 case OP_LCONV_TO_R_UN: {
5401                         guint8 *br [2];
5402
5403                         /* Based on gcc code */
5404                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5405                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5406
5407                         /* Positive case */
5408                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5409                         br [1] = code; x86_jump8 (code, 0);
5410                         amd64_patch (br [0], code);
5411
5412                         /* Negative case */
5413                         /* Save to the red zone */
5414                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5415                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5416                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5417                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5418                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5419                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5420                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5421                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5422                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5423                         /* Restore */
5424                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5425                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5426                         amd64_patch (br [1], code);
5427                         break;
5428                 }
5429                 case OP_LCONV_TO_OVF_U4:
5430                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5431                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5432                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5433                         break;
5434                 case OP_LCONV_TO_OVF_I4_UN:
5435                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5436                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5437                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5438                         break;
5439                 case OP_FMOVE:
5440                         if (ins->dreg != ins->sreg1)
5441                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5442                         break;
5443                 case OP_RMOVE:
5444                         if (ins->dreg != ins->sreg1)
5445                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5446                         break;
5447                 case OP_MOVE_F_TO_I4:
5448                         if (cfg->r4fp) {
5449                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5450                         } else {
5451                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5452                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5453                         }
5454                         break;
5455                 case OP_MOVE_I4_TO_F:
5456                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5457                         if (!cfg->r4fp)
5458                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5459                         break;
5460                 case OP_MOVE_F_TO_I8:
5461                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5462                         break;
5463                 case OP_MOVE_I8_TO_F:
5464                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5465                         break;
5466                 case OP_FADD:
5467                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5468                         break;
5469                 case OP_FSUB:
5470                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5471                         break;
5472                 case OP_FMUL:
5473                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5474                         break;
5475                 case OP_FDIV:
5476                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5477                         break;
5478                 case OP_FNEG: {
5479                         static double r8_0 = -0.0;
5480
5481                         g_assert (ins->sreg1 == ins->dreg);
5482
5483                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5484                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5485                         break;
5486                 }
5487                 case OP_SIN:
5488                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5489                         break;
5490                 case OP_COS:
5491                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5492                         break;
5493                 case OP_ABS: {
5494                         static guint64 d = 0x7fffffffffffffffUL;
5495
5496                         g_assert (ins->sreg1 == ins->dreg);
5497
5498                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5499                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5500                         break;
5501                 }
5502                 case OP_SQRT:
5503                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5504                         break;
5505
5506                 case OP_RADD:
5507                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5508                         break;
5509                 case OP_RSUB:
5510                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5511                         break;
5512                 case OP_RMUL:
5513                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5514                         break;
5515                 case OP_RDIV:
5516                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5517                         break;
5518                 case OP_RNEG: {
5519                         static float r4_0 = -0.0;
5520
5521                         g_assert (ins->sreg1 == ins->dreg);
5522
5523                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5524                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5525                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5526                         break;
5527                 }
5528
5529                 case OP_IMIN:
5530                         g_assert (cfg->opt & MONO_OPT_CMOV);
5531                         g_assert (ins->dreg == ins->sreg1);
5532                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5533                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5534                         break;
5535                 case OP_IMIN_UN:
5536                         g_assert (cfg->opt & MONO_OPT_CMOV);
5537                         g_assert (ins->dreg == ins->sreg1);
5538                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5539                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5540                         break;
5541                 case OP_IMAX:
5542                         g_assert (cfg->opt & MONO_OPT_CMOV);
5543                         g_assert (ins->dreg == ins->sreg1);
5544                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5545                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5546                         break;
5547                 case OP_IMAX_UN:
5548                         g_assert (cfg->opt & MONO_OPT_CMOV);
5549                         g_assert (ins->dreg == ins->sreg1);
5550                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5551                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5552                         break;
5553                 case OP_LMIN:
5554                         g_assert (cfg->opt & MONO_OPT_CMOV);
5555                         g_assert (ins->dreg == ins->sreg1);
5556                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5557                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5558                         break;
5559                 case OP_LMIN_UN:
5560                         g_assert (cfg->opt & MONO_OPT_CMOV);
5561                         g_assert (ins->dreg == ins->sreg1);
5562                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5563                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5564                         break;
5565                 case OP_LMAX:
5566                         g_assert (cfg->opt & MONO_OPT_CMOV);
5567                         g_assert (ins->dreg == ins->sreg1);
5568                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5569                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5570                         break;
5571                 case OP_LMAX_UN:
5572                         g_assert (cfg->opt & MONO_OPT_CMOV);
5573                         g_assert (ins->dreg == ins->sreg1);
5574                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5575                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5576                         break;
5577                 case OP_X86_FPOP:
5578                         break;
5579                 case OP_FCOMPARE:
5580                         /*
5581                          * The two arguments are swapped because the fbranch instructions
5582                          * depend on this for the non-sse case to work.
5583                          */
5584                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5585                         break;
5586                 case OP_RCOMPARE:
5587                         /*
5588                          * FIXME: Get rid of this.
5589                          * The two arguments are swapped because the fbranch instructions
5590                          * depend on this for the non-sse case to work.
5591                          */
5592                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5593                         break;
5594                 case OP_FCNEQ:
5595                 case OP_FCEQ: {
5596                         /* zeroing the register at the start results in
5597                          * shorter and faster code (we can also remove the widening op)
5598                          */
5599                         guchar *unordered_check;
5600
5601                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5602                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5603                         unordered_check = code;
5604                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5605
5606                         if (ins->opcode == OP_FCEQ) {
5607                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5608                                 amd64_patch (unordered_check, code);
5609                         } else {
5610                                 guchar *jump_to_end;
5611                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5612                                 jump_to_end = code;
5613                                 x86_jump8 (code, 0);
5614                                 amd64_patch (unordered_check, code);
5615                                 amd64_inc_reg (code, ins->dreg);
5616                                 amd64_patch (jump_to_end, code);
5617                         }
5618                         break;
5619                 }
5620                 case OP_FCLT:
5621                 case OP_FCLT_UN: {
5622                         /* zeroing the register at the start results in
5623                          * shorter and faster code (we can also remove the widening op)
5624                          */
5625                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5626                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5627                         if (ins->opcode == OP_FCLT_UN) {
5628                                 guchar *unordered_check = code;
5629                                 guchar *jump_to_end;
5630                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5631                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5632                                 jump_to_end = code;
5633                                 x86_jump8 (code, 0);
5634                                 amd64_patch (unordered_check, code);
5635                                 amd64_inc_reg (code, ins->dreg);
5636                                 amd64_patch (jump_to_end, code);
5637                         } else {
5638                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5639                         }
5640                         break;
5641                 }
5642                 case OP_FCLE: {
5643                         guchar *unordered_check;
5644                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5645                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5646                         unordered_check = code;
5647                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5648                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5649                         amd64_patch (unordered_check, code);
5650                         break;
5651                 }
5652                 case OP_FCGT:
5653                 case OP_FCGT_UN: {
5654                         /* zeroing the register at the start results in
5655                          * shorter and faster code (we can also remove the widening op)
5656                          */
5657                         guchar *unordered_check;
5658
5659                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5660                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5661                         if (ins->opcode == OP_FCGT) {
5662                                 unordered_check = code;
5663                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5664                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5665                                 amd64_patch (unordered_check, code);
5666                         } else {
5667                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5668                         }
5669                         break;
5670                 }
5671                 case OP_FCGE: {
5672                         guchar *unordered_check;
5673                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5674                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5675                         unordered_check = code;
5676                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5677                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5678                         amd64_patch (unordered_check, code);
5679                         break;
5680                 }
5681
5682                 case OP_RCEQ:
5683                 case OP_RCGT:
5684                 case OP_RCLT:
5685                 case OP_RCLT_UN:
5686                 case OP_RCGT_UN: {
5687                         int x86_cond;
5688                         gboolean unordered = FALSE;
5689
5690                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5691                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5692
5693                         switch (ins->opcode) {
5694                         case OP_RCEQ:
5695                                 x86_cond = X86_CC_EQ;
5696                                 break;
5697                         case OP_RCGT:
5698                                 x86_cond = X86_CC_LT;
5699                                 break;
5700                         case OP_RCLT:
5701                                 x86_cond = X86_CC_GT;
5702                                 break;
5703                         case OP_RCLT_UN:
5704                                 x86_cond = X86_CC_GT;
5705                                 unordered = TRUE;
5706                                 break;
5707                         case OP_RCGT_UN:
5708                                 x86_cond = X86_CC_LT;
5709                                 unordered = TRUE;
5710                                 break;
5711                         default:
5712                                 g_assert_not_reached ();
5713                                 break;
5714                         }
5715
5716                         if (unordered) {
5717                                 guchar *unordered_check;
5718                                 guchar *jump_to_end;
5719
5720                                 unordered_check = code;
5721                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5722                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5723                                 jump_to_end = code;
5724                                 x86_jump8 (code, 0);
5725                                 amd64_patch (unordered_check, code);
5726                                 amd64_inc_reg (code, ins->dreg);
5727                                 amd64_patch (jump_to_end, code);
5728                         } else {
5729                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5730                         }
5731                         break;
5732                 }
5733                 case OP_FCLT_MEMBASE:
5734                 case OP_FCGT_MEMBASE:
5735                 case OP_FCLT_UN_MEMBASE:
5736                 case OP_FCGT_UN_MEMBASE:
5737                 case OP_FCEQ_MEMBASE: {
5738                         guchar *unordered_check, *jump_to_end;
5739                         int x86_cond;
5740
5741                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5742                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5743
5744                         switch (ins->opcode) {
5745                         case OP_FCEQ_MEMBASE:
5746                                 x86_cond = X86_CC_EQ;
5747                                 break;
5748                         case OP_FCLT_MEMBASE:
5749                         case OP_FCLT_UN_MEMBASE:
5750                                 x86_cond = X86_CC_LT;
5751                                 break;
5752                         case OP_FCGT_MEMBASE:
5753                         case OP_FCGT_UN_MEMBASE:
5754                                 x86_cond = X86_CC_GT;
5755                                 break;
5756                         default:
5757                                 g_assert_not_reached ();
5758                         }
5759
5760                         unordered_check = code;
5761                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5762                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5763
5764                         switch (ins->opcode) {
5765                         case OP_FCEQ_MEMBASE:
5766                         case OP_FCLT_MEMBASE:
5767                         case OP_FCGT_MEMBASE:
5768                                 amd64_patch (unordered_check, code);
5769                                 break;
5770                         case OP_FCLT_UN_MEMBASE:
5771                         case OP_FCGT_UN_MEMBASE:
5772                                 jump_to_end = code;
5773                                 x86_jump8 (code, 0);
5774                                 amd64_patch (unordered_check, code);
5775                                 amd64_inc_reg (code, ins->dreg);
5776                                 amd64_patch (jump_to_end, code);
5777                                 break;
5778                         default:
5779                                 break;
5780                         }
5781                         break;
5782                 }
5783                 case OP_FBEQ: {
5784                         guchar *jump = code;
5785                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5786                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5787                         amd64_patch (jump, code);
5788                         break;
5789                 }
5790                 case OP_FBNE_UN:
5791                         /* Branch if C013 != 100 */
5792                         /* branch if !ZF or (PF|CF) */
5793                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5794                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5795                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5796                         break;
5797                 case OP_FBLT:
5798                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5799                         break;
5800                 case OP_FBLT_UN:
5801                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5802                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5803                         break;
5804                 case OP_FBGT:
5805                 case OP_FBGT_UN:
5806                         if (ins->opcode == OP_FBGT) {
5807                                 guchar *br1;
5808
5809                                 /* skip branch if C1=1 */
5810                                 br1 = code;
5811                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5812                                 /* branch if (C0 | C3) = 1 */
5813                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5814                                 amd64_patch (br1, code);
5815                                 break;
5816                         } else {
5817                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5818                         }
5819                         break;
5820                 case OP_FBGE: {
5821                         /* Branch if C013 == 100 or 001 */
5822                         guchar *br1;
5823
5824                         /* skip branch if C1=1 */
5825                         br1 = code;
5826                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5827                         /* branch if (C0 | C3) = 1 */
5828                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5829                         amd64_patch (br1, code);
5830                         break;
5831                 }
5832                 case OP_FBGE_UN:
5833                         /* Branch if C013 == 000 */
5834                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5835                         break;
5836                 case OP_FBLE: {
5837                         /* Branch if C013=000 or 100 */
5838                         guchar *br1;
5839
5840                         /* skip branch if C1=1 */
5841                         br1 = code;
5842                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5843                         /* branch if C0=0 */
5844                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5845                         amd64_patch (br1, code);
5846                         break;
5847                 }
5848                 case OP_FBLE_UN:
5849                         /* Branch if C013 != 001 */
5850                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5851                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5852                         break;
5853                 case OP_CKFINITE:
5854                         /* Transfer value to the fp stack */
5855                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5856                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5857                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5858
5859                         amd64_push_reg (code, AMD64_RAX);
5860                         amd64_fxam (code);
5861                         amd64_fnstsw (code);
5862                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5863                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5864                         amd64_pop_reg (code, AMD64_RAX);
5865                         amd64_fstp (code, 0);
5866                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5867                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5868                         break;
5869                 case OP_TLS_GET: {
5870                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5871                         break;
5872                 }
5873                 case OP_TLS_GET_REG:
5874                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5875                         break;
5876                 case OP_TLS_SET: {
5877                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5878                         break;
5879                 }
5880                 case OP_TLS_SET_REG: {
5881                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5882                         break;
5883                 }
5884                 case OP_MEMORY_BARRIER: {
5885                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5886                                 x86_mfence (code);
5887                         break;
5888                 }
5889                 case OP_ATOMIC_ADD_I4:
5890                 case OP_ATOMIC_ADD_I8: {
5891                         int dreg = ins->dreg;
5892                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5893
5894                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5895                                 dreg = AMD64_R11;
5896
5897                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5898                         amd64_prefix (code, X86_LOCK_PREFIX);
5899                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5900                         /* dreg contains the old value, add with sreg2 value */
5901                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5902
5903                         if (ins->dreg != dreg)
5904                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5905
5906                         break;
5907                 }
5908                 case OP_ATOMIC_EXCHANGE_I4:
5909                 case OP_ATOMIC_EXCHANGE_I8: {
5910                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5911
5912                         /* LOCK prefix is implied. */
5913                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5914                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5915                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5916                         break;
5917                 }
5918                 case OP_ATOMIC_CAS_I4:
5919                 case OP_ATOMIC_CAS_I8: {
5920                         guint32 size;
5921
5922                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5923                                 size = 8;
5924                         else
5925                                 size = 4;
5926
5927                         /*
5928                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5929                          * an explanation of how this works.
5930                          */
5931                         g_assert (ins->sreg3 == AMD64_RAX);
5932                         g_assert (ins->sreg1 != AMD64_RAX);
5933                         g_assert (ins->sreg1 != ins->sreg2);
5934
5935                         amd64_prefix (code, X86_LOCK_PREFIX);
5936                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5937
5938                         if (ins->dreg != AMD64_RAX)
5939                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5940                         break;
5941                 }
5942                 case OP_ATOMIC_LOAD_I1: {
5943                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5944                         break;
5945                 }
5946                 case OP_ATOMIC_LOAD_U1: {
5947                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5948                         break;
5949                 }
5950                 case OP_ATOMIC_LOAD_I2: {
5951                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5952                         break;
5953                 }
5954                 case OP_ATOMIC_LOAD_U2: {
5955                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5956                         break;
5957                 }
5958                 case OP_ATOMIC_LOAD_I4: {
5959                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5960                         break;
5961                 }
5962                 case OP_ATOMIC_LOAD_U4:
5963                 case OP_ATOMIC_LOAD_I8:
5964                 case OP_ATOMIC_LOAD_U8: {
5965                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
5966                         break;
5967                 }
5968                 case OP_ATOMIC_LOAD_R4: {
5969                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5970                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5971                         break;
5972                 }
5973                 case OP_ATOMIC_LOAD_R8: {
5974                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5975                         break;
5976                 }
5977                 case OP_ATOMIC_STORE_I1:
5978                 case OP_ATOMIC_STORE_U1:
5979                 case OP_ATOMIC_STORE_I2:
5980                 case OP_ATOMIC_STORE_U2:
5981                 case OP_ATOMIC_STORE_I4:
5982                 case OP_ATOMIC_STORE_U4:
5983                 case OP_ATOMIC_STORE_I8:
5984                 case OP_ATOMIC_STORE_U8: {
5985                         int size;
5986
5987                         switch (ins->opcode) {
5988                         case OP_ATOMIC_STORE_I1:
5989                         case OP_ATOMIC_STORE_U1:
5990                                 size = 1;
5991                                 break;
5992                         case OP_ATOMIC_STORE_I2:
5993                         case OP_ATOMIC_STORE_U2:
5994                                 size = 2;
5995                                 break;
5996                         case OP_ATOMIC_STORE_I4:
5997                         case OP_ATOMIC_STORE_U4:
5998                                 size = 4;
5999                                 break;
6000                         case OP_ATOMIC_STORE_I8:
6001                         case OP_ATOMIC_STORE_U8:
6002                                 size = 8;
6003                                 break;
6004                         }
6005
6006                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
6007
6008                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6009                                 x86_mfence (code);
6010                         break;
6011                 }
6012                 case OP_ATOMIC_STORE_R4: {
6013                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6014                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6015
6016                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6017                                 x86_mfence (code);
6018                         break;
6019                 }
6020                 case OP_ATOMIC_STORE_R8: {
6021                         x86_nop (code);
6022                         x86_nop (code);
6023                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6024                         x86_nop (code);
6025                         x86_nop (code);
6026
6027                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6028                                 x86_mfence (code);
6029                         break;
6030                 }
6031                 case OP_CARD_TABLE_WBARRIER: {
6032                         int ptr = ins->sreg1;
6033                         int value = ins->sreg2;
6034                         guchar *br = 0;
6035                         int nursery_shift, card_table_shift;
6036                         gpointer card_table_mask;
6037                         size_t nursery_size;
6038
6039                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6040                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6041                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6042
6043                         /*If either point to the stack we can simply avoid the WB. This happens due to
6044                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6045                          */
6046                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6047                                 continue;
6048
6049                         /*
6050                          * We need one register we can clobber, we choose EDX and make sreg1
6051                          * fixed EAX to work around limitations in the local register allocator.
6052                          * sreg2 might get allocated to EDX, but that is not a problem since
6053                          * we use it before clobbering EDX.
6054                          */
6055                         g_assert (ins->sreg1 == AMD64_RAX);
6056
6057                         /*
6058                          * This is the code we produce:
6059                          *
6060                          *   edx = value
6061                          *   edx >>= nursery_shift
6062                          *   cmp edx, (nursery_start >> nursery_shift)
6063                          *   jne done
6064                          *   edx = ptr
6065                          *   edx >>= card_table_shift
6066                          *   edx += cardtable
6067                          *   [edx] = 1
6068                          * done:
6069                          */
6070
6071                         if (mono_gc_card_table_nursery_check ()) {
6072                                 if (value != AMD64_RDX)
6073                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6074                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6075                                 if (shifted_nursery_start >> 31) {
6076                                         /*
6077                                          * The value we need to compare against is 64 bits, so we need
6078                                          * another spare register.  We use RBX, which we save and
6079                                          * restore.
6080                                          */
6081                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6082                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6083                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6084                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6085                                 } else {
6086                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6087                                 }
6088                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6089                         }
6090                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6091                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6092                         if (card_table_mask)
6093                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6094
6095                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6096                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6097
6098                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6099
6100                         if (mono_gc_card_table_nursery_check ())
6101                                 x86_patch (br, code);
6102                         break;
6103                 }
6104 #ifdef MONO_ARCH_SIMD_INTRINSICS
6105                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6106                 case OP_ADDPS:
6107                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6108                         break;
6109                 case OP_DIVPS:
6110                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6111                         break;
6112                 case OP_MULPS:
6113                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6114                         break;
6115                 case OP_SUBPS:
6116                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6117                         break;
6118                 case OP_MAXPS:
6119                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6120                         break;
6121                 case OP_MINPS:
6122                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6123                         break;
6124                 case OP_COMPPS:
6125                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6126                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6127                         break;
6128                 case OP_ANDPS:
6129                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6130                         break;
6131                 case OP_ANDNPS:
6132                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6133                         break;
6134                 case OP_ORPS:
6135                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6136                         break;
6137                 case OP_XORPS:
6138                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6139                         break;
6140                 case OP_SQRTPS:
6141                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6142                         break;
6143                 case OP_RSQRTPS:
6144                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6145                         break;
6146                 case OP_RCPPS:
6147                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6148                         break;
6149                 case OP_ADDSUBPS:
6150                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6151                         break;
6152                 case OP_HADDPS:
6153                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6154                         break;
6155                 case OP_HSUBPS:
6156                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6157                         break;
6158                 case OP_DUPPS_HIGH:
6159                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6160                         break;
6161                 case OP_DUPPS_LOW:
6162                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6163                         break;
6164
6165                 case OP_PSHUFLEW_HIGH:
6166                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6167                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6168                         break;
6169                 case OP_PSHUFLEW_LOW:
6170                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6171                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6172                         break;
6173                 case OP_PSHUFLED:
6174                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6175                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6176                         break;
6177                 case OP_SHUFPS:
6178                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6179                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6180                         break;
6181                 case OP_SHUFPD:
6182                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6183                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6184                         break;
6185
6186                 case OP_ADDPD:
6187                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_DIVPD:
6190                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6191                         break;
6192                 case OP_MULPD:
6193                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6194                         break;
6195                 case OP_SUBPD:
6196                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6197                         break;
6198                 case OP_MAXPD:
6199                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6200                         break;
6201                 case OP_MINPD:
6202                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6203                         break;
6204                 case OP_COMPPD:
6205                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6206                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6207                         break;
6208                 case OP_ANDPD:
6209                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6210                         break;
6211                 case OP_ANDNPD:
6212                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6213                         break;
6214                 case OP_ORPD:
6215                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6216                         break;
6217                 case OP_XORPD:
6218                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6219                         break;
6220                 case OP_SQRTPD:
6221                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6222                         break;
6223                 case OP_ADDSUBPD:
6224                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6225                         break;
6226                 case OP_HADDPD:
6227                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6228                         break;
6229                 case OP_HSUBPD:
6230                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6231                         break;
6232                 case OP_DUPPD:
6233                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6234                         break;
6235
6236                 case OP_EXTRACT_MASK:
6237                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6238                         break;
6239
6240                 case OP_PAND:
6241                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6242                         break;
6243                 case OP_POR:
6244                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6245                         break;
6246                 case OP_PXOR:
6247                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6248                         break;
6249
6250                 case OP_PADDB:
6251                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6252                         break;
6253                 case OP_PADDW:
6254                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6255                         break;
6256                 case OP_PADDD:
6257                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6258                         break;
6259                 case OP_PADDQ:
6260                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6261                         break;
6262
6263                 case OP_PSUBB:
6264                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6265                         break;
6266                 case OP_PSUBW:
6267                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6268                         break;
6269                 case OP_PSUBD:
6270                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6271                         break;
6272                 case OP_PSUBQ:
6273                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6274                         break;
6275
6276                 case OP_PMAXB_UN:
6277                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6278                         break;
6279                 case OP_PMAXW_UN:
6280                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6281                         break;
6282                 case OP_PMAXD_UN:
6283                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6284                         break;
6285
6286                 case OP_PMAXB:
6287                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6288                         break;
6289                 case OP_PMAXW:
6290                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6291                         break;
6292                 case OP_PMAXD:
6293                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6294                         break;
6295
6296                 case OP_PAVGB_UN:
6297                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6298                         break;
6299                 case OP_PAVGW_UN:
6300                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6301                         break;
6302
6303                 case OP_PMINB_UN:
6304                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6305                         break;
6306                 case OP_PMINW_UN:
6307                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6308                         break;
6309                 case OP_PMIND_UN:
6310                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6311                         break;
6312
6313                 case OP_PMINB:
6314                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6315                         break;
6316                 case OP_PMINW:
6317                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6318                         break;
6319                 case OP_PMIND:
6320                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6321                         break;
6322
6323                 case OP_PCMPEQB:
6324                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6325                         break;
6326                 case OP_PCMPEQW:
6327                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6328                         break;
6329                 case OP_PCMPEQD:
6330                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6331                         break;
6332                 case OP_PCMPEQQ:
6333                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6334                         break;
6335
6336                 case OP_PCMPGTB:
6337                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6338                         break;
6339                 case OP_PCMPGTW:
6340                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6341                         break;
6342                 case OP_PCMPGTD:
6343                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6344                         break;
6345                 case OP_PCMPGTQ:
6346                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6347                         break;
6348
6349                 case OP_PSUM_ABS_DIFF:
6350                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6351                         break;
6352
6353                 case OP_UNPACK_LOWB:
6354                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6355                         break;
6356                 case OP_UNPACK_LOWW:
6357                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6358                         break;
6359                 case OP_UNPACK_LOWD:
6360                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6361                         break;
6362                 case OP_UNPACK_LOWQ:
6363                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6364                         break;
6365                 case OP_UNPACK_LOWPS:
6366                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6367                         break;
6368                 case OP_UNPACK_LOWPD:
6369                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6370                         break;
6371
6372                 case OP_UNPACK_HIGHB:
6373                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6374                         break;
6375                 case OP_UNPACK_HIGHW:
6376                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6377                         break;
6378                 case OP_UNPACK_HIGHD:
6379                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6380                         break;
6381                 case OP_UNPACK_HIGHQ:
6382                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6383                         break;
6384                 case OP_UNPACK_HIGHPS:
6385                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6386                         break;
6387                 case OP_UNPACK_HIGHPD:
6388                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6389                         break;
6390
6391                 case OP_PACKW:
6392                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6393                         break;
6394                 case OP_PACKD:
6395                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6396                         break;
6397                 case OP_PACKW_UN:
6398                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6399                         break;
6400                 case OP_PACKD_UN:
6401                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6402                         break;
6403
6404                 case OP_PADDB_SAT_UN:
6405                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6406                         break;
6407                 case OP_PSUBB_SAT_UN:
6408                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6409                         break;
6410                 case OP_PADDW_SAT_UN:
6411                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6412                         break;
6413                 case OP_PSUBW_SAT_UN:
6414                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6415                         break;
6416
6417                 case OP_PADDB_SAT:
6418                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6419                         break;
6420                 case OP_PSUBB_SAT:
6421                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6422                         break;
6423                 case OP_PADDW_SAT:
6424                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6425                         break;
6426                 case OP_PSUBW_SAT:
6427                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6428                         break;
6429
6430                 case OP_PMULW:
6431                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6432                         break;
6433                 case OP_PMULD:
6434                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6435                         break;
6436                 case OP_PMULQ:
6437                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6438                         break;
6439                 case OP_PMULW_HIGH_UN:
6440                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6441                         break;
6442                 case OP_PMULW_HIGH:
6443                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6444                         break;
6445
6446                 case OP_PSHRW:
6447                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6448                         break;
6449                 case OP_PSHRW_REG:
6450                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6451                         break;
6452
6453                 case OP_PSARW:
6454                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6455                         break;
6456                 case OP_PSARW_REG:
6457                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6458                         break;
6459
6460                 case OP_PSHLW:
6461                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6462                         break;
6463                 case OP_PSHLW_REG:
6464                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6465                         break;
6466
6467                 case OP_PSHRD:
6468                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6469                         break;
6470                 case OP_PSHRD_REG:
6471                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6472                         break;
6473
6474                 case OP_PSARD:
6475                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6476                         break;
6477                 case OP_PSARD_REG:
6478                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6479                         break;
6480
6481                 case OP_PSHLD:
6482                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6483                         break;
6484                 case OP_PSHLD_REG:
6485                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6486                         break;
6487
6488                 case OP_PSHRQ:
6489                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6490                         break;
6491                 case OP_PSHRQ_REG:
6492                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6493                         break;
6494
6495                 /*TODO: This is appart of the sse spec but not added
6496                 case OP_PSARQ:
6497                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6498                         break;
6499                 case OP_PSARQ_REG:
6500                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6501                         break;
6502                 */
6503
6504                 case OP_PSHLQ:
6505                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6506                         break;
6507                 case OP_PSHLQ_REG:
6508                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6509                         break;
6510                 case OP_CVTDQ2PD:
6511                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6512                         break;
6513                 case OP_CVTDQ2PS:
6514                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6515                         break;
6516                 case OP_CVTPD2DQ:
6517                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6518                         break;
6519                 case OP_CVTPD2PS:
6520                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6521                         break;
6522                 case OP_CVTPS2DQ:
6523                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6524                         break;
6525                 case OP_CVTPS2PD:
6526                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6527                         break;
6528                 case OP_CVTTPD2DQ:
6529                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6530                         break;
6531                 case OP_CVTTPS2DQ:
6532                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6533                         break;
6534
6535                 case OP_ICONV_TO_X:
6536                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6537                         break;
6538                 case OP_EXTRACT_I4:
6539                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6540                         break;
6541                 case OP_EXTRACT_I8:
6542                         if (ins->inst_c0) {
6543                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6544                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6545                         } else {
6546                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6547                         }
6548                         break;
6549                 case OP_EXTRACT_I1:
6550                 case OP_EXTRACT_U1:
6551                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6552                         if (ins->inst_c0)
6553                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6554                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6555                         break;
6556                 case OP_EXTRACT_I2:
6557                 case OP_EXTRACT_U2:
6558                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6559                         if (ins->inst_c0)
6560                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6561                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6562                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6563                         break;
6564                 case OP_EXTRACT_R8:
6565                         if (ins->inst_c0)
6566                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6567                         else
6568                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6569                         break;
6570                 case OP_INSERT_I2:
6571                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6572                         break;
6573                 case OP_EXTRACTX_U2:
6574                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6575                         break;
6576                 case OP_INSERTX_U1_SLOW:
6577                         /*sreg1 is the extracted ireg (scratch)
6578                         /sreg2 is the to be inserted ireg (scratch)
6579                         /dreg is the xreg to receive the value*/
6580
6581                         /*clear the bits from the extracted word*/
6582                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6583                         /*shift the value to insert if needed*/
6584                         if (ins->inst_c0 & 1)
6585                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6586                         /*join them together*/
6587                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6588                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6589                         break;
6590                 case OP_INSERTX_I4_SLOW:
6591                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6592                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6593                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6594                         break;
6595                 case OP_INSERTX_I8_SLOW:
6596                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6597                         if (ins->inst_c0)
6598                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6599                         else
6600                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6601                         break;
6602
6603                 case OP_INSERTX_R4_SLOW:
6604                         switch (ins->inst_c0) {
6605                         case 0:
6606                                 if (cfg->r4fp)
6607                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6608                                 else
6609                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6610                                 break;
6611                         case 1:
6612                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6613                                 if (cfg->r4fp)
6614                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6615                                 else
6616                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6617                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6618                                 break;
6619                         case 2:
6620                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6621                                 if (cfg->r4fp)
6622                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6623                                 else
6624                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6625                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6626                                 break;
6627                         case 3:
6628                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6629                                 if (cfg->r4fp)
6630                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6631                                 else
6632                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6633                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6634                                 break;
6635                         }
6636                         break;
6637                 case OP_INSERTX_R8_SLOW:
6638                         if (ins->inst_c0)
6639                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6640                         else
6641                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6642                         break;
6643                 case OP_STOREX_MEMBASE_REG:
6644                 case OP_STOREX_MEMBASE:
6645                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6646                         break;
6647                 case OP_LOADX_MEMBASE:
6648                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6649                         break;
6650                 case OP_LOADX_ALIGNED_MEMBASE:
6651                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6652                         break;
6653                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6654                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6655                         break;
6656                 case OP_STOREX_NTA_MEMBASE_REG:
6657                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6658                         break;
6659                 case OP_PREFETCH_MEMBASE:
6660                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6661                         break;
6662
6663                 case OP_XMOVE:
6664                         /*FIXME the peephole pass should have killed this*/
6665                         if (ins->dreg != ins->sreg1)
6666                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6667                         break;
6668                 case OP_XZERO:
6669                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6670                         break;
6671                 case OP_ICONV_TO_R4_RAW:
6672                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6673                         break;
6674
6675                 case OP_FCONV_TO_R8_X:
6676                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6677                         break;
6678
6679                 case OP_XCONV_R8_TO_I4:
6680                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6681                         switch (ins->backend.source_opcode) {
6682                         case OP_FCONV_TO_I1:
6683                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6684                                 break;
6685                         case OP_FCONV_TO_U1:
6686                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6687                                 break;
6688                         case OP_FCONV_TO_I2:
6689                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6690                                 break;
6691                         case OP_FCONV_TO_U2:
6692                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6693                                 break;
6694                         }
6695                         break;
6696
6697                 case OP_EXPAND_I2:
6698                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6699                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6700                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6701                         break;
6702                 case OP_EXPAND_I4:
6703                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6704                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6705                         break;
6706                 case OP_EXPAND_I8:
6707                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6708                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6709                         break;
6710                 case OP_EXPAND_R4:
6711                         if (cfg->r4fp) {
6712                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6713                         } else {
6714                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6715                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6716                         }
6717                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6718                         break;
6719                 case OP_EXPAND_R8:
6720                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6721                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6722                         break;
6723 #endif
6724                 case OP_LIVERANGE_START: {
6725                         if (cfg->verbose_level > 1)
6726                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6727                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6728                         break;
6729                 }
6730                 case OP_LIVERANGE_END: {
6731                         if (cfg->verbose_level > 1)
6732                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6733                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6734                         break;
6735                 }
6736                 case OP_GC_SAFE_POINT: {
6737                         const char *polling_func = NULL;
6738                         int compare_val = 0;
6739                         guint8 *br [1];
6740
6741 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6742                         polling_func = "mono_nacl_gc";
6743                         compare_val = 0xFFFFFFFF;
6744 #else
6745                         g_assert (mono_threads_is_coop_enabled ());
6746                         polling_func = "mono_threads_state_poll";
6747                         compare_val = 1;
6748 #endif
6749
6750                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6751                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6752                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6753                         amd64_patch (br[0], code);
6754                         break;
6755                 }
6756
6757                 case OP_GC_LIVENESS_DEF:
6758                 case OP_GC_LIVENESS_USE:
6759                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6760                         ins->backend.pc_offset = code - cfg->native_code;
6761                         break;
6762                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6763                         ins->backend.pc_offset = code - cfg->native_code;
6764                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6765                         break;
6766                 default:
6767                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6768                         g_assert_not_reached ();
6769                 }
6770
6771                 if ((code - cfg->native_code - offset) > max_len) {
6772 #if !defined(__native_client_codegen__)
6773                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6774                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6775                         g_assert_not_reached ();
6776 #endif
6777                 }
6778         }
6779
6780         cfg->code_len = code - cfg->native_code;
6781 }
6782
6783 #endif /* DISABLE_JIT */
6784
6785 void
6786 mono_arch_register_lowlevel_calls (void)
6787 {
6788         /* The signature doesn't matter */
6789         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6790 }
6791
6792 void
6793 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6794 {
6795         unsigned char *ip = ji->ip.i + code;
6796
6797         /*
6798          * Debug code to help track down problems where the target of a near call is
6799          * is not valid.
6800          */
6801         if (amd64_is_near_call (ip)) {
6802                 gint64 disp = (guint8*)target - (guint8*)ip;
6803
6804                 if (!amd64_is_imm32 (disp)) {
6805                         printf ("TYPE: %d\n", ji->type);
6806                         switch (ji->type) {
6807                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6808                                 printf ("V: %s\n", ji->data.name);
6809                                 break;
6810                         case MONO_PATCH_INFO_METHOD_JUMP:
6811                         case MONO_PATCH_INFO_METHOD:
6812                                 printf ("V: %s\n", ji->data.method->name);
6813                                 break;
6814                         default:
6815                                 break;
6816                         }
6817                 }
6818         }
6819
6820         amd64_patch (ip, (gpointer)target);
6821 }
6822
6823 #ifndef DISABLE_JIT
6824
6825 static int
6826 get_max_epilog_size (MonoCompile *cfg)
6827 {
6828         int max_epilog_size = 16;
6829
6830         if (cfg->method->save_lmf)
6831                 max_epilog_size += 256;
6832
6833         if (mono_jit_trace_calls != NULL)
6834                 max_epilog_size += 50;
6835
6836         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6837                 max_epilog_size += 50;
6838
6839         max_epilog_size += (AMD64_NREG * 2);
6840
6841         return max_epilog_size;
6842 }
6843
6844 /*
6845  * This macro is used for testing whenever the unwinder works correctly at every point
6846  * where an async exception can happen.
6847  */
6848 /* This will generate a SIGSEGV at the given point in the code */
6849 #define async_exc_point(code) do { \
6850     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6851          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6852              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6853          cfg->arch.async_point_count ++; \
6854     } \
6855 } while (0)
6856
6857 guint8 *
6858 mono_arch_emit_prolog (MonoCompile *cfg)
6859 {
6860         MonoMethod *method = cfg->method;
6861         MonoBasicBlock *bb;
6862         MonoMethodSignature *sig;
6863         MonoInst *ins;
6864         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6865         guint8 *code;
6866         CallInfo *cinfo;
6867         MonoInst *lmf_var = cfg->lmf_var;
6868         gboolean args_clobbered = FALSE;
6869         gboolean trace = FALSE;
6870 #ifdef __native_client_codegen__
6871         guint alignment_check;
6872 #endif
6873
6874         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6875
6876 #if defined(__default_codegen__)
6877         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6878 #elif defined(__native_client_codegen__)
6879         /* native_code_alloc is not 32-byte aligned, native_code is. */
6880         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6881
6882         /* Align native_code to next nearest kNaclAlignment byte. */
6883         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6884         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6885
6886         code = cfg->native_code;
6887
6888         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6889         g_assert (alignment_check == 0);
6890 #endif
6891
6892         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6893                 trace = TRUE;
6894
6895         /* Amount of stack space allocated by register saving code */
6896         pos = 0;
6897
6898         /* Offset between RSP and the CFA */
6899         cfa_offset = 0;
6900
6901         /*
6902          * The prolog consists of the following parts:
6903          * FP present:
6904          * - push rbp, mov rbp, rsp
6905          * - save callee saved regs using pushes
6906          * - allocate frame
6907          * - save rgctx if needed
6908          * - save lmf if needed
6909          * FP not present:
6910          * - allocate frame
6911          * - save rgctx if needed
6912          * - save lmf if needed
6913          * - save callee saved regs using moves
6914          */
6915
6916         // CFA = sp + 8
6917         cfa_offset = 8;
6918         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6919         // IP saved at CFA - 8
6920         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6921         async_exc_point (code);
6922         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6923
6924         if (!cfg->arch.omit_fp) {
6925                 amd64_push_reg (code, AMD64_RBP);
6926                 cfa_offset += 8;
6927                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6928                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6929                 async_exc_point (code);
6930 #ifdef TARGET_WIN32
6931                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6932 #endif
6933                 /* These are handled automatically by the stack marking code */
6934                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6935
6936                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6937                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6938                 async_exc_point (code);
6939 #ifdef TARGET_WIN32
6940                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6941 #endif
6942         }
6943
6944         /* The param area is always at offset 0 from sp */
6945         /* This needs to be allocated here, since it has to come after the spill area */
6946         if (cfg->param_area) {
6947                 if (cfg->arch.omit_fp)
6948                         // FIXME:
6949                         g_assert_not_reached ();
6950                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6951         }
6952
6953         if (cfg->arch.omit_fp) {
6954                 /*
6955                  * On enter, the stack is misaligned by the pushing of the return
6956                  * address. It is either made aligned by the pushing of %rbp, or by
6957                  * this.
6958                  */
6959                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6960                 if ((alloc_size % 16) == 0) {
6961                         alloc_size += 8;
6962                         /* Mark the padding slot as NOREF */
6963                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6964                 }
6965         } else {
6966                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6967                 if (cfg->stack_offset != alloc_size) {
6968                         /* Mark the padding slot as NOREF */
6969                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
6970                 }
6971                 cfg->arch.sp_fp_offset = alloc_size;
6972                 alloc_size -= pos;
6973         }
6974
6975         cfg->arch.stack_alloc_size = alloc_size;
6976
6977         /* Allocate stack frame */
6978         if (alloc_size) {
6979                 /* See mono_emit_stack_alloc */
6980 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
6981                 guint32 remaining_size = alloc_size;
6982                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
6983                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
6984                 guint32 offset = code - cfg->native_code;
6985                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
6986                         while (required_code_size >= (cfg->code_size - offset))
6987                                 cfg->code_size *= 2;
6988                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
6989                         code = cfg->native_code + offset;
6990                         cfg->stat_code_reallocs++;
6991                 }
6992
6993                 while (remaining_size >= 0x1000) {
6994                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
6995                         if (cfg->arch.omit_fp) {
6996                                 cfa_offset += 0x1000;
6997                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6998                         }
6999                         async_exc_point (code);
7000 #ifdef TARGET_WIN32
7001                         if (cfg->arch.omit_fp)
7002                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
7003 #endif
7004
7005                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
7006                         remaining_size -= 0x1000;
7007                 }
7008                 if (remaining_size) {
7009                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7010                         if (cfg->arch.omit_fp) {
7011                                 cfa_offset += remaining_size;
7012                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7013                                 async_exc_point (code);
7014                         }
7015 #ifdef TARGET_WIN32
7016                         if (cfg->arch.omit_fp)
7017                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7018 #endif
7019                 }
7020 #else
7021                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7022                 if (cfg->arch.omit_fp) {
7023                         cfa_offset += alloc_size;
7024                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7025                         async_exc_point (code);
7026                 }
7027 #endif
7028         }
7029
7030         /* Stack alignment check */
7031 #if 0
7032         {
7033                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7034                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7035                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7036                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
7037                 amd64_breakpoint (code);
7038         }
7039 #endif
7040
7041         if (mini_get_debug_options ()->init_stacks) {
7042                 /* Fill the stack frame with a dummy value to force deterministic behavior */
7043
7044                 /* Save registers to the red zone */
7045                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7046                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7047
7048                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7049                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7050                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7051
7052                 amd64_cld (code);
7053 #if defined(__default_codegen__)
7054                 amd64_prefix (code, X86_REP_PREFIX);
7055                 amd64_stosl (code);
7056 #elif defined(__native_client_codegen__)
7057                 /* NaCl stos pseudo-instruction */
7058                 amd64_codegen_pre (code);
7059                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
7060                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7061                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7062                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7063                 amd64_prefix (code, X86_REP_PREFIX);
7064                 amd64_stosl (code);
7065                 amd64_codegen_post (code);
7066 #endif /* __native_client_codegen__ */
7067
7068                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7069                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7070         }
7071
7072         /* Save LMF */
7073         if (method->save_lmf)
7074                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7075
7076         /* Save callee saved registers */
7077         if (cfg->arch.omit_fp) {
7078                 save_area_offset = cfg->arch.reg_save_area_offset;
7079                 /* Save caller saved registers after sp is adjusted */
7080                 /* The registers are saved at the bottom of the frame */
7081                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7082         } else {
7083                 /* The registers are saved just below the saved rbp */
7084                 save_area_offset = cfg->arch.reg_save_area_offset;
7085         }
7086
7087         for (i = 0; i < AMD64_NREG; ++i) {
7088                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7089                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7090
7091                         if (cfg->arch.omit_fp) {
7092                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7093                                 /* These are handled automatically by the stack marking code */
7094                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7095                         } else {
7096                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7097                                 // FIXME: GC
7098                         }
7099
7100                         save_area_offset += 8;
7101                         async_exc_point (code);
7102                 }
7103         }
7104
7105         /* store runtime generic context */
7106         if (cfg->rgctx_var) {
7107                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7108                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7109
7110                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7111
7112                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7113                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7114         }
7115
7116         /* compute max_length in order to use short forward jumps */
7117         max_epilog_size = get_max_epilog_size (cfg);
7118         if (cfg->opt & MONO_OPT_BRANCH) {
7119                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7120                         MonoInst *ins;
7121                         int max_length = 0;
7122
7123                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7124                                 max_length += 6;
7125                         /* max alignment for loops */
7126                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7127                                 max_length += LOOP_ALIGNMENT;
7128 #ifdef __native_client_codegen__
7129                         /* max alignment for native client */
7130                         max_length += kNaClAlignment;
7131 #endif
7132
7133                         MONO_BB_FOR_EACH_INS (bb, ins) {
7134 #ifdef __native_client_codegen__
7135                                 {
7136                                         int space_in_block = kNaClAlignment -
7137                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7138                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7139                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7140                                                 max_length += space_in_block;
7141                                         }
7142                                 }
7143 #endif  /*__native_client_codegen__*/
7144                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7145                         }
7146
7147                         /* Take prolog and epilog instrumentation into account */
7148                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7149                                 max_length += max_epilog_size;
7150
7151                         bb->max_length = max_length;
7152                 }
7153         }
7154
7155         sig = mono_method_signature (method);
7156         pos = 0;
7157
7158         cinfo = (CallInfo *)cfg->arch.cinfo;
7159
7160         if (sig->ret->type != MONO_TYPE_VOID) {
7161                 /* Save volatile arguments to the stack */
7162                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7163                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7164         }
7165
7166         /* Keep this in sync with emit_load_volatile_arguments */
7167         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7168                 ArgInfo *ainfo = cinfo->args + i;
7169
7170                 ins = cfg->args [i];
7171
7172                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7173                         /* Unused arguments */
7174                         continue;
7175
7176                 /* Save volatile arguments to the stack */
7177                 if (ins->opcode != OP_REGVAR) {
7178                         switch (ainfo->storage) {
7179                         case ArgInIReg: {
7180                                 guint32 size = 8;
7181
7182                                 /* FIXME: I1 etc */
7183                                 /*
7184                                 if (stack_offset & 0x1)
7185                                         size = 1;
7186                                 else if (stack_offset & 0x2)
7187                                         size = 2;
7188                                 else if (stack_offset & 0x4)
7189                                         size = 4;
7190                                 else
7191                                         size = 8;
7192                                 */
7193                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7194
7195                                 /*
7196                                  * Save the original location of 'this',
7197                                  * get_generic_info_from_stack_frame () needs this to properly look up
7198                                  * the argument value during the handling of async exceptions.
7199                                  */
7200                                 if (ins == cfg->args [0]) {
7201                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7202                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7203                                 }
7204                                 break;
7205                         }
7206                         case ArgInFloatSSEReg:
7207                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7208                                 break;
7209                         case ArgInDoubleSSEReg:
7210                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7211                                 break;
7212                         case ArgValuetypeInReg:
7213                                 for (quad = 0; quad < 2; quad ++) {
7214                                         switch (ainfo->pair_storage [quad]) {
7215                                         case ArgInIReg:
7216                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7217                                                 break;
7218                                         case ArgInFloatSSEReg:
7219                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7220                                                 break;
7221                                         case ArgInDoubleSSEReg:
7222                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7223                                                 break;
7224                                         case ArgNone:
7225                                                 break;
7226                                         default:
7227                                                 g_assert_not_reached ();
7228                                         }
7229                                 }
7230                                 break;
7231                         case ArgValuetypeAddrInIReg:
7232                                 if (ainfo->pair_storage [0] == ArgInIReg)
7233                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7234                                 break;
7235                         default:
7236                                 break;
7237                         }
7238                 } else {
7239                         /* Argument allocated to (non-volatile) register */
7240                         switch (ainfo->storage) {
7241                         case ArgInIReg:
7242                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7243                                 break;
7244                         case ArgOnStack:
7245                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7246                                 break;
7247                         default:
7248                                 g_assert_not_reached ();
7249                         }
7250
7251                         if (ins == cfg->args [0]) {
7252                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7253                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7254                         }
7255                 }
7256         }
7257
7258         if (cfg->method->save_lmf)
7259                 args_clobbered = TRUE;
7260
7261         if (trace) {
7262                 args_clobbered = TRUE;
7263                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7264         }
7265
7266         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7267                 args_clobbered = TRUE;
7268
7269         /*
7270          * Optimize the common case of the first bblock making a call with the same
7271          * arguments as the method. This works because the arguments are still in their
7272          * original argument registers.
7273          * FIXME: Generalize this
7274          */
7275         if (!args_clobbered) {
7276                 MonoBasicBlock *first_bb = cfg->bb_entry;
7277                 MonoInst *next;
7278                 int filter = FILTER_IL_SEQ_POINT;
7279
7280                 next = mono_bb_first_inst (first_bb, filter);
7281                 if (!next && first_bb->next_bb) {
7282                         first_bb = first_bb->next_bb;
7283                         next = mono_bb_first_inst (first_bb, filter);
7284                 }
7285
7286                 if (first_bb->in_count > 1)
7287                         next = NULL;
7288
7289                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7290                         ArgInfo *ainfo = cinfo->args + i;
7291                         gboolean match = FALSE;
7292
7293                         ins = cfg->args [i];
7294                         if (ins->opcode != OP_REGVAR) {
7295                                 switch (ainfo->storage) {
7296                                 case ArgInIReg: {
7297                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7298                                                 if (next->dreg == ainfo->reg) {
7299                                                         NULLIFY_INS (next);
7300                                                         match = TRUE;
7301                                                 } else {
7302                                                         next->opcode = OP_MOVE;
7303                                                         next->sreg1 = ainfo->reg;
7304                                                         /* Only continue if the instruction doesn't change argument regs */
7305                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7306                                                                 match = TRUE;
7307                                                 }
7308                                         }
7309                                         break;
7310                                 }
7311                                 default:
7312                                         break;
7313                                 }
7314                         } else {
7315                                 /* Argument allocated to (non-volatile) register */
7316                                 switch (ainfo->storage) {
7317                                 case ArgInIReg:
7318                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7319                                                 NULLIFY_INS (next);
7320                                                 match = TRUE;
7321                                         }
7322                                         break;
7323                                 default:
7324                                         break;
7325                                 }
7326                         }
7327
7328                         if (match) {
7329                                 next = mono_inst_next (next, filter);
7330                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7331                                 if (!next)
7332                                         break;
7333                         }
7334                 }
7335         }
7336
7337         if (cfg->gen_sdb_seq_points) {
7338                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7339
7340                 /* Initialize seq_point_info_var */
7341                 if (cfg->compile_aot) {
7342                         /* Initialize the variable from a GOT slot */
7343                         /* Same as OP_AOTCONST */
7344                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7345                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7346                         g_assert (info_var->opcode == OP_REGOFFSET);
7347                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7348                 }
7349
7350                 if (cfg->compile_aot) {
7351                         /* Initialize ss_tramp_var */
7352                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7353                         g_assert (ins->opcode == OP_REGOFFSET);
7354
7355                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7356                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7357                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7358                 } else {
7359                         /* Initialize ss_tramp_var */
7360                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7361                         g_assert (ins->opcode == OP_REGOFFSET);
7362
7363                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7364                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7365
7366                         /* Initialize bp_tramp_var */
7367                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7368                         g_assert (ins->opcode == OP_REGOFFSET);
7369
7370                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7371                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7372                 }
7373         }
7374
7375         cfg->code_len = code - cfg->native_code;
7376
7377         g_assert (cfg->code_len < cfg->code_size);
7378
7379         return code;
7380 }
7381
7382 void
7383 mono_arch_emit_epilog (MonoCompile *cfg)
7384 {
7385         MonoMethod *method = cfg->method;
7386         int quad, i;
7387         guint8 *code;
7388         int max_epilog_size;
7389         CallInfo *cinfo;
7390         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7391         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7392
7393         max_epilog_size = get_max_epilog_size (cfg);
7394
7395         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7396                 cfg->code_size *= 2;
7397                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7398                 cfg->stat_code_reallocs++;
7399         }
7400         code = cfg->native_code + cfg->code_len;
7401
7402         cfg->has_unwind_info_for_epilog = TRUE;
7403
7404         /* Mark the start of the epilog */
7405         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7406
7407         /* Save the uwind state which is needed by the out-of-line code */
7408         mono_emit_unwind_op_remember_state (cfg, code);
7409
7410         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7411                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7412
7413         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7414
7415         if (method->save_lmf) {
7416                 /* check if we need to restore protection of the stack after a stack overflow */
7417                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7418                         guint8 *patch;
7419                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7420                         /* we load the value in a separate instruction: this mechanism may be
7421                          * used later as a safer way to do thread interruption
7422                          */
7423                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7424                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7425                         patch = code;
7426                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7427                         /* note that the call trampoline will preserve eax/edx */
7428                         x86_call_reg (code, X86_ECX);
7429                         x86_patch (patch, code);
7430                 } else {
7431                         /* FIXME: maybe save the jit tls in the prolog */
7432                 }
7433                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7434                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7435                 }
7436         }
7437
7438         /* Restore callee saved regs */
7439         for (i = 0; i < AMD64_NREG; ++i) {
7440                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7441                         /* Restore only used_int_regs, not arch.saved_iregs */
7442                         if (cfg->used_int_regs & (1 << i)) {
7443                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7444                                 mono_emit_unwind_op_same_value (cfg, code, i);
7445                                 async_exc_point (code);
7446                         }
7447                         save_area_offset += 8;
7448                 }
7449         }
7450
7451         /* Load returned vtypes into registers if needed */
7452         cinfo = (CallInfo *)cfg->arch.cinfo;
7453         if (cinfo->ret.storage == ArgValuetypeInReg) {
7454                 ArgInfo *ainfo = &cinfo->ret;
7455                 MonoInst *inst = cfg->ret;
7456
7457                 for (quad = 0; quad < 2; quad ++) {
7458                         switch (ainfo->pair_storage [quad]) {
7459                         case ArgInIReg:
7460                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7461                                 break;
7462                         case ArgInFloatSSEReg:
7463                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7464                                 break;
7465                         case ArgInDoubleSSEReg:
7466                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7467                                 break;
7468                         case ArgNone:
7469                                 break;
7470                         default:
7471                                 g_assert_not_reached ();
7472                         }
7473                 }
7474         }
7475
7476         if (cfg->arch.omit_fp) {
7477                 if (cfg->arch.stack_alloc_size) {
7478                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7479                 }
7480         } else {
7481                 amd64_leave (code);
7482                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7483         }
7484         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7485         async_exc_point (code);
7486         amd64_ret (code);
7487
7488         /* Restore the unwind state to be the same as before the epilog */
7489         mono_emit_unwind_op_restore_state (cfg, code);
7490
7491         cfg->code_len = code - cfg->native_code;
7492
7493         g_assert (cfg->code_len < cfg->code_size);
7494 }
7495
7496 void
7497 mono_arch_emit_exceptions (MonoCompile *cfg)
7498 {
7499         MonoJumpInfo *patch_info;
7500         int nthrows, i;
7501         guint8 *code;
7502         MonoClass *exc_classes [16];
7503         guint8 *exc_throw_start [16], *exc_throw_end [16];
7504         guint32 code_size = 0;
7505
7506         /* Compute needed space */
7507         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7508                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7509                         code_size += 40;
7510                 if (patch_info->type == MONO_PATCH_INFO_R8)
7511                         code_size += 8 + 15; /* sizeof (double) + alignment */
7512                 if (patch_info->type == MONO_PATCH_INFO_R4)
7513                         code_size += 4 + 15; /* sizeof (float) + alignment */
7514                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7515                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7516         }
7517
7518 #ifdef __native_client_codegen__
7519         /* Give us extra room on Native Client.  This could be   */
7520         /* more carefully calculated, but bundle alignment makes */
7521         /* it much trickier, so *2 like other places is good.    */
7522         code_size *= 2;
7523 #endif
7524
7525         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7526                 cfg->code_size *= 2;
7527                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7528                 cfg->stat_code_reallocs++;
7529         }
7530
7531         code = cfg->native_code + cfg->code_len;
7532
7533         /* add code to raise exceptions */
7534         nthrows = 0;
7535         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7536                 switch (patch_info->type) {
7537                 case MONO_PATCH_INFO_EXC: {
7538                         MonoClass *exc_class;
7539                         guint8 *buf, *buf2;
7540                         guint32 throw_ip;
7541
7542                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7543
7544                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7545                         g_assert (exc_class);
7546                         throw_ip = patch_info->ip.i;
7547
7548                         //x86_breakpoint (code);
7549                         /* Find a throw sequence for the same exception class */
7550                         for (i = 0; i < nthrows; ++i)
7551                                 if (exc_classes [i] == exc_class)
7552                                         break;
7553                         if (i < nthrows) {
7554                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7555                                 x86_jump_code (code, exc_throw_start [i]);
7556                                 patch_info->type = MONO_PATCH_INFO_NONE;
7557                         }
7558                         else {
7559                                 buf = code;
7560                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7561                                 buf2 = code;
7562
7563                                 if (nthrows < 16) {
7564                                         exc_classes [nthrows] = exc_class;
7565                                         exc_throw_start [nthrows] = code;
7566                                 }
7567                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7568
7569                                 patch_info->type = MONO_PATCH_INFO_NONE;
7570
7571                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7572
7573                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7574                                 while (buf < buf2)
7575                                         x86_nop (buf);
7576
7577                                 if (nthrows < 16) {
7578                                         exc_throw_end [nthrows] = code;
7579                                         nthrows ++;
7580                                 }
7581                         }
7582                         break;
7583                 }
7584                 default:
7585                         /* do nothing */
7586                         break;
7587                 }
7588                 g_assert(code < cfg->native_code + cfg->code_size);
7589         }
7590
7591         /* Handle relocations with RIP relative addressing */
7592         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7593                 gboolean remove = FALSE;
7594                 guint8 *orig_code = code;
7595
7596                 switch (patch_info->type) {
7597                 case MONO_PATCH_INFO_R8:
7598                 case MONO_PATCH_INFO_R4: {
7599                         guint8 *pos, *patch_pos;
7600                         guint32 target_pos;
7601
7602                         /* The SSE opcodes require a 16 byte alignment */
7603 #if defined(__default_codegen__)
7604                         code = (guint8*)ALIGN_TO (code, 16);
7605 #elif defined(__native_client_codegen__)
7606                         {
7607                                 /* Pad this out with HLT instructions  */
7608                                 /* or we can get garbage bytes emitted */
7609                                 /* which will fail validation          */
7610                                 guint8 *aligned_code;
7611                                 /* extra align to make room for  */
7612                                 /* mov/push below                      */
7613                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7614                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7615                                 /* The technique of hiding data in an  */
7616                                 /* instruction has a problem here: we  */
7617                                 /* need the data aligned to a 16-byte  */
7618                                 /* boundary but the instruction cannot */
7619                                 /* cross the bundle boundary. so only  */
7620                                 /* odd multiples of 16 can be used     */
7621                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7622                                         aligned_code += 16;
7623                                 }
7624                                 while (code < aligned_code) {
7625                                         *(code++) = 0xf4; /* hlt */
7626                                 }
7627                         }
7628 #endif
7629
7630                         pos = cfg->native_code + patch_info->ip.i;
7631                         if (IS_REX (pos [1])) {
7632                                 patch_pos = pos + 5;
7633                                 target_pos = code - pos - 9;
7634                         }
7635                         else {
7636                                 patch_pos = pos + 4;
7637                                 target_pos = code - pos - 8;
7638                         }
7639
7640                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7641 #ifdef __native_client_codegen__
7642                                 /* Hide 64-bit data in a         */
7643                                 /* "mov imm64, r11" instruction. */
7644                                 /* write it before the start of  */
7645                                 /* the data*/
7646                                 *(code-2) = 0x49; /* prefix      */
7647                                 *(code-1) = 0xbb; /* mov X, %r11 */
7648 #endif
7649                                 *(double*)code = *(double*)patch_info->data.target;
7650                                 code += sizeof (double);
7651                         } else {
7652 #ifdef __native_client_codegen__
7653                                 /* Hide 32-bit data in a        */
7654                                 /* "push imm32" instruction.    */
7655                                 *(code-1) = 0x68; /* push */
7656 #endif
7657                                 *(float*)code = *(float*)patch_info->data.target;
7658                                 code += sizeof (float);
7659                         }
7660
7661                         *(guint32*)(patch_pos) = target_pos;
7662
7663                         remove = TRUE;
7664                         break;
7665                 }
7666                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7667                         guint8 *pos;
7668
7669                         if (cfg->compile_aot)
7670                                 continue;
7671
7672                         /*loading is faster against aligned addresses.*/
7673                         code = (guint8*)ALIGN_TO (code, 8);
7674                         memset (orig_code, 0, code - orig_code);
7675
7676                         pos = cfg->native_code + patch_info->ip.i;
7677
7678                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7679                         if (IS_REX (pos [1]))
7680                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7681                         else
7682                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7683
7684                         *(gpointer*)code = (gpointer)patch_info->data.target;
7685                         code += sizeof (gpointer);
7686
7687                         remove = TRUE;
7688                         break;
7689                 }
7690                 default:
7691                         break;
7692                 }
7693
7694                 if (remove) {
7695                         if (patch_info == cfg->patch_info)
7696                                 cfg->patch_info = patch_info->next;
7697                         else {
7698                                 MonoJumpInfo *tmp;
7699
7700                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7701                                         ;
7702                                 tmp->next = patch_info->next;
7703                         }
7704                 }
7705                 g_assert (code < cfg->native_code + cfg->code_size);
7706         }
7707
7708         cfg->code_len = code - cfg->native_code;
7709
7710         g_assert (cfg->code_len < cfg->code_size);
7711
7712 }
7713
7714 #endif /* DISABLE_JIT */
7715
7716 void*
7717 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7718 {
7719         guchar *code = (guchar *)p;
7720         MonoMethodSignature *sig;
7721         MonoInst *inst;
7722         int i, n, stack_area = 0;
7723
7724         /* Keep this in sync with mono_arch_get_argument_info */
7725
7726         if (enable_arguments) {
7727                 /* Allocate a new area on the stack and save arguments there */
7728                 sig = mono_method_signature (cfg->method);
7729
7730                 n = sig->param_count + sig->hasthis;
7731
7732                 stack_area = ALIGN_TO (n * 8, 16);
7733
7734                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7735
7736                 for (i = 0; i < n; ++i) {
7737                         inst = cfg->args [i];
7738
7739                         if (inst->opcode == OP_REGVAR)
7740                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7741                         else {
7742                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7743                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7744                         }
7745                 }
7746         }
7747
7748         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7749         amd64_set_reg_template (code, AMD64_ARG_REG1);
7750         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7751         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7752
7753         if (enable_arguments)
7754                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7755
7756         return code;
7757 }
7758
7759 enum {
7760         SAVE_NONE,
7761         SAVE_STRUCT,
7762         SAVE_EAX,
7763         SAVE_EAX_EDX,
7764         SAVE_XMM
7765 };
7766
7767 void*
7768 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7769 {
7770         guchar *code = (guchar *)p;
7771         int save_mode = SAVE_NONE;
7772         MonoMethod *method = cfg->method;
7773         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7774         int i;
7775
7776         switch (ret_type->type) {
7777         case MONO_TYPE_VOID:
7778                 /* special case string .ctor icall */
7779                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7780                         save_mode = SAVE_EAX;
7781                 else
7782                         save_mode = SAVE_NONE;
7783                 break;
7784         case MONO_TYPE_I8:
7785         case MONO_TYPE_U8:
7786                 save_mode = SAVE_EAX;
7787                 break;
7788         case MONO_TYPE_R4:
7789         case MONO_TYPE_R8:
7790                 save_mode = SAVE_XMM;
7791                 break;
7792         case MONO_TYPE_GENERICINST:
7793                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7794                         save_mode = SAVE_EAX;
7795                         break;
7796                 }
7797                 /* Fall through */
7798         case MONO_TYPE_VALUETYPE:
7799                 save_mode = SAVE_STRUCT;
7800                 break;
7801         default:
7802                 save_mode = SAVE_EAX;
7803                 break;
7804         }
7805
7806         /* Save the result and copy it into the proper argument register */
7807         switch (save_mode) {
7808         case SAVE_EAX:
7809                 amd64_push_reg (code, AMD64_RAX);
7810                 /* Align stack */
7811                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7812                 if (enable_arguments)
7813                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7814                 break;
7815         case SAVE_STRUCT:
7816                 /* FIXME: */
7817                 if (enable_arguments)
7818                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7819                 break;
7820         case SAVE_XMM:
7821                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7822                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7823                 /* Align stack */
7824                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7825                 /*
7826                  * The result is already in the proper argument register so no copying
7827                  * needed.
7828                  */
7829                 break;
7830         case SAVE_NONE:
7831                 break;
7832         default:
7833                 g_assert_not_reached ();
7834         }
7835
7836         /* Set %al since this is a varargs call */
7837         if (save_mode == SAVE_XMM)
7838                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7839         else
7840                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7841
7842         if (preserve_argument_registers) {
7843                 for (i = 0; i < PARAM_REGS; ++i)
7844                         amd64_push_reg (code, param_regs [i]);
7845         }
7846
7847         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7848         amd64_set_reg_template (code, AMD64_ARG_REG1);
7849         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7850
7851         if (preserve_argument_registers) {
7852                 for (i = PARAM_REGS - 1; i >= 0; --i)
7853                         amd64_pop_reg (code, param_regs [i]);
7854         }
7855
7856         /* Restore result */
7857         switch (save_mode) {
7858         case SAVE_EAX:
7859                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7860                 amd64_pop_reg (code, AMD64_RAX);
7861                 break;
7862         case SAVE_STRUCT:
7863                 /* FIXME: */
7864                 break;
7865         case SAVE_XMM:
7866                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7867                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7868                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7869                 break;
7870         case SAVE_NONE:
7871                 break;
7872         default:
7873                 g_assert_not_reached ();
7874         }
7875
7876         return code;
7877 }
7878
7879 void
7880 mono_arch_flush_icache (guint8 *code, gint size)
7881 {
7882         /* Not needed */
7883 }
7884
7885 void
7886 mono_arch_flush_register_windows (void)
7887 {
7888 }
7889
7890 gboolean
7891 mono_arch_is_inst_imm (gint64 imm)
7892 {
7893         return amd64_use_imm32 (imm);
7894 }
7895
7896 /*
7897  * Determine whenever the trap whose info is in SIGINFO is caused by
7898  * integer overflow.
7899  */
7900 gboolean
7901 mono_arch_is_int_overflow (void *sigctx, void *info)
7902 {
7903         MonoContext ctx;
7904         guint8* rip;
7905         int reg;
7906         gint64 value;
7907
7908         mono_sigctx_to_monoctx (sigctx, &ctx);
7909
7910         rip = (guint8*)ctx.gregs [AMD64_RIP];
7911
7912         if (IS_REX (rip [0])) {
7913                 reg = amd64_rex_b (rip [0]);
7914                 rip ++;
7915         }
7916         else
7917                 reg = 0;
7918
7919         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7920                 /* idiv REG */
7921                 reg += x86_modrm_rm (rip [1]);
7922
7923                 value = ctx.gregs [reg];
7924
7925                 if (value == -1)
7926                         return TRUE;
7927         }
7928
7929         return FALSE;
7930 }
7931
7932 guint32
7933 mono_arch_get_patch_offset (guint8 *code)
7934 {
7935         return 3;
7936 }
7937
7938 /**
7939  * mono_breakpoint_clean_code:
7940  *
7941  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7942  * breakpoints in the original code, they are removed in the copy.
7943  *
7944  * Returns TRUE if no sw breakpoint was present.
7945  */
7946 gboolean
7947 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7948 {
7949         /*
7950          * If method_start is non-NULL we need to perform bound checks, since we access memory
7951          * at code - offset we could go before the start of the method and end up in a different
7952          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7953          * instead.
7954          */
7955         if (!method_start || code - offset >= method_start) {
7956                 memcpy (buf, code - offset, size);
7957         } else {
7958                 int diff = code - method_start;
7959                 memset (buf, 0, size);
7960                 memcpy (buf + offset - diff, method_start, diff + size - offset);
7961         }
7962         return TRUE;
7963 }
7964
7965 #if defined(__native_client_codegen__)
7966 /* For membase calls, we want the base register. for Native Client,  */
7967 /* all indirect calls have the following sequence with the given sizes: */
7968 /* mov %eXX,%eXX                                [2-3]   */
7969 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
7970 /* and $0xffffffffffffffe0,%r11d                [4]     */
7971 /* add %r15,%r11                                [3]     */
7972 /* callq *%r11                                  [3]     */
7973
7974
7975 /* Determine if code points to a NaCl call-through-register sequence, */
7976 /* (i.e., the last 3 instructions listed above) */
7977 int
7978 is_nacl_call_reg_sequence(guint8* code)
7979 {
7980         const char *sequence = "\x41\x83\xe3\xe0" /* and */
7981                                "\x4d\x03\xdf"     /* add */
7982                                "\x41\xff\xd3";   /* call */
7983         return memcmp(code, sequence, 10) == 0;
7984 }
7985
7986 /* Determine if code points to the first opcode of the mov membase component */
7987 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
7988 /* (there could be a REX prefix before the opcode but it is ignored) */
7989 static int
7990 is_nacl_indirect_call_membase_sequence(guint8* code)
7991 {
7992                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
7993         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
7994                /* and that src reg = dest reg */
7995                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
7996                /* Check that next inst is mov, uses SIB byte (rm = 4), */
7997                IS_REX(code[2]) &&
7998                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
7999                /* and has dst of r11 and base of r15 */
8000                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
8001                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
8002 }
8003 #endif /* __native_client_codegen__ */
8004
8005 int
8006 mono_arch_get_this_arg_reg (guint8 *code)
8007 {
8008         return AMD64_ARG_REG1;
8009 }
8010
8011 gpointer
8012 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8013 {
8014         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8015 }
8016
8017 #define MAX_ARCH_DELEGATE_PARAMS 10
8018
8019 static gpointer
8020 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8021 {
8022         guint8 *code, *start;
8023         GSList *unwind_ops = NULL;
8024         int i;
8025
8026         unwind_ops = mono_arch_get_cie_program ();
8027
8028         if (has_target) {
8029                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8030
8031                 /* Replace the this argument with the target */
8032                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8033                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8034                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8035
8036                 g_assert ((code - start) < 64);
8037         } else {
8038                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8039
8040                 if (param_count == 0) {
8041                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8042                 } else {
8043                         /* We have to shift the arguments left */
8044                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8045                         for (i = 0; i < param_count; ++i) {
8046 #ifdef TARGET_WIN32
8047                                 if (i < 3)
8048                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8049                                 else
8050                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8051 #else
8052                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8053 #endif
8054                         }
8055
8056                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8057                 }
8058                 g_assert ((code - start) < 64);
8059         }
8060
8061         nacl_global_codeman_validate (&start, 64, &code);
8062         mono_arch_flush_icache (start, code - start);
8063
8064         if (has_target) {
8065                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8066         } else {
8067                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8068                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8069                 g_free (name);
8070         }
8071
8072         if (mono_jit_map_is_enabled ()) {
8073                 char *buff;
8074                 if (has_target)
8075                         buff = (char*)"delegate_invoke_has_target";
8076                 else
8077                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8078                 mono_emit_jit_tramp (start, code - start, buff);
8079                 if (!has_target)
8080                         g_free (buff);
8081         }
8082         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8083
8084         return start;
8085 }
8086
8087 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8088
8089 static gpointer
8090 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8091 {
8092         guint8 *code, *start;
8093         int size = 20;
8094         char *tramp_name;
8095         GSList *unwind_ops;
8096
8097         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8098                 return NULL;
8099
8100         start = code = (guint8 *)mono_global_codeman_reserve (size);
8101
8102         unwind_ops = mono_arch_get_cie_program ();
8103
8104         /* Replace the this argument with the target */
8105         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8106         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8107
8108         if (load_imt_reg) {
8109                 /* Load the IMT reg */
8110                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8111         }
8112
8113         /* Load the vtable */
8114         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8115         amd64_jump_membase (code, AMD64_RAX, offset);
8116         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8117
8118         if (load_imt_reg)
8119                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8120         else
8121                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8122         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8123         g_free (tramp_name);
8124
8125         return start;
8126 }
8127
8128 /*
8129  * mono_arch_get_delegate_invoke_impls:
8130  *
8131  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8132  * trampolines.
8133  */
8134 GSList*
8135 mono_arch_get_delegate_invoke_impls (void)
8136 {
8137         GSList *res = NULL;
8138         MonoTrampInfo *info;
8139         int i;
8140
8141         get_delegate_invoke_impl (&info, TRUE, 0);
8142         res = g_slist_prepend (res, info);
8143
8144         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8145                 get_delegate_invoke_impl (&info, FALSE, i);
8146                 res = g_slist_prepend (res, info);
8147         }
8148
8149         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8150                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8151                 res = g_slist_prepend (res, info);
8152
8153                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8154                 res = g_slist_prepend (res, info);
8155         }
8156
8157         return res;
8158 }
8159
8160 gpointer
8161 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8162 {
8163         guint8 *code, *start;
8164         int i;
8165
8166         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8167                 return NULL;
8168
8169         /* FIXME: Support more cases */
8170         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8171                 return NULL;
8172
8173         if (has_target) {
8174                 static guint8* cached = NULL;
8175
8176                 if (cached)
8177                         return cached;
8178
8179                 if (mono_aot_only) {
8180                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8181                 } else {
8182                         MonoTrampInfo *info;
8183                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
8184                         mono_tramp_info_register (info, NULL);
8185                 }
8186
8187                 mono_memory_barrier ();
8188
8189                 cached = start;
8190         } else {
8191                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8192                 for (i = 0; i < sig->param_count; ++i)
8193                         if (!mono_is_regsize_var (sig->params [i]))
8194                                 return NULL;
8195                 if (sig->param_count > 4)
8196                         return NULL;
8197
8198                 code = cache [sig->param_count];
8199                 if (code)
8200                         return code;
8201
8202                 if (mono_aot_only) {
8203                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8204                         start = (guint8 *)mono_aot_get_trampoline (name);
8205                         g_free (name);
8206                 } else {
8207                         MonoTrampInfo *info;
8208                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8209                         mono_tramp_info_register (info, NULL);
8210                 }
8211
8212                 mono_memory_barrier ();
8213
8214                 cache [sig->param_count] = start;
8215         }
8216
8217         return start;
8218 }
8219
8220 gpointer
8221 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8222 {
8223         MonoTrampInfo *info;
8224         gpointer code;
8225
8226         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8227         if (code)
8228                 mono_tramp_info_register (info, NULL);
8229         return code;
8230 }
8231
8232 void
8233 mono_arch_finish_init (void)
8234 {
8235 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8236         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8237 #endif
8238 }
8239
8240 void
8241 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8242 {
8243 }
8244
8245 #if defined(__default_codegen__)
8246 #define CMP_SIZE (6 + 1)
8247 #define CMP_REG_REG_SIZE (4 + 1)
8248 #define BR_SMALL_SIZE 2
8249 #define BR_LARGE_SIZE 6
8250 #define MOV_REG_IMM_SIZE 10
8251 #define MOV_REG_IMM_32BIT_SIZE 6
8252 #define JUMP_REG_SIZE (2 + 1)
8253 #elif defined(__native_client_codegen__)
8254 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8255 #define CMP_SIZE ((6 + 1) * 2 - 1)
8256 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8257 #define BR_SMALL_SIZE (2 * 2 - 1)
8258 #define BR_LARGE_SIZE (6 * 2 - 1)
8259 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8260 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8261 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8262 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8263 /* Jump membase's size is large and unpredictable    */
8264 /* in native client, just pad it out a whole bundle. */
8265 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8266 #endif
8267
8268 static int
8269 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8270 {
8271         int i, distance = 0;
8272         for (i = start; i < target; ++i)
8273                 distance += imt_entries [i]->chunk_size;
8274         return distance;
8275 }
8276
8277 /*
8278  * LOCKING: called with the domain lock held
8279  */
8280 gpointer
8281 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8282         gpointer fail_tramp)
8283 {
8284         int i;
8285         int size = 0;
8286         guint8 *code, *start;
8287         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8288         GSList *unwind_ops;
8289
8290         for (i = 0; i < count; ++i) {
8291                 MonoIMTCheckItem *item = imt_entries [i];
8292                 if (item->is_equals) {
8293                         if (item->check_target_idx) {
8294                                 if (!item->compare_done) {
8295                                         if (amd64_use_imm32 ((gint64)item->key))
8296                                                 item->chunk_size += CMP_SIZE;
8297                                         else
8298                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8299                                 }
8300                                 if (item->has_target_code) {
8301                                         item->chunk_size += MOV_REG_IMM_SIZE;
8302                                 } else {
8303                                         if (vtable_is_32bit)
8304                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8305                                         else
8306                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8307 #ifdef __native_client_codegen__
8308                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8309 #endif
8310                                 }
8311                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8312                         } else {
8313                                 if (fail_tramp) {
8314                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8315                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8316                                 } else {
8317                                         if (vtable_is_32bit)
8318                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8319                                         else
8320                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8321                                         item->chunk_size += JUMP_REG_SIZE;
8322                                         /* with assert below:
8323                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8324                                          */
8325 #ifdef __native_client_codegen__
8326                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8327 #endif
8328                                 }
8329                         }
8330                 } else {
8331                         if (amd64_use_imm32 ((gint64)item->key))
8332                                 item->chunk_size += CMP_SIZE;
8333                         else
8334                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8335                         item->chunk_size += BR_LARGE_SIZE;
8336                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8337                 }
8338                 size += item->chunk_size;
8339         }
8340 #if defined(__native_client__) && defined(__native_client_codegen__)
8341         /* In Native Client, we don't re-use thunks, allocate from the */
8342         /* normal code manager paths. */
8343         code = mono_domain_code_reserve (domain, size);
8344 #else
8345         if (fail_tramp)
8346                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8347         else
8348                 code = (guint8 *)mono_domain_code_reserve (domain, size);
8349 #endif
8350         start = code;
8351
8352         unwind_ops = mono_arch_get_cie_program ();
8353
8354         for (i = 0; i < count; ++i) {
8355                 MonoIMTCheckItem *item = imt_entries [i];
8356                 item->code_target = code;
8357                 if (item->is_equals) {
8358                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8359
8360                         if (item->check_target_idx || fail_case) {
8361                                 if (!item->compare_done || fail_case) {
8362                                         if (amd64_use_imm32 ((gint64)item->key))
8363                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8364                                         else {
8365                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8366                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8367                                         }
8368                                 }
8369                                 item->jmp_code = code;
8370                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8371                                 if (item->has_target_code) {
8372                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8373                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8374                                 } else {
8375                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8376                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8377                                 }
8378
8379                                 if (fail_case) {
8380                                         amd64_patch (item->jmp_code, code);
8381                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8382                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8383                                         item->jmp_code = NULL;
8384                                 }
8385                         } else {
8386                                 /* enable the commented code to assert on wrong method */
8387 #if 0
8388                                 if (amd64_is_imm32 (item->key))
8389                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8390                                 else {
8391                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8392                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8393                                 }
8394                                 item->jmp_code = code;
8395                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8396                                 /* See the comment below about R10 */
8397                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8398                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8399                                 amd64_patch (item->jmp_code, code);
8400                                 amd64_breakpoint (code);
8401                                 item->jmp_code = NULL;
8402 #else
8403                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8404                                    needs to be preserved.  R10 needs
8405                                    to be preserved for calls which
8406                                    require a runtime generic context,
8407                                    but interface calls don't. */
8408                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8409                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8410 #endif
8411                         }
8412                 } else {
8413                         if (amd64_use_imm32 ((gint64)item->key))
8414                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8415                         else {
8416                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8417                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8418                         }
8419                         item->jmp_code = code;
8420                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8421                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8422                         else
8423                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8424                 }
8425                 g_assert (code - item->code_target <= item->chunk_size);
8426         }
8427         /* patch the branches to get to the target items */
8428         for (i = 0; i < count; ++i) {
8429                 MonoIMTCheckItem *item = imt_entries [i];
8430                 if (item->jmp_code) {
8431                         if (item->check_target_idx) {
8432                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8433                         }
8434                 }
8435         }
8436
8437         if (!fail_tramp)
8438                 mono_stats.imt_thunks_size += code - start;
8439         g_assert (code - start <= size);
8440
8441         nacl_domain_code_validate(domain, &start, size, &code);
8442         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8443
8444         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8445
8446         return start;
8447 }
8448
8449 MonoMethod*
8450 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8451 {
8452         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8453 }
8454
8455 MonoVTable*
8456 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8457 {
8458         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8459 }
8460
8461 GSList*
8462 mono_arch_get_cie_program (void)
8463 {
8464         GSList *l = NULL;
8465
8466         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8467         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8468
8469         return l;
8470 }
8471
8472 #ifndef DISABLE_JIT
8473
8474 MonoInst*
8475 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8476 {
8477         MonoInst *ins = NULL;
8478         int opcode = 0;
8479
8480         if (cmethod->klass == mono_defaults.math_class) {
8481                 if (strcmp (cmethod->name, "Sin") == 0) {
8482                         opcode = OP_SIN;
8483                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8484                         opcode = OP_COS;
8485                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8486                         opcode = OP_SQRT;
8487                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8488                         opcode = OP_ABS;
8489                 }
8490
8491                 if (opcode && fsig->param_count == 1) {
8492                         MONO_INST_NEW (cfg, ins, opcode);
8493                         ins->type = STACK_R8;
8494                         ins->dreg = mono_alloc_freg (cfg);
8495                         ins->sreg1 = args [0]->dreg;
8496                         MONO_ADD_INS (cfg->cbb, ins);
8497                 }
8498
8499                 opcode = 0;
8500                 if (cfg->opt & MONO_OPT_CMOV) {
8501                         if (strcmp (cmethod->name, "Min") == 0) {
8502                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8503                                         opcode = OP_IMIN;
8504                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8505                                         opcode = OP_IMIN_UN;
8506                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8507                                         opcode = OP_LMIN;
8508                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8509                                         opcode = OP_LMIN_UN;
8510                         } else if (strcmp (cmethod->name, "Max") == 0) {
8511                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8512                                         opcode = OP_IMAX;
8513                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8514                                         opcode = OP_IMAX_UN;
8515                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8516                                         opcode = OP_LMAX;
8517                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8518                                         opcode = OP_LMAX_UN;
8519                         }
8520                 }
8521
8522                 if (opcode && fsig->param_count == 2) {
8523                         MONO_INST_NEW (cfg, ins, opcode);
8524                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8525                         ins->dreg = mono_alloc_ireg (cfg);
8526                         ins->sreg1 = args [0]->dreg;
8527                         ins->sreg2 = args [1]->dreg;
8528                         MONO_ADD_INS (cfg->cbb, ins);
8529                 }
8530
8531 #if 0
8532                 /* OP_FREM is not IEEE compatible */
8533                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8534                         MONO_INST_NEW (cfg, ins, OP_FREM);
8535                         ins->inst_i0 = args [0];
8536                         ins->inst_i1 = args [1];
8537                 }
8538 #endif
8539         }
8540
8541         return ins;
8542 }
8543 #endif
8544
8545 gboolean
8546 mono_arch_print_tree (MonoInst *tree, int arity)
8547 {
8548         return 0;
8549 }
8550
8551 mgreg_t
8552 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8553 {
8554         return ctx->gregs [reg];
8555 }
8556
8557 void
8558 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8559 {
8560         ctx->gregs [reg] = val;
8561 }
8562
8563 gpointer
8564 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8565 {
8566         gpointer *sp, old_value;
8567         char *bp;
8568
8569         /*Load the spvar*/
8570         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8571         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8572
8573         old_value = *sp;
8574         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8575                 return old_value;
8576
8577         *sp = new_value;
8578
8579         return old_value;
8580 }
8581
8582 /*
8583  * mono_arch_emit_load_aotconst:
8584  *
8585  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8586  * TARGET from the mscorlib GOT in full-aot code.
8587  * On AMD64, the result is placed into R11.
8588  */
8589 guint8*
8590 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8591 {
8592         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8593         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8594
8595         return code;
8596 }
8597
8598 /*
8599  * mono_arch_get_trampolines:
8600  *
8601  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8602  * for AOT.
8603  */
8604 GSList *
8605 mono_arch_get_trampolines (gboolean aot)
8606 {
8607         return mono_amd64_get_exception_trampolines (aot);
8608 }
8609
8610 /* Soft Debug support */
8611 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8612
8613 /*
8614  * mono_arch_set_breakpoint:
8615  *
8616  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8617  * The location should contain code emitted by OP_SEQ_POINT.
8618  */
8619 void
8620 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8621 {
8622         guint8 *code = ip;
8623
8624         if (ji->from_aot) {
8625                 guint32 native_offset = ip - (guint8*)ji->code_start;
8626                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8627
8628                 g_assert (info->bp_addrs [native_offset] == 0);
8629                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8630         } else {
8631                 /* ip points to a mov r11, 0 */
8632                 g_assert (code [0] == 0x41);
8633                 g_assert (code [1] == 0xbb);
8634                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8635         }
8636 }
8637
8638 /*
8639  * mono_arch_clear_breakpoint:
8640  *
8641  *   Clear the breakpoint at IP.
8642  */
8643 void
8644 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8645 {
8646         guint8 *code = ip;
8647
8648         if (ji->from_aot) {
8649                 guint32 native_offset = ip - (guint8*)ji->code_start;
8650                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8651
8652                 info->bp_addrs [native_offset] = NULL;
8653         } else {
8654                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8655         }
8656 }
8657
8658 gboolean
8659 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8660 {
8661         /* We use soft breakpoints on amd64 */
8662         return FALSE;
8663 }
8664
8665 /*
8666  * mono_arch_skip_breakpoint:
8667  *
8668  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8669  * we resume, the instruction is not executed again.
8670  */
8671 void
8672 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8673 {
8674         g_assert_not_reached ();
8675 }
8676
8677 /*
8678  * mono_arch_start_single_stepping:
8679  *
8680  *   Start single stepping.
8681  */
8682 void
8683 mono_arch_start_single_stepping (void)
8684 {
8685         ss_trampoline = mini_get_single_step_trampoline ();
8686 }
8687
8688 /*
8689  * mono_arch_stop_single_stepping:
8690  *
8691  *   Stop single stepping.
8692  */
8693 void
8694 mono_arch_stop_single_stepping (void)
8695 {
8696         ss_trampoline = NULL;
8697 }
8698
8699 /*
8700  * mono_arch_is_single_step_event:
8701  *
8702  *   Return whenever the machine state in SIGCTX corresponds to a single
8703  * step event.
8704  */
8705 gboolean
8706 mono_arch_is_single_step_event (void *info, void *sigctx)
8707 {
8708         /* We use soft breakpoints on amd64 */
8709         return FALSE;
8710 }
8711
8712 /*
8713  * mono_arch_skip_single_step:
8714  *
8715  *   Modify CTX so the ip is placed after the single step trigger instruction,
8716  * we resume, the instruction is not executed again.
8717  */
8718 void
8719 mono_arch_skip_single_step (MonoContext *ctx)
8720 {
8721         g_assert_not_reached ();
8722 }
8723
8724 /*
8725  * mono_arch_create_seq_point_info:
8726  *
8727  *   Return a pointer to a data structure which is used by the sequence
8728  * point implementation in AOTed code.
8729  */
8730 gpointer
8731 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8732 {
8733         SeqPointInfo *info;
8734         MonoJitInfo *ji;
8735
8736         // FIXME: Add a free function
8737
8738         mono_domain_lock (domain);
8739         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8740                                                                 code);
8741         mono_domain_unlock (domain);
8742
8743         if (!info) {
8744                 ji = mono_jit_info_table_find (domain, (char*)code);
8745                 g_assert (ji);
8746
8747                 // FIXME: Optimize the size
8748                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8749
8750                 info->ss_tramp_addr = &ss_trampoline;
8751
8752                 mono_domain_lock (domain);
8753                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8754                                                          code, info);
8755                 mono_domain_unlock (domain);
8756         }
8757
8758         return info;
8759 }
8760
8761 void
8762 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8763 {
8764         ext->lmf.previous_lmf = prev_lmf;
8765         /* Mark that this is a MonoLMFExt */
8766         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8767         ext->lmf.rsp = (gssize)ext;
8768 }
8769
8770 #endif
8771
8772 gboolean
8773 mono_arch_opcode_supported (int opcode)
8774 {
8775         switch (opcode) {
8776         case OP_ATOMIC_ADD_I4:
8777         case OP_ATOMIC_ADD_I8:
8778         case OP_ATOMIC_EXCHANGE_I4:
8779         case OP_ATOMIC_EXCHANGE_I8:
8780         case OP_ATOMIC_CAS_I4:
8781         case OP_ATOMIC_CAS_I8:
8782         case OP_ATOMIC_LOAD_I1:
8783         case OP_ATOMIC_LOAD_I2:
8784         case OP_ATOMIC_LOAD_I4:
8785         case OP_ATOMIC_LOAD_I8:
8786         case OP_ATOMIC_LOAD_U1:
8787         case OP_ATOMIC_LOAD_U2:
8788         case OP_ATOMIC_LOAD_U4:
8789         case OP_ATOMIC_LOAD_U8:
8790         case OP_ATOMIC_LOAD_R4:
8791         case OP_ATOMIC_LOAD_R8:
8792         case OP_ATOMIC_STORE_I1:
8793         case OP_ATOMIC_STORE_I2:
8794         case OP_ATOMIC_STORE_I4:
8795         case OP_ATOMIC_STORE_I8:
8796         case OP_ATOMIC_STORE_U1:
8797         case OP_ATOMIC_STORE_U2:
8798         case OP_ATOMIC_STORE_U4:
8799         case OP_ATOMIC_STORE_U8:
8800         case OP_ATOMIC_STORE_R4:
8801         case OP_ATOMIC_STORE_R8:
8802                 return TRUE;
8803         default:
8804                 return FALSE;
8805         }
8806 }
8807
8808 #if defined(ENABLE_GSHAREDVT) && defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
8809
8810 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8811
8812 #endif /* !MONOTOUCH */