2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
21 #include <mono/metadata/appdomain.h>
22 #include <mono/metadata/debug-helpers.h>
23 #include <mono/metadata/threads.h>
24 #include <mono/metadata/profiler-private.h>
25 #include <mono/metadata/mono-debug.h>
26 #include <mono/utils/mono-math.h>
29 #include "mini-amd64.h"
31 #include "cpu-amd64.h"
34 * Can't define this in mini-amd64.h cause that would turn on the generic code in
37 #define MONO_ARCH_IMT_REG AMD64_R11
39 static gint lmf_tls_offset = -1;
40 static gint lmf_addr_tls_offset = -1;
41 static gint appdomain_tls_offset = -1;
42 static gint thread_tls_offset = -1;
45 static gboolean optimize_for_xen = TRUE;
47 #define optimize_for_xen 0
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
66 static CRITICAL_SECTION mini_arch_mutex;
69 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
72 /* On Win64 always reserve first 32 bytes for first four arguments */
73 #define ARGS_OFFSET 48
75 #define ARGS_OFFSET 16
77 #define GP_SCRATCH_REG AMD64_R11
80 * AMD64 register usage:
81 * - callee saved registers are used for global register allocation
82 * - %r11 is used for materializing 64 bit constants in opcodes
83 * - the rest is used for local allocation
87 * Floating point comparison results:
96 void mini_emit_memcpy2 (MonoCompile *cfg, int destreg, int doffset, int srcreg, int soffset, int size, int align);
99 mono_arch_regname (int reg)
102 case AMD64_RAX: return "%rax";
103 case AMD64_RBX: return "%rbx";
104 case AMD64_RCX: return "%rcx";
105 case AMD64_RDX: return "%rdx";
106 case AMD64_RSP: return "%rsp";
107 case AMD64_RBP: return "%rbp";
108 case AMD64_RDI: return "%rdi";
109 case AMD64_RSI: return "%rsi";
110 case AMD64_R8: return "%r8";
111 case AMD64_R9: return "%r9";
112 case AMD64_R10: return "%r10";
113 case AMD64_R11: return "%r11";
114 case AMD64_R12: return "%r12";
115 case AMD64_R13: return "%r13";
116 case AMD64_R14: return "%r14";
117 case AMD64_R15: return "%r15";
122 static const char * xmmregs [] = {
123 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8",
124 "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
128 mono_arch_fregname (int reg)
130 if (reg < AMD64_XMM_NREG)
131 return xmmregs [reg];
136 G_GNUC_UNUSED static void
141 G_GNUC_UNUSED static gboolean
144 static int count = 0;
147 if (!getenv ("COUNT"))
150 if (count == atoi (getenv ("COUNT"))) {
154 if (count > atoi (getenv ("COUNT"))) {
165 return debug_count ();
171 static inline gboolean
172 amd64_is_near_call (guint8 *code)
175 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
178 return code [0] == 0xe8;
182 amd64_patch (unsigned char* code, gpointer target)
187 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
192 if ((code [0] & 0xf8) == 0xb8) {
193 /* amd64_set_reg_template */
194 *(guint64*)(code + 1) = (guint64)target;
196 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
197 /* mov 0(%rip), %dreg */
198 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
200 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
201 /* call *<OFFSET>(%rip) */
202 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
204 else if ((code [0] == 0xe8)) {
206 gint64 disp = (guint8*)target - (guint8*)code;
207 g_assert (amd64_is_imm32 (disp));
208 x86_patch (code, (unsigned char*)target);
211 x86_patch (code, (unsigned char*)target);
215 mono_amd64_patch (unsigned char* code, gpointer target)
217 amd64_patch (code, target);
226 ArgValuetypeAddrInIReg,
227 ArgNone /* only in pair_storage */
235 /* Only if storage == ArgValuetypeInReg */
236 ArgStorage pair_storage [2];
245 gboolean need_stack_align;
251 #define DEBUG(a) if (cfg->verbose_level > 1) a
253 #define NEW_ICONST(cfg,dest,val) do { \
254 (dest) = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
255 (dest)->opcode = OP_ICONST; \
256 (dest)->inst_c0 = (val); \
257 (dest)->type = STACK_I4; \
260 #ifdef PLATFORM_WIN32
263 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
265 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
269 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
271 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
275 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
277 ainfo->offset = *stack_size;
279 if (*gr >= PARAM_REGS) {
280 ainfo->storage = ArgOnStack;
281 (*stack_size) += sizeof (gpointer);
284 ainfo->storage = ArgInIReg;
285 ainfo->reg = param_regs [*gr];
290 #ifdef PLATFORM_WIN32
291 #define FLOAT_PARAM_REGS 4
293 #define FLOAT_PARAM_REGS 8
297 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
299 ainfo->offset = *stack_size;
301 if (*gr >= FLOAT_PARAM_REGS) {
302 ainfo->storage = ArgOnStack;
303 (*stack_size) += sizeof (gpointer);
306 /* A double register */
308 ainfo->storage = ArgInDoubleSSEReg;
310 ainfo->storage = ArgInFloatSSEReg;
316 typedef enum ArgumentClass {
324 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
326 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
329 ptype = mini_type_get_underlying_type (NULL, type);
330 switch (ptype->type) {
331 case MONO_TYPE_BOOLEAN:
341 case MONO_TYPE_STRING:
342 case MONO_TYPE_OBJECT:
343 case MONO_TYPE_CLASS:
344 case MONO_TYPE_SZARRAY:
346 case MONO_TYPE_FNPTR:
347 case MONO_TYPE_ARRAY:
350 class2 = ARG_CLASS_INTEGER;
354 #ifdef PLATFORM_WIN32
355 class2 = ARG_CLASS_INTEGER;
357 class2 = ARG_CLASS_SSE;
361 case MONO_TYPE_TYPEDBYREF:
362 g_assert_not_reached ();
364 case MONO_TYPE_GENERICINST:
365 if (!mono_type_generic_inst_is_valuetype (ptype)) {
366 class2 = ARG_CLASS_INTEGER;
370 case MONO_TYPE_VALUETYPE: {
371 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
374 for (i = 0; i < info->num_fields; ++i) {
376 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
381 g_assert_not_reached ();
385 if (class1 == class2)
387 else if (class1 == ARG_CLASS_NO_CLASS)
389 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
390 class1 = ARG_CLASS_MEMORY;
391 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
392 class1 = ARG_CLASS_INTEGER;
394 class1 = ARG_CLASS_SSE;
400 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
402 guint32 *gr, guint32 *fr, guint32 *stack_size)
404 guint32 size, quad, nquads, i;
405 ArgumentClass args [2];
406 MonoMarshalType *info;
408 MonoGenericSharingContext tmp_gsctx;
411 * The gsctx currently contains no data, it is only used for checking whenever
412 * open types are allowed, some callers like mono_arch_get_argument_info ()
413 * don't pass it to us, so work around that.
418 klass = mono_class_from_mono_type (type);
419 size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
420 #ifndef PLATFORM_WIN32
421 if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
422 /* We pass and return vtypes of size 8 in a register */
423 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
427 /* Allways pass in memory */
428 ainfo->offset = *stack_size;
429 *stack_size += ALIGN_TO (size, 8);
430 ainfo->storage = ArgOnStack;
435 /* FIXME: Handle structs smaller than 8 bytes */
436 //if ((size % 8) != 0)
445 /* Always pass in 1 or 2 integer registers */
446 args [0] = ARG_CLASS_INTEGER;
447 args [1] = ARG_CLASS_INTEGER;
448 /* Only the simplest cases are supported */
449 if (is_return && nquads != 1) {
450 args [0] = ARG_CLASS_MEMORY;
451 args [1] = ARG_CLASS_MEMORY;
455 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
456 * The X87 and SSEUP stuff is left out since there are no such types in
459 info = mono_marshal_load_type_info (klass);
462 #ifndef PLATFORM_WIN32
463 if (info->native_size > 16) {
464 ainfo->offset = *stack_size;
465 *stack_size += ALIGN_TO (info->native_size, 8);
466 ainfo->storage = ArgOnStack;
471 switch (info->native_size) {
472 case 1: case 2: case 4: case 8:
476 ainfo->storage = ArgOnStack;
477 ainfo->offset = *stack_size;
478 *stack_size += ALIGN_TO (info->native_size, 8);
481 ainfo->storage = ArgValuetypeAddrInIReg;
483 if (*gr < PARAM_REGS) {
484 ainfo->pair_storage [0] = ArgInIReg;
485 ainfo->pair_regs [0] = param_regs [*gr];
489 ainfo->pair_storage [0] = ArgOnStack;
490 ainfo->offset = *stack_size;
499 args [0] = ARG_CLASS_NO_CLASS;
500 args [1] = ARG_CLASS_NO_CLASS;
501 for (quad = 0; quad < nquads; ++quad) {
504 ArgumentClass class1;
506 if (info->num_fields == 0)
507 class1 = ARG_CLASS_MEMORY;
509 class1 = ARG_CLASS_NO_CLASS;
510 for (i = 0; i < info->num_fields; ++i) {
511 size = mono_marshal_type_size (info->fields [i].field->type,
512 info->fields [i].mspec,
513 &align, TRUE, klass->unicode);
514 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
515 /* Unaligned field */
519 /* Skip fields in other quad */
520 if ((quad == 0) && (info->fields [i].offset >= 8))
522 if ((quad == 1) && (info->fields [i].offset < 8))
525 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
527 g_assert (class1 != ARG_CLASS_NO_CLASS);
528 args [quad] = class1;
532 /* Post merger cleanup */
533 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
534 args [0] = args [1] = ARG_CLASS_MEMORY;
536 /* Allocate registers */
541 ainfo->storage = ArgValuetypeInReg;
542 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
543 for (quad = 0; quad < nquads; ++quad) {
544 switch (args [quad]) {
545 case ARG_CLASS_INTEGER:
546 if (*gr >= PARAM_REGS)
547 args [quad] = ARG_CLASS_MEMORY;
549 ainfo->pair_storage [quad] = ArgInIReg;
551 ainfo->pair_regs [quad] = return_regs [*gr];
553 ainfo->pair_regs [quad] = param_regs [*gr];
558 if (*fr >= FLOAT_PARAM_REGS)
559 args [quad] = ARG_CLASS_MEMORY;
561 ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
562 ainfo->pair_regs [quad] = *fr;
566 case ARG_CLASS_MEMORY:
569 g_assert_not_reached ();
573 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
574 /* Revert possible register assignments */
578 ainfo->offset = *stack_size;
580 *stack_size += ALIGN_TO (info->native_size, 8);
582 *stack_size += nquads * sizeof (gpointer);
583 ainfo->storage = ArgOnStack;
591 * Obtain information about a call according to the calling convention.
592 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
593 * Draft Version 0.23" document for more information.
596 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
600 int n = sig->hasthis + sig->param_count;
601 guint32 stack_size = 0;
605 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
607 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
614 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
615 switch (ret_type->type) {
616 case MONO_TYPE_BOOLEAN:
627 case MONO_TYPE_FNPTR:
628 case MONO_TYPE_CLASS:
629 case MONO_TYPE_OBJECT:
630 case MONO_TYPE_SZARRAY:
631 case MONO_TYPE_ARRAY:
632 case MONO_TYPE_STRING:
633 cinfo->ret.storage = ArgInIReg;
634 cinfo->ret.reg = AMD64_RAX;
638 cinfo->ret.storage = ArgInIReg;
639 cinfo->ret.reg = AMD64_RAX;
642 cinfo->ret.storage = ArgInFloatSSEReg;
643 cinfo->ret.reg = AMD64_XMM0;
646 cinfo->ret.storage = ArgInDoubleSSEReg;
647 cinfo->ret.reg = AMD64_XMM0;
649 case MONO_TYPE_GENERICINST:
650 if (!mono_type_generic_inst_is_valuetype (sig->ret)) {
651 cinfo->ret.storage = ArgInIReg;
652 cinfo->ret.reg = AMD64_RAX;
656 case MONO_TYPE_VALUETYPE: {
657 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
659 add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
660 if (cinfo->ret.storage == ArgOnStack)
661 /* The caller passes the address where the value is stored */
662 add_general (&gr, &stack_size, &cinfo->ret);
665 case MONO_TYPE_TYPEDBYREF:
666 /* Same as a valuetype with size 24 */
667 add_general (&gr, &stack_size, &cinfo->ret);
673 g_error ("Can't handle as return value 0x%x", sig->ret->type);
679 add_general (&gr, &stack_size, cinfo->args + 0);
681 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
683 fr = FLOAT_PARAM_REGS;
685 /* Emit the signature cookie just before the implicit arguments */
686 add_general (&gr, &stack_size, &cinfo->sig_cookie);
689 for (i = 0; i < sig->param_count; ++i) {
690 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
693 #ifdef PLATFORM_WIN32
694 /* The float param registers and other param registers must be the same index on Windows x64.*/
701 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
702 /* We allways pass the sig cookie on the stack for simplicity */
704 * Prevent implicit arguments + the sig cookie from being passed
708 fr = FLOAT_PARAM_REGS;
710 /* Emit the signature cookie just before the implicit arguments */
711 add_general (&gr, &stack_size, &cinfo->sig_cookie);
714 if (sig->params [i]->byref) {
715 add_general (&gr, &stack_size, ainfo);
718 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
719 switch (ptype->type) {
720 case MONO_TYPE_BOOLEAN:
723 add_general (&gr, &stack_size, ainfo);
728 add_general (&gr, &stack_size, ainfo);
732 add_general (&gr, &stack_size, ainfo);
737 case MONO_TYPE_FNPTR:
738 case MONO_TYPE_CLASS:
739 case MONO_TYPE_OBJECT:
740 case MONO_TYPE_STRING:
741 case MONO_TYPE_SZARRAY:
742 case MONO_TYPE_ARRAY:
743 add_general (&gr, &stack_size, ainfo);
745 case MONO_TYPE_GENERICINST:
746 if (!mono_type_generic_inst_is_valuetype (ptype)) {
747 add_general (&gr, &stack_size, ainfo);
751 case MONO_TYPE_VALUETYPE:
752 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
754 case MONO_TYPE_TYPEDBYREF:
755 #ifdef PLATFORM_WIN32
756 add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
758 stack_size += sizeof (MonoTypedRef);
759 ainfo->storage = ArgOnStack;
764 add_general (&gr, &stack_size, ainfo);
767 add_float (&fr, &stack_size, ainfo, FALSE);
770 add_float (&fr, &stack_size, ainfo, TRUE);
773 g_assert_not_reached ();
777 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
779 fr = FLOAT_PARAM_REGS;
781 /* Emit the signature cookie just before the implicit arguments */
782 add_general (&gr, &stack_size, &cinfo->sig_cookie);
785 #ifdef PLATFORM_WIN32
786 // There always is 32 bytes reserved on the stack when calling on Winx64
790 if (stack_size & 0x8) {
791 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
792 cinfo->need_stack_align = TRUE;
796 cinfo->stack_usage = stack_size;
797 cinfo->reg_usage = gr;
798 cinfo->freg_usage = fr;
803 * mono_arch_get_argument_info:
804 * @csig: a method signature
805 * @param_count: the number of parameters to consider
806 * @arg_info: an array to store the result infos
808 * Gathers information on parameters such as size, alignment and
809 * padding. arg_info should be large enought to hold param_count + 1 entries.
811 * Returns the size of the argument area on the stack.
814 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
817 CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
818 guint32 args_size = cinfo->stack_usage;
820 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
822 arg_info [0].offset = 0;
825 for (k = 0; k < param_count; k++) {
826 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
828 arg_info [k + 1].size = 0;
837 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
840 __asm__ __volatile__ ("cpuid"
841 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
855 * Initialize the cpu to execute managed code.
858 mono_arch_cpu_init (void)
863 /* spec compliance requires running with double precision */
864 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
865 fpcw &= ~X86_FPCW_PRECC_MASK;
866 fpcw |= X86_FPCW_PREC_DOUBLE;
867 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
868 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
870 /* TODO: This is crashing on Win64 right now.
871 * _control87 (_PC_53, MCW_PC);
877 * Initialize architecture specific code.
880 mono_arch_init (void)
882 InitializeCriticalSection (&mini_arch_mutex);
886 * Cleanup architecture specific code.
889 mono_arch_cleanup (void)
891 DeleteCriticalSection (&mini_arch_mutex);
895 * This function returns the optimizations supported on this cpu.
898 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
900 int eax, ebx, ecx, edx;
906 /* Feature Flags function, flags returned in EDX. */
907 if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
908 if (edx & (1 << 15)) {
909 opts |= MONO_OPT_CMOV;
911 opts |= MONO_OPT_FCMOV;
913 *exclude_mask |= MONO_OPT_FCMOV;
915 *exclude_mask |= MONO_OPT_CMOV;
922 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
927 for (i = 0; i < cfg->num_varinfo; i++) {
928 MonoInst *ins = cfg->varinfo [i];
929 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
932 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
935 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
936 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
939 if (mono_is_regsize_var (ins->inst_vtype)) {
940 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
941 g_assert (i == vmv->idx);
942 vars = g_list_prepend (vars, vmv);
946 vars = mono_varlist_sort (cfg, vars, 0);
952 * mono_arch_compute_omit_fp:
954 * Determine whenever the frame pointer can be eliminated.
957 mono_arch_compute_omit_fp (MonoCompile *cfg)
959 MonoMethodSignature *sig;
960 MonoMethodHeader *header;
964 if (cfg->arch.omit_fp_computed)
967 header = mono_method_get_header (cfg->method);
969 sig = mono_method_signature (cfg->method);
971 if (!cfg->arch.cinfo)
972 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
973 cinfo = cfg->arch.cinfo;
976 * FIXME: Remove some of the restrictions.
978 cfg->arch.omit_fp = TRUE;
979 cfg->arch.omit_fp_computed = TRUE;
981 if (cfg->disable_omit_fp)
982 cfg->arch.omit_fp = FALSE;
984 if (!debug_omit_fp ())
985 cfg->arch.omit_fp = FALSE;
987 if (cfg->method->save_lmf)
988 cfg->arch.omit_fp = FALSE;
990 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
991 cfg->arch.omit_fp = FALSE;
992 if (header->num_clauses)
993 cfg->arch.omit_fp = FALSE;
995 cfg->arch.omit_fp = FALSE;
996 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
997 cfg->arch.omit_fp = FALSE;
998 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
999 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1000 cfg->arch.omit_fp = FALSE;
1001 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1002 ArgInfo *ainfo = &cinfo->args [i];
1004 if (ainfo->storage == ArgOnStack) {
1006 * The stack offset can only be determined when the frame
1009 cfg->arch.omit_fp = FALSE;
1014 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1015 MonoInst *ins = cfg->varinfo [i];
1018 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1021 if ((cfg->num_varinfo > 10000) || (locals_size >= (1 << 15))) {
1022 /* Avoid hitting the stack_alloc_size < (1 << 16) assertion in emit_epilog () */
1023 cfg->arch.omit_fp = FALSE;
1028 mono_arch_get_global_int_regs (MonoCompile *cfg)
1032 mono_arch_compute_omit_fp (cfg);
1034 if (cfg->globalra) {
1035 if (cfg->arch.omit_fp)
1036 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1038 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1039 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1040 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1041 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1042 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1044 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1045 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1046 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1047 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1048 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1049 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1050 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1051 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1053 if (cfg->arch.omit_fp)
1054 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1056 /* We use the callee saved registers for global allocation */
1057 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1058 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1059 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1060 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1061 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1068 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1073 /* All XMM registers */
1074 for (i = 0; i < 16; ++i)
1075 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1081 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1083 static GList *r = NULL;
1088 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1089 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1090 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1091 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1092 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1093 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1095 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1096 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1097 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1098 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1099 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1100 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1101 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1102 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1104 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1111 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1114 static GList *r = NULL;
1119 for (i = 0; i < AMD64_XMM_NREG; ++i)
1120 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1122 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1129 * mono_arch_regalloc_cost:
1131 * Return the cost, in number of memory references, of the action of
1132 * allocating the variable VMV into a register during global register
1136 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1138 MonoInst *ins = cfg->varinfo [vmv->idx];
1140 if (cfg->method->save_lmf)
1141 /* The register is already saved */
1142 /* substract 1 for the invisible store in the prolog */
1143 return (ins->opcode == OP_ARG) ? 0 : 1;
1146 return (ins->opcode == OP_ARG) ? 1 : 2;
1150 * mono_arch_fill_argument_info:
1152 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1156 mono_arch_fill_argument_info (MonoCompile *cfg)
1158 MonoMethodSignature *sig;
1159 MonoMethodHeader *header;
1164 header = mono_method_get_header (cfg->method);
1166 sig = mono_method_signature (cfg->method);
1168 cinfo = cfg->arch.cinfo;
1171 * Contrary to mono_arch_allocate_vars (), the information should describe
1172 * where the arguments are at the beginning of the method, not where they can be
1173 * accessed during the execution of the method. The later makes no sense for the
1174 * global register allocator, since a variable can be in more than one location.
1176 if (sig->ret->type != MONO_TYPE_VOID) {
1177 switch (cinfo->ret.storage) {
1179 case ArgInFloatSSEReg:
1180 case ArgInDoubleSSEReg:
1181 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1182 cfg->vret_addr->opcode = OP_REGVAR;
1183 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1186 cfg->ret->opcode = OP_REGVAR;
1187 cfg->ret->inst_c0 = cinfo->ret.reg;
1190 case ArgValuetypeInReg:
1191 cfg->ret->opcode = OP_REGOFFSET;
1192 cfg->ret->inst_basereg = -1;
1193 cfg->ret->inst_offset = -1;
1196 g_assert_not_reached ();
1200 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1201 ArgInfo *ainfo = &cinfo->args [i];
1204 ins = cfg->args [i];
1206 if (sig->hasthis && (i == 0))
1207 arg_type = &mono_defaults.object_class->byval_arg;
1209 arg_type = sig->params [i - sig->hasthis];
1211 switch (ainfo->storage) {
1213 case ArgInFloatSSEReg:
1214 case ArgInDoubleSSEReg:
1215 ins->opcode = OP_REGVAR;
1216 ins->inst_c0 = ainfo->reg;
1219 ins->opcode = OP_REGOFFSET;
1220 ins->inst_basereg = -1;
1221 ins->inst_offset = -1;
1223 case ArgValuetypeInReg:
1225 ins->opcode = OP_NOP;
1228 g_assert_not_reached ();
1234 mono_arch_allocate_vars (MonoCompile *cfg)
1236 MonoMethodSignature *sig;
1237 MonoMethodHeader *header;
1240 guint32 locals_stack_size, locals_stack_align;
1244 header = mono_method_get_header (cfg->method);
1246 sig = mono_method_signature (cfg->method);
1248 cinfo = cfg->arch.cinfo;
1250 mono_arch_compute_omit_fp (cfg);
1253 * We use the ABI calling conventions for managed code as well.
1254 * Exception: valuetypes are never passed or returned in registers.
1257 if (cfg->arch.omit_fp) {
1258 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1259 cfg->frame_reg = AMD64_RSP;
1262 /* Locals are allocated backwards from %fp */
1263 cfg->frame_reg = AMD64_RBP;
1267 if (cfg->method->save_lmf) {
1268 /* Reserve stack space for saving LMF */
1269 /* mono_arch_find_jit_info () expects to find the LMF at a fixed offset */
1270 g_assert (offset == 0);
1271 if (cfg->arch.omit_fp) {
1272 cfg->arch.lmf_offset = offset;
1273 offset += sizeof (MonoLMF);
1276 offset += sizeof (MonoLMF);
1277 cfg->arch.lmf_offset = -offset;
1280 if (cfg->arch.omit_fp)
1281 cfg->arch.reg_save_area_offset = offset;
1282 /* Reserve space for caller saved registers */
1283 for (i = 0; i < AMD64_NREG; ++i)
1284 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1285 offset += sizeof (gpointer);
1289 if (sig->ret->type != MONO_TYPE_VOID) {
1290 switch (cinfo->ret.storage) {
1292 case ArgInFloatSSEReg:
1293 case ArgInDoubleSSEReg:
1294 if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1295 if (cfg->globalra) {
1296 cfg->vret_addr->opcode = OP_REGVAR;
1297 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1299 /* The register is volatile */
1300 cfg->vret_addr->opcode = OP_REGOFFSET;
1301 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1302 if (cfg->arch.omit_fp) {
1303 cfg->vret_addr->inst_offset = offset;
1307 cfg->vret_addr->inst_offset = -offset;
1309 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1310 printf ("vret_addr =");
1311 mono_print_ins (cfg->vret_addr);
1316 cfg->ret->opcode = OP_REGVAR;
1317 cfg->ret->inst_c0 = cinfo->ret.reg;
1320 case ArgValuetypeInReg:
1321 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1322 cfg->ret->opcode = OP_REGOFFSET;
1323 cfg->ret->inst_basereg = cfg->frame_reg;
1324 if (cfg->arch.omit_fp) {
1325 cfg->ret->inst_offset = offset;
1329 cfg->ret->inst_offset = - offset;
1333 g_assert_not_reached ();
1336 cfg->ret->dreg = cfg->ret->inst_c0;
1339 /* Allocate locals */
1340 if (!cfg->globalra) {
1341 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1342 if (locals_stack_align) {
1343 offset += (locals_stack_align - 1);
1344 offset &= ~(locals_stack_align - 1);
1346 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1347 if (offsets [i] != -1) {
1348 MonoInst *ins = cfg->varinfo [i];
1349 ins->opcode = OP_REGOFFSET;
1350 ins->inst_basereg = cfg->frame_reg;
1351 if (cfg->arch.omit_fp)
1352 ins->inst_offset = (offset + offsets [i]);
1354 ins->inst_offset = - (offset + offsets [i]);
1355 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1358 offset += locals_stack_size;
1361 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1362 g_assert (!cfg->arch.omit_fp);
1363 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1364 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1367 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1368 ins = cfg->args [i];
1369 if (ins->opcode != OP_REGVAR) {
1370 ArgInfo *ainfo = &cinfo->args [i];
1371 gboolean inreg = TRUE;
1374 if (sig->hasthis && (i == 0))
1375 arg_type = &mono_defaults.object_class->byval_arg;
1377 arg_type = sig->params [i - sig->hasthis];
1379 if (cfg->globalra) {
1380 /* The new allocator needs info about the original locations of the arguments */
1381 switch (ainfo->storage) {
1383 case ArgInFloatSSEReg:
1384 case ArgInDoubleSSEReg:
1385 ins->opcode = OP_REGVAR;
1386 ins->inst_c0 = ainfo->reg;
1389 g_assert (!cfg->arch.omit_fp);
1390 ins->opcode = OP_REGOFFSET;
1391 ins->inst_basereg = cfg->frame_reg;
1392 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1394 case ArgValuetypeInReg:
1395 ins->opcode = OP_REGOFFSET;
1396 ins->inst_basereg = cfg->frame_reg;
1397 /* These arguments are saved to the stack in the prolog */
1398 offset = ALIGN_TO (offset, sizeof (gpointer));
1399 if (cfg->arch.omit_fp) {
1400 ins->inst_offset = offset;
1401 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1403 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1404 ins->inst_offset = - offset;
1408 g_assert_not_reached ();
1414 /* FIXME: Allocate volatile arguments to registers */
1415 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1419 * Under AMD64, all registers used to pass arguments to functions
1420 * are volatile across calls.
1421 * FIXME: Optimize this.
1423 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1426 ins->opcode = OP_REGOFFSET;
1428 switch (ainfo->storage) {
1430 case ArgInFloatSSEReg:
1431 case ArgInDoubleSSEReg:
1433 ins->opcode = OP_REGVAR;
1434 ins->dreg = ainfo->reg;
1438 g_assert (!cfg->arch.omit_fp);
1439 ins->opcode = OP_REGOFFSET;
1440 ins->inst_basereg = cfg->frame_reg;
1441 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1443 case ArgValuetypeInReg:
1445 case ArgValuetypeAddrInIReg: {
1447 g_assert (!cfg->arch.omit_fp);
1449 MONO_INST_NEW (cfg, indir, 0);
1450 indir->opcode = OP_REGOFFSET;
1451 if (ainfo->pair_storage [0] == ArgInIReg) {
1452 indir->inst_basereg = cfg->frame_reg;
1453 offset = ALIGN_TO (offset, sizeof (gpointer));
1454 offset += (sizeof (gpointer));
1455 indir->inst_offset = - offset;
1458 indir->inst_basereg = cfg->frame_reg;
1459 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1462 ins->opcode = OP_VTARG_ADDR;
1463 ins->inst_left = indir;
1471 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1472 ins->opcode = OP_REGOFFSET;
1473 ins->inst_basereg = cfg->frame_reg;
1474 /* These arguments are saved to the stack in the prolog */
1475 offset = ALIGN_TO (offset, sizeof (gpointer));
1476 if (cfg->arch.omit_fp) {
1477 ins->inst_offset = offset;
1478 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1480 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1481 ins->inst_offset = - offset;
1487 cfg->stack_offset = offset;
1491 mono_arch_create_vars (MonoCompile *cfg)
1493 MonoMethodSignature *sig;
1496 sig = mono_method_signature (cfg->method);
1498 if (!cfg->arch.cinfo)
1499 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1500 cinfo = cfg->arch.cinfo;
1502 if (cinfo->ret.storage == ArgValuetypeInReg)
1503 cfg->ret_var_is_local = TRUE;
1505 if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1506 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1507 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1508 printf ("vret_addr = ");
1509 mono_print_ins (cfg->vret_addr);
1515 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, MonoInst *arg, ArgStorage storage, int reg, MonoInst *tree)
1519 arg->opcode = OP_OUTARG_REG;
1520 arg->inst_left = tree;
1521 arg->inst_call = call;
1522 arg->backend.reg3 = reg;
1524 case ArgInFloatSSEReg:
1525 arg->opcode = OP_AMD64_OUTARG_XMMREG_R4;
1526 arg->inst_left = tree;
1527 arg->inst_call = call;
1528 arg->backend.reg3 = reg;
1530 case ArgInDoubleSSEReg:
1531 arg->opcode = OP_AMD64_OUTARG_XMMREG_R8;
1532 arg->inst_left = tree;
1533 arg->inst_call = call;
1534 arg->backend.reg3 = reg;
1537 g_assert_not_reached ();
1542 add_outarg_reg2 (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1548 MONO_INST_NEW (cfg, ins, OP_MOVE);
1549 ins->dreg = mono_alloc_ireg (cfg);
1550 ins->sreg1 = tree->dreg;
1551 MONO_ADD_INS (cfg->cbb, ins);
1552 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1554 case ArgInFloatSSEReg:
1555 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1556 ins->dreg = mono_alloc_freg (cfg);
1557 ins->sreg1 = tree->dreg;
1558 MONO_ADD_INS (cfg->cbb, ins);
1560 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1562 case ArgInDoubleSSEReg:
1563 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1564 ins->dreg = mono_alloc_freg (cfg);
1565 ins->sreg1 = tree->dreg;
1566 MONO_ADD_INS (cfg->cbb, ins);
1568 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1572 g_assert_not_reached ();
1577 arg_storage_to_ldind (ArgStorage storage)
1582 case ArgInDoubleSSEReg:
1583 return CEE_LDIND_R8;
1584 case ArgInFloatSSEReg:
1585 return CEE_LDIND_R4;
1587 g_assert_not_reached ();
1594 arg_storage_to_load_membase (ArgStorage storage)
1598 return OP_LOAD_MEMBASE;
1599 case ArgInDoubleSSEReg:
1600 return OP_LOADR8_MEMBASE;
1601 case ArgInFloatSSEReg:
1602 return OP_LOADR4_MEMBASE;
1604 g_assert_not_reached ();
1611 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1614 MonoMethodSignature *tmp_sig;
1617 /* FIXME: Add support for signature tokens to AOT */
1618 cfg->disable_aot = TRUE;
1620 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1623 * mono_ArgIterator_Setup assumes the signature cookie is
1624 * passed first and all the arguments which were before it are
1625 * passed on the stack after the signature. So compensate by
1626 * passing a different signature.
1628 tmp_sig = mono_metadata_signature_dup (call->signature);
1629 tmp_sig->param_count -= call->signature->sentinelpos;
1630 tmp_sig->sentinelpos = 0;
1631 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1633 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1634 sig_arg->inst_p0 = tmp_sig;
1636 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1637 arg->inst_left = sig_arg;
1638 arg->type = STACK_PTR;
1640 /* prepend, so they get reversed */
1641 arg->next = call->out_args;
1642 call->out_args = arg;
1646 * take the arguments and generate the arch-specific
1647 * instructions to properly call the function in call.
1648 * This includes pushing, moving arguments to the right register
1652 mono_arch_call_opcode (MonoCompile *cfg, MonoBasicBlock* bb, MonoCallInst *call, int is_virtual) {
1654 MonoMethodSignature *sig;
1655 int i, n, stack_size;
1661 sig = call->signature;
1662 n = sig->param_count + sig->hasthis;
1664 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1666 if (cfg->method->save_lmf) {
1667 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1668 arg->next = call->out_args;
1669 call->out_args = arg;
1672 for (i = 0; i < n; ++i) {
1673 ainfo = cinfo->args + i;
1675 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1676 /* Emit the signature cookie just before the implicit arguments */
1677 emit_sig_cookie (cfg, call, cinfo);
1680 if (is_virtual && i == 0) {
1681 /* the argument will be attached to the call instruction */
1682 in = call->args [i];
1684 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1685 in = call->args [i];
1686 arg->cil_code = in->cil_code;
1687 arg->inst_left = in;
1688 arg->type = in->type;
1689 /* prepend, so they get reversed */
1690 arg->next = call->out_args;
1691 call->out_args = arg;
1693 if (!cinfo->stack_usage)
1694 /* Keep the assignments to the arg registers in order if possible */
1695 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1697 MONO_INST_LIST_ADD (&arg->node, &call->out_args);
1700 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1704 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1705 size = sizeof (MonoTypedRef);
1706 align = sizeof (gpointer);
1710 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1713 * Other backends use mini_type_stack_size (), but that
1714 * aligns the size to 8, which is larger than the size of
1715 * the source, leading to reads of invalid memory if the
1716 * source is at the end of address space.
1718 size = mono_class_value_size (in->klass, &align);
1720 if (ainfo->storage == ArgValuetypeInReg) {
1721 if (ainfo->pair_storage [1] == ArgNone) {
1726 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1727 load->inst_left = in;
1729 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1732 /* Trees can't be shared so make a copy */
1733 MonoInst *vtaddr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1734 MonoInst *load, *load2, *offset_ins;
1737 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1738 load->ssa_op = MONO_SSA_LOAD;
1739 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1741 NEW_ICONST (cfg, offset_ins, 0);
1742 MONO_INST_NEW (cfg, load2, CEE_ADD);
1743 load2->inst_left = load;
1744 load2->inst_right = offset_ins;
1746 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [0]));
1747 load->inst_left = load2;
1749 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [0], ainfo->pair_regs [0], load);
1752 MONO_INST_NEW (cfg, load, CEE_LDIND_I);
1753 load->ssa_op = MONO_SSA_LOAD;
1754 load->inst_i0 = (cfg)->varinfo [vtaddr->inst_c0];
1756 NEW_ICONST (cfg, offset_ins, 8);
1757 MONO_INST_NEW (cfg, load2, CEE_ADD);
1758 load2->inst_left = load;
1759 load2->inst_right = offset_ins;
1761 MONO_INST_NEW (cfg, load, arg_storage_to_ldind (ainfo->pair_storage [1]));
1762 load->inst_left = load2;
1764 MONO_INST_NEW (cfg, arg, OP_OUTARG);
1765 arg->cil_code = in->cil_code;
1766 arg->type = in->type;
1767 /* prepend, so they get reversed */
1768 arg->next = call->out_args;
1769 call->out_args = arg;
1771 add_outarg_reg (cfg, call, arg, ainfo->pair_storage [1], ainfo->pair_regs [1], load);
1773 /* Prepend a copy inst */
1774 MONO_INST_NEW (cfg, arg, CEE_STIND_I);
1775 arg->cil_code = in->cil_code;
1776 arg->ssa_op = MONO_SSA_STORE;
1777 arg->inst_left = vtaddr;
1778 arg->inst_right = in;
1779 arg->type = in->type;
1781 /* prepend, so they get reversed */
1782 arg->next = call->out_args;
1783 call->out_args = arg;
1786 else if (ainfo->storage == ArgValuetypeAddrInIReg){
1788 /* Add a temp variable to the method*/
1790 MonoInst *vtaddr = mono_compile_create_var (cfg, &in->klass->byval_arg, OP_LOCAL);
1792 MONO_INST_NEW (cfg, load, OP_LDADDR);
1793 load->ssa_op = MONO_SSA_LOAD;
1794 load->inst_left = vtaddr;
1796 if (ainfo->pair_storage [0] == ArgInIReg) {
1797 /* Inserted after the copy. Load the address of the temp to the argument regster.*/
1798 arg->opcode = OP_OUTARG_REG;
1799 arg->inst_left = load;
1800 arg->inst_call = call;
1801 arg->backend.reg3 = ainfo->pair_regs [0];
1804 /* Inserted after the copy. Load the address of the temp on the stack.*/
1805 arg->opcode = OP_OUTARG_VT;
1806 arg->inst_left = load;
1807 arg->type = STACK_PTR;
1808 arg->klass = mono_defaults.int_class;
1809 arg->backend.is_pinvoke = sig->pinvoke;
1810 arg->inst_imm = size;
1813 /*Copy the argument to the temp variable.*/
1814 MONO_INST_NEW (cfg, load, OP_MEMCPY);
1815 load->backend.memcpy_args = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoMemcpyArgs));
1816 load->backend.memcpy_args->size = size;
1817 load->backend.memcpy_args->align = align;
1818 load->inst_left = (cfg)->varinfo [vtaddr->inst_c0];
1819 load->inst_right = in->inst_i0;
1822 g_assert_not_reached ();
1823 //MONO_INST_LIST_ADD (&load->node, &call->out_args);
1826 arg->opcode = OP_OUTARG_VT;
1827 arg->klass = in->klass;
1828 arg->backend.is_pinvoke = sig->pinvoke;
1829 arg->inst_imm = size;
1833 switch (ainfo->storage) {
1835 add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1837 case ArgInFloatSSEReg:
1838 case ArgInDoubleSSEReg:
1839 add_outarg_reg (cfg, call, arg, ainfo->storage, ainfo->reg, in);
1842 arg->opcode = OP_OUTARG;
1843 if (!sig->params [i - sig->hasthis]->byref) {
1844 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4)
1845 arg->opcode = OP_OUTARG_R4;
1847 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8)
1848 arg->opcode = OP_OUTARG_R8;
1852 g_assert_not_reached ();
1858 /* Handle the case where there are no implicit arguments */
1859 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
1860 emit_sig_cookie (cfg, call, cinfo);
1863 if (cinfo->ret.storage == ArgValuetypeInReg) {
1864 /* This is needed by mono_arch_emit_this_vret_args () */
1865 if (!cfg->arch.vret_addr_loc) {
1866 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1867 /* Prevent it from being register allocated or optimized away */
1868 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
1872 if (cinfo->need_stack_align) {
1873 MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1875 /* prepend, so they get reversed */
1876 arg->next = call->out_args;
1877 call->out_args = arg;
1880 #ifdef PLATFORM_WIN32
1881 /* Always reserve 32 bytes of stack space on Win64 */
1882 /*MONO_INST_NEW (cfg, arg, OP_AMD64_OUTARG_ALIGN_STACK);
1884 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);*/
1889 if (cfg->method->save_lmf) {
1890 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
1891 MONO_INST_LIST_ADD_TAIL (&arg->node, &call->out_args);
1895 call->stack_usage = cinfo->stack_usage;
1896 cfg->param_area = MAX (cfg->param_area, call->stack_usage);
1897 cfg->flags |= MONO_CFG_HAS_CALLS;
1903 emit_sig_cookie2 (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1906 MonoMethodSignature *tmp_sig;
1909 if (call->tail_call)
1912 /* FIXME: Add support for signature tokens to AOT */
1913 cfg->disable_aot = TRUE;
1915 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1918 * mono_ArgIterator_Setup assumes the signature cookie is
1919 * passed first and all the arguments which were before it are
1920 * passed on the stack after the signature. So compensate by
1921 * passing a different signature.
1923 tmp_sig = mono_metadata_signature_dup (call->signature);
1924 tmp_sig->param_count -= call->signature->sentinelpos;
1925 tmp_sig->sentinelpos = 0;
1926 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1928 MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1929 sig_arg->dreg = mono_alloc_ireg (cfg);
1930 sig_arg->inst_p0 = tmp_sig;
1931 MONO_ADD_INS (cfg->cbb, sig_arg);
1933 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1934 arg->sreg1 = sig_arg->dreg;
1935 MONO_ADD_INS (cfg->cbb, arg);
1939 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1942 MonoMethodSignature *sig;
1943 int i, n, stack_size;
1949 sig = call->signature;
1950 n = sig->param_count + sig->hasthis;
1952 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1954 if (cinfo->need_stack_align) {
1955 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1959 * Emit all parameters passed in registers in non-reverse order for better readability
1960 * and to help the optimization in emit_prolog ().
1962 for (i = 0; i < n; ++i) {
1963 ainfo = cinfo->args + i;
1965 in = call->args [i];
1967 if (ainfo->storage == ArgInIReg)
1968 add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1971 for (i = n - 1; i >= 0; --i) {
1972 ainfo = cinfo->args + i;
1974 in = call->args [i];
1976 switch (ainfo->storage) {
1980 case ArgInFloatSSEReg:
1981 case ArgInDoubleSSEReg:
1982 add_outarg_reg2 (cfg, call, ainfo->storage, ainfo->reg, in);
1985 case ArgValuetypeInReg:
1986 case ArgValuetypeAddrInIReg:
1987 if (ainfo->storage == ArgOnStack && call->tail_call)
1989 if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1993 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1994 size = sizeof (MonoTypedRef);
1995 align = sizeof (gpointer);
1999 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
2002 * Other backends use mono_type_stack_size (), but that
2003 * aligns the size to 8, which is larger than the size of
2004 * the source, leading to reads of invalid memory if the
2005 * source is at the end of address space.
2007 size = mono_class_value_size (in->klass, &align);
2010 g_assert (in->klass);
2013 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2014 arg->sreg1 = in->dreg;
2015 arg->klass = in->klass;
2016 arg->backend.size = size;
2017 arg->inst_p0 = call;
2018 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2019 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2021 MONO_ADD_INS (cfg->cbb, arg);
2024 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2025 arg->sreg1 = in->dreg;
2026 if (!sig->params [i - sig->hasthis]->byref) {
2027 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2028 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2029 arg->opcode = OP_STORER4_MEMBASE_REG;
2030 arg->inst_destbasereg = X86_ESP;
2031 arg->inst_offset = 0;
2032 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2033 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2034 arg->opcode = OP_STORER8_MEMBASE_REG;
2035 arg->inst_destbasereg = X86_ESP;
2036 arg->inst_offset = 0;
2039 MONO_ADD_INS (cfg->cbb, arg);
2043 g_assert_not_reached ();
2046 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
2047 /* Emit the signature cookie just before the implicit arguments */
2048 emit_sig_cookie2 (cfg, call, cinfo);
2052 /* Handle the case where there are no implicit arguments */
2053 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos)) {
2054 emit_sig_cookie2 (cfg, call, cinfo);
2057 if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2060 if (cinfo->ret.storage == ArgValuetypeInReg) {
2061 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2063 * Tell the JIT to use a more efficient calling convention: call using
2064 * OP_CALL, compute the result location after the call, and save the
2067 call->vret_in_reg = TRUE;
2069 * Nullify the instruction computing the vret addr to enable
2070 * future optimizations.
2073 NULLIFY_INS (call->vret_var);
2075 if (call->tail_call)
2078 * The valuetype is in RAX:RDX after the call, need to be copied to
2079 * the stack. Push the address here, so the call instruction can
2082 if (!cfg->arch.vret_addr_loc) {
2083 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2084 /* Prevent it from being register allocated or optimized away */
2085 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2088 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2092 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2093 vtarg->sreg1 = call->vret_var->dreg;
2094 vtarg->dreg = mono_alloc_preg (cfg);
2095 MONO_ADD_INS (cfg->cbb, vtarg);
2097 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2101 #ifdef PLATFORM_WIN32
2102 if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2103 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2107 if (cfg->method->save_lmf) {
2108 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2109 MONO_ADD_INS (cfg->cbb, arg);
2112 call->stack_usage = cinfo->stack_usage;
2116 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2119 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2120 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2121 int size = ins->backend.size;
2123 if (ainfo->storage == ArgValuetypeInReg) {
2127 for (part = 0; part < 2; ++part) {
2128 if (ainfo->pair_storage [part] == ArgNone)
2131 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2132 load->inst_basereg = src->dreg;
2133 load->inst_offset = part * sizeof (gpointer);
2135 switch (ainfo->pair_storage [part]) {
2137 load->dreg = mono_alloc_ireg (cfg);
2139 case ArgInDoubleSSEReg:
2140 case ArgInFloatSSEReg:
2141 load->dreg = mono_alloc_freg (cfg);
2144 g_assert_not_reached ();
2146 MONO_ADD_INS (cfg->cbb, load);
2148 add_outarg_reg2 (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2150 } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2151 MonoInst *vtaddr, *load;
2152 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2154 MONO_INST_NEW (cfg, load, OP_LDADDR);
2155 load->inst_p0 = vtaddr;
2156 vtaddr->flags |= MONO_INST_INDIRECT;
2157 load->type = STACK_MP;
2158 load->klass = vtaddr->klass;
2159 load->dreg = mono_alloc_ireg (cfg);
2160 MONO_ADD_INS (cfg->cbb, load);
2161 mini_emit_memcpy2 (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2163 if (ainfo->pair_storage [0] == ArgInIReg) {
2164 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2165 arg->dreg = ainfo->pair_regs [0];
2166 arg->sreg1 = load->dreg;
2168 MONO_ADD_INS (cfg->cbb, arg);
2170 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2171 arg->sreg1 = load->dreg;
2172 MONO_ADD_INS (cfg->cbb, arg);
2176 /* Can't use this for < 8 since it does an 8 byte memory load */
2177 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2178 arg->inst_basereg = src->dreg;
2179 arg->inst_offset = 0;
2180 MONO_ADD_INS (cfg->cbb, arg);
2181 } else if (size <= 40) {
2182 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2183 mini_emit_memcpy2 (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2185 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2186 arg->inst_basereg = src->dreg;
2187 arg->inst_offset = 0;
2188 arg->inst_imm = size;
2189 MONO_ADD_INS (cfg->cbb, arg);
2195 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2197 MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2200 if (ret->type == MONO_TYPE_R4) {
2201 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2203 } else if (ret->type == MONO_TYPE_R8) {
2204 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2209 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2212 #define EMIT_COND_BRANCH(ins,cond,sign) \
2213 if (ins->flags & MONO_INST_BRLABEL) { \
2214 if (ins->inst_i0->inst_c0) { \
2215 x86_branch (code, cond, cfg->native_code + ins->inst_i0->inst_c0, sign); \
2217 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_LABEL, ins->inst_i0); \
2218 if ((cfg->opt & MONO_OPT_BRANCH) && \
2219 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos)) \
2220 x86_branch8 (code, cond, 0, sign); \
2222 x86_branch32 (code, cond, 0, sign); \
2225 if (ins->inst_true_bb->native_offset) { \
2226 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2228 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2229 if ((cfg->opt & MONO_OPT_BRANCH) && \
2230 x86_is_imm8 (ins->inst_true_bb->max_offset - cpos)) \
2231 x86_branch8 (code, cond, 0, sign); \
2233 x86_branch32 (code, cond, 0, sign); \
2237 /* emit an exception if condition is fail */
2238 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
2240 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2241 if (tins == NULL) { \
2242 mono_add_patch_info (cfg, code - cfg->native_code, \
2243 MONO_PATCH_INFO_EXC, exc_name); \
2244 x86_branch32 (code, cond, 0, signed); \
2246 EMIT_COND_BRANCH (tins, cond, signed); \
2250 #define EMIT_FPCOMPARE(code) do { \
2251 amd64_fcompp (code); \
2252 amd64_fnstsw (code); \
2255 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2256 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2257 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2258 amd64_ ##op (code); \
2259 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2260 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2264 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2266 gboolean no_patch = FALSE;
2269 * FIXME: Add support for thunks
2272 gboolean near_call = FALSE;
2275 * Indirect calls are expensive so try to make a near call if possible.
2276 * The caller memory is allocated by the code manager so it is
2277 * guaranteed to be at a 32 bit offset.
2280 if (patch_type != MONO_PATCH_INFO_ABS) {
2281 /* The target is in memory allocated using the code manager */
2284 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2285 if (((MonoMethod*)data)->klass->image->aot_module)
2286 /* The callee might be an AOT method */
2288 if (((MonoMethod*)data)->dynamic)
2289 /* The target is in malloc-ed memory */
2293 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2295 * The call might go directly to a native function without
2298 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2300 gconstpointer target = mono_icall_get_wrapper (mi);
2301 if ((((guint64)target) >> 32) != 0)
2307 if (!cfg->new_ir && mono_find_class_init_trampoline_by_addr (data))
2309 else if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2311 * This is not really an optimization, but required because the
2312 * generic class init trampolines use R11 to pass the vtable.
2316 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2318 if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2319 strstr (cfg->method->name, info->name)) {
2320 /* A call to the wrapped function */
2321 if ((((guint64)data) >> 32) == 0)
2325 else if (info->func == info->wrapper) {
2327 if ((((guint64)info->func) >> 32) == 0)
2331 /* See the comment in mono_codegen () */
2332 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2336 else if ((((guint64)data) >> 32) == 0) {
2343 if (cfg->method->dynamic)
2344 /* These methods are allocated using malloc */
2347 if (cfg->compile_aot)
2350 #ifdef MONO_ARCH_NOMAP32BIT
2356 * Align the call displacement to an address divisible by 4 so it does
2357 * not span cache lines. This is required for code patching to work on SMP
2360 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2361 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2362 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2363 amd64_call_code (code, 0);
2366 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2367 amd64_set_reg_template (code, GP_SCRATCH_REG);
2368 amd64_call_reg (code, GP_SCRATCH_REG);
2375 static inline guint8*
2376 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2378 #ifdef PLATFORM_WIN32
2379 if (win64_adjust_stack)
2380 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2382 code = emit_call_body (cfg, code, patch_type, data);
2383 #ifdef PLATFORM_WIN32
2384 if (win64_adjust_stack)
2385 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2392 store_membase_imm_to_store_membase_reg (int opcode)
2395 case OP_STORE_MEMBASE_IMM:
2396 return OP_STORE_MEMBASE_REG;
2397 case OP_STOREI4_MEMBASE_IMM:
2398 return OP_STOREI4_MEMBASE_REG;
2399 case OP_STOREI8_MEMBASE_IMM:
2400 return OP_STOREI8_MEMBASE_REG;
2406 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2409 * mono_arch_peephole_pass_1:
2411 * Perform peephole opts which should/can be performed before local regalloc
2414 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2418 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2419 MonoInst *last_ins = ins->prev;
2421 switch (ins->opcode) {
2425 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2427 * X86_LEA is like ADD, but doesn't have the
2428 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2429 * its operand to 64 bit.
2431 ins->opcode = OP_X86_LEA_MEMBASE;
2432 ins->inst_basereg = ins->sreg1;
2437 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2441 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2442 * the latter has length 2-3 instead of 6 (reverse constant
2443 * propagation). These instruction sequences are very common
2444 * in the initlocals bblock.
2446 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2447 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2448 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2449 ins2->sreg1 = ins->dreg;
2450 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2452 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2461 case OP_COMPARE_IMM:
2462 case OP_LCOMPARE_IMM:
2463 /* OP_COMPARE_IMM (reg, 0)
2465 * OP_AMD64_TEST_NULL (reg)
2468 ins->opcode = OP_AMD64_TEST_NULL;
2470 case OP_ICOMPARE_IMM:
2472 ins->opcode = OP_X86_TEST_NULL;
2474 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2476 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2477 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2479 * OP_STORE_MEMBASE_REG reg, offset(basereg)
2480 * OP_COMPARE_IMM reg, imm
2482 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2484 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2485 ins->inst_basereg == last_ins->inst_destbasereg &&
2486 ins->inst_offset == last_ins->inst_offset) {
2487 ins->opcode = OP_ICOMPARE_IMM;
2488 ins->sreg1 = last_ins->sreg1;
2490 /* check if we can remove cmp reg,0 with test null */
2492 ins->opcode = OP_X86_TEST_NULL;
2498 mono_peephole_ins (bb, ins);
2503 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2507 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2508 switch (ins->opcode) {
2511 /* reg = 0 -> XOR (reg, reg) */
2512 /* XOR sets cflags on x86, so we cant do it always */
2513 if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2514 ins->opcode = OP_LXOR;
2515 ins->sreg1 = ins->dreg;
2516 ins->sreg2 = ins->dreg;
2524 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2525 * 0 result into 64 bits.
2527 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2528 ins->opcode = OP_IXOR;
2532 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2536 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2537 * the latter has length 2-3 instead of 6 (reverse constant
2538 * propagation). These instruction sequences are very common
2539 * in the initlocals bblock.
2541 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2542 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2543 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2544 ins2->sreg1 = ins->dreg;
2545 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2547 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2557 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2558 ins->opcode = OP_X86_INC_REG;
2561 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2562 ins->opcode = OP_X86_DEC_REG;
2566 mono_peephole_ins (bb, ins);
2570 #define NEW_INS(cfg,ins,dest,op) do { \
2571 MONO_INST_NEW ((cfg), (dest), (op)); \
2572 (dest)->cil_code = (ins)->cil_code; \
2573 mono_bblock_insert_before_ins (bb, ins, (dest)); \
2577 * mono_arch_lowering_pass:
2579 * Converts complex opcodes into simpler ones so that each IR instruction
2580 * corresponds to one machine instruction.
2583 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2585 MonoInst *ins, *n, *temp;
2587 if (bb->max_vreg > cfg->rs->next_vreg)
2588 cfg->rs->next_vreg = bb->max_vreg;
2591 * FIXME: Need to add more instructions, but the current machine
2592 * description can't model some parts of the composite instructions like
2595 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2596 switch (ins->opcode) {
2601 case OP_IDIV_UN_IMM:
2602 case OP_IREM_UN_IMM:
2603 mono_decompose_op_imm (cfg, bb, ins);
2605 case OP_COMPARE_IMM:
2606 case OP_LCOMPARE_IMM:
2607 if (!amd64_is_imm32 (ins->inst_imm)) {
2608 NEW_INS (cfg, ins, temp, OP_I8CONST);
2609 temp->inst_c0 = ins->inst_imm;
2611 temp->dreg = mono_alloc_ireg (cfg);
2613 temp->dreg = mono_regstate_next_int (cfg->rs);
2614 ins->opcode = OP_COMPARE;
2615 ins->sreg2 = temp->dreg;
2618 case OP_LOAD_MEMBASE:
2619 case OP_LOADI8_MEMBASE:
2620 if (!amd64_is_imm32 (ins->inst_offset)) {
2621 NEW_INS (cfg, ins, temp, OP_I8CONST);
2622 temp->inst_c0 = ins->inst_offset;
2624 temp->dreg = mono_alloc_ireg (cfg);
2626 temp->dreg = mono_regstate_next_int (cfg->rs);
2627 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2628 ins->inst_indexreg = temp->dreg;
2631 case OP_STORE_MEMBASE_IMM:
2632 case OP_STOREI8_MEMBASE_IMM:
2633 if (!amd64_is_imm32 (ins->inst_imm)) {
2634 NEW_INS (cfg, ins, temp, OP_I8CONST);
2635 temp->inst_c0 = ins->inst_imm;
2637 temp->dreg = mono_alloc_ireg (cfg);
2639 temp->dreg = mono_regstate_next_int (cfg->rs);
2640 ins->opcode = OP_STOREI8_MEMBASE_REG;
2641 ins->sreg1 = temp->dreg;
2649 bb->max_vreg = cfg->rs->next_vreg;
2653 branch_cc_table [] = {
2654 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2655 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2656 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2659 /* Maps CMP_... constants to X86_CC_... constants */
2662 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2663 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2667 cc_signed_table [] = {
2668 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2669 FALSE, FALSE, FALSE, FALSE
2672 /*#include "cprop.c"*/
2674 static unsigned char*
2675 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2677 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2680 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2682 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2686 static unsigned char*
2687 mono_emit_stack_alloc (guchar *code, MonoInst* tree)
2689 int sreg = tree->sreg1;
2690 int need_touch = FALSE;
2692 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
2693 if (!tree->flags & MONO_INST_INIT)
2702 * If requested stack size is larger than one page,
2703 * perform stack-touch operation
2706 * Generate stack probe code.
2707 * Under Windows, it is necessary to allocate one page at a time,
2708 * "touching" stack after each successful sub-allocation. This is
2709 * because of the way stack growth is implemented - there is a
2710 * guard page before the lowest stack page that is currently commited.
2711 * Stack normally grows sequentially so OS traps access to the
2712 * guard page and commits more pages when needed.
2714 amd64_test_reg_imm (code, sreg, ~0xFFF);
2715 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2717 br[2] = code; /* loop */
2718 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
2719 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
2720 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
2721 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
2722 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
2723 amd64_patch (br[3], br[2]);
2724 amd64_test_reg_reg (code, sreg, sreg);
2725 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
2726 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2728 br[1] = code; x86_jump8 (code, 0);
2730 amd64_patch (br[0], code);
2731 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
2732 amd64_patch (br[1], code);
2733 amd64_patch (br[4], code);
2736 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
2738 if (tree->flags & MONO_INST_INIT) {
2740 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
2741 amd64_push_reg (code, AMD64_RAX);
2744 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
2745 amd64_push_reg (code, AMD64_RCX);
2748 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
2749 amd64_push_reg (code, AMD64_RDI);
2753 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
2754 if (sreg != AMD64_RCX)
2755 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
2756 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
2758 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
2760 amd64_prefix (code, X86_REP_PREFIX);
2763 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
2764 amd64_pop_reg (code, AMD64_RDI);
2765 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
2766 amd64_pop_reg (code, AMD64_RCX);
2767 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
2768 amd64_pop_reg (code, AMD64_RAX);
2774 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
2779 /* Move return value to the target register */
2780 /* FIXME: do this in the local reg allocator */
2781 switch (ins->opcode) {
2784 case OP_CALL_MEMBASE:
2787 case OP_LCALL_MEMBASE:
2788 g_assert (ins->dreg == AMD64_RAX);
2792 case OP_FCALL_MEMBASE:
2793 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
2794 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
2797 if (ins->dreg != AMD64_XMM0)
2798 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
2803 case OP_VCALL_MEMBASE:
2806 case OP_VCALL2_MEMBASE:
2807 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
2808 if (cinfo->ret.storage == ArgValuetypeInReg) {
2809 MonoInst *loc = cfg->arch.vret_addr_loc;
2811 /* Load the destination address */
2812 g_assert (loc->opcode == OP_REGOFFSET);
2813 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
2815 for (quad = 0; quad < 2; quad ++) {
2816 switch (cinfo->ret.pair_storage [quad]) {
2818 amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
2820 case ArgInFloatSSEReg:
2821 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2823 case ArgInDoubleSSEReg:
2824 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
2841 * @code: buffer to store code to
2842 * @dreg: hard register where to place the result
2843 * @tls_offset: offset info
2845 * emit_tls_get emits in @code the native code that puts in the dreg register
2846 * the item in the thread local storage identified by tls_offset.
2848 * Returns: a pointer to the end of the stored code
2851 emit_tls_get (guint8* code, int dreg, int tls_offset)
2853 #ifdef PLATFORM_WIN32
2854 g_assert (tls_offset < 64);
2855 x86_prefix (code, X86_GS_PREFIX);
2856 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
2858 if (optimize_for_xen) {
2859 x86_prefix (code, X86_FS_PREFIX);
2860 amd64_mov_reg_mem (code, dreg, 0, 8);
2861 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
2863 x86_prefix (code, X86_FS_PREFIX);
2864 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
2871 * emit_load_volatile_arguments:
2873 * Load volatile arguments from the stack to the original input registers.
2874 * Required before a tail call.
2877 emit_load_volatile_arguments (MonoCompile *cfg, guint8 *code)
2879 MonoMethod *method = cfg->method;
2880 MonoMethodSignature *sig;
2885 /* FIXME: Generate intermediate code instead */
2887 sig = mono_method_signature (method);
2889 cinfo = cfg->arch.cinfo;
2891 /* This is the opposite of the code in emit_prolog */
2892 if (sig->ret->type != MONO_TYPE_VOID) {
2893 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
2894 amd64_mov_reg_membase (code, cinfo->ret.reg, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, 8);
2897 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2898 ArgInfo *ainfo = cinfo->args + i;
2900 ins = cfg->args [i];
2902 if (sig->hasthis && (i == 0))
2903 arg_type = &mono_defaults.object_class->byval_arg;
2905 arg_type = sig->params [i - sig->hasthis];
2907 if (ins->opcode != OP_REGVAR) {
2908 switch (ainfo->storage) {
2913 amd64_mov_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset, size);
2916 case ArgInFloatSSEReg:
2917 amd64_movss_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2919 case ArgInDoubleSSEReg:
2920 amd64_movsd_reg_membase (code, ainfo->reg, ins->inst_basereg, ins->inst_offset);
2922 case ArgValuetypeInReg:
2923 for (quad = 0; quad < 2; quad ++) {
2924 switch (ainfo->pair_storage [quad]) {
2926 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
2928 case ArgInFloatSSEReg:
2929 case ArgInDoubleSSEReg:
2930 g_assert_not_reached ();
2935 g_assert_not_reached ();
2939 case ArgValuetypeAddrInIReg:
2940 if (ainfo->pair_storage [0] == ArgInIReg)
2941 amd64_mov_reg_membase (code, ainfo->pair_regs [0], ins->inst_left->inst_basereg, ins->inst_left->inst_offset, sizeof (gpointer));
2948 g_assert (ainfo->storage == ArgInIReg);
2950 amd64_mov_reg_reg (code, ainfo->reg, ins->dreg, 8);
2957 #define REAL_PRINT_REG(text,reg) \
2958 mono_assert (reg >= 0); \
2959 amd64_push_reg (code, AMD64_RAX); \
2960 amd64_push_reg (code, AMD64_RDX); \
2961 amd64_push_reg (code, AMD64_RCX); \
2962 amd64_push_reg (code, reg); \
2963 amd64_push_imm (code, reg); \
2964 amd64_push_imm (code, text " %d %p\n"); \
2965 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
2966 amd64_call_reg (code, AMD64_RAX); \
2967 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
2968 amd64_pop_reg (code, AMD64_RCX); \
2969 amd64_pop_reg (code, AMD64_RDX); \
2970 amd64_pop_reg (code, AMD64_RAX);
2972 /* benchmark and set based on cpu */
2973 #define LOOP_ALIGNMENT 8
2974 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
2979 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
2984 guint8 *code = cfg->native_code + cfg->code_len;
2985 MonoInst *last_ins = NULL;
2986 guint last_offset = 0;
2989 if (cfg->opt & MONO_OPT_LOOP) {
2990 int pad, align = LOOP_ALIGNMENT;
2991 /* set alignment depending on cpu */
2992 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
2994 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
2995 amd64_padding (code, pad);
2996 cfg->code_len += pad;
2997 bb->native_offset = cfg->code_len;
3001 if (cfg->verbose_level > 2)
3002 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3004 cpos = bb->max_offset;
3006 if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3007 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3008 g_assert (!cfg->compile_aot);
3011 cov->data [bb->dfn].cil_code = bb->cil_code;
3012 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3013 /* this is not thread save, but good enough */
3014 amd64_inc_membase (code, AMD64_R11, 0);
3017 offset = code - cfg->native_code;
3019 mono_debug_open_block (cfg, bb, offset);
3021 MONO_BB_FOR_EACH_INS (bb, ins) {
3022 offset = code - cfg->native_code;
3024 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3026 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3027 cfg->code_size *= 2;
3028 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3029 code = cfg->native_code + offset;
3030 mono_jit_stats.code_reallocs++;
3033 if (cfg->debug_info)
3034 mono_debug_record_line_number (cfg, ins, offset);
3036 switch (ins->opcode) {
3038 amd64_mul_reg (code, ins->sreg2, TRUE);
3041 amd64_mul_reg (code, ins->sreg2, FALSE);
3043 case OP_X86_SETEQ_MEMBASE:
3044 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3046 case OP_STOREI1_MEMBASE_IMM:
3047 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3049 case OP_STOREI2_MEMBASE_IMM:
3050 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3052 case OP_STOREI4_MEMBASE_IMM:
3053 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3055 case OP_STOREI1_MEMBASE_REG:
3056 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3058 case OP_STOREI2_MEMBASE_REG:
3059 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3061 case OP_STORE_MEMBASE_REG:
3062 case OP_STOREI8_MEMBASE_REG:
3063 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3065 case OP_STOREI4_MEMBASE_REG:
3066 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3068 case OP_STORE_MEMBASE_IMM:
3069 case OP_STOREI8_MEMBASE_IMM:
3070 g_assert (amd64_is_imm32 (ins->inst_imm));
3071 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3075 // FIXME: Decompose this earlier
3076 if (amd64_is_imm32 (ins->inst_imm))
3077 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3079 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3080 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3084 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3085 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3088 // FIXME: Decompose this earlier
3090 if (amd64_is_imm32 (ins->inst_imm))
3091 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3093 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3094 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3097 amd64_mov_reg_imm (code, ins->dreg, ins->inst_p0);
3098 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3102 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3103 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3106 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3107 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3109 case OP_LOAD_MEMBASE:
3110 case OP_LOADI8_MEMBASE:
3111 g_assert (amd64_is_imm32 (ins->inst_offset));
3112 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3114 case OP_LOADI4_MEMBASE:
3115 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3117 case OP_LOADU4_MEMBASE:
3118 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3120 case OP_LOADU1_MEMBASE:
3121 /* The cpu zero extends the result into 64 bits */
3122 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3124 case OP_LOADI1_MEMBASE:
3125 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3127 case OP_LOADU2_MEMBASE:
3128 /* The cpu zero extends the result into 64 bits */
3129 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3131 case OP_LOADI2_MEMBASE:
3132 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3134 case OP_AMD64_LOADI8_MEMINDEX:
3135 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3137 case OP_LCONV_TO_I1:
3138 case OP_ICONV_TO_I1:
3140 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3142 case OP_LCONV_TO_I2:
3143 case OP_ICONV_TO_I2:
3145 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3147 case OP_LCONV_TO_U1:
3148 case OP_ICONV_TO_U1:
3149 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3151 case OP_LCONV_TO_U2:
3152 case OP_ICONV_TO_U2:
3153 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3156 /* Clean out the upper word */
3157 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3160 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3164 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3166 case OP_COMPARE_IMM:
3167 case OP_LCOMPARE_IMM:
3168 g_assert (amd64_is_imm32 (ins->inst_imm));
3169 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3171 case OP_X86_COMPARE_REG_MEMBASE:
3172 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3174 case OP_X86_TEST_NULL:
3175 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3177 case OP_AMD64_TEST_NULL:
3178 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3181 case OP_X86_ADD_REG_MEMBASE:
3182 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3184 case OP_X86_SUB_REG_MEMBASE:
3185 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3187 case OP_X86_AND_REG_MEMBASE:
3188 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3190 case OP_X86_OR_REG_MEMBASE:
3191 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3193 case OP_X86_XOR_REG_MEMBASE:
3194 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3197 case OP_X86_ADD_MEMBASE_IMM:
3198 /* FIXME: Make a 64 version too */
3199 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3201 case OP_X86_SUB_MEMBASE_IMM:
3202 g_assert (amd64_is_imm32 (ins->inst_imm));
3203 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3205 case OP_X86_AND_MEMBASE_IMM:
3206 g_assert (amd64_is_imm32 (ins->inst_imm));
3207 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3209 case OP_X86_OR_MEMBASE_IMM:
3210 g_assert (amd64_is_imm32 (ins->inst_imm));
3211 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3213 case OP_X86_XOR_MEMBASE_IMM:
3214 g_assert (amd64_is_imm32 (ins->inst_imm));
3215 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3217 case OP_X86_ADD_MEMBASE_REG:
3218 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3220 case OP_X86_SUB_MEMBASE_REG:
3221 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3223 case OP_X86_AND_MEMBASE_REG:
3224 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3226 case OP_X86_OR_MEMBASE_REG:
3227 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3229 case OP_X86_XOR_MEMBASE_REG:
3230 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3232 case OP_X86_INC_MEMBASE:
3233 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3235 case OP_X86_INC_REG:
3236 amd64_inc_reg_size (code, ins->dreg, 4);
3238 case OP_X86_DEC_MEMBASE:
3239 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3241 case OP_X86_DEC_REG:
3242 amd64_dec_reg_size (code, ins->dreg, 4);
3244 case OP_X86_MUL_REG_MEMBASE:
3245 case OP_X86_MUL_MEMBASE_REG:
3246 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3248 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3249 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3251 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3252 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3254 case OP_AMD64_COMPARE_MEMBASE_REG:
3255 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3257 case OP_AMD64_COMPARE_MEMBASE_IMM:
3258 g_assert (amd64_is_imm32 (ins->inst_imm));
3259 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3261 case OP_X86_COMPARE_MEMBASE8_IMM:
3262 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3264 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3265 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3267 case OP_AMD64_COMPARE_REG_MEMBASE:
3268 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3271 case OP_AMD64_ADD_REG_MEMBASE:
3272 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3274 case OP_AMD64_SUB_REG_MEMBASE:
3275 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3277 case OP_AMD64_AND_REG_MEMBASE:
3278 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3280 case OP_AMD64_OR_REG_MEMBASE:
3281 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3283 case OP_AMD64_XOR_REG_MEMBASE:
3284 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3287 case OP_AMD64_ADD_MEMBASE_REG:
3288 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3290 case OP_AMD64_SUB_MEMBASE_REG:
3291 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3293 case OP_AMD64_AND_MEMBASE_REG:
3294 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3296 case OP_AMD64_OR_MEMBASE_REG:
3297 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3299 case OP_AMD64_XOR_MEMBASE_REG:
3300 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3303 case OP_AMD64_ADD_MEMBASE_IMM:
3304 g_assert (amd64_is_imm32 (ins->inst_imm));
3305 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3307 case OP_AMD64_SUB_MEMBASE_IMM:
3308 g_assert (amd64_is_imm32 (ins->inst_imm));
3309 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3311 case OP_AMD64_AND_MEMBASE_IMM:
3312 g_assert (amd64_is_imm32 (ins->inst_imm));
3313 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3315 case OP_AMD64_OR_MEMBASE_IMM:
3316 g_assert (amd64_is_imm32 (ins->inst_imm));
3317 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3319 case OP_AMD64_XOR_MEMBASE_IMM:
3320 g_assert (amd64_is_imm32 (ins->inst_imm));
3321 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3325 amd64_breakpoint (code);
3329 case OP_DUMMY_STORE:
3330 case OP_NOT_REACHED:
3335 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3338 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3342 g_assert (amd64_is_imm32 (ins->inst_imm));
3343 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3346 g_assert (amd64_is_imm32 (ins->inst_imm));
3347 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3351 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3354 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3358 g_assert (amd64_is_imm32 (ins->inst_imm));
3359 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3362 g_assert (amd64_is_imm32 (ins->inst_imm));
3363 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3366 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3370 g_assert (amd64_is_imm32 (ins->inst_imm));
3371 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3374 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3379 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3381 switch (ins->inst_imm) {
3385 if (ins->dreg != ins->sreg1)
3386 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3387 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3390 /* LEA r1, [r2 + r2*2] */
3391 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3394 /* LEA r1, [r2 + r2*4] */
3395 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3398 /* LEA r1, [r2 + r2*2] */
3400 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3401 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3404 /* LEA r1, [r2 + r2*8] */
3405 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3408 /* LEA r1, [r2 + r2*4] */
3410 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3411 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3414 /* LEA r1, [r2 + r2*2] */
3416 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3417 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3420 /* LEA r1, [r2 + r2*4] */
3421 /* LEA r1, [r1 + r1*4] */
3422 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3423 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3426 /* LEA r1, [r2 + r2*4] */
3428 /* LEA r1, [r1 + r1*4] */
3429 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3430 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3431 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3434 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3441 /* Regalloc magic makes the div/rem cases the same */
3442 if (ins->sreg2 == AMD64_RDX) {
3443 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3445 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3448 amd64_div_reg (code, ins->sreg2, TRUE);
3453 if (ins->sreg2 == AMD64_RDX) {
3454 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3455 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3456 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3458 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3459 amd64_div_reg (code, ins->sreg2, FALSE);
3464 if (ins->sreg2 == AMD64_RDX) {
3465 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3466 amd64_cdq_size (code, 4);
3467 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3469 amd64_cdq_size (code, 4);
3470 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3475 if (ins->sreg2 == AMD64_RDX) {
3476 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3477 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3478 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3480 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3481 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3485 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3486 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3489 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3493 g_assert (amd64_is_imm32 (ins->inst_imm));
3494 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3497 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3501 g_assert (amd64_is_imm32 (ins->inst_imm));
3502 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3505 g_assert (ins->sreg2 == AMD64_RCX);
3506 amd64_shift_reg (code, X86_SHL, ins->dreg);
3509 g_assert (ins->sreg2 == AMD64_RCX);
3510 amd64_shift_reg (code, X86_SAR, ins->dreg);
3513 g_assert (amd64_is_imm32 (ins->inst_imm));
3514 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3517 g_assert (amd64_is_imm32 (ins->inst_imm));
3518 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3521 g_assert (amd64_is_imm32 (ins->inst_imm));
3522 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3524 case OP_LSHR_UN_IMM:
3525 g_assert (amd64_is_imm32 (ins->inst_imm));
3526 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3529 g_assert (ins->sreg2 == AMD64_RCX);
3530 amd64_shift_reg (code, X86_SHR, ins->dreg);
3533 g_assert (amd64_is_imm32 (ins->inst_imm));
3534 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3537 g_assert (amd64_is_imm32 (ins->inst_imm));
3538 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3543 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3546 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3549 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3552 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3556 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3559 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3562 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3565 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3568 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3571 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3574 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3577 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3580 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3583 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3586 amd64_neg_reg_size (code, ins->sreg1, 4);
3589 amd64_not_reg_size (code, ins->sreg1, 4);
3592 g_assert (ins->sreg2 == AMD64_RCX);
3593 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3596 g_assert (ins->sreg2 == AMD64_RCX);
3597 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3600 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3602 case OP_ISHR_UN_IMM:
3603 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3606 g_assert (ins->sreg2 == AMD64_RCX);
3607 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3610 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3613 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3616 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3617 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3619 case OP_IMUL_OVF_UN:
3620 case OP_LMUL_OVF_UN: {
3621 /* the mul operation and the exception check should most likely be split */
3622 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3623 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3624 /*g_assert (ins->sreg2 == X86_EAX);
3625 g_assert (ins->dreg == X86_EAX);*/
3626 if (ins->sreg2 == X86_EAX) {
3627 non_eax_reg = ins->sreg1;
3628 } else if (ins->sreg1 == X86_EAX) {
3629 non_eax_reg = ins->sreg2;
3631 /* no need to save since we're going to store to it anyway */
3632 if (ins->dreg != X86_EAX) {
3634 amd64_push_reg (code, X86_EAX);
3636 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3637 non_eax_reg = ins->sreg2;
3639 if (ins->dreg == X86_EDX) {
3642 amd64_push_reg (code, X86_EAX);
3646 amd64_push_reg (code, X86_EDX);
3648 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3649 /* save before the check since pop and mov don't change the flags */
3650 if (ins->dreg != X86_EAX)
3651 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3653 amd64_pop_reg (code, X86_EDX);
3655 amd64_pop_reg (code, X86_EAX);
3656 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3660 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3662 case OP_ICOMPARE_IMM:
3663 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3685 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3693 case OP_CMOV_INE_UN:
3694 case OP_CMOV_IGE_UN:
3695 case OP_CMOV_IGT_UN:
3696 case OP_CMOV_ILE_UN:
3697 case OP_CMOV_ILT_UN:
3703 case OP_CMOV_LNE_UN:
3704 case OP_CMOV_LGE_UN:
3705 case OP_CMOV_LGT_UN:
3706 case OP_CMOV_LLE_UN:
3707 case OP_CMOV_LLT_UN:
3708 g_assert (ins->dreg == ins->sreg1);
3709 /* This needs to operate on 64 bit values */
3710 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
3714 amd64_not_reg (code, ins->sreg1);
3717 amd64_neg_reg (code, ins->sreg1);
3722 if ((((guint64)ins->inst_c0) >> 32) == 0)
3723 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
3725 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
3728 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3729 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
3732 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
3733 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
3736 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
3738 case OP_AMD64_SET_XMMREG_R4: {
3739 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
3742 case OP_AMD64_SET_XMMREG_R8: {
3743 if (ins->dreg != ins->sreg1)
3744 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
3750 * Note: this 'frame destruction' logic is useful for tail calls, too.
3751 * Keep in sync with the code in emit_epilog.
3755 /* FIXME: no tracing support... */
3756 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
3757 code = mono_arch_instrument_epilog (cfg, mono_profiler_method_leave, code, FALSE);
3759 g_assert (!cfg->method->save_lmf);
3761 if (ins->opcode == OP_JMP)
3762 code = emit_load_volatile_arguments (cfg, code);
3764 if (cfg->arch.omit_fp) {
3765 guint32 save_offset = 0;
3766 /* Pop callee-saved registers */
3767 for (i = 0; i < AMD64_NREG; ++i)
3768 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3769 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
3772 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
3775 for (i = 0; i < AMD64_NREG; ++i)
3776 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
3777 pos -= sizeof (gpointer);
3780 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
3782 /* Pop registers in reverse order */
3783 for (i = AMD64_NREG - 1; i > 0; --i)
3784 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
3785 amd64_pop_reg (code, i);
3791 offset = code - cfg->native_code;
3792 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
3793 if (cfg->compile_aot)
3794 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
3796 amd64_set_reg_template (code, AMD64_R11);
3797 amd64_jump_reg (code, AMD64_R11);
3801 /* ensure ins->sreg1 is not NULL */
3802 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
3805 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
3806 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
3815 call = (MonoCallInst*)ins;
3817 * The AMD64 ABI forces callers to know about varargs.
3819 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
3820 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3821 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3823 * Since the unmanaged calling convention doesn't contain a
3824 * 'vararg' entry, we have to treat every pinvoke call as a
3825 * potential vararg call.
3829 for (i = 0; i < AMD64_XMM_NREG; ++i)
3830 if (call->used_fregs & (1 << i))
3833 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3835 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3838 if (ins->flags & MONO_INST_HAS_METHOD)
3839 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
3841 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
3842 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3843 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3844 code = emit_move_return_value (cfg, ins, code);
3850 case OP_VOIDCALL_REG:
3852 call = (MonoCallInst*)ins;
3854 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3855 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
3856 ins->sreg1 = AMD64_R11;
3860 * The AMD64 ABI forces callers to know about varargs.
3862 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
3863 if (ins->sreg1 == AMD64_RAX) {
3864 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3865 ins->sreg1 = AMD64_R11;
3867 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3868 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
3870 * Since the unmanaged calling convention doesn't contain a
3871 * 'vararg' entry, we have to treat every pinvoke call as a
3872 * potential vararg call.
3876 for (i = 0; i < AMD64_XMM_NREG; ++i)
3877 if (call->used_fregs & (1 << i))
3879 if (ins->sreg1 == AMD64_RAX) {
3880 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
3881 ins->sreg1 = AMD64_R11;
3884 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3886 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
3889 amd64_call_reg (code, ins->sreg1);
3890 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3891 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3892 code = emit_move_return_value (cfg, ins, code);
3894 case OP_FCALL_MEMBASE:
3895 case OP_LCALL_MEMBASE:
3896 case OP_VCALL_MEMBASE:
3897 case OP_VCALL2_MEMBASE:
3898 case OP_VOIDCALL_MEMBASE:
3899 case OP_CALL_MEMBASE:
3900 call = (MonoCallInst*)ins;
3902 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
3904 * Can't use R11 because it is clobbered by the trampoline
3905 * code, and the reg value is needed by get_vcall_slot_addr.
3907 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3908 ins->sreg1 = AMD64_RAX;
3911 if (call->method && ins->inst_offset < 0) {
3915 * This is a possible IMT call so save the IMT method in the proper
3916 * register. We don't use the generic code in method-to-ir.c, because
3917 * we need to disassemble this in get_vcall_slot_addr (), so we have to
3918 * maintain control over the layout of the code.
3919 * Also put the base reg in %rax to simplify find_imt_method ().
3921 if (ins->sreg1 != AMD64_RAX) {
3922 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
3923 ins->sreg1 = AMD64_RAX;
3925 val = (gssize)(gpointer)call->method;
3927 // FIXME: Generics sharing
3929 if ((((guint64)val) >> 32) == 0)
3930 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 4);
3932 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_REG, val, 8);
3936 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
3937 if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention))
3938 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
3939 code = emit_move_return_value (cfg, ins, code);
3941 case OP_AMD64_SAVE_SP_TO_LMF:
3942 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3946 amd64_push_reg (code, ins->sreg1);
3948 case OP_X86_PUSH_IMM:
3949 g_assert (amd64_is_imm32 (ins->inst_imm));
3950 amd64_push_imm (code, ins->inst_imm);
3952 case OP_X86_PUSH_MEMBASE:
3953 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
3955 case OP_X86_PUSH_OBJ: {
3956 int size = ALIGN_TO (ins->inst_imm, 8);
3957 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
3958 amd64_push_reg (code, AMD64_RDI);
3959 amd64_push_reg (code, AMD64_RSI);
3960 amd64_push_reg (code, AMD64_RCX);
3961 if (ins->inst_offset)
3962 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
3964 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
3965 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8) + (size - ins->inst_imm));
3966 amd64_mov_reg_imm (code, AMD64_RCX, (ins->inst_imm >> 3));
3968 amd64_prefix (code, X86_REP_PREFIX);
3970 amd64_pop_reg (code, AMD64_RCX);
3971 amd64_pop_reg (code, AMD64_RSI);
3972 amd64_pop_reg (code, AMD64_RDI);
3976 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
3978 case OP_X86_LEA_MEMBASE:
3979 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
3982 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
3985 /* keep alignment */
3986 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
3987 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
3988 code = mono_emit_stack_alloc (code, ins);
3989 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
3991 case OP_LOCALLOC_IMM: {
3992 guint32 size = ins->inst_imm;
3993 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
3995 if (ins->flags & MONO_INST_INIT) {
3999 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4000 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4002 for (i = 0; i < size; i += 8)
4003 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4004 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4006 amd64_mov_reg_imm (code, ins->dreg, size);
4007 ins->sreg1 = ins->dreg;
4009 code = mono_emit_stack_alloc (code, ins);
4010 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4013 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4014 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4019 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4020 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4021 (gpointer)"mono_arch_throw_exception", FALSE);
4025 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4026 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4027 (gpointer)"mono_arch_rethrow_exception", FALSE);
4030 case OP_CALL_HANDLER:
4032 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4033 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4034 amd64_call_imm (code, 0);
4035 /* Restore stack alignment */
4036 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4038 case OP_START_HANDLER: {
4039 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4040 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4043 case OP_ENDFINALLY: {
4044 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4045 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4049 case OP_ENDFILTER: {
4050 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4051 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4052 /* The local allocator will put the result into RAX */
4058 ins->inst_c0 = code - cfg->native_code;
4061 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4062 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4064 if (ins->flags & MONO_INST_BRLABEL) {
4065 if (ins->inst_i0->inst_c0) {
4066 amd64_jump_code (code, cfg->native_code + ins->inst_i0->inst_c0);
4068 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_LABEL, ins->inst_i0);
4069 if ((cfg->opt & MONO_OPT_BRANCH) &&
4070 x86_is_imm8 (ins->inst_i0->inst_c1 - cpos))
4071 x86_jump8 (code, 0);
4073 x86_jump32 (code, 0);
4076 if (ins->inst_target_bb->native_offset) {
4077 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4079 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4080 if ((cfg->opt & MONO_OPT_BRANCH) &&
4081 x86_is_imm8 (ins->inst_target_bb->max_offset - cpos))
4082 x86_jump8 (code, 0);
4084 x86_jump32 (code, 0);
4089 amd64_jump_reg (code, ins->sreg1);
4106 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4107 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4109 case OP_COND_EXC_EQ:
4110 case OP_COND_EXC_NE_UN:
4111 case OP_COND_EXC_LT:
4112 case OP_COND_EXC_LT_UN:
4113 case OP_COND_EXC_GT:
4114 case OP_COND_EXC_GT_UN:
4115 case OP_COND_EXC_GE:
4116 case OP_COND_EXC_GE_UN:
4117 case OP_COND_EXC_LE:
4118 case OP_COND_EXC_LE_UN:
4119 case OP_COND_EXC_IEQ:
4120 case OP_COND_EXC_INE_UN:
4121 case OP_COND_EXC_ILT:
4122 case OP_COND_EXC_ILT_UN:
4123 case OP_COND_EXC_IGT:
4124 case OP_COND_EXC_IGT_UN:
4125 case OP_COND_EXC_IGE:
4126 case OP_COND_EXC_IGE_UN:
4127 case OP_COND_EXC_ILE:
4128 case OP_COND_EXC_ILE_UN:
4129 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4131 case OP_COND_EXC_OV:
4132 case OP_COND_EXC_NO:
4134 case OP_COND_EXC_NC:
4135 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4136 (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4138 case OP_COND_EXC_IOV:
4139 case OP_COND_EXC_INO:
4140 case OP_COND_EXC_IC:
4141 case OP_COND_EXC_INC:
4142 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4143 (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4146 /* floating point opcodes */
4148 double d = *(double *)ins->inst_p0;
4150 if ((d == 0.0) && (mono_signbit (d) == 0)) {
4151 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4154 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4155 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4160 float f = *(float *)ins->inst_p0;
4162 if ((f == 0.0) && (mono_signbit (f) == 0)) {
4163 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4166 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4167 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4168 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4172 case OP_STORER8_MEMBASE_REG:
4173 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4175 case OP_LOADR8_SPILL_MEMBASE:
4176 g_assert_not_reached ();
4178 case OP_LOADR8_MEMBASE:
4179 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4181 case OP_STORER4_MEMBASE_REG:
4182 /* This requires a double->single conversion */
4183 amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4184 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4186 case OP_LOADR4_MEMBASE:
4187 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4188 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4190 case OP_ICONV_TO_R4: /* FIXME: change precision */
4191 case OP_ICONV_TO_R8:
4192 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4194 case OP_LCONV_TO_R4: /* FIXME: change precision */
4195 case OP_LCONV_TO_R8:
4196 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4198 case OP_FCONV_TO_R4:
4199 /* FIXME: nothing to do ?? */
4201 case OP_FCONV_TO_I1:
4202 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4204 case OP_FCONV_TO_U1:
4205 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4207 case OP_FCONV_TO_I2:
4208 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4210 case OP_FCONV_TO_U2:
4211 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4213 case OP_FCONV_TO_U4:
4214 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4216 case OP_FCONV_TO_I4:
4218 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4220 case OP_FCONV_TO_I8:
4221 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4223 case OP_LCONV_TO_R_UN: {
4226 /* Based on gcc code */
4227 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4228 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4231 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4232 br [1] = code; x86_jump8 (code, 0);
4233 amd64_patch (br [0], code);
4236 /* Save to the red zone */
4237 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4238 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4239 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4240 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4241 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4242 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4243 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4244 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4245 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4247 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4248 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4249 amd64_patch (br [1], code);
4252 case OP_LCONV_TO_OVF_U4:
4253 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4254 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4255 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4257 case OP_LCONV_TO_OVF_I4_UN:
4258 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4259 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4260 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4263 if (ins->dreg != ins->sreg1)
4264 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4267 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4270 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4273 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4276 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4279 static double r8_0 = -0.0;
4281 g_assert (ins->sreg1 == ins->dreg);
4283 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4284 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4288 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4291 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4294 static guint64 d = 0x7fffffffffffffffUL;
4296 g_assert (ins->sreg1 == ins->dreg);
4298 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4299 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4303 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4306 g_assert (cfg->opt & MONO_OPT_CMOV);
4307 g_assert (ins->dreg == ins->sreg1);
4308 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4309 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4312 g_assert (cfg->opt & MONO_OPT_CMOV);
4313 g_assert (ins->dreg == ins->sreg1);
4314 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4315 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4318 g_assert (cfg->opt & MONO_OPT_CMOV);
4319 g_assert (ins->dreg == ins->sreg1);
4320 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4321 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4324 g_assert (cfg->opt & MONO_OPT_CMOV);
4325 g_assert (ins->dreg == ins->sreg1);
4326 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4327 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4330 g_assert (cfg->opt & MONO_OPT_CMOV);
4331 g_assert (ins->dreg == ins->sreg1);
4332 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4333 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4336 g_assert (cfg->opt & MONO_OPT_CMOV);
4337 g_assert (ins->dreg == ins->sreg1);
4338 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4339 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4342 g_assert (cfg->opt & MONO_OPT_CMOV);
4343 g_assert (ins->dreg == ins->sreg1);
4344 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4345 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4348 g_assert (cfg->opt & MONO_OPT_CMOV);
4349 g_assert (ins->dreg == ins->sreg1);
4350 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4351 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4357 * The two arguments are swapped because the fbranch instructions
4358 * depend on this for the non-sse case to work.
4360 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4363 /* zeroing the register at the start results in
4364 * shorter and faster code (we can also remove the widening op)
4366 guchar *unordered_check;
4367 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4368 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4369 unordered_check = code;
4370 x86_branch8 (code, X86_CC_P, 0, FALSE);
4371 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4372 amd64_patch (unordered_check, code);
4377 /* zeroing the register at the start results in
4378 * shorter and faster code (we can also remove the widening op)
4380 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4381 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4382 if (ins->opcode == OP_FCLT_UN) {
4383 guchar *unordered_check = code;
4384 guchar *jump_to_end;
4385 x86_branch8 (code, X86_CC_P, 0, FALSE);
4386 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4388 x86_jump8 (code, 0);
4389 amd64_patch (unordered_check, code);
4390 amd64_inc_reg (code, ins->dreg);
4391 amd64_patch (jump_to_end, code);
4393 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4398 /* zeroing the register at the start results in
4399 * shorter and faster code (we can also remove the widening op)
4401 guchar *unordered_check;
4402 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4403 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4404 if (ins->opcode == OP_FCGT) {
4405 unordered_check = code;
4406 x86_branch8 (code, X86_CC_P, 0, FALSE);
4407 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4408 amd64_patch (unordered_check, code);
4410 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4414 case OP_FCLT_MEMBASE:
4415 case OP_FCGT_MEMBASE:
4416 case OP_FCLT_UN_MEMBASE:
4417 case OP_FCGT_UN_MEMBASE:
4418 case OP_FCEQ_MEMBASE: {
4419 guchar *unordered_check, *jump_to_end;
4422 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4423 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4425 switch (ins->opcode) {
4426 case OP_FCEQ_MEMBASE:
4427 x86_cond = X86_CC_EQ;
4429 case OP_FCLT_MEMBASE:
4430 case OP_FCLT_UN_MEMBASE:
4431 x86_cond = X86_CC_LT;
4433 case OP_FCGT_MEMBASE:
4434 case OP_FCGT_UN_MEMBASE:
4435 x86_cond = X86_CC_GT;
4438 g_assert_not_reached ();
4441 unordered_check = code;
4442 x86_branch8 (code, X86_CC_P, 0, FALSE);
4443 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4445 switch (ins->opcode) {
4446 case OP_FCEQ_MEMBASE:
4447 case OP_FCLT_MEMBASE:
4448 case OP_FCGT_MEMBASE:
4449 amd64_patch (unordered_check, code);
4451 case OP_FCLT_UN_MEMBASE:
4452 case OP_FCGT_UN_MEMBASE:
4454 x86_jump8 (code, 0);
4455 amd64_patch (unordered_check, code);
4456 amd64_inc_reg (code, ins->dreg);
4457 amd64_patch (jump_to_end, code);
4465 guchar *jump = code;
4466 x86_branch8 (code, X86_CC_P, 0, TRUE);
4467 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4468 amd64_patch (jump, code);
4472 /* Branch if C013 != 100 */
4473 /* branch if !ZF or (PF|CF) */
4474 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4475 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4476 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4479 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4482 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4483 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4487 if (ins->opcode == OP_FBGT) {
4490 /* skip branch if C1=1 */
4492 x86_branch8 (code, X86_CC_P, 0, FALSE);
4493 /* branch if (C0 | C3) = 1 */
4494 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4495 amd64_patch (br1, code);
4498 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4502 /* Branch if C013 == 100 or 001 */
4505 /* skip branch if C1=1 */
4507 x86_branch8 (code, X86_CC_P, 0, FALSE);
4508 /* branch if (C0 | C3) = 1 */
4509 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4510 amd64_patch (br1, code);
4514 /* Branch if C013 == 000 */
4515 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4518 /* Branch if C013=000 or 100 */
4521 /* skip branch if C1=1 */
4523 x86_branch8 (code, X86_CC_P, 0, FALSE);
4524 /* branch if C0=0 */
4525 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4526 amd64_patch (br1, code);
4530 /* Branch if C013 != 001 */
4531 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4532 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4535 /* Transfer value to the fp stack */
4536 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4537 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4538 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4540 amd64_push_reg (code, AMD64_RAX);
4542 amd64_fnstsw (code);
4543 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4544 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4545 amd64_pop_reg (code, AMD64_RAX);
4546 amd64_fstp (code, 0);
4547 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4548 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4551 code = emit_tls_get (code, ins->dreg, ins->inst_offset);
4554 case OP_MEMORY_BARRIER: {
4555 /* Not needed on amd64 */
4558 case OP_ATOMIC_ADD_I4:
4559 case OP_ATOMIC_ADD_I8: {
4560 int dreg = ins->dreg;
4561 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4563 if (dreg == ins->inst_basereg)
4566 if (dreg != ins->sreg2)
4567 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4569 x86_prefix (code, X86_LOCK_PREFIX);
4570 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4572 if (dreg != ins->dreg)
4573 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4577 case OP_ATOMIC_ADD_NEW_I4:
4578 case OP_ATOMIC_ADD_NEW_I8: {
4579 int dreg = ins->dreg;
4580 guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4582 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4585 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4586 amd64_prefix (code, X86_LOCK_PREFIX);
4587 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4588 /* dreg contains the old value, add with sreg2 value */
4589 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4591 if (ins->dreg != dreg)
4592 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4596 case OP_ATOMIC_EXCHANGE_I4:
4597 case OP_ATOMIC_EXCHANGE_I8:
4598 case OP_ATOMIC_CAS_IMM_I4: {
4600 int sreg2 = ins->sreg2;
4601 int breg = ins->inst_basereg;
4603 gboolean need_push = FALSE, rdx_pushed = FALSE;
4605 if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4611 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4612 * an explanation of how this works.
4615 /* cmpxchg uses eax as comperand, need to make sure we can use it
4616 * hack to overcome limits in x86 reg allocator
4617 * (req: dreg == eax and sreg2 != eax and breg != eax)
4619 g_assert (ins->dreg == AMD64_RAX);
4621 if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4622 /* Highly unlikely, but possible */
4625 /* The pushes invalidate rsp */
4626 if ((breg == AMD64_RAX) || need_push) {
4627 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4631 /* We need the EAX reg for the comparand */
4632 if (ins->sreg2 == AMD64_RAX) {
4633 if (breg != AMD64_R11) {
4634 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4637 g_assert (need_push);
4638 amd64_push_reg (code, AMD64_RDX);
4639 amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4645 if (ins->opcode == OP_ATOMIC_CAS_IMM_I4) {
4646 if (ins->backend.data == NULL)
4647 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4649 amd64_mov_reg_imm (code, AMD64_RAX, ins->backend.data);
4651 amd64_prefix (code, X86_LOCK_PREFIX);
4652 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4654 amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4656 br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4657 amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4658 br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4659 amd64_patch (br [1], br [0]);
4663 amd64_pop_reg (code, AMD64_RDX);
4668 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
4669 g_assert_not_reached ();
4672 if ((code - cfg->native_code - offset) > max_len) {
4673 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
4674 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
4675 g_assert_not_reached ();
4681 last_offset = offset;
4684 cfg->code_len = code - cfg->native_code;
4687 #endif /* DISABLE_JIT */
4690 mono_arch_register_lowlevel_calls (void)
4692 /* The signature doesn't matter */
4693 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
4697 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
4699 MonoJumpInfo *patch_info;
4700 gboolean compile_aot = !run_cctors;
4702 for (patch_info = ji; patch_info; patch_info = patch_info->next) {
4703 unsigned char *ip = patch_info->ip.i + code;
4704 unsigned char *target;
4706 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
4709 switch (patch_info->type) {
4710 case MONO_PATCH_INFO_BB:
4711 case MONO_PATCH_INFO_LABEL:
4714 /* No need to patch these */
4719 switch (patch_info->type) {
4720 case MONO_PATCH_INFO_NONE:
4722 case MONO_PATCH_INFO_METHOD_REL:
4723 case MONO_PATCH_INFO_R8:
4724 case MONO_PATCH_INFO_R4:
4725 g_assert_not_reached ();
4727 case MONO_PATCH_INFO_BB:
4734 * Debug code to help track down problems where the target of a near call is
4737 if (amd64_is_near_call (ip)) {
4738 gint64 disp = (guint8*)target - (guint8*)ip;
4740 if (!amd64_is_imm32 (disp)) {
4741 printf ("TYPE: %d\n", patch_info->type);
4742 switch (patch_info->type) {
4743 case MONO_PATCH_INFO_INTERNAL_METHOD:
4744 printf ("V: %s\n", patch_info->data.name);
4746 case MONO_PATCH_INFO_METHOD_JUMP:
4747 case MONO_PATCH_INFO_METHOD:
4748 printf ("V: %s\n", patch_info->data.method->name);
4756 amd64_patch (ip, (gpointer)target);
4761 get_max_epilog_size (MonoCompile *cfg)
4763 int max_epilog_size = 16;
4765 if (cfg->method->save_lmf)
4766 max_epilog_size += 256;
4768 if (mono_jit_trace_calls != NULL)
4769 max_epilog_size += 50;
4771 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4772 max_epilog_size += 50;
4774 max_epilog_size += (AMD64_NREG * 2);
4776 return max_epilog_size;
4780 * This macro is used for testing whenever the unwinder works correctly at every point
4781 * where an async exception can happen.
4783 /* This will generate a SIGSEGV at the given point in the code */
4784 #define async_exc_point(code) do { \
4785 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
4786 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
4787 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
4788 cfg->arch.async_point_count ++; \
4793 mono_arch_emit_prolog (MonoCompile *cfg)
4795 MonoMethod *method = cfg->method;
4797 MonoMethodSignature *sig;
4799 int alloc_size, pos, max_offset, i, quad, max_epilog_size;
4802 gint32 lmf_offset = cfg->arch.lmf_offset;
4803 gboolean args_clobbered = FALSE;
4804 gboolean trace = FALSE;
4806 cfg->code_size = MAX (((MonoMethodNormal *)method)->header->code_size * 4, 10240);
4808 code = cfg->native_code = g_malloc (cfg->code_size);
4810 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
4813 /* Amount of stack space allocated by register saving code */
4817 * The prolog consists of the following parts:
4819 * - push rbp, mov rbp, rsp
4820 * - save callee saved regs using pushes
4822 * - save rgctx if needed
4823 * - save lmf if needed
4826 * - save rgctx if needed
4827 * - save lmf if needed
4828 * - save callee saved regs using moves
4831 async_exc_point (code);
4833 if (!cfg->arch.omit_fp) {
4834 amd64_push_reg (code, AMD64_RBP);
4835 async_exc_point (code);
4836 #ifdef PLATFORM_WIN32
4837 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4840 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
4841 async_exc_point (code);
4842 #ifdef PLATFORM_WIN32
4843 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
4847 /* Save callee saved registers */
4848 if (!cfg->arch.omit_fp && !method->save_lmf) {
4849 for (i = 0; i < AMD64_NREG; ++i)
4850 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4851 amd64_push_reg (code, i);
4852 pos += sizeof (gpointer);
4853 async_exc_point (code);
4857 if (cfg->arch.omit_fp) {
4859 * On enter, the stack is misaligned by the the pushing of the return
4860 * address. It is either made aligned by the pushing of %rbp, or by
4863 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
4864 if ((alloc_size % 16) == 0)
4867 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
4872 cfg->arch.stack_alloc_size = alloc_size;
4874 /* Allocate stack frame */
4876 /* See mono_emit_stack_alloc */
4877 #if defined(PLATFORM_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
4878 guint32 remaining_size = alloc_size;
4879 while (remaining_size >= 0x1000) {
4880 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
4881 async_exc_point (code);
4882 #ifdef PLATFORM_WIN32
4883 if (cfg->arch.omit_fp)
4884 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
4887 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
4888 remaining_size -= 0x1000;
4890 if (remaining_size) {
4891 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
4892 async_exc_point (code);
4893 #ifdef PLATFORM_WIN32
4894 if (cfg->arch.omit_fp)
4895 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
4899 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
4900 async_exc_point (code);
4904 /* Stack alignment check */
4907 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
4908 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
4909 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
4910 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
4911 amd64_breakpoint (code);
4916 if (method->save_lmf) {
4918 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
4920 /* sp is saved right before calls */
4921 /* Skip method (only needed for trampoline LMF frames) */
4922 /* Save callee saved regs */
4923 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), AMD64_RBX, 8);
4924 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
4925 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), AMD64_R12, 8);
4926 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), AMD64_R13, 8);
4927 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), AMD64_R14, 8);
4928 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), AMD64_R15, 8);
4931 /* Save callee saved registers */
4932 if (cfg->arch.omit_fp && !method->save_lmf) {
4933 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
4935 /* Save caller saved registers after sp is adjusted */
4936 /* The registers are saved at the bottom of the frame */
4937 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
4938 for (i = 0; i < AMD64_NREG; ++i)
4939 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4940 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
4941 save_area_offset += 8;
4942 async_exc_point (code);
4946 /* store runtime generic context */
4947 if (cfg->rgctx_var) {
4948 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
4949 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
4951 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
4954 /* compute max_offset in order to use short forward jumps */
4956 max_epilog_size = get_max_epilog_size (cfg);
4957 if (cfg->opt & MONO_OPT_BRANCH) {
4958 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
4960 bb->max_offset = max_offset;
4962 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
4964 /* max alignment for loops */
4965 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
4966 max_offset += LOOP_ALIGNMENT;
4968 MONO_BB_FOR_EACH_INS (bb, ins) {
4969 if (ins->opcode == OP_LABEL)
4970 ins->inst_c1 = max_offset;
4972 max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4975 if (mono_jit_trace_calls && bb == cfg->bb_exit)
4976 /* The tracing code can be quite large */
4977 max_offset += max_epilog_size;
4981 sig = mono_method_signature (method);
4984 cinfo = cfg->arch.cinfo;
4986 if (sig->ret->type != MONO_TYPE_VOID) {
4987 /* Save volatile arguments to the stack */
4988 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
4989 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
4992 /* Keep this in sync with emit_load_volatile_arguments */
4993 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
4994 ArgInfo *ainfo = cinfo->args + i;
4995 gint32 stack_offset;
4998 ins = cfg->args [i];
5000 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5001 /* Unused arguments */
5004 if (sig->hasthis && (i == 0))
5005 arg_type = &mono_defaults.object_class->byval_arg;
5007 arg_type = sig->params [i - sig->hasthis];
5009 stack_offset = ainfo->offset + ARGS_OFFSET;
5011 if (cfg->globalra) {
5012 /* All the other moves are done by the register allocator */
5013 switch (ainfo->storage) {
5014 case ArgInFloatSSEReg:
5015 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
5017 case ArgValuetypeInReg:
5018 for (quad = 0; quad < 2; quad ++) {
5019 switch (ainfo->pair_storage [quad]) {
5021 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5023 case ArgInFloatSSEReg:
5024 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5026 case ArgInDoubleSSEReg:
5027 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5032 g_assert_not_reached ();
5043 /* Save volatile arguments to the stack */
5044 if (ins->opcode != OP_REGVAR) {
5045 switch (ainfo->storage) {
5051 if (stack_offset & 0x1)
5053 else if (stack_offset & 0x2)
5055 else if (stack_offset & 0x4)
5060 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
5063 case ArgInFloatSSEReg:
5064 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5066 case ArgInDoubleSSEReg:
5067 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
5069 case ArgValuetypeInReg:
5070 for (quad = 0; quad < 2; quad ++) {
5071 switch (ainfo->pair_storage [quad]) {
5073 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
5075 case ArgInFloatSSEReg:
5076 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5078 case ArgInDoubleSSEReg:
5079 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
5084 g_assert_not_reached ();
5088 case ArgValuetypeAddrInIReg:
5089 if (ainfo->pair_storage [0] == ArgInIReg)
5090 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
5096 /* Argument allocated to (non-volatile) register */
5097 switch (ainfo->storage) {
5099 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
5102 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
5105 g_assert_not_reached ();
5110 /* Might need to attach the thread to the JIT or change the domain for the callback */
5111 if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
5112 guint64 domain = (guint64)cfg->domain;
5114 args_clobbered = TRUE;
5117 * The call might clobber argument registers, but they are already
5118 * saved to the stack/global regs.
5120 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
5121 guint8 *buf, *no_domain_branch;
5123 code = emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
5124 if ((domain >> 32) == 0)
5125 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5127 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5128 amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
5129 no_domain_branch = code;
5130 x86_branch8 (code, X86_CC_NE, 0, 0);
5131 code = emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
5132 amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5134 x86_branch8 (code, X86_CC_NE, 0, 0);
5135 amd64_patch (no_domain_branch, code);
5136 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5137 (gpointer)"mono_jit_thread_attach", TRUE);
5138 amd64_patch (buf, code);
5139 #ifdef PLATFORM_WIN32
5140 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5141 /* FIXME: Add a separate key for LMF to avoid this */
5142 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5145 g_assert (!cfg->compile_aot);
5146 if ((domain >> 32) == 0)
5147 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
5149 amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
5150 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5151 (gpointer)"mono_jit_thread_attach", TRUE);
5155 if (method->save_lmf) {
5156 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5158 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5159 * through the mono_lmf_addr TLS variable.
5161 /* %rax = previous_lmf */
5162 x86_prefix (code, X86_FS_PREFIX);
5163 amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
5165 /* Save previous_lmf */
5166 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
5168 if (lmf_offset == 0) {
5169 x86_prefix (code, X86_FS_PREFIX);
5170 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
5172 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5173 x86_prefix (code, X86_FS_PREFIX);
5174 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5177 if (lmf_addr_tls_offset != -1) {
5178 /* Load lmf quicky using the FS register */
5179 code = emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
5180 #ifdef PLATFORM_WIN32
5181 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
5182 /* FIXME: Add a separate key for LMF to avoid this */
5183 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
5188 * The call might clobber argument registers, but they are already
5189 * saved to the stack/global regs.
5191 args_clobbered = TRUE;
5192 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5193 (gpointer)"mono_get_lmf_addr", TRUE);
5197 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
5198 /* Save previous_lmf */
5199 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
5200 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
5202 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
5203 amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
5208 args_clobbered = TRUE;
5209 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
5212 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5213 args_clobbered = TRUE;
5216 * Optimize the common case of the first bblock making a call with the same
5217 * arguments as the method. This works because the arguments are still in their
5218 * original argument registers.
5219 * FIXME: Generalize this
5221 if (!args_clobbered) {
5222 MonoBasicBlock *first_bb = cfg->bb_entry;
5225 next = mono_bb_first_ins (first_bb);
5226 if (!next && first_bb->next_bb) {
5227 first_bb = first_bb->next_bb;
5228 next = mono_bb_first_ins (first_bb);
5231 if (first_bb->in_count > 1)
5234 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
5235 ArgInfo *ainfo = cinfo->args + i;
5236 gboolean match = FALSE;
5238 ins = cfg->args [i];
5239 if (ins->opcode != OP_REGVAR) {
5240 switch (ainfo->storage) {
5242 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
5243 if (next->dreg == ainfo->reg) {
5247 next->opcode = OP_MOVE;
5248 next->sreg1 = ainfo->reg;
5249 /* Only continue if the instruction doesn't change argument regs */
5250 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
5260 /* Argument allocated to (non-volatile) register */
5261 switch (ainfo->storage) {
5263 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
5275 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
5282 cfg->code_len = code - cfg->native_code;
5284 g_assert (cfg->code_len < cfg->code_size);
5290 mono_arch_emit_epilog (MonoCompile *cfg)
5292 MonoMethod *method = cfg->method;
5295 int max_epilog_size;
5297 gint32 lmf_offset = cfg->arch.lmf_offset;
5299 max_epilog_size = get_max_epilog_size (cfg);
5301 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
5302 cfg->code_size *= 2;
5303 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5304 mono_jit_stats.code_reallocs++;
5307 code = cfg->native_code + cfg->code_len;
5309 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5310 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
5312 /* the code restoring the registers must be kept in sync with OP_JMP */
5315 if (method->save_lmf) {
5316 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
5318 * Optimized version which uses the mono_lmf TLS variable instead of indirection
5319 * through the mono_lmf_addr TLS variable.
5321 /* reg = previous_lmf */
5322 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5323 x86_prefix (code, X86_FS_PREFIX);
5324 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
5326 /* Restore previous lmf */
5327 amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
5328 amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
5329 amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
5332 /* Restore caller saved regs */
5333 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
5334 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
5336 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
5337 amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
5339 if (cfg->used_int_regs & (1 << AMD64_R12)) {
5340 amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
5342 if (cfg->used_int_regs & (1 << AMD64_R13)) {
5343 amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
5345 if (cfg->used_int_regs & (1 << AMD64_R14)) {
5346 amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
5348 if (cfg->used_int_regs & (1 << AMD64_R15)) {
5349 amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
5353 if (cfg->arch.omit_fp) {
5354 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5356 for (i = 0; i < AMD64_NREG; ++i)
5357 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5358 amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
5359 save_area_offset += 8;
5363 for (i = 0; i < AMD64_NREG; ++i)
5364 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
5365 pos -= sizeof (gpointer);
5368 if (pos == - sizeof (gpointer)) {
5369 /* Only one register, so avoid lea */
5370 for (i = AMD64_NREG - 1; i > 0; --i)
5371 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5372 amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
5376 amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
5378 /* Pop registers in reverse order */
5379 for (i = AMD64_NREG - 1; i > 0; --i)
5380 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5381 amd64_pop_reg (code, i);
5388 /* Load returned vtypes into registers if needed */
5389 cinfo = cfg->arch.cinfo;
5390 if (cinfo->ret.storage == ArgValuetypeInReg) {
5391 ArgInfo *ainfo = &cinfo->ret;
5392 MonoInst *inst = cfg->ret;
5394 for (quad = 0; quad < 2; quad ++) {
5395 switch (ainfo->pair_storage [quad]) {
5397 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
5399 case ArgInFloatSSEReg:
5400 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5402 case ArgInDoubleSSEReg:
5403 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
5408 g_assert_not_reached ();
5413 if (cfg->arch.omit_fp) {
5414 if (cfg->arch.stack_alloc_size)
5415 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
5419 async_exc_point (code);
5422 cfg->code_len = code - cfg->native_code;
5424 g_assert (cfg->code_len < cfg->code_size);
5426 if (cfg->arch.omit_fp) {
5428 * Encode the stack size into used_int_regs so the exception handler
5431 g_assert (cfg->arch.stack_alloc_size < (1 << 16));
5432 cfg->used_int_regs |= (1 << 31) | (cfg->arch.stack_alloc_size << 16);
5437 mono_arch_emit_exceptions (MonoCompile *cfg)
5439 MonoJumpInfo *patch_info;
5442 MonoClass *exc_classes [16];
5443 guint8 *exc_throw_start [16], *exc_throw_end [16];
5444 guint32 code_size = 0;
5446 /* Compute needed space */
5447 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5448 if (patch_info->type == MONO_PATCH_INFO_EXC)
5450 if (patch_info->type == MONO_PATCH_INFO_R8)
5451 code_size += 8 + 15; /* sizeof (double) + alignment */
5452 if (patch_info->type == MONO_PATCH_INFO_R4)
5453 code_size += 4 + 15; /* sizeof (float) + alignment */
5456 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
5457 cfg->code_size *= 2;
5458 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5459 mono_jit_stats.code_reallocs++;
5462 code = cfg->native_code + cfg->code_len;
5464 /* add code to raise exceptions */
5466 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5467 switch (patch_info->type) {
5468 case MONO_PATCH_INFO_EXC: {
5469 MonoClass *exc_class;
5473 amd64_patch (patch_info->ip.i + cfg->native_code, code);
5475 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
5476 g_assert (exc_class);
5477 throw_ip = patch_info->ip.i;
5479 //x86_breakpoint (code);
5480 /* Find a throw sequence for the same exception class */
5481 for (i = 0; i < nthrows; ++i)
5482 if (exc_classes [i] == exc_class)
5485 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
5486 x86_jump_code (code, exc_throw_start [i]);
5487 patch_info->type = MONO_PATCH_INFO_NONE;
5491 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
5495 exc_classes [nthrows] = exc_class;
5496 exc_throw_start [nthrows] = code;
5498 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token);
5500 patch_info->type = MONO_PATCH_INFO_NONE;
5502 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
5504 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
5509 exc_throw_end [nthrows] = code;
5521 /* Handle relocations with RIP relative addressing */
5522 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
5523 gboolean remove = FALSE;
5525 switch (patch_info->type) {
5526 case MONO_PATCH_INFO_R8:
5527 case MONO_PATCH_INFO_R4: {
5530 /* The SSE opcodes require a 16 byte alignment */
5531 code = (guint8*)ALIGN_TO (code, 16);
5533 pos = cfg->native_code + patch_info->ip.i;
5535 if (IS_REX (pos [1]))
5536 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
5538 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
5540 if (patch_info->type == MONO_PATCH_INFO_R8) {
5541 *(double*)code = *(double*)patch_info->data.target;
5542 code += sizeof (double);
5544 *(float*)code = *(float*)patch_info->data.target;
5545 code += sizeof (float);
5556 if (patch_info == cfg->patch_info)
5557 cfg->patch_info = patch_info->next;
5561 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
5563 tmp->next = patch_info->next;
5568 cfg->code_len = code - cfg->native_code;
5570 g_assert (cfg->code_len < cfg->code_size);
5575 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5578 CallInfo *cinfo = NULL;
5579 MonoMethodSignature *sig;
5581 int i, n, stack_area = 0;
5583 /* Keep this in sync with mono_arch_get_argument_info */
5585 if (enable_arguments) {
5586 /* Allocate a new area on the stack and save arguments there */
5587 sig = mono_method_signature (cfg->method);
5589 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
5591 n = sig->param_count + sig->hasthis;
5593 stack_area = ALIGN_TO (n * 8, 16);
5595 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
5597 for (i = 0; i < n; ++i) {
5598 inst = cfg->args [i];
5600 if (inst->opcode == OP_REGVAR)
5601 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
5603 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
5604 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
5609 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
5610 amd64_set_reg_template (code, AMD64_ARG_REG1);
5611 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
5612 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5614 if (enable_arguments)
5615 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
5629 mono_arch_instrument_epilog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
5632 int save_mode = SAVE_NONE;
5633 MonoMethod *method = cfg->method;
5634 int rtype = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret)->type;
5637 case MONO_TYPE_VOID:
5638 /* special case string .ctor icall */
5639 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
5640 save_mode = SAVE_EAX;
5642 save_mode = SAVE_NONE;
5646 save_mode = SAVE_EAX;
5650 save_mode = SAVE_XMM;
5652 case MONO_TYPE_GENERICINST:
5653 if (!mono_type_generic_inst_is_valuetype (mono_method_signature (method)->ret)) {
5654 save_mode = SAVE_EAX;
5658 case MONO_TYPE_VALUETYPE:
5659 save_mode = SAVE_STRUCT;
5662 save_mode = SAVE_EAX;
5666 /* Save the result and copy it into the proper argument register */
5667 switch (save_mode) {
5669 amd64_push_reg (code, AMD64_RAX);
5671 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5672 if (enable_arguments)
5673 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
5677 if (enable_arguments)
5678 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
5681 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5682 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
5684 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5686 * The result is already in the proper argument register so no copying
5693 g_assert_not_reached ();
5696 /* Set %al since this is a varargs call */
5697 if (save_mode == SAVE_XMM)
5698 amd64_mov_reg_imm (code, AMD64_RAX, 1);
5700 amd64_mov_reg_imm (code, AMD64_RAX, 0);
5702 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
5703 amd64_set_reg_template (code, AMD64_ARG_REG1);
5704 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
5706 /* Restore result */
5707 switch (save_mode) {
5709 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5710 amd64_pop_reg (code, AMD64_RAX);
5716 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5717 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
5718 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5723 g_assert_not_reached ();
5730 mono_arch_flush_icache (guint8 *code, gint size)
5736 mono_arch_flush_register_windows (void)
5741 mono_arch_is_inst_imm (gint64 imm)
5743 return amd64_is_imm32 (imm);
5747 * Determine whenever the trap whose info is in SIGINFO is caused by
5751 mono_arch_is_int_overflow (void *sigctx, void *info)
5758 mono_arch_sigctx_to_monoctx (sigctx, &ctx);
5760 rip = (guint8*)ctx.rip;
5762 if (IS_REX (rip [0])) {
5763 reg = amd64_rex_b (rip [0]);
5769 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
5771 reg += x86_modrm_rm (rip [1]);
5811 g_assert_not_reached ();
5823 mono_arch_get_patch_offset (guint8 *code)
5829 * mono_breakpoint_clean_code:
5831 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
5832 * breakpoints in the original code, they are removed in the copy.
5834 * Returns TRUE if no sw breakpoint was present.
5837 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
5840 gboolean can_write = TRUE;
5842 * If method_start is non-NULL we need to perform bound checks, since we access memory
5843 * at code - offset we could go before the start of the method and end up in a different
5844 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
5847 if (!method_start || code - offset >= method_start) {
5848 memcpy (buf, code - offset, size);
5850 int diff = code - method_start;
5851 memset (buf, 0, size);
5852 memcpy (buf + offset - diff, method_start, diff + size - offset);
5855 for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
5856 int idx = mono_breakpoint_info_index [i];
5860 ptr = mono_breakpoint_info [idx].address;
5861 if (ptr >= code && ptr < code + size) {
5862 guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
5864 /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
5865 buf [ptr - code] = saved_byte;
5872 mono_arch_get_vcall_slot (guint8 *code, gpointer *regs, int *displacement)
5879 mono_breakpoint_clean_code (NULL, code, 9, buf, sizeof (buf));
5884 /* go to the start of the call instruction
5886 * address_byte = (m << 6) | (o << 3) | reg
5887 * call opcode: 0xff address_byte displacement
5889 * 0xff m=2,o=2 imm32
5894 * A given byte sequence can match more than case here, so we have to be
5895 * really careful about the ordering of the cases. Longer sequences
5898 #ifdef MONO_ARCH_HAVE_IMT
5899 if ((code [-2] == 0x41) && (code [-1] == 0xbb) && (code [4] == 0xff) && (x86_modrm_mod (code [5]) == 1) && (x86_modrm_reg (code [5]) == 2) && ((signed char)code [6] < 0)) {
5900 /* IMT-based interface calls: with MONO_ARCH_IMT_REG == r11
5901 * 41 bb 14 f8 28 08 mov $0x828f814,%r11d
5902 * ff 50 fc call *0xfffffffc(%rax)
5904 reg = amd64_modrm_rm (code [5]);
5905 disp = (signed char)code [6];
5906 /* R10 is clobbered by the IMT thunk code */
5907 g_assert (reg != AMD64_R10);
5913 else if ((code [-1] == 0x8b) && (amd64_modrm_mod (code [0]) == 0x2) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5915 * This is a interface call
5916 * 48 8b 80 f0 e8 ff ff mov 0xffffffffffffe8f0(%rax),%rax
5917 * ff 10 callq *(%rax)
5919 if (IS_REX (code [4]))
5921 reg = amd64_modrm_rm (code [6]);
5923 /* R10 is clobbered by the IMT thunk code */
5924 g_assert (reg != AMD64_R10);
5925 } else if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
5926 /* call OFFSET(%rip) */
5927 disp = *(guint32*)(code + 3);
5928 return (gpointer*)(code + disp + 7);
5929 } else if ((code [0] == 0xff) && (amd64_modrm_reg (code [1]) == 0x2) && (amd64_modrm_mod (code [1]) == 0x2) && (amd64_modrm_reg (code [2]) == X86_ESP) && (amd64_modrm_mod (code [2]) == 0) && (amd64_modrm_rm (code [2]) == X86_ESP)) {
5930 /* call *[r12+disp32] */
5931 if (IS_REX (code [-1]))
5934 disp = *(gint32*)(code + 3);
5935 } else if ((code [1] == 0xff) && (amd64_modrm_reg (code [2]) == 0x2) && (amd64_modrm_mod (code [2]) == 0x2)) {
5936 /* call *[reg+disp32] */
5937 if (IS_REX (code [0]))
5939 reg = amd64_modrm_rm (code [2]);
5940 disp = *(gint32*)(code + 3);
5941 /* R10 is clobbered by the IMT thunk code */
5942 g_assert (reg != AMD64_R10);
5943 } else if (code [2] == 0xe8) {
5946 } else if ((code [3] == 0xff) && (amd64_modrm_reg (code [4]) == 0x2) && (amd64_modrm_mod (code [4]) == 0x1) && (amd64_modrm_reg (code [5]) == X86_ESP) && (amd64_modrm_mod (code [5]) == 0) && (amd64_modrm_rm (code [5]) == X86_ESP)) {
5947 /* call *[r12+disp32] */
5948 if (IS_REX (code [2]))
5951 disp = *(gint8*)(code + 6);
5952 } else if (IS_REX (code [4]) && (code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x3)) {
5955 } else if ((code [4] == 0xff) && (amd64_modrm_reg (code [5]) == 0x2) && (amd64_modrm_mod (code [5]) == 0x1)) {
5956 /* call *[reg+disp8] */
5957 if (IS_REX (code [3]))
5959 reg = amd64_modrm_rm (code [5]);
5960 disp = *(gint8*)(code + 6);
5961 //printf ("B: [%%r%d+0x%x]\n", reg, disp);
5963 else if ((code [5] == 0xff) && (amd64_modrm_reg (code [6]) == 0x2) && (amd64_modrm_mod (code [6]) == 0x0)) {
5965 * This is a interface call: should check the above code can't catch it earlier
5966 * 8b 40 30 mov 0x30(%eax),%eax
5967 * ff 10 call *(%eax)
5969 if (IS_REX (code [4]))
5971 reg = amd64_modrm_rm (code [6]);
5975 g_assert_not_reached ();
5977 reg += amd64_rex_b (rex);
5979 /* R11 is clobbered by the trampoline code */
5980 g_assert (reg != AMD64_R11);
5982 *displacement = disp;
5987 mono_arch_get_vcall_slot_addr (guint8* code, gpointer *regs)
5991 vt = mono_arch_get_vcall_slot (code, regs, &displacement);
5994 return (gpointer*)((char*)vt + displacement);
5998 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6000 int this_reg = AMD64_ARG_REG1;
6002 if (MONO_TYPE_ISSTRUCT (sig->ret)) {
6006 gsctx = mono_get_generic_context_from_code (code);
6008 cinfo = get_call_info (gsctx, NULL, sig, FALSE);
6010 if (cinfo->ret.storage != ArgValuetypeInReg)
6011 this_reg = AMD64_ARG_REG2;
6019 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, gssize *regs, guint8 *code)
6021 return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6024 #define MAX_ARCH_DELEGATE_PARAMS 10
6027 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
6029 guint8 *code, *start;
6032 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
6035 /* FIXME: Support more cases */
6036 if (MONO_TYPE_ISSTRUCT (sig->ret))
6040 static guint8* cached = NULL;
6045 start = code = mono_global_codeman_reserve (64);
6047 /* Replace the this argument with the target */
6048 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6049 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6050 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6052 g_assert ((code - start) < 64);
6054 mono_debug_add_delegate_trampoline (start, code - start);
6056 mono_memory_barrier ();
6060 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
6061 for (i = 0; i < sig->param_count; ++i)
6062 if (!mono_is_regsize_var (sig->params [i]))
6064 if (sig->param_count > 4)
6067 code = cache [sig->param_count];
6071 start = code = mono_global_codeman_reserve (64);
6073 if (sig->param_count == 0) {
6074 amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6076 /* We have to shift the arguments left */
6077 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6078 for (i = 0; i < sig->param_count; ++i) {
6079 #ifdef PLATFORM_WIN32
6081 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6083 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6085 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6089 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6091 g_assert ((code - start) < 64);
6093 mono_debug_add_delegate_trampoline (start, code - start);
6095 mono_memory_barrier ();
6097 cache [sig->param_count] = start;
6104 * Support for fast access to the thread-local lmf structure using the GS
6105 * segment register on NPTL + kernel 2.6.x.
6108 static gboolean tls_offset_inited = FALSE;
6111 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
6113 if (!tls_offset_inited) {
6114 #ifdef PLATFORM_WIN32
6116 * We need to init this multiple times, since when we are first called, the key might not
6117 * be initialized yet.
6119 appdomain_tls_offset = mono_domain_get_tls_key ();
6120 lmf_tls_offset = mono_get_jit_tls_key ();
6121 thread_tls_offset = mono_thread_get_tls_key ();
6122 lmf_addr_tls_offset = mono_get_jit_tls_key ();
6124 /* Only 64 tls entries can be accessed using inline code */
6125 if (appdomain_tls_offset >= 64)
6126 appdomain_tls_offset = -1;
6127 if (lmf_tls_offset >= 64)
6128 lmf_tls_offset = -1;
6129 if (thread_tls_offset >= 64)
6130 thread_tls_offset = -1;
6132 tls_offset_inited = TRUE;
6134 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
6136 appdomain_tls_offset = mono_domain_get_tls_offset ();
6137 lmf_tls_offset = mono_get_lmf_tls_offset ();
6138 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
6139 thread_tls_offset = mono_thread_get_tls_offset ();
6145 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
6150 mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int this_reg, int this_type, int vt_reg)
6152 MonoCallInst *call = (MonoCallInst*)inst;
6153 CallInfo * cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, inst->signature, FALSE);
6158 if (cinfo->ret.storage == ArgValuetypeInReg) {
6160 * The valuetype is in RAX:RDX after the call, need to be copied to
6161 * the stack. Save the address here, so the call instruction can
6164 MonoInst *loc = cfg->arch.vret_addr_loc;
6167 g_assert (loc->opcode == OP_REGOFFSET);
6169 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, loc->inst_basereg, loc->inst_offset, vt_reg);
6171 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
6172 vtarg->sreg1 = vt_reg;
6173 vtarg->dreg = mono_regstate_next_int (cfg->rs);
6174 mono_bblock_add_inst (cfg->cbb, vtarg);
6176 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
6180 /* add the this argument */
6181 if (this_reg != -1) {
6183 MONO_INST_NEW (cfg, this, OP_MOVE);
6184 this->type = this_type;
6185 this->sreg1 = this_reg;
6186 this->dreg = mono_regstate_next_int (cfg->rs);
6187 mono_bblock_add_inst (cfg->cbb, this);
6189 mono_call_inst_add_outarg_reg (cfg, call, this->dreg, cinfo->args [0].reg, FALSE);
6193 #ifdef MONO_ARCH_HAVE_IMT
6195 #define CMP_SIZE (6 + 1)
6196 #define CMP_REG_REG_SIZE (4 + 1)
6197 #define BR_SMALL_SIZE 2
6198 #define BR_LARGE_SIZE 6
6199 #define MOV_REG_IMM_SIZE 10
6200 #define MOV_REG_IMM_32BIT_SIZE 6
6201 #define JUMP_REG_SIZE (2 + 1)
6204 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
6206 int i, distance = 0;
6207 for (i = start; i < target; ++i)
6208 distance += imt_entries [i]->chunk_size;
6213 * LOCKING: called with the domain lock held
6216 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count)
6220 guint8 *code, *start;
6221 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
6223 for (i = 0; i < count; ++i) {
6224 MonoIMTCheckItem *item = imt_entries [i];
6225 if (item->is_equals) {
6226 if (item->check_target_idx) {
6227 if (!item->compare_done) {
6228 if (amd64_is_imm32 (item->method))
6229 item->chunk_size += CMP_SIZE;
6231 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6233 if (vtable_is_32bit)
6234 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6236 item->chunk_size += MOV_REG_IMM_SIZE;
6237 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
6239 if (vtable_is_32bit)
6240 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
6242 item->chunk_size += MOV_REG_IMM_SIZE;
6243 item->chunk_size += JUMP_REG_SIZE;
6244 /* with assert below:
6245 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
6249 if (amd64_is_imm32 (item->method))
6250 item->chunk_size += CMP_SIZE;
6252 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
6253 item->chunk_size += BR_LARGE_SIZE;
6254 imt_entries [item->check_target_idx]->compare_done = TRUE;
6256 size += item->chunk_size;
6258 code = mono_code_manager_reserve (domain->code_mp, size);
6260 for (i = 0; i < count; ++i) {
6261 MonoIMTCheckItem *item = imt_entries [i];
6262 item->code_target = code;
6263 if (item->is_equals) {
6264 if (item->check_target_idx) {
6265 if (!item->compare_done) {
6266 if (amd64_is_imm32 (item->method))
6267 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6269 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6270 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6273 item->jmp_code = code;
6274 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6275 /* See the comment below about R10 */
6276 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6277 amd64_jump_membase (code, AMD64_R10, 0);
6279 /* enable the commented code to assert on wrong method */
6281 if (amd64_is_imm32 (item->method))
6282 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6284 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6285 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6287 item->jmp_code = code;
6288 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
6289 /* See the comment below about R10 */
6290 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6291 amd64_jump_membase (code, AMD64_R10, 0);
6292 amd64_patch (item->jmp_code, code);
6293 amd64_breakpoint (code);
6294 item->jmp_code = NULL;
6296 /* We're using R10 here because R11
6297 needs to be preserved. R10 needs
6298 to be preserved for calls which
6299 require a runtime generic context,
6300 but interface calls don't. */
6301 amd64_mov_reg_imm (code, AMD64_R10, & (vtable->vtable [item->vtable_slot]));
6302 amd64_jump_membase (code, AMD64_R10, 0);
6306 if (amd64_is_imm32 (item->method))
6307 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->method);
6309 amd64_mov_reg_imm (code, AMD64_R10, item->method);
6310 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R10);
6312 item->jmp_code = code;
6313 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
6314 x86_branch8 (code, X86_CC_GE, 0, FALSE);
6316 x86_branch32 (code, X86_CC_GE, 0, FALSE);
6318 g_assert (code - item->code_target <= item->chunk_size);
6320 /* patch the branches to get to the target items */
6321 for (i = 0; i < count; ++i) {
6322 MonoIMTCheckItem *item = imt_entries [i];
6323 if (item->jmp_code) {
6324 if (item->check_target_idx) {
6325 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
6330 mono_stats.imt_thunks_size += code - start;
6331 g_assert (code - start <= size);
6337 mono_arch_find_imt_method (gpointer *regs, guint8 *code)
6339 return regs [MONO_ARCH_IMT_REG];
6343 mono_arch_find_this_argument (gpointer *regs, MonoMethod *method, MonoGenericSharingContext *gsctx)
6345 return mono_arch_get_this_arg_from_call (gsctx, mono_method_signature (method), (gssize*)regs, NULL);
6349 mono_arch_emit_imt_argument (MonoCompile *cfg, MonoCallInst *call, MonoInst *imt_arg)
6351 /* Done by the implementation of the CALL_MEMBASE opcodes */
6356 mono_arch_find_static_call_vtable (gpointer *regs, guint8 *code)
6358 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
6362 mono_arch_get_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6364 MonoInst *ins = NULL;
6366 if (cmethod->klass == mono_defaults.math_class) {
6367 if (strcmp (cmethod->name, "Sin") == 0) {
6368 MONO_INST_NEW (cfg, ins, OP_SIN);
6369 ins->inst_i0 = args [0];
6370 } else if (strcmp (cmethod->name, "Cos") == 0) {
6371 MONO_INST_NEW (cfg, ins, OP_COS);
6372 ins->inst_i0 = args [0];
6373 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6374 MONO_INST_NEW (cfg, ins, OP_SQRT);
6375 ins->inst_i0 = args [0];
6376 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6377 MONO_INST_NEW (cfg, ins, OP_ABS);
6378 ins->inst_i0 = args [0];
6381 if (cfg->opt & MONO_OPT_CMOV) {
6384 if (strcmp (cmethod->name, "Min") == 0) {
6385 if (fsig->params [0]->type == MONO_TYPE_I4)
6387 if (fsig->params [0]->type == MONO_TYPE_U4)
6388 opcode = OP_IMIN_UN;
6389 else if (fsig->params [0]->type == MONO_TYPE_I8)
6391 else if (fsig->params [0]->type == MONO_TYPE_U8)
6392 opcode = OP_LMIN_UN;
6393 } else if (strcmp (cmethod->name, "Max") == 0) {
6394 if (fsig->params [0]->type == MONO_TYPE_I4)
6396 if (fsig->params [0]->type == MONO_TYPE_U4)
6397 opcode = OP_IMAX_UN;
6398 else if (fsig->params [0]->type == MONO_TYPE_I8)
6400 else if (fsig->params [0]->type == MONO_TYPE_U8)
6401 opcode = OP_LMAX_UN;
6405 MONO_INST_NEW (cfg, ins, opcode);
6406 ins->inst_i0 = args [0];
6407 ins->inst_i1 = args [1];
6412 /* OP_FREM is not IEEE compatible */
6413 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6414 MONO_INST_NEW (cfg, ins, OP_FREM);
6415 ins->inst_i0 = args [0];
6416 ins->inst_i1 = args [1];
6425 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
6427 MonoInst *ins = NULL;
6430 if (cmethod->klass == mono_defaults.math_class) {
6431 if (strcmp (cmethod->name, "Sin") == 0) {
6433 } else if (strcmp (cmethod->name, "Cos") == 0) {
6435 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
6437 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
6442 MONO_INST_NEW (cfg, ins, opcode);
6443 ins->type = STACK_R8;
6444 ins->dreg = mono_alloc_freg (cfg);
6445 ins->sreg1 = args [0]->dreg;
6446 MONO_ADD_INS (cfg->cbb, ins);
6450 if (cfg->opt & MONO_OPT_CMOV) {
6451 if (strcmp (cmethod->name, "Min") == 0) {
6452 if (fsig->params [0]->type == MONO_TYPE_I4)
6454 if (fsig->params [0]->type == MONO_TYPE_U4)
6455 opcode = OP_IMIN_UN;
6456 else if (fsig->params [0]->type == MONO_TYPE_I8)
6458 else if (fsig->params [0]->type == MONO_TYPE_U8)
6459 opcode = OP_LMIN_UN;
6460 } else if (strcmp (cmethod->name, "Max") == 0) {
6461 if (fsig->params [0]->type == MONO_TYPE_I4)
6463 if (fsig->params [0]->type == MONO_TYPE_U4)
6464 opcode = OP_IMAX_UN;
6465 else if (fsig->params [0]->type == MONO_TYPE_I8)
6467 else if (fsig->params [0]->type == MONO_TYPE_U8)
6468 opcode = OP_LMAX_UN;
6473 MONO_INST_NEW (cfg, ins, opcode);
6474 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
6475 ins->dreg = mono_alloc_ireg (cfg);
6476 ins->sreg1 = args [0]->dreg;
6477 ins->sreg2 = args [1]->dreg;
6478 MONO_ADD_INS (cfg->cbb, ins);
6482 /* OP_FREM is not IEEE compatible */
6483 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
6484 MONO_INST_NEW (cfg, ins, OP_FREM);
6485 ins->inst_i0 = args [0];
6486 ins->inst_i1 = args [1];
6492 * Can't implement CompareExchange methods this way since they have
6500 mono_arch_print_tree (MonoInst *tree, int arity)
6505 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
6509 if (appdomain_tls_offset == -1)
6512 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6513 ins->inst_offset = appdomain_tls_offset;
6517 MonoInst* mono_arch_get_thread_intrinsic (MonoCompile* cfg)
6521 if (thread_tls_offset == -1)
6524 MONO_INST_NEW (cfg, ins, OP_TLS_GET);
6525 ins->inst_offset = thread_tls_offset;
6529 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
6532 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
6535 case AMD64_RCX: return (gpointer)ctx->rcx;
6536 case AMD64_RDX: return (gpointer)ctx->rdx;
6537 case AMD64_RBX: return (gpointer)ctx->rbx;
6538 case AMD64_RBP: return (gpointer)ctx->rbp;
6539 case AMD64_RSP: return (gpointer)ctx->rsp;
6542 return _CTX_REG (ctx, rax, reg);
6544 return _CTX_REG (ctx, r12, reg - 12);
6546 g_assert_not_reached ();