2 * mini-amd64.c: AMD64 backend for the Mono code generator
7 * Paolo Molaro (lupus@ximian.com)
8 * Dietmar Maurer (dietmar@ximian.com)
10 * Zoltan Varga (vargaz@gmail.com)
12 * (C) 2003 Ximian, Inc.
13 * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
14 * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
23 #include <mono/metadata/abi-details.h>
24 #include <mono/metadata/appdomain.h>
25 #include <mono/metadata/debug-helpers.h>
26 #include <mono/metadata/threads.h>
27 #include <mono/metadata/profiler-private.h>
28 #include <mono/metadata/mono-debug.h>
29 #include <mono/metadata/gc-internals.h>
30 #include <mono/utils/mono-math.h>
31 #include <mono/utils/mono-mmap.h>
32 #include <mono/utils/mono-memory-model.h>
33 #include <mono/utils/mono-tls.h>
34 #include <mono/utils/mono-hwcap-x86.h>
35 #include <mono/utils/mono-threads.h>
39 #include "mini-amd64.h"
40 #include "cpu-amd64.h"
41 #include "debugger-agent.h"
45 static gboolean optimize_for_xen = TRUE;
47 #define optimize_for_xen 0
50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
57 /* Under windows, the calling convention is never stdcall */
58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
63 /* This mutex protects architecture specific caches */
64 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
65 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
66 static mono_mutex_t mini_arch_mutex;
68 /* The single step trampoline */
69 static gpointer ss_trampoline;
71 /* The breakpoint trampoline */
72 static gpointer bp_trampoline;
74 /* Offset between fp and the first argument in the callee */
75 #define ARGS_OFFSET 16
76 #define GP_SCRATCH_REG AMD64_R11
79 * AMD64 register usage:
80 * - callee saved registers are used for global register allocation
81 * - %r11 is used for materializing 64 bit constants in opcodes
82 * - the rest is used for local allocation
86 * Floating point comparison results:
96 mono_arch_regname (int reg)
99 case AMD64_RAX: return "%rax";
100 case AMD64_RBX: return "%rbx";
101 case AMD64_RCX: return "%rcx";
102 case AMD64_RDX: return "%rdx";
103 case AMD64_RSP: return "%rsp";
104 case AMD64_RBP: return "%rbp";
105 case AMD64_RDI: return "%rdi";
106 case AMD64_RSI: return "%rsi";
107 case AMD64_R8: return "%r8";
108 case AMD64_R9: return "%r9";
109 case AMD64_R10: return "%r10";
110 case AMD64_R11: return "%r11";
111 case AMD64_R12: return "%r12";
112 case AMD64_R13: return "%r13";
113 case AMD64_R14: return "%r14";
114 case AMD64_R15: return "%r15";
119 static const char * packed_xmmregs [] = {
120 "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
121 "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
124 static const char * single_xmmregs [] = {
125 "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
126 "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
130 mono_arch_fregname (int reg)
132 if (reg < AMD64_XMM_NREG)
133 return single_xmmregs [reg];
139 mono_arch_xregname (int reg)
141 if (reg < AMD64_XMM_NREG)
142 return packed_xmmregs [reg];
151 return mono_debug_count ();
157 static inline gboolean
158 amd64_is_near_call (guint8 *code)
161 if ((code [0] >= 0x40) && (code [0] <= 0x4f))
164 return code [0] == 0xe8;
167 static inline gboolean
168 amd64_use_imm32 (gint64 val)
170 if (mini_get_debug_options()->single_imm_size)
173 return amd64_is_imm32 (val);
176 #ifdef __native_client_codegen__
178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
179 /* for any given instruction. For instance, amd64_call_reg resolves to */
180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc. */
181 /* We only want to force bundle alignment for the top level instruction, */
182 /* so NaCl pseudo-instructions can be implemented with sub instructions. */
183 static MonoNativeTlsKey nacl_instruction_depth;
185 static MonoNativeTlsKey nacl_rex_tag;
186 static MonoNativeTlsKey nacl_legacy_prefix_tag;
189 amd64_nacl_clear_legacy_prefix_tag ()
191 mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
195 amd64_nacl_tag_legacy_prefix (guint8* code)
197 if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
198 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
202 amd64_nacl_tag_rex (guint8* code)
204 mono_native_tls_set_value (nacl_rex_tag, code);
208 amd64_nacl_get_legacy_prefix_tag ()
210 return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
214 amd64_nacl_get_rex_tag ()
216 return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
219 /* Increment the instruction "depth" described above */
221 amd64_nacl_instruction_pre ()
223 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
225 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
229 /* alignment if depth == 0 (top level instruction) */
230 /* IN: start, end pointers to instruction beginning and end */
231 /* OUT: start, end pointers to beginning and end after possible alignment */
232 /* GLOBALS: nacl_instruction_depth defined above */
234 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
236 intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
238 mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
240 g_assert ( depth >= 0 );
242 uintptr_t space_in_block;
244 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
245 /* if legacy prefix is present, and if it was emitted before */
246 /* the start of the instruction sequence, adjust the start */
247 if (prefix != NULL && prefix < *start) {
248 g_assert (*start - prefix <= 3);/* only 3 are allowed */
251 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
252 instlen = (uintptr_t)(*end - *start);
253 /* Only check for instructions which are less than */
254 /* kNaClAlignment. The only instructions that should ever */
255 /* be that long are call sequences, which are already */
256 /* padded out to align the return to the next bundle. */
257 if (instlen > space_in_block && instlen < kNaClAlignment) {
258 const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
259 guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
260 const size_t length = (size_t)((*end)-(*start));
261 g_assert (length < MAX_NACL_INST_LENGTH);
263 memcpy (copy_of_instruction, *start, length);
264 *start = mono_arch_nacl_pad (*start, space_in_block);
265 memcpy (*start, copy_of_instruction, length);
266 *end = *start + length;
268 amd64_nacl_clear_legacy_prefix_tag ();
269 amd64_nacl_tag_rex (NULL);
273 /* amd64_nacl_membase_handler: ensure all access to memory of the form */
274 /* OFFSET(%rXX) is sandboxed. For allowable base registers %rip, %rbp, */
275 /* %rsp, and %r15, emit the membase as usual. For all other registers, */
276 /* make sure the upper 32-bits are cleared, and use that register in the */
277 /* index field of a new address of this form: OFFSET(%r15,%eXX,1) */
279 /* pointer to current instruction stream (in the */
280 /* middle of an instruction, after opcode is emitted) */
281 /* basereg/offset/dreg */
282 /* operands of normal membase address */
284 /* pointer to the end of the membase/memindex emit */
285 /* GLOBALS: nacl_rex_tag */
286 /* position in instruction stream that rex prefix was emitted */
287 /* nacl_legacy_prefix_tag */
288 /* (possibly NULL) position in instruction of legacy x86 prefix */
290 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
292 gint8 true_basereg = basereg;
294 /* Cache these values, they might change */
295 /* as new instructions are emitted below. */
296 guint8* rex_tag = amd64_nacl_get_rex_tag ();
297 guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
299 /* 'basereg' is given masked to 0x7 at this point, so check */
300 /* the rex prefix to see if this is an extended register. */
301 if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
305 #define X86_LEA_OPCODE (0x8D)
307 if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
308 guint8* old_instruction_start;
310 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
311 /* 32-bits of the old base register (new index register) */
313 guint8* buf_ptr = buf;
316 g_assert (rex_tag != NULL);
318 if (IS_REX(*rex_tag)) {
319 /* The old rex.B should be the new rex.X */
320 if (*rex_tag & AMD64_REX_B) {
321 *rex_tag |= AMD64_REX_X;
323 /* Since our new base is %r15 set rex.B */
324 *rex_tag |= AMD64_REX_B;
326 /* Shift the instruction by one byte */
327 /* so we can insert a rex prefix */
328 memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
330 /* New rex prefix only needs rex.B for %r15 base */
331 *rex_tag = AMD64_REX(AMD64_REX_B);
334 if (legacy_prefix_tag) {
335 old_instruction_start = legacy_prefix_tag;
337 old_instruction_start = rex_tag;
340 /* Clears the upper 32-bits of the previous base register */
341 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
342 insert_len = buf_ptr - buf;
344 /* Move the old instruction forward to make */
345 /* room for 'mov' stored in 'buf_ptr' */
346 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
348 memcpy (old_instruction_start, buf, insert_len);
350 /* Sandboxed replacement for the normal membase_emit */
351 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
354 /* Normal default behavior, emit membase memory location */
355 x86_membase_emit_body (*code, dreg, basereg, offset);
360 static inline unsigned char*
361 amd64_skip_nops (unsigned char* code)
366 if ( code[0] == 0x90) {
370 if ( code[0] == 0x66 && code[1] == 0x90) {
374 if (code[0] == 0x0f && code[1] == 0x1f
375 && code[2] == 0x00) {
379 if (code[0] == 0x0f && code[1] == 0x1f
380 && code[2] == 0x40 && code[3] == 0x00) {
384 if (code[0] == 0x0f && code[1] == 0x1f
385 && code[2] == 0x44 && code[3] == 0x00
386 && code[4] == 0x00) {
390 if (code[0] == 0x66 && code[1] == 0x0f
391 && code[2] == 0x1f && code[3] == 0x44
392 && code[4] == 0x00 && code[5] == 0x00) {
396 if (code[0] == 0x0f && code[1] == 0x1f
397 && code[2] == 0x80 && code[3] == 0x00
398 && code[4] == 0x00 && code[5] == 0x00
399 && code[6] == 0x00) {
403 if (code[0] == 0x0f && code[1] == 0x1f
404 && code[2] == 0x84 && code[3] == 0x00
405 && code[4] == 0x00 && code[5] == 0x00
406 && code[6] == 0x00 && code[7] == 0x00) {
415 mono_arch_nacl_skip_nops (guint8* code)
417 return amd64_skip_nops(code);
420 #endif /*__native_client_codegen__*/
423 amd64_patch (unsigned char* code, gpointer target)
427 #ifdef __native_client_codegen__
428 code = amd64_skip_nops (code);
430 #if defined(__native_client_codegen__) && defined(__native_client__)
431 if (nacl_is_code_address (code)) {
432 /* For tail calls, code is patched after being installed */
433 /* but not through the normal "patch callsite" method. */
434 unsigned char buf[kNaClAlignment];
435 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
437 memcpy (buf, aligned_code, kNaClAlignment);
438 /* Patch a temp buffer of bundle size, */
439 /* then install to actual location. */
440 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
441 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
445 target = nacl_modify_patch_target (target);
449 if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
454 if ((code [0] & 0xf8) == 0xb8) {
455 /* amd64_set_reg_template */
456 *(guint64*)(code + 1) = (guint64)target;
458 else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
459 /* mov 0(%rip), %dreg */
460 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
462 else if ((code [0] == 0xff) && (code [1] == 0x15)) {
463 /* call *<OFFSET>(%rip) */
464 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
466 else if (code [0] == 0xe8) {
468 gint64 disp = (guint8*)target - (guint8*)code;
469 g_assert (amd64_is_imm32 (disp));
470 x86_patch (code, (unsigned char*)target);
473 x86_patch (code, (unsigned char*)target);
477 mono_amd64_patch (unsigned char* code, gpointer target)
479 amd64_patch (code, target);
488 ArgValuetypeAddrInIReg,
489 /* gsharedvt argument passed by addr */
492 ArgNone /* only in pair_storage */
498 ArgStorage storage : 8;
499 gboolean is_gsharedvt_return_value : 1;
501 /* Only if storage == ArgValuetypeInReg */
502 ArgStorage pair_storage [2];
504 /* The size of each pair */
507 /* Only if storage == ArgOnStack */
516 gboolean need_stack_align;
517 /* The index of the vret arg in the argument list */
524 #define DEBUG(a) if (cfg->verbose_level > 1) a
527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
533 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
539 ainfo->offset = *stack_size;
541 if (*gr >= PARAM_REGS) {
542 ainfo->storage = ArgOnStack;
543 ainfo->arg_size = sizeof (mgreg_t);
544 /* Since the same stack slot size is used for all arg */
545 /* types, it needs to be big enough to hold them all */
546 (*stack_size) += sizeof(mgreg_t);
549 ainfo->storage = ArgInIReg;
550 ainfo->reg = param_regs [*gr];
556 #define FLOAT_PARAM_REGS 4
558 #define FLOAT_PARAM_REGS 8
562 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
564 ainfo->offset = *stack_size;
566 if (*gr >= FLOAT_PARAM_REGS) {
567 ainfo->storage = ArgOnStack;
568 ainfo->arg_size = sizeof (mgreg_t);
569 /* Since the same stack slot size is used for both float */
570 /* types, it needs to be big enough to hold them both */
571 (*stack_size) += sizeof(mgreg_t);
574 /* A double register */
576 ainfo->storage = ArgInDoubleSSEReg;
578 ainfo->storage = ArgInFloatSSEReg;
584 typedef enum ArgumentClass {
592 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
594 ArgumentClass class2 = ARG_CLASS_NO_CLASS;
597 ptype = mini_get_underlying_type (type);
598 switch (ptype->type) {
607 case MONO_TYPE_STRING:
608 case MONO_TYPE_OBJECT:
609 case MONO_TYPE_CLASS:
610 case MONO_TYPE_SZARRAY:
612 case MONO_TYPE_FNPTR:
613 case MONO_TYPE_ARRAY:
616 class2 = ARG_CLASS_INTEGER;
621 class2 = ARG_CLASS_INTEGER;
623 class2 = ARG_CLASS_SSE;
627 case MONO_TYPE_TYPEDBYREF:
628 g_assert_not_reached ();
630 case MONO_TYPE_GENERICINST:
631 if (!mono_type_generic_inst_is_valuetype (ptype)) {
632 class2 = ARG_CLASS_INTEGER;
636 case MONO_TYPE_VALUETYPE: {
637 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
640 for (i = 0; i < info->num_fields; ++i) {
642 class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
647 g_assert_not_reached ();
651 if (class1 == class2)
653 else if (class1 == ARG_CLASS_NO_CLASS)
655 else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
656 class1 = ARG_CLASS_MEMORY;
657 else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
658 class1 = ARG_CLASS_INTEGER;
660 class1 = ARG_CLASS_SSE;
664 #ifdef __native_client_codegen__
666 /* Default alignment for Native Client is 32-byte. */
667 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code, */
670 /* Check that alignment doesn't cross an alignment boundary. */
672 mono_arch_nacl_pad(guint8 *code, int pad)
674 const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
676 if (pad == 0) return code;
677 /* assertion: alignment cannot cross a block boundary */
678 g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
679 (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
680 while (pad >= kMaxPadding) {
681 amd64_padding (code, kMaxPadding);
684 if (pad != 0) amd64_padding (code, pad);
690 count_fields_nested (MonoClass *klass)
692 MonoMarshalType *info;
695 info = mono_marshal_load_type_info (klass);
698 for (i = 0; i < info->num_fields; ++i) {
699 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
700 count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
708 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
710 MonoMarshalType *info;
713 info = mono_marshal_load_type_info (klass);
715 for (i = 0; i < info->num_fields; ++i) {
716 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
717 index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
719 memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
720 fields [index].offset += offset;
729 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
731 guint32 *gr, guint32 *fr, guint32 *stack_size)
733 guint32 size, i, nfields;
735 ArgumentClass arg_class;
736 MonoMarshalType *info = NULL;
737 MonoMarshalField *fields = NULL;
739 gboolean pass_on_stack = FALSE;
741 klass = mono_class_from_mono_type (type);
742 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
744 pass_on_stack = TRUE;
746 /* If this struct can't be split up naturally into 8-byte */
747 /* chunks (registers), pass it on the stack. */
748 if (sig->pinvoke && !pass_on_stack) {
752 info = mono_marshal_load_type_info (klass);
756 * Collect field information recursively to be able to
757 * handle nested structures.
759 nfields = count_fields_nested (klass);
760 fields = g_new0 (MonoMarshalField, nfields);
761 collect_field_info_nested (klass, fields, 0, 0);
763 for (i = 0; i < nfields; ++i) {
764 field_size = mono_marshal_type_size (fields [i].field->type,
766 &align, TRUE, klass->unicode);
767 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
768 pass_on_stack = TRUE;
775 /* Allways pass in memory */
776 ainfo->offset = *stack_size;
777 *stack_size += ALIGN_TO (size, 8);
778 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
780 ainfo->arg_size = ALIGN_TO (size, 8);
787 int n = mono_class_value_size (klass, NULL);
792 arg_class = ARG_CLASS_MEMORY;
794 /* Always pass in 1 integer register */
795 arg_class = ARG_CLASS_INTEGER;
800 ainfo->storage = ArgValuetypeInReg;
801 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
805 switch (info->native_size) {
806 case 1: case 2: case 4: case 8:
810 ainfo->storage = ArgValuetypeAddrInIReg;
811 ainfo->offset = *stack_size;
812 *stack_size += ALIGN_TO (info->native_size, 8);
815 ainfo->storage = ArgValuetypeAddrInIReg;
817 if (*gr < PARAM_REGS) {
818 ainfo->pair_storage [0] = ArgInIReg;
819 ainfo->pair_regs [0] = param_regs [*gr];
823 ainfo->pair_storage [0] = ArgOnStack;
824 ainfo->offset = *stack_size;
825 ainfo->arg_size = sizeof (mgreg_t);
836 ArgumentClass class1;
839 class1 = ARG_CLASS_MEMORY;
841 class1 = ARG_CLASS_NO_CLASS;
842 for (i = 0; i < nfields; ++i) {
843 size = mono_marshal_type_size (fields [i].field->type,
845 &align, TRUE, klass->unicode);
846 /* How far into this quad this data extends.*/
847 /* (8 is size of quad) */
848 argsize = fields [i].offset + size;
850 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
852 g_assert (class1 != ARG_CLASS_NO_CLASS);
858 /* Allocate registers */
863 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
866 ainfo->storage = ArgValuetypeInReg;
867 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
868 ainfo->pair_size [0] = argsize;
869 ainfo->pair_size [1] = 0;
872 case ARG_CLASS_INTEGER:
873 if (*gr >= PARAM_REGS)
874 arg_class = ARG_CLASS_MEMORY;
876 ainfo->pair_storage [0] = ArgInIReg;
878 ainfo->pair_regs [0] = return_regs [*gr];
880 ainfo->pair_regs [0] = param_regs [*gr];
885 if (*fr >= FLOAT_PARAM_REGS)
886 arg_class = ARG_CLASS_MEMORY;
889 ainfo->pair_storage [0] = ArgInFloatSSEReg;
891 ainfo->pair_storage [0] = ArgInDoubleSSEReg;
892 ainfo->pair_regs [0] = *fr;
896 case ARG_CLASS_MEMORY:
899 g_assert_not_reached ();
902 if (arg_class == ARG_CLASS_MEMORY) {
903 /* Revert possible register assignments */
907 ainfo->offset = *stack_size;
908 *stack_size += sizeof (mgreg_t);
909 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
911 ainfo->arg_size = sizeof (mgreg_t);
915 #endif /* TARGET_WIN32 */
918 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
920 guint32 *gr, guint32 *fr, guint32 *stack_size)
923 add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
925 guint32 size, quad, nquads, i, nfields;
926 /* Keep track of the size used in each quad so we can */
927 /* use the right size when copying args/return vars. */
928 guint32 quadsize [2] = {8, 8};
929 ArgumentClass args [2];
930 MonoMarshalType *info = NULL;
931 MonoMarshalField *fields = NULL;
933 gboolean pass_on_stack = FALSE;
935 klass = mono_class_from_mono_type (type);
936 size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
937 if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
938 /* We pass and return vtypes of size 8 in a register */
939 } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
940 pass_on_stack = TRUE;
943 /* If this struct can't be split up naturally into 8-byte */
944 /* chunks (registers), pass it on the stack. */
945 if (sig->pinvoke && !pass_on_stack) {
949 info = mono_marshal_load_type_info (klass);
953 * Collect field information recursively to be able to
954 * handle nested structures.
956 nfields = count_fields_nested (klass);
957 fields = g_new0 (MonoMarshalField, nfields);
958 collect_field_info_nested (klass, fields, 0, 0);
960 for (i = 0; i < nfields; ++i) {
961 field_size = mono_marshal_type_size (fields [i].field->type,
963 &align, TRUE, klass->unicode);
964 if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
965 pass_on_stack = TRUE;
972 ainfo->storage = ArgValuetypeInReg;
973 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
978 /* Allways pass in memory */
979 ainfo->offset = *stack_size;
980 *stack_size += ALIGN_TO (size, 8);
981 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
983 ainfo->arg_size = ALIGN_TO (size, 8);
995 int n = mono_class_value_size (klass, NULL);
997 quadsize [0] = n >= 8 ? 8 : n;
998 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
1000 /* Always pass in 1 or 2 integer registers */
1001 args [0] = ARG_CLASS_INTEGER;
1002 args [1] = ARG_CLASS_INTEGER;
1003 /* Only the simplest cases are supported */
1004 if (is_return && nquads != 1) {
1005 args [0] = ARG_CLASS_MEMORY;
1006 args [1] = ARG_CLASS_MEMORY;
1010 * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
1011 * The X87 and SSEUP stuff is left out since there are no such types in
1017 ainfo->storage = ArgValuetypeInReg;
1018 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1022 if (info->native_size > 16) {
1023 ainfo->offset = *stack_size;
1024 *stack_size += ALIGN_TO (info->native_size, 8);
1025 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1027 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
1033 args [0] = ARG_CLASS_NO_CLASS;
1034 args [1] = ARG_CLASS_NO_CLASS;
1035 for (quad = 0; quad < nquads; ++quad) {
1038 ArgumentClass class1;
1041 class1 = ARG_CLASS_MEMORY;
1043 class1 = ARG_CLASS_NO_CLASS;
1044 for (i = 0; i < nfields; ++i) {
1045 size = mono_marshal_type_size (fields [i].field->type,
1047 &align, TRUE, klass->unicode);
1048 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
1049 /* Unaligned field */
1053 /* Skip fields in other quad */
1054 if ((quad == 0) && (fields [i].offset >= 8))
1056 if ((quad == 1) && (fields [i].offset < 8))
1059 /* How far into this quad this data extends.*/
1060 /* (8 is size of quad) */
1061 quadsize [quad] = fields [i].offset + size - (quad * 8);
1063 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1065 g_assert (class1 != ARG_CLASS_NO_CLASS);
1066 args [quad] = class1;
1072 /* Post merger cleanup */
1073 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1074 args [0] = args [1] = ARG_CLASS_MEMORY;
1076 /* Allocate registers */
1081 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1083 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1086 ainfo->storage = ArgValuetypeInReg;
1087 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1088 g_assert (quadsize [0] <= 8);
1089 g_assert (quadsize [1] <= 8);
1090 ainfo->pair_size [0] = quadsize [0];
1091 ainfo->pair_size [1] = quadsize [1];
1092 ainfo->nregs = nquads;
1093 for (quad = 0; quad < nquads; ++quad) {
1094 switch (args [quad]) {
1095 case ARG_CLASS_INTEGER:
1096 if (*gr >= PARAM_REGS)
1097 args [quad] = ARG_CLASS_MEMORY;
1099 ainfo->pair_storage [quad] = ArgInIReg;
1101 ainfo->pair_regs [quad] = return_regs [*gr];
1103 ainfo->pair_regs [quad] = param_regs [*gr];
1108 if (*fr >= FLOAT_PARAM_REGS)
1109 args [quad] = ARG_CLASS_MEMORY;
1111 if (quadsize[quad] <= 4)
1112 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1113 else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1114 ainfo->pair_regs [quad] = *fr;
1118 case ARG_CLASS_MEMORY:
1121 g_assert_not_reached ();
1125 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1127 /* Revert possible register assignments */
1131 ainfo->offset = *stack_size;
1133 arg_size = ALIGN_TO (info->native_size, 8);
1135 arg_size = nquads * sizeof(mgreg_t);
1136 *stack_size += arg_size;
1137 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1139 ainfo->arg_size = arg_size;
1142 #endif /* !TARGET_WIN32 */
1148 * Obtain information about a call according to the calling convention.
1149 * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1150 * Draft Version 0.23" document for more information.
1153 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1155 guint32 i, gr, fr, pstart;
1157 int n = sig->hasthis + sig->param_count;
1158 guint32 stack_size = 0;
1160 gboolean is_pinvoke = sig->pinvoke;
1163 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1165 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1173 /* Reserve space where the callee can save the argument registers */
1174 stack_size = 4 * sizeof (mgreg_t);
1178 ret_type = mini_get_underlying_type (sig->ret);
1179 switch (ret_type->type) {
1189 case MONO_TYPE_FNPTR:
1190 case MONO_TYPE_CLASS:
1191 case MONO_TYPE_OBJECT:
1192 case MONO_TYPE_SZARRAY:
1193 case MONO_TYPE_ARRAY:
1194 case MONO_TYPE_STRING:
1195 cinfo->ret.storage = ArgInIReg;
1196 cinfo->ret.reg = AMD64_RAX;
1200 cinfo->ret.storage = ArgInIReg;
1201 cinfo->ret.reg = AMD64_RAX;
1204 cinfo->ret.storage = ArgInFloatSSEReg;
1205 cinfo->ret.reg = AMD64_XMM0;
1208 cinfo->ret.storage = ArgInDoubleSSEReg;
1209 cinfo->ret.reg = AMD64_XMM0;
1211 case MONO_TYPE_GENERICINST:
1212 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1213 cinfo->ret.storage = ArgInIReg;
1214 cinfo->ret.reg = AMD64_RAX;
1217 if (mini_is_gsharedvt_type (ret_type)) {
1218 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1219 cinfo->ret.is_gsharedvt_return_value = 1;
1223 case MONO_TYPE_VALUETYPE:
1224 case MONO_TYPE_TYPEDBYREF: {
1225 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1227 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1228 g_assert (cinfo->ret.storage != ArgInIReg);
1232 case MONO_TYPE_MVAR:
1233 g_assert (mini_is_gsharedvt_type (ret_type));
1234 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1235 cinfo->ret.is_gsharedvt_return_value = 1;
1237 case MONO_TYPE_VOID:
1240 g_error ("Can't handle as return value 0x%x", ret_type->type);
1245 * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1246 * the first argument, allowing 'this' to be always passed in the first arg reg.
1247 * Also do this if the first argument is a reference type, since virtual calls
1248 * are sometimes made using calli without sig->hasthis set, like in the delegate
1251 if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1253 add_general (&gr, &stack_size, cinfo->args + 0);
1255 add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1258 add_general (&gr, &stack_size, &cinfo->ret);
1259 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1260 cinfo->vret_arg_index = 1;
1264 add_general (&gr, &stack_size, cinfo->args + 0);
1266 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1267 add_general (&gr, &stack_size, &cinfo->ret);
1268 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1272 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1274 fr = FLOAT_PARAM_REGS;
1276 /* Emit the signature cookie just before the implicit arguments */
1277 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1280 for (i = pstart; i < sig->param_count; ++i) {
1281 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1285 /* The float param registers and other param registers must be the same index on Windows x64.*/
1292 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1293 /* We allways pass the sig cookie on the stack for simplicity */
1295 * Prevent implicit arguments + the sig cookie from being passed
1299 fr = FLOAT_PARAM_REGS;
1301 /* Emit the signature cookie just before the implicit arguments */
1302 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1305 ptype = mini_get_underlying_type (sig->params [i]);
1306 switch (ptype->type) {
1309 add_general (&gr, &stack_size, ainfo);
1313 add_general (&gr, &stack_size, ainfo);
1317 add_general (&gr, &stack_size, ainfo);
1322 case MONO_TYPE_FNPTR:
1323 case MONO_TYPE_CLASS:
1324 case MONO_TYPE_OBJECT:
1325 case MONO_TYPE_STRING:
1326 case MONO_TYPE_SZARRAY:
1327 case MONO_TYPE_ARRAY:
1328 add_general (&gr, &stack_size, ainfo);
1330 case MONO_TYPE_GENERICINST:
1331 if (!mono_type_generic_inst_is_valuetype (ptype)) {
1332 add_general (&gr, &stack_size, ainfo);
1335 if (mini_is_gsharedvt_variable_type (ptype)) {
1336 /* gsharedvt arguments are passed by ref */
1337 add_general (&gr, &stack_size, ainfo);
1338 if (ainfo->storage == ArgInIReg)
1339 ainfo->storage = ArgGSharedVtInReg;
1341 ainfo->storage = ArgGSharedVtOnStack;
1345 case MONO_TYPE_VALUETYPE:
1346 case MONO_TYPE_TYPEDBYREF:
1347 add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1352 add_general (&gr, &stack_size, ainfo);
1355 add_float (&fr, &stack_size, ainfo, FALSE);
1358 add_float (&fr, &stack_size, ainfo, TRUE);
1361 case MONO_TYPE_MVAR:
1362 /* gsharedvt arguments are passed by ref */
1363 g_assert (mini_is_gsharedvt_type (ptype));
1364 add_general (&gr, &stack_size, ainfo);
1365 if (ainfo->storage == ArgInIReg)
1366 ainfo->storage = ArgGSharedVtInReg;
1368 ainfo->storage = ArgGSharedVtOnStack;
1371 g_assert_not_reached ();
1375 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1377 fr = FLOAT_PARAM_REGS;
1379 /* Emit the signature cookie just before the implicit arguments */
1380 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1383 cinfo->stack_usage = stack_size;
1384 cinfo->reg_usage = gr;
1385 cinfo->freg_usage = fr;
1390 * mono_arch_get_argument_info:
1391 * @csig: a method signature
1392 * @param_count: the number of parameters to consider
1393 * @arg_info: an array to store the result infos
1395 * Gathers information on parameters such as size, alignment and
1396 * padding. arg_info should be large enought to hold param_count + 1 entries.
1398 * Returns the size of the argument area on the stack.
1401 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1404 CallInfo *cinfo = get_call_info (NULL, csig);
1405 guint32 args_size = cinfo->stack_usage;
1407 /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1408 if (csig->hasthis) {
1409 arg_info [0].offset = 0;
1412 for (k = 0; k < param_count; k++) {
1413 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1415 arg_info [k + 1].size = 0;
1424 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1428 MonoType *callee_ret;
1430 c1 = get_call_info (NULL, caller_sig);
1431 c2 = get_call_info (NULL, callee_sig);
1432 res = c1->stack_usage >= c2->stack_usage;
1433 callee_ret = mini_get_underlying_type (callee_sig->ret);
1434 if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1435 /* An address on the callee's stack is passed as the first argument */
1445 * Initialize the cpu to execute managed code.
1448 mono_arch_cpu_init (void)
1453 /* spec compliance requires running with double precision */
1454 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1455 fpcw &= ~X86_FPCW_PRECC_MASK;
1456 fpcw |= X86_FPCW_PREC_DOUBLE;
1457 __asm__ __volatile__ ("fldcw %0\n": : "m" (fpcw));
1458 __asm__ __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1460 /* TODO: This is crashing on Win64 right now.
1461 * _control87 (_PC_53, MCW_PC);
1467 * Initialize architecture specific code.
1470 mono_arch_init (void)
1472 mono_os_mutex_init_recursive (&mini_arch_mutex);
1473 #if defined(__native_client_codegen__)
1474 mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1475 mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1476 mono_native_tls_alloc (&nacl_rex_tag, NULL);
1477 mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1480 mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1481 mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1482 mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1483 mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1484 #if defined(ENABLE_GSHAREDVT)
1485 mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1489 bp_trampoline = mini_get_breakpoint_trampoline ();
1493 * Cleanup architecture specific code.
1496 mono_arch_cleanup (void)
1498 mono_os_mutex_destroy (&mini_arch_mutex);
1499 #if defined(__native_client_codegen__)
1500 mono_native_tls_free (nacl_instruction_depth);
1501 mono_native_tls_free (nacl_rex_tag);
1502 mono_native_tls_free (nacl_legacy_prefix_tag);
1507 * This function returns the optimizations supported on this cpu.
1510 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1516 if (mono_hwcap_x86_has_cmov) {
1517 opts |= MONO_OPT_CMOV;
1519 if (mono_hwcap_x86_has_fcmov)
1520 opts |= MONO_OPT_FCMOV;
1522 *exclude_mask |= MONO_OPT_FCMOV;
1524 *exclude_mask |= MONO_OPT_CMOV;
1531 * This function test for all SSE functions supported.
1533 * Returns a bitmask corresponding to all supported versions.
1537 mono_arch_cpu_enumerate_simd_versions (void)
1539 guint32 sse_opts = 0;
1541 if (mono_hwcap_x86_has_sse1)
1542 sse_opts |= SIMD_VERSION_SSE1;
1544 if (mono_hwcap_x86_has_sse2)
1545 sse_opts |= SIMD_VERSION_SSE2;
1547 if (mono_hwcap_x86_has_sse3)
1548 sse_opts |= SIMD_VERSION_SSE3;
1550 if (mono_hwcap_x86_has_ssse3)
1551 sse_opts |= SIMD_VERSION_SSSE3;
1553 if (mono_hwcap_x86_has_sse41)
1554 sse_opts |= SIMD_VERSION_SSE41;
1556 if (mono_hwcap_x86_has_sse42)
1557 sse_opts |= SIMD_VERSION_SSE42;
1559 if (mono_hwcap_x86_has_sse4a)
1560 sse_opts |= SIMD_VERSION_SSE4a;
1568 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1573 for (i = 0; i < cfg->num_varinfo; i++) {
1574 MonoInst *ins = cfg->varinfo [i];
1575 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1578 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1581 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1582 (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1585 if (mono_is_regsize_var (ins->inst_vtype)) {
1586 g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1587 g_assert (i == vmv->idx);
1588 vars = g_list_prepend (vars, vmv);
1592 vars = mono_varlist_sort (cfg, vars, 0);
1598 * mono_arch_compute_omit_fp:
1600 * Determine whenever the frame pointer can be eliminated.
1603 mono_arch_compute_omit_fp (MonoCompile *cfg)
1605 MonoMethodSignature *sig;
1606 MonoMethodHeader *header;
1610 if (cfg->arch.omit_fp_computed)
1613 header = cfg->header;
1615 sig = mono_method_signature (cfg->method);
1617 if (!cfg->arch.cinfo)
1618 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1619 cinfo = (CallInfo *)cfg->arch.cinfo;
1622 * FIXME: Remove some of the restrictions.
1624 cfg->arch.omit_fp = TRUE;
1625 cfg->arch.omit_fp_computed = TRUE;
1627 #ifdef __native_client_codegen__
1628 /* NaCl modules may not change the value of RBP, so it cannot be */
1629 /* used as a normal register, but it can be used as a frame pointer*/
1630 cfg->disable_omit_fp = TRUE;
1631 cfg->arch.omit_fp = FALSE;
1634 if (cfg->disable_omit_fp)
1635 cfg->arch.omit_fp = FALSE;
1637 if (!debug_omit_fp ())
1638 cfg->arch.omit_fp = FALSE;
1640 if (cfg->method->save_lmf)
1641 cfg->arch.omit_fp = FALSE;
1643 if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1644 cfg->arch.omit_fp = FALSE;
1645 if (header->num_clauses)
1646 cfg->arch.omit_fp = FALSE;
1647 if (cfg->param_area)
1648 cfg->arch.omit_fp = FALSE;
1649 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1650 cfg->arch.omit_fp = FALSE;
1651 if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1652 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1653 cfg->arch.omit_fp = FALSE;
1654 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1655 ArgInfo *ainfo = &cinfo->args [i];
1657 if (ainfo->storage == ArgOnStack) {
1659 * The stack offset can only be determined when the frame
1662 cfg->arch.omit_fp = FALSE;
1667 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1668 MonoInst *ins = cfg->varinfo [i];
1671 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1676 mono_arch_get_global_int_regs (MonoCompile *cfg)
1680 mono_arch_compute_omit_fp (cfg);
1682 if (cfg->arch.omit_fp)
1683 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1685 /* We use the callee saved registers for global allocation */
1686 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1687 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1688 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1689 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1690 #ifndef __native_client_codegen__
1691 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1694 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1695 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1702 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1707 /* All XMM registers */
1708 for (i = 0; i < 16; ++i)
1709 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1715 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1717 static GList *r = NULL;
1722 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1723 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1724 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1725 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1726 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1727 #ifndef __native_client_codegen__
1728 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1731 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1732 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1733 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1734 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1735 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1736 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1737 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1738 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1740 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1747 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1750 static GList *r = NULL;
1755 for (i = 0; i < AMD64_XMM_NREG; ++i)
1756 regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1758 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1765 * mono_arch_regalloc_cost:
1767 * Return the cost, in number of memory references, of the action of
1768 * allocating the variable VMV into a register during global register
1772 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1774 MonoInst *ins = cfg->varinfo [vmv->idx];
1776 if (cfg->method->save_lmf)
1777 /* The register is already saved */
1778 /* substract 1 for the invisible store in the prolog */
1779 return (ins->opcode == OP_ARG) ? 0 : 1;
1782 return (ins->opcode == OP_ARG) ? 1 : 2;
1786 * mono_arch_fill_argument_info:
1788 * Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1792 mono_arch_fill_argument_info (MonoCompile *cfg)
1795 MonoMethodSignature *sig;
1800 sig = mono_method_signature (cfg->method);
1802 cinfo = (CallInfo *)cfg->arch.cinfo;
1803 sig_ret = mini_get_underlying_type (sig->ret);
1806 * Contrary to mono_arch_allocate_vars (), the information should describe
1807 * where the arguments are at the beginning of the method, not where they can be
1808 * accessed during the execution of the method. The later makes no sense for the
1809 * global register allocator, since a variable can be in more than one location.
1811 switch (cinfo->ret.storage) {
1813 case ArgInFloatSSEReg:
1814 case ArgInDoubleSSEReg:
1815 cfg->ret->opcode = OP_REGVAR;
1816 cfg->ret->inst_c0 = cinfo->ret.reg;
1818 case ArgValuetypeInReg:
1819 cfg->ret->opcode = OP_REGOFFSET;
1820 cfg->ret->inst_basereg = -1;
1821 cfg->ret->inst_offset = -1;
1826 g_assert_not_reached ();
1829 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1830 ArgInfo *ainfo = &cinfo->args [i];
1832 ins = cfg->args [i];
1834 switch (ainfo->storage) {
1836 case ArgInFloatSSEReg:
1837 case ArgInDoubleSSEReg:
1838 ins->opcode = OP_REGVAR;
1839 ins->inst_c0 = ainfo->reg;
1842 ins->opcode = OP_REGOFFSET;
1843 ins->inst_basereg = -1;
1844 ins->inst_offset = -1;
1846 case ArgValuetypeInReg:
1848 ins->opcode = OP_NOP;
1851 g_assert_not_reached ();
1857 mono_arch_allocate_vars (MonoCompile *cfg)
1860 MonoMethodSignature *sig;
1863 guint32 locals_stack_size, locals_stack_align;
1867 sig = mono_method_signature (cfg->method);
1869 cinfo = (CallInfo *)cfg->arch.cinfo;
1870 sig_ret = mini_get_underlying_type (sig->ret);
1872 mono_arch_compute_omit_fp (cfg);
1875 * We use the ABI calling conventions for managed code as well.
1876 * Exception: valuetypes are only sometimes passed or returned in registers.
1880 * The stack looks like this:
1881 * <incoming arguments passed on the stack>
1883 * <lmf/caller saved registers>
1886 * <localloc area> -> grows dynamically
1890 if (cfg->arch.omit_fp) {
1891 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1892 cfg->frame_reg = AMD64_RSP;
1895 /* Locals are allocated backwards from %fp */
1896 cfg->frame_reg = AMD64_RBP;
1900 cfg->arch.saved_iregs = cfg->used_int_regs;
1901 if (cfg->method->save_lmf)
1902 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1903 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1905 if (cfg->arch.omit_fp)
1906 cfg->arch.reg_save_area_offset = offset;
1907 /* Reserve space for callee saved registers */
1908 for (i = 0; i < AMD64_NREG; ++i)
1909 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1910 offset += sizeof(mgreg_t);
1912 if (!cfg->arch.omit_fp)
1913 cfg->arch.reg_save_area_offset = -offset;
1915 if (sig_ret->type != MONO_TYPE_VOID) {
1916 switch (cinfo->ret.storage) {
1918 case ArgInFloatSSEReg:
1919 case ArgInDoubleSSEReg:
1920 cfg->ret->opcode = OP_REGVAR;
1921 cfg->ret->inst_c0 = cinfo->ret.reg;
1922 cfg->ret->dreg = cinfo->ret.reg;
1924 case ArgValuetypeAddrInIReg:
1925 /* The register is volatile */
1926 cfg->vret_addr->opcode = OP_REGOFFSET;
1927 cfg->vret_addr->inst_basereg = cfg->frame_reg;
1928 if (cfg->arch.omit_fp) {
1929 cfg->vret_addr->inst_offset = offset;
1933 cfg->vret_addr->inst_offset = -offset;
1935 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1936 printf ("vret_addr =");
1937 mono_print_ins (cfg->vret_addr);
1940 case ArgValuetypeInReg:
1941 /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1942 cfg->ret->opcode = OP_REGOFFSET;
1943 cfg->ret->inst_basereg = cfg->frame_reg;
1944 if (cfg->arch.omit_fp) {
1945 cfg->ret->inst_offset = offset;
1946 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1948 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1949 cfg->ret->inst_offset = - offset;
1953 g_assert_not_reached ();
1957 /* Allocate locals */
1958 offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1959 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1960 char *mname = mono_method_full_name (cfg->method, TRUE);
1961 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1962 cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1967 if (locals_stack_align) {
1968 offset += (locals_stack_align - 1);
1969 offset &= ~(locals_stack_align - 1);
1971 if (cfg->arch.omit_fp) {
1972 cfg->locals_min_stack_offset = offset;
1973 cfg->locals_max_stack_offset = offset + locals_stack_size;
1975 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1976 cfg->locals_max_stack_offset = - offset;
1979 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1980 if (offsets [i] != -1) {
1981 MonoInst *ins = cfg->varinfo [i];
1982 ins->opcode = OP_REGOFFSET;
1983 ins->inst_basereg = cfg->frame_reg;
1984 if (cfg->arch.omit_fp)
1985 ins->inst_offset = (offset + offsets [i]);
1987 ins->inst_offset = - (offset + offsets [i]);
1988 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1991 offset += locals_stack_size;
1993 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1994 g_assert (!cfg->arch.omit_fp);
1995 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1996 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1999 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
2000 ins = cfg->args [i];
2001 if (ins->opcode != OP_REGVAR) {
2002 ArgInfo *ainfo = &cinfo->args [i];
2003 gboolean inreg = TRUE;
2005 /* FIXME: Allocate volatile arguments to registers */
2006 if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
2010 * Under AMD64, all registers used to pass arguments to functions
2011 * are volatile across calls.
2012 * FIXME: Optimize this.
2014 if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
2017 ins->opcode = OP_REGOFFSET;
2019 switch (ainfo->storage) {
2021 case ArgInFloatSSEReg:
2022 case ArgInDoubleSSEReg:
2023 case ArgGSharedVtInReg:
2025 ins->opcode = OP_REGVAR;
2026 ins->dreg = ainfo->reg;
2030 case ArgGSharedVtOnStack:
2031 g_assert (!cfg->arch.omit_fp);
2032 ins->opcode = OP_REGOFFSET;
2033 ins->inst_basereg = cfg->frame_reg;
2034 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
2036 case ArgValuetypeInReg:
2038 case ArgValuetypeAddrInIReg: {
2040 g_assert (!cfg->arch.omit_fp);
2042 MONO_INST_NEW (cfg, indir, 0);
2043 indir->opcode = OP_REGOFFSET;
2044 if (ainfo->pair_storage [0] == ArgInIReg) {
2045 indir->inst_basereg = cfg->frame_reg;
2046 offset = ALIGN_TO (offset, sizeof (gpointer));
2047 offset += (sizeof (gpointer));
2048 indir->inst_offset = - offset;
2051 indir->inst_basereg = cfg->frame_reg;
2052 indir->inst_offset = ainfo->offset + ARGS_OFFSET;
2055 ins->opcode = OP_VTARG_ADDR;
2056 ins->inst_left = indir;
2064 if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
2065 ins->opcode = OP_REGOFFSET;
2066 ins->inst_basereg = cfg->frame_reg;
2067 /* These arguments are saved to the stack in the prolog */
2068 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2069 if (cfg->arch.omit_fp) {
2070 ins->inst_offset = offset;
2071 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2072 // Arguments are yet supported by the stack map creation code
2073 //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2075 offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2076 ins->inst_offset = - offset;
2077 //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2083 cfg->stack_offset = offset;
2087 mono_arch_create_vars (MonoCompile *cfg)
2089 MonoMethodSignature *sig;
2093 sig = mono_method_signature (cfg->method);
2095 if (!cfg->arch.cinfo)
2096 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2097 cinfo = (CallInfo *)cfg->arch.cinfo;
2099 if (cinfo->ret.storage == ArgValuetypeInReg)
2100 cfg->ret_var_is_local = TRUE;
2102 sig_ret = mini_get_underlying_type (sig->ret);
2103 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2104 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2105 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2106 printf ("vret_addr = ");
2107 mono_print_ins (cfg->vret_addr);
2111 if (cfg->gen_sdb_seq_points) {
2114 if (cfg->compile_aot) {
2115 MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2116 ins->flags |= MONO_INST_VOLATILE;
2117 cfg->arch.seq_point_info_var = ins;
2119 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2120 ins->flags |= MONO_INST_VOLATILE;
2121 cfg->arch.ss_tramp_var = ins;
2123 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2124 ins->flags |= MONO_INST_VOLATILE;
2125 cfg->arch.bp_tramp_var = ins;
2128 if (cfg->method->save_lmf)
2129 cfg->create_lmf_var = TRUE;
2131 if (cfg->method->save_lmf) {
2133 #if !defined(TARGET_WIN32)
2134 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2135 cfg->lmf_ir_mono_lmf = TRUE;
2141 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2147 MONO_INST_NEW (cfg, ins, OP_MOVE);
2148 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2149 ins->sreg1 = tree->dreg;
2150 MONO_ADD_INS (cfg->cbb, ins);
2151 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2153 case ArgInFloatSSEReg:
2154 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2155 ins->dreg = mono_alloc_freg (cfg);
2156 ins->sreg1 = tree->dreg;
2157 MONO_ADD_INS (cfg->cbb, ins);
2159 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2161 case ArgInDoubleSSEReg:
2162 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2163 ins->dreg = mono_alloc_freg (cfg);
2164 ins->sreg1 = tree->dreg;
2165 MONO_ADD_INS (cfg->cbb, ins);
2167 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2171 g_assert_not_reached ();
2176 arg_storage_to_load_membase (ArgStorage storage)
2180 #if defined(__mono_ilp32__)
2181 return OP_LOADI8_MEMBASE;
2183 return OP_LOAD_MEMBASE;
2185 case ArgInDoubleSSEReg:
2186 return OP_LOADR8_MEMBASE;
2187 case ArgInFloatSSEReg:
2188 return OP_LOADR4_MEMBASE;
2190 g_assert_not_reached ();
2197 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2199 MonoMethodSignature *tmp_sig;
2202 if (call->tail_call)
2205 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2208 * mono_ArgIterator_Setup assumes the signature cookie is
2209 * passed first and all the arguments which were before it are
2210 * passed on the stack after the signature. So compensate by
2211 * passing a different signature.
2213 tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2214 tmp_sig->param_count -= call->signature->sentinelpos;
2215 tmp_sig->sentinelpos = 0;
2216 memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2218 sig_reg = mono_alloc_ireg (cfg);
2219 MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2221 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2225 static inline LLVMArgStorage
2226 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2230 return LLVMArgInIReg;
2233 case ArgGSharedVtInReg:
2234 case ArgGSharedVtOnStack:
2235 return LLVMArgGSharedVt;
2237 g_assert_not_reached ();
2243 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2249 LLVMCallInfo *linfo;
2250 MonoType *t, *sig_ret;
2252 n = sig->param_count + sig->hasthis;
2253 sig_ret = mini_get_underlying_type (sig->ret);
2255 cinfo = get_call_info (cfg->mempool, sig);
2257 linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2260 * LLVM always uses the native ABI while we use our own ABI, the
2261 * only difference is the handling of vtypes:
2262 * - we only pass/receive them in registers in some cases, and only
2263 * in 1 or 2 integer registers.
2265 switch (cinfo->ret.storage) {
2267 linfo->ret.storage = LLVMArgNone;
2270 case ArgInFloatSSEReg:
2271 case ArgInDoubleSSEReg:
2272 linfo->ret.storage = LLVMArgNormal;
2274 case ArgValuetypeInReg: {
2275 ainfo = &cinfo->ret;
2278 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2279 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2280 cfg->exception_message = g_strdup ("pinvoke + vtype ret");
2281 cfg->disable_llvm = TRUE;
2285 linfo->ret.storage = LLVMArgVtypeInReg;
2286 for (j = 0; j < 2; ++j)
2287 linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2290 case ArgValuetypeAddrInIReg:
2291 /* Vtype returned using a hidden argument */
2292 linfo->ret.storage = LLVMArgVtypeRetAddr;
2293 linfo->vret_arg_index = cinfo->vret_arg_index;
2296 g_assert_not_reached ();
2300 for (i = 0; i < n; ++i) {
2301 ainfo = cinfo->args + i;
2303 if (i >= sig->hasthis)
2304 t = sig->params [i - sig->hasthis];
2306 t = &mono_defaults.int_class->byval_arg;
2308 linfo->args [i].storage = LLVMArgNone;
2310 switch (ainfo->storage) {
2312 linfo->args [i].storage = LLVMArgNormal;
2314 case ArgInDoubleSSEReg:
2315 case ArgInFloatSSEReg:
2316 linfo->args [i].storage = LLVMArgNormal;
2319 if (MONO_TYPE_ISSTRUCT (t))
2320 linfo->args [i].storage = LLVMArgVtypeByVal;
2322 linfo->args [i].storage = LLVMArgNormal;
2324 case ArgValuetypeInReg:
2326 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2327 ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2328 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2329 cfg->disable_llvm = TRUE;
2333 linfo->args [i].storage = LLVMArgVtypeInReg;
2334 for (j = 0; j < 2; ++j)
2335 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2337 case ArgGSharedVtInReg:
2338 case ArgGSharedVtOnStack:
2339 linfo->args [i].storage = LLVMArgGSharedVt;
2342 cfg->exception_message = g_strdup ("ainfo->storage");
2343 cfg->disable_llvm = TRUE;
2353 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2356 MonoMethodSignature *sig;
2362 sig = call->signature;
2363 n = sig->param_count + sig->hasthis;
2365 cinfo = get_call_info (cfg->mempool, sig);
2369 if (COMPILE_LLVM (cfg)) {
2370 /* We shouldn't be called in the llvm case */
2371 cfg->disable_llvm = TRUE;
2376 * Emit all arguments which are passed on the stack to prevent register
2377 * allocation problems.
2379 for (i = 0; i < n; ++i) {
2381 ainfo = cinfo->args + i;
2383 in = call->args [i];
2385 if (sig->hasthis && i == 0)
2386 t = &mono_defaults.object_class->byval_arg;
2388 t = sig->params [i - sig->hasthis];
2390 t = mini_get_underlying_type (t);
2391 //XXX what about ArgGSharedVtOnStack here?
2392 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2394 if (t->type == MONO_TYPE_R4)
2395 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2396 else if (t->type == MONO_TYPE_R8)
2397 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2399 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2401 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2403 if (cfg->compute_gc_maps) {
2406 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2412 * Emit all parameters passed in registers in non-reverse order for better readability
2413 * and to help the optimization in emit_prolog ().
2415 for (i = 0; i < n; ++i) {
2416 ainfo = cinfo->args + i;
2418 in = call->args [i];
2420 if (ainfo->storage == ArgInIReg)
2421 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2424 for (i = n - 1; i >= 0; --i) {
2427 ainfo = cinfo->args + i;
2429 in = call->args [i];
2431 if (sig->hasthis && i == 0)
2432 t = &mono_defaults.object_class->byval_arg;
2434 t = sig->params [i - sig->hasthis];
2435 t = mini_get_underlying_type (t);
2437 switch (ainfo->storage) {
2441 case ArgInFloatSSEReg:
2442 case ArgInDoubleSSEReg:
2443 add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2446 case ArgValuetypeInReg:
2447 case ArgValuetypeAddrInIReg:
2448 case ArgGSharedVtInReg:
2449 case ArgGSharedVtOnStack: {
2450 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2451 /* Already emitted above */
2453 //FIXME what about ArgGSharedVtOnStack ?
2454 if (ainfo->storage == ArgOnStack && call->tail_call) {
2455 MonoInst *call_inst = (MonoInst*)call;
2456 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2457 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2465 size = mono_type_native_stack_size (t, &align);
2468 * Other backends use mono_type_stack_size (), but that
2469 * aligns the size to 8, which is larger than the size of
2470 * the source, leading to reads of invalid memory if the
2471 * source is at the end of address space.
2473 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2476 if (size >= 10000) {
2477 /* Avoid asserts in emit_memcpy () */
2478 cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
2479 cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
2480 /* Continue normally */
2484 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2485 arg->sreg1 = in->dreg;
2486 arg->klass = mono_class_from_mono_type (t);
2487 arg->backend.size = size;
2488 arg->inst_p0 = call;
2489 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2490 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2492 MONO_ADD_INS (cfg->cbb, arg);
2497 g_assert_not_reached ();
2500 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2501 /* Emit the signature cookie just before the implicit arguments */
2502 emit_sig_cookie (cfg, call, cinfo);
2505 /* Handle the case where there are no implicit arguments */
2506 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2507 emit_sig_cookie (cfg, call, cinfo);
2509 switch (cinfo->ret.storage) {
2510 case ArgValuetypeInReg:
2511 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2513 * Tell the JIT to use a more efficient calling convention: call using
2514 * OP_CALL, compute the result location after the call, and save the
2517 call->vret_in_reg = TRUE;
2519 * Nullify the instruction computing the vret addr to enable
2520 * future optimizations.
2523 NULLIFY_INS (call->vret_var);
2525 if (call->tail_call)
2528 * The valuetype is in RAX:RDX after the call, need to be copied to
2529 * the stack. Push the address here, so the call instruction can
2532 if (!cfg->arch.vret_addr_loc) {
2533 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2534 /* Prevent it from being register allocated or optimized away */
2535 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2538 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2541 case ArgValuetypeAddrInIReg: {
2543 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2544 vtarg->sreg1 = call->vret_var->dreg;
2545 vtarg->dreg = mono_alloc_preg (cfg);
2546 MONO_ADD_INS (cfg->cbb, vtarg);
2548 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2555 if (cfg->method->save_lmf) {
2556 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2557 MONO_ADD_INS (cfg->cbb, arg);
2560 call->stack_usage = cinfo->stack_usage;
2564 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2567 MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2568 ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2569 int size = ins->backend.size;
2571 switch (ainfo->storage) {
2572 case ArgValuetypeInReg: {
2576 for (part = 0; part < 2; ++part) {
2577 if (ainfo->pair_storage [part] == ArgNone)
2580 MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2581 load->inst_basereg = src->dreg;
2582 load->inst_offset = part * sizeof(mgreg_t);
2584 switch (ainfo->pair_storage [part]) {
2586 load->dreg = mono_alloc_ireg (cfg);
2588 case ArgInDoubleSSEReg:
2589 case ArgInFloatSSEReg:
2590 load->dreg = mono_alloc_freg (cfg);
2593 g_assert_not_reached ();
2595 MONO_ADD_INS (cfg->cbb, load);
2597 add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2601 case ArgValuetypeAddrInIReg: {
2602 MonoInst *vtaddr, *load;
2603 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2605 MONO_INST_NEW (cfg, load, OP_LDADDR);
2606 cfg->has_indirection = TRUE;
2607 load->inst_p0 = vtaddr;
2608 vtaddr->flags |= MONO_INST_INDIRECT;
2609 load->type = STACK_MP;
2610 load->klass = vtaddr->klass;
2611 load->dreg = mono_alloc_ireg (cfg);
2612 MONO_ADD_INS (cfg->cbb, load);
2613 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2615 if (ainfo->pair_storage [0] == ArgInIReg) {
2616 MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2617 arg->dreg = mono_alloc_ireg (cfg);
2618 arg->sreg1 = load->dreg;
2620 MONO_ADD_INS (cfg->cbb, arg);
2621 mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2623 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2627 case ArgGSharedVtInReg:
2629 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2631 case ArgGSharedVtOnStack:
2632 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2636 int dreg = mono_alloc_ireg (cfg);
2638 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2639 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2640 } else if (size <= 40) {
2641 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2643 // FIXME: Code growth
2644 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2647 if (cfg->compute_gc_maps) {
2649 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2655 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2657 MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2659 if (ret->type == MONO_TYPE_R4) {
2660 if (COMPILE_LLVM (cfg))
2661 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2663 MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2665 } else if (ret->type == MONO_TYPE_R8) {
2666 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2670 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2673 #endif /* DISABLE_JIT */
2675 #define EMIT_COND_BRANCH(ins,cond,sign) \
2676 if (ins->inst_true_bb->native_offset) { \
2677 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2679 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2680 if ((cfg->opt & MONO_OPT_BRANCH) && \
2681 x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2682 x86_branch8 (code, cond, 0, sign); \
2684 x86_branch32 (code, cond, 0, sign); \
2688 MonoMethodSignature *sig;
2693 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2701 switch (cinfo->ret.storage) {
2705 case ArgValuetypeInReg: {
2706 ArgInfo *ainfo = &cinfo->ret;
2708 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2710 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2718 for (i = 0; i < cinfo->nargs; ++i) {
2719 ArgInfo *ainfo = &cinfo->args [i];
2720 switch (ainfo->storage) {
2723 case ArgValuetypeInReg:
2724 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2726 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2738 * mono_arch_dyn_call_prepare:
2740 * Return a pointer to an arch-specific structure which contains information
2741 * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2742 * supported for SIG.
2743 * This function is equivalent to ffi_prep_cif in libffi.
2746 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2748 ArchDynCallInfo *info;
2751 cinfo = get_call_info (NULL, sig);
2753 if (!dyn_call_supported (sig, cinfo)) {
2758 info = g_new0 (ArchDynCallInfo, 1);
2759 // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2761 info->cinfo = cinfo;
2763 return (MonoDynCallInfo*)info;
2767 * mono_arch_dyn_call_free:
2769 * Free a MonoDynCallInfo structure.
2772 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2774 ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2776 g_free (ainfo->cinfo);
2780 #if !defined(__native_client__)
2781 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2782 #define GREG_TO_PTR(greg) (gpointer)(greg)
2784 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2785 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2786 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2790 * mono_arch_get_start_dyn_call:
2792 * Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2793 * store the result into BUF.
2794 * ARGS should be an array of pointers pointing to the arguments.
2795 * RET should point to a memory buffer large enought to hold the result of the
2797 * This function should be as fast as possible, any work which does not depend
2798 * on the actual values of the arguments should be done in
2799 * mono_arch_dyn_call_prepare ().
2800 * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2804 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2806 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2807 DynCallArgs *p = (DynCallArgs*)buf;
2808 int arg_index, greg, i, pindex;
2809 MonoMethodSignature *sig = dinfo->sig;
2810 int buffer_offset = 0;
2812 g_assert (buf_len >= sizeof (DynCallArgs));
2821 if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2822 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2827 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2828 p->regs [greg ++] = PTR_TO_GREG(ret);
2830 for (i = pindex; i < sig->param_count; i++) {
2831 MonoType *t = mini_get_underlying_type (sig->params [i]);
2832 gpointer *arg = args [arg_index ++];
2835 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2840 case MONO_TYPE_STRING:
2841 case MONO_TYPE_CLASS:
2842 case MONO_TYPE_ARRAY:
2843 case MONO_TYPE_SZARRAY:
2844 case MONO_TYPE_OBJECT:
2848 #if !defined(__mono_ilp32__)
2852 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2853 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2855 #if defined(__mono_ilp32__)
2858 g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2859 p->regs [greg ++] = *(guint64*)(arg);
2863 p->regs [greg ++] = *(guint8*)(arg);
2866 p->regs [greg ++] = *(gint8*)(arg);
2869 p->regs [greg ++] = *(gint16*)(arg);
2872 p->regs [greg ++] = *(guint16*)(arg);
2875 p->regs [greg ++] = *(gint32*)(arg);
2878 p->regs [greg ++] = *(guint32*)(arg);
2880 case MONO_TYPE_GENERICINST:
2881 if (MONO_TYPE_IS_REFERENCE (t)) {
2882 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2884 } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2885 MonoClass *klass = mono_class_from_mono_type (t);
2886 guint8 *nullable_buf;
2889 size = mono_class_value_size (klass, NULL);
2890 nullable_buf = p->buffer + buffer_offset;
2891 buffer_offset += size;
2892 g_assert (buffer_offset <= 256);
2894 /* The argument pointed to by arg is either a boxed vtype or null */
2895 mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2897 arg = (gpointer*)nullable_buf;
2903 case MONO_TYPE_VALUETYPE: {
2904 ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2906 g_assert (ainfo->storage == ArgValuetypeInReg);
2907 if (ainfo->pair_storage [0] != ArgNone) {
2908 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2909 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2911 if (ainfo->pair_storage [1] != ArgNone) {
2912 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2913 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2918 g_assert_not_reached ();
2922 g_assert (greg <= PARAM_REGS);
2926 * mono_arch_finish_dyn_call:
2928 * Store the result of a dyn call into the return value buffer passed to
2929 * start_dyn_call ().
2930 * This function should be as fast as possible, any work which does not depend
2931 * on the actual values of the arguments should be done in
2932 * mono_arch_dyn_call_prepare ().
2935 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2937 ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2938 MonoMethodSignature *sig = dinfo->sig;
2939 guint8 *ret = ((DynCallArgs*)buf)->ret;
2940 mgreg_t res = ((DynCallArgs*)buf)->res;
2941 MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2943 switch (sig_ret->type) {
2944 case MONO_TYPE_VOID:
2945 *(gpointer*)ret = NULL;
2947 case MONO_TYPE_STRING:
2948 case MONO_TYPE_CLASS:
2949 case MONO_TYPE_ARRAY:
2950 case MONO_TYPE_SZARRAY:
2951 case MONO_TYPE_OBJECT:
2955 *(gpointer*)ret = GREG_TO_PTR(res);
2961 *(guint8*)ret = res;
2964 *(gint16*)ret = res;
2967 *(guint16*)ret = res;
2970 *(gint32*)ret = res;
2973 *(guint32*)ret = res;
2976 *(gint64*)ret = res;
2979 *(guint64*)ret = res;
2981 case MONO_TYPE_GENERICINST:
2982 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
2983 *(gpointer*)ret = GREG_TO_PTR(res);
2988 case MONO_TYPE_VALUETYPE:
2989 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2992 ArgInfo *ainfo = &dinfo->cinfo->ret;
2994 g_assert (ainfo->storage == ArgValuetypeInReg);
2996 if (ainfo->pair_storage [0] != ArgNone) {
2997 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2998 ((mgreg_t*)ret)[0] = res;
3001 g_assert (ainfo->pair_storage [1] == ArgNone);
3005 g_assert_not_reached ();
3009 /* emit an exception if condition is fail */
3010 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name) \
3012 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
3013 if (tins == NULL) { \
3014 mono_add_patch_info (cfg, code - cfg->native_code, \
3015 MONO_PATCH_INFO_EXC, exc_name); \
3016 x86_branch32 (code, cond, 0, signed); \
3018 EMIT_COND_BRANCH (tins, cond, signed); \
3022 #define EMIT_FPCOMPARE(code) do { \
3023 amd64_fcompp (code); \
3024 amd64_fnstsw (code); \
3027 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
3028 amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
3029 amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
3030 amd64_ ##op (code); \
3031 amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3032 amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3036 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3038 gboolean no_patch = FALSE;
3041 * FIXME: Add support for thunks
3044 gboolean near_call = FALSE;
3047 * Indirect calls are expensive so try to make a near call if possible.
3048 * The caller memory is allocated by the code manager so it is
3049 * guaranteed to be at a 32 bit offset.
3052 if (patch_type != MONO_PATCH_INFO_ABS) {
3053 /* The target is in memory allocated using the code manager */
3056 if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3057 if (((MonoMethod*)data)->klass->image->aot_module)
3058 /* The callee might be an AOT method */
3060 if (((MonoMethod*)data)->dynamic)
3061 /* The target is in malloc-ed memory */
3065 if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3067 * The call might go directly to a native function without
3070 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
3072 gconstpointer target = mono_icall_get_wrapper (mi);
3073 if ((((guint64)target) >> 32) != 0)
3079 MonoJumpInfo *jinfo = NULL;
3081 if (cfg->abs_patches)
3082 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
3084 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3085 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3086 if (mi && (((guint64)mi->func) >> 32) == 0)
3091 * This is not really an optimization, but required because the
3092 * generic class init trampolines use R11 to pass the vtable.
3097 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3099 if (info->func == info->wrapper) {
3101 if ((((guint64)info->func) >> 32) == 0)
3105 /* See the comment in mono_codegen () */
3106 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3110 else if ((((guint64)data) >> 32) == 0) {
3117 if (cfg->method->dynamic)
3118 /* These methods are allocated using malloc */
3121 #ifdef MONO_ARCH_NOMAP32BIT
3124 #if defined(__native_client__)
3125 /* Always use near_call == TRUE for Native Client */
3128 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3129 if (optimize_for_xen)
3132 if (cfg->compile_aot) {
3139 * Align the call displacement to an address divisible by 4 so it does
3140 * not span cache lines. This is required for code patching to work on SMP
3143 if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3144 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3145 amd64_padding (code, pad_size);
3147 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3148 amd64_call_code (code, 0);
3151 mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3152 amd64_set_reg_template (code, GP_SCRATCH_REG);
3153 amd64_call_reg (code, GP_SCRATCH_REG);
3160 static inline guint8*
3161 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3164 if (win64_adjust_stack)
3165 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3167 code = emit_call_body (cfg, code, patch_type, data);
3169 if (win64_adjust_stack)
3170 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3177 store_membase_imm_to_store_membase_reg (int opcode)
3180 case OP_STORE_MEMBASE_IMM:
3181 return OP_STORE_MEMBASE_REG;
3182 case OP_STOREI4_MEMBASE_IMM:
3183 return OP_STOREI4_MEMBASE_REG;
3184 case OP_STOREI8_MEMBASE_IMM:
3185 return OP_STOREI8_MEMBASE_REG;
3193 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3196 * mono_arch_peephole_pass_1:
3198 * Perform peephole opts which should/can be performed before local regalloc
3201 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3205 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3206 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3208 switch (ins->opcode) {
3212 if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3214 * X86_LEA is like ADD, but doesn't have the
3215 * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3216 * its operand to 64 bit.
3218 ins->opcode = OP_X86_LEA_MEMBASE;
3219 ins->inst_basereg = ins->sreg1;
3224 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3228 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3229 * the latter has length 2-3 instead of 6 (reverse constant
3230 * propagation). These instruction sequences are very common
3231 * in the initlocals bblock.
3233 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3234 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3235 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3236 ins2->sreg1 = ins->dreg;
3237 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3239 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3242 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3250 case OP_COMPARE_IMM:
3251 case OP_LCOMPARE_IMM:
3252 /* OP_COMPARE_IMM (reg, 0)
3254 * OP_AMD64_TEST_NULL (reg)
3257 ins->opcode = OP_AMD64_TEST_NULL;
3259 case OP_ICOMPARE_IMM:
3261 ins->opcode = OP_X86_TEST_NULL;
3263 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3265 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3266 * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3268 * OP_STORE_MEMBASE_REG reg, offset(basereg)
3269 * OP_COMPARE_IMM reg, imm
3271 * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3273 if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3274 ins->inst_basereg == last_ins->inst_destbasereg &&
3275 ins->inst_offset == last_ins->inst_offset) {
3276 ins->opcode = OP_ICOMPARE_IMM;
3277 ins->sreg1 = last_ins->sreg1;
3279 /* check if we can remove cmp reg,0 with test null */
3281 ins->opcode = OP_X86_TEST_NULL;
3287 mono_peephole_ins (bb, ins);
3292 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3296 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3297 switch (ins->opcode) {
3300 MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3301 /* reg = 0 -> XOR (reg, reg) */
3302 /* XOR sets cflags on x86, so we cant do it always */
3303 if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3304 ins->opcode = OP_LXOR;
3305 ins->sreg1 = ins->dreg;
3306 ins->sreg2 = ins->dreg;
3314 * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3315 * 0 result into 64 bits.
3317 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3318 ins->opcode = OP_IXOR;
3322 if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3326 * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3327 * the latter has length 2-3 instead of 6 (reverse constant
3328 * propagation). These instruction sequences are very common
3329 * in the initlocals bblock.
3331 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3332 if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3333 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3334 ins2->sreg1 = ins->dreg;
3335 } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3337 } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3340 } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3349 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3350 ins->opcode = OP_X86_INC_REG;
3353 if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3354 ins->opcode = OP_X86_DEC_REG;
3358 mono_peephole_ins (bb, ins);
3362 #define NEW_INS(cfg,ins,dest,op) do { \
3363 MONO_INST_NEW ((cfg), (dest), (op)); \
3364 (dest)->cil_code = (ins)->cil_code; \
3365 mono_bblock_insert_before_ins (bb, ins, (dest)); \
3369 * mono_arch_lowering_pass:
3371 * Converts complex opcodes into simpler ones so that each IR instruction
3372 * corresponds to one machine instruction.
3375 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3377 MonoInst *ins, *n, *temp;
3380 * FIXME: Need to add more instructions, but the current machine
3381 * description can't model some parts of the composite instructions like
3384 MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3385 switch (ins->opcode) {
3389 case OP_IDIV_UN_IMM:
3390 case OP_IREM_UN_IMM:
3393 mono_decompose_op_imm (cfg, bb, ins);
3395 case OP_COMPARE_IMM:
3396 case OP_LCOMPARE_IMM:
3397 if (!amd64_use_imm32 (ins->inst_imm)) {
3398 NEW_INS (cfg, ins, temp, OP_I8CONST);
3399 temp->inst_c0 = ins->inst_imm;
3400 temp->dreg = mono_alloc_ireg (cfg);
3401 ins->opcode = OP_COMPARE;
3402 ins->sreg2 = temp->dreg;
3405 #ifndef __mono_ilp32__
3406 case OP_LOAD_MEMBASE:
3408 case OP_LOADI8_MEMBASE:
3409 #ifndef __native_client_codegen__
3410 /* Don't generate memindex opcodes (to simplify */
3411 /* read sandboxing) */
3412 if (!amd64_use_imm32 (ins->inst_offset)) {
3413 NEW_INS (cfg, ins, temp, OP_I8CONST);
3414 temp->inst_c0 = ins->inst_offset;
3415 temp->dreg = mono_alloc_ireg (cfg);
3416 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3417 ins->inst_indexreg = temp->dreg;
3421 #ifndef __mono_ilp32__
3422 case OP_STORE_MEMBASE_IMM:
3424 case OP_STOREI8_MEMBASE_IMM:
3425 if (!amd64_use_imm32 (ins->inst_imm)) {
3426 NEW_INS (cfg, ins, temp, OP_I8CONST);
3427 temp->inst_c0 = ins->inst_imm;
3428 temp->dreg = mono_alloc_ireg (cfg);
3429 ins->opcode = OP_STOREI8_MEMBASE_REG;
3430 ins->sreg1 = temp->dreg;
3433 #ifdef MONO_ARCH_SIMD_INTRINSICS
3434 case OP_EXPAND_I1: {
3435 int temp_reg1 = mono_alloc_ireg (cfg);
3436 int temp_reg2 = mono_alloc_ireg (cfg);
3437 int original_reg = ins->sreg1;
3439 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3440 temp->sreg1 = original_reg;
3441 temp->dreg = temp_reg1;
3443 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3444 temp->sreg1 = temp_reg1;
3445 temp->dreg = temp_reg2;
3448 NEW_INS (cfg, ins, temp, OP_LOR);
3449 temp->sreg1 = temp->dreg = temp_reg2;
3450 temp->sreg2 = temp_reg1;
3452 ins->opcode = OP_EXPAND_I2;
3453 ins->sreg1 = temp_reg2;
3462 bb->max_vreg = cfg->next_vreg;
3466 branch_cc_table [] = {
3467 X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3468 X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3469 X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3472 /* Maps CMP_... constants to X86_CC_... constants */
3475 X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3476 X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3480 cc_signed_table [] = {
3481 TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3482 FALSE, FALSE, FALSE, FALSE
3485 /*#include "cprop.c"*/
3487 static unsigned char*
3488 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3491 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3493 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3496 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3498 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3502 static unsigned char*
3503 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3505 int sreg = tree->sreg1;
3506 int need_touch = FALSE;
3508 #if defined(TARGET_WIN32)
3510 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3511 if (!tree->flags & MONO_INST_INIT)
3520 * If requested stack size is larger than one page,
3521 * perform stack-touch operation
3524 * Generate stack probe code.
3525 * Under Windows, it is necessary to allocate one page at a time,
3526 * "touching" stack after each successful sub-allocation. This is
3527 * because of the way stack growth is implemented - there is a
3528 * guard page before the lowest stack page that is currently commited.
3529 * Stack normally grows sequentially so OS traps access to the
3530 * guard page and commits more pages when needed.
3532 amd64_test_reg_imm (code, sreg, ~0xFFF);
3533 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3535 br[2] = code; /* loop */
3536 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3537 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3538 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3539 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3540 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3541 amd64_patch (br[3], br[2]);
3542 amd64_test_reg_reg (code, sreg, sreg);
3543 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3544 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3546 br[1] = code; x86_jump8 (code, 0);
3548 amd64_patch (br[0], code);
3549 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3550 amd64_patch (br[1], code);
3551 amd64_patch (br[4], code);
3554 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3556 if (tree->flags & MONO_INST_INIT) {
3558 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3559 amd64_push_reg (code, AMD64_RAX);
3562 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3563 amd64_push_reg (code, AMD64_RCX);
3566 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3567 amd64_push_reg (code, AMD64_RDI);
3571 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3572 if (sreg != AMD64_RCX)
3573 amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3574 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3576 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3577 if (cfg->param_area)
3578 amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3580 #if defined(__default_codegen__)
3581 amd64_prefix (code, X86_REP_PREFIX);
3583 #elif defined(__native_client_codegen__)
3584 /* NaCl stos pseudo-instruction */
3585 amd64_codegen_pre(code);
3586 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
3587 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3588 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3589 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3590 amd64_prefix (code, X86_REP_PREFIX);
3592 amd64_codegen_post(code);
3593 #endif /* __native_client_codegen__ */
3595 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3596 amd64_pop_reg (code, AMD64_RDI);
3597 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3598 amd64_pop_reg (code, AMD64_RCX);
3599 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3600 amd64_pop_reg (code, AMD64_RAX);
3606 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3611 /* Move return value to the target register */
3612 /* FIXME: do this in the local reg allocator */
3613 switch (ins->opcode) {
3616 case OP_CALL_MEMBASE:
3619 case OP_LCALL_MEMBASE:
3620 g_assert (ins->dreg == AMD64_RAX);
3624 case OP_FCALL_MEMBASE: {
3625 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3626 if (rtype->type == MONO_TYPE_R4) {
3627 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3630 if (ins->dreg != AMD64_XMM0)
3631 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3637 case OP_RCALL_MEMBASE:
3638 if (ins->dreg != AMD64_XMM0)
3639 amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3643 case OP_VCALL_MEMBASE:
3646 case OP_VCALL2_MEMBASE:
3647 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3648 if (cinfo->ret.storage == ArgValuetypeInReg) {
3649 MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3651 /* Load the destination address */
3652 g_assert (loc->opcode == OP_REGOFFSET);
3653 amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3655 for (quad = 0; quad < 2; quad ++) {
3656 switch (cinfo->ret.pair_storage [quad]) {
3658 amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3660 case ArgInFloatSSEReg:
3661 amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3663 case ArgInDoubleSSEReg:
3664 amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3679 #endif /* DISABLE_JIT */
3682 static int tls_gs_offset;
3686 mono_amd64_have_tls_get (void)
3689 static gboolean have_tls_get = FALSE;
3690 static gboolean inited = FALSE;
3693 return have_tls_get;
3695 #if MONO_HAVE_FAST_TLS
3696 guint8 *ins = (guint8*)pthread_getspecific;
3699 * We're looking for these two instructions:
3701 * mov %gs:[offset](,%rdi,8),%rax
3704 have_tls_get = ins [0] == 0x65 &&
3714 tls_gs_offset = ins[5];
3717 * Apple now loads a different version of pthread_getspecific when launched from Xcode
3718 * For that version we're looking for these instructions:
3722 * mov %gs:[offset](,%rdi,8),%rax
3726 if (!have_tls_get) {
3727 have_tls_get = ins [0] == 0x55 &&
3742 tls_gs_offset = ins[9];
3748 return have_tls_get;
3749 #elif defined(TARGET_ANDROID)
3757 mono_amd64_get_tls_gs_offset (void)
3760 return tls_gs_offset;
3762 g_assert_not_reached ();
3768 * mono_amd64_emit_tls_get:
3769 * @code: buffer to store code to
3770 * @dreg: hard register where to place the result
3771 * @tls_offset: offset info
3773 * mono_amd64_emit_tls_get emits in @code the native code that puts in
3774 * the dreg register the item in the thread local storage identified
3777 * Returns: a pointer to the end of the stored code
3780 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3783 if (tls_offset < 64) {
3784 x86_prefix (code, X86_GS_PREFIX);
3785 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3789 g_assert (tls_offset < 0x440);
3790 /* Load TEB->TlsExpansionSlots */
3791 x86_prefix (code, X86_GS_PREFIX);
3792 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3793 amd64_test_reg_reg (code, dreg, dreg);
3795 amd64_branch (code, X86_CC_EQ, code, TRUE);
3796 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3797 amd64_patch (buf [0], code);
3799 #elif defined(__APPLE__)
3800 x86_prefix (code, X86_GS_PREFIX);
3801 amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3803 if (optimize_for_xen) {
3804 x86_prefix (code, X86_FS_PREFIX);
3805 amd64_mov_reg_mem (code, dreg, 0, 8);
3806 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3808 x86_prefix (code, X86_FS_PREFIX);
3809 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3816 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3818 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3820 if (dreg != offset_reg)
3821 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3822 amd64_prefix (code, X86_GS_PREFIX);
3823 amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3824 #elif defined(__linux__)
3827 if (dreg == offset_reg) {
3828 /* Use a temporary reg by saving it to the redzone */
3829 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3830 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3831 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3832 offset_reg = tmpreg;
3834 x86_prefix (code, X86_FS_PREFIX);
3835 amd64_mov_reg_mem (code, dreg, 0, 8);
3836 amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3838 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3840 g_assert_not_reached ();
3846 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3849 g_assert_not_reached ();
3850 #elif defined(__APPLE__)
3851 x86_prefix (code, X86_GS_PREFIX);
3852 amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3854 g_assert (!optimize_for_xen);
3855 x86_prefix (code, X86_FS_PREFIX);
3856 amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3862 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3864 /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3866 g_assert_not_reached ();
3867 #elif defined(__APPLE__)
3868 x86_prefix (code, X86_GS_PREFIX);
3869 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3871 x86_prefix (code, X86_FS_PREFIX);
3872 amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3878 * mono_arch_translate_tls_offset:
3880 * Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3883 mono_arch_translate_tls_offset (int offset)
3886 return tls_gs_offset + (offset * 8);
3895 * Emit code to initialize an LMF structure at LMF_OFFSET.
3898 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3901 * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3904 * sp is saved right before calls but we need to save it here too so
3905 * async stack walks would work.
3907 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3909 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3910 if (cfg->arch.omit_fp && cfa_offset != -1)
3911 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3913 /* These can't contain refs */
3914 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3915 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3916 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3917 /* These are handled automatically by the stack marking code */
3918 mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3923 #define REAL_PRINT_REG(text,reg) \
3924 mono_assert (reg >= 0); \
3925 amd64_push_reg (code, AMD64_RAX); \
3926 amd64_push_reg (code, AMD64_RDX); \
3927 amd64_push_reg (code, AMD64_RCX); \
3928 amd64_push_reg (code, reg); \
3929 amd64_push_imm (code, reg); \
3930 amd64_push_imm (code, text " %d %p\n"); \
3931 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3932 amd64_call_reg (code, AMD64_RAX); \
3933 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3934 amd64_pop_reg (code, AMD64_RCX); \
3935 amd64_pop_reg (code, AMD64_RDX); \
3936 amd64_pop_reg (code, AMD64_RAX);
3938 /* benchmark and set based on cpu */
3939 #define LOOP_ALIGNMENT 8
3940 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3944 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3949 guint8 *code = cfg->native_code + cfg->code_len;
3952 /* Fix max_offset estimate for each successor bb */
3953 if (cfg->opt & MONO_OPT_BRANCH) {
3954 int current_offset = cfg->code_len;
3955 MonoBasicBlock *current_bb;
3956 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3957 current_bb->max_offset = current_offset;
3958 current_offset += current_bb->max_length;
3962 if (cfg->opt & MONO_OPT_LOOP) {
3963 int pad, align = LOOP_ALIGNMENT;
3964 /* set alignment depending on cpu */
3965 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3967 /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3968 amd64_padding (code, pad);
3969 cfg->code_len += pad;
3970 bb->native_offset = cfg->code_len;
3974 #if defined(__native_client_codegen__)
3975 /* For Native Client, all indirect call/jump targets must be */
3976 /* 32-byte aligned. Exception handler blocks are jumped to */
3977 /* indirectly as well. */
3978 gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
3979 (bb->flags & BB_EXCEPTION_HANDLER);
3981 if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
3982 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
3983 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
3984 cfg->code_len += pad;
3985 bb->native_offset = cfg->code_len;
3987 #endif /*__native_client_codegen__*/
3989 if (cfg->verbose_level > 2)
3990 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3992 if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
3993 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3994 g_assert (!cfg->compile_aot);
3996 cov->data [bb->dfn].cil_code = bb->cil_code;
3997 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3998 /* this is not thread save, but good enough */
3999 amd64_inc_membase (code, AMD64_R11, 0);
4002 offset = code - cfg->native_code;
4004 mono_debug_open_block (cfg, bb, offset);
4006 if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
4007 x86_breakpoint (code);
4009 MONO_BB_FOR_EACH_INS (bb, ins) {
4010 offset = code - cfg->native_code;
4012 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4014 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
4016 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
4017 cfg->code_size *= 2;
4018 cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
4019 code = cfg->native_code + offset;
4020 cfg->stat_code_reallocs++;
4023 if (cfg->debug_info)
4024 mono_debug_record_line_number (cfg, ins, offset);
4026 switch (ins->opcode) {
4028 amd64_mul_reg (code, ins->sreg2, TRUE);
4031 amd64_mul_reg (code, ins->sreg2, FALSE);
4033 case OP_X86_SETEQ_MEMBASE:
4034 amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
4036 case OP_STOREI1_MEMBASE_IMM:
4037 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
4039 case OP_STOREI2_MEMBASE_IMM:
4040 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
4042 case OP_STOREI4_MEMBASE_IMM:
4043 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
4045 case OP_STOREI1_MEMBASE_REG:
4046 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4048 case OP_STOREI2_MEMBASE_REG:
4049 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4051 /* In AMD64 NaCl, pointers are 4 bytes, */
4052 /* so STORE_* != STOREI8_*. Likewise below. */
4053 case OP_STORE_MEMBASE_REG:
4054 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4056 case OP_STOREI8_MEMBASE_REG:
4057 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4059 case OP_STOREI4_MEMBASE_REG:
4060 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4062 case OP_STORE_MEMBASE_IMM:
4063 #ifndef __native_client_codegen__
4064 /* In NaCl, this could be a PCONST type, which could */
4065 /* mean a pointer type was copied directly into the */
4066 /* lower 32-bits of inst_imm, so for InvalidPtr==-1 */
4067 /* the value would be 0x00000000FFFFFFFF which is */
4068 /* not proper for an imm32 unless you cast it. */
4069 g_assert (amd64_is_imm32 (ins->inst_imm));
4071 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4073 case OP_STOREI8_MEMBASE_IMM:
4074 g_assert (amd64_is_imm32 (ins->inst_imm));
4075 amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4078 #ifdef __mono_ilp32__
4079 /* In ILP32, pointers are 4 bytes, so separate these */
4080 /* cases, use literal 8 below where we really want 8 */
4081 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4082 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4086 // FIXME: Decompose this earlier
4087 if (amd64_use_imm32 (ins->inst_imm))
4088 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4090 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4091 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4095 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4096 amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4099 // FIXME: Decompose this earlier
4100 if (amd64_use_imm32 (ins->inst_imm))
4101 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4103 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4104 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4108 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4109 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4112 /* For NaCl, pointers are 4 bytes, so separate these */
4113 /* cases, use literal 8 below where we really want 8 */
4114 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4115 amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4117 case OP_LOAD_MEMBASE:
4118 g_assert (amd64_is_imm32 (ins->inst_offset));
4119 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4121 case OP_LOADI8_MEMBASE:
4122 /* Use literal 8 instead of sizeof pointer or */
4123 /* register, we really want 8 for this opcode */
4124 g_assert (amd64_is_imm32 (ins->inst_offset));
4125 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4127 case OP_LOADI4_MEMBASE:
4128 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4130 case OP_LOADU4_MEMBASE:
4131 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4133 case OP_LOADU1_MEMBASE:
4134 /* The cpu zero extends the result into 64 bits */
4135 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4137 case OP_LOADI1_MEMBASE:
4138 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4140 case OP_LOADU2_MEMBASE:
4141 /* The cpu zero extends the result into 64 bits */
4142 amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4144 case OP_LOADI2_MEMBASE:
4145 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4147 case OP_AMD64_LOADI8_MEMINDEX:
4148 amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4150 case OP_LCONV_TO_I1:
4151 case OP_ICONV_TO_I1:
4153 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4155 case OP_LCONV_TO_I2:
4156 case OP_ICONV_TO_I2:
4158 amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4160 case OP_LCONV_TO_U1:
4161 case OP_ICONV_TO_U1:
4162 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4164 case OP_LCONV_TO_U2:
4165 case OP_ICONV_TO_U2:
4166 amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4169 /* Clean out the upper word */
4170 amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4173 amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4177 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4179 case OP_COMPARE_IMM:
4180 #if defined(__mono_ilp32__)
4181 /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4182 g_assert (amd64_is_imm32 (ins->inst_imm));
4183 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4186 case OP_LCOMPARE_IMM:
4187 g_assert (amd64_is_imm32 (ins->inst_imm));
4188 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4190 case OP_X86_COMPARE_REG_MEMBASE:
4191 amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4193 case OP_X86_TEST_NULL:
4194 amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4196 case OP_AMD64_TEST_NULL:
4197 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4200 case OP_X86_ADD_REG_MEMBASE:
4201 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4203 case OP_X86_SUB_REG_MEMBASE:
4204 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4206 case OP_X86_AND_REG_MEMBASE:
4207 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4209 case OP_X86_OR_REG_MEMBASE:
4210 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4212 case OP_X86_XOR_REG_MEMBASE:
4213 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4216 case OP_X86_ADD_MEMBASE_IMM:
4217 /* FIXME: Make a 64 version too */
4218 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4220 case OP_X86_SUB_MEMBASE_IMM:
4221 g_assert (amd64_is_imm32 (ins->inst_imm));
4222 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4224 case OP_X86_AND_MEMBASE_IMM:
4225 g_assert (amd64_is_imm32 (ins->inst_imm));
4226 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4228 case OP_X86_OR_MEMBASE_IMM:
4229 g_assert (amd64_is_imm32 (ins->inst_imm));
4230 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4232 case OP_X86_XOR_MEMBASE_IMM:
4233 g_assert (amd64_is_imm32 (ins->inst_imm));
4234 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4236 case OP_X86_ADD_MEMBASE_REG:
4237 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4239 case OP_X86_SUB_MEMBASE_REG:
4240 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4242 case OP_X86_AND_MEMBASE_REG:
4243 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4245 case OP_X86_OR_MEMBASE_REG:
4246 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4248 case OP_X86_XOR_MEMBASE_REG:
4249 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4251 case OP_X86_INC_MEMBASE:
4252 amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4254 case OP_X86_INC_REG:
4255 amd64_inc_reg_size (code, ins->dreg, 4);
4257 case OP_X86_DEC_MEMBASE:
4258 amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4260 case OP_X86_DEC_REG:
4261 amd64_dec_reg_size (code, ins->dreg, 4);
4263 case OP_X86_MUL_REG_MEMBASE:
4264 case OP_X86_MUL_MEMBASE_REG:
4265 amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4267 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4268 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4270 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4271 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4273 case OP_AMD64_COMPARE_MEMBASE_REG:
4274 amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4276 case OP_AMD64_COMPARE_MEMBASE_IMM:
4277 g_assert (amd64_is_imm32 (ins->inst_imm));
4278 amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4280 case OP_X86_COMPARE_MEMBASE8_IMM:
4281 amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4283 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4284 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4286 case OP_AMD64_COMPARE_REG_MEMBASE:
4287 amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4290 case OP_AMD64_ADD_REG_MEMBASE:
4291 amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4293 case OP_AMD64_SUB_REG_MEMBASE:
4294 amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4296 case OP_AMD64_AND_REG_MEMBASE:
4297 amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4299 case OP_AMD64_OR_REG_MEMBASE:
4300 amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4302 case OP_AMD64_XOR_REG_MEMBASE:
4303 amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4306 case OP_AMD64_ADD_MEMBASE_REG:
4307 amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4309 case OP_AMD64_SUB_MEMBASE_REG:
4310 amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4312 case OP_AMD64_AND_MEMBASE_REG:
4313 amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4315 case OP_AMD64_OR_MEMBASE_REG:
4316 amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4318 case OP_AMD64_XOR_MEMBASE_REG:
4319 amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4322 case OP_AMD64_ADD_MEMBASE_IMM:
4323 g_assert (amd64_is_imm32 (ins->inst_imm));
4324 amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4326 case OP_AMD64_SUB_MEMBASE_IMM:
4327 g_assert (amd64_is_imm32 (ins->inst_imm));
4328 amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4330 case OP_AMD64_AND_MEMBASE_IMM:
4331 g_assert (amd64_is_imm32 (ins->inst_imm));
4332 amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4334 case OP_AMD64_OR_MEMBASE_IMM:
4335 g_assert (amd64_is_imm32 (ins->inst_imm));
4336 amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4338 case OP_AMD64_XOR_MEMBASE_IMM:
4339 g_assert (amd64_is_imm32 (ins->inst_imm));
4340 amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4344 amd64_breakpoint (code);
4346 case OP_RELAXED_NOP:
4347 x86_prefix (code, X86_REP_PREFIX);
4355 case OP_DUMMY_STORE:
4356 case OP_DUMMY_ICONST:
4357 case OP_DUMMY_R8CONST:
4358 case OP_NOT_REACHED:
4361 case OP_IL_SEQ_POINT:
4362 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4364 case OP_SEQ_POINT: {
4365 if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4366 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4369 /* Load ss_tramp_var */
4370 /* This is equal to &ss_trampoline */
4371 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4372 /* Load the trampoline address */
4373 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4374 /* Call it if it is non-null */
4375 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4377 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4378 amd64_call_reg (code, AMD64_R11);
4379 amd64_patch (label, code);
4383 * This is the address which is saved in seq points,
4385 mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4387 if (cfg->compile_aot) {
4388 guint32 offset = code - cfg->native_code;
4390 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4394 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4395 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4396 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4397 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4398 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4400 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4401 /* Call the trampoline */
4402 amd64_call_reg (code, AMD64_R11);
4403 amd64_patch (label, code);
4405 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4409 * Emit a test+branch against a constant, the constant will be overwritten
4410 * by mono_arch_set_breakpoint () to cause the test to fail.
4412 amd64_mov_reg_imm (code, AMD64_R11, 0);
4413 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4415 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4418 g_assert (var->opcode == OP_REGOFFSET);
4419 /* Load bp_tramp_var */
4420 /* This is equal to &bp_trampoline */
4421 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4422 /* Call the trampoline */
4423 amd64_call_membase (code, AMD64_R11, 0);
4424 amd64_patch (label, code);
4427 * Add an additional nop so skipping the bp doesn't cause the ip to point
4428 * to another IL offset.
4436 amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4439 amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4443 g_assert (amd64_is_imm32 (ins->inst_imm));
4444 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4447 g_assert (amd64_is_imm32 (ins->inst_imm));
4448 amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4453 amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4456 amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4460 g_assert (amd64_is_imm32 (ins->inst_imm));
4461 amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4464 g_assert (amd64_is_imm32 (ins->inst_imm));
4465 amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4468 amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4472 g_assert (amd64_is_imm32 (ins->inst_imm));
4473 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4476 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4481 guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4483 switch (ins->inst_imm) {
4487 if (ins->dreg != ins->sreg1)
4488 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4489 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4492 /* LEA r1, [r2 + r2*2] */
4493 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4496 /* LEA r1, [r2 + r2*4] */
4497 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4500 /* LEA r1, [r2 + r2*2] */
4502 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4503 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4506 /* LEA r1, [r2 + r2*8] */
4507 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4510 /* LEA r1, [r2 + r2*4] */
4512 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4513 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4516 /* LEA r1, [r2 + r2*2] */
4518 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4519 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4522 /* LEA r1, [r2 + r2*4] */
4523 /* LEA r1, [r1 + r1*4] */
4524 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4525 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4528 /* LEA r1, [r2 + r2*4] */
4530 /* LEA r1, [r1 + r1*4] */
4531 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4532 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4533 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4536 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4543 #if defined( __native_client_codegen__ )
4544 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4545 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4547 /* Regalloc magic makes the div/rem cases the same */
4548 if (ins->sreg2 == AMD64_RDX) {
4549 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4551 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4554 amd64_div_reg (code, ins->sreg2, TRUE);
4559 #if defined( __native_client_codegen__ )
4560 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4561 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4563 if (ins->sreg2 == AMD64_RDX) {
4564 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4565 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4566 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4568 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4569 amd64_div_reg (code, ins->sreg2, FALSE);
4574 #if defined( __native_client_codegen__ )
4575 amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4576 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4578 if (ins->sreg2 == AMD64_RDX) {
4579 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4580 amd64_cdq_size (code, 4);
4581 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4583 amd64_cdq_size (code, 4);
4584 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4589 #if defined( __native_client_codegen__ )
4590 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4591 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4593 if (ins->sreg2 == AMD64_RDX) {
4594 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4595 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4596 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4598 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4599 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4603 amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4604 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4607 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4611 g_assert (amd64_is_imm32 (ins->inst_imm));
4612 amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4615 amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4619 g_assert (amd64_is_imm32 (ins->inst_imm));
4620 amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4623 g_assert (ins->sreg2 == AMD64_RCX);
4624 amd64_shift_reg (code, X86_SHL, ins->dreg);
4627 g_assert (ins->sreg2 == AMD64_RCX);
4628 amd64_shift_reg (code, X86_SAR, ins->dreg);
4632 g_assert (amd64_is_imm32 (ins->inst_imm));
4633 amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4636 g_assert (amd64_is_imm32 (ins->inst_imm));
4637 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4639 case OP_LSHR_UN_IMM:
4640 g_assert (amd64_is_imm32 (ins->inst_imm));
4641 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4644 g_assert (ins->sreg2 == AMD64_RCX);
4645 amd64_shift_reg (code, X86_SHR, ins->dreg);
4649 g_assert (amd64_is_imm32 (ins->inst_imm));
4650 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4655 amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4658 amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4661 amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4664 amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4668 amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4671 amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4674 amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4677 amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4680 amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4683 amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4686 amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4689 amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4692 amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4695 amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4698 amd64_neg_reg_size (code, ins->sreg1, 4);
4701 amd64_not_reg_size (code, ins->sreg1, 4);
4704 g_assert (ins->sreg2 == AMD64_RCX);
4705 amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4708 g_assert (ins->sreg2 == AMD64_RCX);
4709 amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4712 amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4714 case OP_ISHR_UN_IMM:
4715 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4718 g_assert (ins->sreg2 == AMD64_RCX);
4719 amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4722 amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4725 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4728 amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4729 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4731 case OP_IMUL_OVF_UN:
4732 case OP_LMUL_OVF_UN: {
4733 /* the mul operation and the exception check should most likely be split */
4734 int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4735 int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4736 /*g_assert (ins->sreg2 == X86_EAX);
4737 g_assert (ins->dreg == X86_EAX);*/
4738 if (ins->sreg2 == X86_EAX) {
4739 non_eax_reg = ins->sreg1;
4740 } else if (ins->sreg1 == X86_EAX) {
4741 non_eax_reg = ins->sreg2;
4743 /* no need to save since we're going to store to it anyway */
4744 if (ins->dreg != X86_EAX) {
4746 amd64_push_reg (code, X86_EAX);
4748 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4749 non_eax_reg = ins->sreg2;
4751 if (ins->dreg == X86_EDX) {
4754 amd64_push_reg (code, X86_EAX);
4758 amd64_push_reg (code, X86_EDX);
4760 amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4761 /* save before the check since pop and mov don't change the flags */
4762 if (ins->dreg != X86_EAX)
4763 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4765 amd64_pop_reg (code, X86_EDX);
4767 amd64_pop_reg (code, X86_EAX);
4768 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4772 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4774 case OP_ICOMPARE_IMM:
4775 amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4797 EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4805 case OP_CMOV_INE_UN:
4806 case OP_CMOV_IGE_UN:
4807 case OP_CMOV_IGT_UN:
4808 case OP_CMOV_ILE_UN:
4809 case OP_CMOV_ILT_UN:
4815 case OP_CMOV_LNE_UN:
4816 case OP_CMOV_LGE_UN:
4817 case OP_CMOV_LGT_UN:
4818 case OP_CMOV_LLE_UN:
4819 case OP_CMOV_LLT_UN:
4820 g_assert (ins->dreg == ins->sreg1);
4821 /* This needs to operate on 64 bit values */
4822 amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4826 amd64_not_reg (code, ins->sreg1);
4829 amd64_neg_reg (code, ins->sreg1);
4834 if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4835 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4837 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4840 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4841 amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4844 mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4845 amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4848 if (ins->dreg != ins->sreg1)
4849 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4851 case OP_AMD64_SET_XMMREG_R4: {
4853 if (ins->dreg != ins->sreg1)
4854 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4856 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4860 case OP_AMD64_SET_XMMREG_R8: {
4861 if (ins->dreg != ins->sreg1)
4862 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4866 MonoCallInst *call = (MonoCallInst*)ins;
4867 int i, save_area_offset;
4869 g_assert (!cfg->method->save_lmf);
4871 /* Restore callee saved registers */
4872 save_area_offset = cfg->arch.reg_save_area_offset;
4873 for (i = 0; i < AMD64_NREG; ++i)
4874 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4875 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4876 save_area_offset += 8;
4879 if (cfg->arch.omit_fp) {
4880 if (cfg->arch.stack_alloc_size)
4881 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4883 if (call->stack_usage)
4886 /* Copy arguments on the stack to our argument area */
4887 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4888 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4889 amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4895 offset = code - cfg->native_code;
4896 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4897 if (cfg->compile_aot)
4898 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4900 amd64_set_reg_template (code, AMD64_R11);
4901 amd64_jump_reg (code, AMD64_R11);
4902 ins->flags |= MONO_INST_GC_CALLSITE;
4903 ins->backend.pc_offset = code - cfg->native_code;
4907 /* ensure ins->sreg1 is not NULL */
4908 amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4911 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4912 amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4922 call = (MonoCallInst*)ins;
4924 * The AMD64 ABI forces callers to know about varargs.
4926 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4927 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4928 else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4930 * Since the unmanaged calling convention doesn't contain a
4931 * 'vararg' entry, we have to treat every pinvoke call as a
4932 * potential vararg call.
4936 for (i = 0; i < AMD64_XMM_NREG; ++i)
4937 if (call->used_fregs & (1 << i))
4940 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4942 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4945 if (ins->flags & MONO_INST_HAS_METHOD)
4946 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4948 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4949 ins->flags |= MONO_INST_GC_CALLSITE;
4950 ins->backend.pc_offset = code - cfg->native_code;
4951 code = emit_move_return_value (cfg, ins, code);
4958 case OP_VOIDCALL_REG:
4960 call = (MonoCallInst*)ins;
4962 if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4963 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4964 ins->sreg1 = AMD64_R11;
4968 * The AMD64 ABI forces callers to know about varargs.
4970 if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4971 if (ins->sreg1 == AMD64_RAX) {
4972 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4973 ins->sreg1 = AMD64_R11;
4975 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4976 } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4978 * Since the unmanaged calling convention doesn't contain a
4979 * 'vararg' entry, we have to treat every pinvoke call as a
4980 * potential vararg call.
4984 for (i = 0; i < AMD64_XMM_NREG; ++i)
4985 if (call->used_fregs & (1 << i))
4987 if (ins->sreg1 == AMD64_RAX) {
4988 amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4989 ins->sreg1 = AMD64_R11;
4992 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4994 amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4997 amd64_call_reg (code, ins->sreg1);
4998 ins->flags |= MONO_INST_GC_CALLSITE;
4999 ins->backend.pc_offset = code - cfg->native_code;
5000 code = emit_move_return_value (cfg, ins, code);
5002 case OP_FCALL_MEMBASE:
5003 case OP_RCALL_MEMBASE:
5004 case OP_LCALL_MEMBASE:
5005 case OP_VCALL_MEMBASE:
5006 case OP_VCALL2_MEMBASE:
5007 case OP_VOIDCALL_MEMBASE:
5008 case OP_CALL_MEMBASE:
5009 call = (MonoCallInst*)ins;
5011 amd64_call_membase (code, ins->sreg1, ins->inst_offset);
5012 ins->flags |= MONO_INST_GC_CALLSITE;
5013 ins->backend.pc_offset = code - cfg->native_code;
5014 code = emit_move_return_value (cfg, ins, code);
5018 MonoInst *var = cfg->dyn_call_var;
5020 g_assert (var->opcode == OP_REGOFFSET);
5022 /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
5023 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
5025 amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
5027 /* Save args buffer */
5028 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
5030 /* Set argument registers */
5031 for (i = 0; i < PARAM_REGS; ++i)
5032 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
5035 amd64_call_reg (code, AMD64_R10);
5037 ins->flags |= MONO_INST_GC_CALLSITE;
5038 ins->backend.pc_offset = code - cfg->native_code;
5041 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5042 amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5045 case OP_AMD64_SAVE_SP_TO_LMF: {
5046 MonoInst *lmf_var = cfg->lmf_var;
5047 amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5051 g_assert_not_reached ();
5052 amd64_push_reg (code, ins->sreg1);
5054 case OP_X86_PUSH_IMM:
5055 g_assert_not_reached ();
5056 g_assert (amd64_is_imm32 (ins->inst_imm));
5057 amd64_push_imm (code, ins->inst_imm);
5059 case OP_X86_PUSH_MEMBASE:
5060 g_assert_not_reached ();
5061 amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5063 case OP_X86_PUSH_OBJ: {
5064 int size = ALIGN_TO (ins->inst_imm, 8);
5066 g_assert_not_reached ();
5068 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5069 amd64_push_reg (code, AMD64_RDI);
5070 amd64_push_reg (code, AMD64_RSI);
5071 amd64_push_reg (code, AMD64_RCX);
5072 if (ins->inst_offset)
5073 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5075 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5076 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5077 amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5079 amd64_prefix (code, X86_REP_PREFIX);
5081 amd64_pop_reg (code, AMD64_RCX);
5082 amd64_pop_reg (code, AMD64_RSI);
5083 amd64_pop_reg (code, AMD64_RDI);
5086 case OP_GENERIC_CLASS_INIT: {
5087 static int byte_offset = -1;
5088 static guint8 bitmask;
5091 g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5093 if (byte_offset < 0)
5094 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5096 amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5098 amd64_branch8 (code, X86_CC_NZ, -1, 1);
5100 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5101 ins->flags |= MONO_INST_GC_CALLSITE;
5102 ins->backend.pc_offset = code - cfg->native_code;
5104 x86_patch (jump, code);
5109 amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5111 case OP_X86_LEA_MEMBASE:
5112 amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5115 amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5118 /* keep alignment */
5119 amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5120 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5121 code = mono_emit_stack_alloc (cfg, code, ins);
5122 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5123 if (cfg->param_area)
5124 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5126 case OP_LOCALLOC_IMM: {
5127 guint32 size = ins->inst_imm;
5128 size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5130 if (ins->flags & MONO_INST_INIT) {
5134 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5135 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5137 for (i = 0; i < size; i += 8)
5138 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5139 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5141 amd64_mov_reg_imm (code, ins->dreg, size);
5142 ins->sreg1 = ins->dreg;
5144 code = mono_emit_stack_alloc (cfg, code, ins);
5145 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5148 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5149 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5151 if (cfg->param_area)
5152 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5156 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5157 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5158 (gpointer)"mono_arch_throw_exception", FALSE);
5159 ins->flags |= MONO_INST_GC_CALLSITE;
5160 ins->backend.pc_offset = code - cfg->native_code;
5164 amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5165 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5166 (gpointer)"mono_arch_rethrow_exception", FALSE);
5167 ins->flags |= MONO_INST_GC_CALLSITE;
5168 ins->backend.pc_offset = code - cfg->native_code;
5171 case OP_CALL_HANDLER:
5173 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5174 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5175 amd64_call_imm (code, 0);
5176 mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5177 /* Restore stack alignment */
5178 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5180 case OP_START_HANDLER: {
5181 /* Even though we're saving RSP, use sizeof */
5182 /* gpointer because spvar is of type IntPtr */
5183 /* see: mono_create_spvar_for_region */
5184 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5185 amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5187 if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5188 MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5190 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5194 case OP_ENDFINALLY: {
5195 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5196 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5200 case OP_ENDFILTER: {
5201 MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5202 amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5203 /* The local allocator will put the result into RAX */
5208 if (ins->dreg != AMD64_RAX)
5209 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5212 ins->inst_c0 = code - cfg->native_code;
5215 //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5216 //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5218 if (ins->inst_target_bb->native_offset) {
5219 amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5221 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5222 if ((cfg->opt & MONO_OPT_BRANCH) &&
5223 x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5224 x86_jump8 (code, 0);
5226 x86_jump32 (code, 0);
5230 amd64_jump_reg (code, ins->sreg1);
5253 amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5254 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5256 case OP_COND_EXC_EQ:
5257 case OP_COND_EXC_NE_UN:
5258 case OP_COND_EXC_LT:
5259 case OP_COND_EXC_LT_UN:
5260 case OP_COND_EXC_GT:
5261 case OP_COND_EXC_GT_UN:
5262 case OP_COND_EXC_GE:
5263 case OP_COND_EXC_GE_UN:
5264 case OP_COND_EXC_LE:
5265 case OP_COND_EXC_LE_UN:
5266 case OP_COND_EXC_IEQ:
5267 case OP_COND_EXC_INE_UN:
5268 case OP_COND_EXC_ILT:
5269 case OP_COND_EXC_ILT_UN:
5270 case OP_COND_EXC_IGT:
5271 case OP_COND_EXC_IGT_UN:
5272 case OP_COND_EXC_IGE:
5273 case OP_COND_EXC_IGE_UN:
5274 case OP_COND_EXC_ILE:
5275 case OP_COND_EXC_ILE_UN:
5276 EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5278 case OP_COND_EXC_OV:
5279 case OP_COND_EXC_NO:
5281 case OP_COND_EXC_NC:
5282 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5283 (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5285 case OP_COND_EXC_IOV:
5286 case OP_COND_EXC_INO:
5287 case OP_COND_EXC_IC:
5288 case OP_COND_EXC_INC:
5289 EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5290 (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5293 /* floating point opcodes */
5295 double d = *(double *)ins->inst_p0;
5297 if ((d == 0.0) && (mono_signbit (d) == 0)) {
5298 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5301 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5302 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5307 float f = *(float *)ins->inst_p0;
5309 if ((f == 0.0) && (mono_signbit (f) == 0)) {
5311 amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5313 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5316 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5317 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5319 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5323 case OP_STORER8_MEMBASE_REG:
5324 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5326 case OP_LOADR8_MEMBASE:
5327 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5329 case OP_STORER4_MEMBASE_REG:
5331 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5333 /* This requires a double->single conversion */
5334 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5335 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5338 case OP_LOADR4_MEMBASE:
5340 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5342 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5343 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5346 case OP_ICONV_TO_R4:
5348 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5350 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5351 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5354 case OP_ICONV_TO_R8:
5355 amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5357 case OP_LCONV_TO_R4:
5359 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5361 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5362 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5365 case OP_LCONV_TO_R8:
5366 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5368 case OP_FCONV_TO_R4:
5370 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5372 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5373 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5376 case OP_FCONV_TO_I1:
5377 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5379 case OP_FCONV_TO_U1:
5380 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5382 case OP_FCONV_TO_I2:
5383 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5385 case OP_FCONV_TO_U2:
5386 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5388 case OP_FCONV_TO_U4:
5389 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5391 case OP_FCONV_TO_I4:
5393 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5395 case OP_FCONV_TO_I8:
5396 code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5399 case OP_RCONV_TO_I1:
5400 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5401 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5403 case OP_RCONV_TO_U1:
5404 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5405 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5407 case OP_RCONV_TO_I2:
5408 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5409 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5411 case OP_RCONV_TO_U2:
5412 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5413 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5415 case OP_RCONV_TO_I4:
5416 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5418 case OP_RCONV_TO_U4:
5419 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5421 case OP_RCONV_TO_I8:
5422 amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5424 case OP_RCONV_TO_R8:
5425 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5427 case OP_RCONV_TO_R4:
5428 if (ins->dreg != ins->sreg1)
5429 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5432 case OP_LCONV_TO_R_UN: {
5435 /* Based on gcc code */
5436 amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5437 br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5440 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5441 br [1] = code; x86_jump8 (code, 0);
5442 amd64_patch (br [0], code);
5445 /* Save to the red zone */
5446 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5447 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5448 amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5449 amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5450 amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5451 amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5452 amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5453 amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5454 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5456 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5457 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5458 amd64_patch (br [1], code);
5461 case OP_LCONV_TO_OVF_U4:
5462 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5463 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5464 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5466 case OP_LCONV_TO_OVF_I4_UN:
5467 amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5468 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5469 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5472 if (ins->dreg != ins->sreg1)
5473 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5476 if (ins->dreg != ins->sreg1)
5477 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5479 case OP_MOVE_F_TO_I4:
5481 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5483 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5484 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5487 case OP_MOVE_I4_TO_F:
5488 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5490 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5492 case OP_MOVE_F_TO_I8:
5493 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5495 case OP_MOVE_I8_TO_F:
5496 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5499 amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5502 amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5505 amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5508 amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5511 static double r8_0 = -0.0;
5513 g_assert (ins->sreg1 == ins->dreg);
5515 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5516 amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5520 EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5523 EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5526 static guint64 d = 0x7fffffffffffffffUL;
5528 g_assert (ins->sreg1 == ins->dreg);
5530 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5531 amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5535 EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5539 amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5542 amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5545 amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5548 amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5551 static float r4_0 = -0.0;
5553 g_assert (ins->sreg1 == ins->dreg);
5555 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5556 amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5557 amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5562 g_assert (cfg->opt & MONO_OPT_CMOV);
5563 g_assert (ins->dreg == ins->sreg1);
5564 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5565 amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5568 g_assert (cfg->opt & MONO_OPT_CMOV);
5569 g_assert (ins->dreg == ins->sreg1);
5570 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5571 amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5574 g_assert (cfg->opt & MONO_OPT_CMOV);
5575 g_assert (ins->dreg == ins->sreg1);
5576 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5577 amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5580 g_assert (cfg->opt & MONO_OPT_CMOV);
5581 g_assert (ins->dreg == ins->sreg1);
5582 amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5583 amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5586 g_assert (cfg->opt & MONO_OPT_CMOV);
5587 g_assert (ins->dreg == ins->sreg1);
5588 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5589 amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5592 g_assert (cfg->opt & MONO_OPT_CMOV);
5593 g_assert (ins->dreg == ins->sreg1);
5594 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5595 amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5598 g_assert (cfg->opt & MONO_OPT_CMOV);
5599 g_assert (ins->dreg == ins->sreg1);
5600 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5601 amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5604 g_assert (cfg->opt & MONO_OPT_CMOV);
5605 g_assert (ins->dreg == ins->sreg1);
5606 amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5607 amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5613 * The two arguments are swapped because the fbranch instructions
5614 * depend on this for the non-sse case to work.
5616 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5620 * FIXME: Get rid of this.
5621 * The two arguments are swapped because the fbranch instructions
5622 * depend on this for the non-sse case to work.
5624 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5628 /* zeroing the register at the start results in
5629 * shorter and faster code (we can also remove the widening op)
5631 guchar *unordered_check;
5633 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5634 amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5635 unordered_check = code;
5636 x86_branch8 (code, X86_CC_P, 0, FALSE);
5638 if (ins->opcode == OP_FCEQ) {
5639 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5640 amd64_patch (unordered_check, code);
5642 guchar *jump_to_end;
5643 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5645 x86_jump8 (code, 0);
5646 amd64_patch (unordered_check, code);
5647 amd64_inc_reg (code, ins->dreg);
5648 amd64_patch (jump_to_end, code);
5654 /* zeroing the register at the start results in
5655 * shorter and faster code (we can also remove the widening op)
5657 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5658 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5659 if (ins->opcode == OP_FCLT_UN) {
5660 guchar *unordered_check = code;
5661 guchar *jump_to_end;
5662 x86_branch8 (code, X86_CC_P, 0, FALSE);
5663 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5665 x86_jump8 (code, 0);
5666 amd64_patch (unordered_check, code);
5667 amd64_inc_reg (code, ins->dreg);
5668 amd64_patch (jump_to_end, code);
5670 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5675 guchar *unordered_check;
5676 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5677 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5678 unordered_check = code;
5679 x86_branch8 (code, X86_CC_P, 0, FALSE);
5680 amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5681 amd64_patch (unordered_check, code);
5686 /* zeroing the register at the start results in
5687 * shorter and faster code (we can also remove the widening op)
5689 guchar *unordered_check;
5691 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5692 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5693 if (ins->opcode == OP_FCGT) {
5694 unordered_check = code;
5695 x86_branch8 (code, X86_CC_P, 0, FALSE);
5696 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5697 amd64_patch (unordered_check, code);
5699 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5704 guchar *unordered_check;
5705 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5706 amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5707 unordered_check = code;
5708 x86_branch8 (code, X86_CC_P, 0, FALSE);
5709 amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5710 amd64_patch (unordered_check, code);
5720 gboolean unordered = FALSE;
5722 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5723 amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5725 switch (ins->opcode) {
5727 x86_cond = X86_CC_EQ;
5730 x86_cond = X86_CC_LT;
5733 x86_cond = X86_CC_GT;
5736 x86_cond = X86_CC_GT;
5740 x86_cond = X86_CC_LT;
5744 g_assert_not_reached ();
5749 guchar *unordered_check;
5750 guchar *jump_to_end;
5752 unordered_check = code;
5753 x86_branch8 (code, X86_CC_P, 0, FALSE);
5754 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5756 x86_jump8 (code, 0);
5757 amd64_patch (unordered_check, code);
5758 amd64_inc_reg (code, ins->dreg);
5759 amd64_patch (jump_to_end, code);
5761 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5765 case OP_FCLT_MEMBASE:
5766 case OP_FCGT_MEMBASE:
5767 case OP_FCLT_UN_MEMBASE:
5768 case OP_FCGT_UN_MEMBASE:
5769 case OP_FCEQ_MEMBASE: {
5770 guchar *unordered_check, *jump_to_end;
5773 amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5774 amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5776 switch (ins->opcode) {
5777 case OP_FCEQ_MEMBASE:
5778 x86_cond = X86_CC_EQ;
5780 case OP_FCLT_MEMBASE:
5781 case OP_FCLT_UN_MEMBASE:
5782 x86_cond = X86_CC_LT;
5784 case OP_FCGT_MEMBASE:
5785 case OP_FCGT_UN_MEMBASE:
5786 x86_cond = X86_CC_GT;
5789 g_assert_not_reached ();
5792 unordered_check = code;
5793 x86_branch8 (code, X86_CC_P, 0, FALSE);
5794 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5796 switch (ins->opcode) {
5797 case OP_FCEQ_MEMBASE:
5798 case OP_FCLT_MEMBASE:
5799 case OP_FCGT_MEMBASE:
5800 amd64_patch (unordered_check, code);
5802 case OP_FCLT_UN_MEMBASE:
5803 case OP_FCGT_UN_MEMBASE:
5805 x86_jump8 (code, 0);
5806 amd64_patch (unordered_check, code);
5807 amd64_inc_reg (code, ins->dreg);
5808 amd64_patch (jump_to_end, code);
5816 guchar *jump = code;
5817 x86_branch8 (code, X86_CC_P, 0, TRUE);
5818 EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5819 amd64_patch (jump, code);
5823 /* Branch if C013 != 100 */
5824 /* branch if !ZF or (PF|CF) */
5825 EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5826 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5827 EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5830 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5833 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5834 EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5838 if (ins->opcode == OP_FBGT) {
5841 /* skip branch if C1=1 */
5843 x86_branch8 (code, X86_CC_P, 0, FALSE);
5844 /* branch if (C0 | C3) = 1 */
5845 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5846 amd64_patch (br1, code);
5849 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5853 /* Branch if C013 == 100 or 001 */
5856 /* skip branch if C1=1 */
5858 x86_branch8 (code, X86_CC_P, 0, FALSE);
5859 /* branch if (C0 | C3) = 1 */
5860 EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5861 amd64_patch (br1, code);
5865 /* Branch if C013 == 000 */
5866 EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5869 /* Branch if C013=000 or 100 */
5872 /* skip branch if C1=1 */
5874 x86_branch8 (code, X86_CC_P, 0, FALSE);
5875 /* branch if C0=0 */
5876 EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5877 amd64_patch (br1, code);
5881 /* Branch if C013 != 001 */
5882 EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5883 EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5886 /* Transfer value to the fp stack */
5887 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5888 amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5889 amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5891 amd64_push_reg (code, AMD64_RAX);
5893 amd64_fnstsw (code);
5894 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5895 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5896 amd64_pop_reg (code, AMD64_RAX);
5897 amd64_fstp (code, 0);
5898 EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5899 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5902 code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5905 case OP_TLS_GET_REG:
5906 code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5909 code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5912 case OP_TLS_SET_REG: {
5913 code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5916 case OP_MEMORY_BARRIER: {
5917 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5921 case OP_ATOMIC_ADD_I4:
5922 case OP_ATOMIC_ADD_I8: {
5923 int dreg = ins->dreg;
5924 guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5926 if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5929 amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5930 amd64_prefix (code, X86_LOCK_PREFIX);
5931 amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5932 /* dreg contains the old value, add with sreg2 value */
5933 amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5935 if (ins->dreg != dreg)
5936 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5940 case OP_ATOMIC_EXCHANGE_I4:
5941 case OP_ATOMIC_EXCHANGE_I8: {
5942 guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5944 /* LOCK prefix is implied. */
5945 amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5946 amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5947 amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5950 case OP_ATOMIC_CAS_I4:
5951 case OP_ATOMIC_CAS_I8: {
5954 if (ins->opcode == OP_ATOMIC_CAS_I8)
5960 * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5961 * an explanation of how this works.
5963 g_assert (ins->sreg3 == AMD64_RAX);
5964 g_assert (ins->sreg1 != AMD64_RAX);
5965 g_assert (ins->sreg1 != ins->sreg2);
5967 amd64_prefix (code, X86_LOCK_PREFIX);
5968 amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
5970 if (ins->dreg != AMD64_RAX)
5971 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
5974 case OP_ATOMIC_LOAD_I1: {
5975 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
5978 case OP_ATOMIC_LOAD_U1: {
5979 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
5982 case OP_ATOMIC_LOAD_I2: {
5983 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
5986 case OP_ATOMIC_LOAD_U2: {
5987 amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
5990 case OP_ATOMIC_LOAD_I4: {
5991 amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5994 case OP_ATOMIC_LOAD_U4:
5995 case OP_ATOMIC_LOAD_I8:
5996 case OP_ATOMIC_LOAD_U8: {
5997 amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
6000 case OP_ATOMIC_LOAD_R4: {
6001 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
6002 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6005 case OP_ATOMIC_LOAD_R8: {
6006 amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
6009 case OP_ATOMIC_STORE_I1:
6010 case OP_ATOMIC_STORE_U1:
6011 case OP_ATOMIC_STORE_I2:
6012 case OP_ATOMIC_STORE_U2:
6013 case OP_ATOMIC_STORE_I4:
6014 case OP_ATOMIC_STORE_U4:
6015 case OP_ATOMIC_STORE_I8:
6016 case OP_ATOMIC_STORE_U8: {
6019 switch (ins->opcode) {
6020 case OP_ATOMIC_STORE_I1:
6021 case OP_ATOMIC_STORE_U1:
6024 case OP_ATOMIC_STORE_I2:
6025 case OP_ATOMIC_STORE_U2:
6028 case OP_ATOMIC_STORE_I4:
6029 case OP_ATOMIC_STORE_U4:
6032 case OP_ATOMIC_STORE_I8:
6033 case OP_ATOMIC_STORE_U8:
6038 amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
6040 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6044 case OP_ATOMIC_STORE_R4: {
6045 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6046 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6048 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6052 case OP_ATOMIC_STORE_R8: {
6055 amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6059 if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6063 case OP_CARD_TABLE_WBARRIER: {
6064 int ptr = ins->sreg1;
6065 int value = ins->sreg2;
6067 int nursery_shift, card_table_shift;
6068 gpointer card_table_mask;
6069 size_t nursery_size;
6071 gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6072 guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6073 guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6075 /*If either point to the stack we can simply avoid the WB. This happens due to
6076 * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6078 if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6082 * We need one register we can clobber, we choose EDX and make sreg1
6083 * fixed EAX to work around limitations in the local register allocator.
6084 * sreg2 might get allocated to EDX, but that is not a problem since
6085 * we use it before clobbering EDX.
6087 g_assert (ins->sreg1 == AMD64_RAX);
6090 * This is the code we produce:
6093 * edx >>= nursery_shift
6094 * cmp edx, (nursery_start >> nursery_shift)
6097 * edx >>= card_table_shift
6103 if (mono_gc_card_table_nursery_check ()) {
6104 if (value != AMD64_RDX)
6105 amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6106 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6107 if (shifted_nursery_start >> 31) {
6109 * The value we need to compare against is 64 bits, so we need
6110 * another spare register. We use RBX, which we save and
6113 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6114 amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6115 amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6116 amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6118 amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6120 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6122 amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6123 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6124 if (card_table_mask)
6125 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6127 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6128 amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6130 amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6132 if (mono_gc_card_table_nursery_check ())
6133 x86_patch (br, code);
6136 #ifdef MONO_ARCH_SIMD_INTRINSICS
6137 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6139 amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6142 amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6145 amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6148 amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6151 amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6154 amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6157 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6158 amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6161 amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6164 amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6167 amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6170 amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6173 amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6176 amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6179 amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6182 amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6185 amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6188 amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6191 amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6194 amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6197 case OP_PSHUFLEW_HIGH:
6198 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6199 amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6201 case OP_PSHUFLEW_LOW:
6202 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6203 amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6206 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6207 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6210 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6211 amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6214 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6215 amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6219 amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6222 amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6225 amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6228 amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6231 amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6234 amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6237 g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6238 amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6241 amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6244 amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6247 amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6250 amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6253 amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6256 amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6259 amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6262 amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6265 amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6268 case OP_EXTRACT_MASK:
6269 amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6273 amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6276 amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6279 amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6283 amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6286 amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6289 amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6292 amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6296 amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6299 amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6302 amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6305 amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6309 amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6312 amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6315 amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6319 amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6322 amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6325 amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6329 amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6332 amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6336 amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6339 amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6342 amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6346 amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6349 amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6352 amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6356 amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6359 amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6362 amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6365 amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6369 amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6372 amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6375 amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6378 amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6381 case OP_PSUM_ABS_DIFF:
6382 amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6385 case OP_UNPACK_LOWB:
6386 amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6388 case OP_UNPACK_LOWW:
6389 amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6391 case OP_UNPACK_LOWD:
6392 amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6394 case OP_UNPACK_LOWQ:
6395 amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6397 case OP_UNPACK_LOWPS:
6398 amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6400 case OP_UNPACK_LOWPD:
6401 amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6404 case OP_UNPACK_HIGHB:
6405 amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6407 case OP_UNPACK_HIGHW:
6408 amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6410 case OP_UNPACK_HIGHD:
6411 amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6413 case OP_UNPACK_HIGHQ:
6414 amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6416 case OP_UNPACK_HIGHPS:
6417 amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6419 case OP_UNPACK_HIGHPD:
6420 amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6424 amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6427 amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6430 amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6433 amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6436 case OP_PADDB_SAT_UN:
6437 amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6439 case OP_PSUBB_SAT_UN:
6440 amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6442 case OP_PADDW_SAT_UN:
6443 amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6445 case OP_PSUBW_SAT_UN:
6446 amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6450 amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6453 amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6456 amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6459 amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6463 amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6466 amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6469 amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6471 case OP_PMULW_HIGH_UN:
6472 amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6475 amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6479 amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6482 amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6486 amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6489 amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6493 amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6496 amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6500 amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6503 amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6507 amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6510 amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6514 amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6517 amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6521 amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6524 amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6527 /*TODO: This is appart of the sse spec but not added
6529 amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6532 amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6537 amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6540 amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6543 amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6546 amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6549 amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6552 amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6555 amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6558 amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6561 amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6564 amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6568 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6571 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6575 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6576 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6578 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6583 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6585 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6586 amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6590 /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6592 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6593 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6594 amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6598 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6600 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6603 amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6605 case OP_EXTRACTX_U2:
6606 amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6608 case OP_INSERTX_U1_SLOW:
6609 /*sreg1 is the extracted ireg (scratch)
6610 /sreg2 is the to be inserted ireg (scratch)
6611 /dreg is the xreg to receive the value*/
6613 /*clear the bits from the extracted word*/
6614 amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6615 /*shift the value to insert if needed*/
6616 if (ins->inst_c0 & 1)
6617 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6618 /*join them together*/
6619 amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6620 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6622 case OP_INSERTX_I4_SLOW:
6623 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6624 amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6625 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6627 case OP_INSERTX_I8_SLOW:
6628 amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6630 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6632 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6635 case OP_INSERTX_R4_SLOW:
6636 switch (ins->inst_c0) {
6639 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6641 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6644 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6646 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6648 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6649 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6652 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6654 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6656 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6657 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6660 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6662 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6664 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6665 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6669 case OP_INSERTX_R8_SLOW:
6671 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6673 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6675 case OP_STOREX_MEMBASE_REG:
6676 case OP_STOREX_MEMBASE:
6677 amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6679 case OP_LOADX_MEMBASE:
6680 amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6682 case OP_LOADX_ALIGNED_MEMBASE:
6683 amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6685 case OP_STOREX_ALIGNED_MEMBASE_REG:
6686 amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6688 case OP_STOREX_NTA_MEMBASE_REG:
6689 amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6691 case OP_PREFETCH_MEMBASE:
6692 amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6696 /*FIXME the peephole pass should have killed this*/
6697 if (ins->dreg != ins->sreg1)
6698 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6701 amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6703 case OP_ICONV_TO_R4_RAW:
6704 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6707 case OP_FCONV_TO_R8_X:
6708 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6711 case OP_XCONV_R8_TO_I4:
6712 amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6713 switch (ins->backend.source_opcode) {
6714 case OP_FCONV_TO_I1:
6715 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6717 case OP_FCONV_TO_U1:
6718 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6720 case OP_FCONV_TO_I2:
6721 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6723 case OP_FCONV_TO_U2:
6724 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6730 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6731 amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6732 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6735 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6736 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6739 amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6740 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6744 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6746 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6747 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6749 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6752 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6753 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6756 case OP_LIVERANGE_START: {
6757 if (cfg->verbose_level > 1)
6758 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6759 MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6762 case OP_LIVERANGE_END: {
6763 if (cfg->verbose_level > 1)
6764 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6765 MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6768 case OP_GC_SAFE_POINT: {
6769 const char *polling_func = NULL;
6770 int compare_val = 0;
6773 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6774 polling_func = "mono_nacl_gc";
6775 compare_val = 0xFFFFFFFF;
6777 g_assert (mono_threads_is_coop_enabled ());
6778 polling_func = "mono_threads_state_poll";
6782 amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6783 br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6784 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6785 amd64_patch (br[0], code);
6789 case OP_GC_LIVENESS_DEF:
6790 case OP_GC_LIVENESS_USE:
6791 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6792 ins->backend.pc_offset = code - cfg->native_code;
6794 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6795 ins->backend.pc_offset = code - cfg->native_code;
6796 bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6799 g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6800 g_assert_not_reached ();
6803 if ((code - cfg->native_code - offset) > max_len) {
6804 #if !defined(__native_client_codegen__)
6805 g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6806 mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6807 g_assert_not_reached ();
6812 cfg->code_len = code - cfg->native_code;
6815 #endif /* DISABLE_JIT */
6818 mono_arch_register_lowlevel_calls (void)
6820 /* The signature doesn't matter */
6821 mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6825 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6827 unsigned char *ip = ji->ip.i + code;
6830 * Debug code to help track down problems where the target of a near call is
6833 if (amd64_is_near_call (ip)) {
6834 gint64 disp = (guint8*)target - (guint8*)ip;
6836 if (!amd64_is_imm32 (disp)) {
6837 printf ("TYPE: %d\n", ji->type);
6839 case MONO_PATCH_INFO_INTERNAL_METHOD:
6840 printf ("V: %s\n", ji->data.name);
6842 case MONO_PATCH_INFO_METHOD_JUMP:
6843 case MONO_PATCH_INFO_METHOD:
6844 printf ("V: %s\n", ji->data.method->name);
6852 amd64_patch (ip, (gpointer)target);
6858 get_max_epilog_size (MonoCompile *cfg)
6860 int max_epilog_size = 16;
6862 if (cfg->method->save_lmf)
6863 max_epilog_size += 256;
6865 if (mono_jit_trace_calls != NULL)
6866 max_epilog_size += 50;
6868 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6869 max_epilog_size += 50;
6871 max_epilog_size += (AMD64_NREG * 2);
6873 return max_epilog_size;
6877 * This macro is used for testing whenever the unwinder works correctly at every point
6878 * where an async exception can happen.
6880 /* This will generate a SIGSEGV at the given point in the code */
6881 #define async_exc_point(code) do { \
6882 if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6883 if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6884 amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6885 cfg->arch.async_point_count ++; \
6890 mono_arch_emit_prolog (MonoCompile *cfg)
6892 MonoMethod *method = cfg->method;
6894 MonoMethodSignature *sig;
6896 int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6899 MonoInst *lmf_var = cfg->lmf_var;
6900 gboolean args_clobbered = FALSE;
6901 gboolean trace = FALSE;
6902 #ifdef __native_client_codegen__
6903 guint alignment_check;
6906 cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6908 #if defined(__default_codegen__)
6909 code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6910 #elif defined(__native_client_codegen__)
6911 /* native_code_alloc is not 32-byte aligned, native_code is. */
6912 cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6914 /* Align native_code to next nearest kNaclAlignment byte. */
6915 cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6916 cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6918 code = cfg->native_code;
6920 alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6921 g_assert (alignment_check == 0);
6924 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6927 /* Amount of stack space allocated by register saving code */
6930 /* Offset between RSP and the CFA */
6934 * The prolog consists of the following parts:
6936 * - push rbp, mov rbp, rsp
6937 * - save callee saved regs using pushes
6939 * - save rgctx if needed
6940 * - save lmf if needed
6943 * - save rgctx if needed
6944 * - save lmf if needed
6945 * - save callee saved regs using moves
6950 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6951 // IP saved at CFA - 8
6952 mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6953 async_exc_point (code);
6954 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6956 if (!cfg->arch.omit_fp) {
6957 amd64_push_reg (code, AMD64_RBP);
6959 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6960 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6961 async_exc_point (code);
6963 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6965 /* These are handled automatically by the stack marking code */
6966 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6968 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
6969 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
6970 async_exc_point (code);
6972 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6976 /* The param area is always at offset 0 from sp */
6977 /* This needs to be allocated here, since it has to come after the spill area */
6978 if (cfg->param_area) {
6979 if (cfg->arch.omit_fp)
6981 g_assert_not_reached ();
6982 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
6985 if (cfg->arch.omit_fp) {
6987 * On enter, the stack is misaligned by the pushing of the return
6988 * address. It is either made aligned by the pushing of %rbp, or by
6991 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
6992 if ((alloc_size % 16) == 0) {
6994 /* Mark the padding slot as NOREF */
6995 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
6998 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
6999 if (cfg->stack_offset != alloc_size) {
7000 /* Mark the padding slot as NOREF */
7001 mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
7003 cfg->arch.sp_fp_offset = alloc_size;
7007 cfg->arch.stack_alloc_size = alloc_size;
7009 /* Allocate stack frame */
7011 /* See mono_emit_stack_alloc */
7012 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
7013 guint32 remaining_size = alloc_size;
7014 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
7015 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
7016 guint32 offset = code - cfg->native_code;
7017 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
7018 while (required_code_size >= (cfg->code_size - offset))
7019 cfg->code_size *= 2;
7020 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7021 code = cfg->native_code + offset;
7022 cfg->stat_code_reallocs++;
7025 while (remaining_size >= 0x1000) {
7026 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
7027 if (cfg->arch.omit_fp) {
7028 cfa_offset += 0x1000;
7029 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7031 async_exc_point (code);
7033 if (cfg->arch.omit_fp)
7034 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
7037 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
7038 remaining_size -= 0x1000;
7040 if (remaining_size) {
7041 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7042 if (cfg->arch.omit_fp) {
7043 cfa_offset += remaining_size;
7044 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7045 async_exc_point (code);
7048 if (cfg->arch.omit_fp)
7049 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7053 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7054 if (cfg->arch.omit_fp) {
7055 cfa_offset += alloc_size;
7056 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7057 async_exc_point (code);
7062 /* Stack alignment check */
7065 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7066 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7067 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7068 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
7069 amd64_breakpoint (code);
7073 if (mini_get_debug_options ()->init_stacks) {
7074 /* Fill the stack frame with a dummy value to force deterministic behavior */
7076 /* Save registers to the red zone */
7077 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7078 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7080 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7081 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7082 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7085 #if defined(__default_codegen__)
7086 amd64_prefix (code, X86_REP_PREFIX);
7088 #elif defined(__native_client_codegen__)
7089 /* NaCl stos pseudo-instruction */
7090 amd64_codegen_pre (code);
7091 /* First, clear the upper 32 bits of RDI (mov %edi, %edi) */
7092 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7093 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7094 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7095 amd64_prefix (code, X86_REP_PREFIX);
7097 amd64_codegen_post (code);
7098 #endif /* __native_client_codegen__ */
7100 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7101 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7105 if (method->save_lmf)
7106 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7108 /* Save callee saved registers */
7109 if (cfg->arch.omit_fp) {
7110 save_area_offset = cfg->arch.reg_save_area_offset;
7111 /* Save caller saved registers after sp is adjusted */
7112 /* The registers are saved at the bottom of the frame */
7113 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7115 /* The registers are saved just below the saved rbp */
7116 save_area_offset = cfg->arch.reg_save_area_offset;
7119 for (i = 0; i < AMD64_NREG; ++i) {
7120 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7121 amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7123 if (cfg->arch.omit_fp) {
7124 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7125 /* These are handled automatically by the stack marking code */
7126 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7128 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7132 save_area_offset += 8;
7133 async_exc_point (code);
7137 /* store runtime generic context */
7138 if (cfg->rgctx_var) {
7139 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7140 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7142 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7144 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7145 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7148 /* compute max_length in order to use short forward jumps */
7149 max_epilog_size = get_max_epilog_size (cfg);
7150 if (cfg->opt & MONO_OPT_BRANCH) {
7151 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7155 if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7157 /* max alignment for loops */
7158 if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7159 max_length += LOOP_ALIGNMENT;
7160 #ifdef __native_client_codegen__
7161 /* max alignment for native client */
7162 max_length += kNaClAlignment;
7165 MONO_BB_FOR_EACH_INS (bb, ins) {
7166 #ifdef __native_client_codegen__
7168 int space_in_block = kNaClAlignment -
7169 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7170 int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7171 if (space_in_block < max_len && max_len < kNaClAlignment) {
7172 max_length += space_in_block;
7175 #endif /*__native_client_codegen__*/
7176 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7179 /* Take prolog and epilog instrumentation into account */
7180 if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7181 max_length += max_epilog_size;
7183 bb->max_length = max_length;
7187 sig = mono_method_signature (method);
7190 cinfo = (CallInfo *)cfg->arch.cinfo;
7192 if (sig->ret->type != MONO_TYPE_VOID) {
7193 /* Save volatile arguments to the stack */
7194 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7195 amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7198 /* Keep this in sync with emit_load_volatile_arguments */
7199 for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7200 ArgInfo *ainfo = cinfo->args + i;
7202 ins = cfg->args [i];
7204 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7205 /* Unused arguments */
7208 /* Save volatile arguments to the stack */
7209 if (ins->opcode != OP_REGVAR) {
7210 switch (ainfo->storage) {
7216 if (stack_offset & 0x1)
7218 else if (stack_offset & 0x2)
7220 else if (stack_offset & 0x4)
7225 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7228 * Save the original location of 'this',
7229 * get_generic_info_from_stack_frame () needs this to properly look up
7230 * the argument value during the handling of async exceptions.
7232 if (ins == cfg->args [0]) {
7233 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7234 mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7238 case ArgInFloatSSEReg:
7239 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7241 case ArgInDoubleSSEReg:
7242 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7244 case ArgValuetypeInReg:
7245 for (quad = 0; quad < 2; quad ++) {
7246 switch (ainfo->pair_storage [quad]) {
7248 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7250 case ArgInFloatSSEReg:
7251 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7253 case ArgInDoubleSSEReg:
7254 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7259 g_assert_not_reached ();
7263 case ArgValuetypeAddrInIReg:
7264 if (ainfo->pair_storage [0] == ArgInIReg)
7265 amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0], sizeof (gpointer));
7267 case ArgGSharedVtInReg:
7268 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7274 /* Argument allocated to (non-volatile) register */
7275 switch (ainfo->storage) {
7277 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7280 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7283 g_assert_not_reached ();
7286 if (ins == cfg->args [0]) {
7287 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7288 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7293 if (cfg->method->save_lmf)
7294 args_clobbered = TRUE;
7297 args_clobbered = TRUE;
7298 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7301 if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7302 args_clobbered = TRUE;
7305 * Optimize the common case of the first bblock making a call with the same
7306 * arguments as the method. This works because the arguments are still in their
7307 * original argument registers.
7308 * FIXME: Generalize this
7310 if (!args_clobbered) {
7311 MonoBasicBlock *first_bb = cfg->bb_entry;
7313 int filter = FILTER_IL_SEQ_POINT;
7315 next = mono_bb_first_inst (first_bb, filter);
7316 if (!next && first_bb->next_bb) {
7317 first_bb = first_bb->next_bb;
7318 next = mono_bb_first_inst (first_bb, filter);
7321 if (first_bb->in_count > 1)
7324 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7325 ArgInfo *ainfo = cinfo->args + i;
7326 gboolean match = FALSE;
7328 ins = cfg->args [i];
7329 if (ins->opcode != OP_REGVAR) {
7330 switch (ainfo->storage) {
7332 if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7333 if (next->dreg == ainfo->reg) {
7337 next->opcode = OP_MOVE;
7338 next->sreg1 = ainfo->reg;
7339 /* Only continue if the instruction doesn't change argument regs */
7340 if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7350 /* Argument allocated to (non-volatile) register */
7351 switch (ainfo->storage) {
7353 if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7364 next = mono_inst_next (next, filter);
7365 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7372 if (cfg->gen_sdb_seq_points) {
7373 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7375 /* Initialize seq_point_info_var */
7376 if (cfg->compile_aot) {
7377 /* Initialize the variable from a GOT slot */
7378 /* Same as OP_AOTCONST */
7379 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7380 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7381 g_assert (info_var->opcode == OP_REGOFFSET);
7382 amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7385 if (cfg->compile_aot) {
7386 /* Initialize ss_tramp_var */
7387 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7388 g_assert (ins->opcode == OP_REGOFFSET);
7390 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7391 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7392 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7394 /* Initialize ss_tramp_var */
7395 ins = (MonoInst *)cfg->arch.ss_tramp_var;
7396 g_assert (ins->opcode == OP_REGOFFSET);
7398 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7399 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7401 /* Initialize bp_tramp_var */
7402 ins = (MonoInst *)cfg->arch.bp_tramp_var;
7403 g_assert (ins->opcode == OP_REGOFFSET);
7405 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7406 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7410 cfg->code_len = code - cfg->native_code;
7412 g_assert (cfg->code_len < cfg->code_size);
7418 mono_arch_emit_epilog (MonoCompile *cfg)
7420 MonoMethod *method = cfg->method;
7423 int max_epilog_size;
7425 gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7426 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7428 max_epilog_size = get_max_epilog_size (cfg);
7430 while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7431 cfg->code_size *= 2;
7432 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7433 cfg->stat_code_reallocs++;
7435 code = cfg->native_code + cfg->code_len;
7437 cfg->has_unwind_info_for_epilog = TRUE;
7439 /* Mark the start of the epilog */
7440 mono_emit_unwind_op_mark_loc (cfg, code, 0);
7442 /* Save the uwind state which is needed by the out-of-line code */
7443 mono_emit_unwind_op_remember_state (cfg, code);
7445 if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7446 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7448 /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7450 if (method->save_lmf) {
7451 /* check if we need to restore protection of the stack after a stack overflow */
7452 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7454 code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7455 /* we load the value in a separate instruction: this mechanism may be
7456 * used later as a safer way to do thread interruption
7458 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7459 x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7461 x86_branch8 (code, X86_CC_Z, 0, FALSE);
7462 /* note that the call trampoline will preserve eax/edx */
7463 x86_call_reg (code, X86_ECX);
7464 x86_patch (patch, code);
7466 /* FIXME: maybe save the jit tls in the prolog */
7468 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7469 amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7473 /* Restore callee saved regs */
7474 for (i = 0; i < AMD64_NREG; ++i) {
7475 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7476 /* Restore only used_int_regs, not arch.saved_iregs */
7477 if (cfg->used_int_regs & (1 << i)) {
7478 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7479 mono_emit_unwind_op_same_value (cfg, code, i);
7480 async_exc_point (code);
7482 save_area_offset += 8;
7486 /* Load returned vtypes into registers if needed */
7487 cinfo = (CallInfo *)cfg->arch.cinfo;
7488 if (cinfo->ret.storage == ArgValuetypeInReg) {
7489 ArgInfo *ainfo = &cinfo->ret;
7490 MonoInst *inst = cfg->ret;
7492 for (quad = 0; quad < 2; quad ++) {
7493 switch (ainfo->pair_storage [quad]) {
7495 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7497 case ArgInFloatSSEReg:
7498 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7500 case ArgInDoubleSSEReg:
7501 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7506 g_assert_not_reached ();
7511 if (cfg->arch.omit_fp) {
7512 if (cfg->arch.stack_alloc_size) {
7513 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7517 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7519 mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7520 async_exc_point (code);
7523 /* Restore the unwind state to be the same as before the epilog */
7524 mono_emit_unwind_op_restore_state (cfg, code);
7526 cfg->code_len = code - cfg->native_code;
7528 g_assert (cfg->code_len < cfg->code_size);
7532 mono_arch_emit_exceptions (MonoCompile *cfg)
7534 MonoJumpInfo *patch_info;
7537 MonoClass *exc_classes [16];
7538 guint8 *exc_throw_start [16], *exc_throw_end [16];
7539 guint32 code_size = 0;
7541 /* Compute needed space */
7542 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7543 if (patch_info->type == MONO_PATCH_INFO_EXC)
7545 if (patch_info->type == MONO_PATCH_INFO_R8)
7546 code_size += 8 + 15; /* sizeof (double) + alignment */
7547 if (patch_info->type == MONO_PATCH_INFO_R4)
7548 code_size += 4 + 15; /* sizeof (float) + alignment */
7549 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7550 code_size += 8 + 7; /*sizeof (void*) + alignment */
7553 #ifdef __native_client_codegen__
7554 /* Give us extra room on Native Client. This could be */
7555 /* more carefully calculated, but bundle alignment makes */
7556 /* it much trickier, so *2 like other places is good. */
7560 while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7561 cfg->code_size *= 2;
7562 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7563 cfg->stat_code_reallocs++;
7566 code = cfg->native_code + cfg->code_len;
7568 /* add code to raise exceptions */
7570 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7571 switch (patch_info->type) {
7572 case MONO_PATCH_INFO_EXC: {
7573 MonoClass *exc_class;
7577 amd64_patch (patch_info->ip.i + cfg->native_code, code);
7579 exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7580 g_assert (exc_class);
7581 throw_ip = patch_info->ip.i;
7583 //x86_breakpoint (code);
7584 /* Find a throw sequence for the same exception class */
7585 for (i = 0; i < nthrows; ++i)
7586 if (exc_classes [i] == exc_class)
7589 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7590 x86_jump_code (code, exc_throw_start [i]);
7591 patch_info->type = MONO_PATCH_INFO_NONE;
7595 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7599 exc_classes [nthrows] = exc_class;
7600 exc_throw_start [nthrows] = code;
7602 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7604 patch_info->type = MONO_PATCH_INFO_NONE;
7606 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7608 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7613 exc_throw_end [nthrows] = code;
7623 g_assert(code < cfg->native_code + cfg->code_size);
7626 /* Handle relocations with RIP relative addressing */
7627 for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7628 gboolean remove = FALSE;
7629 guint8 *orig_code = code;
7631 switch (patch_info->type) {
7632 case MONO_PATCH_INFO_R8:
7633 case MONO_PATCH_INFO_R4: {
7634 guint8 *pos, *patch_pos;
7637 /* The SSE opcodes require a 16 byte alignment */
7638 #if defined(__default_codegen__)
7639 code = (guint8*)ALIGN_TO (code, 16);
7640 #elif defined(__native_client_codegen__)
7642 /* Pad this out with HLT instructions */
7643 /* or we can get garbage bytes emitted */
7644 /* which will fail validation */
7645 guint8 *aligned_code;
7646 /* extra align to make room for */
7647 /* mov/push below */
7648 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7649 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7650 /* The technique of hiding data in an */
7651 /* instruction has a problem here: we */
7652 /* need the data aligned to a 16-byte */
7653 /* boundary but the instruction cannot */
7654 /* cross the bundle boundary. so only */
7655 /* odd multiples of 16 can be used */
7656 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7659 while (code < aligned_code) {
7660 *(code++) = 0xf4; /* hlt */
7665 pos = cfg->native_code + patch_info->ip.i;
7666 if (IS_REX (pos [1])) {
7667 patch_pos = pos + 5;
7668 target_pos = code - pos - 9;
7671 patch_pos = pos + 4;
7672 target_pos = code - pos - 8;
7675 if (patch_info->type == MONO_PATCH_INFO_R8) {
7676 #ifdef __native_client_codegen__
7677 /* Hide 64-bit data in a */
7678 /* "mov imm64, r11" instruction. */
7679 /* write it before the start of */
7681 *(code-2) = 0x49; /* prefix */
7682 *(code-1) = 0xbb; /* mov X, %r11 */
7684 *(double*)code = *(double*)patch_info->data.target;
7685 code += sizeof (double);
7687 #ifdef __native_client_codegen__
7688 /* Hide 32-bit data in a */
7689 /* "push imm32" instruction. */
7690 *(code-1) = 0x68; /* push */
7692 *(float*)code = *(float*)patch_info->data.target;
7693 code += sizeof (float);
7696 *(guint32*)(patch_pos) = target_pos;
7701 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7704 if (cfg->compile_aot)
7707 /*loading is faster against aligned addresses.*/
7708 code = (guint8*)ALIGN_TO (code, 8);
7709 memset (orig_code, 0, code - orig_code);
7711 pos = cfg->native_code + patch_info->ip.i;
7713 /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7714 if (IS_REX (pos [1]))
7715 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7717 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7719 *(gpointer*)code = (gpointer)patch_info->data.target;
7720 code += sizeof (gpointer);
7730 if (patch_info == cfg->patch_info)
7731 cfg->patch_info = patch_info->next;
7735 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7737 tmp->next = patch_info->next;
7740 g_assert (code < cfg->native_code + cfg->code_size);
7743 cfg->code_len = code - cfg->native_code;
7745 g_assert (cfg->code_len < cfg->code_size);
7749 #endif /* DISABLE_JIT */
7752 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7754 guchar *code = (guchar *)p;
7755 MonoMethodSignature *sig;
7757 int i, n, stack_area = 0;
7759 /* Keep this in sync with mono_arch_get_argument_info */
7761 if (enable_arguments) {
7762 /* Allocate a new area on the stack and save arguments there */
7763 sig = mono_method_signature (cfg->method);
7765 n = sig->param_count + sig->hasthis;
7767 stack_area = ALIGN_TO (n * 8, 16);
7769 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7771 for (i = 0; i < n; ++i) {
7772 inst = cfg->args [i];
7774 if (inst->opcode == OP_REGVAR)
7775 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7777 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7778 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7783 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7784 amd64_set_reg_template (code, AMD64_ARG_REG1);
7785 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7786 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7788 if (enable_arguments)
7789 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7803 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7805 guchar *code = (guchar *)p;
7806 int save_mode = SAVE_NONE;
7807 MonoMethod *method = cfg->method;
7808 MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7811 switch (ret_type->type) {
7812 case MONO_TYPE_VOID:
7813 /* special case string .ctor icall */
7814 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7815 save_mode = SAVE_EAX;
7817 save_mode = SAVE_NONE;
7821 save_mode = SAVE_EAX;
7825 save_mode = SAVE_XMM;
7827 case MONO_TYPE_GENERICINST:
7828 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7829 save_mode = SAVE_EAX;
7833 case MONO_TYPE_VALUETYPE:
7834 save_mode = SAVE_STRUCT;
7837 save_mode = SAVE_EAX;
7841 /* Save the result and copy it into the proper argument register */
7842 switch (save_mode) {
7844 amd64_push_reg (code, AMD64_RAX);
7846 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7847 if (enable_arguments)
7848 amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7852 if (enable_arguments)
7853 amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7856 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7857 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7859 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7861 * The result is already in the proper argument register so no copying
7868 g_assert_not_reached ();
7871 /* Set %al since this is a varargs call */
7872 if (save_mode == SAVE_XMM)
7873 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7875 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7877 if (preserve_argument_registers) {
7878 for (i = 0; i < PARAM_REGS; ++i)
7879 amd64_push_reg (code, param_regs [i]);
7882 mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7883 amd64_set_reg_template (code, AMD64_ARG_REG1);
7884 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7886 if (preserve_argument_registers) {
7887 for (i = PARAM_REGS - 1; i >= 0; --i)
7888 amd64_pop_reg (code, param_regs [i]);
7891 /* Restore result */
7892 switch (save_mode) {
7894 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7895 amd64_pop_reg (code, AMD64_RAX);
7901 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7902 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7903 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7908 g_assert_not_reached ();
7915 mono_arch_flush_icache (guint8 *code, gint size)
7921 mono_arch_flush_register_windows (void)
7926 mono_arch_is_inst_imm (gint64 imm)
7928 return amd64_use_imm32 (imm);
7932 * Determine whenever the trap whose info is in SIGINFO is caused by
7936 mono_arch_is_int_overflow (void *sigctx, void *info)
7943 mono_sigctx_to_monoctx (sigctx, &ctx);
7945 rip = (guint8*)ctx.gregs [AMD64_RIP];
7947 if (IS_REX (rip [0])) {
7948 reg = amd64_rex_b (rip [0]);
7954 if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7956 reg += x86_modrm_rm (rip [1]);
7958 value = ctx.gregs [reg];
7968 mono_arch_get_patch_offset (guint8 *code)
7974 * mono_breakpoint_clean_code:
7976 * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
7977 * breakpoints in the original code, they are removed in the copy.
7979 * Returns TRUE if no sw breakpoint was present.
7982 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
7985 * If method_start is non-NULL we need to perform bound checks, since we access memory
7986 * at code - offset we could go before the start of the method and end up in a different
7987 * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
7990 if (!method_start || code - offset >= method_start) {
7991 memcpy (buf, code - offset, size);
7993 int diff = code - method_start;
7994 memset (buf, 0, size);
7995 memcpy (buf + offset - diff, method_start, diff + size - offset);
8000 #if defined(__native_client_codegen__)
8001 /* For membase calls, we want the base register. for Native Client, */
8002 /* all indirect calls have the following sequence with the given sizes: */
8003 /* mov %eXX,%eXX [2-3] */
8004 /* mov disp(%r15,%rXX,scale),%r11d [4-8] */
8005 /* and $0xffffffffffffffe0,%r11d [4] */
8006 /* add %r15,%r11 [3] */
8007 /* callq *%r11 [3] */
8010 /* Determine if code points to a NaCl call-through-register sequence, */
8011 /* (i.e., the last 3 instructions listed above) */
8013 is_nacl_call_reg_sequence(guint8* code)
8015 const char *sequence = "\x41\x83\xe3\xe0" /* and */
8016 "\x4d\x03\xdf" /* add */
8017 "\x41\xff\xd3"; /* call */
8018 return memcmp(code, sequence, 10) == 0;
8021 /* Determine if code points to the first opcode of the mov membase component */
8022 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
8023 /* (there could be a REX prefix before the opcode but it is ignored) */
8025 is_nacl_indirect_call_membase_sequence(guint8* code)
8027 /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
8028 return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
8029 /* and that src reg = dest reg */
8030 amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
8031 /* Check that next inst is mov, uses SIB byte (rm = 4), */
8033 code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
8034 /* and has dst of r11 and base of r15 */
8035 (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
8036 (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
8038 #endif /* __native_client_codegen__ */
8041 mono_arch_get_this_arg_reg (guint8 *code)
8043 return AMD64_ARG_REG1;
8047 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8049 return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8052 #define MAX_ARCH_DELEGATE_PARAMS 10
8055 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8057 guint8 *code, *start;
8058 GSList *unwind_ops = NULL;
8061 unwind_ops = mono_arch_get_cie_program ();
8064 start = code = (guint8 *)mono_global_codeman_reserve (64);
8066 /* Replace the this argument with the target */
8067 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8068 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8069 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8071 g_assert ((code - start) < 64);
8073 start = code = (guint8 *)mono_global_codeman_reserve (64);
8075 if (param_count == 0) {
8076 amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8078 /* We have to shift the arguments left */
8079 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8080 for (i = 0; i < param_count; ++i) {
8083 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8085 amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8087 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8091 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8093 g_assert ((code - start) < 64);
8096 nacl_global_codeman_validate (&start, 64, &code);
8097 mono_arch_flush_icache (start, code - start);
8100 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8102 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8103 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8107 if (mono_jit_map_is_enabled ()) {
8110 buff = (char*)"delegate_invoke_has_target";
8112 buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8113 mono_emit_jit_tramp (start, code - start, buff);
8117 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8122 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8125 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8127 guint8 *code, *start;
8132 if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8135 start = code = (guint8 *)mono_global_codeman_reserve (size);
8137 unwind_ops = mono_arch_get_cie_program ();
8139 /* Replace the this argument with the target */
8140 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8141 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8144 /* Load the IMT reg */
8145 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8148 /* Load the vtable */
8149 amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8150 amd64_jump_membase (code, AMD64_RAX, offset);
8151 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8154 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8156 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8157 *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8158 g_free (tramp_name);
8164 * mono_arch_get_delegate_invoke_impls:
8166 * Return a list of MonoTrampInfo structures for the delegate invoke impl
8170 mono_arch_get_delegate_invoke_impls (void)
8173 MonoTrampInfo *info;
8176 get_delegate_invoke_impl (&info, TRUE, 0);
8177 res = g_slist_prepend (res, info);
8179 for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8180 get_delegate_invoke_impl (&info, FALSE, i);
8181 res = g_slist_prepend (res, info);
8184 for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8185 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8186 res = g_slist_prepend (res, info);
8188 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8189 res = g_slist_prepend (res, info);
8196 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8198 guint8 *code, *start;
8201 if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8204 /* FIXME: Support more cases */
8205 if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8209 static guint8* cached = NULL;
8214 if (mono_aot_only) {
8215 start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8217 MonoTrampInfo *info;
8218 start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
8219 mono_tramp_info_register (info, NULL);
8222 mono_memory_barrier ();
8226 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8227 for (i = 0; i < sig->param_count; ++i)
8228 if (!mono_is_regsize_var (sig->params [i]))
8230 if (sig->param_count > 4)
8233 code = cache [sig->param_count];
8237 if (mono_aot_only) {
8238 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8239 start = (guint8 *)mono_aot_get_trampoline (name);
8242 MonoTrampInfo *info;
8243 start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8244 mono_tramp_info_register (info, NULL);
8247 mono_memory_barrier ();
8249 cache [sig->param_count] = start;
8256 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8258 MonoTrampInfo *info;
8261 code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8263 mono_tramp_info_register (info, NULL);
8268 mono_arch_finish_init (void)
8270 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8271 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8276 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8280 #if defined(__default_codegen__)
8281 #define CMP_SIZE (6 + 1)
8282 #define CMP_REG_REG_SIZE (4 + 1)
8283 #define BR_SMALL_SIZE 2
8284 #define BR_LARGE_SIZE 6
8285 #define MOV_REG_IMM_SIZE 10
8286 #define MOV_REG_IMM_32BIT_SIZE 6
8287 #define JUMP_REG_SIZE (2 + 1)
8288 #elif defined(__native_client_codegen__)
8289 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8290 #define CMP_SIZE ((6 + 1) * 2 - 1)
8291 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8292 #define BR_SMALL_SIZE (2 * 2 - 1)
8293 #define BR_LARGE_SIZE (6 * 2 - 1)
8294 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8295 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8296 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8297 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8298 /* Jump membase's size is large and unpredictable */
8299 /* in native client, just pad it out a whole bundle. */
8300 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8304 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8306 int i, distance = 0;
8307 for (i = start; i < target; ++i)
8308 distance += imt_entries [i]->chunk_size;
8313 * LOCKING: called with the domain lock held
8316 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8317 gpointer fail_tramp)
8321 guint8 *code, *start;
8322 gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8325 for (i = 0; i < count; ++i) {
8326 MonoIMTCheckItem *item = imt_entries [i];
8327 if (item->is_equals) {
8328 if (item->check_target_idx) {
8329 if (!item->compare_done) {
8330 if (amd64_use_imm32 ((gint64)item->key))
8331 item->chunk_size += CMP_SIZE;
8333 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8335 if (item->has_target_code) {
8336 item->chunk_size += MOV_REG_IMM_SIZE;
8338 if (vtable_is_32bit)
8339 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8341 item->chunk_size += MOV_REG_IMM_SIZE;
8342 #ifdef __native_client_codegen__
8343 item->chunk_size += JUMP_MEMBASE_SIZE;
8346 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8349 item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8350 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8352 if (vtable_is_32bit)
8353 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8355 item->chunk_size += MOV_REG_IMM_SIZE;
8356 item->chunk_size += JUMP_REG_SIZE;
8357 /* with assert below:
8358 * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8360 #ifdef __native_client_codegen__
8361 item->chunk_size += JUMP_MEMBASE_SIZE;
8366 if (amd64_use_imm32 ((gint64)item->key))
8367 item->chunk_size += CMP_SIZE;
8369 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8370 item->chunk_size += BR_LARGE_SIZE;
8371 imt_entries [item->check_target_idx]->compare_done = TRUE;
8373 size += item->chunk_size;
8375 #if defined(__native_client__) && defined(__native_client_codegen__)
8376 /* In Native Client, we don't re-use thunks, allocate from the */
8377 /* normal code manager paths. */
8378 code = mono_domain_code_reserve (domain, size);
8381 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8383 code = (guint8 *)mono_domain_code_reserve (domain, size);
8387 unwind_ops = mono_arch_get_cie_program ();
8389 for (i = 0; i < count; ++i) {
8390 MonoIMTCheckItem *item = imt_entries [i];
8391 item->code_target = code;
8392 if (item->is_equals) {
8393 gboolean fail_case = !item->check_target_idx && fail_tramp;
8395 if (item->check_target_idx || fail_case) {
8396 if (!item->compare_done || fail_case) {
8397 if (amd64_use_imm32 ((gint64)item->key))
8398 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8400 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8401 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8404 item->jmp_code = code;
8405 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8406 if (item->has_target_code) {
8407 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8408 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8410 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8411 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8415 amd64_patch (item->jmp_code, code);
8416 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8417 amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8418 item->jmp_code = NULL;
8421 /* enable the commented code to assert on wrong method */
8423 if (amd64_is_imm32 (item->key))
8424 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8426 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8427 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8429 item->jmp_code = code;
8430 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8431 /* See the comment below about R10 */
8432 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8433 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8434 amd64_patch (item->jmp_code, code);
8435 amd64_breakpoint (code);
8436 item->jmp_code = NULL;
8438 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8439 needs to be preserved. R10 needs
8440 to be preserved for calls which
8441 require a runtime generic context,
8442 but interface calls don't. */
8443 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8444 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8448 if (amd64_use_imm32 ((gint64)item->key))
8449 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8451 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8452 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8454 item->jmp_code = code;
8455 if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8456 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8458 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8460 g_assert (code - item->code_target <= item->chunk_size);
8462 /* patch the branches to get to the target items */
8463 for (i = 0; i < count; ++i) {
8464 MonoIMTCheckItem *item = imt_entries [i];
8465 if (item->jmp_code) {
8466 if (item->check_target_idx) {
8467 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8473 mono_stats.imt_thunks_size += code - start;
8474 g_assert (code - start <= size);
8476 nacl_domain_code_validate(domain, &start, size, &code);
8477 mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8479 mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8485 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8487 return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8491 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8493 return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8497 mono_arch_get_cie_program (void)
8501 mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8502 mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8510 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8512 MonoInst *ins = NULL;
8515 if (cmethod->klass == mono_defaults.math_class) {
8516 if (strcmp (cmethod->name, "Sin") == 0) {
8518 } else if (strcmp (cmethod->name, "Cos") == 0) {
8520 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8522 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8526 if (opcode && fsig->param_count == 1) {
8527 MONO_INST_NEW (cfg, ins, opcode);
8528 ins->type = STACK_R8;
8529 ins->dreg = mono_alloc_freg (cfg);
8530 ins->sreg1 = args [0]->dreg;
8531 MONO_ADD_INS (cfg->cbb, ins);
8535 if (cfg->opt & MONO_OPT_CMOV) {
8536 if (strcmp (cmethod->name, "Min") == 0) {
8537 if (fsig->params [0]->type == MONO_TYPE_I4)
8539 if (fsig->params [0]->type == MONO_TYPE_U4)
8540 opcode = OP_IMIN_UN;
8541 else if (fsig->params [0]->type == MONO_TYPE_I8)
8543 else if (fsig->params [0]->type == MONO_TYPE_U8)
8544 opcode = OP_LMIN_UN;
8545 } else if (strcmp (cmethod->name, "Max") == 0) {
8546 if (fsig->params [0]->type == MONO_TYPE_I4)
8548 if (fsig->params [0]->type == MONO_TYPE_U4)
8549 opcode = OP_IMAX_UN;
8550 else if (fsig->params [0]->type == MONO_TYPE_I8)
8552 else if (fsig->params [0]->type == MONO_TYPE_U8)
8553 opcode = OP_LMAX_UN;
8557 if (opcode && fsig->param_count == 2) {
8558 MONO_INST_NEW (cfg, ins, opcode);
8559 ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8560 ins->dreg = mono_alloc_ireg (cfg);
8561 ins->sreg1 = args [0]->dreg;
8562 ins->sreg2 = args [1]->dreg;
8563 MONO_ADD_INS (cfg->cbb, ins);
8567 /* OP_FREM is not IEEE compatible */
8568 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8569 MONO_INST_NEW (cfg, ins, OP_FREM);
8570 ins->inst_i0 = args [0];
8571 ins->inst_i1 = args [1];
8581 mono_arch_print_tree (MonoInst *tree, int arity)
8587 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8589 return ctx->gregs [reg];
8593 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8595 ctx->gregs [reg] = val;
8599 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8601 gpointer *sp, old_value;
8605 bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8606 sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8609 if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8618 * mono_arch_emit_load_aotconst:
8620 * Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8621 * TARGET from the mscorlib GOT in full-aot code.
8622 * On AMD64, the result is placed into R11.
8625 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8627 *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8628 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8634 * mono_arch_get_trampolines:
8636 * Return a list of MonoTrampInfo structures describing arch specific trampolines
8640 mono_arch_get_trampolines (gboolean aot)
8642 return mono_amd64_get_exception_trampolines (aot);
8645 /* Soft Debug support */
8646 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8649 * mono_arch_set_breakpoint:
8651 * Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8652 * The location should contain code emitted by OP_SEQ_POINT.
8655 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8660 guint32 native_offset = ip - (guint8*)ji->code_start;
8661 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8663 g_assert (info->bp_addrs [native_offset] == 0);
8664 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8666 /* ip points to a mov r11, 0 */
8667 g_assert (code [0] == 0x41);
8668 g_assert (code [1] == 0xbb);
8669 amd64_mov_reg_imm (code, AMD64_R11, 1);
8674 * mono_arch_clear_breakpoint:
8676 * Clear the breakpoint at IP.
8679 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8684 guint32 native_offset = ip - (guint8*)ji->code_start;
8685 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8687 info->bp_addrs [native_offset] = NULL;
8689 amd64_mov_reg_imm (code, AMD64_R11, 0);
8694 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8696 /* We use soft breakpoints on amd64 */
8701 * mono_arch_skip_breakpoint:
8703 * Modify CTX so the ip is placed after the breakpoint instruction, so when
8704 * we resume, the instruction is not executed again.
8707 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8709 g_assert_not_reached ();
8713 * mono_arch_start_single_stepping:
8715 * Start single stepping.
8718 mono_arch_start_single_stepping (void)
8720 ss_trampoline = mini_get_single_step_trampoline ();
8724 * mono_arch_stop_single_stepping:
8726 * Stop single stepping.
8729 mono_arch_stop_single_stepping (void)
8731 ss_trampoline = NULL;
8735 * mono_arch_is_single_step_event:
8737 * Return whenever the machine state in SIGCTX corresponds to a single
8741 mono_arch_is_single_step_event (void *info, void *sigctx)
8743 /* We use soft breakpoints on amd64 */
8748 * mono_arch_skip_single_step:
8750 * Modify CTX so the ip is placed after the single step trigger instruction,
8751 * we resume, the instruction is not executed again.
8754 mono_arch_skip_single_step (MonoContext *ctx)
8756 g_assert_not_reached ();
8760 * mono_arch_create_seq_point_info:
8762 * Return a pointer to a data structure which is used by the sequence
8763 * point implementation in AOTed code.
8766 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8771 // FIXME: Add a free function
8773 mono_domain_lock (domain);
8774 info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8776 mono_domain_unlock (domain);
8779 ji = mono_jit_info_table_find (domain, (char*)code);
8782 // FIXME: Optimize the size
8783 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8785 info->ss_tramp_addr = &ss_trampoline;
8787 mono_domain_lock (domain);
8788 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8790 mono_domain_unlock (domain);
8797 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8799 ext->lmf.previous_lmf = prev_lmf;
8800 /* Mark that this is a MonoLMFExt */
8801 ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8802 ext->lmf.rsp = (gssize)ext;
8808 mono_arch_opcode_supported (int opcode)
8811 case OP_ATOMIC_ADD_I4:
8812 case OP_ATOMIC_ADD_I8:
8813 case OP_ATOMIC_EXCHANGE_I4:
8814 case OP_ATOMIC_EXCHANGE_I8:
8815 case OP_ATOMIC_CAS_I4:
8816 case OP_ATOMIC_CAS_I8:
8817 case OP_ATOMIC_LOAD_I1:
8818 case OP_ATOMIC_LOAD_I2:
8819 case OP_ATOMIC_LOAD_I4:
8820 case OP_ATOMIC_LOAD_I8:
8821 case OP_ATOMIC_LOAD_U1:
8822 case OP_ATOMIC_LOAD_U2:
8823 case OP_ATOMIC_LOAD_U4:
8824 case OP_ATOMIC_LOAD_U8:
8825 case OP_ATOMIC_LOAD_R4:
8826 case OP_ATOMIC_LOAD_R8:
8827 case OP_ATOMIC_STORE_I1:
8828 case OP_ATOMIC_STORE_I2:
8829 case OP_ATOMIC_STORE_I4:
8830 case OP_ATOMIC_STORE_I8:
8831 case OP_ATOMIC_STORE_U1:
8832 case OP_ATOMIC_STORE_U2:
8833 case OP_ATOMIC_STORE_U4:
8834 case OP_ATOMIC_STORE_U8:
8835 case OP_ATOMIC_STORE_R4:
8836 case OP_ATOMIC_STORE_R8:
8843 #if defined(ENABLE_GSHAREDVT) && defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
8845 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8847 #endif /* !ENABLE_GSHAREDVT */