mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  */
  14 #include "mini.h"
  15 #include <string.h>
  16 #include <math.h>
  17 #ifdef HAVE_UNISTD_H
  18 #include <unistd.h>
  19 #endif
  20
  21 #include <mono/metadata/appdomain.h>
  22 #include <mono/metadata/debug-helpers.h>
  23 #include <mono/metadata/threads.h>
  24 #include <mono/metadata/profiler-private.h>
  25 #include <mono/metadata/mono-debug.h>
  26 #include <mono/utils/mono-math.h>
  27 #include <mono/utils/mono-mmap.h>
  28
  29 #include "trace.h"
  30 #include "ir-emit.h"
  31 #include "mini-amd64.h"
  32 #include "cpu-amd64.h"
  33 #include "debugger-agent.h"
  34
  35 static gint lmf_tls_offset = -1;
  36 static gint lmf_addr_tls_offset = -1;
  37 static gint appdomain_tls_offset = -1;
  38
  39 #ifdef MONO_XEN_OPT
  40 static gboolean optimize_for_xen = TRUE;
  41 #else
  42 #define optimize_for_xen 0
  43 #endif
  44
  45 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  46
  47 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  48
  49 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  50
  51 #ifdef HOST_WIN32
  52 /* Under windows, the calling convention is never stdcall */
  53 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  54 #else
  55 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  56 #endif
  57
  58 /* This mutex protects architecture specific caches */
  59 #define mono_mini_arch_lock() EnterCriticalSection (&mini_arch_mutex)
  60 #define mono_mini_arch_unlock() LeaveCriticalSection (&mini_arch_mutex)
  61 static CRITICAL_SECTION mini_arch_mutex;
  62
  63 MonoBreakpointInfo
  64 mono_breakpoint_info [MONO_BREAKPOINT_ARRAY_SIZE];
  65
  66 /*
  67  * The code generated for sequence points reads from this location, which is
  68  * made read-only when single stepping is enabled.
  69  */
  70 static gpointer ss_trigger_page;
  71
  72 /* Enabled breakpoints read from this trigger page */
  73 static gpointer bp_trigger_page;
  74
  75 /* The size of the breakpoint sequence */
  76 static int breakpoint_size;
  77
  78 /* The size of the breakpoint instruction causing the actual fault */
  79 static int breakpoint_fault_size;
  80
  81 /* The size of the single step instruction causing the actual fault */
  82 static int single_step_fault_size;
  83
  84 #ifdef HOST_WIN32
  85 /* On Win64 always reserve first 32 bytes for first four arguments */
  86 #define ARGS_OFFSET 48
  87 #else
  88 #define ARGS_OFFSET 16
  89 #endif
  90 #define GP_SCRATCH_REG AMD64_R11
  91
  92 /*
  93  * AMD64 register usage:
  94  * - callee saved registers are used for global register allocation
  95  * - %r11 is used for materializing 64 bit constants in opcodes
  96  * - the rest is used for local allocation
  97  */
  98
  99 /*
 100  * Floating point comparison results:
 101  *                  ZF PF CF
 102  * A > B            0  0  0
 103  * A < B            0  0  1
 104  * A = B            1  0  0
 105  * A > B            0  0  0
 106  * UNORDERED        1  1  1
 107  */
 108
 109 const char*
 110 mono_arch_regname (int reg)
 111 {
 112         switch (reg) {
 113         case AMD64_RAX: return "%rax";
 114         case AMD64_RBX: return "%rbx";
 115         case AMD64_RCX: return "%rcx";
 116         case AMD64_RDX: return "%rdx";
 117         case AMD64_RSP: return "%rsp";
 118         case AMD64_RBP: return "%rbp";
 119         case AMD64_RDI: return "%rdi";
 120         case AMD64_RSI: return "%rsi";
 121         case AMD64_R8: return "%r8";
 122         case AMD64_R9: return "%r9";
 123         case AMD64_R10: return "%r10";
 124         case AMD64_R11: return "%r11";
 125         case AMD64_R12: return "%r12";
 126         case AMD64_R13: return "%r13";
 127         case AMD64_R14: return "%r14";
 128         case AMD64_R15: return "%r15";
 129         }
 130         return "unknown";
 131 }
 132
 133 static const char * packed_xmmregs [] = {
 134         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 135         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 136 };
 137
 138 static const char * single_xmmregs [] = {
 139         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 140         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 141 };
 142
 143 const char*
 144 mono_arch_fregname (int reg)
 145 {
 146         if (reg < AMD64_XMM_NREG)
 147                 return single_xmmregs [reg];
 148         else
 149                 return "unknown";
 150 }
 151
 152 const char *
 153 mono_arch_xregname (int reg)
 154 {
 155         if (reg < AMD64_XMM_NREG)
 156                 return packed_xmmregs [reg];
 157         else
 158                 return "unknown";
 159 }
 160
 161 G_GNUC_UNUSED static void
 162 break_count (void)
 163 {
 164 }
 165
 166 G_GNUC_UNUSED static gboolean
 167 debug_count (void)
 168 {
 169         static int count = 0;
 170         count ++;
 171
 172         if (!getenv ("COUNT"))
 173                 return TRUE;
 174
 175         if (count == atoi (getenv ("COUNT"))) {
 176                 break_count ();
 177         }
 178
 179         if (count > atoi (getenv ("COUNT"))) {
 180                 return FALSE;
 181         }
 182
 183         return TRUE;
 184 }
 185
 186 static gboolean
 187 debug_omit_fp (void)
 188 {
 189 #if 0
 190         return debug_count ();
 191 #else
 192         return TRUE;
 193 #endif
 194 }
 195
 196 static inline gboolean
 197 amd64_is_near_call (guint8 *code)
 198 {
 199         /* Skip REX */
 200         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 201                 code += 1;
 202
 203         return code [0] == 0xe8;
 204 }
 205
 206 static inline void
 207 amd64_patch (unsigned char* code, gpointer target)
 208 {
 209         guint8 rex = 0;
 210
 211         /* Skip REX */
 212         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 213                 rex = code [0];
 214                 code += 1;
 215         }
 216
 217         if ((code [0] & 0xf8) == 0xb8) {
 218                 /* amd64_set_reg_template */
 219                 *(guint64*)(code + 1) = (guint64)target;
 220         }
 221         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 222                 /* mov 0(%rip), %dreg */
 223                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 224         }
 225         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 226                 /* call *<OFFSET>(%rip) */
 227                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 228         }
 229         else if ((code [0] == 0xe8)) {
 230                 /* call <DISP> */
 231                 gint64 disp = (guint8*)target - (guint8*)code;
 232                 g_assert (amd64_is_imm32 (disp));
 233                 x86_patch (code, (unsigned char*)target);
 234         }
 235         else
 236                 x86_patch (code, (unsigned char*)target);
 237 }
 238
 239 void
 240 mono_amd64_patch (unsigned char* code, gpointer target)
 241 {
 242         amd64_patch (code, target);
 243 }
 244
 245 typedef enum {
 246         ArgInIReg,
 247         ArgInFloatSSEReg,
 248         ArgInDoubleSSEReg,
 249         ArgOnStack,
 250         ArgValuetypeInReg,
 251         ArgValuetypeAddrInIReg,
 252         ArgNone /* only in pair_storage */
 253 } ArgStorage;
 254
 255 typedef struct {
 256         gint16 offset;
 257         gint8  reg;
 258         ArgStorage storage;
 259
 260         /* Only if storage == ArgValuetypeInReg */
 261         ArgStorage pair_storage [2];
 262         gint8 pair_regs [2];
 263 } ArgInfo;
 264
 265 typedef struct {
 266         int nargs;
 267         guint32 stack_usage;
 268         guint32 reg_usage;
 269         guint32 freg_usage;
 270         gboolean need_stack_align;
 271         gboolean vtype_retaddr;
 272         /* The index of the vret arg in the argument list */
 273         int vret_arg_index;
 274         ArgInfo ret;
 275         ArgInfo sig_cookie;
 276         ArgInfo args [1];
 277 } CallInfo;
 278
 279 #define DEBUG(a) if (cfg->verbose_level > 1) a
 280
 281 #ifdef HOST_WIN32
 282 #define PARAM_REGS 4
 283
 284 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 285
 286 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 287 #else
 288 #define PARAM_REGS 6
 289
 290 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 291
 292  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 293 #endif
 294
 295 static void inline
 296 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 297 {
 298     ainfo->offset = *stack_size;
 299
 300     if (*gr >= PARAM_REGS) {
 301                 ainfo->storage = ArgOnStack;
 302                 (*stack_size) += sizeof (gpointer);
 303     }
 304     else {
 305                 ainfo->storage = ArgInIReg;
 306                 ainfo->reg = param_regs [*gr];
 307                 (*gr) ++;
 308     }
 309 }
 310
 311 #ifdef HOST_WIN32
 312 #define FLOAT_PARAM_REGS 4
 313 #else
 314 #define FLOAT_PARAM_REGS 8
 315 #endif
 316
 317 static void inline
 318 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 319 {
 320     ainfo->offset = *stack_size;
 321
 322     if (*gr >= FLOAT_PARAM_REGS) {
 323                 ainfo->storage = ArgOnStack;
 324                 (*stack_size) += sizeof (gpointer);
 325     }
 326     else {
 327                 /* A double register */
 328                 if (is_double)
 329                         ainfo->storage = ArgInDoubleSSEReg;
 330                 else
 331                         ainfo->storage = ArgInFloatSSEReg;
 332                 ainfo->reg = *gr;
 333                 (*gr) += 1;
 334     }
 335 }
 336
 337 typedef enum ArgumentClass {
 338         ARG_CLASS_NO_CLASS,
 339         ARG_CLASS_MEMORY,
 340         ARG_CLASS_INTEGER,
 341         ARG_CLASS_SSE
 342 } ArgumentClass;
 343
 344 static ArgumentClass
 345 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 346 {
 347         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 348         MonoType *ptype;
 349
 350         ptype = mini_type_get_underlying_type (NULL, type);
 351         switch (ptype->type) {
 352         case MONO_TYPE_BOOLEAN:
 353         case MONO_TYPE_CHAR:
 354         case MONO_TYPE_I1:
 355         case MONO_TYPE_U1:
 356         case MONO_TYPE_I2:
 357         case MONO_TYPE_U2:
 358         case MONO_TYPE_I4:
 359         case MONO_TYPE_U4:
 360         case MONO_TYPE_I:
 361         case MONO_TYPE_U:
 362         case MONO_TYPE_STRING:
 363         case MONO_TYPE_OBJECT:
 364         case MONO_TYPE_CLASS:
 365         case MONO_TYPE_SZARRAY:
 366         case MONO_TYPE_PTR:
 367         case MONO_TYPE_FNPTR:
 368         case MONO_TYPE_ARRAY:
 369         case MONO_TYPE_I8:
 370         case MONO_TYPE_U8:
 371                 class2 = ARG_CLASS_INTEGER;
 372                 break;
 373         case MONO_TYPE_R4:
 374         case MONO_TYPE_R8:
 375 #ifdef HOST_WIN32
 376                 class2 = ARG_CLASS_INTEGER;
 377 #else
 378                 class2 = ARG_CLASS_SSE;
 379 #endif
 380                 break;
 381
 382         case MONO_TYPE_TYPEDBYREF:
 383                 g_assert_not_reached ();
 384
 385         case MONO_TYPE_GENERICINST:
 386                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 387                         class2 = ARG_CLASS_INTEGER;
 388                         break;
 389                 }
 390                 /* fall through */
 391         case MONO_TYPE_VALUETYPE: {
 392                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 393                 int i;
 394
 395                 for (i = 0; i < info->num_fields; ++i) {
 396                         class2 = class1;
 397                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 398                 }
 399                 break;
 400         }
 401         default:
 402                 g_assert_not_reached ();
 403         }
 404
 405         /* Merge */
 406         if (class1 == class2)
 407                 ;
 408         else if (class1 == ARG_CLASS_NO_CLASS)
 409                 class1 = class2;
 410         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 411                 class1 = ARG_CLASS_MEMORY;
 412         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 413                 class1 = ARG_CLASS_INTEGER;
 414         else
 415                 class1 = ARG_CLASS_SSE;
 416
 417         return class1;
 418 }
 419
 420 static void
 421 add_valuetype (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 422                            gboolean is_return,
 423                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 424 {
 425         guint32 size, quad, nquads, i;
 426         ArgumentClass args [2];
 427         MonoMarshalType *info = NULL;
 428         MonoClass *klass;
 429         MonoGenericSharingContext tmp_gsctx;
 430         gboolean pass_on_stack = FALSE;
 431
 432         /*
 433          * The gsctx currently contains no data, it is only used for checking whenever
 434          * open types are allowed, some callers like mono_arch_get_argument_info ()
 435          * don't pass it to us, so work around that.
 436          */
 437         if (!gsctx)
 438                 gsctx = &tmp_gsctx;
 439
 440         klass = mono_class_from_mono_type (type);
 441         size = mini_type_stack_size_full (gsctx, &klass->byval_arg, NULL, sig->pinvoke);
 442 #ifndef HOST_WIN32
 443         if (!sig->pinvoke && !disable_vtypes_in_regs && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 444                 /* We pass and return vtypes of size 8 in a register */
 445         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 446                 pass_on_stack = TRUE;
 447         }
 448 #else
 449         if (!sig->pinvoke) {
 450                 pass_on_stack = TRUE;
 451         }
 452 #endif
 453
 454         if (pass_on_stack) {
 455                 /* Allways pass in memory */
 456                 ainfo->offset = *stack_size;
 457                 *stack_size += ALIGN_TO (size, 8);
 458                 ainfo->storage = ArgOnStack;
 459
 460                 return;
 461         }
 462
 463         /* FIXME: Handle structs smaller than 8 bytes */
 464         //if ((size % 8) != 0)
 465         //      NOT_IMPLEMENTED;
 466
 467         if (size > 8)
 468                 nquads = 2;
 469         else
 470                 nquads = 1;
 471
 472         if (!sig->pinvoke) {
 473                 /* Always pass in 1 or 2 integer registers */
 474                 args [0] = ARG_CLASS_INTEGER;
 475                 args [1] = ARG_CLASS_INTEGER;
 476                 /* Only the simplest cases are supported */
 477                 if (is_return && nquads != 1) {
 478                         args [0] = ARG_CLASS_MEMORY;
 479                         args [1] = ARG_CLASS_MEMORY;
 480                 }
 481         } else {
 482                 /*
 483                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
 484                  * The X87 and SSEUP stuff is left out since there are no such types in
 485                  * the CLR.
 486                  */
 487                 info = mono_marshal_load_type_info (klass);
 488                 g_assert (info);
 489
 490 #ifndef HOST_WIN32
 491                 if (info->native_size > 16) {
 492                         ainfo->offset = *stack_size;
 493                         *stack_size += ALIGN_TO (info->native_size, 8);
 494                         ainfo->storage = ArgOnStack;
 495
 496                         return;
 497                 }
 498 #else
 499                 switch (info->native_size) {
 500                 case 1: case 2: case 4: case 8:
 501                         break;
 502                 default:
 503                         if (is_return) {
 504                                 ainfo->storage = ArgOnStack;
 505                                 ainfo->offset = *stack_size;
 506                                 *stack_size += ALIGN_TO (info->native_size, 8);
 507                         }
 508                         else {
 509                                 ainfo->storage = ArgValuetypeAddrInIReg;
 510
 511                                 if (*gr < PARAM_REGS) {
 512                                         ainfo->pair_storage [0] = ArgInIReg;
 513                                         ainfo->pair_regs [0] = param_regs [*gr];
 514                                         (*gr) ++;
 515                                 }
 516                                 else {
 517                                         ainfo->pair_storage [0] = ArgOnStack;
 518                                         ainfo->offset = *stack_size;
 519                                         *stack_size += 8;
 520                                 }
 521                         }
 522
 523                         return;
 524                 }
 525 #endif
 526
 527                 args [0] = ARG_CLASS_NO_CLASS;
 528                 args [1] = ARG_CLASS_NO_CLASS;
 529                 for (quad = 0; quad < nquads; ++quad) {
 530                         int size;
 531                         guint32 align;
 532                         ArgumentClass class1;
 533
 534                         if (info->num_fields == 0)
 535                                 class1 = ARG_CLASS_MEMORY;
 536                         else
 537                                 class1 = ARG_CLASS_NO_CLASS;
 538                         for (i = 0; i < info->num_fields; ++i) {
 539                                 size = mono_marshal_type_size (info->fields [i].field->type,
 540                                                                                            info->fields [i].mspec,
 541                                                                                            &align, TRUE, klass->unicode);
 542                                 if ((info->fields [i].offset < 8) && (info->fields [i].offset + size) > 8) {
 543                                         /* Unaligned field */
 544                                         NOT_IMPLEMENTED;
 545                                 }
 546
 547                                 /* Skip fields in other quad */
 548                                 if ((quad == 0) && (info->fields [i].offset >= 8))
 549                                         continue;
 550                                 if ((quad == 1) && (info->fields [i].offset < 8))
 551                                         continue;
 552
 553                                 class1 = merge_argument_class_from_type (info->fields [i].field->type, class1);
 554                         }
 555                         g_assert (class1 != ARG_CLASS_NO_CLASS);
 556                         args [quad] = class1;
 557                 }
 558         }
 559
 560         /* Post merger cleanup */
 561         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
 562                 args [0] = args [1] = ARG_CLASS_MEMORY;
 563
 564         /* Allocate registers */
 565         {
 566                 int orig_gr = *gr;
 567                 int orig_fr = *fr;
 568
 569                 ainfo->storage = ArgValuetypeInReg;
 570                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 571                 for (quad = 0; quad < nquads; ++quad) {
 572                         switch (args [quad]) {
 573                         case ARG_CLASS_INTEGER:
 574                                 if (*gr >= PARAM_REGS)
 575                                         args [quad] = ARG_CLASS_MEMORY;
 576                                 else {
 577                                         ainfo->pair_storage [quad] = ArgInIReg;
 578                                         if (is_return)
 579                                                 ainfo->pair_regs [quad] = return_regs [*gr];
 580                                         else
 581                                                 ainfo->pair_regs [quad] = param_regs [*gr];
 582                                         (*gr) ++;
 583                                 }
 584                                 break;
 585                         case ARG_CLASS_SSE:
 586                                 if (*fr >= FLOAT_PARAM_REGS)
 587                                         args [quad] = ARG_CLASS_MEMORY;
 588                                 else {
 589                                         ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
 590                                         ainfo->pair_regs [quad] = *fr;
 591                                         (*fr) ++;
 592                                 }
 593                                 break;
 594                         case ARG_CLASS_MEMORY:
 595                                 break;
 596                         default:
 597                                 g_assert_not_reached ();
 598                         }
 599                 }
 600
 601                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
 602                         /* Revert possible register assignments */
 603                         *gr = orig_gr;
 604                         *fr = orig_fr;
 605
 606                         ainfo->offset = *stack_size;
 607                         if (sig->pinvoke)
 608                                 *stack_size += ALIGN_TO (info->native_size, 8);
 609                         else
 610                                 *stack_size += nquads * sizeof (gpointer);
 611                         ainfo->storage = ArgOnStack;
 612                 }
 613         }
 614 }
 615
 616 /*
 617  * get_call_info:
 618  *
 619  *  Obtain information about a call according to the calling convention.
 620  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
 621  * Draft Version 0.23" document for more information.
 622  */
 623 static CallInfo*
 624 get_call_info (MonoGenericSharingContext *gsctx, MonoMemPool *mp, MonoMethodSignature *sig, gboolean is_pinvoke)
 625 {
 626         guint32 i, gr, fr, pstart;
 627         MonoType *ret_type;
 628         int n = sig->hasthis + sig->param_count;
 629         guint32 stack_size = 0;
 630         CallInfo *cinfo;
 631
 632         if (mp)
 633                 cinfo = mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 634         else
 635                 cinfo = g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
 636
 637         cinfo->nargs = n;
 638
 639         gr = 0;
 640         fr = 0;
 641
 642         /* return value */
 643         {
 644                 ret_type = mini_type_get_underlying_type (gsctx, sig->ret);
 645                 switch (ret_type->type) {
 646                 case MONO_TYPE_BOOLEAN:
 647                 case MONO_TYPE_I1:
 648                 case MONO_TYPE_U1:
 649                 case MONO_TYPE_I2:
 650                 case MONO_TYPE_U2:
 651                 case MONO_TYPE_CHAR:
 652                 case MONO_TYPE_I4:
 653                 case MONO_TYPE_U4:
 654                 case MONO_TYPE_I:
 655                 case MONO_TYPE_U:
 656                 case MONO_TYPE_PTR:
 657                 case MONO_TYPE_FNPTR:
 658                 case MONO_TYPE_CLASS:
 659                 case MONO_TYPE_OBJECT:
 660                 case MONO_TYPE_SZARRAY:
 661                 case MONO_TYPE_ARRAY:
 662                 case MONO_TYPE_STRING:
 663                         cinfo->ret.storage = ArgInIReg;
 664                         cinfo->ret.reg = AMD64_RAX;
 665                         break;
 666                 case MONO_TYPE_U8:
 667                 case MONO_TYPE_I8:
 668                         cinfo->ret.storage = ArgInIReg;
 669                         cinfo->ret.reg = AMD64_RAX;
 670                         break;
 671                 case MONO_TYPE_R4:
 672                         cinfo->ret.storage = ArgInFloatSSEReg;
 673                         cinfo->ret.reg = AMD64_XMM0;
 674                         break;
 675                 case MONO_TYPE_R8:
 676                         cinfo->ret.storage = ArgInDoubleSSEReg;
 677                         cinfo->ret.reg = AMD64_XMM0;
 678                         break;
 679                 case MONO_TYPE_GENERICINST:
 680                         if (!mono_type_generic_inst_is_valuetype (ret_type)) {
 681                                 cinfo->ret.storage = ArgInIReg;
 682                                 cinfo->ret.reg = AMD64_RAX;
 683                                 break;
 684                         }
 685                         /* fall through */
 686                 case MONO_TYPE_VALUETYPE: {
 687                         guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
 688
 689                         add_valuetype (gsctx, sig, &cinfo->ret, sig->ret, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
 690                         if (cinfo->ret.storage == ArgOnStack) {
 691                                 cinfo->vtype_retaddr = TRUE;
 692                                 /* The caller passes the address where the value is stored */
 693                         }
 694                         break;
 695                 }
 696                 case MONO_TYPE_TYPEDBYREF:
 697                         /* Same as a valuetype with size 24 */
 698                         cinfo->vtype_retaddr = TRUE;
 699                         break;
 700                 case MONO_TYPE_VOID:
 701                         break;
 702                 default:
 703                         g_error ("Can't handle as return value 0x%x", sig->ret->type);
 704                 }
 705         }
 706
 707         pstart = 0;
 708         /*
 709          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
 710          * the first argument, allowing 'this' to be always passed in the first arg reg.
 711          * Also do this if the first argument is a reference type, since virtual calls
 712          * are sometimes made using calli without sig->hasthis set, like in the delegate
 713          * invoke wrappers.
 714          */
 715         if (cinfo->vtype_retaddr && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_type_get_underlying_type (gsctx, sig->params [0]))))) {
 716                 if (sig->hasthis) {
 717                         add_general (&gr, &stack_size, cinfo->args + 0);
 718                 } else {
 719                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
 720                         pstart = 1;
 721                 }
 722                 add_general (&gr, &stack_size, &cinfo->ret);
 723                 cinfo->vret_arg_index = 1;
 724         } else {
 725                 /* this */
 726                 if (sig->hasthis)
 727                         add_general (&gr, &stack_size, cinfo->args + 0);
 728
 729                 if (cinfo->vtype_retaddr)
 730                         add_general (&gr, &stack_size, &cinfo->ret);
 731         }
 732
 733         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
 734                 gr = PARAM_REGS;
 735                 fr = FLOAT_PARAM_REGS;
 736
 737                 /* Emit the signature cookie just before the implicit arguments */
 738                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 739         }
 740
 741         for (i = pstart; i < sig->param_count; ++i) {
 742                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
 743                 MonoType *ptype;
 744
 745 #ifdef HOST_WIN32
 746                 /* The float param registers and other param registers must be the same index on Windows x64.*/
 747                 if (gr > fr)
 748                         fr = gr;
 749                 else if (fr > gr)
 750                         gr = fr;
 751 #endif
 752
 753                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
 754                         /* We allways pass the sig cookie on the stack for simplicity */
 755                         /*
 756                          * Prevent implicit arguments + the sig cookie from being passed
 757                          * in registers.
 758                          */
 759                         gr = PARAM_REGS;
 760                         fr = FLOAT_PARAM_REGS;
 761
 762                         /* Emit the signature cookie just before the implicit arguments */
 763                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
 764                 }
 765
 766                 ptype = mini_type_get_underlying_type (gsctx, sig->params [i]);
 767                 switch (ptype->type) {
 768                 case MONO_TYPE_BOOLEAN:
 769                 case MONO_TYPE_I1:
 770                 case MONO_TYPE_U1:
 771                         add_general (&gr, &stack_size, ainfo);
 772                         break;
 773                 case MONO_TYPE_I2:
 774                 case MONO_TYPE_U2:
 775                 case MONO_TYPE_CHAR:
 776                         add_general (&gr, &stack_size, ainfo);
 777                         break;
 778                 case MONO_TYPE_I4:
 779                 case MONO_TYPE_U4:
 780                         add_general (&gr, &stack_size, ainfo);
 781                         break;
 782                 case MONO_TYPE_I:
 783                 case MONO_TYPE_U:
 784                 case MONO_TYPE_PTR:
 785                 case MONO_TYPE_FNPTR:
 786                 case MONO_TYPE_CLASS:
 787                 case MONO_TYPE_OBJECT:
 788                 case MONO_TYPE_STRING:
 789                 case MONO_TYPE_SZARRAY:
 790                 case MONO_TYPE_ARRAY:
 791                         add_general (&gr, &stack_size, ainfo);
 792                         break;
 793                 case MONO_TYPE_GENERICINST:
 794                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
 795                                 add_general (&gr, &stack_size, ainfo);
 796                                 break;
 797                         }
 798                         /* fall through */
 799                 case MONO_TYPE_VALUETYPE:
 800                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 801                         break;
 802                 case MONO_TYPE_TYPEDBYREF:
 803 #ifdef HOST_WIN32
 804                         add_valuetype (gsctx, sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
 805 #else
 806                         stack_size += sizeof (MonoTypedRef);
 807                         ainfo->storage = ArgOnStack;
 808 #endif
 809                         break;
 810                 case MONO_TYPE_U8:
 811                 case MONO_TYPE_I8:
 812                         add_general (&gr, &stack_size, ainfo);
 813                         break;
 814                 case MONO_TYPE_R4:
 815                         add_float (&fr, &stack_size, ainfo, FALSE);
 816                         break;
 817                 case MONO_TYPE_R8:
 818                         add_float (&fr, &stack_size, ainfo, TRUE);
 819                         break;
 820                 default:
 821                         g_assert_not_reached ();
 822                 }
 823         }
 824
 825         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
 826                 gr = PARAM_REGS;
 827                 fr = FLOAT_PARAM_REGS;
 828
 829                 /* Emit the signature cookie just before the implicit arguments */
 830                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
 831         }
 832
 833 #ifdef HOST_WIN32
 834         // There always is 32 bytes reserved on the stack when calling on Winx64
 835         stack_size += 0x20;
 836 #endif
 837
 838         if (stack_size & 0x8) {
 839                 /* The AMD64 ABI requires each stack frame to be 16 byte aligned */
 840                 cinfo->need_stack_align = TRUE;
 841                 stack_size += 8;
 842         }
 843
 844         cinfo->stack_usage = stack_size;
 845         cinfo->reg_usage = gr;
 846         cinfo->freg_usage = fr;
 847         return cinfo;
 848 }
 849
 850 /*
 851  * mono_arch_get_argument_info:
 852  * @csig:  a method signature
 853  * @param_count: the number of parameters to consider
 854  * @arg_info: an array to store the result infos
 855  *
 856  * Gathers information on parameters such as size, alignment and
 857  * padding. arg_info should be large enought to hold param_count + 1 entries.
 858  *
 859  * Returns the size of the argument area on the stack.
 860  */
 861 int
 862 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
 863 {
 864         int k;
 865         CallInfo *cinfo = get_call_info (NULL, NULL, csig, FALSE);
 866         guint32 args_size = cinfo->stack_usage;
 867
 868         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
 869         if (csig->hasthis) {
 870                 arg_info [0].offset = 0;
 871         }
 872
 873         for (k = 0; k < param_count; k++) {
 874                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
 875                 /* FIXME: */
 876                 arg_info [k + 1].size = 0;
 877         }
 878
 879         g_free (cinfo);
 880
 881         return args_size;
 882 }
 883
 884 static int
 885 cpuid (int id, int* p_eax, int* p_ebx, int* p_ecx, int* p_edx)
 886 {
 887 #ifndef _MSC_VER
 888         __asm__ __volatile__ ("cpuid"
 889                 : "=a" (*p_eax), "=b" (*p_ebx), "=c" (*p_ecx), "=d" (*p_edx)
 890                 : "a" (id));
 891 #else
 892         int info[4];
 893         __cpuid(info, id);
 894         *p_eax = info[0];
 895         *p_ebx = info[1];
 896         *p_ecx = info[2];
 897         *p_edx = info[3];
 898 #endif
 899         return 1;
 900 }
 901
 902 /*
 903  * Initialize the cpu to execute managed code.
 904  */
 905 void
 906 mono_arch_cpu_init (void)
 907 {
 908 #ifndef _MSC_VER
 909         guint16 fpcw;
 910
 911         /* spec compliance requires running with double precision */
 912         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 913         fpcw &= ~X86_FPCW_PRECC_MASK;
 914         fpcw |= X86_FPCW_PREC_DOUBLE;
 915         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
 916         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
 917 #else
 918         /* TODO: This is crashing on Win64 right now.
 919         * _control87 (_PC_53, MCW_PC);
 920         */
 921 #endif
 922 }
 923
 924 /*
 925  * Initialize architecture specific code.
 926  */
 927 void
 928 mono_arch_init (void)
 929 {
 930         int flags;
 931
 932         InitializeCriticalSection (&mini_arch_mutex);
 933
 934 #ifdef MONO_ARCH_NOMAP32BIT
 935         flags = MONO_MMAP_READ;
 936         /* amd64_mov_reg_imm () + amd64_mov_reg_membase () */
 937         breakpoint_size = 13;
 938         breakpoint_fault_size = 3;
 939         /* amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4); */
 940         single_step_fault_size = 5;
 941 #else
 942         flags = MONO_MMAP_READ|MONO_MMAP_32BIT;
 943         /* amd64_mov_reg_mem () */
 944         breakpoint_size = 8;
 945         breakpoint_fault_size = 8;
 946         single_step_fault_size = 8;
 947 #endif
 948
 949         ss_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 950         bp_trigger_page = mono_valloc (NULL, mono_pagesize (), flags);
 951         mono_mprotect (bp_trigger_page, mono_pagesize (), 0);
 952
 953         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
 954         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
 955         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
 956 }
 957
 958 /*
 959  * Cleanup architecture specific code.
 960  */
 961 void
 962 mono_arch_cleanup (void)
 963 {
 964         DeleteCriticalSection (&mini_arch_mutex);
 965 }
 966
 967 /*
 968  * This function returns the optimizations supported on this cpu.
 969  */
 970 guint32
 971 mono_arch_cpu_optimizazions (guint32 *exclude_mask)
 972 {
 973         int eax, ebx, ecx, edx;
 974         guint32 opts = 0;
 975
 976         /* FIXME: AMD64 */
 977
 978         *exclude_mask = 0;
 979         /* Feature Flags function, flags returned in EDX. */
 980         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
 981                 if (edx & (1 << 15)) {
 982                         opts |= MONO_OPT_CMOV;
 983                         if (edx & 1)
 984                                 opts |= MONO_OPT_FCMOV;
 985                         else
 986                                 *exclude_mask |= MONO_OPT_FCMOV;
 987                 } else
 988                         *exclude_mask |= MONO_OPT_CMOV;
 989         }
 990
 991         return opts;
 992 }
 993
 994 /*
 995  * This function test for all SSE functions supported.
 996  *
 997  * Returns a bitmask corresponding to all supported versions.
 998  *
 999  */
1000 guint32
1001 mono_arch_cpu_enumerate_simd_versions (void)
1002 {
1003         int eax, ebx, ecx, edx;
1004         guint32 sse_opts = 0;
1005
1006         if (cpuid (1, &eax, &ebx, &ecx, &edx)) {
1007                 if (edx & (1 << 25))
1008                         sse_opts |= SIMD_VERSION_SSE1;
1009                 if (edx & (1 << 26))
1010                         sse_opts |= SIMD_VERSION_SSE2;
1011                 if (ecx & (1 << 0))
1012                         sse_opts |= SIMD_VERSION_SSE3;
1013                 if (ecx & (1 << 9))
1014                         sse_opts |= SIMD_VERSION_SSSE3;
1015                 if (ecx & (1 << 19))
1016                         sse_opts |= SIMD_VERSION_SSE41;
1017                 if (ecx & (1 << 20))
1018                         sse_opts |= SIMD_VERSION_SSE42;
1019         }
1020
1021         /* Yes, all this needs to be done to check for sse4a.
1022            See: "Amd: CPUID Specification"
1023          */
1024         if (cpuid (0x80000000, &eax, &ebx, &ecx, &edx)) {
1025                 /* eax greater or equal than 0x80000001, ebx = 'htuA', ecx = DMAc', edx = 'itne'*/
1026                 if ((((unsigned int) eax) >= 0x80000001) && (ebx == 0x68747541) && (ecx == 0x444D4163) && (edx == 0x69746E65)) {
1027                         cpuid (0x80000001, &eax, &ebx, &ecx, &edx);
1028                         if (ecx & (1 << 6))
1029                                 sse_opts |= SIMD_VERSION_SSE4a;
1030                 }
1031         }
1032
1033         return sse_opts;
1034 }
1035
1036 #ifndef DISABLE_JIT
1037
1038 GList *
1039 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1040 {
1041         GList *vars = NULL;
1042         int i;
1043
1044         for (i = 0; i < cfg->num_varinfo; i++) {
1045                 MonoInst *ins = cfg->varinfo [i];
1046                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1047
1048                 /* unused vars */
1049                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1050                         continue;
1051
1052                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1053                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1054                         continue;
1055
1056                 if (mono_is_regsize_var (ins->inst_vtype)) {
1057                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1058                         g_assert (i == vmv->idx);
1059                         vars = g_list_prepend (vars, vmv);
1060                 }
1061         }
1062
1063         vars = mono_varlist_sort (cfg, vars, 0);
1064
1065         return vars;
1066 }
1067
1068 /**
1069  * mono_arch_compute_omit_fp:
1070  *
1071  *   Determine whenever the frame pointer can be eliminated.
1072  */
1073 static void
1074 mono_arch_compute_omit_fp (MonoCompile *cfg)
1075 {
1076         MonoMethodSignature *sig;
1077         MonoMethodHeader *header;
1078         int i, locals_size;
1079         CallInfo *cinfo;
1080
1081         if (cfg->arch.omit_fp_computed)
1082                 return;
1083
1084         header = cfg->header;
1085
1086         sig = mono_method_signature (cfg->method);
1087
1088         if (!cfg->arch.cinfo)
1089                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1090         cinfo = cfg->arch.cinfo;
1091
1092         /*
1093          * FIXME: Remove some of the restrictions.
1094          */
1095         cfg->arch.omit_fp = TRUE;
1096         cfg->arch.omit_fp_computed = TRUE;
1097
1098         if (cfg->disable_omit_fp)
1099                 cfg->arch.omit_fp = FALSE;
1100
1101         if (!debug_omit_fp ())
1102                 cfg->arch.omit_fp = FALSE;
1103         /*
1104         if (cfg->method->save_lmf)
1105                 cfg->arch.omit_fp = FALSE;
1106         */
1107         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1108                 cfg->arch.omit_fp = FALSE;
1109         if (header->num_clauses)
1110                 cfg->arch.omit_fp = FALSE;
1111         if (cfg->param_area)
1112                 cfg->arch.omit_fp = FALSE;
1113         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1114                 cfg->arch.omit_fp = FALSE;
1115         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1116                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1117                 cfg->arch.omit_fp = FALSE;
1118         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1119                 ArgInfo *ainfo = &cinfo->args [i];
1120
1121                 if (ainfo->storage == ArgOnStack) {
1122                         /*
1123                          * The stack offset can only be determined when the frame
1124                          * size is known.
1125                          */
1126                         cfg->arch.omit_fp = FALSE;
1127                 }
1128         }
1129
1130         locals_size = 0;
1131         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1132                 MonoInst *ins = cfg->varinfo [i];
1133                 int ialign;
1134
1135                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1136         }
1137 }
1138
1139 GList *
1140 mono_arch_get_global_int_regs (MonoCompile *cfg)
1141 {
1142         GList *regs = NULL;
1143
1144         mono_arch_compute_omit_fp (cfg);
1145
1146         if (cfg->globalra) {
1147                 if (cfg->arch.omit_fp)
1148                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1149
1150                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1151                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1152                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1153                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1154                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1155
1156                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1157                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1158                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1159                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1160                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1161                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1162                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1163                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1164         } else {
1165                 if (cfg->arch.omit_fp)
1166                         regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1167
1168                 /* We use the callee saved registers for global allocation */
1169                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1170                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1171                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1172                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1173                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1174 #ifdef HOST_WIN32
1175                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1176                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1177 #endif
1178         }
1179
1180         return regs;
1181 }
1182
1183 GList*
1184 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1185 {
1186         GList *regs = NULL;
1187         int i;
1188
1189         /* All XMM registers */
1190         for (i = 0; i < 16; ++i)
1191                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1192
1193         return regs;
1194 }
1195
1196 GList*
1197 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1198 {
1199         static GList *r = NULL;
1200
1201         if (r == NULL) {
1202                 GList *regs = NULL;
1203
1204                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1205                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1206                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1207                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1208                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1209                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1210
1211                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1212                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1213                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1214                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1215                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1216                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1217                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1218                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1219
1220                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1221         }
1222
1223         return r;
1224 }
1225
1226 GList*
1227 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1228 {
1229         int i;
1230         static GList *r = NULL;
1231
1232         if (r == NULL) {
1233                 GList *regs = NULL;
1234
1235                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1236                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1237
1238                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1239         }
1240
1241         return r;
1242 }
1243
1244 /*
1245  * mono_arch_regalloc_cost:
1246  *
1247  *  Return the cost, in number of memory references, of the action of
1248  * allocating the variable VMV into a register during global register
1249  * allocation.
1250  */
1251 guint32
1252 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1253 {
1254         MonoInst *ins = cfg->varinfo [vmv->idx];
1255
1256         if (cfg->method->save_lmf)
1257                 /* The register is already saved */
1258                 /* substract 1 for the invisible store in the prolog */
1259                 return (ins->opcode == OP_ARG) ? 0 : 1;
1260         else
1261                 /* push+pop */
1262                 return (ins->opcode == OP_ARG) ? 1 : 2;
1263 }
1264
1265 /*
1266  * mono_arch_fill_argument_info:
1267  *
1268  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1269  * of the method.
1270  */
1271 void
1272 mono_arch_fill_argument_info (MonoCompile *cfg)
1273 {
1274         MonoMethodSignature *sig;
1275         MonoMethodHeader *header;
1276         MonoInst *ins;
1277         int i;
1278         CallInfo *cinfo;
1279
1280         header = cfg->header;
1281
1282         sig = mono_method_signature (cfg->method);
1283
1284         cinfo = cfg->arch.cinfo;
1285
1286         /*
1287          * Contrary to mono_arch_allocate_vars (), the information should describe
1288          * where the arguments are at the beginning of the method, not where they can be
1289          * accessed during the execution of the method. The later makes no sense for the
1290          * global register allocator, since a variable can be in more than one location.
1291          */
1292         if (sig->ret->type != MONO_TYPE_VOID) {
1293                 switch (cinfo->ret.storage) {
1294                 case ArgInIReg:
1295                 case ArgInFloatSSEReg:
1296                 case ArgInDoubleSSEReg:
1297                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1298                                 cfg->vret_addr->opcode = OP_REGVAR;
1299                                 cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1300                         }
1301                         else {
1302                                 cfg->ret->opcode = OP_REGVAR;
1303                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1304                         }
1305                         break;
1306                 case ArgValuetypeInReg:
1307                         cfg->ret->opcode = OP_REGOFFSET;
1308                         cfg->ret->inst_basereg = -1;
1309                         cfg->ret->inst_offset = -1;
1310                         break;
1311                 default:
1312                         g_assert_not_reached ();
1313                 }
1314         }
1315
1316         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1317                 ArgInfo *ainfo = &cinfo->args [i];
1318                 MonoType *arg_type;
1319
1320                 ins = cfg->args [i];
1321
1322                 if (sig->hasthis && (i == 0))
1323                         arg_type = &mono_defaults.object_class->byval_arg;
1324                 else
1325                         arg_type = sig->params [i - sig->hasthis];
1326
1327                 switch (ainfo->storage) {
1328                 case ArgInIReg:
1329                 case ArgInFloatSSEReg:
1330                 case ArgInDoubleSSEReg:
1331                         ins->opcode = OP_REGVAR;
1332                         ins->inst_c0 = ainfo->reg;
1333                         break;
1334                 case ArgOnStack:
1335                         ins->opcode = OP_REGOFFSET;
1336                         ins->inst_basereg = -1;
1337                         ins->inst_offset = -1;
1338                         break;
1339                 case ArgValuetypeInReg:
1340                         /* Dummy */
1341                         ins->opcode = OP_NOP;
1342                         break;
1343                 default:
1344                         g_assert_not_reached ();
1345                 }
1346         }
1347 }
1348
1349 void
1350 mono_arch_allocate_vars (MonoCompile *cfg)
1351 {
1352         MonoMethodSignature *sig;
1353         MonoMethodHeader *header;
1354         MonoInst *ins;
1355         int i, offset;
1356         guint32 locals_stack_size, locals_stack_align;
1357         gint32 *offsets;
1358         CallInfo *cinfo;
1359
1360         header = cfg->header;
1361
1362         sig = mono_method_signature (cfg->method);
1363
1364         cinfo = cfg->arch.cinfo;
1365
1366         mono_arch_compute_omit_fp (cfg);
1367
1368         /*
1369          * We use the ABI calling conventions for managed code as well.
1370          * Exception: valuetypes are only sometimes passed or returned in registers.
1371          */
1372
1373         /*
1374          * The stack looks like this:
1375          * <incoming arguments passed on the stack>
1376          * <return value>
1377          * <lmf/caller saved registers>
1378          * <locals>
1379          * <spill area>
1380          * <localloc area>  -> grows dynamically
1381          * <params area>
1382          */
1383
1384         if (cfg->arch.omit_fp) {
1385                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1386                 cfg->frame_reg = AMD64_RSP;
1387                 offset = 0;
1388         } else {
1389                 /* Locals are allocated backwards from %fp */
1390                 cfg->frame_reg = AMD64_RBP;
1391                 offset = 0;
1392         }
1393
1394         if (cfg->method->save_lmf) {
1395                 /* Reserve stack space for saving LMF */
1396                 if (cfg->arch.omit_fp) {
1397                         cfg->arch.lmf_offset = offset;
1398                         offset += sizeof (MonoLMF);
1399                 }
1400                 else {
1401                         offset += sizeof (MonoLMF);
1402                         cfg->arch.lmf_offset = -offset;
1403                 }
1404         } else {
1405                 if (cfg->arch.omit_fp)
1406                         cfg->arch.reg_save_area_offset = offset;
1407                 /* Reserve space for caller saved registers */
1408                 for (i = 0; i < AMD64_NREG; ++i)
1409                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
1410                                 offset += sizeof (gpointer);
1411                         }
1412         }
1413
1414         if (sig->ret->type != MONO_TYPE_VOID) {
1415                 switch (cinfo->ret.storage) {
1416                 case ArgInIReg:
1417                 case ArgInFloatSSEReg:
1418                 case ArgInDoubleSSEReg:
1419                         if ((MONO_TYPE_ISSTRUCT (sig->ret) && !mono_class_from_mono_type (sig->ret)->enumtype) || (sig->ret->type == MONO_TYPE_TYPEDBYREF)) {
1420                                 if (cfg->globalra) {
1421                                         cfg->vret_addr->opcode = OP_REGVAR;
1422                                         cfg->vret_addr->inst_c0 = cinfo->ret.reg;
1423                                 } else {
1424                                         /* The register is volatile */
1425                                         cfg->vret_addr->opcode = OP_REGOFFSET;
1426                                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1427                                         if (cfg->arch.omit_fp) {
1428                                                 cfg->vret_addr->inst_offset = offset;
1429                                                 offset += 8;
1430                                         } else {
1431                                                 offset += 8;
1432                                                 cfg->vret_addr->inst_offset = -offset;
1433                                         }
1434                                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1435                                                 printf ("vret_addr =");
1436                                                 mono_print_ins (cfg->vret_addr);
1437                                         }
1438                                 }
1439                         }
1440                         else {
1441                                 cfg->ret->opcode = OP_REGVAR;
1442                                 cfg->ret->inst_c0 = cinfo->ret.reg;
1443                         }
1444                         break;
1445                 case ArgValuetypeInReg:
1446                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1447                         cfg->ret->opcode = OP_REGOFFSET;
1448                         cfg->ret->inst_basereg = cfg->frame_reg;
1449                         if (cfg->arch.omit_fp) {
1450                                 cfg->ret->inst_offset = offset;
1451                                 offset += 16;
1452                         } else {
1453                                 offset += 16;
1454                                 cfg->ret->inst_offset = - offset;
1455                         }
1456                         break;
1457                 default:
1458                         g_assert_not_reached ();
1459                 }
1460                 if (!cfg->globalra)
1461                         cfg->ret->dreg = cfg->ret->inst_c0;
1462         }
1463
1464         /* Allocate locals */
1465         if (!cfg->globalra) {
1466                 offsets = mono_allocate_stack_slots_full (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1467                 if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1468                         char *mname = mono_method_full_name (cfg->method, TRUE);
1469                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1470                         cfg->exception_message = g_strdup_printf ("Method %s stack is too big.", mname);
1471                         g_free (mname);
1472                         return;
1473                 }
1474
1475                 if (locals_stack_align) {
1476                         offset += (locals_stack_align - 1);
1477                         offset &= ~(locals_stack_align - 1);
1478                 }
1479                 if (cfg->arch.omit_fp) {
1480                         cfg->locals_min_stack_offset = offset;
1481                         cfg->locals_max_stack_offset = offset + locals_stack_size;
1482                 } else {
1483                         cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1484                         cfg->locals_max_stack_offset = - offset;
1485                 }
1486
1487                 for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1488                         if (offsets [i] != -1) {
1489                                 MonoInst *ins = cfg->varinfo [i];
1490                                 ins->opcode = OP_REGOFFSET;
1491                                 ins->inst_basereg = cfg->frame_reg;
1492                                 if (cfg->arch.omit_fp)
1493                                         ins->inst_offset = (offset + offsets [i]);
1494                                 else
1495                                         ins->inst_offset = - (offset + offsets [i]);
1496                                 //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1497                         }
1498                 }
1499                 offset += locals_stack_size;
1500         }
1501
1502         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1503                 g_assert (!cfg->arch.omit_fp);
1504                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1505                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1506         }
1507
1508         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1509                 ins = cfg->args [i];
1510                 if (ins->opcode != OP_REGVAR) {
1511                         ArgInfo *ainfo = &cinfo->args [i];
1512                         gboolean inreg = TRUE;
1513                         MonoType *arg_type;
1514
1515                         if (sig->hasthis && (i == 0))
1516                                 arg_type = &mono_defaults.object_class->byval_arg;
1517                         else
1518                                 arg_type = sig->params [i - sig->hasthis];
1519
1520                         if (cfg->globalra) {
1521                                 /* The new allocator needs info about the original locations of the arguments */
1522                                 switch (ainfo->storage) {
1523                                 case ArgInIReg:
1524                                 case ArgInFloatSSEReg:
1525                                 case ArgInDoubleSSEReg:
1526                                         ins->opcode = OP_REGVAR;
1527                                         ins->inst_c0 = ainfo->reg;
1528                                         break;
1529                                 case ArgOnStack:
1530                                         g_assert (!cfg->arch.omit_fp);
1531                                         ins->opcode = OP_REGOFFSET;
1532                                         ins->inst_basereg = cfg->frame_reg;
1533                                         ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1534                                         break;
1535                                 case ArgValuetypeInReg:
1536                                         ins->opcode = OP_REGOFFSET;
1537                                         ins->inst_basereg = cfg->frame_reg;
1538                                         /* These arguments are saved to the stack in the prolog */
1539                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1540                                         if (cfg->arch.omit_fp) {
1541                                                 ins->inst_offset = offset;
1542                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1543                                         } else {
1544                                                 offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1545                                                 ins->inst_offset = - offset;
1546                                         }
1547                                         break;
1548                                 default:
1549                                         g_assert_not_reached ();
1550                                 }
1551
1552                                 continue;
1553                         }
1554
1555                         /* FIXME: Allocate volatile arguments to registers */
1556                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
1557                                 inreg = FALSE;
1558
1559                         /*
1560                          * Under AMD64, all registers used to pass arguments to functions
1561                          * are volatile across calls.
1562                          * FIXME: Optimize this.
1563                          */
1564                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg))
1565                                 inreg = FALSE;
1566
1567                         ins->opcode = OP_REGOFFSET;
1568
1569                         switch (ainfo->storage) {
1570                         case ArgInIReg:
1571                         case ArgInFloatSSEReg:
1572                         case ArgInDoubleSSEReg:
1573                                 if (inreg) {
1574                                         ins->opcode = OP_REGVAR;
1575                                         ins->dreg = ainfo->reg;
1576                                 }
1577                                 break;
1578                         case ArgOnStack:
1579                                 g_assert (!cfg->arch.omit_fp);
1580                                 ins->opcode = OP_REGOFFSET;
1581                                 ins->inst_basereg = cfg->frame_reg;
1582                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
1583                                 break;
1584                         case ArgValuetypeInReg:
1585                                 break;
1586                         case ArgValuetypeAddrInIReg: {
1587                                 MonoInst *indir;
1588                                 g_assert (!cfg->arch.omit_fp);
1589
1590                                 MONO_INST_NEW (cfg, indir, 0);
1591                                 indir->opcode = OP_REGOFFSET;
1592                                 if (ainfo->pair_storage [0] == ArgInIReg) {
1593                                         indir->inst_basereg = cfg->frame_reg;
1594                                         offset = ALIGN_TO (offset, sizeof (gpointer));
1595                                         offset += (sizeof (gpointer));
1596                                         indir->inst_offset = - offset;
1597                                 }
1598                                 else {
1599                                         indir->inst_basereg = cfg->frame_reg;
1600                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
1601                                 }
1602
1603                                 ins->opcode = OP_VTARG_ADDR;
1604                                 ins->inst_left = indir;
1605
1606                                 break;
1607                         }
1608                         default:
1609                                 NOT_IMPLEMENTED;
1610                         }
1611
1612                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg)) {
1613                                 ins->opcode = OP_REGOFFSET;
1614                                 ins->inst_basereg = cfg->frame_reg;
1615                                 /* These arguments are saved to the stack in the prolog */
1616                                 offset = ALIGN_TO (offset, sizeof (gpointer));
1617                                 if (cfg->arch.omit_fp) {
1618                                         ins->inst_offset = offset;
1619                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1620                                         // Arguments are yet supported by the stack map creation code
1621                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
1622                                 } else {
1623                                         offset += (ainfo->storage == ArgValuetypeInReg) ? 2 * sizeof (gpointer) : sizeof (gpointer);
1624                                         ins->inst_offset = - offset;
1625                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
1626                                 }
1627                         }
1628                 }
1629         }
1630
1631         cfg->stack_offset = offset;
1632 }
1633
1634 void
1635 mono_arch_create_vars (MonoCompile *cfg)
1636 {
1637         MonoMethodSignature *sig;
1638         CallInfo *cinfo;
1639
1640         sig = mono_method_signature (cfg->method);
1641
1642         if (!cfg->arch.cinfo)
1643                 cfg->arch.cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
1644         cinfo = cfg->arch.cinfo;
1645
1646         if (cinfo->ret.storage == ArgValuetypeInReg)
1647                 cfg->ret_var_is_local = TRUE;
1648
1649         if ((cinfo->ret.storage != ArgValuetypeInReg) && MONO_TYPE_ISSTRUCT (sig->ret)) {
1650                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
1651                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
1652                         printf ("vret_addr = ");
1653                         mono_print_ins (cfg->vret_addr);
1654                 }
1655         }
1656
1657         if (cfg->gen_seq_points) {
1658                 MonoInst *ins;
1659
1660             ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
1661                 ins->flags |= MONO_INST_VOLATILE;
1662                 cfg->arch.ss_trigger_page_var = ins;
1663         }
1664
1665 #ifdef MONO_AMD64_NO_PUSHES
1666         /*
1667          * When this is set, we pass arguments on the stack by moves, and by allocating
1668          * a bigger stack frame, instead of pushes.
1669          * Pushes complicate exception handling because the arguments on the stack have
1670          * to be popped each time a frame is unwound. They also make fp elimination
1671          * impossible.
1672          * FIXME: This doesn't work inside filter/finally clauses, since those execute
1673          * on a new frame which doesn't include a param area.
1674          */
1675         cfg->arch.no_pushes = TRUE;
1676 #endif
1677 }
1678
1679 static void
1680 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
1681 {
1682         MonoInst *ins;
1683
1684         switch (storage) {
1685         case ArgInIReg:
1686                 MONO_INST_NEW (cfg, ins, OP_MOVE);
1687                 ins->dreg = mono_alloc_ireg (cfg);
1688                 ins->sreg1 = tree->dreg;
1689                 MONO_ADD_INS (cfg->cbb, ins);
1690                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
1691                 break;
1692         case ArgInFloatSSEReg:
1693                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
1694                 ins->dreg = mono_alloc_freg (cfg);
1695                 ins->sreg1 = tree->dreg;
1696                 MONO_ADD_INS (cfg->cbb, ins);
1697
1698                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1699                 break;
1700         case ArgInDoubleSSEReg:
1701                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
1702                 ins->dreg = mono_alloc_freg (cfg);
1703                 ins->sreg1 = tree->dreg;
1704                 MONO_ADD_INS (cfg->cbb, ins);
1705
1706                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
1707
1708                 break;
1709         default:
1710                 g_assert_not_reached ();
1711         }
1712 }
1713
1714 static int
1715 arg_storage_to_load_membase (ArgStorage storage)
1716 {
1717         switch (storage) {
1718         case ArgInIReg:
1719                 return OP_LOAD_MEMBASE;
1720         case ArgInDoubleSSEReg:
1721                 return OP_LOADR8_MEMBASE;
1722         case ArgInFloatSSEReg:
1723                 return OP_LOADR4_MEMBASE;
1724         default:
1725                 g_assert_not_reached ();
1726         }
1727
1728         return -1;
1729 }
1730
1731 static void
1732 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
1733 {
1734         MonoInst *arg;
1735         MonoMethodSignature *tmp_sig;
1736         MonoInst *sig_arg;
1737
1738         if (call->tail_call)
1739                 NOT_IMPLEMENTED;
1740
1741         /* FIXME: Add support for signature tokens to AOT */
1742         cfg->disable_aot = TRUE;
1743
1744         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1745
1746         /*
1747          * mono_ArgIterator_Setup assumes the signature cookie is
1748          * passed first and all the arguments which were before it are
1749          * passed on the stack after the signature. So compensate by
1750          * passing a different signature.
1751          */
1752         tmp_sig = mono_metadata_signature_dup (call->signature);
1753         tmp_sig->param_count -= call->signature->sentinelpos;
1754         tmp_sig->sentinelpos = 0;
1755         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
1756
1757         MONO_INST_NEW (cfg, sig_arg, OP_ICONST);
1758         sig_arg->dreg = mono_alloc_ireg (cfg);
1759         sig_arg->inst_p0 = tmp_sig;
1760         MONO_ADD_INS (cfg->cbb, sig_arg);
1761
1762         if (cfg->arch.no_pushes) {
1763                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_arg->dreg);
1764         } else {
1765                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
1766                 arg->sreg1 = sig_arg->dreg;
1767                 MONO_ADD_INS (cfg->cbb, arg);
1768         }
1769 }
1770
1771 static inline LLVMArgStorage
1772 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
1773 {
1774         switch (storage) {
1775         case ArgInIReg:
1776                 return LLVMArgInIReg;
1777         case ArgNone:
1778                 return LLVMArgNone;
1779         default:
1780                 g_assert_not_reached ();
1781                 return LLVMArgNone;
1782         }
1783 }
1784
1785 #ifdef ENABLE_LLVM
1786 LLVMCallInfo*
1787 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
1788 {
1789         int i, n;
1790         CallInfo *cinfo;
1791         ArgInfo *ainfo;
1792         int j;
1793         LLVMCallInfo *linfo;
1794         MonoType *t;
1795
1796         n = sig->param_count + sig->hasthis;
1797
1798         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1799
1800         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
1801
1802         /*
1803          * LLVM always uses the native ABI while we use our own ABI, the
1804          * only difference is the handling of vtypes:
1805          * - we only pass/receive them in registers in some cases, and only
1806          *   in 1 or 2 integer registers.
1807          */
1808         if (cinfo->ret.storage == ArgValuetypeInReg) {
1809                 if (sig->pinvoke) {
1810                         cfg->exception_message = g_strdup ("pinvoke + vtypes");
1811                         cfg->disable_llvm = TRUE;
1812                         return linfo;
1813                 }
1814
1815                 linfo->ret.storage = LLVMArgVtypeInReg;
1816                 for (j = 0; j < 2; ++j)
1817                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, cinfo->ret.pair_storage [j]);
1818         }
1819
1820         if (MONO_TYPE_ISSTRUCT (sig->ret) && cinfo->ret.storage == ArgInIReg) {
1821                 /* Vtype returned using a hidden argument */
1822                 linfo->ret.storage = LLVMArgVtypeRetAddr;
1823                 linfo->vret_arg_index = cinfo->vret_arg_index;
1824         }
1825
1826         for (i = 0; i < n; ++i) {
1827                 ainfo = cinfo->args + i;
1828
1829                 if (i >= sig->hasthis)
1830                         t = sig->params [i - sig->hasthis];
1831                 else
1832                         t = &mono_defaults.int_class->byval_arg;
1833
1834                 linfo->args [i].storage = LLVMArgNone;
1835
1836                 switch (ainfo->storage) {
1837                 case ArgInIReg:
1838                         linfo->args [i].storage = LLVMArgInIReg;
1839                         break;
1840                 case ArgInDoubleSSEReg:
1841                 case ArgInFloatSSEReg:
1842                         linfo->args [i].storage = LLVMArgInFPReg;
1843                         break;
1844                 case ArgOnStack:
1845                         if (MONO_TYPE_ISSTRUCT (t)) {
1846                                 linfo->args [i].storage = LLVMArgVtypeByVal;
1847                         } else {
1848                                 linfo->args [i].storage = LLVMArgInIReg;
1849                                 if (!t->byref) {
1850                                         if (t->type == MONO_TYPE_R4)
1851                                                 linfo->args [i].storage = LLVMArgInFPReg;
1852                                         else if (t->type == MONO_TYPE_R8)
1853                                                 linfo->args [i].storage = LLVMArgInFPReg;
1854                                 }
1855                         }
1856                         break;
1857                 case ArgValuetypeInReg:
1858                         if (sig->pinvoke) {
1859                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
1860                                 cfg->disable_llvm = TRUE;
1861                                 return linfo;
1862                         }
1863
1864                         linfo->args [i].storage = LLVMArgVtypeInReg;
1865                         for (j = 0; j < 2; ++j)
1866                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
1867                         break;
1868                 default:
1869                         cfg->exception_message = g_strdup ("ainfo->storage");
1870                         cfg->disable_llvm = TRUE;
1871                         break;
1872                 }
1873         }
1874
1875         return linfo;
1876 }
1877 #endif
1878
1879 void
1880 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
1881 {
1882         MonoInst *arg, *in;
1883         MonoMethodSignature *sig;
1884         int i, n, stack_size;
1885         CallInfo *cinfo;
1886         ArgInfo *ainfo;
1887
1888         stack_size = 0;
1889
1890         sig = call->signature;
1891         n = sig->param_count + sig->hasthis;
1892
1893         cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, sig->pinvoke);
1894
1895         if (COMPILE_LLVM (cfg)) {
1896                 /* We shouldn't be called in the llvm case */
1897                 cfg->disable_llvm = TRUE;
1898                 return;
1899         }
1900
1901         if (cinfo->need_stack_align) {
1902                 if (!cfg->arch.no_pushes)
1903                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
1904         }
1905
1906         /*
1907          * Emit all arguments which are passed on the stack to prevent register
1908          * allocation problems.
1909          */
1910         if (cfg->arch.no_pushes) {
1911                 for (i = 0; i < n; ++i) {
1912                         MonoType *t;
1913                         ainfo = cinfo->args + i;
1914
1915                         in = call->args [i];
1916
1917                         if (sig->hasthis && i == 0)
1918                                 t = &mono_defaults.object_class->byval_arg;
1919                         else
1920                                 t = sig->params [i - sig->hasthis];
1921
1922                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
1923                                 if (!t->byref) {
1924                                         if (t->type == MONO_TYPE_R4)
1925                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1926                                         else if (t->type == MONO_TYPE_R8)
1927                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1928                                         else
1929                                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1930                                 } else {
1931                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
1932                                 }
1933                         }
1934                 }
1935         }
1936
1937         /*
1938          * Emit all parameters passed in registers in non-reverse order for better readability
1939          * and to help the optimization in emit_prolog ().
1940          */
1941         for (i = 0; i < n; ++i) {
1942                 ainfo = cinfo->args + i;
1943
1944                 in = call->args [i];
1945
1946                 if (ainfo->storage == ArgInIReg)
1947                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1948         }
1949
1950         for (i = n - 1; i >= 0; --i) {
1951                 ainfo = cinfo->args + i;
1952
1953                 in = call->args [i];
1954
1955                 switch (ainfo->storage) {
1956                 case ArgInIReg:
1957                         /* Already done */
1958                         break;
1959                 case ArgInFloatSSEReg:
1960                 case ArgInDoubleSSEReg:
1961                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
1962                         break;
1963                 case ArgOnStack:
1964                 case ArgValuetypeInReg:
1965                 case ArgValuetypeAddrInIReg:
1966                         if (ainfo->storage == ArgOnStack && call->tail_call) {
1967                                 MonoInst *call_inst = (MonoInst*)call;
1968                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
1969                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
1970                         } else if ((i >= sig->hasthis) && (MONO_TYPE_ISSTRUCT(sig->params [i - sig->hasthis]))) {
1971                                 guint32 align;
1972                                 guint32 size;
1973
1974                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_TYPEDBYREF) {
1975                                         size = sizeof (MonoTypedRef);
1976                                         align = sizeof (gpointer);
1977                                 }
1978                                 else {
1979                                         if (sig->pinvoke)
1980                                                 size = mono_type_native_stack_size (&in->klass->byval_arg, &align);
1981                                         else {
1982                                                 /*
1983                                                  * Other backends use mono_type_stack_size (), but that
1984                                                  * aligns the size to 8, which is larger than the size of
1985                                                  * the source, leading to reads of invalid memory if the
1986                                                  * source is at the end of address space.
1987                                                  */
1988                                                 size = mono_class_value_size (in->klass, &align);
1989                                         }
1990                                 }
1991                                 g_assert (in->klass);
1992
1993                                 if (ainfo->storage == ArgOnStack && size >= 10000) {
1994                                         /* Avoid asserts in emit_memcpy () */
1995                                         cfg->exception_type = MONO_EXCEPTION_INVALID_PROGRAM;
1996                                         cfg->exception_message = g_strdup_printf ("Passing an argument of size '%d'.", size);
1997                                         /* Continue normally */
1998                                 }
1999
2000                                 if (size > 0) {
2001                                         MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2002                                         arg->sreg1 = in->dreg;
2003                                         arg->klass = in->klass;
2004                                         arg->backend.size = size;
2005                                         arg->inst_p0 = call;
2006                                         arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2007                                         memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2008
2009                                         MONO_ADD_INS (cfg->cbb, arg);
2010                                 }
2011                         } else {
2012                                 if (cfg->arch.no_pushes) {
2013                                         /* Already done */
2014                                 } else {
2015                                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2016                                         arg->sreg1 = in->dreg;
2017                                         if (!sig->params [i - sig->hasthis]->byref) {
2018                                                 if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R4) {
2019                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2020                                                         arg->opcode = OP_STORER4_MEMBASE_REG;
2021                                                         arg->inst_destbasereg = X86_ESP;
2022                                                         arg->inst_offset = 0;
2023                                                 } else if (sig->params [i - sig->hasthis]->type == MONO_TYPE_R8) {
2024                                                         MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
2025                                                         arg->opcode = OP_STORER8_MEMBASE_REG;
2026                                                         arg->inst_destbasereg = X86_ESP;
2027                                                         arg->inst_offset = 0;
2028                                                 }
2029                                         }
2030                                         MONO_ADD_INS (cfg->cbb, arg);
2031                                 }
2032                         }
2033                         break;
2034                 default:
2035                         g_assert_not_reached ();
2036                 }
2037
2038                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2039                         /* Emit the signature cookie just before the implicit arguments */
2040                         emit_sig_cookie (cfg, call, cinfo);
2041         }
2042
2043         /* Handle the case where there are no implicit arguments */
2044         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2045                 emit_sig_cookie (cfg, call, cinfo);
2046
2047         if (sig->ret && MONO_TYPE_ISSTRUCT (sig->ret)) {
2048                 MonoInst *vtarg;
2049
2050                 if (cinfo->ret.storage == ArgValuetypeInReg) {
2051                         if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2052                                 /*
2053                                  * Tell the JIT to use a more efficient calling convention: call using
2054                                  * OP_CALL, compute the result location after the call, and save the
2055                                  * result there.
2056                                  */
2057                                 call->vret_in_reg = TRUE;
2058                                 /*
2059                                  * Nullify the instruction computing the vret addr to enable
2060                                  * future optimizations.
2061                                  */
2062                                 if (call->vret_var)
2063                                         NULLIFY_INS (call->vret_var);
2064                         } else {
2065                                 if (call->tail_call)
2066                                         NOT_IMPLEMENTED;
2067                                 /*
2068                                  * The valuetype is in RAX:RDX after the call, need to be copied to
2069                                  * the stack. Push the address here, so the call instruction can
2070                                  * access it.
2071                                  */
2072                                 if (!cfg->arch.vret_addr_loc) {
2073                                         cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2074                                         /* Prevent it from being register allocated or optimized away */
2075                                         ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2076                                 }
2077
2078                                 MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2079                         }
2080                 }
2081                 else {
2082                         MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2083                         vtarg->sreg1 = call->vret_var->dreg;
2084                         vtarg->dreg = mono_alloc_preg (cfg);
2085                         MONO_ADD_INS (cfg->cbb, vtarg);
2086
2087                         mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2088                 }
2089         }
2090
2091 #ifdef HOST_WIN32
2092         if (call->inst.opcode != OP_JMP && OP_TAILCALL != call->inst.opcode) {
2093                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, 0x20);
2094         }
2095 #endif
2096
2097         if (cfg->method->save_lmf) {
2098                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2099                 MONO_ADD_INS (cfg->cbb, arg);
2100         }
2101
2102         call->stack_usage = cinfo->stack_usage;
2103 }
2104
2105 void
2106 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2107 {
2108         MonoInst *arg;
2109         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2110         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2111         int size = ins->backend.size;
2112
2113         if (ainfo->storage == ArgValuetypeInReg) {
2114                 MonoInst *load;
2115                 int part;
2116
2117                 for (part = 0; part < 2; ++part) {
2118                         if (ainfo->pair_storage [part] == ArgNone)
2119                                 continue;
2120
2121                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2122                         load->inst_basereg = src->dreg;
2123                         load->inst_offset = part * sizeof (gpointer);
2124
2125                         switch (ainfo->pair_storage [part]) {
2126                         case ArgInIReg:
2127                                 load->dreg = mono_alloc_ireg (cfg);
2128                                 break;
2129                         case ArgInDoubleSSEReg:
2130                         case ArgInFloatSSEReg:
2131                                 load->dreg = mono_alloc_freg (cfg);
2132                                 break;
2133                         default:
2134                                 g_assert_not_reached ();
2135                         }
2136                         MONO_ADD_INS (cfg->cbb, load);
2137
2138                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2139                 }
2140         } else if (ainfo->storage == ArgValuetypeAddrInIReg) {
2141                 MonoInst *vtaddr, *load;
2142                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2143
2144                 g_assert (!cfg->arch.no_pushes);
2145
2146                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2147                 load->inst_p0 = vtaddr;
2148                 vtaddr->flags |= MONO_INST_INDIRECT;
2149                 load->type = STACK_MP;
2150                 load->klass = vtaddr->klass;
2151                 load->dreg = mono_alloc_ireg (cfg);
2152                 MONO_ADD_INS (cfg->cbb, load);
2153                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2154
2155                 if (ainfo->pair_storage [0] == ArgInIReg) {
2156                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2157                         arg->dreg = mono_alloc_ireg (cfg);
2158                         arg->sreg1 = load->dreg;
2159                         arg->inst_imm = 0;
2160                         MONO_ADD_INS (cfg->cbb, arg);
2161                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2162                 } else {
2163                         MONO_INST_NEW (cfg, arg, OP_X86_PUSH);
2164                         arg->sreg1 = load->dreg;
2165                         MONO_ADD_INS (cfg->cbb, arg);
2166                 }
2167         } else {
2168                 if (size == 8) {
2169                         if (cfg->arch.no_pushes) {
2170                                 int dreg = mono_alloc_ireg (cfg);
2171
2172                                 MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2173                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2174                         } else {
2175                                 /* Can't use this for < 8 since it does an 8 byte memory load */
2176                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_MEMBASE);
2177                                 arg->inst_basereg = src->dreg;
2178                                 arg->inst_offset = 0;
2179                                 MONO_ADD_INS (cfg->cbb, arg);
2180                         }
2181                 } else if (size <= 40) {
2182                         if (cfg->arch.no_pushes) {
2183                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2184                         } else {
2185                                 MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP, X86_ESP, ALIGN_TO (size, 8));
2186                                 mini_emit_memcpy (cfg, X86_ESP, 0, src->dreg, 0, size, 4);
2187                         }
2188                 } else {
2189                         if (cfg->arch.no_pushes) {
2190                                 // FIXME: Code growth
2191                                 mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2192                         } else {
2193                                 MONO_INST_NEW (cfg, arg, OP_X86_PUSH_OBJ);
2194                                 arg->inst_basereg = src->dreg;
2195                                 arg->inst_offset = 0;
2196                                 arg->inst_imm = size;
2197                                 MONO_ADD_INS (cfg->cbb, arg);
2198                         }
2199                 }
2200         }
2201 }
2202
2203 void
2204 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2205 {
2206         MonoType *ret = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
2207
2208         if (ret->type == MONO_TYPE_R4) {
2209                 if (COMPILE_LLVM (cfg))
2210                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2211                 else
2212                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2213                 return;
2214         } else if (ret->type == MONO_TYPE_R8) {
2215                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2216                 return;
2217         }
2218
2219         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2220 }
2221
2222 #endif /* DISABLE_JIT */
2223
2224 #define EMIT_COND_BRANCH(ins,cond,sign) \
2225         if (ins->inst_true_bb->native_offset) { \
2226                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2227         } else { \
2228                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2229                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2230             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2231                         x86_branch8 (code, cond, 0, sign); \
2232                 else \
2233                         x86_branch32 (code, cond, 0, sign); \
2234 }
2235
2236 typedef struct {
2237         MonoMethodSignature *sig;
2238         CallInfo *cinfo;
2239 } ArchDynCallInfo;
2240
2241 typedef struct {
2242         mgreg_t regs [PARAM_REGS];
2243         mgreg_t res;
2244         guint8 *ret;
2245 } DynCallArgs;
2246
2247 static gboolean
2248 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2249 {
2250         int i;
2251
2252 #ifdef HOST_WIN32
2253         return FALSE;
2254 #endif
2255
2256         switch (cinfo->ret.storage) {
2257         case ArgNone:
2258         case ArgInIReg:
2259                 break;
2260         case ArgValuetypeInReg: {
2261                 ArgInfo *ainfo = &cinfo->ret;
2262
2263                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2264                         return FALSE;
2265                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2266                         return FALSE;
2267                 break;
2268         }
2269         default:
2270                 return FALSE;
2271         }
2272
2273         for (i = 0; i < cinfo->nargs; ++i) {
2274                 ArgInfo *ainfo = &cinfo->args [i];
2275                 switch (ainfo->storage) {
2276                 case ArgInIReg:
2277                         break;
2278                 case ArgValuetypeInReg:
2279                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2280                                 return FALSE;
2281                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2282                                 return FALSE;
2283                         break;
2284                 default:
2285                         return FALSE;
2286                 }
2287         }
2288
2289         return TRUE;
2290 }
2291
2292 /*
2293  * mono_arch_dyn_call_prepare:
2294  *
2295  *   Return a pointer to an arch-specific structure which contains information
2296  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2297  * supported for SIG.
2298  * This function is equivalent to ffi_prep_cif in libffi.
2299  */
2300 MonoDynCallInfo*
2301 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2302 {
2303         ArchDynCallInfo *info;
2304         CallInfo *cinfo;
2305
2306         cinfo = get_call_info (NULL, NULL, sig, FALSE);
2307
2308         if (!dyn_call_supported (sig, cinfo)) {
2309                 g_free (cinfo);
2310                 return NULL;
2311         }
2312
2313         info = g_new0 (ArchDynCallInfo, 1);
2314         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2315         info->sig = sig;
2316         info->cinfo = cinfo;
2317
2318         return (MonoDynCallInfo*)info;
2319 }
2320
2321 /*
2322  * mono_arch_dyn_call_free:
2323  *
2324  *   Free a MonoDynCallInfo structure.
2325  */
2326 void
2327 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2328 {
2329         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2330
2331         g_free (ainfo->cinfo);
2332         g_free (ainfo);
2333 }
2334
2335 /*
2336  * mono_arch_get_start_dyn_call:
2337  *
2338  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2339  * store the result into BUF.
2340  * ARGS should be an array of pointers pointing to the arguments.
2341  * RET should point to a memory buffer large enought to hold the result of the
2342  * call.
2343  * This function should be as fast as possible, any work which does not depend
2344  * on the actual values of the arguments should be done in
2345  * mono_arch_dyn_call_prepare ().
2346  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2347  * libffi.
2348  */
2349 void
2350 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2351 {
2352         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2353         DynCallArgs *p = (DynCallArgs*)buf;
2354         int arg_index, greg, i;
2355         MonoMethodSignature *sig = dinfo->sig;
2356
2357         g_assert (buf_len >= sizeof (DynCallArgs));
2358
2359         p->res = 0;
2360         p->ret = ret;
2361
2362         arg_index = 0;
2363         greg = 0;
2364
2365         if (dinfo->cinfo->vtype_retaddr)
2366                 p->regs [greg ++] = (mgreg_t)ret;
2367
2368         if (sig->hasthis) {
2369                 p->regs [greg ++] = (mgreg_t)*(args [arg_index ++]);
2370         }
2371
2372         for (i = 0; i < sig->param_count; i++) {
2373                 MonoType *t = mono_type_get_underlying_type (sig->params [i]);
2374                 gpointer *arg = args [arg_index ++];
2375
2376                 if (t->byref) {
2377                         p->regs [greg ++] = (mgreg_t)*(arg);
2378                         continue;
2379                 }
2380
2381                 switch (t->type) {
2382                 case MONO_TYPE_STRING:
2383                 case MONO_TYPE_CLASS:
2384                 case MONO_TYPE_ARRAY:
2385                 case MONO_TYPE_SZARRAY:
2386                 case MONO_TYPE_OBJECT:
2387                 case MONO_TYPE_PTR:
2388                 case MONO_TYPE_I:
2389                 case MONO_TYPE_U:
2390                 case MONO_TYPE_I8:
2391                 case MONO_TYPE_U8:
2392                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2393                         p->regs [greg ++] = (mgreg_t)*(arg);
2394                         break;
2395                 case MONO_TYPE_BOOLEAN:
2396                 case MONO_TYPE_U1:
2397                         p->regs [greg ++] = *(guint8*)(arg);
2398                         break;
2399                 case MONO_TYPE_I1:
2400                         p->regs [greg ++] = *(gint8*)(arg);
2401                         break;
2402                 case MONO_TYPE_I2:
2403                         p->regs [greg ++] = *(gint16*)(arg);
2404                         break;
2405                 case MONO_TYPE_U2:
2406                 case MONO_TYPE_CHAR:
2407                         p->regs [greg ++] = *(guint16*)(arg);
2408                         break;
2409                 case MONO_TYPE_I4:
2410                         p->regs [greg ++] = *(gint32*)(arg);
2411                         break;
2412                 case MONO_TYPE_U4:
2413                         p->regs [greg ++] = *(guint32*)(arg);
2414                         break;
2415                 case MONO_TYPE_GENERICINST:
2416                     if (MONO_TYPE_IS_REFERENCE (t)) {
2417                                 p->regs [greg ++] = (mgreg_t)*(arg);
2418                                 break;
2419                         } else {
2420                                 /* Fall through */
2421                         }
2422                 case MONO_TYPE_VALUETYPE: {
2423                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2424
2425                         g_assert (ainfo->storage == ArgValuetypeInReg);
2426                         if (ainfo->pair_storage [0] != ArgNone) {
2427                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2428                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2429                         }
2430                         if (ainfo->pair_storage [1] != ArgNone) {
2431                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2432                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2433                         }
2434                         break;
2435                 }
2436                 default:
2437                         g_assert_not_reached ();
2438                 }
2439         }
2440
2441         g_assert (greg <= PARAM_REGS);
2442 }
2443
2444 /*
2445  * mono_arch_finish_dyn_call:
2446  *
2447  *   Store the result of a dyn call into the return value buffer passed to
2448  * start_dyn_call ().
2449  * This function should be as fast as possible, any work which does not depend
2450  * on the actual values of the arguments should be done in
2451  * mono_arch_dyn_call_prepare ().
2452  */
2453 void
2454 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2455 {
2456         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2457         MonoMethodSignature *sig = dinfo->sig;
2458         guint8 *ret = ((DynCallArgs*)buf)->ret;
2459         mgreg_t res = ((DynCallArgs*)buf)->res;
2460
2461         switch (mono_type_get_underlying_type (sig->ret)->type) {
2462         case MONO_TYPE_VOID:
2463                 *(gpointer*)ret = NULL;
2464                 break;
2465         case MONO_TYPE_STRING:
2466         case MONO_TYPE_CLASS:
2467         case MONO_TYPE_ARRAY:
2468         case MONO_TYPE_SZARRAY:
2469         case MONO_TYPE_OBJECT:
2470         case MONO_TYPE_I:
2471         case MONO_TYPE_U:
2472         case MONO_TYPE_PTR:
2473                 *(gpointer*)ret = (gpointer)res;
2474                 break;
2475         case MONO_TYPE_I1:
2476                 *(gint8*)ret = res;
2477                 break;
2478         case MONO_TYPE_U1:
2479         case MONO_TYPE_BOOLEAN:
2480                 *(guint8*)ret = res;
2481                 break;
2482         case MONO_TYPE_I2:
2483                 *(gint16*)ret = res;
2484                 break;
2485         case MONO_TYPE_U2:
2486         case MONO_TYPE_CHAR:
2487                 *(guint16*)ret = res;
2488                 break;
2489         case MONO_TYPE_I4:
2490                 *(gint32*)ret = res;
2491                 break;
2492         case MONO_TYPE_U4:
2493                 *(guint32*)ret = res;
2494                 break;
2495         case MONO_TYPE_I8:
2496                 *(gint64*)ret = res;
2497                 break;
2498         case MONO_TYPE_U8:
2499                 *(guint64*)ret = res;
2500                 break;
2501         case MONO_TYPE_GENERICINST:
2502                 if (MONO_TYPE_IS_REFERENCE (sig->ret)) {
2503                         *(gpointer*)ret = (gpointer)res;
2504                         break;
2505                 } else {
2506                         /* Fall through */
2507                 }
2508         case MONO_TYPE_VALUETYPE:
2509                 if (dinfo->cinfo->vtype_retaddr) {
2510                         /* Nothing to do */
2511                 } else {
2512                         ArgInfo *ainfo = &dinfo->cinfo->ret;
2513
2514                         g_assert (ainfo->storage == ArgValuetypeInReg);
2515
2516                         if (ainfo->pair_storage [0] != ArgNone) {
2517                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2518                                 ((mgreg_t*)ret)[0] = res;
2519                         }
2520
2521                         g_assert (ainfo->pair_storage [1] == ArgNone);
2522                 }
2523                 break;
2524         default:
2525                 g_assert_not_reached ();
2526         }
2527 }
2528
2529 /* emit an exception if condition is fail */
2530 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
2531         do {                                                        \
2532                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
2533                 if (tins == NULL) {                                                                             \
2534                         mono_add_patch_info (cfg, code - cfg->native_code,   \
2535                                         MONO_PATCH_INFO_EXC, exc_name);  \
2536                         x86_branch32 (code, cond, 0, signed);               \
2537                 } else {        \
2538                         EMIT_COND_BRANCH (tins, cond, signed);  \
2539                 }                       \
2540         } while (0);
2541
2542 #define EMIT_FPCOMPARE(code) do { \
2543         amd64_fcompp (code); \
2544         amd64_fnstsw (code); \
2545 } while (0);
2546
2547 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
2548     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
2549         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
2550         amd64_ ##op (code); \
2551         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
2552         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
2553 } while (0);
2554
2555 static guint8*
2556 emit_call_body (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data)
2557 {
2558         gboolean no_patch = FALSE;
2559
2560         /*
2561          * FIXME: Add support for thunks
2562          */
2563         {
2564                 gboolean near_call = FALSE;
2565
2566                 /*
2567                  * Indirect calls are expensive so try to make a near call if possible.
2568                  * The caller memory is allocated by the code manager so it is
2569                  * guaranteed to be at a 32 bit offset.
2570                  */
2571
2572                 if (patch_type != MONO_PATCH_INFO_ABS) {
2573                         /* The target is in memory allocated using the code manager */
2574                         near_call = TRUE;
2575
2576                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
2577                                 if (((MonoMethod*)data)->klass->image->aot_module)
2578                                         /* The callee might be an AOT method */
2579                                         near_call = FALSE;
2580                                 if (((MonoMethod*)data)->dynamic)
2581                                         /* The target is in malloc-ed memory */
2582                                         near_call = FALSE;
2583                         }
2584
2585                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
2586                                 /*
2587                                  * The call might go directly to a native function without
2588                                  * the wrapper.
2589                                  */
2590                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name (data);
2591                                 if (mi) {
2592                                         gconstpointer target = mono_icall_get_wrapper (mi);
2593                                         if ((((guint64)target) >> 32) != 0)
2594                                                 near_call = FALSE;
2595                                 }
2596                         }
2597                 }
2598                 else {
2599                         if (cfg->abs_patches && g_hash_table_lookup (cfg->abs_patches, data)) {
2600                                 /*
2601                                  * This is not really an optimization, but required because the
2602                                  * generic class init trampolines use R11 to pass the vtable.
2603                                  */
2604                                 near_call = TRUE;
2605                         } else {
2606                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
2607                                 if (info) {
2608                                         if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) &&
2609                                                 strstr (cfg->method->name, info->name)) {
2610                                                 /* A call to the wrapped function */
2611                                                 if ((((guint64)data) >> 32) == 0)
2612                                                         near_call = TRUE;
2613                                                 no_patch = TRUE;
2614                                         }
2615                                         else if (info->func == info->wrapper) {
2616                                                 /* No wrapper */
2617                                                 if ((((guint64)info->func) >> 32) == 0)
2618                                                         near_call = TRUE;
2619                                         }
2620                                         else {
2621                                                 /* See the comment in mono_codegen () */
2622                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
2623                                                         near_call = TRUE;
2624                                         }
2625                                 }
2626                                 else if ((((guint64)data) >> 32) == 0) {
2627                                         near_call = TRUE;
2628                                         no_patch = TRUE;
2629                                 }
2630                         }
2631                 }
2632
2633                 if (cfg->method->dynamic)
2634                         /* These methods are allocated using malloc */
2635                         near_call = FALSE;
2636
2637 #ifdef MONO_ARCH_NOMAP32BIT
2638                 near_call = FALSE;
2639 #endif
2640
2641                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
2642                 if (optimize_for_xen)
2643                         near_call = FALSE;
2644
2645                 if (cfg->compile_aot) {
2646                         near_call = TRUE;
2647                         no_patch = TRUE;
2648                 }
2649
2650                 if (near_call) {
2651                         /*
2652                          * Align the call displacement to an address divisible by 4 so it does
2653                          * not span cache lines. This is required for code patching to work on SMP
2654                          * systems.
2655                          */
2656                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0)
2657                                 amd64_padding (code, 4 - ((guint32)(code + 1 - cfg->native_code) % 4));
2658                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2659                         amd64_call_code (code, 0);
2660                 }
2661                 else {
2662                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
2663                         amd64_set_reg_template (code, GP_SCRATCH_REG);
2664                         amd64_call_reg (code, GP_SCRATCH_REG);
2665                 }
2666         }
2667
2668         return code;
2669 }
2670
2671 static inline guint8*
2672 emit_call (MonoCompile *cfg, guint8 *code, guint32 patch_type, gconstpointer data, gboolean win64_adjust_stack)
2673 {
2674 #ifdef HOST_WIN32
2675         if (win64_adjust_stack)
2676                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
2677 #endif
2678         code = emit_call_body (cfg, code, patch_type, data);
2679 #ifdef HOST_WIN32
2680         if (win64_adjust_stack)
2681                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
2682 #endif
2683
2684         return code;
2685 }
2686
2687 static inline int
2688 store_membase_imm_to_store_membase_reg (int opcode)
2689 {
2690         switch (opcode) {
2691         case OP_STORE_MEMBASE_IMM:
2692                 return OP_STORE_MEMBASE_REG;
2693         case OP_STOREI4_MEMBASE_IMM:
2694                 return OP_STOREI4_MEMBASE_REG;
2695         case OP_STOREI8_MEMBASE_IMM:
2696                 return OP_STOREI8_MEMBASE_REG;
2697         }
2698
2699         return -1;
2700 }
2701
2702 #ifndef DISABLE_JIT
2703
2704 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
2705
2706 /*
2707  * mono_arch_peephole_pass_1:
2708  *
2709  *   Perform peephole opts which should/can be performed before local regalloc
2710  */
2711 void
2712 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
2713 {
2714         MonoInst *ins, *n;
2715
2716         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2717                 MonoInst *last_ins = ins->prev;
2718
2719                 switch (ins->opcode) {
2720                 case OP_ADD_IMM:
2721                 case OP_IADD_IMM:
2722                 case OP_LADD_IMM:
2723                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
2724                                 /*
2725                                  * X86_LEA is like ADD, but doesn't have the
2726                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
2727                                  * its operand to 64 bit.
2728                                  */
2729                                 ins->opcode = OP_X86_LEA_MEMBASE;
2730                                 ins->inst_basereg = ins->sreg1;
2731                         }
2732                         break;
2733                 case OP_LXOR:
2734                 case OP_IXOR:
2735                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2736                                 MonoInst *ins2;
2737
2738                                 /*
2739                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2740                                  * the latter has length 2-3 instead of 6 (reverse constant
2741                                  * propagation). These instruction sequences are very common
2742                                  * in the initlocals bblock.
2743                                  */
2744                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2745                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2746                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2747                                                 ins2->sreg1 = ins->dreg;
2748                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
2749                                                 /* Continue */
2750                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2751                                                 NULLIFY_INS (ins2);
2752                                                 /* Continue */
2753                                         } else {
2754                                                 break;
2755                                         }
2756                                 }
2757                         }
2758                         break;
2759                 case OP_COMPARE_IMM:
2760                 case OP_LCOMPARE_IMM:
2761                         /* OP_COMPARE_IMM (reg, 0)
2762                          * -->
2763                          * OP_AMD64_TEST_NULL (reg)
2764                          */
2765                         if (!ins->inst_imm)
2766                                 ins->opcode = OP_AMD64_TEST_NULL;
2767                         break;
2768                 case OP_ICOMPARE_IMM:
2769                         if (!ins->inst_imm)
2770                                 ins->opcode = OP_X86_TEST_NULL;
2771                         break;
2772                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
2773                         /*
2774                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2775                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
2776                          * -->
2777                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
2778                          * OP_COMPARE_IMM reg, imm
2779                          *
2780                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
2781                          */
2782                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
2783                             ins->inst_basereg == last_ins->inst_destbasereg &&
2784                             ins->inst_offset == last_ins->inst_offset) {
2785                                         ins->opcode = OP_ICOMPARE_IMM;
2786                                         ins->sreg1 = last_ins->sreg1;
2787
2788                                         /* check if we can remove cmp reg,0 with test null */
2789                                         if (!ins->inst_imm)
2790                                                 ins->opcode = OP_X86_TEST_NULL;
2791                                 }
2792
2793                         break;
2794                 }
2795
2796                 mono_peephole_ins (bb, ins);
2797         }
2798 }
2799
2800 void
2801 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
2802 {
2803         MonoInst *ins, *n;
2804
2805         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2806                 switch (ins->opcode) {
2807                 case OP_ICONST:
2808                 case OP_I8CONST: {
2809                         /* reg = 0 -> XOR (reg, reg) */
2810                         /* XOR sets cflags on x86, so we cant do it always */
2811                         if (ins->inst_c0 == 0 && (!ins->next || (ins->next && INST_IGNORES_CFLAGS (ins->next->opcode)))) {
2812                                 ins->opcode = OP_LXOR;
2813                                 ins->sreg1 = ins->dreg;
2814                                 ins->sreg2 = ins->dreg;
2815                                 /* Fall through */
2816                         } else {
2817                                 break;
2818                         }
2819                 }
2820                 case OP_LXOR:
2821                         /*
2822                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
2823                          * 0 result into 64 bits.
2824                          */
2825                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2826                                 ins->opcode = OP_IXOR;
2827                         }
2828                         /* Fall through */
2829                 case OP_IXOR:
2830                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
2831                                 MonoInst *ins2;
2832
2833                                 /*
2834                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
2835                                  * the latter has length 2-3 instead of 6 (reverse constant
2836                                  * propagation). These instruction sequences are very common
2837                                  * in the initlocals bblock.
2838                                  */
2839                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
2840                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
2841                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
2842                                                 ins2->sreg1 = ins->dreg;
2843                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START)) {
2844                                                 /* Continue */
2845                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
2846                                                 NULLIFY_INS (ins2);
2847                                                 /* Continue */
2848                                         } else {
2849                                                 break;
2850                                         }
2851                                 }
2852                         }
2853                         break;
2854                 case OP_IADD_IMM:
2855                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2856                                 ins->opcode = OP_X86_INC_REG;
2857                         break;
2858                 case OP_ISUB_IMM:
2859                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
2860                                 ins->opcode = OP_X86_DEC_REG;
2861                         break;
2862                 }
2863
2864                 mono_peephole_ins (bb, ins);
2865         }
2866 }
2867
2868 #define NEW_INS(cfg,ins,dest,op) do {   \
2869                 MONO_INST_NEW ((cfg), (dest), (op)); \
2870         (dest)->cil_code = (ins)->cil_code; \
2871         mono_bblock_insert_before_ins (bb, ins, (dest)); \
2872         } while (0)
2873
2874 /*
2875  * mono_arch_lowering_pass:
2876  *
2877  *  Converts complex opcodes into simpler ones so that each IR instruction
2878  * corresponds to one machine instruction.
2879  */
2880 void
2881 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
2882 {
2883         MonoInst *ins, *n, *temp;
2884
2885         /*
2886          * FIXME: Need to add more instructions, but the current machine
2887          * description can't model some parts of the composite instructions like
2888          * cdq.
2889          */
2890         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
2891                 switch (ins->opcode) {
2892                 case OP_DIV_IMM:
2893                 case OP_REM_IMM:
2894                 case OP_IDIV_IMM:
2895                 case OP_IDIV_UN_IMM:
2896                 case OP_IREM_UN_IMM:
2897                         mono_decompose_op_imm (cfg, bb, ins);
2898                         break;
2899                 case OP_IREM_IMM:
2900                         /* Keep the opcode if we can implement it efficiently */
2901                         if (!((ins->inst_imm > 0) && (mono_is_power_of_two (ins->inst_imm) != -1)))
2902                                 mono_decompose_op_imm (cfg, bb, ins);
2903                         break;
2904                 case OP_COMPARE_IMM:
2905                 case OP_LCOMPARE_IMM:
2906                         if (!amd64_is_imm32 (ins->inst_imm)) {
2907                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2908                                 temp->inst_c0 = ins->inst_imm;
2909                                 temp->dreg = mono_alloc_ireg (cfg);
2910                                 ins->opcode = OP_COMPARE;
2911                                 ins->sreg2 = temp->dreg;
2912                         }
2913                         break;
2914                 case OP_LOAD_MEMBASE:
2915                 case OP_LOADI8_MEMBASE:
2916                         if (!amd64_is_imm32 (ins->inst_offset)) {
2917                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2918                                 temp->inst_c0 = ins->inst_offset;
2919                                 temp->dreg = mono_alloc_ireg (cfg);
2920                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
2921                                 ins->inst_indexreg = temp->dreg;
2922                         }
2923                         break;
2924                 case OP_STORE_MEMBASE_IMM:
2925                 case OP_STOREI8_MEMBASE_IMM:
2926                         if (!amd64_is_imm32 (ins->inst_imm)) {
2927                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
2928                                 temp->inst_c0 = ins->inst_imm;
2929                                 temp->dreg = mono_alloc_ireg (cfg);
2930                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
2931                                 ins->sreg1 = temp->dreg;
2932                         }
2933                         break;
2934 #ifdef MONO_ARCH_SIMD_INTRINSICS
2935                 case OP_EXPAND_I1: {
2936                                 int temp_reg1 = mono_alloc_ireg (cfg);
2937                                 int temp_reg2 = mono_alloc_ireg (cfg);
2938                                 int original_reg = ins->sreg1;
2939
2940                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
2941                                 temp->sreg1 = original_reg;
2942                                 temp->dreg = temp_reg1;
2943
2944                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
2945                                 temp->sreg1 = temp_reg1;
2946                                 temp->dreg = temp_reg2;
2947                                 temp->inst_imm = 8;
2948
2949                                 NEW_INS (cfg, ins, temp, OP_LOR);
2950                                 temp->sreg1 = temp->dreg = temp_reg2;
2951                                 temp->sreg2 = temp_reg1;
2952
2953                                 ins->opcode = OP_EXPAND_I2;
2954                                 ins->sreg1 = temp_reg2;
2955                         }
2956                         break;
2957 #endif
2958                 default:
2959                         break;
2960                 }
2961         }
2962
2963         bb->max_vreg = cfg->next_vreg;
2964 }
2965
2966 static const int
2967 branch_cc_table [] = {
2968         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2969         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
2970         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
2971 };
2972
2973 /* Maps CMP_... constants to X86_CC_... constants */
2974 static const int
2975 cc_table [] = {
2976         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
2977         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
2978 };
2979
2980 static const int
2981 cc_signed_table [] = {
2982         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
2983         FALSE, FALSE, FALSE, FALSE
2984 };
2985
2986 /*#include "cprop.c"*/
2987
2988 static unsigned char*
2989 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
2990 {
2991         amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
2992
2993         if (size == 1)
2994                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
2995         else if (size == 2)
2996                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
2997         return code;
2998 }
2999
3000 static unsigned char*
3001 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3002 {
3003         int sreg = tree->sreg1;
3004         int need_touch = FALSE;
3005
3006 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3007         if (!tree->flags & MONO_INST_INIT)
3008                 need_touch = TRUE;
3009 #endif
3010
3011         if (need_touch) {
3012                 guint8* br[5];
3013
3014                 /*
3015                  * Under Windows:
3016                  * If requested stack size is larger than one page,
3017                  * perform stack-touch operation
3018                  */
3019                 /*
3020                  * Generate stack probe code.
3021                  * Under Windows, it is necessary to allocate one page at a time,
3022                  * "touching" stack after each successful sub-allocation. This is
3023                  * because of the way stack growth is implemented - there is a
3024                  * guard page before the lowest stack page that is currently commited.
3025                  * Stack normally grows sequentially so OS traps access to the
3026                  * guard page and commits more pages when needed.
3027                  */
3028                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3029                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3030
3031                 br[2] = code; /* loop */
3032                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3033                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3034                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3035                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3036                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3037                 amd64_patch (br[3], br[2]);
3038                 amd64_test_reg_reg (code, sreg, sreg);
3039                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3040                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3041
3042                 br[1] = code; x86_jump8 (code, 0);
3043
3044                 amd64_patch (br[0], code);
3045                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3046                 amd64_patch (br[1], code);
3047                 amd64_patch (br[4], code);
3048         }
3049         else
3050                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3051
3052         if (tree->flags & MONO_INST_INIT) {
3053                 int offset = 0;
3054                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3055                         amd64_push_reg (code, AMD64_RAX);
3056                         offset += 8;
3057                 }
3058                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3059                         amd64_push_reg (code, AMD64_RCX);
3060                         offset += 8;
3061                 }
3062                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3063                         amd64_push_reg (code, AMD64_RDI);
3064                         offset += 8;
3065                 }
3066
3067                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3068                 if (sreg != AMD64_RCX)
3069                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3070                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3071
3072                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3073                 if (cfg->param_area && cfg->arch.no_pushes)
3074                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3075                 amd64_cld (code);
3076                 amd64_prefix (code, X86_REP_PREFIX);
3077                 amd64_stosl (code);
3078
3079                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3080                         amd64_pop_reg (code, AMD64_RDI);
3081                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3082                         amd64_pop_reg (code, AMD64_RCX);
3083                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3084                         amd64_pop_reg (code, AMD64_RAX);
3085         }
3086         return code;
3087 }
3088
3089 static guint8*
3090 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3091 {
3092         CallInfo *cinfo;
3093         guint32 quad;
3094
3095         /* Move return value to the target register */
3096         /* FIXME: do this in the local reg allocator */
3097         switch (ins->opcode) {
3098         case OP_CALL:
3099         case OP_CALL_REG:
3100         case OP_CALL_MEMBASE:
3101         case OP_LCALL:
3102         case OP_LCALL_REG:
3103         case OP_LCALL_MEMBASE:
3104                 g_assert (ins->dreg == AMD64_RAX);
3105                 break;
3106         case OP_FCALL:
3107         case OP_FCALL_REG:
3108         case OP_FCALL_MEMBASE:
3109                 if (((MonoCallInst*)ins)->signature->ret->type == MONO_TYPE_R4) {
3110                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3111                 }
3112                 else {
3113                         if (ins->dreg != AMD64_XMM0)
3114                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3115                 }
3116                 break;
3117         case OP_VCALL:
3118         case OP_VCALL_REG:
3119         case OP_VCALL_MEMBASE:
3120         case OP_VCALL2:
3121         case OP_VCALL2_REG:
3122         case OP_VCALL2_MEMBASE:
3123                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, ((MonoCallInst*)ins)->signature, FALSE);
3124                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3125                         MonoInst *loc = cfg->arch.vret_addr_loc;
3126
3127                         /* Load the destination address */
3128                         g_assert (loc->opcode == OP_REGOFFSET);
3129                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, 8);
3130
3131                         for (quad = 0; quad < 2; quad ++) {
3132                                 switch (cinfo->ret.pair_storage [quad]) {
3133                                 case ArgInIReg:
3134                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad], 8);
3135                                         break;
3136                                 case ArgInFloatSSEReg:
3137                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3138                                         break;
3139                                 case ArgInDoubleSSEReg:
3140                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3141                                         break;
3142                                 case ArgNone:
3143                                         break;
3144                                 default:
3145                                         NOT_IMPLEMENTED;
3146                                 }
3147                         }
3148                 }
3149                 break;
3150         }
3151
3152         return code;
3153 }
3154
3155 #endif /* DISABLE_JIT */
3156
3157 /*
3158  * mono_amd64_emit_tls_get:
3159  * @code: buffer to store code to
3160  * @dreg: hard register where to place the result
3161  * @tls_offset: offset info
3162  *
3163  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3164  * the dreg register the item in the thread local storage identified
3165  * by tls_offset.
3166  *
3167  * Returns: a pointer to the end of the stored code
3168  */
3169 guint8*
3170 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3171 {
3172 #ifdef HOST_WIN32
3173         g_assert (tls_offset < 64);
3174         x86_prefix (code, X86_GS_PREFIX);
3175         amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3176 #else
3177         if (optimize_for_xen) {
3178                 x86_prefix (code, X86_FS_PREFIX);
3179                 amd64_mov_reg_mem (code, dreg, 0, 8);
3180                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3181         } else {
3182                 x86_prefix (code, X86_FS_PREFIX);
3183                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3184         }
3185 #endif
3186         return code;
3187 }
3188
3189 #define REAL_PRINT_REG(text,reg) \
3190 mono_assert (reg >= 0); \
3191 amd64_push_reg (code, AMD64_RAX); \
3192 amd64_push_reg (code, AMD64_RDX); \
3193 amd64_push_reg (code, AMD64_RCX); \
3194 amd64_push_reg (code, reg); \
3195 amd64_push_imm (code, reg); \
3196 amd64_push_imm (code, text " %d %p\n"); \
3197 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3198 amd64_call_reg (code, AMD64_RAX); \
3199 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3200 amd64_pop_reg (code, AMD64_RCX); \
3201 amd64_pop_reg (code, AMD64_RDX); \
3202 amd64_pop_reg (code, AMD64_RAX);
3203
3204 /* benchmark and set based on cpu */
3205 #define LOOP_ALIGNMENT 8
3206 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3207
3208 #ifndef DISABLE_JIT
3209
3210 void
3211 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3212 {
3213         MonoInst *ins;
3214         MonoCallInst *call;
3215         guint offset;
3216         guint8 *code = cfg->native_code + cfg->code_len;
3217         MonoInst *last_ins = NULL;
3218         guint last_offset = 0;
3219         int max_len;
3220
3221         /* Fix max_offset estimate for each successor bb */
3222         if (cfg->opt & MONO_OPT_BRANCH) {
3223                 int current_offset = cfg->code_len;
3224                 MonoBasicBlock *current_bb;
3225                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3226                         current_bb->max_offset = current_offset;
3227                         current_offset += current_bb->max_length;
3228                 }
3229         }
3230
3231         if (cfg->opt & MONO_OPT_LOOP) {
3232                 int pad, align = LOOP_ALIGNMENT;
3233                 /* set alignment depending on cpu */
3234                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3235                         pad = align - pad;
3236                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3237                         amd64_padding (code, pad);
3238                         cfg->code_len += pad;
3239                         bb->native_offset = cfg->code_len;
3240                 }
3241         }
3242
3243         if (cfg->verbose_level > 2)
3244                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
3245
3246         if (cfg->prof_options & MONO_PROFILE_COVERAGE) {
3247                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
3248                 g_assert (!cfg->compile_aot);
3249
3250                 cov->data [bb->dfn].cil_code = bb->cil_code;
3251                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
3252                 /* this is not thread save, but good enough */
3253                 amd64_inc_membase (code, AMD64_R11, 0);
3254         }
3255
3256         offset = code - cfg->native_code;
3257
3258         mono_debug_open_block (cfg, bb, offset);
3259
3260     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
3261                 x86_breakpoint (code);
3262
3263         MONO_BB_FOR_EACH_INS (bb, ins) {
3264                 offset = code - cfg->native_code;
3265
3266                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
3267
3268                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - 16))) {
3269                         cfg->code_size *= 2;
3270                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
3271                         code = cfg->native_code + offset;
3272                         mono_jit_stats.code_reallocs++;
3273                 }
3274
3275                 if (cfg->debug_info)
3276                         mono_debug_record_line_number (cfg, ins, offset);
3277
3278                 switch (ins->opcode) {
3279                 case OP_BIGMUL:
3280                         amd64_mul_reg (code, ins->sreg2, TRUE);
3281                         break;
3282                 case OP_BIGMUL_UN:
3283                         amd64_mul_reg (code, ins->sreg2, FALSE);
3284                         break;
3285                 case OP_X86_SETEQ_MEMBASE:
3286                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
3287                         break;
3288                 case OP_STOREI1_MEMBASE_IMM:
3289                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
3290                         break;
3291                 case OP_STOREI2_MEMBASE_IMM:
3292                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
3293                         break;
3294                 case OP_STOREI4_MEMBASE_IMM:
3295                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
3296                         break;
3297                 case OP_STOREI1_MEMBASE_REG:
3298                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
3299                         break;
3300                 case OP_STOREI2_MEMBASE_REG:
3301                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
3302                         break;
3303                 case OP_STORE_MEMBASE_REG:
3304                 case OP_STOREI8_MEMBASE_REG:
3305                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
3306                         break;
3307                 case OP_STOREI4_MEMBASE_REG:
3308                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
3309                         break;
3310                 case OP_STORE_MEMBASE_IMM:
3311                 case OP_STOREI8_MEMBASE_IMM:
3312                         g_assert (amd64_is_imm32 (ins->inst_imm));
3313                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
3314                         break;
3315                 case OP_LOAD_MEM:
3316                 case OP_LOADI8_MEM:
3317                         // FIXME: Decompose this earlier
3318                         if (amd64_is_imm32 (ins->inst_imm))
3319                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, sizeof (gpointer));
3320                         else {
3321                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3322                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
3323                         }
3324                         break;
3325                 case OP_LOADI4_MEM:
3326                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3327                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
3328                         break;
3329                 case OP_LOADU4_MEM:
3330                         // FIXME: Decompose this earlier
3331                         if (amd64_is_imm32 (ins->inst_imm))
3332                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
3333                         else {
3334                                 amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3335                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
3336                         }
3337                         break;
3338                 case OP_LOADU1_MEM:
3339                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3340                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
3341                         break;
3342                 case OP_LOADU2_MEM:
3343                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
3344                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
3345                         break;
3346                 case OP_LOAD_MEMBASE:
3347                 case OP_LOADI8_MEMBASE:
3348                         g_assert (amd64_is_imm32 (ins->inst_offset));
3349                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof (gpointer));
3350                         break;
3351                 case OP_LOADI4_MEMBASE:
3352                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
3353                         break;
3354                 case OP_LOADU4_MEMBASE:
3355                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
3356                         break;
3357                 case OP_LOADU1_MEMBASE:
3358                         /* The cpu zero extends the result into 64 bits */
3359                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
3360                         break;
3361                 case OP_LOADI1_MEMBASE:
3362                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
3363                         break;
3364                 case OP_LOADU2_MEMBASE:
3365                         /* The cpu zero extends the result into 64 bits */
3366                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
3367                         break;
3368                 case OP_LOADI2_MEMBASE:
3369                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
3370                         break;
3371                 case OP_AMD64_LOADI8_MEMINDEX:
3372                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
3373                         break;
3374                 case OP_LCONV_TO_I1:
3375                 case OP_ICONV_TO_I1:
3376                 case OP_SEXT_I1:
3377                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
3378                         break;
3379                 case OP_LCONV_TO_I2:
3380                 case OP_ICONV_TO_I2:
3381                 case OP_SEXT_I2:
3382                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
3383                         break;
3384                 case OP_LCONV_TO_U1:
3385                 case OP_ICONV_TO_U1:
3386                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
3387                         break;
3388                 case OP_LCONV_TO_U2:
3389                 case OP_ICONV_TO_U2:
3390                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
3391                         break;
3392                 case OP_ZEXT_I4:
3393                         /* Clean out the upper word */
3394                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
3395                         break;
3396                 case OP_SEXT_I4:
3397                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
3398                         break;
3399                 case OP_COMPARE:
3400                 case OP_LCOMPARE:
3401                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
3402                         break;
3403                 case OP_COMPARE_IMM:
3404                 case OP_LCOMPARE_IMM:
3405                         g_assert (amd64_is_imm32 (ins->inst_imm));
3406                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
3407                         break;
3408                 case OP_X86_COMPARE_REG_MEMBASE:
3409                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
3410                         break;
3411                 case OP_X86_TEST_NULL:
3412                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
3413                         break;
3414                 case OP_AMD64_TEST_NULL:
3415                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
3416                         break;
3417
3418                 case OP_X86_ADD_REG_MEMBASE:
3419                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3420                         break;
3421                 case OP_X86_SUB_REG_MEMBASE:
3422                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3423                         break;
3424                 case OP_X86_AND_REG_MEMBASE:
3425                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3426                         break;
3427                 case OP_X86_OR_REG_MEMBASE:
3428                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3429                         break;
3430                 case OP_X86_XOR_REG_MEMBASE:
3431                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3432                         break;
3433
3434                 case OP_X86_ADD_MEMBASE_IMM:
3435                         /* FIXME: Make a 64 version too */
3436                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3437                         break;
3438                 case OP_X86_SUB_MEMBASE_IMM:
3439                         g_assert (amd64_is_imm32 (ins->inst_imm));
3440                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3441                         break;
3442                 case OP_X86_AND_MEMBASE_IMM:
3443                         g_assert (amd64_is_imm32 (ins->inst_imm));
3444                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3445                         break;
3446                 case OP_X86_OR_MEMBASE_IMM:
3447                         g_assert (amd64_is_imm32 (ins->inst_imm));
3448                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3449                         break;
3450                 case OP_X86_XOR_MEMBASE_IMM:
3451                         g_assert (amd64_is_imm32 (ins->inst_imm));
3452                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3453                         break;
3454                 case OP_X86_ADD_MEMBASE_REG:
3455                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3456                         break;
3457                 case OP_X86_SUB_MEMBASE_REG:
3458                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3459                         break;
3460                 case OP_X86_AND_MEMBASE_REG:
3461                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3462                         break;
3463                 case OP_X86_OR_MEMBASE_REG:
3464                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3465                         break;
3466                 case OP_X86_XOR_MEMBASE_REG:
3467                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3468                         break;
3469                 case OP_X86_INC_MEMBASE:
3470                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3471                         break;
3472                 case OP_X86_INC_REG:
3473                         amd64_inc_reg_size (code, ins->dreg, 4);
3474                         break;
3475                 case OP_X86_DEC_MEMBASE:
3476                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
3477                         break;
3478                 case OP_X86_DEC_REG:
3479                         amd64_dec_reg_size (code, ins->dreg, 4);
3480                         break;
3481                 case OP_X86_MUL_REG_MEMBASE:
3482                 case OP_X86_MUL_MEMBASE_REG:
3483                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3484                         break;
3485                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
3486                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
3487                         break;
3488                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3489                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3490                         break;
3491                 case OP_AMD64_COMPARE_MEMBASE_REG:
3492                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3493                         break;
3494                 case OP_AMD64_COMPARE_MEMBASE_IMM:
3495                         g_assert (amd64_is_imm32 (ins->inst_imm));
3496                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3497                         break;
3498                 case OP_X86_COMPARE_MEMBASE8_IMM:
3499                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
3500                         break;
3501                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
3502                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
3503                         break;
3504                 case OP_AMD64_COMPARE_REG_MEMBASE:
3505                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3506                         break;
3507
3508                 case OP_AMD64_ADD_REG_MEMBASE:
3509                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3510                         break;
3511                 case OP_AMD64_SUB_REG_MEMBASE:
3512                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3513                         break;
3514                 case OP_AMD64_AND_REG_MEMBASE:
3515                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3516                         break;
3517                 case OP_AMD64_OR_REG_MEMBASE:
3518                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3519                         break;
3520                 case OP_AMD64_XOR_REG_MEMBASE:
3521                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
3522                         break;
3523
3524                 case OP_AMD64_ADD_MEMBASE_REG:
3525                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3526                         break;
3527                 case OP_AMD64_SUB_MEMBASE_REG:
3528                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3529                         break;
3530                 case OP_AMD64_AND_MEMBASE_REG:
3531                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3532                         break;
3533                 case OP_AMD64_OR_MEMBASE_REG:
3534                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3535                         break;
3536                 case OP_AMD64_XOR_MEMBASE_REG:
3537                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
3538                         break;
3539
3540                 case OP_AMD64_ADD_MEMBASE_IMM:
3541                         g_assert (amd64_is_imm32 (ins->inst_imm));
3542                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3543                         break;
3544                 case OP_AMD64_SUB_MEMBASE_IMM:
3545                         g_assert (amd64_is_imm32 (ins->inst_imm));
3546                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3547                         break;
3548                 case OP_AMD64_AND_MEMBASE_IMM:
3549                         g_assert (amd64_is_imm32 (ins->inst_imm));
3550                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3551                         break;
3552                 case OP_AMD64_OR_MEMBASE_IMM:
3553                         g_assert (amd64_is_imm32 (ins->inst_imm));
3554                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3555                         break;
3556                 case OP_AMD64_XOR_MEMBASE_IMM:
3557                         g_assert (amd64_is_imm32 (ins->inst_imm));
3558                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
3559                         break;
3560
3561                 case OP_BREAK:
3562                         amd64_breakpoint (code);
3563                         break;
3564                 case OP_RELAXED_NOP:
3565                         x86_prefix (code, X86_REP_PREFIX);
3566                         x86_nop (code);
3567                         break;
3568                 case OP_HARD_NOP:
3569                         x86_nop (code);
3570                         break;
3571                 case OP_NOP:
3572                 case OP_DUMMY_USE:
3573                 case OP_DUMMY_STORE:
3574                 case OP_NOT_REACHED:
3575                 case OP_NOT_NULL:
3576                         break;
3577                 case OP_SEQ_POINT: {
3578                         int i;
3579
3580                         if (cfg->compile_aot)
3581                                 NOT_IMPLEMENTED;
3582
3583                         /*
3584                          * Read from the single stepping trigger page. This will cause a
3585                          * SIGSEGV when single stepping is enabled.
3586                          * We do this _before_ the breakpoint, so single stepping after
3587                          * a breakpoint is hit will step to the next IL offset.
3588                          */
3589                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
3590                                 if (((guint64)ss_trigger_page >> 32) == 0)
3591                                         amd64_mov_reg_mem (code, AMD64_R11, (guint64)ss_trigger_page, 4);
3592                                 else {
3593                                         MonoInst *var = cfg->arch.ss_trigger_page_var;
3594
3595                                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
3596                                         amd64_alu_membase_imm_size (code, X86_CMP, AMD64_R11, 0, 0, 4);
3597                                 }
3598                         }
3599
3600                         /*
3601                          * This is the address which is saved in seq points,
3602                          * get_ip_for_single_step () / get_ip_for_breakpoint () needs to compute this
3603                          * from the address of the instruction causing the fault.
3604                          */
3605                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
3606
3607                         /*
3608                          * A placeholder for a possible breakpoint inserted by
3609                          * mono_arch_set_breakpoint ().
3610                          */
3611                         for (i = 0; i < breakpoint_size; ++i)
3612                                 x86_nop (code);
3613                         break;
3614                 }
3615                 case OP_ADDCC:
3616                 case OP_LADD:
3617                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
3618                         break;
3619                 case OP_ADC:
3620                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
3621                         break;
3622                 case OP_ADD_IMM:
3623                 case OP_LADD_IMM:
3624                         g_assert (amd64_is_imm32 (ins->inst_imm));
3625                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
3626                         break;
3627                 case OP_ADC_IMM:
3628                         g_assert (amd64_is_imm32 (ins->inst_imm));
3629                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
3630                         break;
3631                 case OP_SUBCC:
3632                 case OP_LSUB:
3633                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
3634                         break;
3635                 case OP_SBB:
3636                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
3637                         break;
3638                 case OP_SUB_IMM:
3639                 case OP_LSUB_IMM:
3640                         g_assert (amd64_is_imm32 (ins->inst_imm));
3641                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
3642                         break;
3643                 case OP_SBB_IMM:
3644                         g_assert (amd64_is_imm32 (ins->inst_imm));
3645                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
3646                         break;
3647                 case OP_LAND:
3648                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
3649                         break;
3650                 case OP_AND_IMM:
3651                 case OP_LAND_IMM:
3652                         g_assert (amd64_is_imm32 (ins->inst_imm));
3653                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
3654                         break;
3655                 case OP_LMUL:
3656                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3657                         break;
3658                 case OP_MUL_IMM:
3659                 case OP_LMUL_IMM:
3660                 case OP_IMUL_IMM: {
3661                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
3662
3663                         switch (ins->inst_imm) {
3664                         case 2:
3665                                 /* MOV r1, r2 */
3666                                 /* ADD r1, r1 */
3667                                 if (ins->dreg != ins->sreg1)
3668                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
3669                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3670                                 break;
3671                         case 3:
3672                                 /* LEA r1, [r2 + r2*2] */
3673                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3674                                 break;
3675                         case 5:
3676                                 /* LEA r1, [r2 + r2*4] */
3677                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3678                                 break;
3679                         case 6:
3680                                 /* LEA r1, [r2 + r2*2] */
3681                                 /* ADD r1, r1          */
3682                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3683                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3684                                 break;
3685                         case 9:
3686                                 /* LEA r1, [r2 + r2*8] */
3687                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
3688                                 break;
3689                         case 10:
3690                                 /* LEA r1, [r2 + r2*4] */
3691                                 /* ADD r1, r1          */
3692                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3693                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
3694                                 break;
3695                         case 12:
3696                                 /* LEA r1, [r2 + r2*2] */
3697                                 /* SHL r1, 2           */
3698                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
3699                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3700                                 break;
3701                         case 25:
3702                                 /* LEA r1, [r2 + r2*4] */
3703                                 /* LEA r1, [r1 + r1*4] */
3704                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3705                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3706                                 break;
3707                         case 100:
3708                                 /* LEA r1, [r2 + r2*4] */
3709                                 /* SHL r1, 2           */
3710                                 /* LEA r1, [r1 + r1*4] */
3711                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
3712                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
3713                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
3714                                 break;
3715                         default:
3716                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
3717                                 break;
3718                         }
3719                         break;
3720                 }
3721                 case OP_LDIV:
3722                 case OP_LREM:
3723                         /* Regalloc magic makes the div/rem cases the same */
3724                         if (ins->sreg2 == AMD64_RDX) {
3725                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3726                                 amd64_cdq (code);
3727                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
3728                         } else {
3729                                 amd64_cdq (code);
3730                                 amd64_div_reg (code, ins->sreg2, TRUE);
3731                         }
3732                         break;
3733                 case OP_LDIV_UN:
3734                 case OP_LREM_UN:
3735                         if (ins->sreg2 == AMD64_RDX) {
3736                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3737                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3738                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
3739                         } else {
3740                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3741                                 amd64_div_reg (code, ins->sreg2, FALSE);
3742                         }
3743                         break;
3744                 case OP_IDIV:
3745                 case OP_IREM:
3746                         if (ins->sreg2 == AMD64_RDX) {
3747                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3748                                 amd64_cdq_size (code, 4);
3749                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
3750                         } else {
3751                                 amd64_cdq_size (code, 4);
3752                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
3753                         }
3754                         break;
3755                 case OP_IDIV_UN:
3756                 case OP_IREM_UN:
3757                         if (ins->sreg2 == AMD64_RDX) {
3758                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
3759                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3760                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
3761                         } else {
3762                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
3763                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
3764                         }
3765                         break;
3766                 case OP_IREM_IMM: {
3767                         int power = mono_is_power_of_two (ins->inst_imm);
3768
3769                         g_assert (ins->sreg1 == X86_EAX);
3770                         g_assert (ins->dreg == X86_EAX);
3771                         g_assert (power >= 0);
3772
3773                         if (power == 0) {
3774                                 amd64_mov_reg_imm (code, ins->dreg, 0);
3775                                 break;
3776                         }
3777
3778                         /* Based on gcc code */
3779
3780                         /* Add compensation for negative dividents */
3781                         amd64_mov_reg_reg_size (code, AMD64_RDX, AMD64_RAX, 4);
3782                         if (power > 1)
3783                                 amd64_shift_reg_imm_size (code, X86_SAR, AMD64_RDX, 31, 4);
3784                         amd64_shift_reg_imm_size (code, X86_SHR, AMD64_RDX, 32 - power, 4);
3785                         amd64_alu_reg_reg_size (code, X86_ADD, AMD64_RAX, AMD64_RDX, 4);
3786                         /* Compute remainder */
3787                         amd64_alu_reg_imm_size (code, X86_AND, AMD64_RAX, (1 << power) - 1, 4);
3788                         /* Remove compensation */
3789                         amd64_alu_reg_reg_size (code, X86_SUB, AMD64_RAX, AMD64_RDX, 4);
3790                         break;
3791                 }
3792                 case OP_LMUL_OVF:
3793                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
3794                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3795                         break;
3796                 case OP_LOR:
3797                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
3798                         break;
3799                 case OP_OR_IMM:
3800                 case OP_LOR_IMM:
3801                         g_assert (amd64_is_imm32 (ins->inst_imm));
3802                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
3803                         break;
3804                 case OP_LXOR:
3805                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
3806                         break;
3807                 case OP_XOR_IMM:
3808                 case OP_LXOR_IMM:
3809                         g_assert (amd64_is_imm32 (ins->inst_imm));
3810                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
3811                         break;
3812                 case OP_LSHL:
3813                         g_assert (ins->sreg2 == AMD64_RCX);
3814                         amd64_shift_reg (code, X86_SHL, ins->dreg);
3815                         break;
3816                 case OP_LSHR:
3817                         g_assert (ins->sreg2 == AMD64_RCX);
3818                         amd64_shift_reg (code, X86_SAR, ins->dreg);
3819                         break;
3820                 case OP_SHR_IMM:
3821                         g_assert (amd64_is_imm32 (ins->inst_imm));
3822                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3823                         break;
3824                 case OP_LSHR_IMM:
3825                         g_assert (amd64_is_imm32 (ins->inst_imm));
3826                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
3827                         break;
3828                 case OP_SHR_UN_IMM:
3829                         g_assert (amd64_is_imm32 (ins->inst_imm));
3830                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3831                         break;
3832                 case OP_LSHR_UN_IMM:
3833                         g_assert (amd64_is_imm32 (ins->inst_imm));
3834                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
3835                         break;
3836                 case OP_LSHR_UN:
3837                         g_assert (ins->sreg2 == AMD64_RCX);
3838                         amd64_shift_reg (code, X86_SHR, ins->dreg);
3839                         break;
3840                 case OP_SHL_IMM:
3841                         g_assert (amd64_is_imm32 (ins->inst_imm));
3842                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3843                         break;
3844                 case OP_LSHL_IMM:
3845                         g_assert (amd64_is_imm32 (ins->inst_imm));
3846                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
3847                         break;
3848
3849                 case OP_IADDCC:
3850                 case OP_IADD:
3851                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
3852                         break;
3853                 case OP_IADC:
3854                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
3855                         break;
3856                 case OP_IADD_IMM:
3857                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
3858                         break;
3859                 case OP_IADC_IMM:
3860                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
3861                         break;
3862                 case OP_ISUBCC:
3863                 case OP_ISUB:
3864                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
3865                         break;
3866                 case OP_ISBB:
3867                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
3868                         break;
3869                 case OP_ISUB_IMM:
3870                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
3871                         break;
3872                 case OP_ISBB_IMM:
3873                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
3874                         break;
3875                 case OP_IAND:
3876                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
3877                         break;
3878                 case OP_IAND_IMM:
3879                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
3880                         break;
3881                 case OP_IOR:
3882                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
3883                         break;
3884                 case OP_IOR_IMM:
3885                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
3886                         break;
3887                 case OP_IXOR:
3888                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
3889                         break;
3890                 case OP_IXOR_IMM:
3891                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
3892                         break;
3893                 case OP_INEG:
3894                         amd64_neg_reg_size (code, ins->sreg1, 4);
3895                         break;
3896                 case OP_INOT:
3897                         amd64_not_reg_size (code, ins->sreg1, 4);
3898                         break;
3899                 case OP_ISHL:
3900                         g_assert (ins->sreg2 == AMD64_RCX);
3901                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
3902                         break;
3903                 case OP_ISHR:
3904                         g_assert (ins->sreg2 == AMD64_RCX);
3905                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
3906                         break;
3907                 case OP_ISHR_IMM:
3908                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
3909                         break;
3910                 case OP_ISHR_UN_IMM:
3911                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
3912                         break;
3913                 case OP_ISHR_UN:
3914                         g_assert (ins->sreg2 == AMD64_RCX);
3915                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
3916                         break;
3917                 case OP_ISHL_IMM:
3918                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
3919                         break;
3920                 case OP_IMUL:
3921                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3922                         break;
3923                 case OP_IMUL_OVF:
3924                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
3925                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3926                         break;
3927                 case OP_IMUL_OVF_UN:
3928                 case OP_LMUL_OVF_UN: {
3929                         /* the mul operation and the exception check should most likely be split */
3930                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
3931                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
3932                         /*g_assert (ins->sreg2 == X86_EAX);
3933                         g_assert (ins->dreg == X86_EAX);*/
3934                         if (ins->sreg2 == X86_EAX) {
3935                                 non_eax_reg = ins->sreg1;
3936                         } else if (ins->sreg1 == X86_EAX) {
3937                                 non_eax_reg = ins->sreg2;
3938                         } else {
3939                                 /* no need to save since we're going to store to it anyway */
3940                                 if (ins->dreg != X86_EAX) {
3941                                         saved_eax = TRUE;
3942                                         amd64_push_reg (code, X86_EAX);
3943                                 }
3944                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
3945                                 non_eax_reg = ins->sreg2;
3946                         }
3947                         if (ins->dreg == X86_EDX) {
3948                                 if (!saved_eax) {
3949                                         saved_eax = TRUE;
3950                                         amd64_push_reg (code, X86_EAX);
3951                                 }
3952                         } else {
3953                                 saved_edx = TRUE;
3954                                 amd64_push_reg (code, X86_EDX);
3955                         }
3956                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
3957                         /* save before the check since pop and mov don't change the flags */
3958                         if (ins->dreg != X86_EAX)
3959                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
3960                         if (saved_edx)
3961                                 amd64_pop_reg (code, X86_EDX);
3962                         if (saved_eax)
3963                                 amd64_pop_reg (code, X86_EAX);
3964                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
3965                         break;
3966                 }
3967                 case OP_ICOMPARE:
3968                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
3969                         break;
3970                 case OP_ICOMPARE_IMM:
3971                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
3972                         break;
3973                 case OP_IBEQ:
3974                 case OP_IBLT:
3975                 case OP_IBGT:
3976                 case OP_IBGE:
3977                 case OP_IBLE:
3978                 case OP_LBEQ:
3979                 case OP_LBLT:
3980                 case OP_LBGT:
3981                 case OP_LBGE:
3982                 case OP_LBLE:
3983                 case OP_IBNE_UN:
3984                 case OP_IBLT_UN:
3985                 case OP_IBGT_UN:
3986                 case OP_IBGE_UN:
3987                 case OP_IBLE_UN:
3988                 case OP_LBNE_UN:
3989                 case OP_LBLT_UN:
3990                 case OP_LBGT_UN:
3991                 case OP_LBGE_UN:
3992                 case OP_LBLE_UN:
3993                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
3994                         break;
3995
3996                 case OP_CMOV_IEQ:
3997                 case OP_CMOV_IGE:
3998                 case OP_CMOV_IGT:
3999                 case OP_CMOV_ILE:
4000                 case OP_CMOV_ILT:
4001                 case OP_CMOV_INE_UN:
4002                 case OP_CMOV_IGE_UN:
4003                 case OP_CMOV_IGT_UN:
4004                 case OP_CMOV_ILE_UN:
4005                 case OP_CMOV_ILT_UN:
4006                 case OP_CMOV_LEQ:
4007                 case OP_CMOV_LGE:
4008                 case OP_CMOV_LGT:
4009                 case OP_CMOV_LLE:
4010                 case OP_CMOV_LLT:
4011                 case OP_CMOV_LNE_UN:
4012                 case OP_CMOV_LGE_UN:
4013                 case OP_CMOV_LGT_UN:
4014                 case OP_CMOV_LLE_UN:
4015                 case OP_CMOV_LLT_UN:
4016                         g_assert (ins->dreg == ins->sreg1);
4017                         /* This needs to operate on 64 bit values */
4018                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4019                         break;
4020
4021                 case OP_LNOT:
4022                         amd64_not_reg (code, ins->sreg1);
4023                         break;
4024                 case OP_LNEG:
4025                         amd64_neg_reg (code, ins->sreg1);
4026                         break;
4027
4028                 case OP_ICONST:
4029                 case OP_I8CONST:
4030                         if ((((guint64)ins->inst_c0) >> 32) == 0)
4031                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4032                         else
4033                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4034                         break;
4035                 case OP_AOTCONST:
4036                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4037                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, 8);
4038                         break;
4039                 case OP_JUMP_TABLE:
4040                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4041                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4042                         break;
4043                 case OP_MOVE:
4044                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof (gpointer));
4045                         break;
4046                 case OP_AMD64_SET_XMMREG_R4: {
4047                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4048                         break;
4049                 }
4050                 case OP_AMD64_SET_XMMREG_R8: {
4051                         if (ins->dreg != ins->sreg1)
4052                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4053                         break;
4054                 }
4055                 case OP_TAILCALL: {
4056                         /*
4057                          * Note: this 'frame destruction' logic is useful for tail calls, too.
4058                          * Keep in sync with the code in emit_epilog.
4059                          */
4060                         int pos = 0, i;
4061
4062                         /* FIXME: no tracing support... */
4063                         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
4064                                 code = mono_arch_instrument_epilog_full (cfg, mono_profiler_method_leave, code, FALSE, FALSE);
4065
4066                         g_assert (!cfg->method->save_lmf);
4067
4068                         if (cfg->arch.omit_fp) {
4069                                 guint32 save_offset = 0;
4070                                 /* Pop callee-saved registers */
4071                                 for (i = 0; i < AMD64_NREG; ++i)
4072                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4073                                                 amd64_mov_reg_membase (code, i, AMD64_RSP, save_offset, 8);
4074                                                 save_offset += 8;
4075                                         }
4076                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4077                         }
4078                         else {
4079                                 for (i = 0; i < AMD64_NREG; ++i)
4080                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
4081                                                 pos -= sizeof (gpointer);
4082
4083                                 if (pos)
4084                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
4085
4086                                 /* Pop registers in reverse order */
4087                                 for (i = AMD64_NREG - 1; i > 0; --i)
4088                                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4089                                                 amd64_pop_reg (code, i);
4090                                         }
4091
4092                                 amd64_leave (code);
4093                         }
4094
4095                         offset = code - cfg->native_code;
4096                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, ins->inst_p0);
4097                         if (cfg->compile_aot)
4098                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4099                         else
4100                                 amd64_set_reg_template (code, AMD64_R11);
4101                         amd64_jump_reg (code, AMD64_R11);
4102                         break;
4103                 }
4104                 case OP_CHECK_THIS:
4105                         /* ensure ins->sreg1 is not NULL */
4106                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4107                         break;
4108                 case OP_ARGLIST: {
4109                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4110                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, 8);
4111                         break;
4112                 }
4113                 case OP_CALL:
4114                 case OP_FCALL:
4115                 case OP_LCALL:
4116                 case OP_VCALL:
4117                 case OP_VCALL2:
4118                 case OP_VOIDCALL:
4119                         call = (MonoCallInst*)ins;
4120                         /*
4121                          * The AMD64 ABI forces callers to know about varargs.
4122                          */
4123                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4124                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4125                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4126                                 /*
4127                                  * Since the unmanaged calling convention doesn't contain a
4128                                  * 'vararg' entry, we have to treat every pinvoke call as a
4129                                  * potential vararg call.
4130                                  */
4131                                 guint32 nregs, i;
4132                                 nregs = 0;
4133                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4134                                         if (call->used_fregs & (1 << i))
4135                                                 nregs ++;
4136                                 if (!nregs)
4137                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4138                                 else
4139                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4140                         }
4141
4142                         if (ins->flags & MONO_INST_HAS_METHOD)
4143                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4144                         else
4145                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4146                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4147                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4148                         code = emit_move_return_value (cfg, ins, code);
4149                         break;
4150                 case OP_FCALL_REG:
4151                 case OP_LCALL_REG:
4152                 case OP_VCALL_REG:
4153                 case OP_VCALL2_REG:
4154                 case OP_VOIDCALL_REG:
4155                 case OP_CALL_REG:
4156                         call = (MonoCallInst*)ins;
4157
4158                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4159                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4160                                 ins->sreg1 = AMD64_R11;
4161                         }
4162
4163                         /*
4164                          * The AMD64 ABI forces callers to know about varargs.
4165                          */
4166                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4167                                 if (ins->sreg1 == AMD64_RAX) {
4168                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4169                                         ins->sreg1 = AMD64_R11;
4170                                 }
4171                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4172                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4173                                 /*
4174                                  * Since the unmanaged calling convention doesn't contain a
4175                                  * 'vararg' entry, we have to treat every pinvoke call as a
4176                                  * potential vararg call.
4177                                  */
4178                                 guint32 nregs, i;
4179                                 nregs = 0;
4180                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4181                                         if (call->used_fregs & (1 << i))
4182                                                 nregs ++;
4183                                 if (ins->sreg1 == AMD64_RAX) {
4184                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4185                                         ins->sreg1 = AMD64_R11;
4186                                 }
4187                                 if (!nregs)
4188                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4189                                 else
4190                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4191                         }
4192
4193                         amd64_call_reg (code, ins->sreg1);
4194                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4195                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4196                         code = emit_move_return_value (cfg, ins, code);
4197                         break;
4198                 case OP_FCALL_MEMBASE:
4199                 case OP_LCALL_MEMBASE:
4200                 case OP_VCALL_MEMBASE:
4201                 case OP_VCALL2_MEMBASE:
4202                 case OP_VOIDCALL_MEMBASE:
4203                 case OP_CALL_MEMBASE:
4204                         call = (MonoCallInst*)ins;
4205
4206                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
4207                         if (call->stack_usage && !CALLCONV_IS_STDCALL (call->signature->call_convention) && !cfg->arch.no_pushes)
4208                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, call->stack_usage);
4209                         code = emit_move_return_value (cfg, ins, code);
4210                         break;
4211                 case OP_DYN_CALL: {
4212                         int i;
4213                         MonoInst *var = cfg->dyn_call_var;
4214
4215                         g_assert (var->opcode == OP_REGOFFSET);
4216
4217                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
4218                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4219                         /* r10 = ftn */
4220                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
4221
4222                         /* Save args buffer */
4223                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
4224
4225                         /* Set argument registers */
4226                         for (i = 0; i < PARAM_REGS; ++i)
4227                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof (gpointer), 8);
4228
4229                         /* Make the call */
4230                         amd64_call_reg (code, AMD64_R10);
4231
4232                         /* Save result */
4233                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4234                         amd64_mov_membase_reg (code, AMD64_R11, G_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
4235                         break;
4236                 }
4237                 case OP_AMD64_SAVE_SP_TO_LMF:
4238                         amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
4239                         break;
4240                 case OP_X86_PUSH:
4241                         g_assert (!cfg->arch.no_pushes);
4242                         amd64_push_reg (code, ins->sreg1);
4243                         break;
4244                 case OP_X86_PUSH_IMM:
4245                         g_assert (!cfg->arch.no_pushes);
4246                         g_assert (amd64_is_imm32 (ins->inst_imm));
4247                         amd64_push_imm (code, ins->inst_imm);
4248                         break;
4249                 case OP_X86_PUSH_MEMBASE:
4250                         g_assert (!cfg->arch.no_pushes);
4251                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
4252                         break;
4253                 case OP_X86_PUSH_OBJ: {
4254                         int size = ALIGN_TO (ins->inst_imm, 8);
4255
4256                         g_assert (!cfg->arch.no_pushes);
4257
4258                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4259                         amd64_push_reg (code, AMD64_RDI);
4260                         amd64_push_reg (code, AMD64_RSI);
4261                         amd64_push_reg (code, AMD64_RCX);
4262                         if (ins->inst_offset)
4263                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
4264                         else
4265                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
4266                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
4267                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
4268                         amd64_cld (code);
4269                         amd64_prefix (code, X86_REP_PREFIX);
4270                         amd64_movsd (code);
4271                         amd64_pop_reg (code, AMD64_RCX);
4272                         amd64_pop_reg (code, AMD64_RSI);
4273                         amd64_pop_reg (code, AMD64_RDI);
4274                         break;
4275                 }
4276                 case OP_X86_LEA:
4277                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
4278                         break;
4279                 case OP_X86_LEA_MEMBASE:
4280                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
4281                         break;
4282                 case OP_X86_XCHG:
4283                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
4284                         break;
4285                 case OP_LOCALLOC:
4286                         /* keep alignment */
4287                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
4288                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
4289                         code = mono_emit_stack_alloc (cfg, code, ins);
4290                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4291                         if (cfg->param_area && cfg->arch.no_pushes)
4292                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4293                         break;
4294                 case OP_LOCALLOC_IMM: {
4295                         guint32 size = ins->inst_imm;
4296                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
4297
4298                         if (ins->flags & MONO_INST_INIT) {
4299                                 if (size < 64) {
4300                                         int i;
4301
4302                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4303                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4304
4305                                         for (i = 0; i < size; i += 8)
4306                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
4307                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4308                                 } else {
4309                                         amd64_mov_reg_imm (code, ins->dreg, size);
4310                                         ins->sreg1 = ins->dreg;
4311
4312                                         code = mono_emit_stack_alloc (cfg, code, ins);
4313                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4314                                 }
4315                         } else {
4316                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
4317                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
4318                         }
4319                         if (cfg->param_area && cfg->arch.no_pushes)
4320                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
4321                         break;
4322                 }
4323                 case OP_THROW: {
4324                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4325                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4326                                              (gpointer)"mono_arch_throw_exception", FALSE);
4327                         break;
4328                 }
4329                 case OP_RETHROW: {
4330                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
4331                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
4332                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
4333                         break;
4334                 }
4335                 case OP_CALL_HANDLER:
4336                         /* Align stack */
4337                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
4338                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4339                         amd64_call_imm (code, 0);
4340                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
4341                         /* Restore stack alignment */
4342                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
4343                         break;
4344                 case OP_START_HANDLER: {
4345                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4346                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, 8);
4347
4348                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
4349                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
4350                                 cfg->param_area && cfg->arch.no_pushes) {
4351                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
4352                         }
4353                         break;
4354                 }
4355                 case OP_ENDFINALLY: {
4356                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4357                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4358                         amd64_ret (code);
4359                         break;
4360                 }
4361                 case OP_ENDFILTER: {
4362                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
4363                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, 8);
4364                         /* The local allocator will put the result into RAX */
4365                         amd64_ret (code);
4366                         break;
4367                 }
4368
4369                 case OP_LABEL:
4370                         ins->inst_c0 = code - cfg->native_code;
4371                         break;
4372                 case OP_BR:
4373                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
4374                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
4375                         //break;
4376                                 if (ins->inst_target_bb->native_offset) {
4377                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
4378                                 } else {
4379                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
4380                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
4381                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
4382                                                 x86_jump8 (code, 0);
4383                                         else
4384                                                 x86_jump32 (code, 0);
4385                         }
4386                         break;
4387                 case OP_BR_REG:
4388                         amd64_jump_reg (code, ins->sreg1);
4389                         break;
4390                 case OP_CEQ:
4391                 case OP_LCEQ:
4392                 case OP_ICEQ:
4393                 case OP_CLT:
4394                 case OP_LCLT:
4395                 case OP_ICLT:
4396                 case OP_CGT:
4397                 case OP_ICGT:
4398                 case OP_LCGT:
4399                 case OP_CLT_UN:
4400                 case OP_LCLT_UN:
4401                 case OP_ICLT_UN:
4402                 case OP_CGT_UN:
4403                 case OP_LCGT_UN:
4404                 case OP_ICGT_UN:
4405                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4406                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
4407                         break;
4408                 case OP_COND_EXC_EQ:
4409                 case OP_COND_EXC_NE_UN:
4410                 case OP_COND_EXC_LT:
4411                 case OP_COND_EXC_LT_UN:
4412                 case OP_COND_EXC_GT:
4413                 case OP_COND_EXC_GT_UN:
4414                 case OP_COND_EXC_GE:
4415                 case OP_COND_EXC_GE_UN:
4416                 case OP_COND_EXC_LE:
4417                 case OP_COND_EXC_LE_UN:
4418                 case OP_COND_EXC_IEQ:
4419                 case OP_COND_EXC_INE_UN:
4420                 case OP_COND_EXC_ILT:
4421                 case OP_COND_EXC_ILT_UN:
4422                 case OP_COND_EXC_IGT:
4423                 case OP_COND_EXC_IGT_UN:
4424                 case OP_COND_EXC_IGE:
4425                 case OP_COND_EXC_IGE_UN:
4426                 case OP_COND_EXC_ILE:
4427                 case OP_COND_EXC_ILE_UN:
4428                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->inst_p1);
4429                         break;
4430                 case OP_COND_EXC_OV:
4431                 case OP_COND_EXC_NO:
4432                 case OP_COND_EXC_C:
4433                 case OP_COND_EXC_NC:
4434                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
4435                                                     (ins->opcode < OP_COND_EXC_NE_UN), ins->inst_p1);
4436                         break;
4437                 case OP_COND_EXC_IOV:
4438                 case OP_COND_EXC_INO:
4439                 case OP_COND_EXC_IC:
4440                 case OP_COND_EXC_INC:
4441                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
4442                                                     (ins->opcode < OP_COND_EXC_INE_UN), ins->inst_p1);
4443                         break;
4444
4445                 /* floating point opcodes */
4446                 case OP_R8CONST: {
4447                         double d = *(double *)ins->inst_p0;
4448
4449                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
4450                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4451                         }
4452                         else {
4453                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
4454                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4455                         }
4456                         break;
4457                 }
4458                 case OP_R4CONST: {
4459                         float f = *(float *)ins->inst_p0;
4460
4461                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
4462                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
4463                         }
4464                         else {
4465                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
4466                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4467                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4468                         }
4469                         break;
4470                 }
4471                 case OP_STORER8_MEMBASE_REG:
4472                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
4473                         break;
4474                 case OP_LOADR8_MEMBASE:
4475                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4476                         break;
4477                 case OP_STORER4_MEMBASE_REG:
4478                         /* This requires a double->single conversion */
4479                         amd64_sse_cvtsd2ss_reg_reg (code, AMD64_XMM15, ins->sreg1);
4480                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, AMD64_XMM15);
4481                         break;
4482                 case OP_LOADR4_MEMBASE:
4483                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4484                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
4485                         break;
4486                 case OP_ICONV_TO_R4: /* FIXME: change precision */
4487                 case OP_ICONV_TO_R8:
4488                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4489                         break;
4490                 case OP_LCONV_TO_R4: /* FIXME: change precision */
4491                 case OP_LCONV_TO_R8:
4492                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4493                         break;
4494                 case OP_FCONV_TO_R4:
4495                         /* FIXME: nothing to do ?? */
4496                         break;
4497                 case OP_FCONV_TO_I1:
4498                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
4499                         break;
4500                 case OP_FCONV_TO_U1:
4501                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
4502                         break;
4503                 case OP_FCONV_TO_I2:
4504                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
4505                         break;
4506                 case OP_FCONV_TO_U2:
4507                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
4508                         break;
4509                 case OP_FCONV_TO_U4:
4510                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
4511                         break;
4512                 case OP_FCONV_TO_I4:
4513                 case OP_FCONV_TO_I:
4514                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
4515                         break;
4516                 case OP_FCONV_TO_I8:
4517                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
4518                         break;
4519                 case OP_LCONV_TO_R_UN: {
4520                         guint8 *br [2];
4521
4522                         /* Based on gcc code */
4523                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4524                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
4525
4526                         /* Positive case */
4527                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
4528                         br [1] = code; x86_jump8 (code, 0);
4529                         amd64_patch (br [0], code);
4530
4531                         /* Negative case */
4532                         /* Save to the red zone */
4533                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
4534                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
4535                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
4536                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
4537                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
4538                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
4539                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
4540                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
4541                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
4542                         /* Restore */
4543                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
4544                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
4545                         amd64_patch (br [1], code);
4546                         break;
4547                 }
4548                 case OP_LCONV_TO_OVF_U4:
4549                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
4550                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
4551                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4552                         break;
4553                 case OP_LCONV_TO_OVF_I4_UN:
4554                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
4555                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
4556                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
4557                         break;
4558                 case OP_FMOVE:
4559                         if (ins->dreg != ins->sreg1)
4560                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4561                         break;
4562                 case OP_FADD:
4563                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
4564                         break;
4565                 case OP_FSUB:
4566                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
4567                         break;
4568                 case OP_FMUL:
4569                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
4570                         break;
4571                 case OP_FDIV:
4572                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
4573                         break;
4574                 case OP_FNEG: {
4575                         static double r8_0 = -0.0;
4576
4577                         g_assert (ins->sreg1 == ins->dreg);
4578
4579                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
4580                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4581                         break;
4582                 }
4583                 case OP_SIN:
4584                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
4585                         break;
4586                 case OP_COS:
4587                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
4588                         break;
4589                 case OP_ABS: {
4590                         static guint64 d = 0x7fffffffffffffffUL;
4591
4592                         g_assert (ins->sreg1 == ins->dreg);
4593
4594                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
4595                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
4596                         break;
4597                 }
4598                 case OP_SQRT:
4599                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
4600                         break;
4601                 case OP_IMIN:
4602                         g_assert (cfg->opt & MONO_OPT_CMOV);
4603                         g_assert (ins->dreg == ins->sreg1);
4604                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4605                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
4606                         break;
4607                 case OP_IMIN_UN:
4608                         g_assert (cfg->opt & MONO_OPT_CMOV);
4609                         g_assert (ins->dreg == ins->sreg1);
4610                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4611                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
4612                         break;
4613                 case OP_IMAX:
4614                         g_assert (cfg->opt & MONO_OPT_CMOV);
4615                         g_assert (ins->dreg == ins->sreg1);
4616                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4617                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
4618                         break;
4619                 case OP_IMAX_UN:
4620                         g_assert (cfg->opt & MONO_OPT_CMOV);
4621                         g_assert (ins->dreg == ins->sreg1);
4622                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4623                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
4624                         break;
4625                 case OP_LMIN:
4626                         g_assert (cfg->opt & MONO_OPT_CMOV);
4627                         g_assert (ins->dreg == ins->sreg1);
4628                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4629                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
4630                         break;
4631                 case OP_LMIN_UN:
4632                         g_assert (cfg->opt & MONO_OPT_CMOV);
4633                         g_assert (ins->dreg == ins->sreg1);
4634                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4635                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
4636                         break;
4637                 case OP_LMAX:
4638                         g_assert (cfg->opt & MONO_OPT_CMOV);
4639                         g_assert (ins->dreg == ins->sreg1);
4640                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4641                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
4642                         break;
4643                 case OP_LMAX_UN:
4644                         g_assert (cfg->opt & MONO_OPT_CMOV);
4645                         g_assert (ins->dreg == ins->sreg1);
4646                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4647                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
4648                         break;
4649                 case OP_X86_FPOP:
4650                         break;
4651                 case OP_FCOMPARE:
4652                         /*
4653                          * The two arguments are swapped because the fbranch instructions
4654                          * depend on this for the non-sse case to work.
4655                          */
4656                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4657                         break;
4658                 case OP_FCEQ: {
4659                         /* zeroing the register at the start results in
4660                          * shorter and faster code (we can also remove the widening op)
4661                          */
4662                         guchar *unordered_check;
4663                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4664                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
4665                         unordered_check = code;
4666                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4667                         amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
4668                         amd64_patch (unordered_check, code);
4669                         break;
4670                 }
4671                 case OP_FCLT:
4672                 case OP_FCLT_UN:
4673                         /* zeroing the register at the start results in
4674                          * shorter and faster code (we can also remove the widening op)
4675                          */
4676                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4677                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4678                         if (ins->opcode == OP_FCLT_UN) {
4679                                 guchar *unordered_check = code;
4680                                 guchar *jump_to_end;
4681                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4682                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4683                                 jump_to_end = code;
4684                                 x86_jump8 (code, 0);
4685                                 amd64_patch (unordered_check, code);
4686                                 amd64_inc_reg (code, ins->dreg);
4687                                 amd64_patch (jump_to_end, code);
4688                         } else {
4689                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
4690                         }
4691                         break;
4692                 case OP_FCGT:
4693                 case OP_FCGT_UN: {
4694                         /* zeroing the register at the start results in
4695                          * shorter and faster code (we can also remove the widening op)
4696                          */
4697                         guchar *unordered_check;
4698                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4699                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
4700                         if (ins->opcode == OP_FCGT) {
4701                                 unordered_check = code;
4702                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4703                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4704                                 amd64_patch (unordered_check, code);
4705                         } else {
4706                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
4707                         }
4708                         break;
4709                 }
4710                 case OP_FCLT_MEMBASE:
4711                 case OP_FCGT_MEMBASE:
4712                 case OP_FCLT_UN_MEMBASE:
4713                 case OP_FCGT_UN_MEMBASE:
4714                 case OP_FCEQ_MEMBASE: {
4715                         guchar *unordered_check, *jump_to_end;
4716                         int x86_cond;
4717
4718                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
4719                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
4720
4721                         switch (ins->opcode) {
4722                         case OP_FCEQ_MEMBASE:
4723                                 x86_cond = X86_CC_EQ;
4724                                 break;
4725                         case OP_FCLT_MEMBASE:
4726                         case OP_FCLT_UN_MEMBASE:
4727                                 x86_cond = X86_CC_LT;
4728                                 break;
4729                         case OP_FCGT_MEMBASE:
4730                         case OP_FCGT_UN_MEMBASE:
4731                                 x86_cond = X86_CC_GT;
4732                                 break;
4733                         default:
4734                                 g_assert_not_reached ();
4735                         }
4736
4737                         unordered_check = code;
4738                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4739                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
4740
4741                         switch (ins->opcode) {
4742                         case OP_FCEQ_MEMBASE:
4743                         case OP_FCLT_MEMBASE:
4744                         case OP_FCGT_MEMBASE:
4745                                 amd64_patch (unordered_check, code);
4746                                 break;
4747                         case OP_FCLT_UN_MEMBASE:
4748                         case OP_FCGT_UN_MEMBASE:
4749                                 jump_to_end = code;
4750                                 x86_jump8 (code, 0);
4751                                 amd64_patch (unordered_check, code);
4752                                 amd64_inc_reg (code, ins->dreg);
4753                                 amd64_patch (jump_to_end, code);
4754                                 break;
4755                         default:
4756                                 break;
4757                         }
4758                         break;
4759                 }
4760                 case OP_FBEQ: {
4761                         guchar *jump = code;
4762                         x86_branch8 (code, X86_CC_P, 0, TRUE);
4763                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
4764                         amd64_patch (jump, code);
4765                         break;
4766                 }
4767                 case OP_FBNE_UN:
4768                         /* Branch if C013 != 100 */
4769                         /* branch if !ZF or (PF|CF) */
4770                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
4771                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4772                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
4773                         break;
4774                 case OP_FBLT:
4775                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4776                         break;
4777                 case OP_FBLT_UN:
4778                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4779                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
4780                         break;
4781                 case OP_FBGT:
4782                 case OP_FBGT_UN:
4783                         if (ins->opcode == OP_FBGT) {
4784                                 guchar *br1;
4785
4786                                 /* skip branch if C1=1 */
4787                                 br1 = code;
4788                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
4789                                 /* branch if (C0 | C3) = 1 */
4790                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4791                                 amd64_patch (br1, code);
4792                                 break;
4793                         } else {
4794                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
4795                         }
4796                         break;
4797                 case OP_FBGE: {
4798                         /* Branch if C013 == 100 or 001 */
4799                         guchar *br1;
4800
4801                         /* skip branch if C1=1 */
4802                         br1 = code;
4803                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4804                         /* branch if (C0 | C3) = 1 */
4805                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
4806                         amd64_patch (br1, code);
4807                         break;
4808                 }
4809                 case OP_FBGE_UN:
4810                         /* Branch if C013 == 000 */
4811                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
4812                         break;
4813                 case OP_FBLE: {
4814                         /* Branch if C013=000 or 100 */
4815                         guchar *br1;
4816
4817                         /* skip branch if C1=1 */
4818                         br1 = code;
4819                         x86_branch8 (code, X86_CC_P, 0, FALSE);
4820                         /* branch if C0=0 */
4821                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
4822                         amd64_patch (br1, code);
4823                         break;
4824                 }
4825                 case OP_FBLE_UN:
4826                         /* Branch if C013 != 001 */
4827                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
4828                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
4829                         break;
4830                 case OP_CKFINITE:
4831                         /* Transfer value to the fp stack */
4832                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
4833                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
4834                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
4835
4836                         amd64_push_reg (code, AMD64_RAX);
4837                         amd64_fxam (code);
4838                         amd64_fnstsw (code);
4839                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
4840                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
4841                         amd64_pop_reg (code, AMD64_RAX);
4842                         amd64_fstp (code, 0);
4843                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
4844                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
4845                         break;
4846                 case OP_TLS_GET: {
4847                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
4848                         break;
4849                 }
4850                 case OP_MEMORY_BARRIER: {
4851                         /* Not needed on amd64 */
4852                         break;
4853                 }
4854                 case OP_ATOMIC_ADD_I4:
4855                 case OP_ATOMIC_ADD_I8: {
4856                         int dreg = ins->dreg;
4857                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
4858
4859                         if (dreg == ins->inst_basereg)
4860                                 dreg = AMD64_R11;
4861
4862                         if (dreg != ins->sreg2)
4863                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg2, size);
4864
4865                         x86_prefix (code, X86_LOCK_PREFIX);
4866                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4867
4868                         if (dreg != ins->dreg)
4869                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4870
4871                         break;
4872                 }
4873                 case OP_ATOMIC_ADD_NEW_I4:
4874                 case OP_ATOMIC_ADD_NEW_I8: {
4875                         int dreg = ins->dreg;
4876                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_NEW_I4) ? 4 : 8;
4877
4878                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
4879                                 dreg = AMD64_R11;
4880
4881                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
4882                         amd64_prefix (code, X86_LOCK_PREFIX);
4883                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
4884                         /* dreg contains the old value, add with sreg2 value */
4885                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
4886
4887                         if (ins->dreg != dreg)
4888                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
4889
4890                         break;
4891                 }
4892                 case OP_ATOMIC_EXCHANGE_I4:
4893                 case OP_ATOMIC_EXCHANGE_I8: {
4894                         guchar *br[2];
4895                         int sreg2 = ins->sreg2;
4896                         int breg = ins->inst_basereg;
4897                         guint32 size;
4898                         gboolean need_push = FALSE, rdx_pushed = FALSE;
4899
4900                         if (ins->opcode == OP_ATOMIC_EXCHANGE_I8)
4901                                 size = 8;
4902                         else
4903                                 size = 4;
4904
4905                         /*
4906                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4907                          * an explanation of how this works.
4908                          */
4909
4910                         /* cmpxchg uses eax as comperand, need to make sure we can use it
4911                          * hack to overcome limits in x86 reg allocator
4912                          * (req: dreg == eax and sreg2 != eax and breg != eax)
4913                          */
4914                         g_assert (ins->dreg == AMD64_RAX);
4915
4916                         if (breg == AMD64_RAX && ins->sreg2 == AMD64_RAX)
4917                                 /* Highly unlikely, but possible */
4918                                 need_push = TRUE;
4919
4920                         /* The pushes invalidate rsp */
4921                         if ((breg == AMD64_RAX) || need_push) {
4922                                 amd64_mov_reg_reg (code, AMD64_R11, breg, 8);
4923                                 breg = AMD64_R11;
4924                         }
4925
4926                         /* We need the EAX reg for the comparand */
4927                         if (ins->sreg2 == AMD64_RAX) {
4928                                 if (breg != AMD64_R11) {
4929                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4930                                         sreg2 = AMD64_R11;
4931                                 } else {
4932                                         g_assert (need_push);
4933                                         amd64_push_reg (code, AMD64_RDX);
4934                                         amd64_mov_reg_reg (code, AMD64_RDX, AMD64_RAX, size);
4935                                         sreg2 = AMD64_RDX;
4936                                         rdx_pushed = TRUE;
4937                                 }
4938                         }
4939
4940                         amd64_mov_reg_membase (code, AMD64_RAX, breg, ins->inst_offset, size);
4941
4942                         br [0] = code; amd64_prefix (code, X86_LOCK_PREFIX);
4943                         amd64_cmpxchg_membase_reg_size (code, breg, ins->inst_offset, sreg2, size);
4944                         br [1] = code; amd64_branch8 (code, X86_CC_NE, -1, FALSE);
4945                         amd64_patch (br [1], br [0]);
4946
4947                         if (rdx_pushed)
4948                                 amd64_pop_reg (code, AMD64_RDX);
4949
4950                         break;
4951                 }
4952                 case OP_ATOMIC_CAS_I4:
4953                 case OP_ATOMIC_CAS_I8: {
4954                         guint32 size;
4955
4956                         if (ins->opcode == OP_ATOMIC_CAS_I8)
4957                                 size = 8;
4958                         else
4959                                 size = 4;
4960
4961                         /*
4962                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
4963                          * an explanation of how this works.
4964                          */
4965                         g_assert (ins->sreg3 == AMD64_RAX);
4966                         g_assert (ins->sreg1 != AMD64_RAX);
4967                         g_assert (ins->sreg1 != ins->sreg2);
4968
4969                         amd64_prefix (code, X86_LOCK_PREFIX);
4970                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
4971
4972                         if (ins->dreg != AMD64_RAX)
4973                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
4974                         break;
4975                 }
4976 #ifdef MONO_ARCH_SIMD_INTRINSICS
4977                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
4978                 case OP_ADDPS:
4979                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
4980                         break;
4981                 case OP_DIVPS:
4982                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
4983                         break;
4984                 case OP_MULPS:
4985                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
4986                         break;
4987                 case OP_SUBPS:
4988                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
4989                         break;
4990                 case OP_MAXPS:
4991                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
4992                         break;
4993                 case OP_MINPS:
4994                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
4995                         break;
4996                 case OP_COMPPS:
4997                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
4998                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
4999                         break;
5000                 case OP_ANDPS:
5001                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
5002                         break;
5003                 case OP_ANDNPS:
5004                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
5005                         break;
5006                 case OP_ORPS:
5007                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
5008                         break;
5009                 case OP_XORPS:
5010                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
5011                         break;
5012                 case OP_SQRTPS:
5013                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5014                         break;
5015                 case OP_RSQRTPS:
5016                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
5017                         break;
5018                 case OP_RCPPS:
5019                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
5020                         break;
5021                 case OP_ADDSUBPS:
5022                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5023                         break;
5024                 case OP_HADDPS:
5025                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
5026                         break;
5027                 case OP_HSUBPS:
5028                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
5029                         break;
5030                 case OP_DUPPS_HIGH:
5031                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
5032                         break;
5033                 case OP_DUPPS_LOW:
5034                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
5035                         break;
5036
5037                 case OP_PSHUFLEW_HIGH:
5038                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5039                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5040                         break;
5041                 case OP_PSHUFLEW_LOW:
5042                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5043                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5044                         break;
5045                 case OP_PSHUFLED:
5046                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
5047                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5048                         break;
5049
5050                 case OP_ADDPD:
5051                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
5052                         break;
5053                 case OP_DIVPD:
5054                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
5055                         break;
5056                 case OP_MULPD:
5057                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
5058                         break;
5059                 case OP_SUBPD:
5060                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
5061                         break;
5062                 case OP_MAXPD:
5063                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
5064                         break;
5065                 case OP_MINPD:
5066                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
5067                         break;
5068                 case OP_COMPPD:
5069                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
5070                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5071                         break;
5072                 case OP_ANDPD:
5073                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
5074                         break;
5075                 case OP_ANDNPD:
5076                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
5077                         break;
5078                 case OP_ORPD:
5079                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
5080                         break;
5081                 case OP_XORPD:
5082                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
5083                         break;
5084                 case OP_SQRTPD:
5085                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
5086                         break;
5087                 case OP_ADDSUBPD:
5088                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5089                         break;
5090                 case OP_HADDPD:
5091                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
5092                         break;
5093                 case OP_HSUBPD:
5094                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
5095                         break;
5096                 case OP_DUPPD:
5097                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
5098                         break;
5099
5100                 case OP_EXTRACT_MASK:
5101                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
5102                         break;
5103
5104                 case OP_PAND:
5105                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
5106                         break;
5107                 case OP_POR:
5108                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
5109                         break;
5110                 case OP_PXOR:
5111                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
5112                         break;
5113
5114                 case OP_PADDB:
5115                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
5116                         break;
5117                 case OP_PADDW:
5118                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
5119                         break;
5120                 case OP_PADDD:
5121                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
5122                         break;
5123                 case OP_PADDQ:
5124                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
5125                         break;
5126
5127                 case OP_PSUBB:
5128                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
5129                         break;
5130                 case OP_PSUBW:
5131                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
5132                         break;
5133                 case OP_PSUBD:
5134                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
5135                         break;
5136                 case OP_PSUBQ:
5137                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
5138                         break;
5139
5140                 case OP_PMAXB_UN:
5141                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
5142                         break;
5143                 case OP_PMAXW_UN:
5144                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
5145                         break;
5146                 case OP_PMAXD_UN:
5147                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
5148                         break;
5149
5150                 case OP_PMAXB:
5151                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
5152                         break;
5153                 case OP_PMAXW:
5154                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
5155                         break;
5156                 case OP_PMAXD:
5157                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
5158                         break;
5159
5160                 case OP_PAVGB_UN:
5161                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
5162                         break;
5163                 case OP_PAVGW_UN:
5164                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
5165                         break;
5166
5167                 case OP_PMINB_UN:
5168                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
5169                         break;
5170                 case OP_PMINW_UN:
5171                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
5172                         break;
5173                 case OP_PMIND_UN:
5174                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
5175                         break;
5176
5177                 case OP_PMINB:
5178                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
5179                         break;
5180                 case OP_PMINW:
5181                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
5182                         break;
5183                 case OP_PMIND:
5184                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
5185                         break;
5186
5187                 case OP_PCMPEQB:
5188                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
5189                         break;
5190                 case OP_PCMPEQW:
5191                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
5192                         break;
5193                 case OP_PCMPEQD:
5194                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
5195                         break;
5196                 case OP_PCMPEQQ:
5197                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
5198                         break;
5199
5200                 case OP_PCMPGTB:
5201                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
5202                         break;
5203                 case OP_PCMPGTW:
5204                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
5205                         break;
5206                 case OP_PCMPGTD:
5207                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
5208                         break;
5209                 case OP_PCMPGTQ:
5210                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
5211                         break;
5212
5213                 case OP_PSUM_ABS_DIFF:
5214                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
5215                         break;
5216
5217                 case OP_UNPACK_LOWB:
5218                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
5219                         break;
5220                 case OP_UNPACK_LOWW:
5221                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
5222                         break;
5223                 case OP_UNPACK_LOWD:
5224                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
5225                         break;
5226                 case OP_UNPACK_LOWQ:
5227                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5228                         break;
5229                 case OP_UNPACK_LOWPS:
5230                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
5231                         break;
5232                 case OP_UNPACK_LOWPD:
5233                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
5234                         break;
5235
5236                 case OP_UNPACK_HIGHB:
5237                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
5238                         break;
5239                 case OP_UNPACK_HIGHW:
5240                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
5241                         break;
5242                 case OP_UNPACK_HIGHD:
5243                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
5244                         break;
5245                 case OP_UNPACK_HIGHQ:
5246                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
5247                         break;
5248                 case OP_UNPACK_HIGHPS:
5249                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
5250                         break;
5251                 case OP_UNPACK_HIGHPD:
5252                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
5253                         break;
5254
5255                 case OP_PACKW:
5256                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
5257                         break;
5258                 case OP_PACKD:
5259                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
5260                         break;
5261                 case OP_PACKW_UN:
5262                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
5263                         break;
5264                 case OP_PACKD_UN:
5265                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
5266                         break;
5267
5268                 case OP_PADDB_SAT_UN:
5269                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
5270                         break;
5271                 case OP_PSUBB_SAT_UN:
5272                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
5273                         break;
5274                 case OP_PADDW_SAT_UN:
5275                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
5276                         break;
5277                 case OP_PSUBW_SAT_UN:
5278                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
5279                         break;
5280
5281                 case OP_PADDB_SAT:
5282                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
5283                         break;
5284                 case OP_PSUBB_SAT:
5285                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
5286                         break;
5287                 case OP_PADDW_SAT:
5288                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
5289                         break;
5290                 case OP_PSUBW_SAT:
5291                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
5292                         break;
5293
5294                 case OP_PMULW:
5295                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
5296                         break;
5297                 case OP_PMULD:
5298                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
5299                         break;
5300                 case OP_PMULQ:
5301                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
5302                         break;
5303                 case OP_PMULW_HIGH_UN:
5304                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
5305                         break;
5306                 case OP_PMULW_HIGH:
5307                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
5308                         break;
5309
5310                 case OP_PSHRW:
5311                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
5312                         break;
5313                 case OP_PSHRW_REG:
5314                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
5315                         break;
5316
5317                 case OP_PSARW:
5318                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
5319                         break;
5320                 case OP_PSARW_REG:
5321                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
5322                         break;
5323
5324                 case OP_PSHLW:
5325                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
5326                         break;
5327                 case OP_PSHLW_REG:
5328                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
5329                         break;
5330
5331                 case OP_PSHRD:
5332                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
5333                         break;
5334                 case OP_PSHRD_REG:
5335                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
5336                         break;
5337
5338                 case OP_PSARD:
5339                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
5340                         break;
5341                 case OP_PSARD_REG:
5342                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
5343                         break;
5344
5345                 case OP_PSHLD:
5346                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
5347                         break;
5348                 case OP_PSHLD_REG:
5349                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
5350                         break;
5351
5352                 case OP_PSHRQ:
5353                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
5354                         break;
5355                 case OP_PSHRQ_REG:
5356                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
5357                         break;
5358
5359                 /*TODO: This is appart of the sse spec but not added
5360                 case OP_PSARQ:
5361                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
5362                         break;
5363                 case OP_PSARQ_REG:
5364                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
5365                         break;
5366                 */
5367
5368                 case OP_PSHLQ:
5369                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
5370                         break;
5371                 case OP_PSHLQ_REG:
5372                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
5373                         break;
5374
5375                 case OP_ICONV_TO_X:
5376                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5377                         break;
5378                 case OP_EXTRACT_I4:
5379                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5380                         break;
5381                 case OP_EXTRACT_I8:
5382                         if (ins->inst_c0) {
5383                                 amd64_movhlps_reg_reg (code, AMD64_XMM15, ins->sreg1);
5384                                 amd64_movd_reg_xreg_size (code, ins->dreg, AMD64_XMM15, 8);
5385                         } else {
5386                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5387                         }
5388                         break;
5389                 case OP_EXTRACT_I1:
5390                 case OP_EXTRACT_U1:
5391                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5392                         if (ins->inst_c0)
5393                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
5394                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
5395                         break;
5396                 case OP_EXTRACT_I2:
5397                 case OP_EXTRACT_U2:
5398                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5399                         if (ins->inst_c0)
5400                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
5401                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5402                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
5403                         break;
5404                 case OP_EXTRACT_R8:
5405                         if (ins->inst_c0)
5406                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
5407                         else
5408                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5409                         break;
5410                 case OP_INSERT_I2:
5411                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
5412                         break;
5413                 case OP_EXTRACTX_U2:
5414                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
5415                         break;
5416                 case OP_INSERTX_U1_SLOW:
5417                         /*sreg1 is the extracted ireg (scratch)
5418                         /sreg2 is the to be inserted ireg (scratch)
5419                         /dreg is the xreg to receive the value*/
5420
5421                         /*clear the bits from the extracted word*/
5422                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
5423                         /*shift the value to insert if needed*/
5424                         if (ins->inst_c0 & 1)
5425                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
5426                         /*join them together*/
5427                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
5428                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
5429                         break;
5430                 case OP_INSERTX_I4_SLOW:
5431                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
5432                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
5433                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
5434                         break;
5435                 case OP_INSERTX_I8_SLOW:
5436                         amd64_movd_xreg_reg_size(code, AMD64_XMM15, ins->sreg2, 8);
5437                         if (ins->inst_c0)
5438                                 amd64_movlhps_reg_reg (code, ins->dreg, AMD64_XMM15);
5439                         else
5440                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM15);
5441                         break;
5442
5443                 case OP_INSERTX_R4_SLOW:
5444                         switch (ins->inst_c0) {
5445                         case 0:
5446                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5447                                 break;
5448                         case 1:
5449                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5450                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5451                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
5452                                 break;
5453                         case 2:
5454                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5455                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5456                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
5457                                 break;
5458                         case 3:
5459                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5460                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
5461                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
5462                                 break;
5463                         }
5464                         break;
5465                 case OP_INSERTX_R8_SLOW:
5466                         if (ins->inst_c0)
5467                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
5468                         else
5469                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
5470                         break;
5471                 case OP_STOREX_MEMBASE_REG:
5472                 case OP_STOREX_MEMBASE:
5473                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5474                         break;
5475                 case OP_LOADX_MEMBASE:
5476                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5477                         break;
5478                 case OP_LOADX_ALIGNED_MEMBASE:
5479                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5480                         break;
5481                 case OP_STOREX_ALIGNED_MEMBASE_REG:
5482                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
5483                         break;
5484                 case OP_STOREX_NTA_MEMBASE_REG:
5485                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
5486                         break;
5487                 case OP_PREFETCH_MEMBASE:
5488                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
5489                         break;
5490
5491                 case OP_XMOVE:
5492                         /*FIXME the peephole pass should have killed this*/
5493                         if (ins->dreg != ins->sreg1)
5494                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
5495                         break;
5496                 case OP_XZERO:
5497                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
5498                         break;
5499                 case OP_ICONV_TO_R8_RAW:
5500                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5501                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5502                         break;
5503
5504                 case OP_FCONV_TO_R8_X:
5505                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5506                         break;
5507
5508                 case OP_XCONV_R8_TO_I4:
5509                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
5510                         switch (ins->backend.source_opcode) {
5511                         case OP_FCONV_TO_I1:
5512                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5513                                 break;
5514                         case OP_FCONV_TO_U1:
5515                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5516                                 break;
5517                         case OP_FCONV_TO_I2:
5518                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5519                                 break;
5520                         case OP_FCONV_TO_U2:
5521                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5522                                 break;
5523                         }
5524                         break;
5525
5526                 case OP_EXPAND_I2:
5527                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
5528                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
5529                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5530                         break;
5531                 case OP_EXPAND_I4:
5532                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
5533                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5534                         break;
5535                 case OP_EXPAND_I8:
5536                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5537                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5538                         break;
5539                 case OP_EXPAND_R4:
5540                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5541                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
5542                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
5543                         break;
5544                 case OP_EXPAND_R8:
5545                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5546                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
5547                         break;
5548 #endif
5549                 case OP_LIVERANGE_START: {
5550                         if (cfg->verbose_level > 1)
5551                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5552                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
5553                         break;
5554                 }
5555                 case OP_LIVERANGE_END: {
5556                         if (cfg->verbose_level > 1)
5557                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
5558                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
5559                         break;
5560                 }
5561                 default:
5562                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
5563                         g_assert_not_reached ();
5564                 }
5565
5566                 if ((code - cfg->native_code - offset) > max_len) {
5567                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
5568                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
5569                         g_assert_not_reached ();
5570                 }
5571
5572                 last_ins = ins;
5573                 last_offset = offset;
5574         }
5575
5576         cfg->code_len = code - cfg->native_code;
5577 }
5578
5579 #endif /* DISABLE_JIT */
5580
5581 void
5582 mono_arch_register_lowlevel_calls (void)
5583 {
5584         /* The signature doesn't matter */
5585         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
5586 }
5587
5588 void
5589 mono_arch_patch_code (MonoMethod *method, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gboolean run_cctors)
5590 {
5591         MonoJumpInfo *patch_info;
5592         gboolean compile_aot = !run_cctors;
5593
5594         for (patch_info = ji; patch_info; patch_info = patch_info->next) {
5595                 unsigned char *ip = patch_info->ip.i + code;
5596                 unsigned char *target;
5597
5598                 target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
5599
5600                 if (compile_aot) {
5601                         switch (patch_info->type) {
5602                         case MONO_PATCH_INFO_BB:
5603                         case MONO_PATCH_INFO_LABEL:
5604                                 break;
5605                         default:
5606                                 /* No need to patch these */
5607                                 continue;
5608                         }
5609                 }
5610
5611                 switch (patch_info->type) {
5612                 case MONO_PATCH_INFO_NONE:
5613                         continue;
5614                 case MONO_PATCH_INFO_METHOD_REL:
5615                 case MONO_PATCH_INFO_R8:
5616                 case MONO_PATCH_INFO_R4:
5617                         g_assert_not_reached ();
5618                         continue;
5619                 case MONO_PATCH_INFO_BB:
5620                         break;
5621                 default:
5622                         break;
5623                 }
5624
5625                 /*
5626                  * Debug code to help track down problems where the target of a near call is
5627                  * is not valid.
5628                  */
5629                 if (amd64_is_near_call (ip)) {
5630                         gint64 disp = (guint8*)target - (guint8*)ip;
5631
5632                         if (!amd64_is_imm32 (disp)) {
5633                                 printf ("TYPE: %d\n", patch_info->type);
5634                                 switch (patch_info->type) {
5635                                 case MONO_PATCH_INFO_INTERNAL_METHOD:
5636                                         printf ("V: %s\n", patch_info->data.name);
5637                                         break;
5638                                 case MONO_PATCH_INFO_METHOD_JUMP:
5639                                 case MONO_PATCH_INFO_METHOD:
5640                                         printf ("V: %s\n", patch_info->data.method->name);
5641                                         break;
5642                                 default:
5643                                         break;
5644                                 }
5645                         }
5646                 }
5647
5648                 amd64_patch (ip, (gpointer)target);
5649         }
5650 }
5651
5652 #ifndef DISABLE_JIT
5653
5654 static int
5655 get_max_epilog_size (MonoCompile *cfg)
5656 {
5657         int max_epilog_size = 16;
5658
5659         if (cfg->method->save_lmf)
5660                 max_epilog_size += 256;
5661
5662         if (mono_jit_trace_calls != NULL)
5663                 max_epilog_size += 50;
5664
5665         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
5666                 max_epilog_size += 50;
5667
5668         max_epilog_size += (AMD64_NREG * 2);
5669
5670         return max_epilog_size;
5671 }
5672
5673 /*
5674  * This macro is used for testing whenever the unwinder works correctly at every point
5675  * where an async exception can happen.
5676  */
5677 /* This will generate a SIGSEGV at the given point in the code */
5678 #define async_exc_point(code) do { \
5679     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
5680          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
5681              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
5682          cfg->arch.async_point_count ++; \
5683     } \
5684 } while (0)
5685
5686 guint8 *
5687 mono_arch_emit_prolog (MonoCompile *cfg)
5688 {
5689         MonoMethod *method = cfg->method;
5690         MonoBasicBlock *bb;
5691         MonoMethodSignature *sig;
5692         MonoInst *ins;
5693         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size;
5694         guint8 *code;
5695         CallInfo *cinfo;
5696         gint32 lmf_offset = cfg->arch.lmf_offset;
5697         gboolean args_clobbered = FALSE;
5698         gboolean trace = FALSE;
5699
5700         cfg->code_size =  MAX (cfg->header->code_size * 4, 10240);
5701
5702         code = cfg->native_code = g_malloc (cfg->code_size);
5703
5704         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
5705                 trace = TRUE;
5706
5707         /* Amount of stack space allocated by register saving code */
5708         pos = 0;
5709
5710         /* Offset between RSP and the CFA */
5711         cfa_offset = 0;
5712
5713         /*
5714          * The prolog consists of the following parts:
5715          * FP present:
5716          * - push rbp, mov rbp, rsp
5717          * - save callee saved regs using pushes
5718          * - allocate frame
5719          * - save rgctx if needed
5720          * - save lmf if needed
5721          * FP not present:
5722          * - allocate frame
5723          * - save rgctx if needed
5724          * - save lmf if needed
5725          * - save callee saved regs using moves
5726          */
5727
5728         // CFA = sp + 8
5729         cfa_offset = 8;
5730         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
5731         // IP saved at CFA - 8
5732         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
5733         async_exc_point (code);
5734
5735         if (!cfg->arch.omit_fp) {
5736                 amd64_push_reg (code, AMD64_RBP);
5737                 cfa_offset += 8;
5738                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5739                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
5740                 async_exc_point (code);
5741 #ifdef HOST_WIN32
5742                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5743 #endif
5744
5745                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof (gpointer));
5746                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
5747                 async_exc_point (code);
5748 #ifdef HOST_WIN32
5749                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
5750 #endif
5751         }
5752
5753         /* Save callee saved registers */
5754         if (!cfg->arch.omit_fp && !method->save_lmf) {
5755                 int offset = cfa_offset;
5756
5757                 for (i = 0; i < AMD64_NREG; ++i)
5758                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5759                                 amd64_push_reg (code, i);
5760                                 pos += sizeof (gpointer);
5761                                 offset += 8;
5762                                 mono_emit_unwind_op_offset (cfg, code, i, - offset);
5763                                 async_exc_point (code);
5764                         }
5765         }
5766
5767         /* The param area is always at offset 0 from sp */
5768         /* This needs to be allocated here, since it has to come after the spill area */
5769         if (cfg->arch.no_pushes && cfg->param_area) {
5770                 if (cfg->arch.omit_fp)
5771                         // FIXME:
5772                         g_assert_not_reached ();
5773                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof (gpointer));
5774         }
5775
5776         if (cfg->arch.omit_fp) {
5777                 /*
5778                  * On enter, the stack is misaligned by the the pushing of the return
5779                  * address. It is either made aligned by the pushing of %rbp, or by
5780                  * this.
5781                  */
5782                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
5783                 if ((alloc_size % 16) == 0)
5784                         alloc_size += 8;
5785         } else {
5786                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
5787
5788                 alloc_size -= pos;
5789         }
5790
5791         cfg->arch.stack_alloc_size = alloc_size;
5792
5793         /* Allocate stack frame */
5794         if (alloc_size) {
5795                 /* See mono_emit_stack_alloc */
5796 #if defined(HOST_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
5797                 guint32 remaining_size = alloc_size;
5798                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
5799                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
5800                 guint32 offset = code - cfg->native_code;
5801                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
5802                         while (required_code_size >= (cfg->code_size - offset))
5803                                 cfg->code_size *= 2;
5804                         cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
5805                         code = cfg->native_code + offset;
5806                         mono_jit_stats.code_reallocs++;
5807                 }
5808
5809                 while (remaining_size >= 0x1000) {
5810                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
5811                         if (cfg->arch.omit_fp) {
5812                                 cfa_offset += 0x1000;
5813                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5814                         }
5815                         async_exc_point (code);
5816 #ifdef HOST_WIN32
5817                         if (cfg->arch.omit_fp)
5818                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
5819 #endif
5820
5821                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
5822                         remaining_size -= 0x1000;
5823                 }
5824                 if (remaining_size) {
5825                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
5826                         if (cfg->arch.omit_fp) {
5827                                 cfa_offset += remaining_size;
5828                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5829                                 async_exc_point (code);
5830                         }
5831 #ifdef HOST_WIN32
5832                         if (cfg->arch.omit_fp)
5833                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
5834 #endif
5835                 }
5836 #else
5837                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
5838                 if (cfg->arch.omit_fp) {
5839                         cfa_offset += alloc_size;
5840                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
5841                         async_exc_point (code);
5842                 }
5843 #endif
5844         }
5845
5846         /* Stack alignment check */
5847 #if 0
5848         {
5849                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
5850                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
5851                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
5852                 x86_branch8 (code, X86_CC_EQ, 2, FALSE);
5853                 amd64_breakpoint (code);
5854         }
5855 #endif
5856
5857 #ifndef TARGET_WIN32
5858         if (mini_get_debug_options ()->init_stacks) {
5859                 /* Fill the stack frame with a dummy value to force deterministic behavior */
5860
5861                 /* Save registers to the red zone */
5862                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
5863                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5864
5865                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
5866                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
5867                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
5868
5869                 amd64_cld (code);
5870                 amd64_prefix (code, X86_REP_PREFIX);
5871                 amd64_stosl (code);
5872
5873                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
5874                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5875         }
5876 #endif
5877
5878         /* Save LMF */
5879         if (method->save_lmf) {
5880                 /*
5881                  * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
5882                  */
5883                 /*
5884                  * sp is saved right before calls but we need to save it here too so
5885                  * async stack walks would work.
5886                  */
5887                 amd64_mov_membase_reg (code, cfg->frame_reg, cfg->arch.lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5888                 /* Skip method (only needed for trampoline LMF frames) */
5889                 /* Save callee saved regs */
5890                 for (i = 0; i < MONO_MAX_IREGS; ++i) {
5891                         int offset;
5892
5893                         switch (i) {
5894                         case AMD64_RBX: offset = G_STRUCT_OFFSET (MonoLMF, rbx); break;
5895                         case AMD64_RBP: offset = G_STRUCT_OFFSET (MonoLMF, rbp); break;
5896                         case AMD64_R12: offset = G_STRUCT_OFFSET (MonoLMF, r12); break;
5897                         case AMD64_R13: offset = G_STRUCT_OFFSET (MonoLMF, r13); break;
5898                         case AMD64_R14: offset = G_STRUCT_OFFSET (MonoLMF, r14); break;
5899                         case AMD64_R15: offset = G_STRUCT_OFFSET (MonoLMF, r15); break;
5900 #ifdef HOST_WIN32
5901                         case AMD64_RDI: offset = G_STRUCT_OFFSET (MonoLMF, rdi); break;
5902                         case AMD64_RSI: offset = G_STRUCT_OFFSET (MonoLMF, rsi); break;
5903 #endif
5904                         default:
5905                                 offset = -1;
5906                                 break;
5907                         }
5908
5909                         if (offset != -1) {
5910                                 amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + offset, i, 8);
5911                                 if (cfg->arch.omit_fp || (i != AMD64_RBP))
5912                                         mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - (lmf_offset + offset)));
5913                         }
5914                 }
5915         }
5916
5917         /* Save callee saved registers */
5918         if (cfg->arch.omit_fp && !method->save_lmf) {
5919                 gint32 save_area_offset = cfg->arch.reg_save_area_offset;
5920
5921                 /* Save caller saved registers after sp is adjusted */
5922                 /* The registers are saved at the bottom of the frame */
5923                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
5924                 for (i = 0; i < AMD64_NREG; ++i)
5925                         if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
5926                                 amd64_mov_membase_reg (code, AMD64_RSP, save_area_offset, i, 8);
5927                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
5928                                 save_area_offset += 8;
5929                                 async_exc_point (code);
5930                         }
5931         }
5932
5933         /* store runtime generic context */
5934         if (cfg->rgctx_var) {
5935                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
5936                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
5937
5938                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, 8);
5939         }
5940
5941         /* compute max_length in order to use short forward jumps */
5942         max_epilog_size = get_max_epilog_size (cfg);
5943         if (cfg->opt & MONO_OPT_BRANCH) {
5944                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
5945                         MonoInst *ins;
5946                         int max_length = 0;
5947
5948                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
5949                                 max_length += 6;
5950                         /* max alignment for loops */
5951                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
5952                                 max_length += LOOP_ALIGNMENT;
5953
5954                         MONO_BB_FOR_EACH_INS (bb, ins) {
5955                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
5956                         }
5957
5958                         /* Take prolog and epilog instrumentation into account */
5959                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
5960                                 max_length += max_epilog_size;
5961
5962                         bb->max_length = max_length;
5963                 }
5964         }
5965
5966         sig = mono_method_signature (method);
5967         pos = 0;
5968
5969         cinfo = cfg->arch.cinfo;
5970
5971         if (sig->ret->type != MONO_TYPE_VOID) {
5972                 /* Save volatile arguments to the stack */
5973                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
5974                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
5975         }
5976
5977         /* Keep this in sync with emit_load_volatile_arguments */
5978         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
5979                 ArgInfo *ainfo = cinfo->args + i;
5980                 gint32 stack_offset;
5981                 MonoType *arg_type;
5982
5983                 ins = cfg->args [i];
5984
5985                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
5986                         /* Unused arguments */
5987                         continue;
5988
5989                 if (sig->hasthis && (i == 0))
5990                         arg_type = &mono_defaults.object_class->byval_arg;
5991                 else
5992                         arg_type = sig->params [i - sig->hasthis];
5993
5994                 stack_offset = ainfo->offset + ARGS_OFFSET;
5995
5996                 if (cfg->globalra) {
5997                         /* All the other moves are done by the register allocator */
5998                         switch (ainfo->storage) {
5999                         case ArgInFloatSSEReg:
6000                                 amd64_sse_cvtss2sd_reg_reg (code, ainfo->reg, ainfo->reg);
6001                                 break;
6002                         case ArgValuetypeInReg:
6003                                 for (quad = 0; quad < 2; quad ++) {
6004                                         switch (ainfo->pair_storage [quad]) {
6005                                         case ArgInIReg:
6006                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6007                                                 break;
6008                                         case ArgInFloatSSEReg:
6009                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6010                                                 break;
6011                                         case ArgInDoubleSSEReg:
6012                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6013                                                 break;
6014                                         case ArgNone:
6015                                                 break;
6016                                         default:
6017                                                 g_assert_not_reached ();
6018                                         }
6019                                 }
6020                                 break;
6021                         default:
6022                                 break;
6023                         }
6024
6025                         continue;
6026                 }
6027
6028                 /* Save volatile arguments to the stack */
6029                 if (ins->opcode != OP_REGVAR) {
6030                         switch (ainfo->storage) {
6031                         case ArgInIReg: {
6032                                 guint32 size = 8;
6033
6034                                 /* FIXME: I1 etc */
6035                                 /*
6036                                 if (stack_offset & 0x1)
6037                                         size = 1;
6038                                 else if (stack_offset & 0x2)
6039                                         size = 2;
6040                                 else if (stack_offset & 0x4)
6041                                         size = 4;
6042                                 else
6043                                         size = 8;
6044                                 */
6045                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
6046                                 break;
6047                         }
6048                         case ArgInFloatSSEReg:
6049                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6050                                 break;
6051                         case ArgInDoubleSSEReg:
6052                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
6053                                 break;
6054                         case ArgValuetypeInReg:
6055                                 for (quad = 0; quad < 2; quad ++) {
6056                                         switch (ainfo->pair_storage [quad]) {
6057                                         case ArgInIReg:
6058                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad], sizeof (gpointer));
6059                                                 break;
6060                                         case ArgInFloatSSEReg:
6061                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6062                                                 break;
6063                                         case ArgInDoubleSSEReg:
6064                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof (gpointer)), ainfo->pair_regs [quad]);
6065                                                 break;
6066                                         case ArgNone:
6067                                                 break;
6068                                         default:
6069                                                 g_assert_not_reached ();
6070                                         }
6071                                 }
6072                                 break;
6073                         case ArgValuetypeAddrInIReg:
6074                                 if (ainfo->pair_storage [0] == ArgInIReg)
6075                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
6076                                 break;
6077                         default:
6078                                 break;
6079                         }
6080                 } else {
6081                         /* Argument allocated to (non-volatile) register */
6082                         switch (ainfo->storage) {
6083                         case ArgInIReg:
6084                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
6085                                 break;
6086                         case ArgOnStack:
6087                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
6088                                 break;
6089                         default:
6090                                 g_assert_not_reached ();
6091                         }
6092                 }
6093         }
6094
6095         /* Might need to attach the thread to the JIT  or change the domain for the callback */
6096         if (method->wrapper_type == MONO_WRAPPER_NATIVE_TO_MANAGED) {
6097                 guint64 domain = (guint64)cfg->domain;
6098
6099                 args_clobbered = TRUE;
6100
6101                 /*
6102                  * The call might clobber argument registers, but they are already
6103                  * saved to the stack/global regs.
6104                  */
6105                 if (appdomain_tls_offset != -1 && lmf_tls_offset != -1) {
6106                         guint8 *buf, *no_domain_branch;
6107
6108                         code = mono_amd64_emit_tls_get (code, AMD64_RAX, appdomain_tls_offset);
6109                         if (cfg->compile_aot) {
6110                                 /* AOT code is only used in the root domain */
6111                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6112                         } else {
6113                                 if ((domain >> 32) == 0)
6114                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6115                                 else
6116                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6117                         }
6118                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RAX, AMD64_ARG_REG1);
6119                         no_domain_branch = code;
6120                         x86_branch8 (code, X86_CC_NE, 0, 0);
6121                         code = mono_amd64_emit_tls_get ( code, AMD64_RAX, lmf_addr_tls_offset);
6122                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
6123                         buf = code;
6124                         x86_branch8 (code, X86_CC_NE, 0, 0);
6125                         amd64_patch (no_domain_branch, code);
6126                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6127                                           (gpointer)"mono_jit_thread_attach", TRUE);
6128                         amd64_patch (buf, code);
6129 #ifdef HOST_WIN32
6130                         /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6131                         /* FIXME: Add a separate key for LMF to avoid this */
6132                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6133 #endif
6134                 } else {
6135                         g_assert (!cfg->compile_aot);
6136                         if (cfg->compile_aot) {
6137                                 /* AOT code is only used in the root domain */
6138                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, 0);
6139                         } else {
6140                                 if ((domain >> 32) == 0)
6141                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 4);
6142                                 else
6143                                         amd64_mov_reg_imm_size (code, AMD64_ARG_REG1, domain, 8);
6144                         }
6145                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6146                                           (gpointer)"mono_jit_thread_attach", TRUE);
6147                 }
6148         }
6149
6150         if (method->save_lmf) {
6151                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6152                         /*
6153                          * Optimized version which uses the mono_lmf TLS variable instead of
6154                          * indirection through the mono_lmf_addr TLS variable.
6155                          */
6156                         /* %rax = previous_lmf */
6157                         x86_prefix (code, X86_FS_PREFIX);
6158                         amd64_mov_reg_mem (code, AMD64_RAX, lmf_tls_offset, 8);
6159
6160                         /* Save previous_lmf */
6161                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_RAX, 8);
6162                         /* Set new lmf */
6163                         if (lmf_offset == 0) {
6164                                 x86_prefix (code, X86_FS_PREFIX);
6165                                 amd64_mov_mem_reg (code, lmf_tls_offset, cfg->frame_reg, 8);
6166                         } else {
6167                                 amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6168                                 x86_prefix (code, X86_FS_PREFIX);
6169                                 amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6170                         }
6171                 } else {
6172                         if (lmf_addr_tls_offset != -1) {
6173                                 /* Load lmf quicky using the FS register */
6174                                 code = mono_amd64_emit_tls_get (code, AMD64_RAX, lmf_addr_tls_offset);
6175 #ifdef HOST_WIN32
6176                                 /* The TLS key actually contains a pointer to the MonoJitTlsData structure */
6177                                 /* FIXME: Add a separate key for LMF to avoid this */
6178                                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RAX, G_STRUCT_OFFSET (MonoJitTlsData, lmf));
6179 #endif
6180                         }
6181                         else {
6182                                 /*
6183                                  * The call might clobber argument registers, but they are already
6184                                  * saved to the stack/global regs.
6185                                  */
6186                                 args_clobbered = TRUE;
6187                                 code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
6188                                                                   (gpointer)"mono_get_lmf_addr", TRUE);
6189                         }
6190
6191                         /* Save lmf_addr */
6192                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), AMD64_RAX, 8);
6193                         /* Save previous_lmf */
6194                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RAX, 0, 8);
6195                         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), AMD64_R11, 8);
6196                         /* Set new lmf */
6197                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset);
6198                         amd64_mov_membase_reg (code, AMD64_RAX, 0, AMD64_R11, 8);
6199                 }
6200         }
6201
6202         if (trace) {
6203                 args_clobbered = TRUE;
6204                 code = mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
6205         }
6206
6207         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6208                 args_clobbered = TRUE;
6209
6210         /*
6211          * Optimize the common case of the first bblock making a call with the same
6212          * arguments as the method. This works because the arguments are still in their
6213          * original argument registers.
6214          * FIXME: Generalize this
6215          */
6216         if (!args_clobbered) {
6217                 MonoBasicBlock *first_bb = cfg->bb_entry;
6218                 MonoInst *next;
6219
6220                 next = mono_bb_first_ins (first_bb);
6221                 if (!next && first_bb->next_bb) {
6222                         first_bb = first_bb->next_bb;
6223                         next = mono_bb_first_ins (first_bb);
6224                 }
6225
6226                 if (first_bb->in_count > 1)
6227                         next = NULL;
6228
6229                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
6230                         ArgInfo *ainfo = cinfo->args + i;
6231                         gboolean match = FALSE;
6232
6233                         ins = cfg->args [i];
6234                         if (ins->opcode != OP_REGVAR) {
6235                                 switch (ainfo->storage) {
6236                                 case ArgInIReg: {
6237                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
6238                                                 if (next->dreg == ainfo->reg) {
6239                                                         NULLIFY_INS (next);
6240                                                         match = TRUE;
6241                                                 } else {
6242                                                         next->opcode = OP_MOVE;
6243                                                         next->sreg1 = ainfo->reg;
6244                                                         /* Only continue if the instruction doesn't change argument regs */
6245                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
6246                                                                 match = TRUE;
6247                                                 }
6248                                         }
6249                                         break;
6250                                 }
6251                                 default:
6252                                         break;
6253                                 }
6254                         } else {
6255                                 /* Argument allocated to (non-volatile) register */
6256                                 switch (ainfo->storage) {
6257                                 case ArgInIReg:
6258                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
6259                                                 NULLIFY_INS (next);
6260                                                 match = TRUE;
6261                                         }
6262                                         break;
6263                                 default:
6264                                         break;
6265                                 }
6266                         }
6267
6268                         if (match) {
6269                                 next = next->next;
6270                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
6271                                 if (!next)
6272                                         break;
6273                         }
6274                 }
6275         }
6276
6277         /* Initialize ss_trigger_page_var */
6278         if (cfg->arch.ss_trigger_page_var) {
6279                 MonoInst *var = cfg->arch.ss_trigger_page_var;
6280
6281                 g_assert (!cfg->compile_aot);
6282                 g_assert (var->opcode == OP_REGOFFSET);
6283
6284                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)ss_trigger_page);
6285                 amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
6286         }
6287
6288         cfg->code_len = code - cfg->native_code;
6289
6290         g_assert (cfg->code_len < cfg->code_size);
6291
6292         return code;
6293 }
6294
6295 void
6296 mono_arch_emit_epilog (MonoCompile *cfg)
6297 {
6298         MonoMethod *method = cfg->method;
6299         int quad, pos, i;
6300         guint8 *code;
6301         int max_epilog_size;
6302         CallInfo *cinfo;
6303         gint32 lmf_offset = cfg->arch.lmf_offset;
6304
6305         max_epilog_size = get_max_epilog_size (cfg);
6306
6307         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
6308                 cfg->code_size *= 2;
6309                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6310                 mono_jit_stats.code_reallocs++;
6311         }
6312
6313         code = cfg->native_code + cfg->code_len;
6314
6315         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6316                 code = mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
6317
6318         /* the code restoring the registers must be kept in sync with OP_JMP */
6319         pos = 0;
6320
6321         if (method->save_lmf) {
6322                 /* check if we need to restore protection of the stack after a stack overflow */
6323                 if (mono_get_jit_tls_offset () != -1) {
6324                         guint8 *patch;
6325                         code = mono_amd64_emit_tls_get (code, X86_ECX, mono_get_jit_tls_offset ());
6326                         /* we load the value in a separate instruction: this mechanism may be
6327                          * used later as a safer way to do thread interruption
6328                          */
6329                         amd64_mov_reg_membase (code, X86_ECX, X86_ECX, G_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
6330                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
6331                         patch = code;
6332                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
6333                         /* note that the call trampoline will preserve eax/edx */
6334                         x86_call_reg (code, X86_ECX);
6335                         x86_patch (patch, code);
6336                 } else {
6337                         /* FIXME: maybe save the jit tls in the prolog */
6338                 }
6339                 if ((lmf_tls_offset != -1) && !optimize_for_xen) {
6340                         /*
6341                          * Optimized version which uses the mono_lmf TLS variable instead of indirection
6342                          * through the mono_lmf_addr TLS variable.
6343                          */
6344                         /* reg = previous_lmf */
6345                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6346                         x86_prefix (code, X86_FS_PREFIX);
6347                         amd64_mov_mem_reg (code, lmf_tls_offset, AMD64_R11, 8);
6348                 } else {
6349                         /* Restore previous lmf */
6350                         amd64_mov_reg_membase (code, AMD64_RCX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, previous_lmf), 8);
6351                         amd64_mov_reg_membase (code, AMD64_R11, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, lmf_addr), 8);
6352                         amd64_mov_membase_reg (code, AMD64_R11, 0, AMD64_RCX, 8);
6353                 }
6354
6355                 /* Restore caller saved regs */
6356                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
6357                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbp), 8);
6358                 }
6359                 if (cfg->used_int_regs & (1 << AMD64_RBX)) {
6360                         amd64_mov_reg_membase (code, AMD64_RBX, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rbx), 8);
6361                 }
6362                 if (cfg->used_int_regs & (1 << AMD64_R12)) {
6363                         amd64_mov_reg_membase (code, AMD64_R12, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r12), 8);
6364                 }
6365                 if (cfg->used_int_regs & (1 << AMD64_R13)) {
6366                         amd64_mov_reg_membase (code, AMD64_R13, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r13), 8);
6367                 }
6368                 if (cfg->used_int_regs & (1 << AMD64_R14)) {
6369                         amd64_mov_reg_membase (code, AMD64_R14, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r14), 8);
6370                 }
6371                 if (cfg->used_int_regs & (1 << AMD64_R15)) {
6372                         amd64_mov_reg_membase (code, AMD64_R15, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, r15), 8);
6373                 }
6374 #ifdef HOST_WIN32
6375                 if (cfg->used_int_regs & (1 << AMD64_RDI)) {
6376                         amd64_mov_reg_membase (code, AMD64_RDI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rdi), 8);
6377                 }
6378                 if (cfg->used_int_regs & (1 << AMD64_RSI)) {
6379                         amd64_mov_reg_membase (code, AMD64_RSI, cfg->frame_reg, lmf_offset + G_STRUCT_OFFSET (MonoLMF, rsi), 8);
6380                 }
6381 #endif
6382         } else {
6383
6384                 if (cfg->arch.omit_fp) {
6385                         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
6386
6387                         for (i = 0; i < AMD64_NREG; ++i)
6388                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6389                                         amd64_mov_reg_membase (code, i, AMD64_RSP, save_area_offset, 8);
6390                                         save_area_offset += 8;
6391                                 }
6392                 }
6393                 else {
6394                         for (i = 0; i < AMD64_NREG; ++i)
6395                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i)))
6396                                         pos -= sizeof (gpointer);
6397
6398                         if (pos) {
6399                                 if (pos == - sizeof (gpointer)) {
6400                                         /* Only one register, so avoid lea */
6401                                         for (i = AMD64_NREG - 1; i > 0; --i)
6402                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6403                                                         amd64_mov_reg_membase (code, i, AMD64_RBP, pos, 8);
6404                                                 }
6405                                 }
6406                                 else {
6407                                         amd64_lea_membase (code, AMD64_RSP, AMD64_RBP, pos);
6408
6409                                         /* Pop registers in reverse order */
6410                                         for (i = AMD64_NREG - 1; i > 0; --i)
6411                                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
6412                                                         amd64_pop_reg (code, i);
6413                                                 }
6414                                 }
6415                         }
6416                 }
6417         }
6418
6419         /* Load returned vtypes into registers if needed */
6420         cinfo = cfg->arch.cinfo;
6421         if (cinfo->ret.storage == ArgValuetypeInReg) {
6422                 ArgInfo *ainfo = &cinfo->ret;
6423                 MonoInst *inst = cfg->ret;
6424
6425                 for (quad = 0; quad < 2; quad ++) {
6426                         switch (ainfo->pair_storage [quad]) {
6427                         case ArgInIReg:
6428                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)), sizeof (gpointer));
6429                                 break;
6430                         case ArgInFloatSSEReg:
6431                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6432                                 break;
6433                         case ArgInDoubleSSEReg:
6434                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof (gpointer)));
6435                                 break;
6436                         case ArgNone:
6437                                 break;
6438                         default:
6439                                 g_assert_not_reached ();
6440                         }
6441                 }
6442         }
6443
6444         if (cfg->arch.omit_fp) {
6445                 if (cfg->arch.stack_alloc_size)
6446                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
6447         } else {
6448                 amd64_leave (code);
6449         }
6450         async_exc_point (code);
6451         amd64_ret (code);
6452
6453         cfg->code_len = code - cfg->native_code;
6454
6455         g_assert (cfg->code_len < cfg->code_size);
6456 }
6457
6458 void
6459 mono_arch_emit_exceptions (MonoCompile *cfg)
6460 {
6461         MonoJumpInfo *patch_info;
6462         int nthrows, i;
6463         guint8 *code;
6464         MonoClass *exc_classes [16];
6465         guint8 *exc_throw_start [16], *exc_throw_end [16];
6466         guint32 code_size = 0;
6467
6468         /* Compute needed space */
6469         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6470                 if (patch_info->type == MONO_PATCH_INFO_EXC)
6471                         code_size += 40;
6472                 if (patch_info->type == MONO_PATCH_INFO_R8)
6473                         code_size += 8 + 15; /* sizeof (double) + alignment */
6474                 if (patch_info->type == MONO_PATCH_INFO_R4)
6475                         code_size += 4 + 15; /* sizeof (float) + alignment */
6476         }
6477
6478         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
6479                 cfg->code_size *= 2;
6480                 cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
6481                 mono_jit_stats.code_reallocs++;
6482         }
6483
6484         code = cfg->native_code + cfg->code_len;
6485
6486         /* add code to raise exceptions */
6487         nthrows = 0;
6488         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6489                 switch (patch_info->type) {
6490                 case MONO_PATCH_INFO_EXC: {
6491                         MonoClass *exc_class;
6492                         guint8 *buf, *buf2;
6493                         guint32 throw_ip;
6494
6495                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
6496
6497                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
6498                         g_assert (exc_class);
6499                         throw_ip = patch_info->ip.i;
6500
6501                         //x86_breakpoint (code);
6502                         /* Find a throw sequence for the same exception class */
6503                         for (i = 0; i < nthrows; ++i)
6504                                 if (exc_classes [i] == exc_class)
6505                                         break;
6506                         if (i < nthrows) {
6507                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
6508                                 x86_jump_code (code, exc_throw_start [i]);
6509                                 patch_info->type = MONO_PATCH_INFO_NONE;
6510                         }
6511                         else {
6512                                 buf = code;
6513                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
6514                                 buf2 = code;
6515
6516                                 if (nthrows < 16) {
6517                                         exc_classes [nthrows] = exc_class;
6518                                         exc_throw_start [nthrows] = code;
6519                                 }
6520                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
6521
6522                                 patch_info->type = MONO_PATCH_INFO_NONE;
6523
6524                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
6525
6526                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
6527                                 while (buf < buf2)
6528                                         x86_nop (buf);
6529
6530                                 if (nthrows < 16) {
6531                                         exc_throw_end [nthrows] = code;
6532                                         nthrows ++;
6533                                 }
6534                         }
6535                         break;
6536                 }
6537                 default:
6538                         /* do nothing */
6539                         break;
6540                 }
6541         }
6542
6543         /* Handle relocations with RIP relative addressing */
6544         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
6545                 gboolean remove = FALSE;
6546
6547                 switch (patch_info->type) {
6548                 case MONO_PATCH_INFO_R8:
6549                 case MONO_PATCH_INFO_R4: {
6550                         guint8 *pos;
6551
6552                         /* The SSE opcodes require a 16 byte alignment */
6553                         code = (guint8*)ALIGN_TO (code, 16);
6554
6555                         pos = cfg->native_code + patch_info->ip.i;
6556
6557                         if (IS_REX (pos [1]))
6558                                 *(guint32*)(pos + 5) = (guint8*)code - pos - 9;
6559                         else
6560                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
6561
6562                         if (patch_info->type == MONO_PATCH_INFO_R8) {
6563                                 *(double*)code = *(double*)patch_info->data.target;
6564                                 code += sizeof (double);
6565                         } else {
6566                                 *(float*)code = *(float*)patch_info->data.target;
6567                                 code += sizeof (float);
6568                         }
6569
6570                         remove = TRUE;
6571                         break;
6572                 }
6573                 default:
6574                         break;
6575                 }
6576
6577                 if (remove) {
6578                         if (patch_info == cfg->patch_info)
6579                                 cfg->patch_info = patch_info->next;
6580                         else {
6581                                 MonoJumpInfo *tmp;
6582
6583                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
6584                                         ;
6585                                 tmp->next = patch_info->next;
6586                         }
6587                 }
6588         }
6589
6590         cfg->code_len = code - cfg->native_code;
6591
6592         g_assert (cfg->code_len < cfg->code_size);
6593
6594 }
6595
6596 #endif /* DISABLE_JIT */
6597
6598 void*
6599 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
6600 {
6601         guchar *code = p;
6602         CallInfo *cinfo = NULL;
6603         MonoMethodSignature *sig;
6604         MonoInst *inst;
6605         int i, n, stack_area = 0;
6606
6607         /* Keep this in sync with mono_arch_get_argument_info */
6608
6609         if (enable_arguments) {
6610                 /* Allocate a new area on the stack and save arguments there */
6611                 sig = mono_method_signature (cfg->method);
6612
6613                 cinfo = get_call_info (cfg->generic_sharing_context, cfg->mempool, sig, FALSE);
6614
6615                 n = sig->param_count + sig->hasthis;
6616
6617                 stack_area = ALIGN_TO (n * 8, 16);
6618
6619                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
6620
6621                 for (i = 0; i < n; ++i) {
6622                         inst = cfg->args [i];
6623
6624                         if (inst->opcode == OP_REGVAR)
6625                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
6626                         else {
6627                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
6628                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
6629                         }
6630                 }
6631         }
6632
6633         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
6634         amd64_set_reg_template (code, AMD64_ARG_REG1);
6635         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
6636         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6637
6638         if (enable_arguments)
6639                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
6640
6641         return code;
6642 }
6643
6644 enum {
6645         SAVE_NONE,
6646         SAVE_STRUCT,
6647         SAVE_EAX,
6648         SAVE_EAX_EDX,
6649         SAVE_XMM
6650 };
6651
6652 void*
6653 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
6654 {
6655         guchar *code = p;
6656         int save_mode = SAVE_NONE;
6657         MonoMethod *method = cfg->method;
6658         MonoType *ret_type = mini_type_get_underlying_type (NULL, mono_method_signature (method)->ret);
6659
6660         switch (ret_type->type) {
6661         case MONO_TYPE_VOID:
6662                 /* special case string .ctor icall */
6663                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
6664                         save_mode = SAVE_EAX;
6665                 else
6666                         save_mode = SAVE_NONE;
6667                 break;
6668         case MONO_TYPE_I8:
6669         case MONO_TYPE_U8:
6670                 save_mode = SAVE_EAX;
6671                 break;
6672         case MONO_TYPE_R4:
6673         case MONO_TYPE_R8:
6674                 save_mode = SAVE_XMM;
6675                 break;
6676         case MONO_TYPE_GENERICINST:
6677                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
6678                         save_mode = SAVE_EAX;
6679                         break;
6680                 }
6681                 /* Fall through */
6682         case MONO_TYPE_VALUETYPE:
6683                 save_mode = SAVE_STRUCT;
6684                 break;
6685         default:
6686                 save_mode = SAVE_EAX;
6687                 break;
6688         }
6689
6690         /* Save the result and copy it into the proper argument register */
6691         switch (save_mode) {
6692         case SAVE_EAX:
6693                 amd64_push_reg (code, AMD64_RAX);
6694                 /* Align stack */
6695                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6696                 if (enable_arguments)
6697                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
6698                 break;
6699         case SAVE_STRUCT:
6700                 /* FIXME: */
6701                 if (enable_arguments)
6702                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
6703                 break;
6704         case SAVE_XMM:
6705                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6706                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
6707                 /* Align stack */
6708                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
6709                 /*
6710                  * The result is already in the proper argument register so no copying
6711                  * needed.
6712                  */
6713                 break;
6714         case SAVE_NONE:
6715                 break;
6716         default:
6717                 g_assert_not_reached ();
6718         }
6719
6720         /* Set %al since this is a varargs call */
6721         if (save_mode == SAVE_XMM)
6722                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
6723         else
6724                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
6725
6726         if (preserve_argument_registers) {
6727                 amd64_push_reg (code, MONO_AMD64_ARG_REG1);
6728                 amd64_push_reg (code, MONO_AMD64_ARG_REG2);
6729         }
6730
6731         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
6732         amd64_set_reg_template (code, AMD64_ARG_REG1);
6733         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
6734
6735         if (preserve_argument_registers) {
6736                 amd64_pop_reg (code, MONO_AMD64_ARG_REG2);
6737                 amd64_pop_reg (code, MONO_AMD64_ARG_REG1);
6738         }
6739
6740         /* Restore result */
6741         switch (save_mode) {
6742         case SAVE_EAX:
6743                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6744                 amd64_pop_reg (code, AMD64_RAX);
6745                 break;
6746         case SAVE_STRUCT:
6747                 /* FIXME: */
6748                 break;
6749         case SAVE_XMM:
6750                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6751                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
6752                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
6753                 break;
6754         case SAVE_NONE:
6755                 break;
6756         default:
6757                 g_assert_not_reached ();
6758         }
6759
6760         return code;
6761 }
6762
6763 void
6764 mono_arch_flush_icache (guint8 *code, gint size)
6765 {
6766         /* Not needed */
6767 }
6768
6769 void
6770 mono_arch_flush_register_windows (void)
6771 {
6772 }
6773
6774 gboolean
6775 mono_arch_is_inst_imm (gint64 imm)
6776 {
6777         return amd64_is_imm32 (imm);
6778 }
6779
6780 /*
6781  * Determine whenever the trap whose info is in SIGINFO is caused by
6782  * integer overflow.
6783  */
6784 gboolean
6785 mono_arch_is_int_overflow (void *sigctx, void *info)
6786 {
6787         MonoContext ctx;
6788         guint8* rip;
6789         int reg;
6790         gint64 value;
6791
6792         mono_arch_sigctx_to_monoctx (sigctx, &ctx);
6793
6794         rip = (guint8*)ctx.rip;
6795
6796         if (IS_REX (rip [0])) {
6797                 reg = amd64_rex_b (rip [0]);
6798                 rip ++;
6799         }
6800         else
6801                 reg = 0;
6802
6803         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
6804                 /* idiv REG */
6805                 reg += x86_modrm_rm (rip [1]);
6806
6807                 switch (reg) {
6808                 case AMD64_RAX:
6809                         value = ctx.rax;
6810                         break;
6811                 case AMD64_RBX:
6812                         value = ctx.rbx;
6813                         break;
6814                 case AMD64_RCX:
6815                         value = ctx.rcx;
6816                         break;
6817                 case AMD64_RDX:
6818                         value = ctx.rdx;
6819                         break;
6820                 case AMD64_RBP:
6821                         value = ctx.rbp;
6822                         break;
6823                 case AMD64_RSP:
6824                         value = ctx.rsp;
6825                         break;
6826                 case AMD64_RSI:
6827                         value = ctx.rsi;
6828                         break;
6829                 case AMD64_RDI:
6830                         value = ctx.rdi;
6831                         break;
6832                 case AMD64_R12:
6833                         value = ctx.r12;
6834                         break;
6835                 case AMD64_R13:
6836                         value = ctx.r13;
6837                         break;
6838                 case AMD64_R14:
6839                         value = ctx.r14;
6840                         break;
6841                 case AMD64_R15:
6842                         value = ctx.r15;
6843                         break;
6844                 default:
6845                         g_assert_not_reached ();
6846                         reg = -1;
6847                 }
6848
6849                 if (value == -1)
6850                         return TRUE;
6851         }
6852
6853         return FALSE;
6854 }
6855
6856 guint32
6857 mono_arch_get_patch_offset (guint8 *code)
6858 {
6859         return 3;
6860 }
6861
6862 /**
6863  * mono_breakpoint_clean_code:
6864  *
6865  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
6866  * breakpoints in the original code, they are removed in the copy.
6867  *
6868  * Returns TRUE if no sw breakpoint was present.
6869  */
6870 gboolean
6871 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
6872 {
6873         int i;
6874         gboolean can_write = TRUE;
6875         /*
6876          * If method_start is non-NULL we need to perform bound checks, since we access memory
6877          * at code - offset we could go before the start of the method and end up in a different
6878          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
6879          * instead.
6880          */
6881         if (!method_start || code - offset >= method_start) {
6882                 memcpy (buf, code - offset, size);
6883         } else {
6884                 int diff = code - method_start;
6885                 memset (buf, 0, size);
6886                 memcpy (buf + offset - diff, method_start, diff + size - offset);
6887         }
6888         code -= offset;
6889         for (i = 0; i < MONO_BREAKPOINT_ARRAY_SIZE; ++i) {
6890                 int idx = mono_breakpoint_info_index [i];
6891                 guint8 *ptr;
6892                 if (idx < 1)
6893                         continue;
6894                 ptr = mono_breakpoint_info [idx].address;
6895                 if (ptr >= code && ptr < code + size) {
6896                         guint8 saved_byte = mono_breakpoint_info [idx].saved_byte;
6897                         can_write = FALSE;
6898                         /*g_print ("patching %p with 0x%02x (was: 0x%02x)\n", ptr, saved_byte, buf [ptr - code]);*/
6899                         buf [ptr - code] = saved_byte;
6900                 }
6901         }
6902         return can_write;
6903 }
6904
6905 gpointer
6906 mono_arch_get_vcall_slot (guint8 *code, mgreg_t *regs, int *displacement)
6907 {
6908         guint8 buf [10];
6909         gint32 disp;
6910         MonoJitInfo *ji = NULL;
6911
6912 #ifdef ENABLE_LLVM
6913         /* code - 9 might be before the start of the method */
6914         /* FIXME: Avoid this expensive call somehow */
6915         ji = mono_jit_info_table_find (mono_domain_get (), (char*)code);
6916 #endif
6917
6918         mono_breakpoint_clean_code (ji ? ji->code_start : NULL, code, 9, buf, sizeof (buf));
6919         code = buf + 9;
6920
6921         *displacement = 0;
6922
6923         code -= 7;
6924
6925         /*
6926          * This function is no longer used, the only caller is
6927          * mono_arch_nullify_class_init_trampoline ().
6928          */
6929         if ((code [0] == 0x41) && (code [1] == 0xff) && (code [2] == 0x15)) {
6930                 /* call OFFSET(%rip) */
6931                 g_assert_not_reached ();
6932                 *displacement = *(guint32*)(code + 3);
6933                 return (gpointer*)(code + disp + 7);
6934         } else {
6935                 g_assert_not_reached ();
6936                 return NULL;
6937         }
6938 }
6939
6940 int
6941 mono_arch_get_this_arg_reg (MonoMethodSignature *sig, MonoGenericSharingContext *gsctx, guint8 *code)
6942 {
6943         return AMD64_ARG_REG1;
6944 }
6945
6946 gpointer
6947 mono_arch_get_this_arg_from_call (MonoGenericSharingContext *gsctx, MonoMethodSignature *sig, mgreg_t *regs, guint8 *code)
6948 {
6949         return (gpointer)regs [mono_arch_get_this_arg_reg (sig, gsctx, code)];
6950 }
6951
6952 #define MAX_ARCH_DELEGATE_PARAMS 10
6953
6954 static gpointer
6955 get_delegate_invoke_impl (gboolean has_target, guint32 param_count, guint32 *code_len)
6956 {
6957         guint8 *code, *start;
6958         int i;
6959
6960         if (has_target) {
6961                 start = code = mono_global_codeman_reserve (64);
6962
6963                 /* Replace the this argument with the target */
6964                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6965                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, target), 8);
6966                 amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6967
6968                 g_assert ((code - start) < 64);
6969         } else {
6970                 start = code = mono_global_codeman_reserve (64);
6971
6972                 if (param_count == 0) {
6973                         amd64_jump_membase (code, AMD64_ARG_REG1, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6974                 } else {
6975                         /* We have to shift the arguments left */
6976                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
6977                         for (i = 0; i < param_count; ++i) {
6978 #ifdef HOST_WIN32
6979                                 if (i < 3)
6980                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6981                                 else
6982                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
6983 #else
6984                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
6985 #endif
6986                         }
6987
6988                         amd64_jump_membase (code, AMD64_RAX, G_STRUCT_OFFSET (MonoDelegate, method_ptr));
6989                 }
6990                 g_assert ((code - start) < 64);
6991         }
6992
6993         mono_debug_add_delegate_trampoline (start, code - start);
6994
6995         if (code_len)
6996                 *code_len = code - start;
6997
6998         return start;
6999 }
7000
7001 /*
7002  * mono_arch_get_delegate_invoke_impls:
7003  *
7004  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
7005  * trampolines.
7006  */
7007 GSList*
7008 mono_arch_get_delegate_invoke_impls (void)
7009 {
7010         GSList *res = NULL;
7011         guint8 *code;
7012         guint32 code_len;
7013         int i;
7014
7015         code = get_delegate_invoke_impl (TRUE, 0, &code_len);
7016         res = g_slist_prepend (res, mono_tramp_info_create (g_strdup ("delegate_invoke_impl_has_target"), code, code_len, NULL, NULL));
7017
7018         for (i = 0; i < MAX_ARCH_DELEGATE_PARAMS; ++i) {
7019                 code = get_delegate_invoke_impl (FALSE, i, &code_len);
7020                 res = g_slist_prepend (res, mono_tramp_info_create (g_strdup_printf ("delegate_invoke_impl_target_%d", i), code, code_len, NULL, NULL));
7021         }
7022
7023         return res;
7024 }
7025
7026 gpointer
7027 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
7028 {
7029         guint8 *code, *start;
7030         int i;
7031
7032         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
7033                 return NULL;
7034
7035         /* FIXME: Support more cases */
7036         if (MONO_TYPE_ISSTRUCT (sig->ret))
7037                 return NULL;
7038
7039         if (has_target) {
7040                 static guint8* cached = NULL;
7041
7042                 if (cached)
7043                         return cached;
7044
7045                 if (mono_aot_only)
7046                         start = mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
7047                 else
7048                         start = get_delegate_invoke_impl (TRUE, 0, NULL);
7049
7050                 mono_memory_barrier ();
7051
7052                 cached = start;
7053         } else {
7054                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
7055                 for (i = 0; i < sig->param_count; ++i)
7056                         if (!mono_is_regsize_var (sig->params [i]))
7057                                 return NULL;
7058                 if (sig->param_count > 4)
7059                         return NULL;
7060
7061                 code = cache [sig->param_count];
7062                 if (code)
7063                         return code;
7064
7065                 if (mono_aot_only) {
7066                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
7067                         start = mono_aot_get_trampoline (name);
7068                         g_free (name);
7069                 } else {
7070                         start = get_delegate_invoke_impl (FALSE, sig->param_count, NULL);
7071                 }
7072
7073                 mono_memory_barrier ();
7074
7075                 cache [sig->param_count] = start;
7076         }
7077
7078         return start;
7079 }
7080
7081 /*
7082  * Support for fast access to the thread-local lmf structure using the GS
7083  * segment register on NPTL + kernel 2.6.x.
7084  */
7085
7086 static gboolean tls_offset_inited = FALSE;
7087
7088 void
7089 mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
7090 {
7091         if (!tls_offset_inited) {
7092 #ifdef HOST_WIN32
7093                 /*
7094                  * We need to init this multiple times, since when we are first called, the key might not
7095                  * be initialized yet.
7096                  */
7097                 appdomain_tls_offset = mono_domain_get_tls_key ();
7098                 lmf_tls_offset = mono_get_jit_tls_key ();
7099                 lmf_addr_tls_offset = mono_get_jit_tls_key ();
7100
7101                 /* Only 64 tls entries can be accessed using inline code */
7102                 if (appdomain_tls_offset >= 64)
7103                         appdomain_tls_offset = -1;
7104                 if (lmf_tls_offset >= 64)
7105                         lmf_tls_offset = -1;
7106 #else
7107                 tls_offset_inited = TRUE;
7108 #ifdef MONO_XEN_OPT
7109                 optimize_for_xen = access ("/proc/xen", F_OK) == 0;
7110 #endif
7111                 appdomain_tls_offset = mono_domain_get_tls_offset ();
7112                 lmf_tls_offset = mono_get_lmf_tls_offset ();
7113                 lmf_addr_tls_offset = mono_get_lmf_addr_tls_offset ();
7114 #endif
7115         }
7116 }
7117
7118 void
7119 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
7120 {
7121 }
7122
7123 #ifdef MONO_ARCH_HAVE_IMT
7124
7125 #define CMP_SIZE (6 + 1)
7126 #define CMP_REG_REG_SIZE (4 + 1)
7127 #define BR_SMALL_SIZE 2
7128 #define BR_LARGE_SIZE 6
7129 #define MOV_REG_IMM_SIZE 10
7130 #define MOV_REG_IMM_32BIT_SIZE 6
7131 #define JUMP_REG_SIZE (2 + 1)
7132
7133 static int
7134 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
7135 {
7136         int i, distance = 0;
7137         for (i = start; i < target; ++i)
7138                 distance += imt_entries [i]->chunk_size;
7139         return distance;
7140 }
7141
7142 /*
7143  * LOCKING: called with the domain lock held
7144  */
7145 gpointer
7146 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
7147         gpointer fail_tramp)
7148 {
7149         int i;
7150         int size = 0;
7151         guint8 *code, *start;
7152         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
7153
7154         for (i = 0; i < count; ++i) {
7155                 MonoIMTCheckItem *item = imt_entries [i];
7156                 if (item->is_equals) {
7157                         if (item->check_target_idx) {
7158                                 if (!item->compare_done) {
7159                                         if (amd64_is_imm32 (item->key))
7160                                                 item->chunk_size += CMP_SIZE;
7161                                         else
7162                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7163                                 }
7164                                 if (item->has_target_code) {
7165                                         item->chunk_size += MOV_REG_IMM_SIZE;
7166                                 } else {
7167                                         if (vtable_is_32bit)
7168                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7169                                         else
7170                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7171                                 }
7172                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
7173                         } else {
7174                                 if (fail_tramp) {
7175                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
7176                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
7177                                 } else {
7178                                         if (vtable_is_32bit)
7179                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
7180                                         else
7181                                                 item->chunk_size += MOV_REG_IMM_SIZE;
7182                                         item->chunk_size += JUMP_REG_SIZE;
7183                                         /* with assert below:
7184                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
7185                                          */
7186                                 }
7187                         }
7188                 } else {
7189                         if (amd64_is_imm32 (item->key))
7190                                 item->chunk_size += CMP_SIZE;
7191                         else
7192                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
7193                         item->chunk_size += BR_LARGE_SIZE;
7194                         imt_entries [item->check_target_idx]->compare_done = TRUE;
7195                 }
7196                 size += item->chunk_size;
7197         }
7198         if (fail_tramp)
7199                 code = mono_method_alloc_generic_virtual_thunk (domain, size);
7200         else
7201                 code = mono_domain_code_reserve (domain, size);
7202         start = code;
7203         for (i = 0; i < count; ++i) {
7204                 MonoIMTCheckItem *item = imt_entries [i];
7205                 item->code_target = code;
7206                 if (item->is_equals) {
7207                         gboolean fail_case = !item->check_target_idx && fail_tramp;
7208
7209                         if (item->check_target_idx || fail_case) {
7210                                 if (!item->compare_done || fail_case) {
7211                                         if (amd64_is_imm32 (item->key))
7212                                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7213                                         else {
7214                                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7215                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7216                                         }
7217                                 }
7218                                 item->jmp_code = code;
7219                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7220                                 if (item->has_target_code) {
7221                                         amd64_mov_reg_imm (code, AMD64_R11, item->value.target_code);
7222                                         amd64_jump_reg (code, AMD64_R11);
7223                                 } else {
7224                                         amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7225                                         amd64_jump_membase (code, AMD64_R11, 0);
7226                                 }
7227
7228                                 if (fail_case) {
7229                                         amd64_patch (item->jmp_code, code);
7230                                         amd64_mov_reg_imm (code, AMD64_R11, fail_tramp);
7231                                         amd64_jump_reg (code, AMD64_R11);
7232                                         item->jmp_code = NULL;
7233                                 }
7234                         } else {
7235                                 /* enable the commented code to assert on wrong method */
7236 #if 0
7237                                 if (amd64_is_imm32 (item->key))
7238                                         amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7239                                 else {
7240                                         amd64_mov_reg_imm (code, AMD64_R11, item->key);
7241                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7242                                 }
7243                                 item->jmp_code = code;
7244                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
7245                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7246                                 amd64_jump_membase (code, AMD64_R11, 0);
7247                                 amd64_patch (item->jmp_code, code);
7248                                 amd64_breakpoint (code);
7249                                 item->jmp_code = NULL;
7250 #else
7251                                 amd64_mov_reg_imm (code, AMD64_R11, & (vtable->vtable [item->value.vtable_slot]));
7252                                 amd64_jump_membase (code, AMD64_R11, 0);
7253 #endif
7254                         }
7255                 } else {
7256                         if (amd64_is_imm32 (item->key))
7257                                 amd64_alu_reg_imm (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key);
7258                         else {
7259                                 amd64_mov_reg_imm (code, AMD64_R11, item->key);
7260                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, AMD64_R11);
7261                         }
7262                         item->jmp_code = code;
7263                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
7264                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
7265                         else
7266                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
7267                 }
7268                 g_assert (code - item->code_target <= item->chunk_size);
7269         }
7270         /* patch the branches to get to the target items */
7271         for (i = 0; i < count; ++i) {
7272                 MonoIMTCheckItem *item = imt_entries [i];
7273                 if (item->jmp_code) {
7274                         if (item->check_target_idx) {
7275                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
7276                         }
7277                 }
7278         }
7279
7280         if (!fail_tramp)
7281                 mono_stats.imt_thunks_size += code - start;
7282         g_assert (code - start <= size);
7283
7284         return start;
7285 }
7286
7287 MonoMethod*
7288 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
7289 {
7290         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
7291 }
7292 #endif
7293
7294 MonoVTable*
7295 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
7296 {
7297         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
7298 }
7299
7300 GSList*
7301 mono_arch_get_cie_program (void)
7302 {
7303         GSList *l = NULL;
7304
7305         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
7306         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
7307
7308         return l;
7309 }
7310
7311 MonoInst*
7312 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
7313 {
7314         MonoInst *ins = NULL;
7315         int opcode = 0;
7316
7317         if (cmethod->klass == mono_defaults.math_class) {
7318                 if (strcmp (cmethod->name, "Sin") == 0) {
7319                         opcode = OP_SIN;
7320                 } else if (strcmp (cmethod->name, "Cos") == 0) {
7321                         opcode = OP_COS;
7322                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
7323                         opcode = OP_SQRT;
7324                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
7325                         opcode = OP_ABS;
7326                 }
7327
7328                 if (opcode) {
7329                         MONO_INST_NEW (cfg, ins, opcode);
7330                         ins->type = STACK_R8;
7331                         ins->dreg = mono_alloc_freg (cfg);
7332                         ins->sreg1 = args [0]->dreg;
7333                         MONO_ADD_INS (cfg->cbb, ins);
7334                 }
7335
7336                 opcode = 0;
7337                 if (cfg->opt & MONO_OPT_CMOV) {
7338                         if (strcmp (cmethod->name, "Min") == 0) {
7339                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7340                                         opcode = OP_IMIN;
7341                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7342                                         opcode = OP_IMIN_UN;
7343                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7344                                         opcode = OP_LMIN;
7345                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7346                                         opcode = OP_LMIN_UN;
7347                         } else if (strcmp (cmethod->name, "Max") == 0) {
7348                                 if (fsig->params [0]->type == MONO_TYPE_I4)
7349                                         opcode = OP_IMAX;
7350                                 if (fsig->params [0]->type == MONO_TYPE_U4)
7351                                         opcode = OP_IMAX_UN;
7352                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
7353                                         opcode = OP_LMAX;
7354                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
7355                                         opcode = OP_LMAX_UN;
7356                         }
7357                 }
7358
7359                 if (opcode) {
7360                         MONO_INST_NEW (cfg, ins, opcode);
7361                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
7362                         ins->dreg = mono_alloc_ireg (cfg);
7363                         ins->sreg1 = args [0]->dreg;
7364                         ins->sreg2 = args [1]->dreg;
7365                         MONO_ADD_INS (cfg->cbb, ins);
7366                 }
7367
7368 #if 0
7369                 /* OP_FREM is not IEEE compatible */
7370                 else if (strcmp (cmethod->name, "IEEERemainder") == 0) {
7371                         MONO_INST_NEW (cfg, ins, OP_FREM);
7372                         ins->inst_i0 = args [0];
7373                         ins->inst_i1 = args [1];
7374                 }
7375 #endif
7376         }
7377
7378         /*
7379          * Can't implement CompareExchange methods this way since they have
7380          * three arguments.
7381          */
7382
7383         return ins;
7384 }
7385
7386 gboolean
7387 mono_arch_print_tree (MonoInst *tree, int arity)
7388 {
7389         return 0;
7390 }
7391
7392 MonoInst* mono_arch_get_domain_intrinsic (MonoCompile* cfg)
7393 {
7394         MonoInst* ins;
7395
7396         if (appdomain_tls_offset == -1)
7397                 return NULL;
7398
7399         MONO_INST_NEW (cfg, ins, OP_TLS_GET);
7400         ins->inst_offset = appdomain_tls_offset;
7401         return ins;
7402 }
7403
7404 #define _CTX_REG(ctx,fld,i) ((gpointer)((&ctx->fld)[i]))
7405
7406 gpointer
7407 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
7408 {
7409         switch (reg) {
7410         case AMD64_RCX: return (gpointer)ctx->rcx;
7411         case AMD64_RDX: return (gpointer)ctx->rdx;
7412         case AMD64_RBX: return (gpointer)ctx->rbx;
7413         case AMD64_RBP: return (gpointer)ctx->rbp;
7414         case AMD64_RSP: return (gpointer)ctx->rsp;
7415         default:
7416                 if (reg < 8)
7417                         return _CTX_REG (ctx, rax, reg);
7418                 else if (reg >= 12)
7419                         return _CTX_REG (ctx, r12, reg - 12);
7420                 else
7421                         g_assert_not_reached ();
7422         }
7423 }
7424
7425 /*
7426  * mono_arch_emit_load_aotconst:
7427  *
7428  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
7429  * TARGET from the mscorlib GOT in full-aot code.
7430  * On AMD64, the result is placed into R11.
7431  */
7432 guint8*
7433 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, int tramp_type, gconstpointer target)
7434 {
7435         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
7436         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
7437
7438         return code;
7439 }
7440
7441 /*
7442  * mono_arch_get_trampolines:
7443  *
7444  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
7445  * for AOT.
7446  */
7447 GSList *
7448 mono_arch_get_trampolines (gboolean aot)
7449 {
7450         MonoTrampInfo *info;
7451         GSList *tramps = NULL;
7452
7453         mono_arch_get_throw_pending_exception (&info, aot);
7454
7455         tramps = g_slist_append (tramps, info);
7456
7457         return tramps;
7458 }
7459
7460 /* Soft Debug support */
7461 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
7462
7463 /*
7464  * mono_arch_set_breakpoint:
7465  *
7466  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
7467  * The location should contain code emitted by OP_SEQ_POINT.
7468  */
7469 void
7470 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
7471 {
7472         guint8 *code = ip;
7473         guint8 *orig_code = code;
7474
7475         /*
7476          * In production, we will use int3 (has to fix the size in the md
7477          * file). But that could confuse gdb, so during development, we emit a SIGSEGV
7478          * instead.
7479          */
7480         g_assert (code [0] == 0x90);
7481         if (breakpoint_size == 8) {
7482                 amd64_mov_reg_mem (code, AMD64_R11, (guint64)bp_trigger_page, 4);
7483         } else {
7484                 amd64_mov_reg_imm_size (code, AMD64_R11, (guint64)bp_trigger_page, 8);
7485                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 4);
7486         }
7487
7488         g_assert (code - orig_code == breakpoint_size);
7489 }
7490
7491 /*
7492  * mono_arch_clear_breakpoint:
7493  *
7494  *   Clear the breakpoint at IP.
7495  */
7496 void
7497 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
7498 {
7499         guint8 *code = ip;
7500         int i;
7501
7502         for (i = 0; i < breakpoint_size; ++i)
7503                 x86_nop (code);
7504 }
7505
7506 gboolean
7507 mono_arch_is_breakpoint_event (void *info, void *sigctx)
7508 {
7509 #ifdef HOST_WIN32
7510         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7511         return FALSE;
7512 #else
7513         siginfo_t* sinfo = (siginfo_t*) info;
7514         /* Sometimes the address is off by 4 */
7515         if (sinfo->si_addr >= bp_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)bp_trigger_page + 128)
7516                 return TRUE;
7517         else
7518                 return FALSE;
7519 #endif
7520 }
7521
7522 /*
7523  * mono_arch_get_ip_for_breakpoint:
7524  *
7525  *   Convert the ip in CTX to the address where a breakpoint was placed.
7526  */
7527 guint8*
7528 mono_arch_get_ip_for_breakpoint (MonoJitInfo *ji, MonoContext *ctx)
7529 {
7530         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7531
7532         /* ip points to the instruction causing the fault */
7533         ip -= (breakpoint_size - breakpoint_fault_size);
7534
7535         return ip;
7536 }
7537
7538 /*
7539  * mono_arch_skip_breakpoint:
7540  *
7541  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
7542  * we resume, the instruction is not executed again.
7543  */
7544 void
7545 mono_arch_skip_breakpoint (MonoContext *ctx)
7546 {
7547         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + breakpoint_fault_size);
7548 }
7549
7550 /*
7551  * mono_arch_start_single_stepping:
7552  *
7553  *   Start single stepping.
7554  */
7555 void
7556 mono_arch_start_single_stepping (void)
7557 {
7558         mono_mprotect (ss_trigger_page, mono_pagesize (), 0);
7559 }
7560
7561 /*
7562  * mono_arch_stop_single_stepping:
7563  *
7564  *   Stop single stepping.
7565  */
7566 void
7567 mono_arch_stop_single_stepping (void)
7568 {
7569         mono_mprotect (ss_trigger_page, mono_pagesize (), MONO_MMAP_READ);
7570 }
7571
7572 /*
7573  * mono_arch_is_single_step_event:
7574  *
7575  *   Return whenever the machine state in SIGCTX corresponds to a single
7576  * step event.
7577  */
7578 gboolean
7579 mono_arch_is_single_step_event (void *info, void *sigctx)
7580 {
7581 #ifdef HOST_WIN32
7582         EXCEPTION_RECORD* einfo = (EXCEPTION_RECORD*)info;
7583         return FALSE;
7584 #else
7585         siginfo_t* sinfo = (siginfo_t*) info;
7586         /* Sometimes the address is off by 4 */
7587         if (sinfo->si_addr >= ss_trigger_page && (guint8*)sinfo->si_addr <= (guint8*)ss_trigger_page + 128)
7588                 return TRUE;
7589         else
7590                 return FALSE;
7591 #endif
7592 }
7593
7594 /*
7595  * mono_arch_get_ip_for_single_step:
7596  *
7597  *   Convert the ip in CTX to the address stored in seq_points.
7598  */
7599 guint8*
7600 mono_arch_get_ip_for_single_step (MonoJitInfo *ji, MonoContext *ctx)
7601 {
7602         guint8 *ip = MONO_CONTEXT_GET_IP (ctx);
7603
7604         ip += single_step_fault_size;
7605
7606         return ip;
7607 }
7608
7609 /*
7610  * mono_arch_skip_single_step:
7611  *
7612  *   Modify CTX so the ip is placed after the single step trigger instruction,
7613  * we resume, the instruction is not executed again.
7614  */
7615 void
7616 mono_arch_skip_single_step (MonoContext *ctx)
7617 {
7618         MONO_CONTEXT_SET_IP (ctx, (guint8*)MONO_CONTEXT_GET_IP (ctx) + single_step_fault_size);
7619 }
7620
7621 /*
7622  * mono_arch_create_seq_point_info:
7623  *
7624  *   Return a pointer to a data structure which is used by the sequence
7625  * point implementation in AOTed code.
7626  */
7627 gpointer
7628 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
7629 {
7630         NOT_IMPLEMENTED;
7631         return NULL;
7632 }
7633
7634 #endif