mono/mini/mini-amd64.c

   1 /*
   2  * mini-amd64.c: AMD64 backend for the Mono code generator
   3  *
   4  * Based on mini-x86.c.
   5  *
   6  * Authors:
   7  *   Paolo Molaro (lupus@ximian.com)
   8  *   Dietmar Maurer (dietmar@ximian.com)
   9  *   Patrik Torstensson
  10  *   Zoltan Varga (vargaz@gmail.com)
  11  *
  12  * (C) 2003 Ximian, Inc.
  13  * Copyright 2003-2011 Novell, Inc (http://www.novell.com)
  14  * Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
  15  */
  16 #include "mini.h"
  17 #include <string.h>
  18 #include <math.h>
  19 #ifdef HAVE_UNISTD_H
  20 #include <unistd.h>
  21 #endif
  22
  23 #include <mono/metadata/abi-details.h>
  24 #include <mono/metadata/appdomain.h>
  25 #include <mono/metadata/debug-helpers.h>
  26 #include <mono/metadata/threads.h>
  27 #include <mono/metadata/profiler-private.h>
  28 #include <mono/metadata/mono-debug.h>
  29 #include <mono/metadata/gc-internals.h>
  30 #include <mono/utils/mono-math.h>
  31 #include <mono/utils/mono-mmap.h>
  32 #include <mono/utils/mono-memory-model.h>
  33 #include <mono/utils/mono-tls.h>
  34 #include <mono/utils/mono-hwcap-x86.h>
  35 #include <mono/utils/mono-threads.h>
  36
  37 #include "trace.h"
  38 #include "ir-emit.h"
  39 #include "mini-amd64.h"
  40 #include "cpu-amd64.h"
  41 #include "debugger-agent.h"
  42 #include "mini-gc.h"
  43
  44 #ifdef MONO_XEN_OPT
  45 static gboolean optimize_for_xen = TRUE;
  46 #else
  47 #define optimize_for_xen 0
  48 #endif
  49
  50 #define ALIGN_TO(val,align) ((((guint64)val) + ((align) - 1)) & ~((align) - 1))
  51
  52 #define IS_IMM32(val) ((((guint64)val) >> 32) == 0)
  53
  54 #define IS_REX(inst) (((inst) >= 0x40) && ((inst) <= 0x4f))
  55
  56 #ifdef TARGET_WIN32
  57 /* Under windows, the calling convention is never stdcall */
  58 #define CALLCONV_IS_STDCALL(call_conv) (FALSE)
  59 #else
  60 #define CALLCONV_IS_STDCALL(call_conv) ((call_conv) == MONO_CALL_STDCALL)
  61 #endif
  62
  63 /* This mutex protects architecture specific caches */
  64 #define mono_mini_arch_lock() mono_os_mutex_lock (&mini_arch_mutex)
  65 #define mono_mini_arch_unlock() mono_os_mutex_unlock (&mini_arch_mutex)
  66 static mono_mutex_t mini_arch_mutex;
  67
  68 /* The single step trampoline */
  69 static gpointer ss_trampoline;
  70
  71 /* The breakpoint trampoline */
  72 static gpointer bp_trampoline;
  73
  74 /* Offset between fp and the first argument in the callee */
  75 #define ARGS_OFFSET 16
  76 #define GP_SCRATCH_REG AMD64_R11
  77
  78 /*
  79  * AMD64 register usage:
  80  * - callee saved registers are used for global register allocation
  81  * - %r11 is used for materializing 64 bit constants in opcodes
  82  * - the rest is used for local allocation
  83  */
  84
  85 /*
  86  * Floating point comparison results:
  87  *                  ZF PF CF
  88  * A > B            0  0  0
  89  * A < B            0  0  1
  90  * A = B            1  0  0
  91  * A > B            0  0  0
  92  * UNORDERED        1  1  1
  93  */
  94
  95 const char*
  96 mono_arch_regname (int reg)
  97 {
  98         switch (reg) {
  99         case AMD64_RAX: return "%rax";
 100         case AMD64_RBX: return "%rbx";
 101         case AMD64_RCX: return "%rcx";
 102         case AMD64_RDX: return "%rdx";
 103         case AMD64_RSP: return "%rsp";
 104         case AMD64_RBP: return "%rbp";
 105         case AMD64_RDI: return "%rdi";
 106         case AMD64_RSI: return "%rsi";
 107         case AMD64_R8: return "%r8";
 108         case AMD64_R9: return "%r9";
 109         case AMD64_R10: return "%r10";
 110         case AMD64_R11: return "%r11";
 111         case AMD64_R12: return "%r12";
 112         case AMD64_R13: return "%r13";
 113         case AMD64_R14: return "%r14";
 114         case AMD64_R15: return "%r15";
 115         }
 116         return "unknown";
 117 }
 118
 119 static const char * packed_xmmregs [] = {
 120         "p:xmm0", "p:xmm1", "p:xmm2", "p:xmm3", "p:xmm4", "p:xmm5", "p:xmm6", "p:xmm7", "p:xmm8",
 121         "p:xmm9", "p:xmm10", "p:xmm11", "p:xmm12", "p:xmm13", "p:xmm14", "p:xmm15"
 122 };
 123
 124 static const char * single_xmmregs [] = {
 125         "s:xmm0", "s:xmm1", "s:xmm2", "s:xmm3", "s:xmm4", "s:xmm5", "s:xmm6", "s:xmm7", "s:xmm8",
 126         "s:xmm9", "s:xmm10", "s:xmm11", "s:xmm12", "s:xmm13", "s:xmm14", "s:xmm15"
 127 };
 128
 129 const char*
 130 mono_arch_fregname (int reg)
 131 {
 132         if (reg < AMD64_XMM_NREG)
 133                 return single_xmmregs [reg];
 134         else
 135                 return "unknown";
 136 }
 137
 138 const char *
 139 mono_arch_xregname (int reg)
 140 {
 141         if (reg < AMD64_XMM_NREG)
 142                 return packed_xmmregs [reg];
 143         else
 144                 return "unknown";
 145 }
 146
 147 static gboolean
 148 debug_omit_fp (void)
 149 {
 150 #if 0
 151         return mono_debug_count ();
 152 #else
 153         return TRUE;
 154 #endif
 155 }
 156
 157 static inline gboolean
 158 amd64_is_near_call (guint8 *code)
 159 {
 160         /* Skip REX */
 161         if ((code [0] >= 0x40) && (code [0] <= 0x4f))
 162                 code += 1;
 163
 164         return code [0] == 0xe8;
 165 }
 166
 167 static inline gboolean
 168 amd64_use_imm32 (gint64 val)
 169 {
 170         if (mini_get_debug_options()->single_imm_size)
 171                 return FALSE;
 172
 173         return amd64_is_imm32 (val);
 174 }
 175
 176 #ifdef __native_client_codegen__
 177
 178 /* Keep track of instruction "depth", that is, the level of sub-instruction */
 179 /* for any given instruction.  For instance, amd64_call_reg resolves to     */
 180 /* amd64_call_reg_internal, which uses amd64_alu_* macros, etc.             */
 181 /* We only want to force bundle alignment for the top level instruction,    */
 182 /* so NaCl pseudo-instructions can be implemented with sub instructions.    */
 183 static MonoNativeTlsKey nacl_instruction_depth;
 184
 185 static MonoNativeTlsKey nacl_rex_tag;
 186 static MonoNativeTlsKey nacl_legacy_prefix_tag;
 187
 188 void
 189 amd64_nacl_clear_legacy_prefix_tag ()
 190 {
 191         mono_native_tls_set_value (nacl_legacy_prefix_tag, NULL);
 192 }
 193
 194 void
 195 amd64_nacl_tag_legacy_prefix (guint8* code)
 196 {
 197         if (mono_native_tls_get_value (nacl_legacy_prefix_tag) == NULL)
 198                 mono_native_tls_set_value (nacl_legacy_prefix_tag, code);
 199 }
 200
 201 void
 202 amd64_nacl_tag_rex (guint8* code)
 203 {
 204         mono_native_tls_set_value (nacl_rex_tag, code);
 205 }
 206
 207 guint8*
 208 amd64_nacl_get_legacy_prefix_tag ()
 209 {
 210         return (guint8*)mono_native_tls_get_value (nacl_legacy_prefix_tag);
 211 }
 212
 213 guint8*
 214 amd64_nacl_get_rex_tag ()
 215 {
 216         return (guint8*)mono_native_tls_get_value (nacl_rex_tag);
 217 }
 218
 219 /* Increment the instruction "depth" described above */
 220 void
 221 amd64_nacl_instruction_pre ()
 222 {
 223         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 224         depth++;
 225         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)depth);
 226 }
 227
 228 /* amd64_nacl_instruction_post: Decrement instruction "depth", force bundle */
 229 /* alignment if depth == 0 (top level instruction)                          */
 230 /* IN: start, end    pointers to instruction beginning and end              */
 231 /* OUT: start, end   pointers to beginning and end after possible alignment */
 232 /* GLOBALS: nacl_instruction_depth     defined above                        */
 233 void
 234 amd64_nacl_instruction_post (guint8 **start, guint8 **end)
 235 {
 236         intptr_t depth = (intptr_t) mono_native_tls_get_value (nacl_instruction_depth);
 237         depth--;
 238         mono_native_tls_set_value (nacl_instruction_depth, (void*)depth);
 239
 240         g_assert ( depth >= 0 );
 241         if (depth == 0) {
 242                 uintptr_t space_in_block;
 243                 uintptr_t instlen;
 244                 guint8 *prefix = amd64_nacl_get_legacy_prefix_tag ();
 245                 /* if legacy prefix is present, and if it was emitted before */
 246                 /* the start of the instruction sequence, adjust the start   */
 247                 if (prefix != NULL && prefix < *start) {
 248                         g_assert (*start - prefix <= 3);/* only 3 are allowed */
 249                         *start = prefix;
 250                 }
 251                 space_in_block = kNaClAlignment - ((uintptr_t)(*start) & kNaClAlignmentMask);
 252                 instlen = (uintptr_t)(*end - *start);
 253                 /* Only check for instructions which are less than        */
 254                 /* kNaClAlignment. The only instructions that should ever */
 255                 /* be that long are call sequences, which are already     */
 256                 /* padded out to align the return to the next bundle.     */
 257                 if (instlen > space_in_block && instlen < kNaClAlignment) {
 258                         const size_t MAX_NACL_INST_LENGTH = kNaClAlignment;
 259                         guint8 copy_of_instruction[MAX_NACL_INST_LENGTH];
 260                         const size_t length = (size_t)((*end)-(*start));
 261                         g_assert (length < MAX_NACL_INST_LENGTH);
 262
 263                         memcpy (copy_of_instruction, *start, length);
 264                         *start = mono_arch_nacl_pad (*start, space_in_block);
 265                         memcpy (*start, copy_of_instruction, length);
 266                         *end = *start + length;
 267                 }
 268                 amd64_nacl_clear_legacy_prefix_tag ();
 269                 amd64_nacl_tag_rex (NULL);
 270         }
 271 }
 272
 273 /* amd64_nacl_membase_handler: ensure all access to memory of the form      */
 274 /*   OFFSET(%rXX) is sandboxed.  For allowable base registers %rip, %rbp,   */
 275 /*   %rsp, and %r15, emit the membase as usual.  For all other registers,   */
 276 /*   make sure the upper 32-bits are cleared, and use that register in the  */
 277 /*   index field of a new address of this form: OFFSET(%r15,%eXX,1)         */
 278 /* IN:      code                                                            */
 279 /*             pointer to current instruction stream (in the                */
 280 /*             middle of an instruction, after opcode is emitted)           */
 281 /*          basereg/offset/dreg                                             */
 282 /*             operands of normal membase address                           */
 283 /* OUT:     code                                                            */
 284 /*             pointer to the end of the membase/memindex emit              */
 285 /* GLOBALS: nacl_rex_tag                                                    */
 286 /*             position in instruction stream that rex prefix was emitted   */
 287 /*          nacl_legacy_prefix_tag                                          */
 288 /*             (possibly NULL) position in instruction of legacy x86 prefix */
 289 void
 290 amd64_nacl_membase_handler (guint8** code, gint8 basereg, gint32 offset, gint8 dreg)
 291 {
 292         gint8 true_basereg = basereg;
 293
 294         /* Cache these values, they might change  */
 295         /* as new instructions are emitted below. */
 296         guint8* rex_tag = amd64_nacl_get_rex_tag ();
 297         guint8* legacy_prefix_tag = amd64_nacl_get_legacy_prefix_tag ();
 298
 299         /* 'basereg' is given masked to 0x7 at this point, so check */
 300         /* the rex prefix to see if this is an extended register.   */
 301         if ((rex_tag != NULL) && IS_REX(*rex_tag) && (*rex_tag & AMD64_REX_B)) {
 302                 true_basereg |= 0x8;
 303         }
 304
 305 #define X86_LEA_OPCODE (0x8D)
 306
 307         if (!amd64_is_valid_nacl_base (true_basereg) && (*(*code-1) != X86_LEA_OPCODE)) {
 308                 guint8* old_instruction_start;
 309
 310                 /* This will hold the 'mov %eXX, %eXX' that clears the upper */
 311                 /* 32-bits of the old base register (new index register)     */
 312                 guint8 buf[32];
 313                 guint8* buf_ptr = buf;
 314                 size_t insert_len;
 315
 316                 g_assert (rex_tag != NULL);
 317
 318                 if (IS_REX(*rex_tag)) {
 319                         /* The old rex.B should be the new rex.X */
 320                         if (*rex_tag & AMD64_REX_B) {
 321                                 *rex_tag |= AMD64_REX_X;
 322                         }
 323                         /* Since our new base is %r15 set rex.B */
 324                         *rex_tag |= AMD64_REX_B;
 325                 } else {
 326                         /* Shift the instruction by one byte  */
 327                         /* so we can insert a rex prefix      */
 328                         memmove (rex_tag + 1, rex_tag, (size_t)(*code - rex_tag));
 329                         *code += 1;
 330                         /* New rex prefix only needs rex.B for %r15 base */
 331                         *rex_tag = AMD64_REX(AMD64_REX_B);
 332                 }
 333
 334                 if (legacy_prefix_tag) {
 335                         old_instruction_start = legacy_prefix_tag;
 336                 } else {
 337                         old_instruction_start = rex_tag;
 338                 }
 339
 340                 /* Clears the upper 32-bits of the previous base register */
 341                 amd64_mov_reg_reg_size (buf_ptr, true_basereg, true_basereg, 4);
 342                 insert_len = buf_ptr - buf;
 343
 344                 /* Move the old instruction forward to make */
 345                 /* room for 'mov' stored in 'buf_ptr'       */
 346                 memmove (old_instruction_start + insert_len, old_instruction_start, (size_t)(*code - old_instruction_start));
 347                 *code += insert_len;
 348                 memcpy (old_instruction_start, buf, insert_len);
 349
 350                 /* Sandboxed replacement for the normal membase_emit */
 351                 x86_memindex_emit (*code, dreg, AMD64_R15, offset, basereg, 0);
 352
 353         } else {
 354                 /* Normal default behavior, emit membase memory location */
 355                 x86_membase_emit_body (*code, dreg, basereg, offset);
 356         }
 357 }
 358
 359
 360 static inline unsigned char*
 361 amd64_skip_nops (unsigned char* code)
 362 {
 363         guint8 in_nop;
 364         do {
 365                 in_nop = 0;
 366                 if (   code[0] == 0x90) {
 367                         in_nop = 1;
 368                         code += 1;
 369                 }
 370                 if (   code[0] == 0x66 && code[1] == 0x90) {
 371                         in_nop = 1;
 372                         code += 2;
 373                 }
 374                 if (code[0] == 0x0f && code[1] == 0x1f
 375                  && code[2] == 0x00) {
 376                         in_nop = 1;
 377                         code += 3;
 378                 }
 379                 if (code[0] == 0x0f && code[1] == 0x1f
 380                  && code[2] == 0x40 && code[3] == 0x00) {
 381                         in_nop = 1;
 382                         code += 4;
 383                 }
 384                 if (code[0] == 0x0f && code[1] == 0x1f
 385                  && code[2] == 0x44 && code[3] == 0x00
 386                  && code[4] == 0x00) {
 387                         in_nop = 1;
 388                         code += 5;
 389                 }
 390                 if (code[0] == 0x66 && code[1] == 0x0f
 391                  && code[2] == 0x1f && code[3] == 0x44
 392                  && code[4] == 0x00 && code[5] == 0x00) {
 393                         in_nop = 1;
 394                         code += 6;
 395                 }
 396                 if (code[0] == 0x0f && code[1] == 0x1f
 397                  && code[2] == 0x80 && code[3] == 0x00
 398                  && code[4] == 0x00 && code[5] == 0x00
 399                  && code[6] == 0x00) {
 400                         in_nop = 1;
 401                         code += 7;
 402                 }
 403                 if (code[0] == 0x0f && code[1] == 0x1f
 404                  && code[2] == 0x84 && code[3] == 0x00
 405                  && code[4] == 0x00 && code[5] == 0x00
 406                  && code[6] == 0x00 && code[7] == 0x00) {
 407                         in_nop = 1;
 408                         code += 8;
 409                 }
 410         } while ( in_nop );
 411         return code;
 412 }
 413
 414 guint8*
 415 mono_arch_nacl_skip_nops (guint8* code)
 416 {
 417   return amd64_skip_nops(code);
 418 }
 419
 420 #endif /*__native_client_codegen__*/
 421
 422 static void
 423 amd64_patch (unsigned char* code, gpointer target)
 424 {
 425         guint8 rex = 0;
 426
 427 #ifdef __native_client_codegen__
 428         code = amd64_skip_nops (code);
 429 #endif
 430 #if defined(__native_client_codegen__) && defined(__native_client__)
 431         if (nacl_is_code_address (code)) {
 432                 /* For tail calls, code is patched after being installed */
 433                 /* but not through the normal "patch callsite" method.   */
 434                 unsigned char buf[kNaClAlignment];
 435                 unsigned char *aligned_code = (uintptr_t)code & ~kNaClAlignmentMask;
 436                 int ret;
 437                 memcpy (buf, aligned_code, kNaClAlignment);
 438                 /* Patch a temp buffer of bundle size, */
 439                 /* then install to actual location.    */
 440                 amd64_patch (buf + ((uintptr_t)code - (uintptr_t)aligned_code), target);
 441                 ret = nacl_dyncode_modify (aligned_code, buf, kNaClAlignment);
 442                 g_assert (ret == 0);
 443                 return;
 444         }
 445         target = nacl_modify_patch_target (target);
 446 #endif
 447
 448         /* Skip REX */
 449         if ((code [0] >= 0x40) && (code [0] <= 0x4f)) {
 450                 rex = code [0];
 451                 code += 1;
 452         }
 453
 454         if ((code [0] & 0xf8) == 0xb8) {
 455                 /* amd64_set_reg_template */
 456                 *(guint64*)(code + 1) = (guint64)target;
 457         }
 458         else if ((code [0] == 0x8b) && rex && x86_modrm_mod (code [1]) == 0 && x86_modrm_rm (code [1]) == 5) {
 459                 /* mov 0(%rip), %dreg */
 460                 *(guint32*)(code + 2) = (guint32)(guint64)target - 7;
 461         }
 462         else if ((code [0] == 0xff) && (code [1] == 0x15)) {
 463                 /* call *<OFFSET>(%rip) */
 464                 *(guint32*)(code + 2) = ((guint32)(guint64)target) - 7;
 465         }
 466         else if (code [0] == 0xe8) {
 467                 /* call <DISP> */
 468                 gint64 disp = (guint8*)target - (guint8*)code;
 469                 g_assert (amd64_is_imm32 (disp));
 470                 x86_patch (code, (unsigned char*)target);
 471         }
 472         else
 473                 x86_patch (code, (unsigned char*)target);
 474 }
 475
 476 void
 477 mono_amd64_patch (unsigned char* code, gpointer target)
 478 {
 479         amd64_patch (code, target);
 480 }
 481
 482 typedef enum {
 483         ArgInIReg,
 484         ArgInFloatSSEReg,
 485         ArgInDoubleSSEReg,
 486         ArgOnStack,
 487         ArgValuetypeInReg,
 488         ArgValuetypeAddrInIReg,
 489         /* gsharedvt argument passed by addr */
 490         ArgGSharedVtInReg,
 491         ArgGSharedVtOnStack,
 492         ArgNone /* only in pair_storage */
 493 } ArgStorage;
 494
 495 typedef struct {
 496         gint16 offset;
 497         gint8  reg;
 498         ArgStorage storage : 8;
 499         gboolean is_gsharedvt_return_value : 1;
 500
 501         /* Only if storage == ArgValuetypeInReg */
 502         ArgStorage pair_storage [2];
 503         gint8 pair_regs [2];
 504         /* The size of each pair */
 505         int pair_size [2];
 506         int nregs;
 507         /* Only if storage == ArgOnStack */
 508         int arg_size;
 509 } ArgInfo;
 510
 511 typedef struct {
 512         int nargs;
 513         guint32 stack_usage;
 514         guint32 reg_usage;
 515         guint32 freg_usage;
 516         gboolean need_stack_align;
 517         /* The index of the vret arg in the argument list */
 518         int vret_arg_index;
 519         ArgInfo ret;
 520         ArgInfo sig_cookie;
 521         ArgInfo args [1];
 522 } CallInfo;
 523
 524 #define DEBUG(a) if (cfg->verbose_level > 1) a
 525
 526 #ifdef TARGET_WIN32
 527 static AMD64_Reg_No param_regs [] = { AMD64_RCX, AMD64_RDX, AMD64_R8, AMD64_R9 };
 528
 529 static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 530 #else
 531 static AMD64_Reg_No param_regs [] = { AMD64_RDI, AMD64_RSI, AMD64_RDX, AMD64_RCX, AMD64_R8, AMD64_R9 };
 532
 533  static AMD64_Reg_No return_regs [] = { AMD64_RAX, AMD64_RDX };
 534 #endif
 535
 536 static void inline
 537 add_general (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo)
 538 {
 539     ainfo->offset = *stack_size;
 540
 541     if (*gr >= PARAM_REGS) {
 542                 ainfo->storage = ArgOnStack;
 543                 ainfo->arg_size = sizeof (mgreg_t);
 544                 /* Since the same stack slot size is used for all arg */
 545                 /*  types, it needs to be big enough to hold them all */
 546                 (*stack_size) += sizeof(mgreg_t);
 547     }
 548     else {
 549                 ainfo->storage = ArgInIReg;
 550                 ainfo->reg = param_regs [*gr];
 551                 (*gr) ++;
 552     }
 553 }
 554
 555 #ifdef TARGET_WIN32
 556 #define FLOAT_PARAM_REGS 4
 557 #else
 558 #define FLOAT_PARAM_REGS 8
 559 #endif
 560
 561 static void inline
 562 add_float (guint32 *gr, guint32 *stack_size, ArgInfo *ainfo, gboolean is_double)
 563 {
 564     ainfo->offset = *stack_size;
 565
 566     if (*gr >= FLOAT_PARAM_REGS) {
 567                 ainfo->storage = ArgOnStack;
 568                 ainfo->arg_size = sizeof (mgreg_t);
 569                 /* Since the same stack slot size is used for both float */
 570                 /*  types, it needs to be big enough to hold them both */
 571                 (*stack_size) += sizeof(mgreg_t);
 572     }
 573     else {
 574                 /* A double register */
 575                 if (is_double)
 576                         ainfo->storage = ArgInDoubleSSEReg;
 577                 else
 578                         ainfo->storage = ArgInFloatSSEReg;
 579                 ainfo->reg = *gr;
 580                 (*gr) += 1;
 581     }
 582 }
 583
 584 typedef enum ArgumentClass {
 585         ARG_CLASS_NO_CLASS,
 586         ARG_CLASS_MEMORY,
 587         ARG_CLASS_INTEGER,
 588         ARG_CLASS_SSE
 589 } ArgumentClass;
 590
 591 static ArgumentClass
 592 merge_argument_class_from_type (MonoType *type, ArgumentClass class1)
 593 {
 594         ArgumentClass class2 = ARG_CLASS_NO_CLASS;
 595         MonoType *ptype;
 596
 597         ptype = mini_get_underlying_type (type);
 598         switch (ptype->type) {
 599         case MONO_TYPE_I1:
 600         case MONO_TYPE_U1:
 601         case MONO_TYPE_I2:
 602         case MONO_TYPE_U2:
 603         case MONO_TYPE_I4:
 604         case MONO_TYPE_U4:
 605         case MONO_TYPE_I:
 606         case MONO_TYPE_U:
 607         case MONO_TYPE_STRING:
 608         case MONO_TYPE_OBJECT:
 609         case MONO_TYPE_CLASS:
 610         case MONO_TYPE_SZARRAY:
 611         case MONO_TYPE_PTR:
 612         case MONO_TYPE_FNPTR:
 613         case MONO_TYPE_ARRAY:
 614         case MONO_TYPE_I8:
 615         case MONO_TYPE_U8:
 616                 class2 = ARG_CLASS_INTEGER;
 617                 break;
 618         case MONO_TYPE_R4:
 619         case MONO_TYPE_R8:
 620 #ifdef TARGET_WIN32
 621                 class2 = ARG_CLASS_INTEGER;
 622 #else
 623                 class2 = ARG_CLASS_SSE;
 624 #endif
 625                 break;
 626
 627         case MONO_TYPE_TYPEDBYREF:
 628                 g_assert_not_reached ();
 629
 630         case MONO_TYPE_GENERICINST:
 631                 if (!mono_type_generic_inst_is_valuetype (ptype)) {
 632                         class2 = ARG_CLASS_INTEGER;
 633                         break;
 634                 }
 635                 /* fall through */
 636         case MONO_TYPE_VALUETYPE: {
 637                 MonoMarshalType *info = mono_marshal_load_type_info (ptype->data.klass);
 638                 int i;
 639
 640                 for (i = 0; i < info->num_fields; ++i) {
 641                         class2 = class1;
 642                         class2 = merge_argument_class_from_type (info->fields [i].field->type, class2);
 643                 }
 644                 break;
 645         }
 646         default:
 647                 g_assert_not_reached ();
 648         }
 649
 650         /* Merge */
 651         if (class1 == class2)
 652                 ;
 653         else if (class1 == ARG_CLASS_NO_CLASS)
 654                 class1 = class2;
 655         else if ((class1 == ARG_CLASS_MEMORY) || (class2 == ARG_CLASS_MEMORY))
 656                 class1 = ARG_CLASS_MEMORY;
 657         else if ((class1 == ARG_CLASS_INTEGER) || (class2 == ARG_CLASS_INTEGER))
 658                 class1 = ARG_CLASS_INTEGER;
 659         else
 660                 class1 = ARG_CLASS_SSE;
 661
 662         return class1;
 663 }
 664 #ifdef __native_client_codegen__
 665
 666 /* Default alignment for Native Client is 32-byte. */
 667 gint8 nacl_align_byte = -32; /* signed version of 0xe0 */
 668
 669 /* mono_arch_nacl_pad: Add pad bytes of alignment instructions at code,  */
 670 /* Check that alignment doesn't cross an alignment boundary.             */
 671 guint8*
 672 mono_arch_nacl_pad(guint8 *code, int pad)
 673 {
 674         const int kMaxPadding = 8; /* see amd64-codegen.h:amd64_padding_size() */
 675
 676         if (pad == 0) return code;
 677         /* assertion: alignment cannot cross a block boundary */
 678         g_assert (((uintptr_t)code & (~kNaClAlignmentMask)) ==
 679                  (((uintptr_t)code + pad - 1) & (~kNaClAlignmentMask)));
 680         while (pad >= kMaxPadding) {
 681                 amd64_padding (code, kMaxPadding);
 682                 pad -= kMaxPadding;
 683         }
 684         if (pad != 0) amd64_padding (code, pad);
 685         return code;
 686 }
 687 #endif
 688
 689 static int
 690 count_fields_nested (MonoClass *klass)
 691 {
 692         MonoMarshalType *info;
 693         int i, count;
 694
 695         info = mono_marshal_load_type_info (klass);
 696         g_assert(info);
 697         count = 0;
 698         for (i = 0; i < info->num_fields; ++i) {
 699                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type))
 700                         count += count_fields_nested (mono_class_from_mono_type (info->fields [i].field->type));
 701                 else
 702                         count ++;
 703         }
 704         return count;
 705 }
 706
 707 static int
 708 collect_field_info_nested (MonoClass *klass, MonoMarshalField *fields, int index, int offset)
 709 {
 710         MonoMarshalType *info;
 711         int i;
 712
 713         info = mono_marshal_load_type_info (klass);
 714         g_assert(info);
 715         for (i = 0; i < info->num_fields; ++i) {
 716                 if (MONO_TYPE_ISSTRUCT (info->fields [i].field->type)) {
 717                         index = collect_field_info_nested (mono_class_from_mono_type (info->fields [i].field->type), fields, index, info->fields [i].offset);
 718                 } else {
 719                         memcpy (&fields [index], &info->fields [i], sizeof (MonoMarshalField));
 720                         fields [index].offset += offset;
 721                         index ++;
 722                 }
 723         }
 724         return index;
 725 }
 726
 727 #ifdef TARGET_WIN32
 728 static void
 729 add_valuetype_win64 (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 730                                          gboolean is_return,
 731                                          guint32 *gr, guint32 *fr, guint32 *stack_size)
 732 {
 733         guint32 size, i, nfields;
 734         guint32 argsize = 8;
 735         ArgumentClass arg_class;
 736         MonoMarshalType *info = NULL;
 737         MonoMarshalField *fields = NULL;
 738         MonoClass *klass;
 739         gboolean pass_on_stack = FALSE;
 740
 741         klass = mono_class_from_mono_type (type);
 742         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 743         if (!sig->pinvoke)
 744                 pass_on_stack = TRUE;
 745
 746         /* If this struct can't be split up naturally into 8-byte */
 747         /* chunks (registers), pass it on the stack.              */
 748         if (sig->pinvoke && !pass_on_stack) {
 749                 guint32 align;
 750                 guint32 field_size;
 751
 752                 info = mono_marshal_load_type_info (klass);
 753                 g_assert (info);
 754
 755                 /*
 756                  * Collect field information recursively to be able to
 757                  * handle nested structures.
 758                  */
 759                 nfields = count_fields_nested (klass);
 760                 fields = g_new0 (MonoMarshalField, nfields);
 761                 collect_field_info_nested (klass, fields, 0, 0);
 762
 763                 for (i = 0; i < nfields; ++i) {
 764                         field_size = mono_marshal_type_size (fields [i].field->type,
 765                                                            fields [i].mspec,
 766                                                            &align, TRUE, klass->unicode);
 767                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 768                                 pass_on_stack = TRUE;
 769                                 break;
 770                         }
 771                 }
 772         }
 773
 774         if (pass_on_stack) {
 775                 /* Allways pass in memory */
 776                 ainfo->offset = *stack_size;
 777                 *stack_size += ALIGN_TO (size, 8);
 778                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 779                 if (!is_return)
 780                         ainfo->arg_size = ALIGN_TO (size, 8);
 781
 782                 g_free (fields);
 783                 return;
 784         }
 785
 786         if (!sig->pinvoke) {
 787                 int n = mono_class_value_size (klass, NULL);
 788
 789                 argsize = n;
 790
 791                 if (n > 8)
 792                         arg_class = ARG_CLASS_MEMORY;
 793                 else
 794                         /* Always pass in 1 integer register */
 795                         arg_class = ARG_CLASS_INTEGER;
 796         } else {
 797                 g_assert (info);
 798
 799                 if (!fields) {
 800                         ainfo->storage = ArgValuetypeInReg;
 801                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 802                         return;
 803                 }
 804
 805                 switch (info->native_size) {
 806                 case 1: case 2: case 4: case 8:
 807                         break;
 808                 default:
 809                         if (is_return) {
 810                                 ainfo->storage = ArgValuetypeAddrInIReg;
 811                                 ainfo->offset = *stack_size;
 812                                 *stack_size += ALIGN_TO (info->native_size, 8);
 813                         }
 814                         else {
 815                                 ainfo->storage = ArgValuetypeAddrInIReg;
 816
 817                                 if (*gr < PARAM_REGS) {
 818                                         ainfo->pair_storage [0] = ArgInIReg;
 819                                         ainfo->pair_regs [0] = param_regs [*gr];
 820                                         (*gr) ++;
 821                                 }
 822                                 else {
 823                                         ainfo->pair_storage [0] = ArgOnStack;
 824                                         ainfo->offset = *stack_size;
 825                                         ainfo->arg_size = sizeof (mgreg_t);
 826                                         *stack_size += 8;
 827                                 }
 828                         }
 829
 830                         g_free (fields);
 831                         return;
 832                 }
 833
 834                 int size;
 835                 guint32 align;
 836                 ArgumentClass class1;
 837
 838                 if (nfields == 0)
 839                         class1 = ARG_CLASS_MEMORY;
 840                 else
 841                         class1 = ARG_CLASS_NO_CLASS;
 842                 for (i = 0; i < nfields; ++i) {
 843                         size = mono_marshal_type_size (fields [i].field->type,
 844                                                                                    fields [i].mspec,
 845                                                                                    &align, TRUE, klass->unicode);
 846                         /* How far into this quad this data extends.*/
 847                         /* (8 is size of quad) */
 848                         argsize = fields [i].offset + size;
 849
 850                         class1 = merge_argument_class_from_type (fields [i].field->type, class1);
 851                 }
 852                 g_assert (class1 != ARG_CLASS_NO_CLASS);
 853                 arg_class = class1;
 854         }
 855
 856         g_free (fields);
 857
 858         /* Allocate registers */
 859         {
 860                 int orig_gr = *gr;
 861                 int orig_fr = *fr;
 862
 863                 while (argsize != 1 && argsize != 2 && argsize != 4 && argsize != 8)
 864                         argsize ++;
 865
 866                 ainfo->storage = ArgValuetypeInReg;
 867                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 868                 ainfo->pair_size [0] = argsize;
 869                 ainfo->pair_size [1] = 0;
 870                 ainfo->nregs = 1;
 871                 switch (arg_class) {
 872                 case ARG_CLASS_INTEGER:
 873                         if (*gr >= PARAM_REGS)
 874                                 arg_class = ARG_CLASS_MEMORY;
 875                         else {
 876                                 ainfo->pair_storage [0] = ArgInIReg;
 877                                 if (is_return)
 878                                         ainfo->pair_regs [0] = return_regs [*gr];
 879                                 else
 880                                         ainfo->pair_regs [0] = param_regs [*gr];
 881                                 (*gr) ++;
 882                         }
 883                         break;
 884                 case ARG_CLASS_SSE:
 885                         if (*fr >= FLOAT_PARAM_REGS)
 886                                 arg_class = ARG_CLASS_MEMORY;
 887                         else {
 888                                 if (argsize <= 4)
 889                                         ainfo->pair_storage [0] = ArgInFloatSSEReg;
 890                                 else
 891                                         ainfo->pair_storage [0] = ArgInDoubleSSEReg;
 892                                 ainfo->pair_regs [0] = *fr;
 893                                 (*fr) ++;
 894                         }
 895                         break;
 896                 case ARG_CLASS_MEMORY:
 897                         break;
 898                 default:
 899                         g_assert_not_reached ();
 900                 }
 901
 902                 if (arg_class == ARG_CLASS_MEMORY) {
 903                         /* Revert possible register assignments */
 904                         *gr = orig_gr;
 905                         *fr = orig_fr;
 906
 907                         ainfo->offset = *stack_size;
 908                         *stack_size += sizeof (mgreg_t);
 909                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 910                         if (!is_return)
 911                                 ainfo->arg_size = sizeof (mgreg_t);
 912                 }
 913         }
 914 }
 915 #endif /* TARGET_WIN32 */
 916
 917 static void
 918 add_valuetype (MonoMethodSignature *sig, ArgInfo *ainfo, MonoType *type,
 919                            gboolean is_return,
 920                            guint32 *gr, guint32 *fr, guint32 *stack_size)
 921 {
 922 #ifdef TARGET_WIN32
 923         add_valuetype_win64 (sig, ainfo, type, is_return, gr, fr, stack_size);
 924 #else
 925         guint32 size, quad, nquads, i, nfields;
 926         /* Keep track of the size used in each quad so we can */
 927         /* use the right size when copying args/return vars.  */
 928         guint32 quadsize [2] = {8, 8};
 929         ArgumentClass args [2];
 930         MonoMarshalType *info = NULL;
 931         MonoMarshalField *fields = NULL;
 932         MonoClass *klass;
 933         gboolean pass_on_stack = FALSE;
 934
 935         klass = mono_class_from_mono_type (type);
 936         size = mini_type_stack_size_full (&klass->byval_arg, NULL, sig->pinvoke);
 937         if (!sig->pinvoke && ((is_return && (size == 8)) || (!is_return && (size <= 16)))) {
 938                 /* We pass and return vtypes of size 8 in a register */
 939         } else if (!sig->pinvoke || (size == 0) || (size > 16)) {
 940                 pass_on_stack = TRUE;
 941         }
 942
 943         /* If this struct can't be split up naturally into 8-byte */
 944         /* chunks (registers), pass it on the stack.              */
 945         if (sig->pinvoke && !pass_on_stack) {
 946                 guint32 align;
 947                 guint32 field_size;
 948
 949                 info = mono_marshal_load_type_info (klass);
 950                 g_assert (info);
 951
 952                 /*
 953                  * Collect field information recursively to be able to
 954                  * handle nested structures.
 955                  */
 956                 nfields = count_fields_nested (klass);
 957                 fields = g_new0 (MonoMarshalField, nfields);
 958                 collect_field_info_nested (klass, fields, 0, 0);
 959
 960                 for (i = 0; i < nfields; ++i) {
 961                         field_size = mono_marshal_type_size (fields [i].field->type,
 962                                                            fields [i].mspec,
 963                                                            &align, TRUE, klass->unicode);
 964                         if ((fields [i].offset < 8) && (fields [i].offset + field_size) > 8) {
 965                                 pass_on_stack = TRUE;
 966                                 break;
 967                         }
 968                 }
 969         }
 970
 971         if (size == 0) {
 972                 ainfo->storage = ArgValuetypeInReg;
 973                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
 974                 return;
 975         }
 976
 977         if (pass_on_stack) {
 978                 /* Allways pass in memory */
 979                 ainfo->offset = *stack_size;
 980                 *stack_size += ALIGN_TO (size, 8);
 981                 ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
 982                 if (!is_return)
 983                         ainfo->arg_size = ALIGN_TO (size, 8);
 984
 985                 g_free (fields);
 986                 return;
 987         }
 988
 989         if (size > 8)
 990                 nquads = 2;
 991         else
 992                 nquads = 1;
 993
 994         if (!sig->pinvoke) {
 995                 int n = mono_class_value_size (klass, NULL);
 996
 997                 quadsize [0] = n >= 8 ? 8 : n;
 998                 quadsize [1] = n >= 8 ? MAX (n - 8, 8) : 0;
 999
1000                 /* Always pass in 1 or 2 integer registers */
1001                 args [0] = ARG_CLASS_INTEGER;
1002                 args [1] = ARG_CLASS_INTEGER;
1003                 /* Only the simplest cases are supported */
1004                 if (is_return && nquads != 1) {
1005                         args [0] = ARG_CLASS_MEMORY;
1006                         args [1] = ARG_CLASS_MEMORY;
1007                 }
1008         } else {
1009                 /*
1010                  * Implement the algorithm from section 3.2.3 of the X86_64 ABI.
1011                  * The X87 and SSEUP stuff is left out since there are no such types in
1012                  * the CLR.
1013                  */
1014                 g_assert (info);
1015
1016                 if (!fields) {
1017                         ainfo->storage = ArgValuetypeInReg;
1018                         ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1019                         return;
1020                 }
1021
1022                 if (info->native_size > 16) {
1023                         ainfo->offset = *stack_size;
1024                         *stack_size += ALIGN_TO (info->native_size, 8);
1025                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1026                         if (!is_return)
1027                                 ainfo->arg_size = ALIGN_TO (info->native_size, 8);
1028
1029                         g_free (fields);
1030                         return;
1031                 }
1032
1033                 args [0] = ARG_CLASS_NO_CLASS;
1034                 args [1] = ARG_CLASS_NO_CLASS;
1035                 for (quad = 0; quad < nquads; ++quad) {
1036                         int size;
1037                         guint32 align;
1038                         ArgumentClass class1;
1039
1040                         if (nfields == 0)
1041                                 class1 = ARG_CLASS_MEMORY;
1042                         else
1043                                 class1 = ARG_CLASS_NO_CLASS;
1044                         for (i = 0; i < nfields; ++i) {
1045                                 size = mono_marshal_type_size (fields [i].field->type,
1046                                                                                            fields [i].mspec,
1047                                                                                            &align, TRUE, klass->unicode);
1048                                 if ((fields [i].offset < 8) && (fields [i].offset + size) > 8) {
1049                                         /* Unaligned field */
1050                                         NOT_IMPLEMENTED;
1051                                 }
1052
1053                                 /* Skip fields in other quad */
1054                                 if ((quad == 0) && (fields [i].offset >= 8))
1055                                         continue;
1056                                 if ((quad == 1) && (fields [i].offset < 8))
1057                                         continue;
1058
1059                                 /* How far into this quad this data extends.*/
1060                                 /* (8 is size of quad) */
1061                                 quadsize [quad] = fields [i].offset + size - (quad * 8);
1062
1063                                 class1 = merge_argument_class_from_type (fields [i].field->type, class1);
1064                         }
1065                         g_assert (class1 != ARG_CLASS_NO_CLASS);
1066                         args [quad] = class1;
1067                 }
1068         }
1069
1070         g_free (fields);
1071
1072         /* Post merger cleanup */
1073         if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY))
1074                 args [0] = args [1] = ARG_CLASS_MEMORY;
1075
1076         /* Allocate registers */
1077         {
1078                 int orig_gr = *gr;
1079                 int orig_fr = *fr;
1080
1081                 while (quadsize [0] != 1 && quadsize [0] != 2 && quadsize [0] != 4 && quadsize [0] != 8)
1082                         quadsize [0] ++;
1083                 while (quadsize [1] != 0 && quadsize [1] != 1 && quadsize [1] != 2 && quadsize [1] != 4 && quadsize [1] != 8)
1084                         quadsize [1] ++;
1085
1086                 ainfo->storage = ArgValuetypeInReg;
1087                 ainfo->pair_storage [0] = ainfo->pair_storage [1] = ArgNone;
1088                 g_assert (quadsize [0] <= 8);
1089                 g_assert (quadsize [1] <= 8);
1090                 ainfo->pair_size [0] = quadsize [0];
1091                 ainfo->pair_size [1] = quadsize [1];
1092                 ainfo->nregs = nquads;
1093                 for (quad = 0; quad < nquads; ++quad) {
1094                         switch (args [quad]) {
1095                         case ARG_CLASS_INTEGER:
1096                                 if (*gr >= PARAM_REGS)
1097                                         args [quad] = ARG_CLASS_MEMORY;
1098                                 else {
1099                                         ainfo->pair_storage [quad] = ArgInIReg;
1100                                         if (is_return)
1101                                                 ainfo->pair_regs [quad] = return_regs [*gr];
1102                                         else
1103                                                 ainfo->pair_regs [quad] = param_regs [*gr];
1104                                         (*gr) ++;
1105                                 }
1106                                 break;
1107                         case ARG_CLASS_SSE:
1108                                 if (*fr >= FLOAT_PARAM_REGS)
1109                                         args [quad] = ARG_CLASS_MEMORY;
1110                                 else {
1111                                         if (quadsize[quad] <= 4)
1112                                                 ainfo->pair_storage [quad] = ArgInFloatSSEReg;
1113                                         else ainfo->pair_storage [quad] = ArgInDoubleSSEReg;
1114                                         ainfo->pair_regs [quad] = *fr;
1115                                         (*fr) ++;
1116                                 }
1117                                 break;
1118                         case ARG_CLASS_MEMORY:
1119                                 break;
1120                         default:
1121                                 g_assert_not_reached ();
1122                         }
1123                 }
1124
1125                 if ((args [0] == ARG_CLASS_MEMORY) || (args [1] == ARG_CLASS_MEMORY)) {
1126                         int arg_size;
1127                         /* Revert possible register assignments */
1128                         *gr = orig_gr;
1129                         *fr = orig_fr;
1130
1131                         ainfo->offset = *stack_size;
1132                         if (sig->pinvoke)
1133                                 arg_size = ALIGN_TO (info->native_size, 8);
1134                         else
1135                                 arg_size = nquads * sizeof(mgreg_t);
1136                         *stack_size += arg_size;
1137                         ainfo->storage = is_return ? ArgValuetypeAddrInIReg : ArgOnStack;
1138                         if (!is_return)
1139                                 ainfo->arg_size = arg_size;
1140                 }
1141         }
1142 #endif /* !TARGET_WIN32 */
1143 }
1144
1145 /*
1146  * get_call_info:
1147  *
1148  *  Obtain information about a call according to the calling convention.
1149  * For AMD64, see the "System V ABI, x86-64 Architecture Processor Supplement
1150  * Draft Version 0.23" document for more information.
1151  */
1152 static CallInfo*
1153 get_call_info (MonoMemPool *mp, MonoMethodSignature *sig)
1154 {
1155         guint32 i, gr, fr, pstart;
1156         MonoType *ret_type;
1157         int n = sig->hasthis + sig->param_count;
1158         guint32 stack_size = 0;
1159         CallInfo *cinfo;
1160         gboolean is_pinvoke = sig->pinvoke;
1161
1162         if (mp)
1163                 cinfo = (CallInfo *)mono_mempool_alloc0 (mp, sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1164         else
1165                 cinfo = (CallInfo *)g_malloc0 (sizeof (CallInfo) + (sizeof (ArgInfo) * n));
1166
1167         cinfo->nargs = n;
1168
1169         gr = 0;
1170         fr = 0;
1171
1172 #ifdef TARGET_WIN32
1173         /* Reserve space where the callee can save the argument registers */
1174         stack_size = 4 * sizeof (mgreg_t);
1175 #endif
1176
1177         /* return value */
1178         ret_type = mini_get_underlying_type (sig->ret);
1179         switch (ret_type->type) {
1180         case MONO_TYPE_I1:
1181         case MONO_TYPE_U1:
1182         case MONO_TYPE_I2:
1183         case MONO_TYPE_U2:
1184         case MONO_TYPE_I4:
1185         case MONO_TYPE_U4:
1186         case MONO_TYPE_I:
1187         case MONO_TYPE_U:
1188         case MONO_TYPE_PTR:
1189         case MONO_TYPE_FNPTR:
1190         case MONO_TYPE_CLASS:
1191         case MONO_TYPE_OBJECT:
1192         case MONO_TYPE_SZARRAY:
1193         case MONO_TYPE_ARRAY:
1194         case MONO_TYPE_STRING:
1195                 cinfo->ret.storage = ArgInIReg;
1196                 cinfo->ret.reg = AMD64_RAX;
1197                 break;
1198         case MONO_TYPE_U8:
1199         case MONO_TYPE_I8:
1200                 cinfo->ret.storage = ArgInIReg;
1201                 cinfo->ret.reg = AMD64_RAX;
1202                 break;
1203         case MONO_TYPE_R4:
1204                 cinfo->ret.storage = ArgInFloatSSEReg;
1205                 cinfo->ret.reg = AMD64_XMM0;
1206                 break;
1207         case MONO_TYPE_R8:
1208                 cinfo->ret.storage = ArgInDoubleSSEReg;
1209                 cinfo->ret.reg = AMD64_XMM0;
1210                 break;
1211         case MONO_TYPE_GENERICINST:
1212                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
1213                         cinfo->ret.storage = ArgInIReg;
1214                         cinfo->ret.reg = AMD64_RAX;
1215                         break;
1216                 }
1217                 if (mini_is_gsharedvt_type (ret_type)) {
1218                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1219                         cinfo->ret.is_gsharedvt_return_value = 1;
1220                         break;
1221                 }
1222                 /* fall through */
1223         case MONO_TYPE_VALUETYPE:
1224         case MONO_TYPE_TYPEDBYREF: {
1225                 guint32 tmp_gr = 0, tmp_fr = 0, tmp_stacksize = 0;
1226
1227                 add_valuetype (sig, &cinfo->ret, ret_type, TRUE, &tmp_gr, &tmp_fr, &tmp_stacksize);
1228                 g_assert (cinfo->ret.storage != ArgInIReg);
1229                 break;
1230         }
1231         case MONO_TYPE_VAR:
1232         case MONO_TYPE_MVAR:
1233                 g_assert (mini_is_gsharedvt_type (ret_type));
1234                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1235                 cinfo->ret.is_gsharedvt_return_value = 1;
1236                 break;
1237         case MONO_TYPE_VOID:
1238                 break;
1239         default:
1240                 g_error ("Can't handle as return value 0x%x", ret_type->type);
1241         }
1242
1243         pstart = 0;
1244         /*
1245          * To simplify get_this_arg_reg () and LLVM integration, emit the vret arg after
1246          * the first argument, allowing 'this' to be always passed in the first arg reg.
1247          * Also do this if the first argument is a reference type, since virtual calls
1248          * are sometimes made using calli without sig->hasthis set, like in the delegate
1249          * invoke wrappers.
1250          */
1251         if (cinfo->ret.storage == ArgValuetypeAddrInIReg && !is_pinvoke && (sig->hasthis || (sig->param_count > 0 && MONO_TYPE_IS_REFERENCE (mini_get_underlying_type (sig->params [0]))))) {
1252                 if (sig->hasthis) {
1253                         add_general (&gr, &stack_size, cinfo->args + 0);
1254                 } else {
1255                         add_general (&gr, &stack_size, &cinfo->args [sig->hasthis + 0]);
1256                         pstart = 1;
1257                 }
1258                 add_general (&gr, &stack_size, &cinfo->ret);
1259                 cinfo->ret.storage = ArgValuetypeAddrInIReg;
1260                 cinfo->vret_arg_index = 1;
1261         } else {
1262                 /* this */
1263                 if (sig->hasthis)
1264                         add_general (&gr, &stack_size, cinfo->args + 0);
1265
1266                 if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
1267                         add_general (&gr, &stack_size, &cinfo->ret);
1268                         cinfo->ret.storage = ArgValuetypeAddrInIReg;
1269                 }
1270         }
1271
1272         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == 0)) {
1273                 gr = PARAM_REGS;
1274                 fr = FLOAT_PARAM_REGS;
1275
1276                 /* Emit the signature cookie just before the implicit arguments */
1277                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1278         }
1279
1280         for (i = pstart; i < sig->param_count; ++i) {
1281                 ArgInfo *ainfo = &cinfo->args [sig->hasthis + i];
1282                 MonoType *ptype;
1283
1284 #ifdef TARGET_WIN32
1285                 /* The float param registers and other param registers must be the same index on Windows x64.*/
1286                 if (gr > fr)
1287                         fr = gr;
1288                 else if (fr > gr)
1289                         gr = fr;
1290 #endif
1291
1292                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos)) {
1293                         /* We allways pass the sig cookie on the stack for simplicity */
1294                         /*
1295                          * Prevent implicit arguments + the sig cookie from being passed
1296                          * in registers.
1297                          */
1298                         gr = PARAM_REGS;
1299                         fr = FLOAT_PARAM_REGS;
1300
1301                         /* Emit the signature cookie just before the implicit arguments */
1302                         add_general (&gr, &stack_size, &cinfo->sig_cookie);
1303                 }
1304
1305                 ptype = mini_get_underlying_type (sig->params [i]);
1306                 switch (ptype->type) {
1307                 case MONO_TYPE_I1:
1308                 case MONO_TYPE_U1:
1309                         add_general (&gr, &stack_size, ainfo);
1310                         break;
1311                 case MONO_TYPE_I2:
1312                 case MONO_TYPE_U2:
1313                         add_general (&gr, &stack_size, ainfo);
1314                         break;
1315                 case MONO_TYPE_I4:
1316                 case MONO_TYPE_U4:
1317                         add_general (&gr, &stack_size, ainfo);
1318                         break;
1319                 case MONO_TYPE_I:
1320                 case MONO_TYPE_U:
1321                 case MONO_TYPE_PTR:
1322                 case MONO_TYPE_FNPTR:
1323                 case MONO_TYPE_CLASS:
1324                 case MONO_TYPE_OBJECT:
1325                 case MONO_TYPE_STRING:
1326                 case MONO_TYPE_SZARRAY:
1327                 case MONO_TYPE_ARRAY:
1328                         add_general (&gr, &stack_size, ainfo);
1329                         break;
1330                 case MONO_TYPE_GENERICINST:
1331                         if (!mono_type_generic_inst_is_valuetype (ptype)) {
1332                                 add_general (&gr, &stack_size, ainfo);
1333                                 break;
1334                         }
1335                         if (mini_is_gsharedvt_variable_type (ptype)) {
1336                                 /* gsharedvt arguments are passed by ref */
1337                                 add_general (&gr, &stack_size, ainfo);
1338                                 if (ainfo->storage == ArgInIReg)
1339                                         ainfo->storage = ArgGSharedVtInReg;
1340                                 else
1341                                         ainfo->storage = ArgGSharedVtOnStack;
1342                                 break;
1343                         }
1344                         /* fall through */
1345                 case MONO_TYPE_VALUETYPE:
1346                 case MONO_TYPE_TYPEDBYREF:
1347                         add_valuetype (sig, ainfo, sig->params [i], FALSE, &gr, &fr, &stack_size);
1348                         break;
1349                 case MONO_TYPE_U8:
1350
1351                 case MONO_TYPE_I8:
1352                         add_general (&gr, &stack_size, ainfo);
1353                         break;
1354                 case MONO_TYPE_R4:
1355                         add_float (&fr, &stack_size, ainfo, FALSE);
1356                         break;
1357                 case MONO_TYPE_R8:
1358                         add_float (&fr, &stack_size, ainfo, TRUE);
1359                         break;
1360                 case MONO_TYPE_VAR:
1361                 case MONO_TYPE_MVAR:
1362                         /* gsharedvt arguments are passed by ref */
1363                         g_assert (mini_is_gsharedvt_type (ptype));
1364                         add_general (&gr, &stack_size, ainfo);
1365                         if (ainfo->storage == ArgInIReg)
1366                                 ainfo->storage = ArgGSharedVtInReg;
1367                         else
1368                                 ainfo->storage = ArgGSharedVtOnStack;
1369                         break;
1370                 default:
1371                         g_assert_not_reached ();
1372                 }
1373         }
1374
1375         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n > 0) && (sig->sentinelpos == sig->param_count)) {
1376                 gr = PARAM_REGS;
1377                 fr = FLOAT_PARAM_REGS;
1378
1379                 /* Emit the signature cookie just before the implicit arguments */
1380                 add_general (&gr, &stack_size, &cinfo->sig_cookie);
1381         }
1382
1383         cinfo->stack_usage = stack_size;
1384         cinfo->reg_usage = gr;
1385         cinfo->freg_usage = fr;
1386         return cinfo;
1387 }
1388
1389 /*
1390  * mono_arch_get_argument_info:
1391  * @csig:  a method signature
1392  * @param_count: the number of parameters to consider
1393  * @arg_info: an array to store the result infos
1394  *
1395  * Gathers information on parameters such as size, alignment and
1396  * padding. arg_info should be large enought to hold param_count + 1 entries.
1397  *
1398  * Returns the size of the argument area on the stack.
1399  */
1400 int
1401 mono_arch_get_argument_info (MonoMethodSignature *csig, int param_count, MonoJitArgumentInfo *arg_info)
1402 {
1403         int k;
1404         CallInfo *cinfo = get_call_info (NULL, csig);
1405         guint32 args_size = cinfo->stack_usage;
1406
1407         /* The arguments are saved to a stack area in mono_arch_instrument_prolog */
1408         if (csig->hasthis) {
1409                 arg_info [0].offset = 0;
1410         }
1411
1412         for (k = 0; k < param_count; k++) {
1413                 arg_info [k + 1].offset = ((k + csig->hasthis) * 8);
1414                 /* FIXME: */
1415                 arg_info [k + 1].size = 0;
1416         }
1417
1418         g_free (cinfo);
1419
1420         return args_size;
1421 }
1422
1423 gboolean
1424 mono_arch_tail_call_supported (MonoCompile *cfg, MonoMethodSignature *caller_sig, MonoMethodSignature *callee_sig)
1425 {
1426         CallInfo *c1, *c2;
1427         gboolean res;
1428         MonoType *callee_ret;
1429
1430         c1 = get_call_info (NULL, caller_sig);
1431         c2 = get_call_info (NULL, callee_sig);
1432         res = c1->stack_usage >= c2->stack_usage;
1433         callee_ret = mini_get_underlying_type (callee_sig->ret);
1434         if (callee_ret && MONO_TYPE_ISSTRUCT (callee_ret) && c2->ret.storage != ArgValuetypeInReg)
1435                 /* An address on the callee's stack is passed as the first argument */
1436                 res = FALSE;
1437
1438         g_free (c1);
1439         g_free (c2);
1440
1441         return res;
1442 }
1443
1444 /*
1445  * Initialize the cpu to execute managed code.
1446  */
1447 void
1448 mono_arch_cpu_init (void)
1449 {
1450 #ifndef _MSC_VER
1451         guint16 fpcw;
1452
1453         /* spec compliance requires running with double precision */
1454         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1455         fpcw &= ~X86_FPCW_PRECC_MASK;
1456         fpcw |= X86_FPCW_PREC_DOUBLE;
1457         __asm__  __volatile__ ("fldcw %0\n": : "m" (fpcw));
1458         __asm__  __volatile__ ("fnstcw %0\n": "=m" (fpcw));
1459 #else
1460         /* TODO: This is crashing on Win64 right now.
1461         * _control87 (_PC_53, MCW_PC);
1462         */
1463 #endif
1464 }
1465
1466 /*
1467  * Initialize architecture specific code.
1468  */
1469 void
1470 mono_arch_init (void)
1471 {
1472         mono_os_mutex_init_recursive (&mini_arch_mutex);
1473 #if defined(__native_client_codegen__)
1474         mono_native_tls_alloc (&nacl_instruction_depth, NULL);
1475         mono_native_tls_set_value (nacl_instruction_depth, (gpointer)0);
1476         mono_native_tls_alloc (&nacl_rex_tag, NULL);
1477         mono_native_tls_alloc (&nacl_legacy_prefix_tag, NULL);
1478 #endif
1479
1480         mono_aot_register_jit_icall ("mono_amd64_throw_exception", mono_amd64_throw_exception);
1481         mono_aot_register_jit_icall ("mono_amd64_throw_corlib_exception", mono_amd64_throw_corlib_exception);
1482         mono_aot_register_jit_icall ("mono_amd64_resume_unwind", mono_amd64_resume_unwind);
1483         mono_aot_register_jit_icall ("mono_amd64_get_original_ip", mono_amd64_get_original_ip);
1484 #if defined(ENABLE_GSHAREDVT)
1485         mono_aot_register_jit_icall ("mono_amd64_start_gsharedvt_call", mono_amd64_start_gsharedvt_call);
1486 #endif
1487
1488         if (!mono_aot_only)
1489                 bp_trampoline = mini_get_breakpoint_trampoline ();
1490 }
1491
1492 /*
1493  * Cleanup architecture specific code.
1494  */
1495 void
1496 mono_arch_cleanup (void)
1497 {
1498         mono_os_mutex_destroy (&mini_arch_mutex);
1499 #if defined(__native_client_codegen__)
1500         mono_native_tls_free (nacl_instruction_depth);
1501         mono_native_tls_free (nacl_rex_tag);
1502         mono_native_tls_free (nacl_legacy_prefix_tag);
1503 #endif
1504 }
1505
1506 /*
1507  * This function returns the optimizations supported on this cpu.
1508  */
1509 guint32
1510 mono_arch_cpu_optimizations (guint32 *exclude_mask)
1511 {
1512         guint32 opts = 0;
1513
1514         *exclude_mask = 0;
1515
1516         if (mono_hwcap_x86_has_cmov) {
1517                 opts |= MONO_OPT_CMOV;
1518
1519                 if (mono_hwcap_x86_has_fcmov)
1520                         opts |= MONO_OPT_FCMOV;
1521                 else
1522                         *exclude_mask |= MONO_OPT_FCMOV;
1523         } else {
1524                 *exclude_mask |= MONO_OPT_CMOV;
1525         }
1526
1527         return opts;
1528 }
1529
1530 /*
1531  * This function test for all SSE functions supported.
1532  *
1533  * Returns a bitmask corresponding to all supported versions.
1534  *
1535  */
1536 guint32
1537 mono_arch_cpu_enumerate_simd_versions (void)
1538 {
1539         guint32 sse_opts = 0;
1540
1541         if (mono_hwcap_x86_has_sse1)
1542                 sse_opts |= SIMD_VERSION_SSE1;
1543
1544         if (mono_hwcap_x86_has_sse2)
1545                 sse_opts |= SIMD_VERSION_SSE2;
1546
1547         if (mono_hwcap_x86_has_sse3)
1548                 sse_opts |= SIMD_VERSION_SSE3;
1549
1550         if (mono_hwcap_x86_has_ssse3)
1551                 sse_opts |= SIMD_VERSION_SSSE3;
1552
1553         if (mono_hwcap_x86_has_sse41)
1554                 sse_opts |= SIMD_VERSION_SSE41;
1555
1556         if (mono_hwcap_x86_has_sse42)
1557                 sse_opts |= SIMD_VERSION_SSE42;
1558
1559         if (mono_hwcap_x86_has_sse4a)
1560                 sse_opts |= SIMD_VERSION_SSE4a;
1561
1562         return sse_opts;
1563 }
1564
1565 #ifndef DISABLE_JIT
1566
1567 GList *
1568 mono_arch_get_allocatable_int_vars (MonoCompile *cfg)
1569 {
1570         GList *vars = NULL;
1571         int i;
1572
1573         for (i = 0; i < cfg->num_varinfo; i++) {
1574                 MonoInst *ins = cfg->varinfo [i];
1575                 MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
1576
1577                 /* unused vars */
1578                 if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
1579                         continue;
1580
1581                 if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
1582                     (ins->opcode != OP_LOCAL && ins->opcode != OP_ARG))
1583                         continue;
1584
1585                 if (mono_is_regsize_var (ins->inst_vtype)) {
1586                         g_assert (MONO_VARINFO (cfg, i)->reg == -1);
1587                         g_assert (i == vmv->idx);
1588                         vars = g_list_prepend (vars, vmv);
1589                 }
1590         }
1591
1592         vars = mono_varlist_sort (cfg, vars, 0);
1593
1594         return vars;
1595 }
1596
1597 /**
1598  * mono_arch_compute_omit_fp:
1599  *
1600  *   Determine whenever the frame pointer can be eliminated.
1601  */
1602 static void
1603 mono_arch_compute_omit_fp (MonoCompile *cfg)
1604 {
1605         MonoMethodSignature *sig;
1606         MonoMethodHeader *header;
1607         int i, locals_size;
1608         CallInfo *cinfo;
1609
1610         if (cfg->arch.omit_fp_computed)
1611                 return;
1612
1613         header = cfg->header;
1614
1615         sig = mono_method_signature (cfg->method);
1616
1617         if (!cfg->arch.cinfo)
1618                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
1619         cinfo = (CallInfo *)cfg->arch.cinfo;
1620
1621         /*
1622          * FIXME: Remove some of the restrictions.
1623          */
1624         cfg->arch.omit_fp = TRUE;
1625         cfg->arch.omit_fp_computed = TRUE;
1626
1627 #ifdef __native_client_codegen__
1628         /* NaCl modules may not change the value of RBP, so it cannot be */
1629         /* used as a normal register, but it can be used as a frame pointer*/
1630         cfg->disable_omit_fp = TRUE;
1631         cfg->arch.omit_fp = FALSE;
1632 #endif
1633
1634         if (cfg->disable_omit_fp)
1635                 cfg->arch.omit_fp = FALSE;
1636
1637         if (!debug_omit_fp ())
1638                 cfg->arch.omit_fp = FALSE;
1639         /*
1640         if (cfg->method->save_lmf)
1641                 cfg->arch.omit_fp = FALSE;
1642         */
1643         if (cfg->flags & MONO_CFG_HAS_ALLOCA)
1644                 cfg->arch.omit_fp = FALSE;
1645         if (header->num_clauses)
1646                 cfg->arch.omit_fp = FALSE;
1647         if (cfg->param_area)
1648                 cfg->arch.omit_fp = FALSE;
1649         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG))
1650                 cfg->arch.omit_fp = FALSE;
1651         if ((mono_jit_trace_calls != NULL && mono_trace_eval (cfg->method)) ||
1652                 (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE))
1653                 cfg->arch.omit_fp = FALSE;
1654         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1655                 ArgInfo *ainfo = &cinfo->args [i];
1656
1657                 if (ainfo->storage == ArgOnStack) {
1658                         /*
1659                          * The stack offset can only be determined when the frame
1660                          * size is known.
1661                          */
1662                         cfg->arch.omit_fp = FALSE;
1663                 }
1664         }
1665
1666         locals_size = 0;
1667         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1668                 MonoInst *ins = cfg->varinfo [i];
1669                 int ialign;
1670
1671                 locals_size += mono_type_size (ins->inst_vtype, &ialign);
1672         }
1673 }
1674
1675 GList *
1676 mono_arch_get_global_int_regs (MonoCompile *cfg)
1677 {
1678         GList *regs = NULL;
1679
1680         mono_arch_compute_omit_fp (cfg);
1681
1682         if (cfg->arch.omit_fp)
1683                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1684
1685         /* We use the callee saved registers for global allocation */
1686         regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1687         regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1688         regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1689         regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1690 #ifndef __native_client_codegen__
1691         regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1692 #endif
1693 #ifdef TARGET_WIN32
1694         regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1695         regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1696 #endif
1697
1698         return regs;
1699 }
1700
1701 GList*
1702 mono_arch_get_global_fp_regs (MonoCompile *cfg)
1703 {
1704         GList *regs = NULL;
1705         int i;
1706
1707         /* All XMM registers */
1708         for (i = 0; i < 16; ++i)
1709                 regs = g_list_prepend (regs, GINT_TO_POINTER (i));
1710
1711         return regs;
1712 }
1713
1714 GList*
1715 mono_arch_get_iregs_clobbered_by_call (MonoCallInst *call)
1716 {
1717         static GList *r = NULL;
1718
1719         if (r == NULL) {
1720                 GList *regs = NULL;
1721
1722                 regs = g_list_prepend (regs, (gpointer)AMD64_RBP);
1723                 regs = g_list_prepend (regs, (gpointer)AMD64_RBX);
1724                 regs = g_list_prepend (regs, (gpointer)AMD64_R12);
1725                 regs = g_list_prepend (regs, (gpointer)AMD64_R13);
1726                 regs = g_list_prepend (regs, (gpointer)AMD64_R14);
1727 #ifndef __native_client_codegen__
1728                 regs = g_list_prepend (regs, (gpointer)AMD64_R15);
1729 #endif
1730
1731                 regs = g_list_prepend (regs, (gpointer)AMD64_R10);
1732                 regs = g_list_prepend (regs, (gpointer)AMD64_R9);
1733                 regs = g_list_prepend (regs, (gpointer)AMD64_R8);
1734                 regs = g_list_prepend (regs, (gpointer)AMD64_RDI);
1735                 regs = g_list_prepend (regs, (gpointer)AMD64_RSI);
1736                 regs = g_list_prepend (regs, (gpointer)AMD64_RDX);
1737                 regs = g_list_prepend (regs, (gpointer)AMD64_RCX);
1738                 regs = g_list_prepend (regs, (gpointer)AMD64_RAX);
1739
1740                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1741         }
1742
1743         return r;
1744 }
1745
1746 GList*
1747 mono_arch_get_fregs_clobbered_by_call (MonoCallInst *call)
1748 {
1749         int i;
1750         static GList *r = NULL;
1751
1752         if (r == NULL) {
1753                 GList *regs = NULL;
1754
1755                 for (i = 0; i < AMD64_XMM_NREG; ++i)
1756                         regs = g_list_prepend (regs, GINT_TO_POINTER (MONO_MAX_IREGS + i));
1757
1758                 InterlockedCompareExchangePointer ((gpointer*)&r, regs, NULL);
1759         }
1760
1761         return r;
1762 }
1763
1764 /*
1765  * mono_arch_regalloc_cost:
1766  *
1767  *  Return the cost, in number of memory references, of the action of
1768  * allocating the variable VMV into a register during global register
1769  * allocation.
1770  */
1771 guint32
1772 mono_arch_regalloc_cost (MonoCompile *cfg, MonoMethodVar *vmv)
1773 {
1774         MonoInst *ins = cfg->varinfo [vmv->idx];
1775
1776         if (cfg->method->save_lmf)
1777                 /* The register is already saved */
1778                 /* substract 1 for the invisible store in the prolog */
1779                 return (ins->opcode == OP_ARG) ? 0 : 1;
1780         else
1781                 /* push+pop */
1782                 return (ins->opcode == OP_ARG) ? 1 : 2;
1783 }
1784
1785 /*
1786  * mono_arch_fill_argument_info:
1787  *
1788  *   Populate cfg->args, cfg->ret and cfg->vret_addr with information about the arguments
1789  * of the method.
1790  */
1791 void
1792 mono_arch_fill_argument_info (MonoCompile *cfg)
1793 {
1794         MonoType *sig_ret;
1795         MonoMethodSignature *sig;
1796         MonoInst *ins;
1797         int i;
1798         CallInfo *cinfo;
1799
1800         sig = mono_method_signature (cfg->method);
1801
1802         cinfo = (CallInfo *)cfg->arch.cinfo;
1803         sig_ret = mini_get_underlying_type (sig->ret);
1804
1805         /*
1806          * Contrary to mono_arch_allocate_vars (), the information should describe
1807          * where the arguments are at the beginning of the method, not where they can be
1808          * accessed during the execution of the method. The later makes no sense for the
1809          * global register allocator, since a variable can be in more than one location.
1810          */
1811         switch (cinfo->ret.storage) {
1812         case ArgInIReg:
1813         case ArgInFloatSSEReg:
1814         case ArgInDoubleSSEReg:
1815                 cfg->ret->opcode = OP_REGVAR;
1816                 cfg->ret->inst_c0 = cinfo->ret.reg;
1817                 break;
1818         case ArgValuetypeInReg:
1819                 cfg->ret->opcode = OP_REGOFFSET;
1820                 cfg->ret->inst_basereg = -1;
1821                 cfg->ret->inst_offset = -1;
1822                 break;
1823         case ArgNone:
1824                 break;
1825         default:
1826                 g_assert_not_reached ();
1827         }
1828
1829         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1830                 ArgInfo *ainfo = &cinfo->args [i];
1831
1832                 ins = cfg->args [i];
1833
1834                 switch (ainfo->storage) {
1835                 case ArgInIReg:
1836                 case ArgInFloatSSEReg:
1837                 case ArgInDoubleSSEReg:
1838                         ins->opcode = OP_REGVAR;
1839                         ins->inst_c0 = ainfo->reg;
1840                         break;
1841                 case ArgOnStack:
1842                         ins->opcode = OP_REGOFFSET;
1843                         ins->inst_basereg = -1;
1844                         ins->inst_offset = -1;
1845                         break;
1846                 case ArgValuetypeInReg:
1847                         /* Dummy */
1848                         ins->opcode = OP_NOP;
1849                         break;
1850                 default:
1851                         g_assert_not_reached ();
1852                 }
1853         }
1854 }
1855
1856 void
1857 mono_arch_allocate_vars (MonoCompile *cfg)
1858 {
1859         MonoType *sig_ret;
1860         MonoMethodSignature *sig;
1861         MonoInst *ins;
1862         int i, offset;
1863         guint32 locals_stack_size, locals_stack_align;
1864         gint32 *offsets;
1865         CallInfo *cinfo;
1866
1867         sig = mono_method_signature (cfg->method);
1868
1869         cinfo = (CallInfo *)cfg->arch.cinfo;
1870         sig_ret = mini_get_underlying_type (sig->ret);
1871
1872         mono_arch_compute_omit_fp (cfg);
1873
1874         /*
1875          * We use the ABI calling conventions for managed code as well.
1876          * Exception: valuetypes are only sometimes passed or returned in registers.
1877          */
1878
1879         /*
1880          * The stack looks like this:
1881          * <incoming arguments passed on the stack>
1882          * <return value>
1883          * <lmf/caller saved registers>
1884          * <locals>
1885          * <spill area>
1886          * <localloc area>  -> grows dynamically
1887          * <params area>
1888          */
1889
1890         if (cfg->arch.omit_fp) {
1891                 cfg->flags |= MONO_CFG_HAS_SPILLUP;
1892                 cfg->frame_reg = AMD64_RSP;
1893                 offset = 0;
1894         } else {
1895                 /* Locals are allocated backwards from %fp */
1896                 cfg->frame_reg = AMD64_RBP;
1897                 offset = 0;
1898         }
1899
1900         cfg->arch.saved_iregs = cfg->used_int_regs;
1901         if (cfg->method->save_lmf)
1902                 /* Save all callee-saved registers normally, and restore them when unwinding through an LMF */
1903                 cfg->arch.saved_iregs |= (1 << AMD64_RBX) | (1 << AMD64_R12) | (1 << AMD64_R13) | (1 << AMD64_R14) | (1 << AMD64_R15);
1904
1905         if (cfg->arch.omit_fp)
1906                 cfg->arch.reg_save_area_offset = offset;
1907         /* Reserve space for callee saved registers */
1908         for (i = 0; i < AMD64_NREG; ++i)
1909                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
1910                         offset += sizeof(mgreg_t);
1911                 }
1912         if (!cfg->arch.omit_fp)
1913                 cfg->arch.reg_save_area_offset = -offset;
1914
1915         if (sig_ret->type != MONO_TYPE_VOID) {
1916                 switch (cinfo->ret.storage) {
1917                 case ArgInIReg:
1918                 case ArgInFloatSSEReg:
1919                 case ArgInDoubleSSEReg:
1920                         cfg->ret->opcode = OP_REGVAR;
1921                         cfg->ret->inst_c0 = cinfo->ret.reg;
1922                         cfg->ret->dreg = cinfo->ret.reg;
1923                         break;
1924                 case ArgValuetypeAddrInIReg:
1925                         /* The register is volatile */
1926                         cfg->vret_addr->opcode = OP_REGOFFSET;
1927                         cfg->vret_addr->inst_basereg = cfg->frame_reg;
1928                         if (cfg->arch.omit_fp) {
1929                                 cfg->vret_addr->inst_offset = offset;
1930                                 offset += 8;
1931                         } else {
1932                                 offset += 8;
1933                                 cfg->vret_addr->inst_offset = -offset;
1934                         }
1935                         if (G_UNLIKELY (cfg->verbose_level > 1)) {
1936                                 printf ("vret_addr =");
1937                                 mono_print_ins (cfg->vret_addr);
1938                         }
1939                         break;
1940                 case ArgValuetypeInReg:
1941                         /* Allocate a local to hold the result, the epilog will copy it to the correct place */
1942                         cfg->ret->opcode = OP_REGOFFSET;
1943                         cfg->ret->inst_basereg = cfg->frame_reg;
1944                         if (cfg->arch.omit_fp) {
1945                                 cfg->ret->inst_offset = offset;
1946                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1947                         } else {
1948                                 offset += cinfo->ret.pair_storage [1] == ArgNone ? 8 : 16;
1949                                 cfg->ret->inst_offset = - offset;
1950                         }
1951                         break;
1952                 default:
1953                         g_assert_not_reached ();
1954                 }
1955         }
1956
1957         /* Allocate locals */
1958         offsets = mono_allocate_stack_slots (cfg, cfg->arch.omit_fp ? FALSE: TRUE, &locals_stack_size, &locals_stack_align);
1959         if (locals_stack_size > MONO_ARCH_MAX_FRAME_SIZE) {
1960                 char *mname = mono_method_full_name (cfg->method, TRUE);
1961                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Method %s stack is too big.", mname));
1962                 g_free (mname);
1963                 return;
1964         }
1965
1966         if (locals_stack_align) {
1967                 offset += (locals_stack_align - 1);
1968                 offset &= ~(locals_stack_align - 1);
1969         }
1970         if (cfg->arch.omit_fp) {
1971                 cfg->locals_min_stack_offset = offset;
1972                 cfg->locals_max_stack_offset = offset + locals_stack_size;
1973         } else {
1974                 cfg->locals_min_stack_offset = - (offset + locals_stack_size);
1975                 cfg->locals_max_stack_offset = - offset;
1976         }
1977
1978         for (i = cfg->locals_start; i < cfg->num_varinfo; i++) {
1979                 if (offsets [i] != -1) {
1980                         MonoInst *ins = cfg->varinfo [i];
1981                         ins->opcode = OP_REGOFFSET;
1982                         ins->inst_basereg = cfg->frame_reg;
1983                         if (cfg->arch.omit_fp)
1984                                 ins->inst_offset = (offset + offsets [i]);
1985                         else
1986                                 ins->inst_offset = - (offset + offsets [i]);
1987                         //printf ("allocated local %d to ", i); mono_print_tree_nl (ins);
1988                 }
1989         }
1990         offset += locals_stack_size;
1991
1992         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG)) {
1993                 g_assert (!cfg->arch.omit_fp);
1994                 g_assert (cinfo->sig_cookie.storage == ArgOnStack);
1995                 cfg->sig_cookie = cinfo->sig_cookie.offset + ARGS_OFFSET;
1996         }
1997
1998         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
1999                 ins = cfg->args [i];
2000                 if (ins->opcode != OP_REGVAR) {
2001                         ArgInfo *ainfo = &cinfo->args [i];
2002                         gboolean inreg = TRUE;
2003
2004                         /* FIXME: Allocate volatile arguments to registers */
2005                         if (ins->flags & (MONO_INST_VOLATILE|MONO_INST_INDIRECT))
2006                                 inreg = FALSE;
2007
2008                         /*
2009                          * Under AMD64, all registers used to pass arguments to functions
2010                          * are volatile across calls.
2011                          * FIXME: Optimize this.
2012                          */
2013                         if ((ainfo->storage == ArgInIReg) || (ainfo->storage == ArgInFloatSSEReg) || (ainfo->storage == ArgInDoubleSSEReg) || (ainfo->storage == ArgValuetypeInReg) || (ainfo->storage == ArgGSharedVtInReg))
2014                                 inreg = FALSE;
2015
2016                         ins->opcode = OP_REGOFFSET;
2017
2018                         switch (ainfo->storage) {
2019                         case ArgInIReg:
2020                         case ArgInFloatSSEReg:
2021                         case ArgInDoubleSSEReg:
2022                         case ArgGSharedVtInReg:
2023                                 if (inreg) {
2024                                         ins->opcode = OP_REGVAR;
2025                                         ins->dreg = ainfo->reg;
2026                                 }
2027                                 break;
2028                         case ArgOnStack:
2029                         case ArgGSharedVtOnStack:
2030                                 g_assert (!cfg->arch.omit_fp);
2031                                 ins->opcode = OP_REGOFFSET;
2032                                 ins->inst_basereg = cfg->frame_reg;
2033                                 ins->inst_offset = ainfo->offset + ARGS_OFFSET;
2034                                 break;
2035                         case ArgValuetypeInReg:
2036                                 break;
2037                         case ArgValuetypeAddrInIReg: {
2038                                 MonoInst *indir;
2039                                 g_assert (!cfg->arch.omit_fp);
2040
2041                                 MONO_INST_NEW (cfg, indir, 0);
2042                                 indir->opcode = OP_REGOFFSET;
2043                                 if (ainfo->pair_storage [0] == ArgInIReg) {
2044                                         indir->inst_basereg = cfg->frame_reg;
2045                                         offset = ALIGN_TO (offset, sizeof (gpointer));
2046                                         offset += (sizeof (gpointer));
2047                                         indir->inst_offset = - offset;
2048                                 }
2049                                 else {
2050                                         indir->inst_basereg = cfg->frame_reg;
2051                                         indir->inst_offset = ainfo->offset + ARGS_OFFSET;
2052                                 }
2053
2054                                 ins->opcode = OP_VTARG_ADDR;
2055                                 ins->inst_left = indir;
2056
2057                                 break;
2058                         }
2059                         default:
2060                                 NOT_IMPLEMENTED;
2061                         }
2062
2063                         if (!inreg && (ainfo->storage != ArgOnStack) && (ainfo->storage != ArgValuetypeAddrInIReg) && (ainfo->storage != ArgGSharedVtOnStack)) {
2064                                 ins->opcode = OP_REGOFFSET;
2065                                 ins->inst_basereg = cfg->frame_reg;
2066                                 /* These arguments are saved to the stack in the prolog */
2067                                 offset = ALIGN_TO (offset, sizeof(mgreg_t));
2068                                 if (cfg->arch.omit_fp) {
2069                                         ins->inst_offset = offset;
2070                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2071                                         // Arguments are yet supported by the stack map creation code
2072                                         //cfg->locals_max_stack_offset = MAX (cfg->locals_max_stack_offset, offset);
2073                                 } else {
2074                                         offset += (ainfo->storage == ArgValuetypeInReg) ? ainfo->nregs * sizeof (mgreg_t) : sizeof (mgreg_t);
2075                                         ins->inst_offset = - offset;
2076                                         //cfg->locals_min_stack_offset = MIN (cfg->locals_min_stack_offset, offset);
2077                                 }
2078                         }
2079                 }
2080         }
2081
2082         cfg->stack_offset = offset;
2083 }
2084
2085 void
2086 mono_arch_create_vars (MonoCompile *cfg)
2087 {
2088         MonoMethodSignature *sig;
2089         CallInfo *cinfo;
2090         MonoType *sig_ret;
2091
2092         sig = mono_method_signature (cfg->method);
2093
2094         if (!cfg->arch.cinfo)
2095                 cfg->arch.cinfo = get_call_info (cfg->mempool, sig);
2096         cinfo = (CallInfo *)cfg->arch.cinfo;
2097
2098         if (cinfo->ret.storage == ArgValuetypeInReg)
2099                 cfg->ret_var_is_local = TRUE;
2100
2101         sig_ret = mini_get_underlying_type (sig->ret);
2102         if (cinfo->ret.storage == ArgValuetypeAddrInIReg) {
2103                 cfg->vret_addr = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_ARG);
2104                 if (G_UNLIKELY (cfg->verbose_level > 1)) {
2105                         printf ("vret_addr = ");
2106                         mono_print_ins (cfg->vret_addr);
2107                 }
2108         }
2109
2110         if (cfg->gen_sdb_seq_points) {
2111                 MonoInst *ins;
2112
2113                 if (cfg->compile_aot) {
2114                         MonoInst *ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2115                         ins->flags |= MONO_INST_VOLATILE;
2116                         cfg->arch.seq_point_info_var = ins;
2117                 }
2118                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2119                 ins->flags |= MONO_INST_VOLATILE;
2120                 cfg->arch.ss_tramp_var = ins;
2121
2122                 ins = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2123                 ins->flags |= MONO_INST_VOLATILE;
2124                 cfg->arch.bp_tramp_var = ins;
2125         }
2126
2127         if (cfg->method->save_lmf)
2128                 cfg->create_lmf_var = TRUE;
2129
2130         if (cfg->method->save_lmf) {
2131                 cfg->lmf_ir = TRUE;
2132 #if !defined(TARGET_WIN32)
2133                 if (mono_get_lmf_tls_offset () != -1 && !optimize_for_xen)
2134                         cfg->lmf_ir_mono_lmf = TRUE;
2135 #endif
2136         }
2137 }
2138
2139 static void
2140 add_outarg_reg (MonoCompile *cfg, MonoCallInst *call, ArgStorage storage, int reg, MonoInst *tree)
2141 {
2142         MonoInst *ins;
2143
2144         switch (storage) {
2145         case ArgInIReg:
2146                 MONO_INST_NEW (cfg, ins, OP_MOVE);
2147                 ins->dreg = mono_alloc_ireg_copy (cfg, tree->dreg);
2148                 ins->sreg1 = tree->dreg;
2149                 MONO_ADD_INS (cfg->cbb, ins);
2150                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, FALSE);
2151                 break;
2152         case ArgInFloatSSEReg:
2153                 MONO_INST_NEW (cfg, ins, OP_AMD64_SET_XMMREG_R4);
2154                 ins->dreg = mono_alloc_freg (cfg);
2155                 ins->sreg1 = tree->dreg;
2156                 MONO_ADD_INS (cfg->cbb, ins);
2157
2158                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2159                 break;
2160         case ArgInDoubleSSEReg:
2161                 MONO_INST_NEW (cfg, ins, OP_FMOVE);
2162                 ins->dreg = mono_alloc_freg (cfg);
2163                 ins->sreg1 = tree->dreg;
2164                 MONO_ADD_INS (cfg->cbb, ins);
2165
2166                 mono_call_inst_add_outarg_reg (cfg, call, ins->dreg, reg, TRUE);
2167
2168                 break;
2169         default:
2170                 g_assert_not_reached ();
2171         }
2172 }
2173
2174 static int
2175 arg_storage_to_load_membase (ArgStorage storage)
2176 {
2177         switch (storage) {
2178         case ArgInIReg:
2179 #if defined(__mono_ilp32__)
2180                 return OP_LOADI8_MEMBASE;
2181 #else
2182                 return OP_LOAD_MEMBASE;
2183 #endif
2184         case ArgInDoubleSSEReg:
2185                 return OP_LOADR8_MEMBASE;
2186         case ArgInFloatSSEReg:
2187                 return OP_LOADR4_MEMBASE;
2188         default:
2189                 g_assert_not_reached ();
2190         }
2191
2192         return -1;
2193 }
2194
2195 static void
2196 emit_sig_cookie (MonoCompile *cfg, MonoCallInst *call, CallInfo *cinfo)
2197 {
2198         MonoMethodSignature *tmp_sig;
2199         int sig_reg;
2200
2201         if (call->tail_call)
2202                 NOT_IMPLEMENTED;
2203
2204         g_assert (cinfo->sig_cookie.storage == ArgOnStack);
2205
2206         /*
2207          * mono_ArgIterator_Setup assumes the signature cookie is
2208          * passed first and all the arguments which were before it are
2209          * passed on the stack after the signature. So compensate by
2210          * passing a different signature.
2211          */
2212         tmp_sig = mono_metadata_signature_dup_full (cfg->method->klass->image, call->signature);
2213         tmp_sig->param_count -= call->signature->sentinelpos;
2214         tmp_sig->sentinelpos = 0;
2215         memcpy (tmp_sig->params, call->signature->params + call->signature->sentinelpos, tmp_sig->param_count * sizeof (MonoType*));
2216
2217         sig_reg = mono_alloc_ireg (cfg);
2218         MONO_EMIT_NEW_SIGNATURECONST (cfg, sig_reg, tmp_sig);
2219
2220         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, cinfo->sig_cookie.offset, sig_reg);
2221 }
2222
2223 #ifdef ENABLE_LLVM
2224 static inline LLVMArgStorage
2225 arg_storage_to_llvm_arg_storage (MonoCompile *cfg, ArgStorage storage)
2226 {
2227         switch (storage) {
2228         case ArgInIReg:
2229                 return LLVMArgInIReg;
2230         case ArgNone:
2231                 return LLVMArgNone;
2232         case ArgGSharedVtInReg:
2233         case ArgGSharedVtOnStack:
2234                 return LLVMArgGSharedVt;
2235         default:
2236                 g_assert_not_reached ();
2237                 return LLVMArgNone;
2238         }
2239 }
2240
2241 LLVMCallInfo*
2242 mono_arch_get_llvm_call_info (MonoCompile *cfg, MonoMethodSignature *sig)
2243 {
2244         int i, n;
2245         CallInfo *cinfo;
2246         ArgInfo *ainfo;
2247         int j;
2248         LLVMCallInfo *linfo;
2249         MonoType *t, *sig_ret;
2250
2251         n = sig->param_count + sig->hasthis;
2252         sig_ret = mini_get_underlying_type (sig->ret);
2253
2254         cinfo = get_call_info (cfg->mempool, sig);
2255
2256         linfo = mono_mempool_alloc0 (cfg->mempool, sizeof (LLVMCallInfo) + (sizeof (LLVMArgInfo) * n));
2257
2258         /*
2259          * LLVM always uses the native ABI while we use our own ABI, the
2260          * only difference is the handling of vtypes:
2261          * - we only pass/receive them in registers in some cases, and only
2262          *   in 1 or 2 integer registers.
2263          */
2264         switch (cinfo->ret.storage) {
2265         case ArgNone:
2266                 linfo->ret.storage = LLVMArgNone;
2267                 break;
2268         case ArgInIReg:
2269         case ArgInFloatSSEReg:
2270         case ArgInDoubleSSEReg:
2271                 linfo->ret.storage = LLVMArgNormal;
2272                 break;
2273         case ArgValuetypeInReg: {
2274                 ainfo = &cinfo->ret;
2275
2276                 if (sig->pinvoke &&
2277                         (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2278                          ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2279                         cfg->exception_message = g_strdup ("pinvoke + vtype ret");
2280                         cfg->disable_llvm = TRUE;
2281                         return linfo;
2282                 }
2283
2284                 linfo->ret.storage = LLVMArgVtypeInReg;
2285                 for (j = 0; j < 2; ++j)
2286                         linfo->ret.pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2287                 break;
2288         }
2289         case ArgValuetypeAddrInIReg:
2290                 /* Vtype returned using a hidden argument */
2291                 linfo->ret.storage = LLVMArgVtypeRetAddr;
2292                 linfo->vret_arg_index = cinfo->vret_arg_index;
2293                 break;
2294         default:
2295                 g_assert_not_reached ();
2296                 break;
2297         }
2298
2299         for (i = 0; i < n; ++i) {
2300                 ainfo = cinfo->args + i;
2301
2302                 if (i >= sig->hasthis)
2303                         t = sig->params [i - sig->hasthis];
2304                 else
2305                         t = &mono_defaults.int_class->byval_arg;
2306
2307                 linfo->args [i].storage = LLVMArgNone;
2308
2309                 switch (ainfo->storage) {
2310                 case ArgInIReg:
2311                         linfo->args [i].storage = LLVMArgNormal;
2312                         break;
2313                 case ArgInDoubleSSEReg:
2314                 case ArgInFloatSSEReg:
2315                         linfo->args [i].storage = LLVMArgNormal;
2316                         break;
2317                 case ArgOnStack:
2318                         if (MONO_TYPE_ISSTRUCT (t))
2319                                 linfo->args [i].storage = LLVMArgVtypeByVal;
2320                         else
2321                                 linfo->args [i].storage = LLVMArgNormal;
2322                         break;
2323                 case ArgValuetypeInReg:
2324                         if (sig->pinvoke &&
2325                                 (ainfo->pair_storage [0] == ArgInFloatSSEReg || ainfo->pair_storage [0] == ArgInDoubleSSEReg ||
2326                                  ainfo->pair_storage [1] == ArgInFloatSSEReg || ainfo->pair_storage [1] == ArgInDoubleSSEReg)) {
2327                                 cfg->exception_message = g_strdup ("pinvoke + vtypes");
2328                                 cfg->disable_llvm = TRUE;
2329                                 return linfo;
2330                         }
2331
2332                         linfo->args [i].storage = LLVMArgVtypeInReg;
2333                         for (j = 0; j < 2; ++j)
2334                                 linfo->args [i].pair_storage [j] = arg_storage_to_llvm_arg_storage (cfg, ainfo->pair_storage [j]);
2335                         break;
2336                 case ArgGSharedVtInReg:
2337                 case ArgGSharedVtOnStack:
2338                         linfo->args [i].storage = LLVMArgGSharedVt;
2339                         break;
2340                 default:
2341                         cfg->exception_message = g_strdup ("ainfo->storage");
2342                         cfg->disable_llvm = TRUE;
2343                         break;
2344                 }
2345         }
2346
2347         return linfo;
2348 }
2349 #endif
2350
2351 void
2352 mono_arch_emit_call (MonoCompile *cfg, MonoCallInst *call)
2353 {
2354         MonoInst *arg, *in;
2355         MonoMethodSignature *sig;
2356         MonoType *sig_ret;
2357         int i, n;
2358         CallInfo *cinfo;
2359         ArgInfo *ainfo;
2360
2361         sig = call->signature;
2362         n = sig->param_count + sig->hasthis;
2363
2364         cinfo = get_call_info (cfg->mempool, sig);
2365
2366         sig_ret = sig->ret;
2367
2368         if (COMPILE_LLVM (cfg)) {
2369                 /* We shouldn't be called in the llvm case */
2370                 cfg->disable_llvm = TRUE;
2371                 return;
2372         }
2373
2374         /*
2375          * Emit all arguments which are passed on the stack to prevent register
2376          * allocation problems.
2377          */
2378         for (i = 0; i < n; ++i) {
2379                 MonoType *t;
2380                 ainfo = cinfo->args + i;
2381
2382                 in = call->args [i];
2383
2384                 if (sig->hasthis && i == 0)
2385                         t = &mono_defaults.object_class->byval_arg;
2386                 else
2387                         t = sig->params [i - sig->hasthis];
2388
2389                 t = mini_get_underlying_type (t);
2390                 //XXX what about ArgGSharedVtOnStack here?
2391                 if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call) {
2392                         if (!t->byref) {
2393                                 if (t->type == MONO_TYPE_R4)
2394                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER4_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2395                                 else if (t->type == MONO_TYPE_R8)
2396                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORER8_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2397                                 else
2398                                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2399                         } else {
2400                                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, in->dreg);
2401                         }
2402                         if (cfg->compute_gc_maps) {
2403                                 MonoInst *def;
2404
2405                                 EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, t);
2406                         }
2407                 }
2408         }
2409
2410         /*
2411          * Emit all parameters passed in registers in non-reverse order for better readability
2412          * and to help the optimization in emit_prolog ().
2413          */
2414         for (i = 0; i < n; ++i) {
2415                 ainfo = cinfo->args + i;
2416
2417                 in = call->args [i];
2418
2419                 if (ainfo->storage == ArgInIReg)
2420                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2421         }
2422
2423         for (i = n - 1; i >= 0; --i) {
2424                 MonoType *t;
2425
2426                 ainfo = cinfo->args + i;
2427
2428                 in = call->args [i];
2429
2430                 if (sig->hasthis && i == 0)
2431                         t = &mono_defaults.object_class->byval_arg;
2432                 else
2433                         t = sig->params [i - sig->hasthis];
2434                 t = mini_get_underlying_type (t);
2435
2436                 switch (ainfo->storage) {
2437                 case ArgInIReg:
2438                         /* Already done */
2439                         break;
2440                 case ArgInFloatSSEReg:
2441                 case ArgInDoubleSSEReg:
2442                         add_outarg_reg (cfg, call, ainfo->storage, ainfo->reg, in);
2443                         break;
2444                 case ArgOnStack:
2445                 case ArgValuetypeInReg:
2446                 case ArgValuetypeAddrInIReg:
2447                 case ArgGSharedVtInReg:
2448                 case ArgGSharedVtOnStack: {
2449                         if (ainfo->storage == ArgOnStack && !MONO_TYPE_ISSTRUCT (t) && !call->tail_call)
2450                                 /* Already emitted above */
2451                                 break;
2452                         //FIXME what about ArgGSharedVtOnStack ?
2453                         if (ainfo->storage == ArgOnStack && call->tail_call) {
2454                                 MonoInst *call_inst = (MonoInst*)call;
2455                                 cfg->args [i]->flags |= MONO_INST_VOLATILE;
2456                                 EMIT_NEW_ARGSTORE (cfg, call_inst, i, in);
2457                                 break;
2458                         }
2459
2460                         guint32 align;
2461                         guint32 size;
2462
2463                         if (sig->pinvoke)
2464                                 size = mono_type_native_stack_size (t, &align);
2465                         else {
2466                                 /*
2467                                  * Other backends use mono_type_stack_size (), but that
2468                                  * aligns the size to 8, which is larger than the size of
2469                                  * the source, leading to reads of invalid memory if the
2470                                  * source is at the end of address space.
2471                                  */
2472                                 size = mono_class_value_size (mono_class_from_mono_type (t), &align);
2473                         }
2474
2475                         if (size >= 10000) {
2476                                 /* Avoid asserts in emit_memcpy () */
2477                                 mono_cfg_set_exception_invalid_program (cfg, g_strdup_printf ("Passing an argument of size '%d'.", size));
2478                                 /* Continue normally */
2479                         }
2480
2481                         if (size > 0) {
2482                                 MONO_INST_NEW (cfg, arg, OP_OUTARG_VT);
2483                                 arg->sreg1 = in->dreg;
2484                                 arg->klass = mono_class_from_mono_type (t);
2485                                 arg->backend.size = size;
2486                                 arg->inst_p0 = call;
2487                                 arg->inst_p1 = mono_mempool_alloc (cfg->mempool, sizeof (ArgInfo));
2488                                 memcpy (arg->inst_p1, ainfo, sizeof (ArgInfo));
2489
2490                                 MONO_ADD_INS (cfg->cbb, arg);
2491                         }
2492                         break;
2493                 }
2494                 default:
2495                         g_assert_not_reached ();
2496                 }
2497
2498                 if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (i == sig->sentinelpos))
2499                         /* Emit the signature cookie just before the implicit arguments */
2500                         emit_sig_cookie (cfg, call, cinfo);
2501         }
2502
2503         /* Handle the case where there are no implicit arguments */
2504         if (!sig->pinvoke && (sig->call_convention == MONO_CALL_VARARG) && (n == sig->sentinelpos))
2505                 emit_sig_cookie (cfg, call, cinfo);
2506
2507         switch (cinfo->ret.storage) {
2508         case ArgValuetypeInReg:
2509                 if (cinfo->ret.pair_storage [0] == ArgInIReg && cinfo->ret.pair_storage [1] == ArgNone) {
2510                         /*
2511                          * Tell the JIT to use a more efficient calling convention: call using
2512                          * OP_CALL, compute the result location after the call, and save the
2513                          * result there.
2514                          */
2515                         call->vret_in_reg = TRUE;
2516                         /*
2517                          * Nullify the instruction computing the vret addr to enable
2518                          * future optimizations.
2519                          */
2520                         if (call->vret_var)
2521                                 NULLIFY_INS (call->vret_var);
2522                 } else {
2523                         if (call->tail_call)
2524                                 NOT_IMPLEMENTED;
2525                         /*
2526                          * The valuetype is in RAX:RDX after the call, need to be copied to
2527                          * the stack. Push the address here, so the call instruction can
2528                          * access it.
2529                          */
2530                         if (!cfg->arch.vret_addr_loc) {
2531                                 cfg->arch.vret_addr_loc = mono_compile_create_var (cfg, &mono_defaults.int_class->byval_arg, OP_LOCAL);
2532                                 /* Prevent it from being register allocated or optimized away */
2533                                 ((MonoInst*)cfg->arch.vret_addr_loc)->flags |= MONO_INST_VOLATILE;
2534                         }
2535
2536                         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, ((MonoInst*)cfg->arch.vret_addr_loc)->dreg, call->vret_var->dreg);
2537                 }
2538                 break;
2539         case ArgValuetypeAddrInIReg: {
2540                 MonoInst *vtarg;
2541                 MONO_INST_NEW (cfg, vtarg, OP_MOVE);
2542                 vtarg->sreg1 = call->vret_var->dreg;
2543                 vtarg->dreg = mono_alloc_preg (cfg);
2544                 MONO_ADD_INS (cfg->cbb, vtarg);
2545
2546                 mono_call_inst_add_outarg_reg (cfg, call, vtarg->dreg, cinfo->ret.reg, FALSE);
2547                 break;
2548         }
2549         default:
2550                 break;
2551         }
2552
2553         if (cfg->method->save_lmf) {
2554                 MONO_INST_NEW (cfg, arg, OP_AMD64_SAVE_SP_TO_LMF);
2555                 MONO_ADD_INS (cfg->cbb, arg);
2556         }
2557
2558         call->stack_usage = cinfo->stack_usage;
2559 }
2560
2561 void
2562 mono_arch_emit_outarg_vt (MonoCompile *cfg, MonoInst *ins, MonoInst *src)
2563 {
2564         MonoInst *arg;
2565         MonoCallInst *call = (MonoCallInst*)ins->inst_p0;
2566         ArgInfo *ainfo = (ArgInfo*)ins->inst_p1;
2567         int size = ins->backend.size;
2568
2569         switch (ainfo->storage) {
2570         case ArgValuetypeInReg: {
2571                 MonoInst *load;
2572                 int part;
2573
2574                 for (part = 0; part < 2; ++part) {
2575                         if (ainfo->pair_storage [part] == ArgNone)
2576                                 continue;
2577
2578                         MONO_INST_NEW (cfg, load, arg_storage_to_load_membase (ainfo->pair_storage [part]));
2579                         load->inst_basereg = src->dreg;
2580                         load->inst_offset = part * sizeof(mgreg_t);
2581
2582                         switch (ainfo->pair_storage [part]) {
2583                         case ArgInIReg:
2584                                 load->dreg = mono_alloc_ireg (cfg);
2585                                 break;
2586                         case ArgInDoubleSSEReg:
2587                         case ArgInFloatSSEReg:
2588                                 load->dreg = mono_alloc_freg (cfg);
2589                                 break;
2590                         default:
2591                                 g_assert_not_reached ();
2592                         }
2593                         MONO_ADD_INS (cfg->cbb, load);
2594
2595                         add_outarg_reg (cfg, call, ainfo->pair_storage [part], ainfo->pair_regs [part], load);
2596                 }
2597                 break;
2598         }
2599         case ArgValuetypeAddrInIReg: {
2600                 MonoInst *vtaddr, *load;
2601                 vtaddr = mono_compile_create_var (cfg, &ins->klass->byval_arg, OP_LOCAL);
2602
2603                 MONO_INST_NEW (cfg, load, OP_LDADDR);
2604                 cfg->has_indirection = TRUE;
2605                 load->inst_p0 = vtaddr;
2606                 vtaddr->flags |= MONO_INST_INDIRECT;
2607                 load->type = STACK_MP;
2608                 load->klass = vtaddr->klass;
2609                 load->dreg = mono_alloc_ireg (cfg);
2610                 MONO_ADD_INS (cfg->cbb, load);
2611                 mini_emit_memcpy (cfg, load->dreg, 0, src->dreg, 0, size, 4);
2612
2613                 if (ainfo->pair_storage [0] == ArgInIReg) {
2614                         MONO_INST_NEW (cfg, arg, OP_X86_LEA_MEMBASE);
2615                         arg->dreg = mono_alloc_ireg (cfg);
2616                         arg->sreg1 = load->dreg;
2617                         arg->inst_imm = 0;
2618                         MONO_ADD_INS (cfg->cbb, arg);
2619                         mono_call_inst_add_outarg_reg (cfg, call, arg->dreg, ainfo->pair_regs [0], FALSE);
2620                 } else {
2621                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, load->dreg);
2622                 }
2623                 break;
2624         }
2625         case ArgGSharedVtInReg:
2626                 /* Pass by addr */
2627                 mono_call_inst_add_outarg_reg (cfg, call, src->dreg, ainfo->reg, FALSE);
2628                 break;
2629         case ArgGSharedVtOnStack:
2630                 MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, src->dreg);
2631                 break;
2632         default:
2633                 if (size == 8) {
2634                         int dreg = mono_alloc_ireg (cfg);
2635
2636                         MONO_EMIT_NEW_LOAD_MEMBASE (cfg, dreg, src->dreg, 0);
2637                         MONO_EMIT_NEW_STORE_MEMBASE (cfg, OP_STORE_MEMBASE_REG, AMD64_RSP, ainfo->offset, dreg);
2638                 } else if (size <= 40) {
2639                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2640                 } else {
2641                         // FIXME: Code growth
2642                         mini_emit_memcpy (cfg, AMD64_RSP, ainfo->offset, src->dreg, 0, size, 4);
2643                 }
2644
2645                 if (cfg->compute_gc_maps) {
2646                         MonoInst *def;
2647                         EMIT_NEW_GC_PARAM_SLOT_LIVENESS_DEF (cfg, def, ainfo->offset, &ins->klass->byval_arg);
2648                 }
2649         }
2650 }
2651
2652 void
2653 mono_arch_emit_setret (MonoCompile *cfg, MonoMethod *method, MonoInst *val)
2654 {
2655         MonoType *ret = mini_get_underlying_type (mono_method_signature (method)->ret);
2656
2657         if (ret->type == MONO_TYPE_R4) {
2658                 if (COMPILE_LLVM (cfg))
2659                         MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2660                 else
2661                         MONO_EMIT_NEW_UNALU (cfg, OP_AMD64_SET_XMMREG_R4, cfg->ret->dreg, val->dreg);
2662                 return;
2663         } else if (ret->type == MONO_TYPE_R8) {
2664                 MONO_EMIT_NEW_UNALU (cfg, OP_FMOVE, cfg->ret->dreg, val->dreg);
2665                 return;
2666         }
2667
2668         MONO_EMIT_NEW_UNALU (cfg, OP_MOVE, cfg->ret->dreg, val->dreg);
2669 }
2670
2671 #endif /* DISABLE_JIT */
2672
2673 #define EMIT_COND_BRANCH(ins,cond,sign) \
2674         if (ins->inst_true_bb->native_offset) { \
2675                 x86_branch (code, cond, cfg->native_code + ins->inst_true_bb->native_offset, sign); \
2676         } else { \
2677                 mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_true_bb); \
2678                 if ((cfg->opt & MONO_OPT_BRANCH) && \
2679             x86_is_imm8 (ins->inst_true_bb->max_offset - offset)) \
2680                         x86_branch8 (code, cond, 0, sign); \
2681                 else \
2682                         x86_branch32 (code, cond, 0, sign); \
2683 }
2684
2685 typedef struct {
2686         MonoMethodSignature *sig;
2687         CallInfo *cinfo;
2688 } ArchDynCallInfo;
2689
2690 static gboolean
2691 dyn_call_supported (MonoMethodSignature *sig, CallInfo *cinfo)
2692 {
2693         int i;
2694
2695 #ifdef HOST_WIN32
2696         return FALSE;
2697 #endif
2698
2699         switch (cinfo->ret.storage) {
2700         case ArgNone:
2701         case ArgInIReg:
2702         case ArgInFloatSSEReg:
2703         case ArgInDoubleSSEReg:
2704                 break;
2705         case ArgValuetypeInReg: {
2706                 ArgInfo *ainfo = &cinfo->ret;
2707
2708                 if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2709                         return FALSE;
2710                 if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2711                         return FALSE;
2712                 break;
2713         }
2714         default:
2715                 return FALSE;
2716         }
2717
2718         for (i = 0; i < cinfo->nargs; ++i) {
2719                 ArgInfo *ainfo = &cinfo->args [i];
2720                 switch (ainfo->storage) {
2721                 case ArgInIReg:
2722                 case ArgInFloatSSEReg:
2723                 case ArgInDoubleSSEReg:
2724                         break;
2725                 case ArgValuetypeInReg:
2726                         if (ainfo->pair_storage [0] != ArgNone && ainfo->pair_storage [0] != ArgInIReg)
2727                                 return FALSE;
2728                         if (ainfo->pair_storage [1] != ArgNone && ainfo->pair_storage [1] != ArgInIReg)
2729                                 return FALSE;
2730                         break;
2731                 default:
2732                         return FALSE;
2733                 }
2734         }
2735
2736         return TRUE;
2737 }
2738
2739 /*
2740  * mono_arch_dyn_call_prepare:
2741  *
2742  *   Return a pointer to an arch-specific structure which contains information
2743  * needed by mono_arch_get_dyn_call_args (). Return NULL if OP_DYN_CALL is not
2744  * supported for SIG.
2745  * This function is equivalent to ffi_prep_cif in libffi.
2746  */
2747 MonoDynCallInfo*
2748 mono_arch_dyn_call_prepare (MonoMethodSignature *sig)
2749 {
2750         ArchDynCallInfo *info;
2751         CallInfo *cinfo;
2752
2753         cinfo = get_call_info (NULL, sig);
2754
2755         if (!dyn_call_supported (sig, cinfo)) {
2756                 g_free (cinfo);
2757                 return NULL;
2758         }
2759
2760         info = g_new0 (ArchDynCallInfo, 1);
2761         // FIXME: Preprocess the info to speed up get_dyn_call_args ().
2762         info->sig = sig;
2763         info->cinfo = cinfo;
2764
2765         return (MonoDynCallInfo*)info;
2766 }
2767
2768 /*
2769  * mono_arch_dyn_call_free:
2770  *
2771  *   Free a MonoDynCallInfo structure.
2772  */
2773 void
2774 mono_arch_dyn_call_free (MonoDynCallInfo *info)
2775 {
2776         ArchDynCallInfo *ainfo = (ArchDynCallInfo*)info;
2777
2778         g_free (ainfo->cinfo);
2779         g_free (ainfo);
2780 }
2781
2782 #if !defined(__native_client__)
2783 #define PTR_TO_GREG(ptr) (mgreg_t)(ptr)
2784 #define GREG_TO_PTR(greg) (gpointer)(greg)
2785 #else
2786 /* Correctly handle casts to/from 32-bit pointers without compiler warnings */
2787 #define PTR_TO_GREG(ptr) (mgreg_t)(uintptr_t)(ptr)
2788 #define GREG_TO_PTR(greg) (gpointer)(guint32)(greg)
2789 #endif
2790
2791 /*
2792  * mono_arch_get_start_dyn_call:
2793  *
2794  *   Convert the arguments ARGS to a format which can be passed to OP_DYN_CALL, and
2795  * store the result into BUF.
2796  * ARGS should be an array of pointers pointing to the arguments.
2797  * RET should point to a memory buffer large enought to hold the result of the
2798  * call.
2799  * This function should be as fast as possible, any work which does not depend
2800  * on the actual values of the arguments should be done in
2801  * mono_arch_dyn_call_prepare ().
2802  * start_dyn_call + OP_DYN_CALL + finish_dyn_call is equivalent to ffi_call in
2803  * libffi.
2804  */
2805 void
2806 mono_arch_start_dyn_call (MonoDynCallInfo *info, gpointer **args, guint8 *ret, guint8 *buf, int buf_len)
2807 {
2808         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2809         DynCallArgs *p = (DynCallArgs*)buf;
2810         int arg_index, greg, freg, i, pindex;
2811         MonoMethodSignature *sig = dinfo->sig;
2812         int buffer_offset = 0;
2813
2814         g_assert (buf_len >= sizeof (DynCallArgs));
2815
2816         p->res = 0;
2817         p->ret = ret;
2818
2819         arg_index = 0;
2820         greg = 0;
2821         freg = 0;
2822         pindex = 0;
2823
2824         if (sig->hasthis || dinfo->cinfo->vret_arg_index == 1) {
2825                 p->regs [greg ++] = PTR_TO_GREG(*(args [arg_index ++]));
2826                 if (!sig->hasthis)
2827                         pindex = 1;
2828         }
2829
2830         if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg)
2831                 p->regs [greg ++] = PTR_TO_GREG(ret);
2832
2833         for (i = pindex; i < sig->param_count; i++) {
2834                 MonoType *t = mini_get_underlying_type (sig->params [i]);
2835                 gpointer *arg = args [arg_index ++];
2836
2837                 if (t->byref) {
2838                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2839                         continue;
2840                 }
2841
2842                 switch (t->type) {
2843                 case MONO_TYPE_STRING:
2844                 case MONO_TYPE_CLASS:
2845                 case MONO_TYPE_ARRAY:
2846                 case MONO_TYPE_SZARRAY:
2847                 case MONO_TYPE_OBJECT:
2848                 case MONO_TYPE_PTR:
2849                 case MONO_TYPE_I:
2850                 case MONO_TYPE_U:
2851 #if !defined(__mono_ilp32__)
2852                 case MONO_TYPE_I8:
2853                 case MONO_TYPE_U8:
2854 #endif
2855                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2856                         p->regs [greg ++] = PTR_TO_GREG(*(arg));
2857                         break;
2858 #if defined(__mono_ilp32__)
2859                 case MONO_TYPE_I8:
2860                 case MONO_TYPE_U8:
2861                         g_assert (dinfo->cinfo->args [i + sig->hasthis].reg == param_regs [greg]);
2862                         p->regs [greg ++] = *(guint64*)(arg);
2863                         break;
2864 #endif
2865                 case MONO_TYPE_U1:
2866                         p->regs [greg ++] = *(guint8*)(arg);
2867                         break;
2868                 case MONO_TYPE_I1:
2869                         p->regs [greg ++] = *(gint8*)(arg);
2870                         break;
2871                 case MONO_TYPE_I2:
2872                         p->regs [greg ++] = *(gint16*)(arg);
2873                         break;
2874                 case MONO_TYPE_U2:
2875                         p->regs [greg ++] = *(guint16*)(arg);
2876                         break;
2877                 case MONO_TYPE_I4:
2878                         p->regs [greg ++] = *(gint32*)(arg);
2879                         break;
2880                 case MONO_TYPE_U4:
2881                         p->regs [greg ++] = *(guint32*)(arg);
2882                         break;
2883                 case MONO_TYPE_R4: {
2884                         double d;
2885
2886                         *(float*)&d = *(float*)(arg);
2887                         p->has_fp = 1;
2888                         p->fregs [freg ++] = d;
2889                         break;
2890                 }
2891                 case MONO_TYPE_R8:
2892                         p->has_fp = 1;
2893                         p->fregs [freg ++] = *(double*)(arg);
2894                         break;
2895                 case MONO_TYPE_GENERICINST:
2896                     if (MONO_TYPE_IS_REFERENCE (t)) {
2897                                 p->regs [greg ++] = PTR_TO_GREG(*(arg));
2898                                 break;
2899                         } else if (t->type == MONO_TYPE_GENERICINST && mono_class_is_nullable (mono_class_from_mono_type (t))) {
2900                                         MonoClass *klass = mono_class_from_mono_type (t);
2901                                         guint8 *nullable_buf;
2902                                         int size;
2903
2904                                         size = mono_class_value_size (klass, NULL);
2905                                         nullable_buf = p->buffer + buffer_offset;
2906                                         buffer_offset += size;
2907                                         g_assert (buffer_offset <= 256);
2908
2909                                         /* The argument pointed to by arg is either a boxed vtype or null */
2910                                         mono_nullable_init (nullable_buf, (MonoObject*)arg, klass);
2911
2912                                         arg = (gpointer*)nullable_buf;
2913                                         /* Fall though */
2914
2915                         } else {
2916                                 /* Fall through */
2917                         }
2918                 case MONO_TYPE_VALUETYPE: {
2919                         ArgInfo *ainfo = &dinfo->cinfo->args [i + sig->hasthis];
2920
2921                         g_assert (ainfo->storage == ArgValuetypeInReg);
2922                         if (ainfo->pair_storage [0] != ArgNone) {
2923                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
2924                                 p->regs [greg ++] = ((mgreg_t*)(arg))[0];
2925                         }
2926                         if (ainfo->pair_storage [1] != ArgNone) {
2927                                 g_assert (ainfo->pair_storage [1] == ArgInIReg);
2928                                 p->regs [greg ++] = ((mgreg_t*)(arg))[1];
2929                         }
2930                         break;
2931                 }
2932                 default:
2933                         g_assert_not_reached ();
2934                 }
2935         }
2936
2937         g_assert (greg <= PARAM_REGS);
2938 }
2939
2940 /*
2941  * mono_arch_finish_dyn_call:
2942  *
2943  *   Store the result of a dyn call into the return value buffer passed to
2944  * start_dyn_call ().
2945  * This function should be as fast as possible, any work which does not depend
2946  * on the actual values of the arguments should be done in
2947  * mono_arch_dyn_call_prepare ().
2948  */
2949 void
2950 mono_arch_finish_dyn_call (MonoDynCallInfo *info, guint8 *buf)
2951 {
2952         ArchDynCallInfo *dinfo = (ArchDynCallInfo*)info;
2953         MonoMethodSignature *sig = dinfo->sig;
2954         DynCallArgs *dargs = (DynCallArgs*)buf;
2955         guint8 *ret = dargs->ret;
2956         mgreg_t res = dargs->res;
2957         MonoType *sig_ret = mini_get_underlying_type (sig->ret);
2958
2959         switch (sig_ret->type) {
2960         case MONO_TYPE_VOID:
2961                 *(gpointer*)ret = NULL;
2962                 break;
2963         case MONO_TYPE_STRING:
2964         case MONO_TYPE_CLASS:
2965         case MONO_TYPE_ARRAY:
2966         case MONO_TYPE_SZARRAY:
2967         case MONO_TYPE_OBJECT:
2968         case MONO_TYPE_I:
2969         case MONO_TYPE_U:
2970         case MONO_TYPE_PTR:
2971                 *(gpointer*)ret = GREG_TO_PTR(res);
2972                 break;
2973         case MONO_TYPE_I1:
2974                 *(gint8*)ret = res;
2975                 break;
2976         case MONO_TYPE_U1:
2977                 *(guint8*)ret = res;
2978                 break;
2979         case MONO_TYPE_I2:
2980                 *(gint16*)ret = res;
2981                 break;
2982         case MONO_TYPE_U2:
2983                 *(guint16*)ret = res;
2984                 break;
2985         case MONO_TYPE_I4:
2986                 *(gint32*)ret = res;
2987                 break;
2988         case MONO_TYPE_U4:
2989                 *(guint32*)ret = res;
2990                 break;
2991         case MONO_TYPE_I8:
2992                 *(gint64*)ret = res;
2993                 break;
2994         case MONO_TYPE_U8:
2995                 *(guint64*)ret = res;
2996                 break;
2997         case MONO_TYPE_R4:
2998                 *(float*)ret = *(float*)&(dargs->fregs [0]);
2999                 break;
3000         case MONO_TYPE_R8:
3001                 *(double*)ret = dargs->fregs [0];
3002                 break;
3003         case MONO_TYPE_GENERICINST:
3004                 if (MONO_TYPE_IS_REFERENCE (sig_ret)) {
3005                         *(gpointer*)ret = GREG_TO_PTR(res);
3006                         break;
3007                 } else {
3008                         /* Fall through */
3009                 }
3010         case MONO_TYPE_VALUETYPE:
3011                 if (dinfo->cinfo->ret.storage == ArgValuetypeAddrInIReg) {
3012                         /* Nothing to do */
3013                 } else {
3014                         ArgInfo *ainfo = &dinfo->cinfo->ret;
3015
3016                         g_assert (ainfo->storage == ArgValuetypeInReg);
3017
3018                         if (ainfo->pair_storage [0] != ArgNone) {
3019                                 g_assert (ainfo->pair_storage [0] == ArgInIReg);
3020                                 ((mgreg_t*)ret)[0] = res;
3021                         }
3022
3023                         g_assert (ainfo->pair_storage [1] == ArgNone);
3024                 }
3025                 break;
3026         default:
3027                 g_assert_not_reached ();
3028         }
3029 }
3030
3031 /* emit an exception if condition is fail */
3032 #define EMIT_COND_SYSTEM_EXCEPTION(cond,signed,exc_name)            \
3033         do {                                                        \
3034                 MonoInst *tins = mono_branch_optimize_exception_target (cfg, bb, exc_name); \
3035                 if (tins == NULL) {                                                                             \
3036                         mono_add_patch_info (cfg, code - cfg->native_code,   \
3037                                         MONO_PATCH_INFO_EXC, exc_name);  \
3038                         x86_branch32 (code, cond, 0, signed);               \
3039                 } else {        \
3040                         EMIT_COND_BRANCH (tins, cond, signed);  \
3041                 }                       \
3042         } while (0);
3043
3044 #define EMIT_FPCOMPARE(code) do { \
3045         amd64_fcompp (code); \
3046         amd64_fnstsw (code); \
3047 } while (0);
3048
3049 #define EMIT_SSE2_FPFUNC(code, op, dreg, sreg1) do { \
3050     amd64_movsd_membase_reg (code, AMD64_RSP, -8, (sreg1)); \
3051         amd64_fld_membase (code, AMD64_RSP, -8, TRUE); \
3052         amd64_ ##op (code); \
3053         amd64_fst_membase (code, AMD64_RSP, -8, TRUE, TRUE); \
3054         amd64_movsd_reg_membase (code, (dreg), AMD64_RSP, -8); \
3055 } while (0);
3056
3057 static guint8*
3058 emit_call_body (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data)
3059 {
3060         gboolean no_patch = FALSE;
3061
3062         /*
3063          * FIXME: Add support for thunks
3064          */
3065         {
3066                 gboolean near_call = FALSE;
3067
3068                 /*
3069                  * Indirect calls are expensive so try to make a near call if possible.
3070                  * The caller memory is allocated by the code manager so it is
3071                  * guaranteed to be at a 32 bit offset.
3072                  */
3073
3074                 if (patch_type != MONO_PATCH_INFO_ABS) {
3075                         /* The target is in memory allocated using the code manager */
3076                         near_call = TRUE;
3077
3078                         if ((patch_type == MONO_PATCH_INFO_METHOD) || (patch_type == MONO_PATCH_INFO_METHOD_JUMP)) {
3079                                 if (((MonoMethod*)data)->klass->image->aot_module)
3080                                         /* The callee might be an AOT method */
3081                                         near_call = FALSE;
3082                                 if (((MonoMethod*)data)->dynamic)
3083                                         /* The target is in malloc-ed memory */
3084                                         near_call = FALSE;
3085                         }
3086
3087                         if (patch_type == MONO_PATCH_INFO_INTERNAL_METHOD) {
3088                                 /*
3089                                  * The call might go directly to a native function without
3090                                  * the wrapper.
3091                                  */
3092                                 MonoJitICallInfo *mi = mono_find_jit_icall_by_name ((const char *)data);
3093                                 if (mi) {
3094                                         gconstpointer target = mono_icall_get_wrapper (mi);
3095                                         if ((((guint64)target) >> 32) != 0)
3096                                                 near_call = FALSE;
3097                                 }
3098                         }
3099                 }
3100                 else {
3101                         MonoJumpInfo *jinfo = NULL;
3102
3103                         if (cfg->abs_patches)
3104                                 jinfo = (MonoJumpInfo *)g_hash_table_lookup (cfg->abs_patches, data);
3105                         if (jinfo) {
3106                                 if (jinfo->type == MONO_PATCH_INFO_JIT_ICALL_ADDR) {
3107                                         MonoJitICallInfo *mi = mono_find_jit_icall_by_name (jinfo->data.name);
3108                                         if (mi && (((guint64)mi->func) >> 32) == 0)
3109                                                 near_call = TRUE;
3110                                         no_patch = TRUE;
3111                                 } else {
3112                                         /*
3113                                          * This is not really an optimization, but required because the
3114                                          * generic class init trampolines use R11 to pass the vtable.
3115                                          */
3116                                         near_call = TRUE;
3117                                 }
3118                         } else {
3119                                 MonoJitICallInfo *info = mono_find_jit_icall_by_addr (data);
3120                                 if (info) {
3121                                         if (info->func == info->wrapper) {
3122                                                 /* No wrapper */
3123                                                 if ((((guint64)info->func) >> 32) == 0)
3124                                                         near_call = TRUE;
3125                                         }
3126                                         else {
3127                                                 /* See the comment in mono_codegen () */
3128                                                 if ((info->name [0] != 'v') || (strstr (info->name, "ves_array_new_va_") == NULL && strstr (info->name, "ves_array_element_address_") == NULL))
3129                                                         near_call = TRUE;
3130                                         }
3131                                 }
3132                                 else if ((((guint64)data) >> 32) == 0) {
3133                                         near_call = TRUE;
3134                                         no_patch = TRUE;
3135                                 }
3136                         }
3137                 }
3138
3139                 if (cfg->method->dynamic)
3140                         /* These methods are allocated using malloc */
3141                         near_call = FALSE;
3142
3143 #ifdef MONO_ARCH_NOMAP32BIT
3144                 near_call = FALSE;
3145 #endif
3146 #if defined(__native_client__)
3147                 /* Always use near_call == TRUE for Native Client */
3148                 near_call = TRUE;
3149 #endif
3150                 /* The 64bit XEN kernel does not honour the MAP_32BIT flag. (#522894) */
3151                 if (optimize_for_xen)
3152                         near_call = FALSE;
3153
3154                 if (cfg->compile_aot) {
3155                         near_call = TRUE;
3156                         no_patch = TRUE;
3157                 }
3158
3159                 if (near_call) {
3160                         /*
3161                          * Align the call displacement to an address divisible by 4 so it does
3162                          * not span cache lines. This is required for code patching to work on SMP
3163                          * systems.
3164                          */
3165                         if (!no_patch && ((guint32)(code + 1 - cfg->native_code) % 4) != 0) {
3166                                 guint32 pad_size = 4 - ((guint32)(code + 1 - cfg->native_code) % 4);
3167                                 amd64_padding (code, pad_size);
3168                         }
3169                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3170                         amd64_call_code (code, 0);
3171                 }
3172                 else {
3173                         mono_add_patch_info (cfg, code - cfg->native_code, patch_type, data);
3174                         amd64_set_reg_template (code, GP_SCRATCH_REG);
3175                         amd64_call_reg (code, GP_SCRATCH_REG);
3176                 }
3177         }
3178
3179         return code;
3180 }
3181
3182 static inline guint8*
3183 emit_call (MonoCompile *cfg, guint8 *code, MonoJumpInfoType patch_type, gconstpointer data, gboolean win64_adjust_stack)
3184 {
3185 #ifdef TARGET_WIN32
3186         if (win64_adjust_stack)
3187                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 32);
3188 #endif
3189         code = emit_call_body (cfg, code, patch_type, data);
3190 #ifdef TARGET_WIN32
3191         if (win64_adjust_stack)
3192                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 32);
3193 #endif
3194
3195         return code;
3196 }
3197
3198 static inline int
3199 store_membase_imm_to_store_membase_reg (int opcode)
3200 {
3201         switch (opcode) {
3202         case OP_STORE_MEMBASE_IMM:
3203                 return OP_STORE_MEMBASE_REG;
3204         case OP_STOREI4_MEMBASE_IMM:
3205                 return OP_STOREI4_MEMBASE_REG;
3206         case OP_STOREI8_MEMBASE_IMM:
3207                 return OP_STOREI8_MEMBASE_REG;
3208         }
3209
3210         return -1;
3211 }
3212
3213 #ifndef DISABLE_JIT
3214
3215 #define INST_IGNORES_CFLAGS(opcode) (!(((opcode) == OP_ADC) || ((opcode) == OP_ADC_IMM) || ((opcode) == OP_IADC) || ((opcode) == OP_IADC_IMM) || ((opcode) == OP_SBB) || ((opcode) == OP_SBB_IMM) || ((opcode) == OP_ISBB) || ((opcode) == OP_ISBB_IMM)))
3216
3217 /*
3218  * mono_arch_peephole_pass_1:
3219  *
3220  *   Perform peephole opts which should/can be performed before local regalloc
3221  */
3222 void
3223 mono_arch_peephole_pass_1 (MonoCompile *cfg, MonoBasicBlock *bb)
3224 {
3225         MonoInst *ins, *n;
3226
3227         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3228                 MonoInst *last_ins = mono_inst_prev (ins, FILTER_IL_SEQ_POINT);
3229
3230                 switch (ins->opcode) {
3231                 case OP_ADD_IMM:
3232                 case OP_IADD_IMM:
3233                 case OP_LADD_IMM:
3234                         if ((ins->sreg1 < MONO_MAX_IREGS) && (ins->dreg >= MONO_MAX_IREGS) && (ins->inst_imm > 0)) {
3235                                 /*
3236                                  * X86_LEA is like ADD, but doesn't have the
3237                                  * sreg1==dreg restriction. inst_imm > 0 is needed since LEA sign-extends
3238                                  * its operand to 64 bit.
3239                                  */
3240                                 ins->opcode = OP_X86_LEA_MEMBASE;
3241                                 ins->inst_basereg = ins->sreg1;
3242                         }
3243                         break;
3244                 case OP_LXOR:
3245                 case OP_IXOR:
3246                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3247                                 MonoInst *ins2;
3248
3249                                 /*
3250                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3251                                  * the latter has length 2-3 instead of 6 (reverse constant
3252                                  * propagation). These instruction sequences are very common
3253                                  * in the initlocals bblock.
3254                                  */
3255                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3256                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3257                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3258                                                 ins2->sreg1 = ins->dreg;
3259                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG)) {
3260                                                 /* Continue */
3261                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3262                                                 NULLIFY_INS (ins2);
3263                                                 /* Continue */
3264                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3265                                                 /* Continue */
3266                                         } else {
3267                                                 break;
3268                                         }
3269                                 }
3270                         }
3271                         break;
3272                 case OP_COMPARE_IMM:
3273                 case OP_LCOMPARE_IMM:
3274                         /* OP_COMPARE_IMM (reg, 0)
3275                          * -->
3276                          * OP_AMD64_TEST_NULL (reg)
3277                          */
3278                         if (!ins->inst_imm)
3279                                 ins->opcode = OP_AMD64_TEST_NULL;
3280                         break;
3281                 case OP_ICOMPARE_IMM:
3282                         if (!ins->inst_imm)
3283                                 ins->opcode = OP_X86_TEST_NULL;
3284                         break;
3285                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
3286                         /*
3287                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3288                          * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
3289                          * -->
3290                          * OP_STORE_MEMBASE_REG reg, offset(basereg)
3291                          * OP_COMPARE_IMM reg, imm
3292                          *
3293                          * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
3294                          */
3295                         if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
3296                             ins->inst_basereg == last_ins->inst_destbasereg &&
3297                             ins->inst_offset == last_ins->inst_offset) {
3298                                         ins->opcode = OP_ICOMPARE_IMM;
3299                                         ins->sreg1 = last_ins->sreg1;
3300
3301                                         /* check if we can remove cmp reg,0 with test null */
3302                                         if (!ins->inst_imm)
3303                                                 ins->opcode = OP_X86_TEST_NULL;
3304                                 }
3305
3306                         break;
3307                 }
3308
3309                 mono_peephole_ins (bb, ins);
3310         }
3311 }
3312
3313 void
3314 mono_arch_peephole_pass_2 (MonoCompile *cfg, MonoBasicBlock *bb)
3315 {
3316         MonoInst *ins, *n;
3317
3318         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3319                 switch (ins->opcode) {
3320                 case OP_ICONST:
3321                 case OP_I8CONST: {
3322                         MonoInst *next = mono_inst_next (ins, FILTER_IL_SEQ_POINT);
3323                         /* reg = 0 -> XOR (reg, reg) */
3324                         /* XOR sets cflags on x86, so we cant do it always */
3325                         if (ins->inst_c0 == 0 && (!next || (next && INST_IGNORES_CFLAGS (next->opcode)))) {
3326                                 ins->opcode = OP_LXOR;
3327                                 ins->sreg1 = ins->dreg;
3328                                 ins->sreg2 = ins->dreg;
3329                                 /* Fall through */
3330                         } else {
3331                                 break;
3332                         }
3333                 }
3334                 case OP_LXOR:
3335                         /*
3336                          * Use IXOR to avoid a rex prefix if possible. The cpu will sign extend the
3337                          * 0 result into 64 bits.
3338                          */
3339                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3340                                 ins->opcode = OP_IXOR;
3341                         }
3342                         /* Fall through */
3343                 case OP_IXOR:
3344                         if ((ins->sreg1 == ins->sreg2) && (ins->sreg1 == ins->dreg)) {
3345                                 MonoInst *ins2;
3346
3347                                 /*
3348                                  * Replace STORE_MEMBASE_IMM 0 with STORE_MEMBASE_REG since
3349                                  * the latter has length 2-3 instead of 6 (reverse constant
3350                                  * propagation). These instruction sequences are very common
3351                                  * in the initlocals bblock.
3352                                  */
3353                                 for (ins2 = ins->next; ins2; ins2 = ins2->next) {
3354                                         if (((ins2->opcode == OP_STORE_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_IMM) || (ins2->opcode == OP_STOREI8_MEMBASE_IMM) || (ins2->opcode == OP_STORE_MEMBASE_IMM)) && (ins2->inst_imm == 0)) {
3355                                                 ins2->opcode = store_membase_imm_to_store_membase_reg (ins2->opcode);
3356                                                 ins2->sreg1 = ins->dreg;
3357                                         } else if ((ins2->opcode == OP_STOREI1_MEMBASE_IMM) || (ins2->opcode == OP_STOREI2_MEMBASE_IMM) || (ins2->opcode == OP_STOREI4_MEMBASE_REG) || (ins2->opcode == OP_STOREI8_MEMBASE_REG) || (ins2->opcode == OP_STORE_MEMBASE_REG) || (ins2->opcode == OP_LIVERANGE_START) || (ins2->opcode == OP_GC_LIVENESS_DEF) || (ins2->opcode == OP_GC_LIVENESS_USE)) {
3358                                                 /* Continue */
3359                                         } else if (((ins2->opcode == OP_ICONST) || (ins2->opcode == OP_I8CONST)) && (ins2->dreg == ins->dreg) && (ins2->inst_c0 == 0)) {
3360                                                 NULLIFY_INS (ins2);
3361                                                 /* Continue */
3362                                         } else if (ins2->opcode == OP_IL_SEQ_POINT) {
3363                                                 /* Continue */
3364                                         } else {
3365                                                 break;
3366                                         }
3367                                 }
3368                         }
3369                         break;
3370                 case OP_IADD_IMM:
3371                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3372                                 ins->opcode = OP_X86_INC_REG;
3373                         break;
3374                 case OP_ISUB_IMM:
3375                         if ((ins->inst_imm == 1) && (ins->dreg == ins->sreg1))
3376                                 ins->opcode = OP_X86_DEC_REG;
3377                         break;
3378                 }
3379
3380                 mono_peephole_ins (bb, ins);
3381         }
3382 }
3383
3384 #define NEW_INS(cfg,ins,dest,op) do {   \
3385                 MONO_INST_NEW ((cfg), (dest), (op)); \
3386         (dest)->cil_code = (ins)->cil_code; \
3387         mono_bblock_insert_before_ins (bb, ins, (dest)); \
3388         } while (0)
3389
3390 /*
3391  * mono_arch_lowering_pass:
3392  *
3393  *  Converts complex opcodes into simpler ones so that each IR instruction
3394  * corresponds to one machine instruction.
3395  */
3396 void
3397 mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
3398 {
3399         MonoInst *ins, *n, *temp;
3400
3401         /*
3402          * FIXME: Need to add more instructions, but the current machine
3403          * description can't model some parts of the composite instructions like
3404          * cdq.
3405          */
3406         MONO_BB_FOR_EACH_INS_SAFE (bb, n, ins) {
3407                 switch (ins->opcode) {
3408                 case OP_DIV_IMM:
3409                 case OP_REM_IMM:
3410                 case OP_IDIV_IMM:
3411                 case OP_IDIV_UN_IMM:
3412                 case OP_IREM_UN_IMM:
3413                 case OP_LREM_IMM:
3414                 case OP_IREM_IMM:
3415                         mono_decompose_op_imm (cfg, bb, ins);
3416                         break;
3417                 case OP_COMPARE_IMM:
3418                 case OP_LCOMPARE_IMM:
3419                         if (!amd64_use_imm32 (ins->inst_imm)) {
3420                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3421                                 temp->inst_c0 = ins->inst_imm;
3422                                 temp->dreg = mono_alloc_ireg (cfg);
3423                                 ins->opcode = OP_COMPARE;
3424                                 ins->sreg2 = temp->dreg;
3425                         }
3426                         break;
3427 #ifndef __mono_ilp32__
3428                 case OP_LOAD_MEMBASE:
3429 #endif
3430                 case OP_LOADI8_MEMBASE:
3431 #ifndef __native_client_codegen__
3432                 /*  Don't generate memindex opcodes (to simplify */
3433                 /*  read sandboxing) */
3434                         if (!amd64_use_imm32 (ins->inst_offset)) {
3435                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3436                                 temp->inst_c0 = ins->inst_offset;
3437                                 temp->dreg = mono_alloc_ireg (cfg);
3438                                 ins->opcode = OP_AMD64_LOADI8_MEMINDEX;
3439                                 ins->inst_indexreg = temp->dreg;
3440                         }
3441 #endif
3442                         break;
3443 #ifndef __mono_ilp32__
3444                 case OP_STORE_MEMBASE_IMM:
3445 #endif
3446                 case OP_STOREI8_MEMBASE_IMM:
3447                         if (!amd64_use_imm32 (ins->inst_imm)) {
3448                                 NEW_INS (cfg, ins, temp, OP_I8CONST);
3449                                 temp->inst_c0 = ins->inst_imm;
3450                                 temp->dreg = mono_alloc_ireg (cfg);
3451                                 ins->opcode = OP_STOREI8_MEMBASE_REG;
3452                                 ins->sreg1 = temp->dreg;
3453                         }
3454                         break;
3455 #ifdef MONO_ARCH_SIMD_INTRINSICS
3456                 case OP_EXPAND_I1: {
3457                                 int temp_reg1 = mono_alloc_ireg (cfg);
3458                                 int temp_reg2 = mono_alloc_ireg (cfg);
3459                                 int original_reg = ins->sreg1;
3460
3461                                 NEW_INS (cfg, ins, temp, OP_ICONV_TO_U1);
3462                                 temp->sreg1 = original_reg;
3463                                 temp->dreg = temp_reg1;
3464
3465                                 NEW_INS (cfg, ins, temp, OP_SHL_IMM);
3466                                 temp->sreg1 = temp_reg1;
3467                                 temp->dreg = temp_reg2;
3468                                 temp->inst_imm = 8;
3469
3470                                 NEW_INS (cfg, ins, temp, OP_LOR);
3471                                 temp->sreg1 = temp->dreg = temp_reg2;
3472                                 temp->sreg2 = temp_reg1;
3473
3474                                 ins->opcode = OP_EXPAND_I2;
3475                                 ins->sreg1 = temp_reg2;
3476                         }
3477                         break;
3478 #endif
3479                 default:
3480                         break;
3481                 }
3482         }
3483
3484         bb->max_vreg = cfg->next_vreg;
3485 }
3486
3487 static const int
3488 branch_cc_table [] = {
3489         X86_CC_EQ, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3490         X86_CC_NE, X86_CC_GE, X86_CC_GT, X86_CC_LE, X86_CC_LT,
3491         X86_CC_O, X86_CC_NO, X86_CC_C, X86_CC_NC
3492 };
3493
3494 /* Maps CMP_... constants to X86_CC_... constants */
3495 static const int
3496 cc_table [] = {
3497         X86_CC_EQ, X86_CC_NE, X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT,
3498         X86_CC_LE, X86_CC_GE, X86_CC_LT, X86_CC_GT
3499 };
3500
3501 static const int
3502 cc_signed_table [] = {
3503         TRUE, TRUE, TRUE, TRUE, TRUE, TRUE,
3504         FALSE, FALSE, FALSE, FALSE
3505 };
3506
3507 /*#include "cprop.c"*/
3508
3509 static unsigned char*
3510 emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
3511 {
3512         if (size == 8)
3513                 amd64_sse_cvttsd2si_reg_reg (code, dreg, sreg);
3514         else
3515                 amd64_sse_cvttsd2si_reg_reg_size (code, dreg, sreg, 4);
3516
3517         if (size == 1)
3518                 amd64_widen_reg (code, dreg, dreg, is_signed, FALSE);
3519         else if (size == 2)
3520                 amd64_widen_reg (code, dreg, dreg, is_signed, TRUE);
3521         return code;
3522 }
3523
3524 static unsigned char*
3525 mono_emit_stack_alloc (MonoCompile *cfg, guchar *code, MonoInst* tree)
3526 {
3527         int sreg = tree->sreg1;
3528         int need_touch = FALSE;
3529
3530 #if defined(TARGET_WIN32)
3531         need_touch = TRUE;
3532 #elif defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
3533         if (!tree->flags & MONO_INST_INIT)
3534                 need_touch = TRUE;
3535 #endif
3536
3537         if (need_touch) {
3538                 guint8* br[5];
3539
3540                 /*
3541                  * Under Windows:
3542                  * If requested stack size is larger than one page,
3543                  * perform stack-touch operation
3544                  */
3545                 /*
3546                  * Generate stack probe code.
3547                  * Under Windows, it is necessary to allocate one page at a time,
3548                  * "touching" stack after each successful sub-allocation. This is
3549                  * because of the way stack growth is implemented - there is a
3550                  * guard page before the lowest stack page that is currently commited.
3551                  * Stack normally grows sequentially so OS traps access to the
3552                  * guard page and commits more pages when needed.
3553                  */
3554                 amd64_test_reg_imm (code, sreg, ~0xFFF);
3555                 br[0] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3556
3557                 br[2] = code; /* loop */
3558                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
3559                 amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
3560                 amd64_alu_reg_imm (code, X86_SUB, sreg, 0x1000);
3561                 amd64_alu_reg_imm (code, X86_CMP, sreg, 0x1000);
3562                 br[3] = code; x86_branch8 (code, X86_CC_AE, 0, FALSE);
3563                 amd64_patch (br[3], br[2]);
3564                 amd64_test_reg_reg (code, sreg, sreg);
3565                 br[4] = code; x86_branch8 (code, X86_CC_Z, 0, FALSE);
3566                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3567
3568                 br[1] = code; x86_jump8 (code, 0);
3569
3570                 amd64_patch (br[0], code);
3571                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, sreg);
3572                 amd64_patch (br[1], code);
3573                 amd64_patch (br[4], code);
3574         }
3575         else
3576                 amd64_alu_reg_reg (code, X86_SUB, AMD64_RSP, tree->sreg1);
3577
3578         if (tree->flags & MONO_INST_INIT) {
3579                 int offset = 0;
3580                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX) {
3581                         amd64_push_reg (code, AMD64_RAX);
3582                         offset += 8;
3583                 }
3584                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX) {
3585                         amd64_push_reg (code, AMD64_RCX);
3586                         offset += 8;
3587                 }
3588                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI) {
3589                         amd64_push_reg (code, AMD64_RDI);
3590                         offset += 8;
3591                 }
3592
3593                 amd64_shift_reg_imm (code, X86_SHR, sreg, 3);
3594                 if (sreg != AMD64_RCX)
3595                         amd64_mov_reg_reg (code, AMD64_RCX, sreg, 8);
3596                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
3597
3598                 amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, offset);
3599                 if (cfg->param_area)
3600                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RDI, cfg->param_area);
3601                 amd64_cld (code);
3602 #if defined(__default_codegen__)
3603                 amd64_prefix (code, X86_REP_PREFIX);
3604                 amd64_stosl (code);
3605 #elif defined(__native_client_codegen__)
3606                 /* NaCl stos pseudo-instruction */
3607                 amd64_codegen_pre(code);
3608                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
3609                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
3610                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
3611                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
3612                 amd64_prefix (code, X86_REP_PREFIX);
3613                 amd64_stosl (code);
3614                 amd64_codegen_post(code);
3615 #endif /* __native_client_codegen__ */
3616
3617                 if (tree->dreg != AMD64_RDI && sreg != AMD64_RDI)
3618                         amd64_pop_reg (code, AMD64_RDI);
3619                 if (tree->dreg != AMD64_RCX && sreg != AMD64_RCX)
3620                         amd64_pop_reg (code, AMD64_RCX);
3621                 if (tree->dreg != AMD64_RAX && sreg != AMD64_RAX)
3622                         amd64_pop_reg (code, AMD64_RAX);
3623         }
3624         return code;
3625 }
3626
3627 static guint8*
3628 emit_move_return_value (MonoCompile *cfg, MonoInst *ins, guint8 *code)
3629 {
3630         CallInfo *cinfo;
3631         guint32 quad;
3632
3633         /* Move return value to the target register */
3634         /* FIXME: do this in the local reg allocator */
3635         switch (ins->opcode) {
3636         case OP_CALL:
3637         case OP_CALL_REG:
3638         case OP_CALL_MEMBASE:
3639         case OP_LCALL:
3640         case OP_LCALL_REG:
3641         case OP_LCALL_MEMBASE:
3642                 g_assert (ins->dreg == AMD64_RAX);
3643                 break;
3644         case OP_FCALL:
3645         case OP_FCALL_REG:
3646         case OP_FCALL_MEMBASE: {
3647                 MonoType *rtype = mini_get_underlying_type (((MonoCallInst*)ins)->signature->ret);
3648                 if (rtype->type == MONO_TYPE_R4) {
3649                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, AMD64_XMM0);
3650                 }
3651                 else {
3652                         if (ins->dreg != AMD64_XMM0)
3653                                 amd64_sse_movsd_reg_reg (code, ins->dreg, AMD64_XMM0);
3654                 }
3655                 break;
3656         }
3657         case OP_RCALL:
3658         case OP_RCALL_REG:
3659         case OP_RCALL_MEMBASE:
3660                 if (ins->dreg != AMD64_XMM0)
3661                         amd64_sse_movss_reg_reg (code, ins->dreg, AMD64_XMM0);
3662                 break;
3663         case OP_VCALL:
3664         case OP_VCALL_REG:
3665         case OP_VCALL_MEMBASE:
3666         case OP_VCALL2:
3667         case OP_VCALL2_REG:
3668         case OP_VCALL2_MEMBASE:
3669                 cinfo = get_call_info (cfg->mempool, ((MonoCallInst*)ins)->signature);
3670                 if (cinfo->ret.storage == ArgValuetypeInReg) {
3671                         MonoInst *loc = (MonoInst *)cfg->arch.vret_addr_loc;
3672
3673                         /* Load the destination address */
3674                         g_assert (loc->opcode == OP_REGOFFSET);
3675                         amd64_mov_reg_membase (code, AMD64_RCX, loc->inst_basereg, loc->inst_offset, sizeof(gpointer));
3676
3677                         for (quad = 0; quad < 2; quad ++) {
3678                                 switch (cinfo->ret.pair_storage [quad]) {
3679                                 case ArgInIReg:
3680                                         amd64_mov_membase_reg (code, AMD64_RCX, (quad * sizeof(mgreg_t)), cinfo->ret.pair_regs [quad], sizeof(mgreg_t));
3681                                         break;
3682                                 case ArgInFloatSSEReg:
3683                                         amd64_movss_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3684                                         break;
3685                                 case ArgInDoubleSSEReg:
3686                                         amd64_movsd_membase_reg (code, AMD64_RCX, (quad * 8), cinfo->ret.pair_regs [quad]);
3687                                         break;
3688                                 case ArgNone:
3689                                         break;
3690                                 default:
3691                                         NOT_IMPLEMENTED;
3692                                 }
3693                         }
3694                 }
3695                 break;
3696         }
3697
3698         return code;
3699 }
3700
3701 #endif /* DISABLE_JIT */
3702
3703 #ifdef __APPLE__
3704 static int tls_gs_offset;
3705 #endif
3706
3707 gboolean
3708 mono_amd64_have_tls_get (void)
3709 {
3710 #ifdef TARGET_MACH
3711         static gboolean have_tls_get = FALSE;
3712         static gboolean inited = FALSE;
3713
3714         if (inited)
3715                 return have_tls_get;
3716
3717 #if MONO_HAVE_FAST_TLS
3718         guint8 *ins = (guint8*)pthread_getspecific;
3719
3720         /*
3721          * We're looking for these two instructions:
3722          *
3723          * mov    %gs:[offset](,%rdi,8),%rax
3724          * retq
3725          */
3726         have_tls_get = ins [0] == 0x65 &&
3727                        ins [1] == 0x48 &&
3728                        ins [2] == 0x8b &&
3729                        ins [3] == 0x04 &&
3730                        ins [4] == 0xfd &&
3731                        ins [6] == 0x00 &&
3732                        ins [7] == 0x00 &&
3733                        ins [8] == 0x00 &&
3734                        ins [9] == 0xc3;
3735
3736         tls_gs_offset = ins[5];
3737
3738         /*
3739          * Apple now loads a different version of pthread_getspecific when launched from Xcode
3740          * For that version we're looking for these instructions:
3741          *
3742          * pushq  %rbp
3743          * movq   %rsp, %rbp
3744          * mov    %gs:[offset](,%rdi,8),%rax
3745          * popq   %rbp
3746          * retq
3747          */
3748         if (!have_tls_get) {
3749                 have_tls_get = ins [0] == 0x55 &&
3750                                ins [1] == 0x48 &&
3751                                ins [2] == 0x89 &&
3752                                ins [3] == 0xe5 &&
3753                                ins [4] == 0x65 &&
3754                                ins [5] == 0x48 &&
3755                                ins [6] == 0x8b &&
3756                                ins [7] == 0x04 &&
3757                                ins [8] == 0xfd &&
3758                                ins [10] == 0x00 &&
3759                                ins [11] == 0x00 &&
3760                                ins [12] == 0x00 &&
3761                                ins [13] == 0x5d &&
3762                                ins [14] == 0xc3;
3763
3764                 tls_gs_offset = ins[9];
3765         }
3766 #endif
3767
3768         inited = TRUE;
3769
3770         return have_tls_get;
3771 #elif defined(TARGET_ANDROID)
3772         return FALSE;
3773 #else
3774         return TRUE;
3775 #endif
3776 }
3777
3778 int
3779 mono_amd64_get_tls_gs_offset (void)
3780 {
3781 #ifdef TARGET_OSX
3782         return tls_gs_offset;
3783 #else
3784         g_assert_not_reached ();
3785         return -1;
3786 #endif
3787 }
3788
3789 /*
3790  * mono_amd64_emit_tls_get:
3791  * @code: buffer to store code to
3792  * @dreg: hard register where to place the result
3793  * @tls_offset: offset info
3794  *
3795  * mono_amd64_emit_tls_get emits in @code the native code that puts in
3796  * the dreg register the item in the thread local storage identified
3797  * by tls_offset.
3798  *
3799  * Returns: a pointer to the end of the stored code
3800  */
3801 guint8*
3802 mono_amd64_emit_tls_get (guint8* code, int dreg, int tls_offset)
3803 {
3804 #ifdef TARGET_WIN32
3805         if (tls_offset < 64) {
3806                 x86_prefix (code, X86_GS_PREFIX);
3807                 amd64_mov_reg_mem (code, dreg, (tls_offset * 8) + 0x1480, 8);
3808         } else {
3809                 guint8 *buf [16];
3810
3811                 g_assert (tls_offset < 0x440);
3812                 /* Load TEB->TlsExpansionSlots */
3813                 x86_prefix (code, X86_GS_PREFIX);
3814                 amd64_mov_reg_mem (code, dreg, 0x1780, 8);
3815                 amd64_test_reg_reg (code, dreg, dreg);
3816                 buf [0] = code;
3817                 amd64_branch (code, X86_CC_EQ, code, TRUE);
3818                 amd64_mov_reg_membase (code, dreg, dreg, (tls_offset * 8) - 0x200, 8);
3819                 amd64_patch (buf [0], code);
3820         }
3821 #elif defined(__APPLE__)
3822         x86_prefix (code, X86_GS_PREFIX);
3823         amd64_mov_reg_mem (code, dreg, tls_gs_offset + (tls_offset * 8), 8);
3824 #else
3825         if (optimize_for_xen) {
3826                 x86_prefix (code, X86_FS_PREFIX);
3827                 amd64_mov_reg_mem (code, dreg, 0, 8);
3828                 amd64_mov_reg_membase (code, dreg, dreg, tls_offset, 8);
3829         } else {
3830                 x86_prefix (code, X86_FS_PREFIX);
3831                 amd64_mov_reg_mem (code, dreg, tls_offset, 8);
3832         }
3833 #endif
3834         return code;
3835 }
3836
3837 static guint8*
3838 emit_tls_get_reg (guint8* code, int dreg, int offset_reg)
3839 {
3840         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3841 #ifdef TARGET_OSX
3842         if (dreg != offset_reg)
3843                 amd64_mov_reg_reg (code, dreg, offset_reg, sizeof (mgreg_t));
3844         amd64_prefix (code, X86_GS_PREFIX);
3845         amd64_mov_reg_membase (code, dreg, dreg, 0, sizeof (mgreg_t));
3846 #elif defined(__linux__)
3847         int tmpreg = -1;
3848
3849         if (dreg == offset_reg) {
3850                 /* Use a temporary reg by saving it to the redzone */
3851                 tmpreg = dreg == AMD64_RAX ? AMD64_RCX : AMD64_RAX;
3852                 amd64_mov_membase_reg (code, AMD64_RSP, -8, tmpreg, 8);
3853                 amd64_mov_reg_reg (code, tmpreg, offset_reg, sizeof (gpointer));
3854                 offset_reg = tmpreg;
3855         }
3856         x86_prefix (code, X86_FS_PREFIX);
3857         amd64_mov_reg_mem (code, dreg, 0, 8);
3858         amd64_mov_reg_memindex (code, dreg, dreg, 0, offset_reg, 0, 8);
3859         if (tmpreg != -1)
3860                 amd64_mov_reg_membase (code, tmpreg, AMD64_RSP, -8, 8);
3861 #else
3862         g_assert_not_reached ();
3863 #endif
3864         return code;
3865 }
3866
3867 static guint8*
3868 amd64_emit_tls_set (guint8 *code, int sreg, int tls_offset)
3869 {
3870 #ifdef TARGET_WIN32
3871         g_assert_not_reached ();
3872 #elif defined(__APPLE__)
3873         x86_prefix (code, X86_GS_PREFIX);
3874         amd64_mov_mem_reg (code, tls_gs_offset + (tls_offset * 8), sreg, 8);
3875 #else
3876         g_assert (!optimize_for_xen);
3877         x86_prefix (code, X86_FS_PREFIX);
3878         amd64_mov_mem_reg (code, tls_offset, sreg, 8);
3879 #endif
3880         return code;
3881 }
3882
3883 static guint8*
3884 amd64_emit_tls_set_reg (guint8 *code, int sreg, int offset_reg)
3885 {
3886         /* offset_reg contains a value translated by mono_arch_translate_tls_offset () */
3887 #ifdef TARGET_WIN32
3888         g_assert_not_reached ();
3889 #elif defined(__APPLE__)
3890         x86_prefix (code, X86_GS_PREFIX);
3891         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3892 #else
3893         x86_prefix (code, X86_FS_PREFIX);
3894         amd64_mov_membase_reg (code, offset_reg, 0, sreg, 8);
3895 #endif
3896         return code;
3897 }
3898
3899  /*
3900  * mono_arch_translate_tls_offset:
3901  *
3902  *   Translate the TLS offset OFFSET computed by MONO_THREAD_VAR_OFFSET () into a format usable by OP_TLS_GET_REG/OP_TLS_SET_REG.
3903  */
3904 int
3905 mono_arch_translate_tls_offset (int offset)
3906 {
3907 #ifdef __APPLE__
3908         return tls_gs_offset + (offset * 8);
3909 #else
3910         return offset;
3911 #endif
3912 }
3913
3914 /*
3915  * emit_setup_lmf:
3916  *
3917  *   Emit code to initialize an LMF structure at LMF_OFFSET.
3918  */
3919 static guint8*
3920 emit_setup_lmf (MonoCompile *cfg, guint8 *code, gint32 lmf_offset, int cfa_offset)
3921 {
3922         /*
3923          * The ip field is not set, the exception handling code will obtain it from the stack location pointed to by the sp field.
3924          */
3925         /*
3926          * sp is saved right before calls but we need to save it here too so
3927          * async stack walks would work.
3928          */
3929         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
3930         /* Save rbp */
3931         amd64_mov_membase_reg (code, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), AMD64_RBP, 8);
3932         if (cfg->arch.omit_fp && cfa_offset != -1)
3933                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - (cfa_offset - (lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp))));
3934
3935         /* These can't contain refs */
3936         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, previous_lmf), SLOT_NOREF);
3937         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rip), SLOT_NOREF);
3938         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), SLOT_NOREF);
3939         /* These are handled automatically by the stack marking code */
3940         mini_gc_set_slot_type_from_fp (cfg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), SLOT_NOREF);
3941
3942         return code;
3943 }
3944
3945 #define REAL_PRINT_REG(text,reg) \
3946 mono_assert (reg >= 0); \
3947 amd64_push_reg (code, AMD64_RAX); \
3948 amd64_push_reg (code, AMD64_RDX); \
3949 amd64_push_reg (code, AMD64_RCX); \
3950 amd64_push_reg (code, reg); \
3951 amd64_push_imm (code, reg); \
3952 amd64_push_imm (code, text " %d %p\n"); \
3953 amd64_mov_reg_imm (code, AMD64_RAX, printf); \
3954 amd64_call_reg (code, AMD64_RAX); \
3955 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 3*4); \
3956 amd64_pop_reg (code, AMD64_RCX); \
3957 amd64_pop_reg (code, AMD64_RDX); \
3958 amd64_pop_reg (code, AMD64_RAX);
3959
3960 /* benchmark and set based on cpu */
3961 #define LOOP_ALIGNMENT 8
3962 #define bb_is_loop_start(bb) ((bb)->loop_body_start && (bb)->nesting)
3963
3964 #ifndef DISABLE_JIT
3965 void
3966 mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
3967 {
3968         MonoInst *ins;
3969         MonoCallInst *call;
3970         guint offset;
3971         guint8 *code = cfg->native_code + cfg->code_len;
3972         int max_len;
3973
3974         /* Fix max_offset estimate for each successor bb */
3975         if (cfg->opt & MONO_OPT_BRANCH) {
3976                 int current_offset = cfg->code_len;
3977                 MonoBasicBlock *current_bb;
3978                 for (current_bb = bb; current_bb != NULL; current_bb = current_bb->next_bb) {
3979                         current_bb->max_offset = current_offset;
3980                         current_offset += current_bb->max_length;
3981                 }
3982         }
3983
3984         if (cfg->opt & MONO_OPT_LOOP) {
3985                 int pad, align = LOOP_ALIGNMENT;
3986                 /* set alignment depending on cpu */
3987                 if (bb_is_loop_start (bb) && (pad = (cfg->code_len & (align - 1)))) {
3988                         pad = align - pad;
3989                         /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
3990                         amd64_padding (code, pad);
3991                         cfg->code_len += pad;
3992                         bb->native_offset = cfg->code_len;
3993                 }
3994         }
3995
3996 #if defined(__native_client_codegen__)
3997         /* For Native Client, all indirect call/jump targets must be */
3998         /* 32-byte aligned.  Exception handler blocks are jumped to  */
3999         /* indirectly as well.                                       */
4000         gboolean bb_needs_alignment = (bb->flags & BB_INDIRECT_JUMP_TARGET) ||
4001                                       (bb->flags & BB_EXCEPTION_HANDLER);
4002
4003         if ( bb_needs_alignment && ((cfg->code_len & kNaClAlignmentMask) != 0)) {
4004                 int pad = kNaClAlignment - (cfg->code_len & kNaClAlignmentMask);
4005                 if (pad != kNaClAlignment) code = mono_arch_nacl_pad(code, pad);
4006                 cfg->code_len += pad;
4007                 bb->native_offset = cfg->code_len;
4008         }
4009 #endif  /*__native_client_codegen__*/
4010
4011         if (cfg->verbose_level > 2)
4012                 g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
4013
4014         if ((cfg->prof_options & MONO_PROFILE_COVERAGE) && cfg->coverage_info) {
4015                 MonoProfileCoverageInfo *cov = cfg->coverage_info;
4016                 g_assert (!cfg->compile_aot);
4017
4018                 cov->data [bb->dfn].cil_code = bb->cil_code;
4019                 amd64_mov_reg_imm (code, AMD64_R11, (guint64)&cov->data [bb->dfn].count);
4020                 /* this is not thread save, but good enough */
4021                 amd64_inc_membase (code, AMD64_R11, 0);
4022         }
4023
4024         offset = code - cfg->native_code;
4025
4026         mono_debug_open_block (cfg, bb, offset);
4027
4028     if (mono_break_at_bb_method && mono_method_desc_full_match (mono_break_at_bb_method, cfg->method) && bb->block_num == mono_break_at_bb_bb_num)
4029                 x86_breakpoint (code);
4030
4031         MONO_BB_FOR_EACH_INS (bb, ins) {
4032                 offset = code - cfg->native_code;
4033
4034                 max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
4035
4036 #define EXTRA_CODE_SPACE (NACL_SIZE (16, 16 + kNaClAlignment))
4037
4038                 if (G_UNLIKELY (offset > (cfg->code_size - max_len - EXTRA_CODE_SPACE))) {
4039                         cfg->code_size *= 2;
4040                         cfg->native_code = (unsigned char *)mono_realloc_native_code(cfg);
4041                         code = cfg->native_code + offset;
4042                         cfg->stat_code_reallocs++;
4043                 }
4044
4045                 if (cfg->debug_info)
4046                         mono_debug_record_line_number (cfg, ins, offset);
4047
4048                 switch (ins->opcode) {
4049                 case OP_BIGMUL:
4050                         amd64_mul_reg (code, ins->sreg2, TRUE);
4051                         break;
4052                 case OP_BIGMUL_UN:
4053                         amd64_mul_reg (code, ins->sreg2, FALSE);
4054                         break;
4055                 case OP_X86_SETEQ_MEMBASE:
4056                         amd64_set_membase (code, X86_CC_EQ, ins->inst_basereg, ins->inst_offset, TRUE);
4057                         break;
4058                 case OP_STOREI1_MEMBASE_IMM:
4059                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 1);
4060                         break;
4061                 case OP_STOREI2_MEMBASE_IMM:
4062                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 2);
4063                         break;
4064                 case OP_STOREI4_MEMBASE_IMM:
4065                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 4);
4066                         break;
4067                 case OP_STOREI1_MEMBASE_REG:
4068                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 1);
4069                         break;
4070                 case OP_STOREI2_MEMBASE_REG:
4071                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 2);
4072                         break;
4073                 /* In AMD64 NaCl, pointers are 4 bytes, */
4074                 /*  so STORE_* != STOREI8_*. Likewise below. */
4075                 case OP_STORE_MEMBASE_REG:
4076                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, sizeof(gpointer));
4077                         break;
4078                 case OP_STOREI8_MEMBASE_REG:
4079                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 8);
4080                         break;
4081                 case OP_STOREI4_MEMBASE_REG:
4082                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, 4);
4083                         break;
4084                 case OP_STORE_MEMBASE_IMM:
4085 #ifndef __native_client_codegen__
4086                         /* In NaCl, this could be a PCONST type, which could */
4087                         /* mean a pointer type was copied directly into the  */
4088                         /* lower 32-bits of inst_imm, so for InvalidPtr==-1  */
4089                         /* the value would be 0x00000000FFFFFFFF which is    */
4090                         /* not proper for an imm32 unless you cast it.       */
4091                         g_assert (amd64_is_imm32 (ins->inst_imm));
4092 #endif
4093                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, (gint32)ins->inst_imm, sizeof(gpointer));
4094                         break;
4095                 case OP_STOREI8_MEMBASE_IMM:
4096                         g_assert (amd64_is_imm32 (ins->inst_imm));
4097                         amd64_mov_membase_imm (code, ins->inst_destbasereg, ins->inst_offset, ins->inst_imm, 8);
4098                         break;
4099                 case OP_LOAD_MEM:
4100 #ifdef __mono_ilp32__
4101                         /* In ILP32, pointers are 4 bytes, so separate these */
4102                         /* cases, use literal 8 below where we really want 8 */
4103                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4104                         amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, sizeof(gpointer));
4105                         break;
4106 #endif
4107                 case OP_LOADI8_MEM:
4108                         // FIXME: Decompose this earlier
4109                         if (amd64_use_imm32 (ins->inst_imm))
4110                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 8);
4111                         else {
4112                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4113                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 8);
4114                         }
4115                         break;
4116                 case OP_LOADI4_MEM:
4117                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4118                         amd64_movsxd_reg_membase (code, ins->dreg, ins->dreg, 0);
4119                         break;
4120                 case OP_LOADU4_MEM:
4121                         // FIXME: Decompose this earlier
4122                         if (amd64_use_imm32 (ins->inst_imm))
4123                                 amd64_mov_reg_mem (code, ins->dreg, ins->inst_imm, 4);
4124                         else {
4125                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_imm, sizeof(gpointer));
4126                                 amd64_mov_reg_membase (code, ins->dreg, ins->dreg, 0, 4);
4127                         }
4128                         break;
4129                 case OP_LOADU1_MEM:
4130                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4131                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, FALSE);
4132                         break;
4133                 case OP_LOADU2_MEM:
4134                         /* For NaCl, pointers are 4 bytes, so separate these */
4135                         /* cases, use literal 8 below where we really want 8 */
4136                         amd64_mov_reg_imm (code, ins->dreg, ins->inst_imm);
4137                         amd64_widen_membase (code, ins->dreg, ins->dreg, 0, FALSE, TRUE);
4138                         break;
4139                 case OP_LOAD_MEMBASE:
4140                         g_assert (amd64_is_imm32 (ins->inst_offset));
4141                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, sizeof(gpointer));
4142                         break;
4143                 case OP_LOADI8_MEMBASE:
4144                         /* Use literal 8 instead of sizeof pointer or */
4145                         /* register, we really want 8 for this opcode */
4146                         g_assert (amd64_is_imm32 (ins->inst_offset));
4147                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 8);
4148                         break;
4149                 case OP_LOADI4_MEMBASE:
4150                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
4151                         break;
4152                 case OP_LOADU4_MEMBASE:
4153                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, 4);
4154                         break;
4155                 case OP_LOADU1_MEMBASE:
4156                         /* The cpu zero extends the result into 64 bits */
4157                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE, 4);
4158                         break;
4159                 case OP_LOADI1_MEMBASE:
4160                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
4161                         break;
4162                 case OP_LOADU2_MEMBASE:
4163                         /* The cpu zero extends the result into 64 bits */
4164                         amd64_widen_membase_size (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE, 4);
4165                         break;
4166                 case OP_LOADI2_MEMBASE:
4167                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
4168                         break;
4169                 case OP_AMD64_LOADI8_MEMINDEX:
4170                         amd64_mov_reg_memindex_size (code, ins->dreg, ins->inst_basereg, 0, ins->inst_indexreg, 0, 8);
4171                         break;
4172                 case OP_LCONV_TO_I1:
4173                 case OP_ICONV_TO_I1:
4174                 case OP_SEXT_I1:
4175                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, FALSE);
4176                         break;
4177                 case OP_LCONV_TO_I2:
4178                 case OP_ICONV_TO_I2:
4179                 case OP_SEXT_I2:
4180                         amd64_widen_reg (code, ins->dreg, ins->sreg1, TRUE, TRUE);
4181                         break;
4182                 case OP_LCONV_TO_U1:
4183                 case OP_ICONV_TO_U1:
4184                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, FALSE);
4185                         break;
4186                 case OP_LCONV_TO_U2:
4187                 case OP_ICONV_TO_U2:
4188                         amd64_widen_reg (code, ins->dreg, ins->sreg1, FALSE, TRUE);
4189                         break;
4190                 case OP_ZEXT_I4:
4191                         /* Clean out the upper word */
4192                         amd64_mov_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
4193                         break;
4194                 case OP_SEXT_I4:
4195                         amd64_movsxd_reg_reg (code, ins->dreg, ins->sreg1);
4196                         break;
4197                 case OP_COMPARE:
4198                 case OP_LCOMPARE:
4199                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
4200                         break;
4201                 case OP_COMPARE_IMM:
4202 #if defined(__mono_ilp32__)
4203                         /* Comparison of pointer immediates should be 4 bytes to avoid sign-extend problems */
4204                         g_assert (amd64_is_imm32 (ins->inst_imm));
4205                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4206                         break;
4207 #endif
4208                 case OP_LCOMPARE_IMM:
4209                         g_assert (amd64_is_imm32 (ins->inst_imm));
4210                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, ins->inst_imm);
4211                         break;
4212                 case OP_X86_COMPARE_REG_MEMBASE:
4213                         amd64_alu_reg_membase (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset);
4214                         break;
4215                 case OP_X86_TEST_NULL:
4216                         amd64_test_reg_reg_size (code, ins->sreg1, ins->sreg1, 4);
4217                         break;
4218                 case OP_AMD64_TEST_NULL:
4219                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
4220                         break;
4221
4222                 case OP_X86_ADD_REG_MEMBASE:
4223                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4224                         break;
4225                 case OP_X86_SUB_REG_MEMBASE:
4226                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4227                         break;
4228                 case OP_X86_AND_REG_MEMBASE:
4229                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4230                         break;
4231                 case OP_X86_OR_REG_MEMBASE:
4232                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4233                         break;
4234                 case OP_X86_XOR_REG_MEMBASE:
4235                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4236                         break;
4237
4238                 case OP_X86_ADD_MEMBASE_IMM:
4239                         /* FIXME: Make a 64 version too */
4240                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4241                         break;
4242                 case OP_X86_SUB_MEMBASE_IMM:
4243                         g_assert (amd64_is_imm32 (ins->inst_imm));
4244                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4245                         break;
4246                 case OP_X86_AND_MEMBASE_IMM:
4247                         g_assert (amd64_is_imm32 (ins->inst_imm));
4248                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4249                         break;
4250                 case OP_X86_OR_MEMBASE_IMM:
4251                         g_assert (amd64_is_imm32 (ins->inst_imm));
4252                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4253                         break;
4254                 case OP_X86_XOR_MEMBASE_IMM:
4255                         g_assert (amd64_is_imm32 (ins->inst_imm));
4256                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4257                         break;
4258                 case OP_X86_ADD_MEMBASE_REG:
4259                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4260                         break;
4261                 case OP_X86_SUB_MEMBASE_REG:
4262                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4263                         break;
4264                 case OP_X86_AND_MEMBASE_REG:
4265                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4266                         break;
4267                 case OP_X86_OR_MEMBASE_REG:
4268                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4269                         break;
4270                 case OP_X86_XOR_MEMBASE_REG:
4271                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4272                         break;
4273                 case OP_X86_INC_MEMBASE:
4274                         amd64_inc_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4275                         break;
4276                 case OP_X86_INC_REG:
4277                         amd64_inc_reg_size (code, ins->dreg, 4);
4278                         break;
4279                 case OP_X86_DEC_MEMBASE:
4280                         amd64_dec_membase_size (code, ins->inst_basereg, ins->inst_offset, 4);
4281                         break;
4282                 case OP_X86_DEC_REG:
4283                         amd64_dec_reg_size (code, ins->dreg, 4);
4284                         break;
4285                 case OP_X86_MUL_REG_MEMBASE:
4286                 case OP_X86_MUL_MEMBASE_REG:
4287                         amd64_imul_reg_membase_size (code, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4288                         break;
4289                 case OP_AMD64_ICOMPARE_MEMBASE_REG:
4290                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 4);
4291                         break;
4292                 case OP_AMD64_ICOMPARE_MEMBASE_IMM:
4293                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4294                         break;
4295                 case OP_AMD64_COMPARE_MEMBASE_REG:
4296                         amd64_alu_membase_reg_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4297                         break;
4298                 case OP_AMD64_COMPARE_MEMBASE_IMM:
4299                         g_assert (amd64_is_imm32 (ins->inst_imm));
4300                         amd64_alu_membase_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4301                         break;
4302                 case OP_X86_COMPARE_MEMBASE8_IMM:
4303                         amd64_alu_membase8_imm_size (code, X86_CMP, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 4);
4304                         break;
4305                 case OP_AMD64_ICOMPARE_REG_MEMBASE:
4306                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 4);
4307                         break;
4308                 case OP_AMD64_COMPARE_REG_MEMBASE:
4309                         amd64_alu_reg_membase_size (code, X86_CMP, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4310                         break;
4311
4312                 case OP_AMD64_ADD_REG_MEMBASE:
4313                         amd64_alu_reg_membase_size (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4314                         break;
4315                 case OP_AMD64_SUB_REG_MEMBASE:
4316                         amd64_alu_reg_membase_size (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4317                         break;
4318                 case OP_AMD64_AND_REG_MEMBASE:
4319                         amd64_alu_reg_membase_size (code, X86_AND, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4320                         break;
4321                 case OP_AMD64_OR_REG_MEMBASE:
4322                         amd64_alu_reg_membase_size (code, X86_OR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4323                         break;
4324                 case OP_AMD64_XOR_REG_MEMBASE:
4325                         amd64_alu_reg_membase_size (code, X86_XOR, ins->sreg1, ins->sreg2, ins->inst_offset, 8);
4326                         break;
4327
4328                 case OP_AMD64_ADD_MEMBASE_REG:
4329                         amd64_alu_membase_reg_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4330                         break;
4331                 case OP_AMD64_SUB_MEMBASE_REG:
4332                         amd64_alu_membase_reg_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4333                         break;
4334                 case OP_AMD64_AND_MEMBASE_REG:
4335                         amd64_alu_membase_reg_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4336                         break;
4337                 case OP_AMD64_OR_MEMBASE_REG:
4338                         amd64_alu_membase_reg_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4339                         break;
4340                 case OP_AMD64_XOR_MEMBASE_REG:
4341                         amd64_alu_membase_reg_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->sreg2, 8);
4342                         break;
4343
4344                 case OP_AMD64_ADD_MEMBASE_IMM:
4345                         g_assert (amd64_is_imm32 (ins->inst_imm));
4346                         amd64_alu_membase_imm_size (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4347                         break;
4348                 case OP_AMD64_SUB_MEMBASE_IMM:
4349                         g_assert (amd64_is_imm32 (ins->inst_imm));
4350                         amd64_alu_membase_imm_size (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4351                         break;
4352                 case OP_AMD64_AND_MEMBASE_IMM:
4353                         g_assert (amd64_is_imm32 (ins->inst_imm));
4354                         amd64_alu_membase_imm_size (code, X86_AND, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4355                         break;
4356                 case OP_AMD64_OR_MEMBASE_IMM:
4357                         g_assert (amd64_is_imm32 (ins->inst_imm));
4358                         amd64_alu_membase_imm_size (code, X86_OR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4359                         break;
4360                 case OP_AMD64_XOR_MEMBASE_IMM:
4361                         g_assert (amd64_is_imm32 (ins->inst_imm));
4362                         amd64_alu_membase_imm_size (code, X86_XOR, ins->inst_basereg, ins->inst_offset, ins->inst_imm, 8);
4363                         break;
4364
4365                 case OP_BREAK:
4366                         amd64_breakpoint (code);
4367                         break;
4368                 case OP_RELAXED_NOP:
4369                         x86_prefix (code, X86_REP_PREFIX);
4370                         x86_nop (code);
4371                         break;
4372                 case OP_HARD_NOP:
4373                         x86_nop (code);
4374                         break;
4375                 case OP_NOP:
4376                 case OP_DUMMY_USE:
4377                 case OP_DUMMY_STORE:
4378                 case OP_DUMMY_ICONST:
4379                 case OP_DUMMY_R8CONST:
4380                 case OP_NOT_REACHED:
4381                 case OP_NOT_NULL:
4382                         break;
4383                 case OP_IL_SEQ_POINT:
4384                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4385                         break;
4386                 case OP_SEQ_POINT: {
4387                         if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
4388                                 MonoInst *var = (MonoInst *)cfg->arch.ss_tramp_var;
4389                                 guint8 *label;
4390
4391                                 /* Load ss_tramp_var */
4392                                 /* This is equal to &ss_trampoline */
4393                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4394                                 /* Load the trampoline address */
4395                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, 0, 8);
4396                                 /* Call it if it is non-null */
4397                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4398                                 label = code;
4399                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4400                                 amd64_call_reg (code, AMD64_R11);
4401                                 amd64_patch (label, code);
4402                         }
4403
4404                         /*
4405                          * This is the address which is saved in seq points,
4406                          */
4407                         mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
4408
4409                         if (cfg->compile_aot) {
4410                                 guint32 offset = code - cfg->native_code;
4411                                 guint32 val;
4412                                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
4413                                 guint8 *label;
4414
4415                                 /* Load info var */
4416                                 amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
4417                                 val = ((offset) * sizeof (guint8*)) + MONO_STRUCT_OFFSET (SeqPointInfo, bp_addrs);
4418                                 /* Load the info->bp_addrs [offset], which is either NULL or the address of the breakpoint trampoline */
4419                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, val, 8);
4420                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4421                                 label = code;
4422                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4423                                 /* Call the trampoline */
4424                                 amd64_call_reg (code, AMD64_R11);
4425                                 amd64_patch (label, code);
4426                         } else {
4427                                 MonoInst *var = (MonoInst *)cfg->arch.bp_tramp_var;
4428                                 guint8 *label;
4429
4430                                 /*
4431                                  * Emit a test+branch against a constant, the constant will be overwritten
4432                                  * by mono_arch_set_breakpoint () to cause the test to fail.
4433                                  */
4434                                 amd64_mov_reg_imm (code, AMD64_R11, 0);
4435                                 amd64_test_reg_reg (code, AMD64_R11, AMD64_R11);
4436                                 label = code;
4437                                 amd64_branch8 (code, X86_CC_Z, 0, FALSE);
4438
4439                                 g_assert (var);
4440                                 g_assert (var->opcode == OP_REGOFFSET);
4441                                 /* Load bp_tramp_var */
4442                                 /* This is equal to &bp_trampoline */
4443                                 amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
4444                                 /* Call the trampoline */
4445                                 amd64_call_membase (code, AMD64_R11, 0);
4446                                 amd64_patch (label, code);
4447                         }
4448                         /*
4449                          * Add an additional nop so skipping the bp doesn't cause the ip to point
4450                          * to another IL offset.
4451                          */
4452                         x86_nop (code);
4453                         break;
4454                 }
4455                 case OP_ADDCC:
4456                 case OP_LADDCC:
4457                 case OP_LADD:
4458                         amd64_alu_reg_reg (code, X86_ADD, ins->sreg1, ins->sreg2);
4459                         break;
4460                 case OP_ADC:
4461                         amd64_alu_reg_reg (code, X86_ADC, ins->sreg1, ins->sreg2);
4462                         break;
4463                 case OP_ADD_IMM:
4464                 case OP_LADD_IMM:
4465                         g_assert (amd64_is_imm32 (ins->inst_imm));
4466                         amd64_alu_reg_imm (code, X86_ADD, ins->dreg, ins->inst_imm);
4467                         break;
4468                 case OP_ADC_IMM:
4469                         g_assert (amd64_is_imm32 (ins->inst_imm));
4470                         amd64_alu_reg_imm (code, X86_ADC, ins->dreg, ins->inst_imm);
4471                         break;
4472                 case OP_SUBCC:
4473                 case OP_LSUBCC:
4474                 case OP_LSUB:
4475                         amd64_alu_reg_reg (code, X86_SUB, ins->sreg1, ins->sreg2);
4476                         break;
4477                 case OP_SBB:
4478                         amd64_alu_reg_reg (code, X86_SBB, ins->sreg1, ins->sreg2);
4479                         break;
4480                 case OP_SUB_IMM:
4481                 case OP_LSUB_IMM:
4482                         g_assert (amd64_is_imm32 (ins->inst_imm));
4483                         amd64_alu_reg_imm (code, X86_SUB, ins->dreg, ins->inst_imm);
4484                         break;
4485                 case OP_SBB_IMM:
4486                         g_assert (amd64_is_imm32 (ins->inst_imm));
4487                         amd64_alu_reg_imm (code, X86_SBB, ins->dreg, ins->inst_imm);
4488                         break;
4489                 case OP_LAND:
4490                         amd64_alu_reg_reg (code, X86_AND, ins->sreg1, ins->sreg2);
4491                         break;
4492                 case OP_AND_IMM:
4493                 case OP_LAND_IMM:
4494                         g_assert (amd64_is_imm32 (ins->inst_imm));
4495                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_imm);
4496                         break;
4497                 case OP_LMUL:
4498                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4499                         break;
4500                 case OP_MUL_IMM:
4501                 case OP_LMUL_IMM:
4502                 case OP_IMUL_IMM: {
4503                         guint32 size = (ins->opcode == OP_IMUL_IMM) ? 4 : 8;
4504
4505                         switch (ins->inst_imm) {
4506                         case 2:
4507                                 /* MOV r1, r2 */
4508                                 /* ADD r1, r1 */
4509                                 if (ins->dreg != ins->sreg1)
4510                                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, size);
4511                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4512                                 break;
4513                         case 3:
4514                                 /* LEA r1, [r2 + r2*2] */
4515                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4516                                 break;
4517                         case 5:
4518                                 /* LEA r1, [r2 + r2*4] */
4519                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4520                                 break;
4521                         case 6:
4522                                 /* LEA r1, [r2 + r2*2] */
4523                                 /* ADD r1, r1          */
4524                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4525                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4526                                 break;
4527                         case 9:
4528                                 /* LEA r1, [r2 + r2*8] */
4529                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 3);
4530                                 break;
4531                         case 10:
4532                                 /* LEA r1, [r2 + r2*4] */
4533                                 /* ADD r1, r1          */
4534                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4535                                 amd64_alu_reg_reg (code, X86_ADD, ins->dreg, ins->dreg);
4536                                 break;
4537                         case 12:
4538                                 /* LEA r1, [r2 + r2*2] */
4539                                 /* SHL r1, 2           */
4540                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 1);
4541                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4542                                 break;
4543                         case 25:
4544                                 /* LEA r1, [r2 + r2*4] */
4545                                 /* LEA r1, [r1 + r1*4] */
4546                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4547                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4548                                 break;
4549                         case 100:
4550                                 /* LEA r1, [r2 + r2*4] */
4551                                 /* SHL r1, 2           */
4552                                 /* LEA r1, [r1 + r1*4] */
4553                                 amd64_lea_memindex (code, ins->dreg, ins->sreg1, 0, ins->sreg1, 2);
4554                                 amd64_shift_reg_imm (code, X86_SHL, ins->dreg, 2);
4555                                 amd64_lea_memindex (code, ins->dreg, ins->dreg, 0, ins->dreg, 2);
4556                                 break;
4557                         default:
4558                                 amd64_imul_reg_reg_imm_size (code, ins->dreg, ins->sreg1, ins->inst_imm, size);
4559                                 break;
4560                         }
4561                         break;
4562                 }
4563                 case OP_LDIV:
4564                 case OP_LREM:
4565 #if defined( __native_client_codegen__ )
4566                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4567                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4568 #endif
4569                         /* Regalloc magic makes the div/rem cases the same */
4570                         if (ins->sreg2 == AMD64_RDX) {
4571                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4572                                 amd64_cdq (code);
4573                                 amd64_div_membase (code, AMD64_RSP, -8, TRUE);
4574                         } else {
4575                                 amd64_cdq (code);
4576                                 amd64_div_reg (code, ins->sreg2, TRUE);
4577                         }
4578                         break;
4579                 case OP_LDIV_UN:
4580                 case OP_LREM_UN:
4581 #if defined( __native_client_codegen__ )
4582                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4583                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4584 #endif
4585                         if (ins->sreg2 == AMD64_RDX) {
4586                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4587                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4588                                 amd64_div_membase (code, AMD64_RSP, -8, FALSE);
4589                         } else {
4590                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4591                                 amd64_div_reg (code, ins->sreg2, FALSE);
4592                         }
4593                         break;
4594                 case OP_IDIV:
4595                 case OP_IREM:
4596 #if defined( __native_client_codegen__ )
4597                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg2, 0);
4598                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4599 #endif
4600                         if (ins->sreg2 == AMD64_RDX) {
4601                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4602                                 amd64_cdq_size (code, 4);
4603                                 amd64_div_membase_size (code, AMD64_RSP, -8, TRUE, 4);
4604                         } else {
4605                                 amd64_cdq_size (code, 4);
4606                                 amd64_div_reg_size (code, ins->sreg2, TRUE, 4);
4607                         }
4608                         break;
4609                 case OP_IDIV_UN:
4610                 case OP_IREM_UN:
4611 #if defined( __native_client_codegen__ )
4612                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg2, 0, 4);
4613                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, TRUE, "DivideByZeroException");
4614 #endif
4615                         if (ins->sreg2 == AMD64_RDX) {
4616                                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDX, 8);
4617                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4618                                 amd64_div_membase_size (code, AMD64_RSP, -8, FALSE, 4);
4619                         } else {
4620                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RDX, AMD64_RDX);
4621                                 amd64_div_reg_size (code, ins->sreg2, FALSE, 4);
4622                         }
4623                         break;
4624                 case OP_LMUL_OVF:
4625                         amd64_imul_reg_reg (code, ins->sreg1, ins->sreg2);
4626                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4627                         break;
4628                 case OP_LOR:
4629                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
4630                         break;
4631                 case OP_OR_IMM:
4632                 case OP_LOR_IMM:
4633                         g_assert (amd64_is_imm32 (ins->inst_imm));
4634                         amd64_alu_reg_imm (code, X86_OR, ins->sreg1, ins->inst_imm);
4635                         break;
4636                 case OP_LXOR:
4637                         amd64_alu_reg_reg (code, X86_XOR, ins->sreg1, ins->sreg2);
4638                         break;
4639                 case OP_XOR_IMM:
4640                 case OP_LXOR_IMM:
4641                         g_assert (amd64_is_imm32 (ins->inst_imm));
4642                         amd64_alu_reg_imm (code, X86_XOR, ins->sreg1, ins->inst_imm);
4643                         break;
4644                 case OP_LSHL:
4645                         g_assert (ins->sreg2 == AMD64_RCX);
4646                         amd64_shift_reg (code, X86_SHL, ins->dreg);
4647                         break;
4648                 case OP_LSHR:
4649                         g_assert (ins->sreg2 == AMD64_RCX);
4650                         amd64_shift_reg (code, X86_SAR, ins->dreg);
4651                         break;
4652                 case OP_SHR_IMM:
4653                 case OP_LSHR_IMM:
4654                         g_assert (amd64_is_imm32 (ins->inst_imm));
4655                         amd64_shift_reg_imm (code, X86_SAR, ins->dreg, ins->inst_imm);
4656                         break;
4657                 case OP_SHR_UN_IMM:
4658                         g_assert (amd64_is_imm32 (ins->inst_imm));
4659                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4660                         break;
4661                 case OP_LSHR_UN_IMM:
4662                         g_assert (amd64_is_imm32 (ins->inst_imm));
4663                         amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_imm);
4664                         break;
4665                 case OP_LSHR_UN:
4666                         g_assert (ins->sreg2 == AMD64_RCX);
4667                         amd64_shift_reg (code, X86_SHR, ins->dreg);
4668                         break;
4669                 case OP_SHL_IMM:
4670                 case OP_LSHL_IMM:
4671                         g_assert (amd64_is_imm32 (ins->inst_imm));
4672                         amd64_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
4673                         break;
4674
4675                 case OP_IADDCC:
4676                 case OP_IADD:
4677                         amd64_alu_reg_reg_size (code, X86_ADD, ins->sreg1, ins->sreg2, 4);
4678                         break;
4679                 case OP_IADC:
4680                         amd64_alu_reg_reg_size (code, X86_ADC, ins->sreg1, ins->sreg2, 4);
4681                         break;
4682                 case OP_IADD_IMM:
4683                         amd64_alu_reg_imm_size (code, X86_ADD, ins->dreg, ins->inst_imm, 4);
4684                         break;
4685                 case OP_IADC_IMM:
4686                         amd64_alu_reg_imm_size (code, X86_ADC, ins->dreg, ins->inst_imm, 4);
4687                         break;
4688                 case OP_ISUBCC:
4689                 case OP_ISUB:
4690                         amd64_alu_reg_reg_size (code, X86_SUB, ins->sreg1, ins->sreg2, 4);
4691                         break;
4692                 case OP_ISBB:
4693                         amd64_alu_reg_reg_size (code, X86_SBB, ins->sreg1, ins->sreg2, 4);
4694                         break;
4695                 case OP_ISUB_IMM:
4696                         amd64_alu_reg_imm_size (code, X86_SUB, ins->dreg, ins->inst_imm, 4);
4697                         break;
4698                 case OP_ISBB_IMM:
4699                         amd64_alu_reg_imm_size (code, X86_SBB, ins->dreg, ins->inst_imm, 4);
4700                         break;
4701                 case OP_IAND:
4702                         amd64_alu_reg_reg_size (code, X86_AND, ins->sreg1, ins->sreg2, 4);
4703                         break;
4704                 case OP_IAND_IMM:
4705                         amd64_alu_reg_imm_size (code, X86_AND, ins->sreg1, ins->inst_imm, 4);
4706                         break;
4707                 case OP_IOR:
4708                         amd64_alu_reg_reg_size (code, X86_OR, ins->sreg1, ins->sreg2, 4);
4709                         break;
4710                 case OP_IOR_IMM:
4711                         amd64_alu_reg_imm_size (code, X86_OR, ins->sreg1, ins->inst_imm, 4);
4712                         break;
4713                 case OP_IXOR:
4714                         amd64_alu_reg_reg_size (code, X86_XOR, ins->sreg1, ins->sreg2, 4);
4715                         break;
4716                 case OP_IXOR_IMM:
4717                         amd64_alu_reg_imm_size (code, X86_XOR, ins->sreg1, ins->inst_imm, 4);
4718                         break;
4719                 case OP_INEG:
4720                         amd64_neg_reg_size (code, ins->sreg1, 4);
4721                         break;
4722                 case OP_INOT:
4723                         amd64_not_reg_size (code, ins->sreg1, 4);
4724                         break;
4725                 case OP_ISHL:
4726                         g_assert (ins->sreg2 == AMD64_RCX);
4727                         amd64_shift_reg_size (code, X86_SHL, ins->dreg, 4);
4728                         break;
4729                 case OP_ISHR:
4730                         g_assert (ins->sreg2 == AMD64_RCX);
4731                         amd64_shift_reg_size (code, X86_SAR, ins->dreg, 4);
4732                         break;
4733                 case OP_ISHR_IMM:
4734                         amd64_shift_reg_imm_size (code, X86_SAR, ins->dreg, ins->inst_imm, 4);
4735                         break;
4736                 case OP_ISHR_UN_IMM:
4737                         amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, ins->inst_imm, 4);
4738                         break;
4739                 case OP_ISHR_UN:
4740                         g_assert (ins->sreg2 == AMD64_RCX);
4741                         amd64_shift_reg_size (code, X86_SHR, ins->dreg, 4);
4742                         break;
4743                 case OP_ISHL_IMM:
4744                         amd64_shift_reg_imm_size (code, X86_SHL, ins->dreg, ins->inst_imm, 4);
4745                         break;
4746                 case OP_IMUL:
4747                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4748                         break;
4749                 case OP_IMUL_OVF:
4750                         amd64_imul_reg_reg_size (code, ins->sreg1, ins->sreg2, 4);
4751                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4752                         break;
4753                 case OP_IMUL_OVF_UN:
4754                 case OP_LMUL_OVF_UN: {
4755                         /* the mul operation and the exception check should most likely be split */
4756                         int non_eax_reg, saved_eax = FALSE, saved_edx = FALSE;
4757                         int size = (ins->opcode == OP_IMUL_OVF_UN) ? 4 : 8;
4758                         /*g_assert (ins->sreg2 == X86_EAX);
4759                         g_assert (ins->dreg == X86_EAX);*/
4760                         if (ins->sreg2 == X86_EAX) {
4761                                 non_eax_reg = ins->sreg1;
4762                         } else if (ins->sreg1 == X86_EAX) {
4763                                 non_eax_reg = ins->sreg2;
4764                         } else {
4765                                 /* no need to save since we're going to store to it anyway */
4766                                 if (ins->dreg != X86_EAX) {
4767                                         saved_eax = TRUE;
4768                                         amd64_push_reg (code, X86_EAX);
4769                                 }
4770                                 amd64_mov_reg_reg (code, X86_EAX, ins->sreg1, size);
4771                                 non_eax_reg = ins->sreg2;
4772                         }
4773                         if (ins->dreg == X86_EDX) {
4774                                 if (!saved_eax) {
4775                                         saved_eax = TRUE;
4776                                         amd64_push_reg (code, X86_EAX);
4777                                 }
4778                         } else {
4779                                 saved_edx = TRUE;
4780                                 amd64_push_reg (code, X86_EDX);
4781                         }
4782                         amd64_mul_reg_size (code, non_eax_reg, FALSE, size);
4783                         /* save before the check since pop and mov don't change the flags */
4784                         if (ins->dreg != X86_EAX)
4785                                 amd64_mov_reg_reg (code, ins->dreg, X86_EAX, size);
4786                         if (saved_edx)
4787                                 amd64_pop_reg (code, X86_EDX);
4788                         if (saved_eax)
4789                                 amd64_pop_reg (code, X86_EAX);
4790                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
4791                         break;
4792                 }
4793                 case OP_ICOMPARE:
4794                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
4795                         break;
4796                 case OP_ICOMPARE_IMM:
4797                         amd64_alu_reg_imm_size (code, X86_CMP, ins->sreg1, ins->inst_imm, 4);
4798                         break;
4799                 case OP_IBEQ:
4800                 case OP_IBLT:
4801                 case OP_IBGT:
4802                 case OP_IBGE:
4803                 case OP_IBLE:
4804                 case OP_LBEQ:
4805                 case OP_LBLT:
4806                 case OP_LBGT:
4807                 case OP_LBGE:
4808                 case OP_LBLE:
4809                 case OP_IBNE_UN:
4810                 case OP_IBLT_UN:
4811                 case OP_IBGT_UN:
4812                 case OP_IBGE_UN:
4813                 case OP_IBLE_UN:
4814                 case OP_LBNE_UN:
4815                 case OP_LBLT_UN:
4816                 case OP_LBGT_UN:
4817                 case OP_LBGE_UN:
4818                 case OP_LBLE_UN:
4819                         EMIT_COND_BRANCH (ins, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
4820                         break;
4821
4822                 case OP_CMOV_IEQ:
4823                 case OP_CMOV_IGE:
4824                 case OP_CMOV_IGT:
4825                 case OP_CMOV_ILE:
4826                 case OP_CMOV_ILT:
4827                 case OP_CMOV_INE_UN:
4828                 case OP_CMOV_IGE_UN:
4829                 case OP_CMOV_IGT_UN:
4830                 case OP_CMOV_ILE_UN:
4831                 case OP_CMOV_ILT_UN:
4832                 case OP_CMOV_LEQ:
4833                 case OP_CMOV_LGE:
4834                 case OP_CMOV_LGT:
4835                 case OP_CMOV_LLE:
4836                 case OP_CMOV_LLT:
4837                 case OP_CMOV_LNE_UN:
4838                 case OP_CMOV_LGE_UN:
4839                 case OP_CMOV_LGT_UN:
4840                 case OP_CMOV_LLE_UN:
4841                 case OP_CMOV_LLT_UN:
4842                         g_assert (ins->dreg == ins->sreg1);
4843                         /* This needs to operate on 64 bit values */
4844                         amd64_cmov_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, ins->sreg2);
4845                         break;
4846
4847                 case OP_LNOT:
4848                         amd64_not_reg (code, ins->sreg1);
4849                         break;
4850                 case OP_LNEG:
4851                         amd64_neg_reg (code, ins->sreg1);
4852                         break;
4853
4854                 case OP_ICONST:
4855                 case OP_I8CONST:
4856                         if ((((guint64)ins->inst_c0) >> 32) == 0 && !mini_get_debug_options()->single_imm_size)
4857                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 4);
4858                         else
4859                                 amd64_mov_reg_imm_size (code, ins->dreg, ins->inst_c0, 8);
4860                         break;
4861                 case OP_AOTCONST:
4862                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4863                         amd64_mov_reg_membase (code, ins->dreg, AMD64_RIP, 0, sizeof(gpointer));
4864                         break;
4865                 case OP_JUMP_TABLE:
4866                         mono_add_patch_info (cfg, offset, (MonoJumpInfoType)ins->inst_i1, ins->inst_p0);
4867                         amd64_mov_reg_imm_size (code, ins->dreg, 0, 8);
4868                         break;
4869                 case OP_MOVE:
4870                         if (ins->dreg != ins->sreg1)
4871                                 amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof(mgreg_t));
4872                         break;
4873                 case OP_AMD64_SET_XMMREG_R4: {
4874                         if (cfg->r4fp) {
4875                                 if (ins->dreg != ins->sreg1)
4876                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
4877                         } else {
4878                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
4879                         }
4880                         break;
4881                 }
4882                 case OP_AMD64_SET_XMMREG_R8: {
4883                         if (ins->dreg != ins->sreg1)
4884                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
4885                         break;
4886                 }
4887                 case OP_TAILCALL: {
4888                         MonoCallInst *call = (MonoCallInst*)ins;
4889                         int i, save_area_offset;
4890
4891                         g_assert (!cfg->method->save_lmf);
4892
4893                         /* Restore callee saved registers */
4894                         save_area_offset = cfg->arch.reg_save_area_offset;
4895                         for (i = 0; i < AMD64_NREG; ++i)
4896                                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->used_int_regs & (1 << i))) {
4897                                         amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
4898                                         save_area_offset += 8;
4899                                 }
4900
4901                         if (cfg->arch.omit_fp) {
4902                                 if (cfg->arch.stack_alloc_size)
4903                                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
4904                                 // FIXME:
4905                                 if (call->stack_usage)
4906                                         NOT_IMPLEMENTED;
4907                         } else {
4908                                 /* Copy arguments on the stack to our argument area */
4909                                 for (i = 0; i < call->stack_usage; i += sizeof(mgreg_t)) {
4910                                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, i, sizeof(mgreg_t));
4911                                         amd64_mov_membase_reg (code, AMD64_RBP, 16 + i, AMD64_RAX, sizeof(mgreg_t));
4912                                 }
4913
4914                                 amd64_leave (code);
4915                         }
4916
4917                         offset = code - cfg->native_code;
4918                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_METHOD_JUMP, call->method);
4919                         if (cfg->compile_aot)
4920                                 amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
4921                         else
4922                                 amd64_set_reg_template (code, AMD64_R11);
4923                         amd64_jump_reg (code, AMD64_R11);
4924                         ins->flags |= MONO_INST_GC_CALLSITE;
4925                         ins->backend.pc_offset = code - cfg->native_code;
4926                         break;
4927                 }
4928                 case OP_CHECK_THIS:
4929                         /* ensure ins->sreg1 is not NULL */
4930                         amd64_alu_membase_imm_size (code, X86_CMP, ins->sreg1, 0, 0, 4);
4931                         break;
4932                 case OP_ARGLIST: {
4933                         amd64_lea_membase (code, AMD64_R11, cfg->frame_reg, cfg->sig_cookie);
4934                         amd64_mov_membase_reg (code, ins->sreg1, 0, AMD64_R11, sizeof(gpointer));
4935                         break;
4936                 }
4937                 case OP_CALL:
4938                 case OP_FCALL:
4939                 case OP_RCALL:
4940                 case OP_LCALL:
4941                 case OP_VCALL:
4942                 case OP_VCALL2:
4943                 case OP_VOIDCALL:
4944                         call = (MonoCallInst*)ins;
4945                         /*
4946                          * The AMD64 ABI forces callers to know about varargs.
4947                          */
4948                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke))
4949                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4950                         else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4951                                 /*
4952                                  * Since the unmanaged calling convention doesn't contain a
4953                                  * 'vararg' entry, we have to treat every pinvoke call as a
4954                                  * potential vararg call.
4955                                  */
4956                                 guint32 nregs, i;
4957                                 nregs = 0;
4958                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
4959                                         if (call->used_fregs & (1 << i))
4960                                                 nregs ++;
4961                                 if (!nregs)
4962                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4963                                 else
4964                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
4965                         }
4966
4967                         if (ins->flags & MONO_INST_HAS_METHOD)
4968                                 code = emit_call (cfg, code, MONO_PATCH_INFO_METHOD, call->method, FALSE);
4969                         else
4970                                 code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, call->fptr, FALSE);
4971                         ins->flags |= MONO_INST_GC_CALLSITE;
4972                         ins->backend.pc_offset = code - cfg->native_code;
4973                         code = emit_move_return_value (cfg, ins, code);
4974                         break;
4975                 case OP_FCALL_REG:
4976                 case OP_RCALL_REG:
4977                 case OP_LCALL_REG:
4978                 case OP_VCALL_REG:
4979                 case OP_VCALL2_REG:
4980                 case OP_VOIDCALL_REG:
4981                 case OP_CALL_REG:
4982                         call = (MonoCallInst*)ins;
4983
4984                         if (AMD64_IS_ARGUMENT_REG (ins->sreg1)) {
4985                                 amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
4986                                 ins->sreg1 = AMD64_R11;
4987                         }
4988
4989                         /*
4990                          * The AMD64 ABI forces callers to know about varargs.
4991                          */
4992                         if ((call->signature->call_convention == MONO_CALL_VARARG) && (call->signature->pinvoke)) {
4993                                 if (ins->sreg1 == AMD64_RAX) {
4994                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
4995                                         ins->sreg1 = AMD64_R11;
4996                                 }
4997                                 amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
4998                         } else if ((cfg->method->wrapper_type == MONO_WRAPPER_MANAGED_TO_NATIVE) && (cfg->method->klass->image != mono_defaults.corlib)) {
4999                                 /*
5000                                  * Since the unmanaged calling convention doesn't contain a
5001                                  * 'vararg' entry, we have to treat every pinvoke call as a
5002                                  * potential vararg call.
5003                                  */
5004                                 guint32 nregs, i;
5005                                 nregs = 0;
5006                                 for (i = 0; i < AMD64_XMM_NREG; ++i)
5007                                         if (call->used_fregs & (1 << i))
5008                                                 nregs ++;
5009                                 if (ins->sreg1 == AMD64_RAX) {
5010                                         amd64_mov_reg_reg (code, AMD64_R11, AMD64_RAX, 8);
5011                                         ins->sreg1 = AMD64_R11;
5012                                 }
5013                                 if (!nregs)
5014                                         amd64_alu_reg_reg (code, X86_XOR, AMD64_RAX, AMD64_RAX);
5015                                 else
5016                                         amd64_mov_reg_imm (code, AMD64_RAX, nregs);
5017                         }
5018
5019                         amd64_call_reg (code, ins->sreg1);
5020                         ins->flags |= MONO_INST_GC_CALLSITE;
5021                         ins->backend.pc_offset = code - cfg->native_code;
5022                         code = emit_move_return_value (cfg, ins, code);
5023                         break;
5024                 case OP_FCALL_MEMBASE:
5025                 case OP_RCALL_MEMBASE:
5026                 case OP_LCALL_MEMBASE:
5027                 case OP_VCALL_MEMBASE:
5028                 case OP_VCALL2_MEMBASE:
5029                 case OP_VOIDCALL_MEMBASE:
5030                 case OP_CALL_MEMBASE:
5031                         call = (MonoCallInst*)ins;
5032
5033                         amd64_call_membase (code, ins->sreg1, ins->inst_offset);
5034                         ins->flags |= MONO_INST_GC_CALLSITE;
5035                         ins->backend.pc_offset = code - cfg->native_code;
5036                         code = emit_move_return_value (cfg, ins, code);
5037                         break;
5038                 case OP_DYN_CALL: {
5039                         int i;
5040                         MonoInst *var = cfg->dyn_call_var;
5041                         guint8 *label;
5042
5043                         g_assert (var->opcode == OP_REGOFFSET);
5044
5045                         /* r11 = args buffer filled by mono_arch_get_dyn_call_args () */
5046                         amd64_mov_reg_reg (code, AMD64_R11, ins->sreg1, 8);
5047                         /* r10 = ftn */
5048                         amd64_mov_reg_reg (code, AMD64_R10, ins->sreg2, 8);
5049
5050                         /* Save args buffer */
5051                         amd64_mov_membase_reg (code, var->inst_basereg, var->inst_offset, AMD64_R11, 8);
5052
5053                         /* Set fp arg regs */
5054                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, has_fp), sizeof (mgreg_t));
5055                         amd64_test_reg_reg (code, AMD64_RAX, AMD64_RAX);
5056                         label = code;
5057                         amd64_branch8 (code, X86_CC_Z, -1, 1);
5058                         for (i = 0; i < FLOAT_PARAM_REGS; ++i)
5059                                 amd64_sse_movsd_reg_membase (code, i, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs) + (i * sizeof (double)));
5060                         amd64_patch (label, code);
5061
5062                         /* Set argument registers */
5063                         for (i = 0; i < PARAM_REGS; ++i)
5064                                 amd64_mov_reg_membase (code, param_regs [i], AMD64_R11, i * sizeof(mgreg_t), sizeof(mgreg_t));
5065
5066                         /* Make the call */
5067                         amd64_call_reg (code, AMD64_R10);
5068
5069                         ins->flags |= MONO_INST_GC_CALLSITE;
5070                         ins->backend.pc_offset = code - cfg->native_code;
5071
5072                         /* Save result */
5073                         amd64_mov_reg_membase (code, AMD64_R11, var->inst_basereg, var->inst_offset, 8);
5074                         amd64_mov_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, res), AMD64_RAX, 8);
5075                         amd64_sse_movsd_membase_reg (code, AMD64_R11, MONO_STRUCT_OFFSET (DynCallArgs, fregs), AMD64_XMM0);
5076                         break;
5077                 }
5078                 case OP_AMD64_SAVE_SP_TO_LMF: {
5079                         MonoInst *lmf_var = cfg->lmf_var;
5080                         amd64_mov_membase_reg (code, lmf_var->inst_basereg, lmf_var->inst_offset + MONO_STRUCT_OFFSET (MonoLMF, rsp), AMD64_RSP, 8);
5081                         break;
5082                 }
5083                 case OP_X86_PUSH:
5084                         g_assert_not_reached ();
5085                         amd64_push_reg (code, ins->sreg1);
5086                         break;
5087                 case OP_X86_PUSH_IMM:
5088                         g_assert_not_reached ();
5089                         g_assert (amd64_is_imm32 (ins->inst_imm));
5090                         amd64_push_imm (code, ins->inst_imm);
5091                         break;
5092                 case OP_X86_PUSH_MEMBASE:
5093                         g_assert_not_reached ();
5094                         amd64_push_membase (code, ins->inst_basereg, ins->inst_offset);
5095                         break;
5096                 case OP_X86_PUSH_OBJ: {
5097                         int size = ALIGN_TO (ins->inst_imm, 8);
5098
5099                         g_assert_not_reached ();
5100
5101                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5102                         amd64_push_reg (code, AMD64_RDI);
5103                         amd64_push_reg (code, AMD64_RSI);
5104                         amd64_push_reg (code, AMD64_RCX);
5105                         if (ins->inst_offset)
5106                                 amd64_lea_membase (code, AMD64_RSI, ins->inst_basereg, ins->inst_offset);
5107                         else
5108                                 amd64_mov_reg_reg (code, AMD64_RSI, ins->inst_basereg, 8);
5109                         amd64_lea_membase (code, AMD64_RDI, AMD64_RSP, (3 * 8));
5110                         amd64_mov_reg_imm (code, AMD64_RCX, (size >> 3));
5111                         amd64_cld (code);
5112                         amd64_prefix (code, X86_REP_PREFIX);
5113                         amd64_movsd (code);
5114                         amd64_pop_reg (code, AMD64_RCX);
5115                         amd64_pop_reg (code, AMD64_RSI);
5116                         amd64_pop_reg (code, AMD64_RDI);
5117                         break;
5118                 }
5119                 case OP_GENERIC_CLASS_INIT: {
5120                         static int byte_offset = -1;
5121                         static guint8 bitmask;
5122                         guint8 *jump;
5123
5124                         g_assert (ins->sreg1 == MONO_AMD64_ARG_REG1);
5125
5126                         if (byte_offset < 0)
5127                                 mono_marshal_find_bitfield_offset (MonoVTable, initialized, &byte_offset, &bitmask);
5128
5129                         amd64_test_membase_imm_size (code, ins->sreg1, byte_offset, bitmask, 1);
5130                         jump = code;
5131                         amd64_branch8 (code, X86_CC_NZ, -1, 1);
5132
5133                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_generic_class_init", FALSE);
5134                         ins->flags |= MONO_INST_GC_CALLSITE;
5135                         ins->backend.pc_offset = code - cfg->native_code;
5136
5137                         x86_patch (jump, code);
5138                         break;
5139                 }
5140
5141                 case OP_X86_LEA:
5142                         amd64_lea_memindex (code, ins->dreg, ins->sreg1, ins->inst_imm, ins->sreg2, ins->backend.shift_amount);
5143                         break;
5144                 case OP_X86_LEA_MEMBASE:
5145                         amd64_lea_membase (code, ins->dreg, ins->sreg1, ins->inst_imm);
5146                         break;
5147                 case OP_X86_XCHG:
5148                         amd64_xchg_reg_reg (code, ins->sreg1, ins->sreg2, 4);
5149                         break;
5150                 case OP_LOCALLOC:
5151                         /* keep alignment */
5152                         amd64_alu_reg_imm (code, X86_ADD, ins->sreg1, MONO_ARCH_FRAME_ALIGNMENT - 1);
5153                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ~(MONO_ARCH_FRAME_ALIGNMENT - 1));
5154                         code = mono_emit_stack_alloc (cfg, code, ins);
5155                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5156                         if (cfg->param_area)
5157                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5158                         break;
5159                 case OP_LOCALLOC_IMM: {
5160                         guint32 size = ins->inst_imm;
5161                         size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
5162
5163                         if (ins->flags & MONO_INST_INIT) {
5164                                 if (size < 64) {
5165                                         int i;
5166
5167                                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5168                                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5169
5170                                         for (i = 0; i < size; i += 8)
5171                                                 amd64_mov_membase_reg (code, AMD64_RSP, i, ins->dreg, 8);
5172                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5173                                 } else {
5174                                         amd64_mov_reg_imm (code, ins->dreg, size);
5175                                         ins->sreg1 = ins->dreg;
5176
5177                                         code = mono_emit_stack_alloc (cfg, code, ins);
5178                                         amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5179                                 }
5180                         } else {
5181                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, size);
5182                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RSP, 8);
5183                         }
5184                         if (cfg->param_area)
5185                                 amd64_alu_reg_imm (code, X86_ADD, ins->dreg, cfg->param_area);
5186                         break;
5187                 }
5188                 case OP_THROW: {
5189                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5190                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5191                                              (gpointer)"mono_arch_throw_exception", FALSE);
5192                         ins->flags |= MONO_INST_GC_CALLSITE;
5193                         ins->backend.pc_offset = code - cfg->native_code;
5194                         break;
5195                 }
5196                 case OP_RETHROW: {
5197                         amd64_mov_reg_reg (code, AMD64_ARG_REG1, ins->sreg1, 8);
5198                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD,
5199                                              (gpointer)"mono_arch_rethrow_exception", FALSE);
5200                         ins->flags |= MONO_INST_GC_CALLSITE;
5201                         ins->backend.pc_offset = code - cfg->native_code;
5202                         break;
5203                 }
5204                 case OP_CALL_HANDLER:
5205                         /* Align stack */
5206                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
5207                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5208                         amd64_call_imm (code, 0);
5209                         mono_cfg_add_try_hole (cfg, ins->inst_eh_block, code, bb);
5210                         /* Restore stack alignment */
5211                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
5212                         break;
5213                 case OP_START_HANDLER: {
5214                         /* Even though we're saving RSP, use sizeof */
5215                         /* gpointer because spvar is of type IntPtr */
5216                         /* see: mono_create_spvar_for_region */
5217                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5218                         amd64_mov_membase_reg (code, spvar->inst_basereg, spvar->inst_offset, AMD64_RSP, sizeof(gpointer));
5219
5220                         if ((MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY) ||
5221                                  MONO_BBLOCK_IS_IN_REGION (bb, MONO_REGION_FINALLY)) &&
5222                                 cfg->param_area) {
5223                                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, ALIGN_TO (cfg->param_area, MONO_ARCH_FRAME_ALIGNMENT));
5224                         }
5225                         break;
5226                 }
5227                 case OP_ENDFINALLY: {
5228                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5229                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5230                         amd64_ret (code);
5231                         break;
5232                 }
5233                 case OP_ENDFILTER: {
5234                         MonoInst *spvar = mono_find_spvar_for_region (cfg, bb->region);
5235                         amd64_mov_reg_membase (code, AMD64_RSP, spvar->inst_basereg, spvar->inst_offset, sizeof(gpointer));
5236                         /* The local allocator will put the result into RAX */
5237                         amd64_ret (code);
5238                         break;
5239                 }
5240                 case OP_GET_EX_OBJ:
5241                         if (ins->dreg != AMD64_RAX)
5242                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, sizeof (gpointer));
5243                         break;
5244                 case OP_LABEL:
5245                         ins->inst_c0 = code - cfg->native_code;
5246                         break;
5247                 case OP_BR:
5248                         //g_print ("target: %p, next: %p, curr: %p, last: %p\n", ins->inst_target_bb, bb->next_bb, ins, bb->last_ins);
5249                         //if ((ins->inst_target_bb == bb->next_bb) && ins == bb->last_ins)
5250                         //break;
5251                                 if (ins->inst_target_bb->native_offset) {
5252                                         amd64_jump_code (code, cfg->native_code + ins->inst_target_bb->native_offset);
5253                                 } else {
5254                                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_BB, ins->inst_target_bb);
5255                                         if ((cfg->opt & MONO_OPT_BRANCH) &&
5256                                             x86_is_imm8 (ins->inst_target_bb->max_offset - offset))
5257                                                 x86_jump8 (code, 0);
5258                                         else
5259                                                 x86_jump32 (code, 0);
5260                         }
5261                         break;
5262                 case OP_BR_REG:
5263                         amd64_jump_reg (code, ins->sreg1);
5264                         break;
5265                 case OP_ICNEQ:
5266                 case OP_ICGE:
5267                 case OP_ICLE:
5268                 case OP_ICGE_UN:
5269                 case OP_ICLE_UN:
5270
5271                 case OP_CEQ:
5272                 case OP_LCEQ:
5273                 case OP_ICEQ:
5274                 case OP_CLT:
5275                 case OP_LCLT:
5276                 case OP_ICLT:
5277                 case OP_CGT:
5278                 case OP_ICGT:
5279                 case OP_LCGT:
5280                 case OP_CLT_UN:
5281                 case OP_LCLT_UN:
5282                 case OP_ICLT_UN:
5283                 case OP_CGT_UN:
5284                 case OP_LCGT_UN:
5285                 case OP_ICGT_UN:
5286                         amd64_set_reg (code, cc_table [mono_opcode_to_cond (ins->opcode)], ins->dreg, cc_signed_table [mono_opcode_to_cond (ins->opcode)]);
5287                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5288                         break;
5289                 case OP_COND_EXC_EQ:
5290                 case OP_COND_EXC_NE_UN:
5291                 case OP_COND_EXC_LT:
5292                 case OP_COND_EXC_LT_UN:
5293                 case OP_COND_EXC_GT:
5294                 case OP_COND_EXC_GT_UN:
5295                 case OP_COND_EXC_GE:
5296                 case OP_COND_EXC_GE_UN:
5297                 case OP_COND_EXC_LE:
5298                 case OP_COND_EXC_LE_UN:
5299                 case OP_COND_EXC_IEQ:
5300                 case OP_COND_EXC_INE_UN:
5301                 case OP_COND_EXC_ILT:
5302                 case OP_COND_EXC_ILT_UN:
5303                 case OP_COND_EXC_IGT:
5304                 case OP_COND_EXC_IGT_UN:
5305                 case OP_COND_EXC_IGE:
5306                 case OP_COND_EXC_IGE_UN:
5307                 case OP_COND_EXC_ILE:
5308                 case OP_COND_EXC_ILE_UN:
5309                         EMIT_COND_SYSTEM_EXCEPTION (cc_table [mono_opcode_to_cond (ins->opcode)], cc_signed_table [mono_opcode_to_cond (ins->opcode)], (const char *)ins->inst_p1);
5310                         break;
5311                 case OP_COND_EXC_OV:
5312                 case OP_COND_EXC_NO:
5313                 case OP_COND_EXC_C:
5314                 case OP_COND_EXC_NC:
5315                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_EQ],
5316                                                     (ins->opcode < OP_COND_EXC_NE_UN), (const char *)ins->inst_p1);
5317                         break;
5318                 case OP_COND_EXC_IOV:
5319                 case OP_COND_EXC_INO:
5320                 case OP_COND_EXC_IC:
5321                 case OP_COND_EXC_INC:
5322                         EMIT_COND_SYSTEM_EXCEPTION (branch_cc_table [ins->opcode - OP_COND_EXC_IEQ],
5323                                                     (ins->opcode < OP_COND_EXC_INE_UN), (const char *)ins->inst_p1);
5324                         break;
5325
5326                 /* floating point opcodes */
5327                 case OP_R8CONST: {
5328                         double d = *(double *)ins->inst_p0;
5329
5330                         if ((d == 0.0) && (mono_signbit (d) == 0)) {
5331                                 amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5332                         }
5333                         else {
5334                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, ins->inst_p0);
5335                                 amd64_sse_movsd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5336                         }
5337                         break;
5338                 }
5339                 case OP_R4CONST: {
5340                         float f = *(float *)ins->inst_p0;
5341
5342                         if ((f == 0.0) && (mono_signbit (f) == 0)) {
5343                                 if (cfg->r4fp)
5344                                         amd64_sse_xorps_reg_reg (code, ins->dreg, ins->dreg);
5345                                 else
5346                                         amd64_sse_xorpd_reg_reg (code, ins->dreg, ins->dreg);
5347                         }
5348                         else {
5349                                 mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, ins->inst_p0);
5350                                 amd64_sse_movss_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5351                                 if (!cfg->r4fp)
5352                                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5353                         }
5354                         break;
5355                 }
5356                 case OP_STORER8_MEMBASE_REG:
5357                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5358                         break;
5359                 case OP_LOADR8_MEMBASE:
5360                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5361                         break;
5362                 case OP_STORER4_MEMBASE_REG:
5363                         if (cfg->r4fp) {
5364                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
5365                         } else {
5366                                 /* This requires a double->single conversion */
5367                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5368                                 amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
5369                         }
5370                         break;
5371                 case OP_LOADR4_MEMBASE:
5372                         if (cfg->r4fp) {
5373                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5374                         } else {
5375                                 amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
5376                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5377                         }
5378                         break;
5379                 case OP_ICONV_TO_R4:
5380                         if (cfg->r4fp) {
5381                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5382                         } else {
5383                                 amd64_sse_cvtsi2ss_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5384                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5385                         }
5386                         break;
5387                 case OP_ICONV_TO_R8:
5388                         amd64_sse_cvtsi2sd_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5389                         break;
5390                 case OP_LCONV_TO_R4:
5391                         if (cfg->r4fp) {
5392                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5393                         } else {
5394                                 amd64_sse_cvtsi2ss_reg_reg (code, ins->dreg, ins->sreg1);
5395                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5396                         }
5397                         break;
5398                 case OP_LCONV_TO_R8:
5399                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5400                         break;
5401                 case OP_FCONV_TO_R4:
5402                         if (cfg->r4fp) {
5403                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5404                         } else {
5405                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg1);
5406                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5407                         }
5408                         break;
5409                 case OP_FCONV_TO_I1:
5410                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
5411                         break;
5412                 case OP_FCONV_TO_U1:
5413                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, FALSE);
5414                         break;
5415                 case OP_FCONV_TO_I2:
5416                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, TRUE);
5417                         break;
5418                 case OP_FCONV_TO_U2:
5419                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 2, FALSE);
5420                         break;
5421                 case OP_FCONV_TO_U4:
5422                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, FALSE);
5423                         break;
5424                 case OP_FCONV_TO_I4:
5425                 case OP_FCONV_TO_I:
5426                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 4, TRUE);
5427                         break;
5428                 case OP_FCONV_TO_I8:
5429                         code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 8, TRUE);
5430                         break;
5431
5432                 case OP_RCONV_TO_I1:
5433                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5434                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
5435                         break;
5436                 case OP_RCONV_TO_U1:
5437                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5438                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
5439                         break;
5440                 case OP_RCONV_TO_I2:
5441                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5442                         amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
5443                         break;
5444                 case OP_RCONV_TO_U2:
5445                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5446                         amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
5447                         break;
5448                 case OP_RCONV_TO_I4:
5449                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5450                         break;
5451                 case OP_RCONV_TO_U4:
5452                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 4);
5453                         break;
5454                 case OP_RCONV_TO_I8:
5455                         amd64_sse_cvtss2si_reg_reg_size (code, ins->dreg, ins->sreg1, 8);
5456                         break;
5457                 case OP_RCONV_TO_R8:
5458                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->sreg1);
5459                         break;
5460                 case OP_RCONV_TO_R4:
5461                         if (ins->dreg != ins->sreg1)
5462                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5463                         break;
5464
5465                 case OP_LCONV_TO_R_UN: {
5466                         guint8 *br [2];
5467
5468                         /* Based on gcc code */
5469                         amd64_test_reg_reg (code, ins->sreg1, ins->sreg1);
5470                         br [0] = code; x86_branch8 (code, X86_CC_S, 0, TRUE);
5471
5472                         /* Positive case */
5473                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, ins->sreg1);
5474                         br [1] = code; x86_jump8 (code, 0);
5475                         amd64_patch (br [0], code);
5476
5477                         /* Negative case */
5478                         /* Save to the red zone */
5479                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RAX, 8);
5480                         amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
5481                         amd64_mov_reg_reg (code, AMD64_RCX, ins->sreg1, 8);
5482                         amd64_mov_reg_reg (code, AMD64_RAX, ins->sreg1, 8);
5483                         amd64_alu_reg_imm (code, X86_AND, AMD64_RCX, 1);
5484                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RAX, 1);
5485                         amd64_alu_reg_imm (code, X86_OR, AMD64_RAX, AMD64_RCX);
5486                         amd64_sse_cvtsi2sd_reg_reg (code, ins->dreg, AMD64_RAX);
5487                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->dreg);
5488                         /* Restore */
5489                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
5490                         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_RSP, -8, 8);
5491                         amd64_patch (br [1], code);
5492                         break;
5493                 }
5494                 case OP_LCONV_TO_OVF_U4:
5495                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0);
5496                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_LT, TRUE, "OverflowException");
5497                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5498                         break;
5499                 case OP_LCONV_TO_OVF_I4_UN:
5500                         amd64_alu_reg_imm (code, X86_CMP, ins->sreg1, 0x7fffffff);
5501                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_GT, FALSE, "OverflowException");
5502                         amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, 8);
5503                         break;
5504                 case OP_FMOVE:
5505                         if (ins->dreg != ins->sreg1)
5506                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
5507                         break;
5508                 case OP_RMOVE:
5509                         if (ins->dreg != ins->sreg1)
5510                                 amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg1);
5511                         break;
5512                 case OP_MOVE_F_TO_I4:
5513                         if (cfg->r4fp) {
5514                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5515                         } else {
5516                                 amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
5517                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
5518                         }
5519                         break;
5520                 case OP_MOVE_I4_TO_F:
5521                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5522                         if (!cfg->r4fp)
5523                                 amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
5524                         break;
5525                 case OP_MOVE_F_TO_I8:
5526                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
5527                         break;
5528                 case OP_MOVE_I8_TO_F:
5529                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
5530                         break;
5531                 case OP_FADD:
5532                         amd64_sse_addsd_reg_reg (code, ins->dreg, ins->sreg2);
5533                         break;
5534                 case OP_FSUB:
5535                         amd64_sse_subsd_reg_reg (code, ins->dreg, ins->sreg2);
5536                         break;
5537                 case OP_FMUL:
5538                         amd64_sse_mulsd_reg_reg (code, ins->dreg, ins->sreg2);
5539                         break;
5540                 case OP_FDIV:
5541                         amd64_sse_divsd_reg_reg (code, ins->dreg, ins->sreg2);
5542                         break;
5543                 case OP_FNEG: {
5544                         static double r8_0 = -0.0;
5545
5546                         g_assert (ins->sreg1 == ins->dreg);
5547
5548                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &r8_0);
5549                         amd64_sse_xorpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5550                         break;
5551                 }
5552                 case OP_SIN:
5553                         EMIT_SSE2_FPFUNC (code, fsin, ins->dreg, ins->sreg1);
5554                         break;
5555                 case OP_COS:
5556                         EMIT_SSE2_FPFUNC (code, fcos, ins->dreg, ins->sreg1);
5557                         break;
5558                 case OP_ABS: {
5559                         static guint64 d = 0x7fffffffffffffffUL;
5560
5561                         g_assert (ins->sreg1 == ins->dreg);
5562
5563                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R8, &d);
5564                         amd64_sse_andpd_reg_membase (code, ins->dreg, AMD64_RIP, 0);
5565                         break;
5566                 }
5567                 case OP_SQRT:
5568                         EMIT_SSE2_FPFUNC (code, fsqrt, ins->dreg, ins->sreg1);
5569                         break;
5570
5571                 case OP_RADD:
5572                         amd64_sse_addss_reg_reg (code, ins->dreg, ins->sreg2);
5573                         break;
5574                 case OP_RSUB:
5575                         amd64_sse_subss_reg_reg (code, ins->dreg, ins->sreg2);
5576                         break;
5577                 case OP_RMUL:
5578                         amd64_sse_mulss_reg_reg (code, ins->dreg, ins->sreg2);
5579                         break;
5580                 case OP_RDIV:
5581                         amd64_sse_divss_reg_reg (code, ins->dreg, ins->sreg2);
5582                         break;
5583                 case OP_RNEG: {
5584                         static float r4_0 = -0.0;
5585
5586                         g_assert (ins->sreg1 == ins->dreg);
5587
5588                         mono_add_patch_info (cfg, offset, MONO_PATCH_INFO_R4, &r4_0);
5589                         amd64_sse_movss_reg_membase (code, MONO_ARCH_FP_SCRATCH_REG, AMD64_RIP, 0);
5590                         amd64_sse_xorps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
5591                         break;
5592                 }
5593
5594                 case OP_IMIN:
5595                         g_assert (cfg->opt & MONO_OPT_CMOV);
5596                         g_assert (ins->dreg == ins->sreg1);
5597                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5598                         amd64_cmov_reg_size (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2, 4);
5599                         break;
5600                 case OP_IMIN_UN:
5601                         g_assert (cfg->opt & MONO_OPT_CMOV);
5602                         g_assert (ins->dreg == ins->sreg1);
5603                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5604                         amd64_cmov_reg_size (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2, 4);
5605                         break;
5606                 case OP_IMAX:
5607                         g_assert (cfg->opt & MONO_OPT_CMOV);
5608                         g_assert (ins->dreg == ins->sreg1);
5609                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5610                         amd64_cmov_reg_size (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2, 4);
5611                         break;
5612                 case OP_IMAX_UN:
5613                         g_assert (cfg->opt & MONO_OPT_CMOV);
5614                         g_assert (ins->dreg == ins->sreg1);
5615                         amd64_alu_reg_reg_size (code, X86_CMP, ins->sreg1, ins->sreg2, 4);
5616                         amd64_cmov_reg_size (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2, 4);
5617                         break;
5618                 case OP_LMIN:
5619                         g_assert (cfg->opt & MONO_OPT_CMOV);
5620                         g_assert (ins->dreg == ins->sreg1);
5621                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5622                         amd64_cmov_reg (code, X86_CC_GT, TRUE, ins->dreg, ins->sreg2);
5623                         break;
5624                 case OP_LMIN_UN:
5625                         g_assert (cfg->opt & MONO_OPT_CMOV);
5626                         g_assert (ins->dreg == ins->sreg1);
5627                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5628                         amd64_cmov_reg (code, X86_CC_GT, FALSE, ins->dreg, ins->sreg2);
5629                         break;
5630                 case OP_LMAX:
5631                         g_assert (cfg->opt & MONO_OPT_CMOV);
5632                         g_assert (ins->dreg == ins->sreg1);
5633                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5634                         amd64_cmov_reg (code, X86_CC_LT, TRUE, ins->dreg, ins->sreg2);
5635                         break;
5636                 case OP_LMAX_UN:
5637                         g_assert (cfg->opt & MONO_OPT_CMOV);
5638                         g_assert (ins->dreg == ins->sreg1);
5639                         amd64_alu_reg_reg (code, X86_CMP, ins->sreg1, ins->sreg2);
5640                         amd64_cmov_reg (code, X86_CC_LT, FALSE, ins->dreg, ins->sreg2);
5641                         break;
5642                 case OP_X86_FPOP:
5643                         break;
5644                 case OP_FCOMPARE:
5645                         /*
5646                          * The two arguments are swapped because the fbranch instructions
5647                          * depend on this for the non-sse case to work.
5648                          */
5649                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5650                         break;
5651                 case OP_RCOMPARE:
5652                         /*
5653                          * FIXME: Get rid of this.
5654                          * The two arguments are swapped because the fbranch instructions
5655                          * depend on this for the non-sse case to work.
5656                          */
5657                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5658                         break;
5659                 case OP_FCNEQ:
5660                 case OP_FCEQ: {
5661                         /* zeroing the register at the start results in
5662                          * shorter and faster code (we can also remove the widening op)
5663                          */
5664                         guchar *unordered_check;
5665
5666                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5667                         amd64_sse_comisd_reg_reg (code, ins->sreg1, ins->sreg2);
5668                         unordered_check = code;
5669                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5670
5671                         if (ins->opcode == OP_FCEQ) {
5672                                 amd64_set_reg (code, X86_CC_EQ, ins->dreg, FALSE);
5673                                 amd64_patch (unordered_check, code);
5674                         } else {
5675                                 guchar *jump_to_end;
5676                                 amd64_set_reg (code, X86_CC_NE, ins->dreg, FALSE);
5677                                 jump_to_end = code;
5678                                 x86_jump8 (code, 0);
5679                                 amd64_patch (unordered_check, code);
5680                                 amd64_inc_reg (code, ins->dreg);
5681                                 amd64_patch (jump_to_end, code);
5682                         }
5683                         break;
5684                 }
5685                 case OP_FCLT:
5686                 case OP_FCLT_UN: {
5687                         /* zeroing the register at the start results in
5688                          * shorter and faster code (we can also remove the widening op)
5689                          */
5690                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5691                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5692                         if (ins->opcode == OP_FCLT_UN) {
5693                                 guchar *unordered_check = code;
5694                                 guchar *jump_to_end;
5695                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5696                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5697                                 jump_to_end = code;
5698                                 x86_jump8 (code, 0);
5699                                 amd64_patch (unordered_check, code);
5700                                 amd64_inc_reg (code, ins->dreg);
5701                                 amd64_patch (jump_to_end, code);
5702                         } else {
5703                                 amd64_set_reg (code, X86_CC_GT, ins->dreg, FALSE);
5704                         }
5705                         break;
5706                 }
5707                 case OP_FCLE: {
5708                         guchar *unordered_check;
5709                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5710                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5711                         unordered_check = code;
5712                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5713                         amd64_set_reg (code, X86_CC_NB, ins->dreg, FALSE);
5714                         amd64_patch (unordered_check, code);
5715                         break;
5716                 }
5717                 case OP_FCGT:
5718                 case OP_FCGT_UN: {
5719                         /* zeroing the register at the start results in
5720                          * shorter and faster code (we can also remove the widening op)
5721                          */
5722                         guchar *unordered_check;
5723
5724                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5725                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5726                         if (ins->opcode == OP_FCGT) {
5727                                 unordered_check = code;
5728                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5729                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5730                                 amd64_patch (unordered_check, code);
5731                         } else {
5732                                 amd64_set_reg (code, X86_CC_LT, ins->dreg, FALSE);
5733                         }
5734                         break;
5735                 }
5736                 case OP_FCGE: {
5737                         guchar *unordered_check;
5738                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5739                         amd64_sse_comisd_reg_reg (code, ins->sreg2, ins->sreg1);
5740                         unordered_check = code;
5741                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5742                         amd64_set_reg (code, X86_CC_NA, ins->dreg, FALSE);
5743                         amd64_patch (unordered_check, code);
5744                         break;
5745                 }
5746
5747                 case OP_RCEQ:
5748                 case OP_RCGT:
5749                 case OP_RCLT:
5750                 case OP_RCLT_UN:
5751                 case OP_RCGT_UN: {
5752                         int x86_cond;
5753                         gboolean unordered = FALSE;
5754
5755                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5756                         amd64_sse_comiss_reg_reg (code, ins->sreg2, ins->sreg1);
5757
5758                         switch (ins->opcode) {
5759                         case OP_RCEQ:
5760                                 x86_cond = X86_CC_EQ;
5761                                 break;
5762                         case OP_RCGT:
5763                                 x86_cond = X86_CC_LT;
5764                                 break;
5765                         case OP_RCLT:
5766                                 x86_cond = X86_CC_GT;
5767                                 break;
5768                         case OP_RCLT_UN:
5769                                 x86_cond = X86_CC_GT;
5770                                 unordered = TRUE;
5771                                 break;
5772                         case OP_RCGT_UN:
5773                                 x86_cond = X86_CC_LT;
5774                                 unordered = TRUE;
5775                                 break;
5776                         default:
5777                                 g_assert_not_reached ();
5778                                 break;
5779                         }
5780
5781                         if (unordered) {
5782                                 guchar *unordered_check;
5783                                 guchar *jump_to_end;
5784
5785                                 unordered_check = code;
5786                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5787                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5788                                 jump_to_end = code;
5789                                 x86_jump8 (code, 0);
5790                                 amd64_patch (unordered_check, code);
5791                                 amd64_inc_reg (code, ins->dreg);
5792                                 amd64_patch (jump_to_end, code);
5793                         } else {
5794                                 amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5795                         }
5796                         break;
5797                 }
5798                 case OP_FCLT_MEMBASE:
5799                 case OP_FCGT_MEMBASE:
5800                 case OP_FCLT_UN_MEMBASE:
5801                 case OP_FCGT_UN_MEMBASE:
5802                 case OP_FCEQ_MEMBASE: {
5803                         guchar *unordered_check, *jump_to_end;
5804                         int x86_cond;
5805
5806                         amd64_alu_reg_reg (code, X86_XOR, ins->dreg, ins->dreg);
5807                         amd64_sse_comisd_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
5808
5809                         switch (ins->opcode) {
5810                         case OP_FCEQ_MEMBASE:
5811                                 x86_cond = X86_CC_EQ;
5812                                 break;
5813                         case OP_FCLT_MEMBASE:
5814                         case OP_FCLT_UN_MEMBASE:
5815                                 x86_cond = X86_CC_LT;
5816                                 break;
5817                         case OP_FCGT_MEMBASE:
5818                         case OP_FCGT_UN_MEMBASE:
5819                                 x86_cond = X86_CC_GT;
5820                                 break;
5821                         default:
5822                                 g_assert_not_reached ();
5823                         }
5824
5825                         unordered_check = code;
5826                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5827                         amd64_set_reg (code, x86_cond, ins->dreg, FALSE);
5828
5829                         switch (ins->opcode) {
5830                         case OP_FCEQ_MEMBASE:
5831                         case OP_FCLT_MEMBASE:
5832                         case OP_FCGT_MEMBASE:
5833                                 amd64_patch (unordered_check, code);
5834                                 break;
5835                         case OP_FCLT_UN_MEMBASE:
5836                         case OP_FCGT_UN_MEMBASE:
5837                                 jump_to_end = code;
5838                                 x86_jump8 (code, 0);
5839                                 amd64_patch (unordered_check, code);
5840                                 amd64_inc_reg (code, ins->dreg);
5841                                 amd64_patch (jump_to_end, code);
5842                                 break;
5843                         default:
5844                                 break;
5845                         }
5846                         break;
5847                 }
5848                 case OP_FBEQ: {
5849                         guchar *jump = code;
5850                         x86_branch8 (code, X86_CC_P, 0, TRUE);
5851                         EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
5852                         amd64_patch (jump, code);
5853                         break;
5854                 }
5855                 case OP_FBNE_UN:
5856                         /* Branch if C013 != 100 */
5857                         /* branch if !ZF or (PF|CF) */
5858                         EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
5859                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5860                         EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
5861                         break;
5862                 case OP_FBLT:
5863                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5864                         break;
5865                 case OP_FBLT_UN:
5866                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5867                         EMIT_COND_BRANCH (ins, X86_CC_GT, FALSE);
5868                         break;
5869                 case OP_FBGT:
5870                 case OP_FBGT_UN:
5871                         if (ins->opcode == OP_FBGT) {
5872                                 guchar *br1;
5873
5874                                 /* skip branch if C1=1 */
5875                                 br1 = code;
5876                                 x86_branch8 (code, X86_CC_P, 0, FALSE);
5877                                 /* branch if (C0 | C3) = 1 */
5878                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5879                                 amd64_patch (br1, code);
5880                                 break;
5881                         } else {
5882                                 EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
5883                         }
5884                         break;
5885                 case OP_FBGE: {
5886                         /* Branch if C013 == 100 or 001 */
5887                         guchar *br1;
5888
5889                         /* skip branch if C1=1 */
5890                         br1 = code;
5891                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5892                         /* branch if (C0 | C3) = 1 */
5893                         EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
5894                         amd64_patch (br1, code);
5895                         break;
5896                 }
5897                 case OP_FBGE_UN:
5898                         /* Branch if C013 == 000 */
5899                         EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
5900                         break;
5901                 case OP_FBLE: {
5902                         /* Branch if C013=000 or 100 */
5903                         guchar *br1;
5904
5905                         /* skip branch if C1=1 */
5906                         br1 = code;
5907                         x86_branch8 (code, X86_CC_P, 0, FALSE);
5908                         /* branch if C0=0 */
5909                         EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
5910                         amd64_patch (br1, code);
5911                         break;
5912                 }
5913                 case OP_FBLE_UN:
5914                         /* Branch if C013 != 001 */
5915                         EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
5916                         EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
5917                         break;
5918                 case OP_CKFINITE:
5919                         /* Transfer value to the fp stack */
5920                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 16);
5921                         amd64_movsd_membase_reg (code, AMD64_RSP, 0, ins->sreg1);
5922                         amd64_fld_membase (code, AMD64_RSP, 0, TRUE);
5923
5924                         amd64_push_reg (code, AMD64_RAX);
5925                         amd64_fxam (code);
5926                         amd64_fnstsw (code);
5927                         amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0x4100);
5928                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, X86_FP_C0);
5929                         amd64_pop_reg (code, AMD64_RAX);
5930                         amd64_fstp (code, 0);
5931                         EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
5932                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 16);
5933                         break;
5934                 case OP_TLS_GET: {
5935                         code = mono_amd64_emit_tls_get (code, ins->dreg, ins->inst_offset);
5936                         break;
5937                 }
5938                 case OP_TLS_GET_REG:
5939                         code = emit_tls_get_reg (code, ins->dreg, ins->sreg1);
5940                         break;
5941                 case OP_TLS_SET: {
5942                         code = amd64_emit_tls_set (code, ins->sreg1, ins->inst_offset);
5943                         break;
5944                 }
5945                 case OP_TLS_SET_REG: {
5946                         code = amd64_emit_tls_set_reg (code, ins->sreg1, ins->sreg2);
5947                         break;
5948                 }
5949                 case OP_MEMORY_BARRIER: {
5950                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
5951                                 x86_mfence (code);
5952                         break;
5953                 }
5954                 case OP_ATOMIC_ADD_I4:
5955                 case OP_ATOMIC_ADD_I8: {
5956                         int dreg = ins->dreg;
5957                         guint32 size = (ins->opcode == OP_ATOMIC_ADD_I4) ? 4 : 8;
5958
5959                         if ((dreg == ins->sreg2) || (dreg == ins->inst_basereg))
5960                                 dreg = AMD64_R11;
5961
5962                         amd64_mov_reg_reg (code, dreg, ins->sreg2, size);
5963                         amd64_prefix (code, X86_LOCK_PREFIX);
5964                         amd64_xadd_membase_reg (code, ins->inst_basereg, ins->inst_offset, dreg, size);
5965                         /* dreg contains the old value, add with sreg2 value */
5966                         amd64_alu_reg_reg_size (code, X86_ADD, dreg, ins->sreg2, size);
5967
5968                         if (ins->dreg != dreg)
5969                                 amd64_mov_reg_reg (code, ins->dreg, dreg, size);
5970
5971                         break;
5972                 }
5973                 case OP_ATOMIC_EXCHANGE_I4:
5974                 case OP_ATOMIC_EXCHANGE_I8: {
5975                         guint32 size = ins->opcode == OP_ATOMIC_EXCHANGE_I4 ? 4 : 8;
5976
5977                         /* LOCK prefix is implied. */
5978                         amd64_mov_reg_reg (code, GP_SCRATCH_REG, ins->sreg2, size);
5979                         amd64_xchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, GP_SCRATCH_REG, size);
5980                         amd64_mov_reg_reg (code, ins->dreg, GP_SCRATCH_REG, size);
5981                         break;
5982                 }
5983                 case OP_ATOMIC_CAS_I4:
5984                 case OP_ATOMIC_CAS_I8: {
5985                         guint32 size;
5986
5987                         if (ins->opcode == OP_ATOMIC_CAS_I8)
5988                                 size = 8;
5989                         else
5990                                 size = 4;
5991
5992                         /*
5993                          * See http://msdn.microsoft.com/en-us/magazine/cc302329.aspx for
5994                          * an explanation of how this works.
5995                          */
5996                         g_assert (ins->sreg3 == AMD64_RAX);
5997                         g_assert (ins->sreg1 != AMD64_RAX);
5998                         g_assert (ins->sreg1 != ins->sreg2);
5999
6000                         amd64_prefix (code, X86_LOCK_PREFIX);
6001                         amd64_cmpxchg_membase_reg_size (code, ins->sreg1, ins->inst_offset, ins->sreg2, size);
6002
6003                         if (ins->dreg != AMD64_RAX)
6004                                 amd64_mov_reg_reg (code, ins->dreg, AMD64_RAX, size);
6005                         break;
6006                 }
6007                 case OP_ATOMIC_LOAD_I1: {
6008                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, FALSE);
6009                         break;
6010                 }
6011                 case OP_ATOMIC_LOAD_U1: {
6012                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, FALSE);
6013                         break;
6014                 }
6015                 case OP_ATOMIC_LOAD_I2: {
6016                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, TRUE, TRUE);
6017                         break;
6018                 }
6019                 case OP_ATOMIC_LOAD_U2: {
6020                         amd64_widen_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, FALSE, TRUE);
6021                         break;
6022                 }
6023                 case OP_ATOMIC_LOAD_I4: {
6024                         amd64_movsxd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
6025                         break;
6026                 }
6027                 case OP_ATOMIC_LOAD_U4:
6028                 case OP_ATOMIC_LOAD_I8:
6029                 case OP_ATOMIC_LOAD_U8: {
6030                         amd64_mov_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset, ins->opcode == OP_ATOMIC_LOAD_U4 ? 4 : 8);
6031                         break;
6032                 }
6033                 case OP_ATOMIC_LOAD_R4: {
6034                         amd64_sse_movss_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
6035                         amd64_sse_cvtss2sd_reg_reg (code, ins->dreg, ins->dreg);
6036                         break;
6037                 }
6038                 case OP_ATOMIC_LOAD_R8: {
6039                         amd64_sse_movsd_reg_membase (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
6040                         break;
6041                 }
6042                 case OP_ATOMIC_STORE_I1:
6043                 case OP_ATOMIC_STORE_U1:
6044                 case OP_ATOMIC_STORE_I2:
6045                 case OP_ATOMIC_STORE_U2:
6046                 case OP_ATOMIC_STORE_I4:
6047                 case OP_ATOMIC_STORE_U4:
6048                 case OP_ATOMIC_STORE_I8:
6049                 case OP_ATOMIC_STORE_U8: {
6050                         int size;
6051
6052                         switch (ins->opcode) {
6053                         case OP_ATOMIC_STORE_I1:
6054                         case OP_ATOMIC_STORE_U1:
6055                                 size = 1;
6056                                 break;
6057                         case OP_ATOMIC_STORE_I2:
6058                         case OP_ATOMIC_STORE_U2:
6059                                 size = 2;
6060                                 break;
6061                         case OP_ATOMIC_STORE_I4:
6062                         case OP_ATOMIC_STORE_U4:
6063                                 size = 4;
6064                                 break;
6065                         case OP_ATOMIC_STORE_I8:
6066                         case OP_ATOMIC_STORE_U8:
6067                                 size = 8;
6068                                 break;
6069                         }
6070
6071                         amd64_mov_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1, size);
6072
6073                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6074                                 x86_mfence (code);
6075                         break;
6076                 }
6077                 case OP_ATOMIC_STORE_R4: {
6078                         amd64_sse_cvtsd2ss_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6079                         amd64_sse_movss_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, MONO_ARCH_FP_SCRATCH_REG);
6080
6081                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6082                                 x86_mfence (code);
6083                         break;
6084                 }
6085                 case OP_ATOMIC_STORE_R8: {
6086                         x86_nop (code);
6087                         x86_nop (code);
6088                         amd64_sse_movsd_membase_reg (code, ins->inst_destbasereg, ins->inst_offset, ins->sreg1);
6089                         x86_nop (code);
6090                         x86_nop (code);
6091
6092                         if (ins->backend.memory_barrier_kind == MONO_MEMORY_BARRIER_SEQ)
6093                                 x86_mfence (code);
6094                         break;
6095                 }
6096                 case OP_CARD_TABLE_WBARRIER: {
6097                         int ptr = ins->sreg1;
6098                         int value = ins->sreg2;
6099                         guchar *br = 0;
6100                         int nursery_shift, card_table_shift;
6101                         gpointer card_table_mask;
6102                         size_t nursery_size;
6103
6104                         gpointer card_table = mono_gc_get_card_table (&card_table_shift, &card_table_mask);
6105                         guint64 nursery_start = (guint64)mono_gc_get_nursery (&nursery_shift, &nursery_size);
6106                         guint64 shifted_nursery_start = nursery_start >> nursery_shift;
6107
6108                         /*If either point to the stack we can simply avoid the WB. This happens due to
6109                          * optimizations revealing a stack store that was not visible when op_cardtable was emited.
6110                          */
6111                         if (ins->sreg1 == AMD64_RSP || ins->sreg2 == AMD64_RSP)
6112                                 continue;
6113
6114                         /*
6115                          * We need one register we can clobber, we choose EDX and make sreg1
6116                          * fixed EAX to work around limitations in the local register allocator.
6117                          * sreg2 might get allocated to EDX, but that is not a problem since
6118                          * we use it before clobbering EDX.
6119                          */
6120                         g_assert (ins->sreg1 == AMD64_RAX);
6121
6122                         /*
6123                          * This is the code we produce:
6124                          *
6125                          *   edx = value
6126                          *   edx >>= nursery_shift
6127                          *   cmp edx, (nursery_start >> nursery_shift)
6128                          *   jne done
6129                          *   edx = ptr
6130                          *   edx >>= card_table_shift
6131                          *   edx += cardtable
6132                          *   [edx] = 1
6133                          * done:
6134                          */
6135
6136                         if (mono_gc_card_table_nursery_check ()) {
6137                                 if (value != AMD64_RDX)
6138                                         amd64_mov_reg_reg (code, AMD64_RDX, value, 8);
6139                                 amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, nursery_shift);
6140                                 if (shifted_nursery_start >> 31) {
6141                                         /*
6142                                          * The value we need to compare against is 64 bits, so we need
6143                                          * another spare register.  We use RBX, which we save and
6144                                          * restore.
6145                                          */
6146                                         amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RBX, 8);
6147                                         amd64_mov_reg_imm (code, AMD64_RBX, shifted_nursery_start);
6148                                         amd64_alu_reg_reg (code, X86_CMP, AMD64_RDX, AMD64_RBX);
6149                                         amd64_mov_reg_membase (code, AMD64_RBX, AMD64_RSP, -8, 8);
6150                                 } else {
6151                                         amd64_alu_reg_imm (code, X86_CMP, AMD64_RDX, shifted_nursery_start);
6152                                 }
6153                                 br = code; x86_branch8 (code, X86_CC_NE, -1, FALSE);
6154                         }
6155                         amd64_mov_reg_reg (code, AMD64_RDX, ptr, 8);
6156                         amd64_shift_reg_imm (code, X86_SHR, AMD64_RDX, card_table_shift);
6157                         if (card_table_mask)
6158                                 amd64_alu_reg_imm (code, X86_AND, AMD64_RDX, (guint32)(guint64)card_table_mask);
6159
6160                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_GC_CARD_TABLE_ADDR, card_table);
6161                         amd64_alu_reg_membase (code, X86_ADD, AMD64_RDX, AMD64_RIP, 0);
6162
6163                         amd64_mov_membase_imm (code, AMD64_RDX, 0, 1, 1);
6164
6165                         if (mono_gc_card_table_nursery_check ())
6166                                 x86_patch (br, code);
6167                         break;
6168                 }
6169 #ifdef MONO_ARCH_SIMD_INTRINSICS
6170                 /* TODO: Some of these IR opcodes are marked as no clobber when they indeed do. */
6171                 case OP_ADDPS:
6172                         amd64_sse_addps_reg_reg (code, ins->sreg1, ins->sreg2);
6173                         break;
6174                 case OP_DIVPS:
6175                         amd64_sse_divps_reg_reg (code, ins->sreg1, ins->sreg2);
6176                         break;
6177                 case OP_MULPS:
6178                         amd64_sse_mulps_reg_reg (code, ins->sreg1, ins->sreg2);
6179                         break;
6180                 case OP_SUBPS:
6181                         amd64_sse_subps_reg_reg (code, ins->sreg1, ins->sreg2);
6182                         break;
6183                 case OP_MAXPS:
6184                         amd64_sse_maxps_reg_reg (code, ins->sreg1, ins->sreg2);
6185                         break;
6186                 case OP_MINPS:
6187                         amd64_sse_minps_reg_reg (code, ins->sreg1, ins->sreg2);
6188                         break;
6189                 case OP_COMPPS:
6190                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6191                         amd64_sse_cmpps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6192                         break;
6193                 case OP_ANDPS:
6194                         amd64_sse_andps_reg_reg (code, ins->sreg1, ins->sreg2);
6195                         break;
6196                 case OP_ANDNPS:
6197                         amd64_sse_andnps_reg_reg (code, ins->sreg1, ins->sreg2);
6198                         break;
6199                 case OP_ORPS:
6200                         amd64_sse_orps_reg_reg (code, ins->sreg1, ins->sreg2);
6201                         break;
6202                 case OP_XORPS:
6203                         amd64_sse_xorps_reg_reg (code, ins->sreg1, ins->sreg2);
6204                         break;
6205                 case OP_SQRTPS:
6206                         amd64_sse_sqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6207                         break;
6208                 case OP_RSQRTPS:
6209                         amd64_sse_rsqrtps_reg_reg (code, ins->dreg, ins->sreg1);
6210                         break;
6211                 case OP_RCPPS:
6212                         amd64_sse_rcpps_reg_reg (code, ins->dreg, ins->sreg1);
6213                         break;
6214                 case OP_ADDSUBPS:
6215                         amd64_sse_addsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6216                         break;
6217                 case OP_HADDPS:
6218                         amd64_sse_haddps_reg_reg (code, ins->sreg1, ins->sreg2);
6219                         break;
6220                 case OP_HSUBPS:
6221                         amd64_sse_hsubps_reg_reg (code, ins->sreg1, ins->sreg2);
6222                         break;
6223                 case OP_DUPPS_HIGH:
6224                         amd64_sse_movshdup_reg_reg (code, ins->dreg, ins->sreg1);
6225                         break;
6226                 case OP_DUPPS_LOW:
6227                         amd64_sse_movsldup_reg_reg (code, ins->dreg, ins->sreg1);
6228                         break;
6229
6230                 case OP_PSHUFLEW_HIGH:
6231                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6232                         amd64_sse_pshufhw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6233                         break;
6234                 case OP_PSHUFLEW_LOW:
6235                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6236                         amd64_sse_pshuflw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6237                         break;
6238                 case OP_PSHUFLED:
6239                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6240                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6241                         break;
6242                 case OP_SHUFPS:
6243                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0xFF);
6244                         amd64_sse_shufps_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6245                         break;
6246                 case OP_SHUFPD:
6247                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 0x3);
6248                         amd64_sse_shufpd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6249                         break;
6250
6251                 case OP_ADDPD:
6252                         amd64_sse_addpd_reg_reg (code, ins->sreg1, ins->sreg2);
6253                         break;
6254                 case OP_DIVPD:
6255                         amd64_sse_divpd_reg_reg (code, ins->sreg1, ins->sreg2);
6256                         break;
6257                 case OP_MULPD:
6258                         amd64_sse_mulpd_reg_reg (code, ins->sreg1, ins->sreg2);
6259                         break;
6260                 case OP_SUBPD:
6261                         amd64_sse_subpd_reg_reg (code, ins->sreg1, ins->sreg2);
6262                         break;
6263                 case OP_MAXPD:
6264                         amd64_sse_maxpd_reg_reg (code, ins->sreg1, ins->sreg2);
6265                         break;
6266                 case OP_MINPD:
6267                         amd64_sse_minpd_reg_reg (code, ins->sreg1, ins->sreg2);
6268                         break;
6269                 case OP_COMPPD:
6270                         g_assert (ins->inst_c0 >= 0 && ins->inst_c0 <= 7);
6271                         amd64_sse_cmppd_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6272                         break;
6273                 case OP_ANDPD:
6274                         amd64_sse_andpd_reg_reg (code, ins->sreg1, ins->sreg2);
6275                         break;
6276                 case OP_ANDNPD:
6277                         amd64_sse_andnpd_reg_reg (code, ins->sreg1, ins->sreg2);
6278                         break;
6279                 case OP_ORPD:
6280                         amd64_sse_orpd_reg_reg (code, ins->sreg1, ins->sreg2);
6281                         break;
6282                 case OP_XORPD:
6283                         amd64_sse_xorpd_reg_reg (code, ins->sreg1, ins->sreg2);
6284                         break;
6285                 case OP_SQRTPD:
6286                         amd64_sse_sqrtpd_reg_reg (code, ins->dreg, ins->sreg1);
6287                         break;
6288                 case OP_ADDSUBPD:
6289                         amd64_sse_addsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6290                         break;
6291                 case OP_HADDPD:
6292                         amd64_sse_haddpd_reg_reg (code, ins->sreg1, ins->sreg2);
6293                         break;
6294                 case OP_HSUBPD:
6295                         amd64_sse_hsubpd_reg_reg (code, ins->sreg1, ins->sreg2);
6296                         break;
6297                 case OP_DUPPD:
6298                         amd64_sse_movddup_reg_reg (code, ins->dreg, ins->sreg1);
6299                         break;
6300
6301                 case OP_EXTRACT_MASK:
6302                         amd64_sse_pmovmskb_reg_reg (code, ins->dreg, ins->sreg1);
6303                         break;
6304
6305                 case OP_PAND:
6306                         amd64_sse_pand_reg_reg (code, ins->sreg1, ins->sreg2);
6307                         break;
6308                 case OP_POR:
6309                         amd64_sse_por_reg_reg (code, ins->sreg1, ins->sreg2);
6310                         break;
6311                 case OP_PXOR:
6312                         amd64_sse_pxor_reg_reg (code, ins->sreg1, ins->sreg2);
6313                         break;
6314
6315                 case OP_PADDB:
6316                         amd64_sse_paddb_reg_reg (code, ins->sreg1, ins->sreg2);
6317                         break;
6318                 case OP_PADDW:
6319                         amd64_sse_paddw_reg_reg (code, ins->sreg1, ins->sreg2);
6320                         break;
6321                 case OP_PADDD:
6322                         amd64_sse_paddd_reg_reg (code, ins->sreg1, ins->sreg2);
6323                         break;
6324                 case OP_PADDQ:
6325                         amd64_sse_paddq_reg_reg (code, ins->sreg1, ins->sreg2);
6326                         break;
6327
6328                 case OP_PSUBB:
6329                         amd64_sse_psubb_reg_reg (code, ins->sreg1, ins->sreg2);
6330                         break;
6331                 case OP_PSUBW:
6332                         amd64_sse_psubw_reg_reg (code, ins->sreg1, ins->sreg2);
6333                         break;
6334                 case OP_PSUBD:
6335                         amd64_sse_psubd_reg_reg (code, ins->sreg1, ins->sreg2);
6336                         break;
6337                 case OP_PSUBQ:
6338                         amd64_sse_psubq_reg_reg (code, ins->sreg1, ins->sreg2);
6339                         break;
6340
6341                 case OP_PMAXB_UN:
6342                         amd64_sse_pmaxub_reg_reg (code, ins->sreg1, ins->sreg2);
6343                         break;
6344                 case OP_PMAXW_UN:
6345                         amd64_sse_pmaxuw_reg_reg (code, ins->sreg1, ins->sreg2);
6346                         break;
6347                 case OP_PMAXD_UN:
6348                         amd64_sse_pmaxud_reg_reg (code, ins->sreg1, ins->sreg2);
6349                         break;
6350
6351                 case OP_PMAXB:
6352                         amd64_sse_pmaxsb_reg_reg (code, ins->sreg1, ins->sreg2);
6353                         break;
6354                 case OP_PMAXW:
6355                         amd64_sse_pmaxsw_reg_reg (code, ins->sreg1, ins->sreg2);
6356                         break;
6357                 case OP_PMAXD:
6358                         amd64_sse_pmaxsd_reg_reg (code, ins->sreg1, ins->sreg2);
6359                         break;
6360
6361                 case OP_PAVGB_UN:
6362                         amd64_sse_pavgb_reg_reg (code, ins->sreg1, ins->sreg2);
6363                         break;
6364                 case OP_PAVGW_UN:
6365                         amd64_sse_pavgw_reg_reg (code, ins->sreg1, ins->sreg2);
6366                         break;
6367
6368                 case OP_PMINB_UN:
6369                         amd64_sse_pminub_reg_reg (code, ins->sreg1, ins->sreg2);
6370                         break;
6371                 case OP_PMINW_UN:
6372                         amd64_sse_pminuw_reg_reg (code, ins->sreg1, ins->sreg2);
6373                         break;
6374                 case OP_PMIND_UN:
6375                         amd64_sse_pminud_reg_reg (code, ins->sreg1, ins->sreg2);
6376                         break;
6377
6378                 case OP_PMINB:
6379                         amd64_sse_pminsb_reg_reg (code, ins->sreg1, ins->sreg2);
6380                         break;
6381                 case OP_PMINW:
6382                         amd64_sse_pminsw_reg_reg (code, ins->sreg1, ins->sreg2);
6383                         break;
6384                 case OP_PMIND:
6385                         amd64_sse_pminsd_reg_reg (code, ins->sreg1, ins->sreg2);
6386                         break;
6387
6388                 case OP_PCMPEQB:
6389                         amd64_sse_pcmpeqb_reg_reg (code, ins->sreg1, ins->sreg2);
6390                         break;
6391                 case OP_PCMPEQW:
6392                         amd64_sse_pcmpeqw_reg_reg (code, ins->sreg1, ins->sreg2);
6393                         break;
6394                 case OP_PCMPEQD:
6395                         amd64_sse_pcmpeqd_reg_reg (code, ins->sreg1, ins->sreg2);
6396                         break;
6397                 case OP_PCMPEQQ:
6398                         amd64_sse_pcmpeqq_reg_reg (code, ins->sreg1, ins->sreg2);
6399                         break;
6400
6401                 case OP_PCMPGTB:
6402                         amd64_sse_pcmpgtb_reg_reg (code, ins->sreg1, ins->sreg2);
6403                         break;
6404                 case OP_PCMPGTW:
6405                         amd64_sse_pcmpgtw_reg_reg (code, ins->sreg1, ins->sreg2);
6406                         break;
6407                 case OP_PCMPGTD:
6408                         amd64_sse_pcmpgtd_reg_reg (code, ins->sreg1, ins->sreg2);
6409                         break;
6410                 case OP_PCMPGTQ:
6411                         amd64_sse_pcmpgtq_reg_reg (code, ins->sreg1, ins->sreg2);
6412                         break;
6413
6414                 case OP_PSUM_ABS_DIFF:
6415                         amd64_sse_psadbw_reg_reg (code, ins->sreg1, ins->sreg2);
6416                         break;
6417
6418                 case OP_UNPACK_LOWB:
6419                         amd64_sse_punpcklbw_reg_reg (code, ins->sreg1, ins->sreg2);
6420                         break;
6421                 case OP_UNPACK_LOWW:
6422                         amd64_sse_punpcklwd_reg_reg (code, ins->sreg1, ins->sreg2);
6423                         break;
6424                 case OP_UNPACK_LOWD:
6425                         amd64_sse_punpckldq_reg_reg (code, ins->sreg1, ins->sreg2);
6426                         break;
6427                 case OP_UNPACK_LOWQ:
6428                         amd64_sse_punpcklqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6429                         break;
6430                 case OP_UNPACK_LOWPS:
6431                         amd64_sse_unpcklps_reg_reg (code, ins->sreg1, ins->sreg2);
6432                         break;
6433                 case OP_UNPACK_LOWPD:
6434                         amd64_sse_unpcklpd_reg_reg (code, ins->sreg1, ins->sreg2);
6435                         break;
6436
6437                 case OP_UNPACK_HIGHB:
6438                         amd64_sse_punpckhbw_reg_reg (code, ins->sreg1, ins->sreg2);
6439                         break;
6440                 case OP_UNPACK_HIGHW:
6441                         amd64_sse_punpckhwd_reg_reg (code, ins->sreg1, ins->sreg2);
6442                         break;
6443                 case OP_UNPACK_HIGHD:
6444                         amd64_sse_punpckhdq_reg_reg (code, ins->sreg1, ins->sreg2);
6445                         break;
6446                 case OP_UNPACK_HIGHQ:
6447                         amd64_sse_punpckhqdq_reg_reg (code, ins->sreg1, ins->sreg2);
6448                         break;
6449                 case OP_UNPACK_HIGHPS:
6450                         amd64_sse_unpckhps_reg_reg (code, ins->sreg1, ins->sreg2);
6451                         break;
6452                 case OP_UNPACK_HIGHPD:
6453                         amd64_sse_unpckhpd_reg_reg (code, ins->sreg1, ins->sreg2);
6454                         break;
6455
6456                 case OP_PACKW:
6457                         amd64_sse_packsswb_reg_reg (code, ins->sreg1, ins->sreg2);
6458                         break;
6459                 case OP_PACKD:
6460                         amd64_sse_packssdw_reg_reg (code, ins->sreg1, ins->sreg2);
6461                         break;
6462                 case OP_PACKW_UN:
6463                         amd64_sse_packuswb_reg_reg (code, ins->sreg1, ins->sreg2);
6464                         break;
6465                 case OP_PACKD_UN:
6466                         amd64_sse_packusdw_reg_reg (code, ins->sreg1, ins->sreg2);
6467                         break;
6468
6469                 case OP_PADDB_SAT_UN:
6470                         amd64_sse_paddusb_reg_reg (code, ins->sreg1, ins->sreg2);
6471                         break;
6472                 case OP_PSUBB_SAT_UN:
6473                         amd64_sse_psubusb_reg_reg (code, ins->sreg1, ins->sreg2);
6474                         break;
6475                 case OP_PADDW_SAT_UN:
6476                         amd64_sse_paddusw_reg_reg (code, ins->sreg1, ins->sreg2);
6477                         break;
6478                 case OP_PSUBW_SAT_UN:
6479                         amd64_sse_psubusw_reg_reg (code, ins->sreg1, ins->sreg2);
6480                         break;
6481
6482                 case OP_PADDB_SAT:
6483                         amd64_sse_paddsb_reg_reg (code, ins->sreg1, ins->sreg2);
6484                         break;
6485                 case OP_PSUBB_SAT:
6486                         amd64_sse_psubsb_reg_reg (code, ins->sreg1, ins->sreg2);
6487                         break;
6488                 case OP_PADDW_SAT:
6489                         amd64_sse_paddsw_reg_reg (code, ins->sreg1, ins->sreg2);
6490                         break;
6491                 case OP_PSUBW_SAT:
6492                         amd64_sse_psubsw_reg_reg (code, ins->sreg1, ins->sreg2);
6493                         break;
6494
6495                 case OP_PMULW:
6496                         amd64_sse_pmullw_reg_reg (code, ins->sreg1, ins->sreg2);
6497                         break;
6498                 case OP_PMULD:
6499                         amd64_sse_pmulld_reg_reg (code, ins->sreg1, ins->sreg2);
6500                         break;
6501                 case OP_PMULQ:
6502                         amd64_sse_pmuludq_reg_reg (code, ins->sreg1, ins->sreg2);
6503                         break;
6504                 case OP_PMULW_HIGH_UN:
6505                         amd64_sse_pmulhuw_reg_reg (code, ins->sreg1, ins->sreg2);
6506                         break;
6507                 case OP_PMULW_HIGH:
6508                         amd64_sse_pmulhw_reg_reg (code, ins->sreg1, ins->sreg2);
6509                         break;
6510
6511                 case OP_PSHRW:
6512                         amd64_sse_psrlw_reg_imm (code, ins->dreg, ins->inst_imm);
6513                         break;
6514                 case OP_PSHRW_REG:
6515                         amd64_sse_psrlw_reg_reg (code, ins->dreg, ins->sreg2);
6516                         break;
6517
6518                 case OP_PSARW:
6519                         amd64_sse_psraw_reg_imm (code, ins->dreg, ins->inst_imm);
6520                         break;
6521                 case OP_PSARW_REG:
6522                         amd64_sse_psraw_reg_reg (code, ins->dreg, ins->sreg2);
6523                         break;
6524
6525                 case OP_PSHLW:
6526                         amd64_sse_psllw_reg_imm (code, ins->dreg, ins->inst_imm);
6527                         break;
6528                 case OP_PSHLW_REG:
6529                         amd64_sse_psllw_reg_reg (code, ins->dreg, ins->sreg2);
6530                         break;
6531
6532                 case OP_PSHRD:
6533                         amd64_sse_psrld_reg_imm (code, ins->dreg, ins->inst_imm);
6534                         break;
6535                 case OP_PSHRD_REG:
6536                         amd64_sse_psrld_reg_reg (code, ins->dreg, ins->sreg2);
6537                         break;
6538
6539                 case OP_PSARD:
6540                         amd64_sse_psrad_reg_imm (code, ins->dreg, ins->inst_imm);
6541                         break;
6542                 case OP_PSARD_REG:
6543                         amd64_sse_psrad_reg_reg (code, ins->dreg, ins->sreg2);
6544                         break;
6545
6546                 case OP_PSHLD:
6547                         amd64_sse_pslld_reg_imm (code, ins->dreg, ins->inst_imm);
6548                         break;
6549                 case OP_PSHLD_REG:
6550                         amd64_sse_pslld_reg_reg (code, ins->dreg, ins->sreg2);
6551                         break;
6552
6553                 case OP_PSHRQ:
6554                         amd64_sse_psrlq_reg_imm (code, ins->dreg, ins->inst_imm);
6555                         break;
6556                 case OP_PSHRQ_REG:
6557                         amd64_sse_psrlq_reg_reg (code, ins->dreg, ins->sreg2);
6558                         break;
6559
6560                 /*TODO: This is appart of the sse spec but not added
6561                 case OP_PSARQ:
6562                         amd64_sse_psraq_reg_imm (code, ins->dreg, ins->inst_imm);
6563                         break;
6564                 case OP_PSARQ_REG:
6565                         amd64_sse_psraq_reg_reg (code, ins->dreg, ins->sreg2);
6566                         break;
6567                 */
6568
6569                 case OP_PSHLQ:
6570                         amd64_sse_psllq_reg_imm (code, ins->dreg, ins->inst_imm);
6571                         break;
6572                 case OP_PSHLQ_REG:
6573                         amd64_sse_psllq_reg_reg (code, ins->dreg, ins->sreg2);
6574                         break;
6575                 case OP_CVTDQ2PD:
6576                         amd64_sse_cvtdq2pd_reg_reg (code, ins->dreg, ins->sreg1);
6577                         break;
6578                 case OP_CVTDQ2PS:
6579                         amd64_sse_cvtdq2ps_reg_reg (code, ins->dreg, ins->sreg1);
6580                         break;
6581                 case OP_CVTPD2DQ:
6582                         amd64_sse_cvtpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6583                         break;
6584                 case OP_CVTPD2PS:
6585                         amd64_sse_cvtpd2ps_reg_reg (code, ins->dreg, ins->sreg1);
6586                         break;
6587                 case OP_CVTPS2DQ:
6588                         amd64_sse_cvtps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6589                         break;
6590                 case OP_CVTPS2PD:
6591                         amd64_sse_cvtps2pd_reg_reg (code, ins->dreg, ins->sreg1);
6592                         break;
6593                 case OP_CVTTPD2DQ:
6594                         amd64_sse_cvttpd2dq_reg_reg (code, ins->dreg, ins->sreg1);
6595                         break;
6596                 case OP_CVTTPS2DQ:
6597                         amd64_sse_cvttps2dq_reg_reg (code, ins->dreg, ins->sreg1);
6598                         break;
6599
6600                 case OP_ICONV_TO_X:
6601                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6602                         break;
6603                 case OP_EXTRACT_I4:
6604                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6605                         break;
6606                 case OP_EXTRACT_I8:
6607                         if (ins->inst_c0) {
6608                                 amd64_movhlps_reg_reg (code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg1);
6609                                 amd64_movd_reg_xreg_size (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG, 8);
6610                         } else {
6611                                 amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 8);
6612                         }
6613                         break;
6614                 case OP_EXTRACT_I1:
6615                 case OP_EXTRACT_U1:
6616                         amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6617                         if (ins->inst_c0)
6618                                 amd64_shift_reg_imm (code, X86_SHR, ins->dreg, ins->inst_c0 * 8);
6619                         amd64_widen_reg (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I1, FALSE);
6620                         break;
6621                 case OP_EXTRACT_I2:
6622                 case OP_EXTRACT_U2:
6623                         /*amd64_movd_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6624                         if (ins->inst_c0)
6625                                 amd64_shift_reg_imm_size (code, X86_SHR, ins->dreg, 16, 4);*/
6626                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6627                         amd64_widen_reg_size (code, ins->dreg, ins->dreg, ins->opcode == OP_EXTRACT_I2, TRUE, 4);
6628                         break;
6629                 case OP_EXTRACT_R8:
6630                         if (ins->inst_c0)
6631                                 amd64_movhlps_reg_reg (code, ins->dreg, ins->sreg1);
6632                         else
6633                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6634                         break;
6635                 case OP_INSERT_I2:
6636                         amd64_sse_pinsrw_reg_reg_imm (code, ins->sreg1, ins->sreg2, ins->inst_c0);
6637                         break;
6638                 case OP_EXTRACTX_U2:
6639                         amd64_sse_pextrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0);
6640                         break;
6641                 case OP_INSERTX_U1_SLOW:
6642                         /*sreg1 is the extracted ireg (scratch)
6643                         /sreg2 is the to be inserted ireg (scratch)
6644                         /dreg is the xreg to receive the value*/
6645
6646                         /*clear the bits from the extracted word*/
6647                         amd64_alu_reg_imm (code, X86_AND, ins->sreg1, ins->inst_c0 & 1 ? 0x00FF : 0xFF00);
6648                         /*shift the value to insert if needed*/
6649                         if (ins->inst_c0 & 1)
6650                                 amd64_shift_reg_imm_size (code, X86_SHL, ins->sreg2, 8, 4);
6651                         /*join them together*/
6652                         amd64_alu_reg_reg (code, X86_OR, ins->sreg1, ins->sreg2);
6653                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, ins->inst_c0 / 2);
6654                         break;
6655                 case OP_INSERTX_I4_SLOW:
6656                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2);
6657                         amd64_shift_reg_imm (code, X86_SHR, ins->sreg2, 16);
6658                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg2, ins->inst_c0 * 2 + 1);
6659                         break;
6660                 case OP_INSERTX_I8_SLOW:
6661                         amd64_movd_xreg_reg_size(code, MONO_ARCH_FP_SCRATCH_REG, ins->sreg2, 8);
6662                         if (ins->inst_c0)
6663                                 amd64_movlhps_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6664                         else
6665                                 amd64_sse_movsd_reg_reg (code, ins->dreg, MONO_ARCH_FP_SCRATCH_REG);
6666                         break;
6667
6668                 case OP_INSERTX_R4_SLOW:
6669                         switch (ins->inst_c0) {
6670                         case 0:
6671                                 if (cfg->r4fp)
6672                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6673                                 else
6674                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6675                                 break;
6676                         case 1:
6677                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6678                                 if (cfg->r4fp)
6679                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6680                                 else
6681                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6682                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(1, 0, 2, 3));
6683                                 break;
6684                         case 2:
6685                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6686                                 if (cfg->r4fp)
6687                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6688                                 else
6689                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6690                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(2, 1, 0, 3));
6691                                 break;
6692                         case 3:
6693                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6694                                 if (cfg->r4fp)
6695                                         amd64_sse_movss_reg_reg (code, ins->dreg, ins->sreg2);
6696                                 else
6697                                         amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->sreg2);
6698                                 amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, mono_simd_shuffle_mask(3, 1, 2, 0));
6699                                 break;
6700                         }
6701                         break;
6702                 case OP_INSERTX_R8_SLOW:
6703                         if (ins->inst_c0)
6704                                 amd64_movlhps_reg_reg (code, ins->dreg, ins->sreg2);
6705                         else
6706                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg2);
6707                         break;
6708                 case OP_STOREX_MEMBASE_REG:
6709                 case OP_STOREX_MEMBASE:
6710                         amd64_sse_movups_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6711                         break;
6712                 case OP_LOADX_MEMBASE:
6713                         amd64_sse_movups_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6714                         break;
6715                 case OP_LOADX_ALIGNED_MEMBASE:
6716                         amd64_sse_movaps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6717                         break;
6718                 case OP_STOREX_ALIGNED_MEMBASE_REG:
6719                         amd64_sse_movaps_membase_reg (code, ins->dreg, ins->inst_offset, ins->sreg1);
6720                         break;
6721                 case OP_STOREX_NTA_MEMBASE_REG:
6722                         amd64_sse_movntps_reg_membase (code, ins->dreg, ins->sreg1, ins->inst_offset);
6723                         break;
6724                 case OP_PREFETCH_MEMBASE:
6725                         amd64_sse_prefetch_reg_membase (code, ins->backend.arg_info, ins->sreg1, ins->inst_offset);
6726                         break;
6727
6728                 case OP_XMOVE:
6729                         /*FIXME the peephole pass should have killed this*/
6730                         if (ins->dreg != ins->sreg1)
6731                                 amd64_sse_movaps_reg_reg (code, ins->dreg, ins->sreg1);
6732                         break;
6733                 case OP_XZERO:
6734                         amd64_sse_pxor_reg_reg (code, ins->dreg, ins->dreg);
6735                         break;
6736                 case OP_ICONV_TO_R4_RAW:
6737                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6738                         break;
6739
6740                 case OP_FCONV_TO_R8_X:
6741                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6742                         break;
6743
6744                 case OP_XCONV_R8_TO_I4:
6745                         amd64_sse_cvttsd2si_reg_xreg_size (code, ins->dreg, ins->sreg1, 4);
6746                         switch (ins->backend.source_opcode) {
6747                         case OP_FCONV_TO_I1:
6748                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, FALSE);
6749                                 break;
6750                         case OP_FCONV_TO_U1:
6751                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
6752                                 break;
6753                         case OP_FCONV_TO_I2:
6754                                 amd64_widen_reg (code, ins->dreg, ins->dreg, TRUE, TRUE);
6755                                 break;
6756                         case OP_FCONV_TO_U2:
6757                                 amd64_widen_reg (code, ins->dreg, ins->dreg, FALSE, TRUE);
6758                                 break;
6759                         }
6760                         break;
6761
6762                 case OP_EXPAND_I2:
6763                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 0);
6764                         amd64_sse_pinsrw_reg_reg_imm (code, ins->dreg, ins->sreg1, 1);
6765                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6766                         break;
6767                 case OP_EXPAND_I4:
6768                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 4);
6769                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6770                         break;
6771                 case OP_EXPAND_I8:
6772                         amd64_movd_xreg_reg_size (code, ins->dreg, ins->sreg1, 8);
6773                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6774                         break;
6775                 case OP_EXPAND_R4:
6776                         if (cfg->r4fp) {
6777                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6778                         } else {
6779                                 amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6780                                 amd64_sse_cvtsd2ss_reg_reg (code, ins->dreg, ins->dreg);
6781                         }
6782                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0);
6783                         break;
6784                 case OP_EXPAND_R8:
6785                         amd64_sse_movsd_reg_reg (code, ins->dreg, ins->sreg1);
6786                         amd64_sse_pshufd_reg_reg_imm (code, ins->dreg, ins->dreg, 0x44);
6787                         break;
6788 #endif
6789                 case OP_LIVERANGE_START: {
6790                         if (cfg->verbose_level > 1)
6791                                 printf ("R%d START=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6792                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_start = code - cfg->native_code;
6793                         break;
6794                 }
6795                 case OP_LIVERANGE_END: {
6796                         if (cfg->verbose_level > 1)
6797                                 printf ("R%d END=0x%x\n", MONO_VARINFO (cfg, ins->inst_c0)->vreg, (int)(code - cfg->native_code));
6798                         MONO_VARINFO (cfg, ins->inst_c0)->live_range_end = code - cfg->native_code;
6799                         break;
6800                 }
6801                 case OP_GC_SAFE_POINT: {
6802                         const char *polling_func = NULL;
6803                         int compare_val = 0;
6804                         guint8 *br [1];
6805
6806 #if defined(__native_client_codegen__) && defined(__native_client_gc__)
6807                         polling_func = "mono_nacl_gc";
6808                         compare_val = 0xFFFFFFFF;
6809 #else
6810                         g_assert (mono_threads_is_coop_enabled ());
6811                         polling_func = "mono_threads_state_poll";
6812                         compare_val = 1;
6813 #endif
6814
6815                         amd64_test_membase_imm_size (code, ins->sreg1, 0, compare_val, 4);
6816                         br[0] = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
6817                         code = emit_call (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, polling_func, FALSE);
6818                         amd64_patch (br[0], code);
6819                         break;
6820                 }
6821
6822                 case OP_GC_LIVENESS_DEF:
6823                 case OP_GC_LIVENESS_USE:
6824                 case OP_GC_PARAM_SLOT_LIVENESS_DEF:
6825                         ins->backend.pc_offset = code - cfg->native_code;
6826                         break;
6827                 case OP_GC_SPILL_SLOT_LIVENESS_DEF:
6828                         ins->backend.pc_offset = code - cfg->native_code;
6829                         bb->spill_slot_defs = g_slist_prepend_mempool (cfg->mempool, bb->spill_slot_defs, ins);
6830                         break;
6831                 default:
6832                         g_warning ("unknown opcode %s in %s()\n", mono_inst_name (ins->opcode), __FUNCTION__);
6833                         g_assert_not_reached ();
6834                 }
6835
6836                 if ((code - cfg->native_code - offset) > max_len) {
6837 #if !defined(__native_client_codegen__)
6838                         g_warning ("wrong maximal instruction length of instruction %s (expected %d, got %ld)",
6839                                    mono_inst_name (ins->opcode), max_len, code - cfg->native_code - offset);
6840                         g_assert_not_reached ();
6841 #endif
6842                 }
6843         }
6844
6845         cfg->code_len = code - cfg->native_code;
6846 }
6847
6848 #endif /* DISABLE_JIT */
6849
6850 void
6851 mono_arch_register_lowlevel_calls (void)
6852 {
6853         /* The signature doesn't matter */
6854         mono_register_jit_icall (mono_amd64_throw_exception, "mono_amd64_throw_exception", mono_create_icall_signature ("void"), TRUE);
6855 }
6856
6857 void
6858 mono_arch_patch_code_new (MonoCompile *cfg, MonoDomain *domain, guint8 *code, MonoJumpInfo *ji, gpointer target)
6859 {
6860         unsigned char *ip = ji->ip.i + code;
6861
6862         /*
6863          * Debug code to help track down problems where the target of a near call is
6864          * is not valid.
6865          */
6866         if (amd64_is_near_call (ip)) {
6867                 gint64 disp = (guint8*)target - (guint8*)ip;
6868
6869                 if (!amd64_is_imm32 (disp)) {
6870                         printf ("TYPE: %d\n", ji->type);
6871                         switch (ji->type) {
6872                         case MONO_PATCH_INFO_INTERNAL_METHOD:
6873                                 printf ("V: %s\n", ji->data.name);
6874                                 break;
6875                         case MONO_PATCH_INFO_METHOD_JUMP:
6876                         case MONO_PATCH_INFO_METHOD:
6877                                 printf ("V: %s\n", ji->data.method->name);
6878                                 break;
6879                         default:
6880                                 break;
6881                         }
6882                 }
6883         }
6884
6885         amd64_patch (ip, (gpointer)target);
6886 }
6887
6888 #ifndef DISABLE_JIT
6889
6890 static int
6891 get_max_epilog_size (MonoCompile *cfg)
6892 {
6893         int max_epilog_size = 16;
6894
6895         if (cfg->method->save_lmf)
6896                 max_epilog_size += 256;
6897
6898         if (mono_jit_trace_calls != NULL)
6899                 max_epilog_size += 50;
6900
6901         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
6902                 max_epilog_size += 50;
6903
6904         max_epilog_size += (AMD64_NREG * 2);
6905
6906         return max_epilog_size;
6907 }
6908
6909 /*
6910  * This macro is used for testing whenever the unwinder works correctly at every point
6911  * where an async exception can happen.
6912  */
6913 /* This will generate a SIGSEGV at the given point in the code */
6914 #define async_exc_point(code) do { \
6915     if (mono_inject_async_exc_method && mono_method_desc_full_match (mono_inject_async_exc_method, cfg->method)) { \
6916          if (cfg->arch.async_point_count == mono_inject_async_exc_pos) \
6917              amd64_mov_reg_mem (code, AMD64_RAX, 0, 4); \
6918          cfg->arch.async_point_count ++; \
6919     } \
6920 } while (0)
6921
6922 guint8 *
6923 mono_arch_emit_prolog (MonoCompile *cfg)
6924 {
6925         MonoMethod *method = cfg->method;
6926         MonoBasicBlock *bb;
6927         MonoMethodSignature *sig;
6928         MonoInst *ins;
6929         int alloc_size, pos, i, cfa_offset, quad, max_epilog_size, save_area_offset;
6930         guint8 *code;
6931         CallInfo *cinfo;
6932         MonoInst *lmf_var = cfg->lmf_var;
6933         gboolean args_clobbered = FALSE;
6934         gboolean trace = FALSE;
6935 #ifdef __native_client_codegen__
6936         guint alignment_check;
6937 #endif
6938
6939         cfg->code_size = MAX (cfg->header->code_size * 4, 1024);
6940
6941 #if defined(__default_codegen__)
6942         code = cfg->native_code = (unsigned char *)g_malloc (cfg->code_size);
6943 #elif defined(__native_client_codegen__)
6944         /* native_code_alloc is not 32-byte aligned, native_code is. */
6945         cfg->native_code_alloc = g_malloc (cfg->code_size + kNaClAlignment);
6946
6947         /* Align native_code to next nearest kNaclAlignment byte. */
6948         cfg->native_code = (uintptr_t)cfg->native_code_alloc + kNaClAlignment;
6949         cfg->native_code = (uintptr_t)cfg->native_code & ~kNaClAlignmentMask;
6950
6951         code = cfg->native_code;
6952
6953         alignment_check = (guint)cfg->native_code & kNaClAlignmentMask;
6954         g_assert (alignment_check == 0);
6955 #endif
6956
6957         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
6958                 trace = TRUE;
6959
6960         /* Amount of stack space allocated by register saving code */
6961         pos = 0;
6962
6963         /* Offset between RSP and the CFA */
6964         cfa_offset = 0;
6965
6966         /*
6967          * The prolog consists of the following parts:
6968          * FP present:
6969          * - push rbp, mov rbp, rsp
6970          * - save callee saved regs using pushes
6971          * - allocate frame
6972          * - save rgctx if needed
6973          * - save lmf if needed
6974          * FP not present:
6975          * - allocate frame
6976          * - save rgctx if needed
6977          * - save lmf if needed
6978          * - save callee saved regs using moves
6979          */
6980
6981         // CFA = sp + 8
6982         cfa_offset = 8;
6983         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
6984         // IP saved at CFA - 8
6985         mono_emit_unwind_op_offset (cfg, code, AMD64_RIP, -cfa_offset);
6986         async_exc_point (code);
6987         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
6988
6989         if (!cfg->arch.omit_fp) {
6990                 amd64_push_reg (code, AMD64_RBP);
6991                 cfa_offset += 8;
6992                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
6993                 mono_emit_unwind_op_offset (cfg, code, AMD64_RBP, - cfa_offset);
6994                 async_exc_point (code);
6995 #ifdef TARGET_WIN32
6996                 mono_arch_unwindinfo_add_push_nonvol (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
6997 #endif
6998                 /* These are handled automatically by the stack marking code */
6999                 mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset, SLOT_NOREF);
7000
7001                 amd64_mov_reg_reg (code, AMD64_RBP, AMD64_RSP, sizeof(mgreg_t));
7002                 mono_emit_unwind_op_def_cfa_reg (cfg, code, AMD64_RBP);
7003                 async_exc_point (code);
7004 #ifdef TARGET_WIN32
7005                 mono_arch_unwindinfo_add_set_fpreg (&cfg->arch.unwindinfo, cfg->native_code, code, AMD64_RBP);
7006 #endif
7007         }
7008
7009         /* The param area is always at offset 0 from sp */
7010         /* This needs to be allocated here, since it has to come after the spill area */
7011         if (cfg->param_area) {
7012                 if (cfg->arch.omit_fp)
7013                         // FIXME:
7014                         g_assert_not_reached ();
7015                 cfg->stack_offset += ALIGN_TO (cfg->param_area, sizeof(mgreg_t));
7016         }
7017
7018         if (cfg->arch.omit_fp) {
7019                 /*
7020                  * On enter, the stack is misaligned by the pushing of the return
7021                  * address. It is either made aligned by the pushing of %rbp, or by
7022                  * this.
7023                  */
7024                 alloc_size = ALIGN_TO (cfg->stack_offset, 8);
7025                 if ((alloc_size % 16) == 0) {
7026                         alloc_size += 8;
7027                         /* Mark the padding slot as NOREF */
7028                         mini_gc_set_slot_type_from_cfa (cfg, -cfa_offset - sizeof (mgreg_t), SLOT_NOREF);
7029                 }
7030         } else {
7031                 alloc_size = ALIGN_TO (cfg->stack_offset, MONO_ARCH_FRAME_ALIGNMENT);
7032                 if (cfg->stack_offset != alloc_size) {
7033                         /* Mark the padding slot as NOREF */
7034                         mini_gc_set_slot_type_from_fp (cfg, -alloc_size + cfg->param_area, SLOT_NOREF);
7035                 }
7036                 cfg->arch.sp_fp_offset = alloc_size;
7037                 alloc_size -= pos;
7038         }
7039
7040         cfg->arch.stack_alloc_size = alloc_size;
7041
7042         /* Allocate stack frame */
7043         if (alloc_size) {
7044                 /* See mono_emit_stack_alloc */
7045 #if defined(TARGET_WIN32) || defined(MONO_ARCH_SIGSEGV_ON_ALTSTACK)
7046                 guint32 remaining_size = alloc_size;
7047                 /*FIXME handle unbounded code expansion, we should use a loop in case of more than X interactions*/
7048                 guint32 required_code_size = ((remaining_size / 0x1000) + 1) * 10; /*10 is the max size of amd64_alu_reg_imm + amd64_test_membase_reg*/
7049                 guint32 offset = code - cfg->native_code;
7050                 if (G_UNLIKELY (required_code_size >= (cfg->code_size - offset))) {
7051                         while (required_code_size >= (cfg->code_size - offset))
7052                                 cfg->code_size *= 2;
7053                         cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7054                         code = cfg->native_code + offset;
7055                         cfg->stat_code_reallocs++;
7056                 }
7057
7058                 while (remaining_size >= 0x1000) {
7059                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 0x1000);
7060                         if (cfg->arch.omit_fp) {
7061                                 cfa_offset += 0x1000;
7062                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7063                         }
7064                         async_exc_point (code);
7065 #ifdef TARGET_WIN32
7066                         if (cfg->arch.omit_fp)
7067                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, 0x1000);
7068 #endif
7069
7070                         amd64_test_membase_reg (code, AMD64_RSP, 0, AMD64_RSP);
7071                         remaining_size -= 0x1000;
7072                 }
7073                 if (remaining_size) {
7074                         amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, remaining_size);
7075                         if (cfg->arch.omit_fp) {
7076                                 cfa_offset += remaining_size;
7077                                 mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7078                                 async_exc_point (code);
7079                         }
7080 #ifdef TARGET_WIN32
7081                         if (cfg->arch.omit_fp)
7082                                 mono_arch_unwindinfo_add_alloc_stack (&cfg->arch.unwindinfo, cfg->native_code, code, remaining_size);
7083 #endif
7084                 }
7085 #else
7086                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, alloc_size);
7087                 if (cfg->arch.omit_fp) {
7088                         cfa_offset += alloc_size;
7089                         mono_emit_unwind_op_def_cfa_offset (cfg, code, cfa_offset);
7090                         async_exc_point (code);
7091                 }
7092 #endif
7093         }
7094
7095         /* Stack alignment check */
7096 #if 0
7097         {
7098                 guint8 *buf;
7099
7100                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_RSP, 8);
7101                 amd64_alu_reg_imm (code, X86_AND, AMD64_RAX, 0xf);
7102                 amd64_alu_reg_imm (code, X86_CMP, AMD64_RAX, 0);
7103                 buf = code;
7104                 x86_branch8 (code, X86_CC_EQ, 1, FALSE);
7105                 amd64_breakpoint (code);
7106                 amd64_patch (buf, code);
7107         }
7108 #endif
7109
7110         if (mini_get_debug_options ()->init_stacks) {
7111                 /* Fill the stack frame with a dummy value to force deterministic behavior */
7112
7113                 /* Save registers to the red zone */
7114                 amd64_mov_membase_reg (code, AMD64_RSP, -8, AMD64_RDI, 8);
7115                 amd64_mov_membase_reg (code, AMD64_RSP, -16, AMD64_RCX, 8);
7116
7117                 amd64_mov_reg_imm (code, AMD64_RAX, 0x2a2a2a2a2a2a2a2a);
7118                 amd64_mov_reg_imm (code, AMD64_RCX, alloc_size / 8);
7119                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RSP, 8);
7120
7121                 amd64_cld (code);
7122 #if defined(__default_codegen__)
7123                 amd64_prefix (code, X86_REP_PREFIX);
7124                 amd64_stosl (code);
7125 #elif defined(__native_client_codegen__)
7126                 /* NaCl stos pseudo-instruction */
7127                 amd64_codegen_pre (code);
7128                 /* First, clear the upper 32 bits of RDI (mov %edi, %edi)  */
7129                 amd64_mov_reg_reg (code, AMD64_RDI, AMD64_RDI, 4);
7130                 /* Add %r15 to %rdi using lea, condition flags unaffected. */
7131                 amd64_lea_memindex_size (code, AMD64_RDI, AMD64_R15, 0, AMD64_RDI, 0, 8);
7132                 amd64_prefix (code, X86_REP_PREFIX);
7133                 amd64_stosl (code);
7134                 amd64_codegen_post (code);
7135 #endif /* __native_client_codegen__ */
7136
7137                 amd64_mov_reg_membase (code, AMD64_RDI, AMD64_RSP, -8, 8);
7138                 amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RSP, -16, 8);
7139         }
7140
7141         /* Save LMF */
7142         if (method->save_lmf)
7143                 code = emit_setup_lmf (cfg, code, lmf_var->inst_offset, cfa_offset);
7144
7145         /* Save callee saved registers */
7146         if (cfg->arch.omit_fp) {
7147                 save_area_offset = cfg->arch.reg_save_area_offset;
7148                 /* Save caller saved registers after sp is adjusted */
7149                 /* The registers are saved at the bottom of the frame */
7150                 /* FIXME: Optimize this so the regs are saved at the end of the frame in increasing order */
7151         } else {
7152                 /* The registers are saved just below the saved rbp */
7153                 save_area_offset = cfg->arch.reg_save_area_offset;
7154         }
7155
7156         for (i = 0; i < AMD64_NREG; ++i) {
7157                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7158                         amd64_mov_membase_reg (code, cfg->frame_reg, save_area_offset, i, 8);
7159
7160                         if (cfg->arch.omit_fp) {
7161                                 mono_emit_unwind_op_offset (cfg, code, i, - (cfa_offset - save_area_offset));
7162                                 /* These are handled automatically by the stack marking code */
7163                                 mini_gc_set_slot_type_from_cfa (cfg, - (cfa_offset - save_area_offset), SLOT_NOREF);
7164                         } else {
7165                                 mono_emit_unwind_op_offset (cfg, code, i, - (-save_area_offset + (2 * 8)));
7166                                 // FIXME: GC
7167                         }
7168
7169                         save_area_offset += 8;
7170                         async_exc_point (code);
7171                 }
7172         }
7173
7174         /* store runtime generic context */
7175         if (cfg->rgctx_var) {
7176                 g_assert (cfg->rgctx_var->opcode == OP_REGOFFSET &&
7177                                 (cfg->rgctx_var->inst_basereg == AMD64_RBP || cfg->rgctx_var->inst_basereg == AMD64_RSP));
7178
7179                 amd64_mov_membase_reg (code, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, MONO_ARCH_RGCTX_REG, sizeof(gpointer));
7180
7181                 mono_add_var_location (cfg, cfg->rgctx_var, TRUE, MONO_ARCH_RGCTX_REG, 0, 0, code - cfg->native_code);
7182                 mono_add_var_location (cfg, cfg->rgctx_var, FALSE, cfg->rgctx_var->inst_basereg, cfg->rgctx_var->inst_offset, code - cfg->native_code, 0);
7183         }
7184
7185         /* compute max_length in order to use short forward jumps */
7186         max_epilog_size = get_max_epilog_size (cfg);
7187         if (cfg->opt & MONO_OPT_BRANCH) {
7188                 for (bb = cfg->bb_entry; bb; bb = bb->next_bb) {
7189                         MonoInst *ins;
7190                         int max_length = 0;
7191
7192                         if (cfg->prof_options & MONO_PROFILE_COVERAGE)
7193                                 max_length += 6;
7194                         /* max alignment for loops */
7195                         if ((cfg->opt & MONO_OPT_LOOP) && bb_is_loop_start (bb))
7196                                 max_length += LOOP_ALIGNMENT;
7197 #ifdef __native_client_codegen__
7198                         /* max alignment for native client */
7199                         max_length += kNaClAlignment;
7200 #endif
7201
7202                         MONO_BB_FOR_EACH_INS (bb, ins) {
7203 #ifdef __native_client_codegen__
7204                                 {
7205                                         int space_in_block = kNaClAlignment -
7206                                                 ((max_length + cfg->code_len) & kNaClAlignmentMask);
7207                                         int max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7208                                         if (space_in_block < max_len && max_len < kNaClAlignment) {
7209                                                 max_length += space_in_block;
7210                                         }
7211                                 }
7212 #endif  /*__native_client_codegen__*/
7213                                 max_length += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
7214                         }
7215
7216                         /* Take prolog and epilog instrumentation into account */
7217                         if (bb == cfg->bb_entry || bb == cfg->bb_exit)
7218                                 max_length += max_epilog_size;
7219
7220                         bb->max_length = max_length;
7221                 }
7222         }
7223
7224         sig = mono_method_signature (method);
7225         pos = 0;
7226
7227         cinfo = (CallInfo *)cfg->arch.cinfo;
7228
7229         if (sig->ret->type != MONO_TYPE_VOID) {
7230                 /* Save volatile arguments to the stack */
7231                 if (cfg->vret_addr && (cfg->vret_addr->opcode != OP_REGVAR))
7232                         amd64_mov_membase_reg (code, cfg->vret_addr->inst_basereg, cfg->vret_addr->inst_offset, cinfo->ret.reg, 8);
7233         }
7234
7235         /* Keep this in sync with emit_load_volatile_arguments */
7236         for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
7237                 ArgInfo *ainfo = cinfo->args + i;
7238
7239                 ins = cfg->args [i];
7240
7241                 if ((ins->flags & MONO_INST_IS_DEAD) && !trace)
7242                         /* Unused arguments */
7243                         continue;
7244
7245                 /* Save volatile arguments to the stack */
7246                 if (ins->opcode != OP_REGVAR) {
7247                         switch (ainfo->storage) {
7248                         case ArgInIReg: {
7249                                 guint32 size = 8;
7250
7251                                 /* FIXME: I1 etc */
7252                                 /*
7253                                 if (stack_offset & 0x1)
7254                                         size = 1;
7255                                 else if (stack_offset & 0x2)
7256                                         size = 2;
7257                                 else if (stack_offset & 0x4)
7258                                         size = 4;
7259                                 else
7260                                         size = 8;
7261                                 */
7262                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, size);
7263
7264                                 /*
7265                                  * Save the original location of 'this',
7266                                  * get_generic_info_from_stack_frame () needs this to properly look up
7267                                  * the argument value during the handling of async exceptions.
7268                                  */
7269                                 if (ins == cfg->args [0]) {
7270                                         mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7271                                         mono_add_var_location (cfg, ins, FALSE, ins->inst_basereg, ins->inst_offset, code - cfg->native_code, 0);
7272                                 }
7273                                 break;
7274                         }
7275                         case ArgInFloatSSEReg:
7276                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7277                                 break;
7278                         case ArgInDoubleSSEReg:
7279                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg);
7280                                 break;
7281                         case ArgValuetypeInReg:
7282                                 for (quad = 0; quad < 2; quad ++) {
7283                                         switch (ainfo->pair_storage [quad]) {
7284                                         case ArgInIReg:
7285                                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad], sizeof(mgreg_t));
7286                                                 break;
7287                                         case ArgInFloatSSEReg:
7288                                                 amd64_movss_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7289                                                 break;
7290                                         case ArgInDoubleSSEReg:
7291                                                 amd64_movsd_membase_reg (code, ins->inst_basereg, ins->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_regs [quad]);
7292                                                 break;
7293                                         case ArgNone:
7294                                                 break;
7295                                         default:
7296                                                 g_assert_not_reached ();
7297                                         }
7298                                 }
7299                                 break;
7300                         case ArgValuetypeAddrInIReg:
7301                                 if (ainfo->pair_storage [0] == ArgInIReg)
7302                                         amd64_mov_membase_reg (code, ins->inst_left->inst_basereg, ins->inst_left->inst_offset, ainfo->pair_regs [0],  sizeof (gpointer));
7303                                 break;
7304                         case ArgGSharedVtInReg:
7305                                 amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, ainfo->reg, 8);
7306                                 break;
7307                         default:
7308                                 break;
7309                         }
7310                 } else {
7311                         /* Argument allocated to (non-volatile) register */
7312                         switch (ainfo->storage) {
7313                         case ArgInIReg:
7314                                 amd64_mov_reg_reg (code, ins->dreg, ainfo->reg, 8);
7315                                 break;
7316                         case ArgOnStack:
7317                                 amd64_mov_reg_membase (code, ins->dreg, AMD64_RBP, ARGS_OFFSET + ainfo->offset, 8);
7318                                 break;
7319                         default:
7320                                 g_assert_not_reached ();
7321                         }
7322
7323                         if (ins == cfg->args [0]) {
7324                                 mono_add_var_location (cfg, ins, TRUE, ainfo->reg, 0, 0, code - cfg->native_code);
7325                                 mono_add_var_location (cfg, ins, TRUE, ins->dreg, 0, code - cfg->native_code, 0);
7326                         }
7327                 }
7328         }
7329
7330         if (cfg->method->save_lmf)
7331                 args_clobbered = TRUE;
7332
7333         if (trace) {
7334                 args_clobbered = TRUE;
7335                 code = (guint8 *)mono_arch_instrument_prolog (cfg, mono_trace_enter_method, code, TRUE);
7336         }
7337
7338         if (cfg->prof_options & MONO_PROFILE_ENTER_LEAVE)
7339                 args_clobbered = TRUE;
7340
7341         /*
7342          * Optimize the common case of the first bblock making a call with the same
7343          * arguments as the method. This works because the arguments are still in their
7344          * original argument registers.
7345          * FIXME: Generalize this
7346          */
7347         if (!args_clobbered) {
7348                 MonoBasicBlock *first_bb = cfg->bb_entry;
7349                 MonoInst *next;
7350                 int filter = FILTER_IL_SEQ_POINT;
7351
7352                 next = mono_bb_first_inst (first_bb, filter);
7353                 if (!next && first_bb->next_bb) {
7354                         first_bb = first_bb->next_bb;
7355                         next = mono_bb_first_inst (first_bb, filter);
7356                 }
7357
7358                 if (first_bb->in_count > 1)
7359                         next = NULL;
7360
7361                 for (i = 0; next && i < sig->param_count + sig->hasthis; ++i) {
7362                         ArgInfo *ainfo = cinfo->args + i;
7363                         gboolean match = FALSE;
7364
7365                         ins = cfg->args [i];
7366                         if (ins->opcode != OP_REGVAR) {
7367                                 switch (ainfo->storage) {
7368                                 case ArgInIReg: {
7369                                         if (((next->opcode == OP_LOAD_MEMBASE) || (next->opcode == OP_LOADI4_MEMBASE)) && next->inst_basereg == ins->inst_basereg && next->inst_offset == ins->inst_offset) {
7370                                                 if (next->dreg == ainfo->reg) {
7371                                                         NULLIFY_INS (next);
7372                                                         match = TRUE;
7373                                                 } else {
7374                                                         next->opcode = OP_MOVE;
7375                                                         next->sreg1 = ainfo->reg;
7376                                                         /* Only continue if the instruction doesn't change argument regs */
7377                                                         if (next->dreg == ainfo->reg || next->dreg == AMD64_RAX)
7378                                                                 match = TRUE;
7379                                                 }
7380                                         }
7381                                         break;
7382                                 }
7383                                 default:
7384                                         break;
7385                                 }
7386                         } else {
7387                                 /* Argument allocated to (non-volatile) register */
7388                                 switch (ainfo->storage) {
7389                                 case ArgInIReg:
7390                                         if (next->opcode == OP_MOVE && next->sreg1 == ins->dreg && next->dreg == ainfo->reg) {
7391                                                 NULLIFY_INS (next);
7392                                                 match = TRUE;
7393                                         }
7394                                         break;
7395                                 default:
7396                                         break;
7397                                 }
7398                         }
7399
7400                         if (match) {
7401                                 next = mono_inst_next (next, filter);
7402                                 //next = mono_inst_list_next (&next->node, &first_bb->ins_list);
7403                                 if (!next)
7404                                         break;
7405                         }
7406                 }
7407         }
7408
7409         if (cfg->gen_sdb_seq_points) {
7410                 MonoInst *info_var = (MonoInst *)cfg->arch.seq_point_info_var;
7411
7412                 /* Initialize seq_point_info_var */
7413                 if (cfg->compile_aot) {
7414                         /* Initialize the variable from a GOT slot */
7415                         /* Same as OP_AOTCONST */
7416                         mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_SEQ_POINT_INFO, cfg->method);
7417                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, sizeof(gpointer));
7418                         g_assert (info_var->opcode == OP_REGOFFSET);
7419                         amd64_mov_membase_reg (code, info_var->inst_basereg, info_var->inst_offset, AMD64_R11, 8);
7420                 }
7421
7422                 if (cfg->compile_aot) {
7423                         /* Initialize ss_tramp_var */
7424                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7425                         g_assert (ins->opcode == OP_REGOFFSET);
7426
7427                         amd64_mov_reg_membase (code, AMD64_R11, info_var->inst_basereg, info_var->inst_offset, 8);
7428                         amd64_mov_reg_membase (code, AMD64_R11, AMD64_R11, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr), 8);
7429                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7430                 } else {
7431                         /* Initialize ss_tramp_var */
7432                         ins = (MonoInst *)cfg->arch.ss_tramp_var;
7433                         g_assert (ins->opcode == OP_REGOFFSET);
7434
7435                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&ss_trampoline);
7436                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7437
7438                         /* Initialize bp_tramp_var */
7439                         ins = (MonoInst *)cfg->arch.bp_tramp_var;
7440                         g_assert (ins->opcode == OP_REGOFFSET);
7441
7442                         amd64_mov_reg_imm (code, AMD64_R11, (guint64)&bp_trampoline);
7443                         amd64_mov_membase_reg (code, ins->inst_basereg, ins->inst_offset, AMD64_R11, 8);
7444                 }
7445         }
7446
7447         cfg->code_len = code - cfg->native_code;
7448
7449         g_assert (cfg->code_len < cfg->code_size);
7450
7451         return code;
7452 }
7453
7454 void
7455 mono_arch_emit_epilog (MonoCompile *cfg)
7456 {
7457         MonoMethod *method = cfg->method;
7458         int quad, i;
7459         guint8 *code;
7460         int max_epilog_size;
7461         CallInfo *cinfo;
7462         gint32 lmf_offset = cfg->lmf_var ? ((MonoInst*)cfg->lmf_var)->inst_offset : -1;
7463         gint32 save_area_offset = cfg->arch.reg_save_area_offset;
7464
7465         max_epilog_size = get_max_epilog_size (cfg);
7466
7467         while (cfg->code_len + max_epilog_size > (cfg->code_size - 16)) {
7468                 cfg->code_size *= 2;
7469                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7470                 cfg->stat_code_reallocs++;
7471         }
7472         code = cfg->native_code + cfg->code_len;
7473
7474         cfg->has_unwind_info_for_epilog = TRUE;
7475
7476         /* Mark the start of the epilog */
7477         mono_emit_unwind_op_mark_loc (cfg, code, 0);
7478
7479         /* Save the uwind state which is needed by the out-of-line code */
7480         mono_emit_unwind_op_remember_state (cfg, code);
7481
7482         if (mono_jit_trace_calls != NULL && mono_trace_eval (method))
7483                 code = (guint8 *)mono_arch_instrument_epilog (cfg, mono_trace_leave_method, code, TRUE);
7484
7485         /* the code restoring the registers must be kept in sync with OP_TAILCALL */
7486
7487         if (method->save_lmf) {
7488                 /* check if we need to restore protection of the stack after a stack overflow */
7489                 if (!cfg->compile_aot && mono_get_jit_tls_offset () != -1) {
7490                         guint8 *patch;
7491                         code = mono_amd64_emit_tls_get (code, AMD64_RCX, mono_get_jit_tls_offset ());
7492                         /* we load the value in a separate instruction: this mechanism may be
7493                          * used later as a safer way to do thread interruption
7494                          */
7495                         amd64_mov_reg_membase (code, AMD64_RCX, AMD64_RCX, MONO_STRUCT_OFFSET (MonoJitTlsData, restore_stack_prot), 8);
7496                         x86_alu_reg_imm (code, X86_CMP, X86_ECX, 0);
7497                         patch = code;
7498                         x86_branch8 (code, X86_CC_Z, 0, FALSE);
7499                         /* note that the call trampoline will preserve eax/edx */
7500                         x86_call_reg (code, X86_ECX);
7501                         x86_patch (patch, code);
7502                 } else {
7503                         /* FIXME: maybe save the jit tls in the prolog */
7504                 }
7505                 if (cfg->used_int_regs & (1 << AMD64_RBP)) {
7506                         amd64_mov_reg_membase (code, AMD64_RBP, cfg->frame_reg, lmf_offset + MONO_STRUCT_OFFSET (MonoLMF, rbp), 8);
7507                 }
7508         }
7509
7510         /* Restore callee saved regs */
7511         for (i = 0; i < AMD64_NREG; ++i) {
7512                 if (AMD64_IS_CALLEE_SAVED_REG (i) && (cfg->arch.saved_iregs & (1 << i))) {
7513                         /* Restore only used_int_regs, not arch.saved_iregs */
7514                         if (cfg->used_int_regs & (1 << i)) {
7515                                 amd64_mov_reg_membase (code, i, cfg->frame_reg, save_area_offset, 8);
7516                                 mono_emit_unwind_op_same_value (cfg, code, i);
7517                                 async_exc_point (code);
7518                         }
7519                         save_area_offset += 8;
7520                 }
7521         }
7522
7523         /* Load returned vtypes into registers if needed */
7524         cinfo = (CallInfo *)cfg->arch.cinfo;
7525         if (cinfo->ret.storage == ArgValuetypeInReg) {
7526                 ArgInfo *ainfo = &cinfo->ret;
7527                 MonoInst *inst = cfg->ret;
7528
7529                 for (quad = 0; quad < 2; quad ++) {
7530                         switch (ainfo->pair_storage [quad]) {
7531                         case ArgInIReg:
7532                                 amd64_mov_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)), ainfo->pair_size [quad]);
7533                                 break;
7534                         case ArgInFloatSSEReg:
7535                                 amd64_movss_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7536                                 break;
7537                         case ArgInDoubleSSEReg:
7538                                 amd64_movsd_reg_membase (code, ainfo->pair_regs [quad], inst->inst_basereg, inst->inst_offset + (quad * sizeof(mgreg_t)));
7539                                 break;
7540                         case ArgNone:
7541                                 break;
7542                         default:
7543                                 g_assert_not_reached ();
7544                         }
7545                 }
7546         }
7547
7548         if (cfg->arch.omit_fp) {
7549                 if (cfg->arch.stack_alloc_size) {
7550                         amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, cfg->arch.stack_alloc_size);
7551                 }
7552         } else {
7553                 amd64_leave (code);
7554                 mono_emit_unwind_op_same_value (cfg, code, AMD64_RBP);
7555         }
7556         mono_emit_unwind_op_def_cfa (cfg, code, AMD64_RSP, 8);
7557         async_exc_point (code);
7558         amd64_ret (code);
7559
7560         /* Restore the unwind state to be the same as before the epilog */
7561         mono_emit_unwind_op_restore_state (cfg, code);
7562
7563         cfg->code_len = code - cfg->native_code;
7564
7565         g_assert (cfg->code_len < cfg->code_size);
7566 }
7567
7568 void
7569 mono_arch_emit_exceptions (MonoCompile *cfg)
7570 {
7571         MonoJumpInfo *patch_info;
7572         int nthrows, i;
7573         guint8 *code;
7574         MonoClass *exc_classes [16];
7575         guint8 *exc_throw_start [16], *exc_throw_end [16];
7576         guint32 code_size = 0;
7577
7578         /* Compute needed space */
7579         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7580                 if (patch_info->type == MONO_PATCH_INFO_EXC)
7581                         code_size += 40;
7582                 if (patch_info->type == MONO_PATCH_INFO_R8)
7583                         code_size += 8 + 15; /* sizeof (double) + alignment */
7584                 if (patch_info->type == MONO_PATCH_INFO_R4)
7585                         code_size += 4 + 15; /* sizeof (float) + alignment */
7586                 if (patch_info->type == MONO_PATCH_INFO_GC_CARD_TABLE_ADDR)
7587                         code_size += 8 + 7; /*sizeof (void*) + alignment */
7588         }
7589
7590 #ifdef __native_client_codegen__
7591         /* Give us extra room on Native Client.  This could be   */
7592         /* more carefully calculated, but bundle alignment makes */
7593         /* it much trickier, so *2 like other places is good.    */
7594         code_size *= 2;
7595 #endif
7596
7597         while (cfg->code_len + code_size > (cfg->code_size - 16)) {
7598                 cfg->code_size *= 2;
7599                 cfg->native_code = (unsigned char *)mono_realloc_native_code (cfg);
7600                 cfg->stat_code_reallocs++;
7601         }
7602
7603         code = cfg->native_code + cfg->code_len;
7604
7605         /* add code to raise exceptions */
7606         nthrows = 0;
7607         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7608                 switch (patch_info->type) {
7609                 case MONO_PATCH_INFO_EXC: {
7610                         MonoClass *exc_class;
7611                         guint8 *buf, *buf2;
7612                         guint32 throw_ip;
7613
7614                         amd64_patch (patch_info->ip.i + cfg->native_code, code);
7615
7616                         exc_class = mono_class_from_name (mono_defaults.corlib, "System", patch_info->data.name);
7617                         g_assert (exc_class);
7618                         throw_ip = patch_info->ip.i;
7619
7620                         //x86_breakpoint (code);
7621                         /* Find a throw sequence for the same exception class */
7622                         for (i = 0; i < nthrows; ++i)
7623                                 if (exc_classes [i] == exc_class)
7624                                         break;
7625                         if (i < nthrows) {
7626                                 amd64_mov_reg_imm (code, AMD64_ARG_REG2, (exc_throw_end [i] - cfg->native_code) - throw_ip);
7627                                 x86_jump_code (code, exc_throw_start [i]);
7628                                 patch_info->type = MONO_PATCH_INFO_NONE;
7629                         }
7630                         else {
7631                                 buf = code;
7632                                 amd64_mov_reg_imm_size (code, AMD64_ARG_REG2, 0xf0f0f0f0, 4);
7633                                 buf2 = code;
7634
7635                                 if (nthrows < 16) {
7636                                         exc_classes [nthrows] = exc_class;
7637                                         exc_throw_start [nthrows] = code;
7638                                 }
7639                                 amd64_mov_reg_imm (code, AMD64_ARG_REG1, exc_class->type_token - MONO_TOKEN_TYPE_DEF);
7640
7641                                 patch_info->type = MONO_PATCH_INFO_NONE;
7642
7643                                 code = emit_call_body (cfg, code, MONO_PATCH_INFO_INTERNAL_METHOD, "mono_arch_throw_corlib_exception");
7644
7645                                 amd64_mov_reg_imm (buf, AMD64_ARG_REG2, (code - cfg->native_code) - throw_ip);
7646                                 while (buf < buf2)
7647                                         x86_nop (buf);
7648
7649                                 if (nthrows < 16) {
7650                                         exc_throw_end [nthrows] = code;
7651                                         nthrows ++;
7652                                 }
7653                         }
7654                         break;
7655                 }
7656                 default:
7657                         /* do nothing */
7658                         break;
7659                 }
7660                 g_assert(code < cfg->native_code + cfg->code_size);
7661         }
7662
7663         /* Handle relocations with RIP relative addressing */
7664         for (patch_info = cfg->patch_info; patch_info; patch_info = patch_info->next) {
7665                 gboolean remove = FALSE;
7666                 guint8 *orig_code = code;
7667
7668                 switch (patch_info->type) {
7669                 case MONO_PATCH_INFO_R8:
7670                 case MONO_PATCH_INFO_R4: {
7671                         guint8 *pos, *patch_pos;
7672                         guint32 target_pos;
7673
7674                         /* The SSE opcodes require a 16 byte alignment */
7675 #if defined(__default_codegen__)
7676                         code = (guint8*)ALIGN_TO (code, 16);
7677 #elif defined(__native_client_codegen__)
7678                         {
7679                                 /* Pad this out with HLT instructions  */
7680                                 /* or we can get garbage bytes emitted */
7681                                 /* which will fail validation          */
7682                                 guint8 *aligned_code;
7683                                 /* extra align to make room for  */
7684                                 /* mov/push below                      */
7685                                 int extra_align = patch_info->type == MONO_PATCH_INFO_R8 ? 2 : 1;
7686                                 aligned_code = (guint8*)ALIGN_TO (code + extra_align, 16);
7687                                 /* The technique of hiding data in an  */
7688                                 /* instruction has a problem here: we  */
7689                                 /* need the data aligned to a 16-byte  */
7690                                 /* boundary but the instruction cannot */
7691                                 /* cross the bundle boundary. so only  */
7692                                 /* odd multiples of 16 can be used     */
7693                                 if ((intptr_t)aligned_code % kNaClAlignment == 0) {
7694                                         aligned_code += 16;
7695                                 }
7696                                 while (code < aligned_code) {
7697                                         *(code++) = 0xf4; /* hlt */
7698                                 }
7699                         }
7700 #endif
7701
7702                         pos = cfg->native_code + patch_info->ip.i;
7703                         if (IS_REX (pos [1])) {
7704                                 patch_pos = pos + 5;
7705                                 target_pos = code - pos - 9;
7706                         }
7707                         else {
7708                                 patch_pos = pos + 4;
7709                                 target_pos = code - pos - 8;
7710                         }
7711
7712                         if (patch_info->type == MONO_PATCH_INFO_R8) {
7713 #ifdef __native_client_codegen__
7714                                 /* Hide 64-bit data in a         */
7715                                 /* "mov imm64, r11" instruction. */
7716                                 /* write it before the start of  */
7717                                 /* the data*/
7718                                 *(code-2) = 0x49; /* prefix      */
7719                                 *(code-1) = 0xbb; /* mov X, %r11 */
7720 #endif
7721                                 *(double*)code = *(double*)patch_info->data.target;
7722                                 code += sizeof (double);
7723                         } else {
7724 #ifdef __native_client_codegen__
7725                                 /* Hide 32-bit data in a        */
7726                                 /* "push imm32" instruction.    */
7727                                 *(code-1) = 0x68; /* push */
7728 #endif
7729                                 *(float*)code = *(float*)patch_info->data.target;
7730                                 code += sizeof (float);
7731                         }
7732
7733                         *(guint32*)(patch_pos) = target_pos;
7734
7735                         remove = TRUE;
7736                         break;
7737                 }
7738                 case MONO_PATCH_INFO_GC_CARD_TABLE_ADDR: {
7739                         guint8 *pos;
7740
7741                         if (cfg->compile_aot)
7742                                 continue;
7743
7744                         /*loading is faster against aligned addresses.*/
7745                         code = (guint8*)ALIGN_TO (code, 8);
7746                         memset (orig_code, 0, code - orig_code);
7747
7748                         pos = cfg->native_code + patch_info->ip.i;
7749
7750                         /*alu_op [rex] modr/m imm32 - 7 or 8 bytes */
7751                         if (IS_REX (pos [1]))
7752                                 *(guint32*)(pos + 4) = (guint8*)code - pos - 8;
7753                         else
7754                                 *(guint32*)(pos + 3) = (guint8*)code - pos - 7;
7755
7756                         *(gpointer*)code = (gpointer)patch_info->data.target;
7757                         code += sizeof (gpointer);
7758
7759                         remove = TRUE;
7760                         break;
7761                 }
7762                 default:
7763                         break;
7764                 }
7765
7766                 if (remove) {
7767                         if (patch_info == cfg->patch_info)
7768                                 cfg->patch_info = patch_info->next;
7769                         else {
7770                                 MonoJumpInfo *tmp;
7771
7772                                 for (tmp = cfg->patch_info; tmp->next != patch_info; tmp = tmp->next)
7773                                         ;
7774                                 tmp->next = patch_info->next;
7775                         }
7776                 }
7777                 g_assert (code < cfg->native_code + cfg->code_size);
7778         }
7779
7780         cfg->code_len = code - cfg->native_code;
7781
7782         g_assert (cfg->code_len < cfg->code_size);
7783
7784 }
7785
7786 #endif /* DISABLE_JIT */
7787
7788 void*
7789 mono_arch_instrument_prolog (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments)
7790 {
7791         guchar *code = (guchar *)p;
7792         MonoMethodSignature *sig;
7793         MonoInst *inst;
7794         int i, n, stack_area = 0;
7795
7796         /* Keep this in sync with mono_arch_get_argument_info */
7797
7798         if (enable_arguments) {
7799                 /* Allocate a new area on the stack and save arguments there */
7800                 sig = mono_method_signature (cfg->method);
7801
7802                 n = sig->param_count + sig->hasthis;
7803
7804                 stack_area = ALIGN_TO (n * 8, 16);
7805
7806                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, stack_area);
7807
7808                 for (i = 0; i < n; ++i) {
7809                         inst = cfg->args [i];
7810
7811                         if (inst->opcode == OP_REGVAR)
7812                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), inst->dreg, 8);
7813                         else {
7814                                 amd64_mov_reg_membase (code, AMD64_R11, inst->inst_basereg, inst->inst_offset, 8);
7815                                 amd64_mov_membase_reg (code, AMD64_RSP, (i * 8), AMD64_R11, 8);
7816                         }
7817                 }
7818         }
7819
7820         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, cfg->method);
7821         amd64_set_reg_template (code, AMD64_ARG_REG1);
7822         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RSP, 8);
7823         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7824
7825         if (enable_arguments)
7826                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, stack_area);
7827
7828         return code;
7829 }
7830
7831 enum {
7832         SAVE_NONE,
7833         SAVE_STRUCT,
7834         SAVE_EAX,
7835         SAVE_EAX_EDX,
7836         SAVE_XMM
7837 };
7838
7839 void*
7840 mono_arch_instrument_epilog_full (MonoCompile *cfg, void *func, void *p, gboolean enable_arguments, gboolean preserve_argument_registers)
7841 {
7842         guchar *code = (guchar *)p;
7843         int save_mode = SAVE_NONE;
7844         MonoMethod *method = cfg->method;
7845         MonoType *ret_type = mini_get_underlying_type (mono_method_signature (method)->ret);
7846         int i;
7847
7848         switch (ret_type->type) {
7849         case MONO_TYPE_VOID:
7850                 /* special case string .ctor icall */
7851                 if (strcmp (".ctor", method->name) && method->klass == mono_defaults.string_class)
7852                         save_mode = SAVE_EAX;
7853                 else
7854                         save_mode = SAVE_NONE;
7855                 break;
7856         case MONO_TYPE_I8:
7857         case MONO_TYPE_U8:
7858                 save_mode = SAVE_EAX;
7859                 break;
7860         case MONO_TYPE_R4:
7861         case MONO_TYPE_R8:
7862                 save_mode = SAVE_XMM;
7863                 break;
7864         case MONO_TYPE_GENERICINST:
7865                 if (!mono_type_generic_inst_is_valuetype (ret_type)) {
7866                         save_mode = SAVE_EAX;
7867                         break;
7868                 }
7869                 /* Fall through */
7870         case MONO_TYPE_VALUETYPE:
7871                 save_mode = SAVE_STRUCT;
7872                 break;
7873         default:
7874                 save_mode = SAVE_EAX;
7875                 break;
7876         }
7877
7878         /* Save the result and copy it into the proper argument register */
7879         switch (save_mode) {
7880         case SAVE_EAX:
7881                 amd64_push_reg (code, AMD64_RAX);
7882                 /* Align stack */
7883                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7884                 if (enable_arguments)
7885                         amd64_mov_reg_reg (code, AMD64_ARG_REG2, AMD64_RAX, 8);
7886                 break;
7887         case SAVE_STRUCT:
7888                 /* FIXME: */
7889                 if (enable_arguments)
7890                         amd64_mov_reg_imm (code, AMD64_ARG_REG2, 0);
7891                 break;
7892         case SAVE_XMM:
7893                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7894                 amd64_movsd_membase_reg (code, AMD64_RSP, 0, AMD64_XMM0);
7895                 /* Align stack */
7896                 amd64_alu_reg_imm (code, X86_SUB, AMD64_RSP, 8);
7897                 /*
7898                  * The result is already in the proper argument register so no copying
7899                  * needed.
7900                  */
7901                 break;
7902         case SAVE_NONE:
7903                 break;
7904         default:
7905                 g_assert_not_reached ();
7906         }
7907
7908         /* Set %al since this is a varargs call */
7909         if (save_mode == SAVE_XMM)
7910                 amd64_mov_reg_imm (code, AMD64_RAX, 1);
7911         else
7912                 amd64_mov_reg_imm (code, AMD64_RAX, 0);
7913
7914         if (preserve_argument_registers) {
7915                 for (i = 0; i < PARAM_REGS; ++i)
7916                         amd64_push_reg (code, param_regs [i]);
7917         }
7918
7919         mono_add_patch_info (cfg, code-cfg->native_code, MONO_PATCH_INFO_METHODCONST, method);
7920         amd64_set_reg_template (code, AMD64_ARG_REG1);
7921         code = emit_call (cfg, code, MONO_PATCH_INFO_ABS, (gpointer)func, TRUE);
7922
7923         if (preserve_argument_registers) {
7924                 for (i = PARAM_REGS - 1; i >= 0; --i)
7925                         amd64_pop_reg (code, param_regs [i]);
7926         }
7927
7928         /* Restore result */
7929         switch (save_mode) {
7930         case SAVE_EAX:
7931                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7932                 amd64_pop_reg (code, AMD64_RAX);
7933                 break;
7934         case SAVE_STRUCT:
7935                 /* FIXME: */
7936                 break;
7937         case SAVE_XMM:
7938                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7939                 amd64_movsd_reg_membase (code, AMD64_XMM0, AMD64_RSP, 0);
7940                 amd64_alu_reg_imm (code, X86_ADD, AMD64_RSP, 8);
7941                 break;
7942         case SAVE_NONE:
7943                 break;
7944         default:
7945                 g_assert_not_reached ();
7946         }
7947
7948         return code;
7949 }
7950
7951 void
7952 mono_arch_flush_icache (guint8 *code, gint size)
7953 {
7954         /* Not needed */
7955 }
7956
7957 void
7958 mono_arch_flush_register_windows (void)
7959 {
7960 }
7961
7962 gboolean
7963 mono_arch_is_inst_imm (gint64 imm)
7964 {
7965         return amd64_use_imm32 (imm);
7966 }
7967
7968 /*
7969  * Determine whenever the trap whose info is in SIGINFO is caused by
7970  * integer overflow.
7971  */
7972 gboolean
7973 mono_arch_is_int_overflow (void *sigctx, void *info)
7974 {
7975         MonoContext ctx;
7976         guint8* rip;
7977         int reg;
7978         gint64 value;
7979
7980         mono_sigctx_to_monoctx (sigctx, &ctx);
7981
7982         rip = (guint8*)ctx.gregs [AMD64_RIP];
7983
7984         if (IS_REX (rip [0])) {
7985                 reg = amd64_rex_b (rip [0]);
7986                 rip ++;
7987         }
7988         else
7989                 reg = 0;
7990
7991         if ((rip [0] == 0xf7) && (x86_modrm_mod (rip [1]) == 0x3) && (x86_modrm_reg (rip [1]) == 0x7)) {
7992                 /* idiv REG */
7993                 reg += x86_modrm_rm (rip [1]);
7994
7995                 value = ctx.gregs [reg];
7996
7997                 if (value == -1)
7998                         return TRUE;
7999         }
8000
8001         return FALSE;
8002 }
8003
8004 guint32
8005 mono_arch_get_patch_offset (guint8 *code)
8006 {
8007         return 3;
8008 }
8009
8010 /**
8011  * mono_breakpoint_clean_code:
8012  *
8013  * Copy @size bytes from @code - @offset to the buffer @buf. If the debugger inserted software
8014  * breakpoints in the original code, they are removed in the copy.
8015  *
8016  * Returns TRUE if no sw breakpoint was present.
8017  */
8018 gboolean
8019 mono_breakpoint_clean_code (guint8 *method_start, guint8 *code, int offset, guint8 *buf, int size)
8020 {
8021         /*
8022          * If method_start is non-NULL we need to perform bound checks, since we access memory
8023          * at code - offset we could go before the start of the method and end up in a different
8024          * page of memory that is not mapped or read incorrect data anyway. We zero-fill the bytes
8025          * instead.
8026          */
8027         if (!method_start || code - offset >= method_start) {
8028                 memcpy (buf, code - offset, size);
8029         } else {
8030                 int diff = code - method_start;
8031                 memset (buf, 0, size);
8032                 memcpy (buf + offset - diff, method_start, diff + size - offset);
8033         }
8034         return TRUE;
8035 }
8036
8037 #if defined(__native_client_codegen__)
8038 /* For membase calls, we want the base register. for Native Client,  */
8039 /* all indirect calls have the following sequence with the given sizes: */
8040 /* mov %eXX,%eXX                                [2-3]   */
8041 /* mov disp(%r15,%rXX,scale),%r11d              [4-8]   */
8042 /* and $0xffffffffffffffe0,%r11d                [4]     */
8043 /* add %r15,%r11                                [3]     */
8044 /* callq *%r11                                  [3]     */
8045
8046
8047 /* Determine if code points to a NaCl call-through-register sequence, */
8048 /* (i.e., the last 3 instructions listed above) */
8049 int
8050 is_nacl_call_reg_sequence(guint8* code)
8051 {
8052         const char *sequence = "\x41\x83\xe3\xe0" /* and */
8053                                "\x4d\x03\xdf"     /* add */
8054                                "\x41\xff\xd3";   /* call */
8055         return memcmp(code, sequence, 10) == 0;
8056 }
8057
8058 /* Determine if code points to the first opcode of the mov membase component */
8059 /* of an indirect call sequence (i.e. the first 2 instructions listed above) */
8060 /* (there could be a REX prefix before the opcode but it is ignored) */
8061 static int
8062 is_nacl_indirect_call_membase_sequence(guint8* code)
8063 {
8064                /* Check for mov opcode, reg-reg addressing mode (mod = 3), */
8065         return code[0] == 0x8b && amd64_modrm_mod(code[1]) == 3 &&
8066                /* and that src reg = dest reg */
8067                amd64_modrm_reg(code[1]) == amd64_modrm_rm(code[1]) &&
8068                /* Check that next inst is mov, uses SIB byte (rm = 4), */
8069                IS_REX(code[2]) &&
8070                code[3] == 0x8b && amd64_modrm_rm(code[4]) == 4 &&
8071                /* and has dst of r11 and base of r15 */
8072                (amd64_modrm_reg(code[4]) + amd64_rex_r(code[2])) == AMD64_R11 &&
8073                (amd64_sib_base(code[5]) + amd64_rex_b(code[2])) == AMD64_R15;
8074 }
8075 #endif /* __native_client_codegen__ */
8076
8077 int
8078 mono_arch_get_this_arg_reg (guint8 *code)
8079 {
8080         return AMD64_ARG_REG1;
8081 }
8082
8083 gpointer
8084 mono_arch_get_this_arg_from_call (mgreg_t *regs, guint8 *code)
8085 {
8086         return (gpointer)regs [mono_arch_get_this_arg_reg (code)];
8087 }
8088
8089 #define MAX_ARCH_DELEGATE_PARAMS 10
8090
8091 static gpointer
8092 get_delegate_invoke_impl (MonoTrampInfo **info, gboolean has_target, guint32 param_count)
8093 {
8094         guint8 *code, *start;
8095         GSList *unwind_ops = NULL;
8096         int i;
8097
8098         unwind_ops = mono_arch_get_cie_program ();
8099
8100         if (has_target) {
8101                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8102
8103                 /* Replace the this argument with the target */
8104                 amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8105                 amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8106                 amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8107
8108                 g_assert ((code - start) < 64);
8109         } else {
8110                 start = code = (guint8 *)mono_global_codeman_reserve (64);
8111
8112                 if (param_count == 0) {
8113                         amd64_jump_membase (code, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8114                 } else {
8115                         /* We have to shift the arguments left */
8116                         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8117                         for (i = 0; i < param_count; ++i) {
8118 #ifdef TARGET_WIN32
8119                                 if (i < 3)
8120                                         amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8121                                 else
8122                                         amd64_mov_reg_membase (code, param_regs [i], AMD64_RSP, 0x28, 8);
8123 #else
8124                                 amd64_mov_reg_reg (code, param_regs [i], param_regs [i + 1], 8);
8125 #endif
8126                         }
8127
8128                         amd64_jump_membase (code, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method_ptr));
8129                 }
8130                 g_assert ((code - start) < 64);
8131         }
8132
8133         nacl_global_codeman_validate (&start, 64, &code);
8134         mono_arch_flush_icache (start, code - start);
8135
8136         if (has_target) {
8137                 *info = mono_tramp_info_create ("delegate_invoke_impl_has_target", start, code - start, NULL, unwind_ops);
8138         } else {
8139                 char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", param_count);
8140                 *info = mono_tramp_info_create (name, start, code - start, NULL, unwind_ops);
8141                 g_free (name);
8142         }
8143
8144         if (mono_jit_map_is_enabled ()) {
8145                 char *buff;
8146                 if (has_target)
8147                         buff = (char*)"delegate_invoke_has_target";
8148                 else
8149                         buff = g_strdup_printf ("delegate_invoke_no_target_%d", param_count);
8150                 mono_emit_jit_tramp (start, code - start, buff);
8151                 if (!has_target)
8152                         g_free (buff);
8153         }
8154         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8155
8156         return start;
8157 }
8158
8159 #define MAX_VIRTUAL_DELEGATE_OFFSET 32
8160
8161 static gpointer
8162 get_delegate_virtual_invoke_impl (MonoTrampInfo **info, gboolean load_imt_reg, int offset)
8163 {
8164         guint8 *code, *start;
8165         int size = 20;
8166         char *tramp_name;
8167         GSList *unwind_ops;
8168
8169         if (offset / (int)sizeof (gpointer) > MAX_VIRTUAL_DELEGATE_OFFSET)
8170                 return NULL;
8171
8172         start = code = (guint8 *)mono_global_codeman_reserve (size);
8173
8174         unwind_ops = mono_arch_get_cie_program ();
8175
8176         /* Replace the this argument with the target */
8177         amd64_mov_reg_reg (code, AMD64_RAX, AMD64_ARG_REG1, 8);
8178         amd64_mov_reg_membase (code, AMD64_ARG_REG1, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, target), 8);
8179
8180         if (load_imt_reg) {
8181                 /* Load the IMT reg */
8182                 amd64_mov_reg_membase (code, MONO_ARCH_IMT_REG, AMD64_RAX, MONO_STRUCT_OFFSET (MonoDelegate, method), 8);
8183         }
8184
8185         /* Load the vtable */
8186         amd64_mov_reg_membase (code, AMD64_RAX, AMD64_ARG_REG1, MONO_STRUCT_OFFSET (MonoObject, vtable), 8);
8187         amd64_jump_membase (code, AMD64_RAX, offset);
8188         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_DELEGATE_INVOKE, NULL);
8189
8190         if (load_imt_reg)
8191                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_imt_%d", - offset / sizeof (gpointer));
8192         else
8193                 tramp_name = g_strdup_printf ("delegate_virtual_invoke_%d", offset / sizeof (gpointer));
8194         *info = mono_tramp_info_create (tramp_name, start, code - start, NULL, unwind_ops);
8195         g_free (tramp_name);
8196
8197         return start;
8198 }
8199
8200 /*
8201  * mono_arch_get_delegate_invoke_impls:
8202  *
8203  *   Return a list of MonoTrampInfo structures for the delegate invoke impl
8204  * trampolines.
8205  */
8206 GSList*
8207 mono_arch_get_delegate_invoke_impls (void)
8208 {
8209         GSList *res = NULL;
8210         MonoTrampInfo *info;
8211         int i;
8212
8213         get_delegate_invoke_impl (&info, TRUE, 0);
8214         res = g_slist_prepend (res, info);
8215
8216         for (i = 0; i <= MAX_ARCH_DELEGATE_PARAMS; ++i) {
8217                 get_delegate_invoke_impl (&info, FALSE, i);
8218                 res = g_slist_prepend (res, info);
8219         }
8220
8221         for (i = 0; i <= MAX_VIRTUAL_DELEGATE_OFFSET; ++i) {
8222                 get_delegate_virtual_invoke_impl (&info, TRUE, - i * SIZEOF_VOID_P);
8223                 res = g_slist_prepend (res, info);
8224
8225                 get_delegate_virtual_invoke_impl (&info, FALSE, i * SIZEOF_VOID_P);
8226                 res = g_slist_prepend (res, info);
8227         }
8228
8229         return res;
8230 }
8231
8232 gpointer
8233 mono_arch_get_delegate_invoke_impl (MonoMethodSignature *sig, gboolean has_target)
8234 {
8235         guint8 *code, *start;
8236         int i;
8237
8238         if (sig->param_count > MAX_ARCH_DELEGATE_PARAMS)
8239                 return NULL;
8240
8241         /* FIXME: Support more cases */
8242         if (MONO_TYPE_ISSTRUCT (mini_get_underlying_type (sig->ret)))
8243                 return NULL;
8244
8245         if (has_target) {
8246                 static guint8* cached = NULL;
8247
8248                 if (cached)
8249                         return cached;
8250
8251                 if (mono_aot_only) {
8252                         start = (guint8 *)mono_aot_get_trampoline ("delegate_invoke_impl_has_target");
8253                 } else {
8254                         MonoTrampInfo *info;
8255                         start = (guint8 *)get_delegate_invoke_impl (&info, TRUE, 0);
8256                         mono_tramp_info_register (info, NULL);
8257                 }
8258
8259                 mono_memory_barrier ();
8260
8261                 cached = start;
8262         } else {
8263                 static guint8* cache [MAX_ARCH_DELEGATE_PARAMS + 1] = {NULL};
8264                 for (i = 0; i < sig->param_count; ++i)
8265                         if (!mono_is_regsize_var (sig->params [i]))
8266                                 return NULL;
8267                 if (sig->param_count > 4)
8268                         return NULL;
8269
8270                 code = cache [sig->param_count];
8271                 if (code)
8272                         return code;
8273
8274                 if (mono_aot_only) {
8275                         char *name = g_strdup_printf ("delegate_invoke_impl_target_%d", sig->param_count);
8276                         start = (guint8 *)mono_aot_get_trampoline (name);
8277                         g_free (name);
8278                 } else {
8279                         MonoTrampInfo *info;
8280                         start = (guint8 *)get_delegate_invoke_impl (&info, FALSE, sig->param_count);
8281                         mono_tramp_info_register (info, NULL);
8282                 }
8283
8284                 mono_memory_barrier ();
8285
8286                 cache [sig->param_count] = start;
8287         }
8288
8289         return start;
8290 }
8291
8292 gpointer
8293 mono_arch_get_delegate_virtual_invoke_impl (MonoMethodSignature *sig, MonoMethod *method, int offset, gboolean load_imt_reg)
8294 {
8295         MonoTrampInfo *info;
8296         gpointer code;
8297
8298         code = get_delegate_virtual_invoke_impl (&info, load_imt_reg, offset);
8299         if (code)
8300                 mono_tramp_info_register (info, NULL);
8301         return code;
8302 }
8303
8304 void
8305 mono_arch_finish_init (void)
8306 {
8307 #if !defined(HOST_WIN32) && defined(MONO_XEN_OPT)
8308         optimize_for_xen = access ("/proc/xen", F_OK) == 0;
8309 #endif
8310 }
8311
8312 void
8313 mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
8314 {
8315 }
8316
8317 #if defined(__default_codegen__)
8318 #define CMP_SIZE (6 + 1)
8319 #define CMP_REG_REG_SIZE (4 + 1)
8320 #define BR_SMALL_SIZE 2
8321 #define BR_LARGE_SIZE 6
8322 #define MOV_REG_IMM_SIZE 10
8323 #define MOV_REG_IMM_32BIT_SIZE 6
8324 #define JUMP_REG_SIZE (2 + 1)
8325 #elif defined(__native_client_codegen__)
8326 /* NaCl N-byte instructions can be padded up to N-1 bytes */
8327 #define CMP_SIZE ((6 + 1) * 2 - 1)
8328 #define CMP_REG_REG_SIZE ((4 + 1) * 2 - 1)
8329 #define BR_SMALL_SIZE (2 * 2 - 1)
8330 #define BR_LARGE_SIZE (6 * 2 - 1)
8331 #define MOV_REG_IMM_SIZE (10 * 2 - 1)
8332 #define MOV_REG_IMM_32BIT_SIZE (6 * 2 - 1)
8333 /* Jump reg for NaCl adds a mask (+4) and add (+3) */
8334 #define JUMP_REG_SIZE ((2 + 1 + 4 + 3) * 2 - 1)
8335 /* Jump membase's size is large and unpredictable    */
8336 /* in native client, just pad it out a whole bundle. */
8337 #define JUMP_MEMBASE_SIZE (kNaClAlignment)
8338 #endif
8339
8340 static int
8341 imt_branch_distance (MonoIMTCheckItem **imt_entries, int start, int target)
8342 {
8343         int i, distance = 0;
8344         for (i = start; i < target; ++i)
8345                 distance += imt_entries [i]->chunk_size;
8346         return distance;
8347 }
8348
8349 /*
8350  * LOCKING: called with the domain lock held
8351  */
8352 gpointer
8353 mono_arch_build_imt_thunk (MonoVTable *vtable, MonoDomain *domain, MonoIMTCheckItem **imt_entries, int count,
8354         gpointer fail_tramp)
8355 {
8356         int i;
8357         int size = 0;
8358         guint8 *code, *start;
8359         gboolean vtable_is_32bit = ((gsize)(vtable) == (gsize)(int)(gsize)(vtable));
8360         GSList *unwind_ops;
8361
8362         for (i = 0; i < count; ++i) {
8363                 MonoIMTCheckItem *item = imt_entries [i];
8364                 if (item->is_equals) {
8365                         if (item->check_target_idx) {
8366                                 if (!item->compare_done) {
8367                                         if (amd64_use_imm32 ((gint64)item->key))
8368                                                 item->chunk_size += CMP_SIZE;
8369                                         else
8370                                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8371                                 }
8372                                 if (item->has_target_code) {
8373                                         item->chunk_size += MOV_REG_IMM_SIZE;
8374                                 } else {
8375                                         if (vtable_is_32bit)
8376                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8377                                         else
8378                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8379 #ifdef __native_client_codegen__
8380                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8381 #endif
8382                                 }
8383                                 item->chunk_size += BR_SMALL_SIZE + JUMP_REG_SIZE;
8384                         } else {
8385                                 if (fail_tramp) {
8386                                         item->chunk_size += MOV_REG_IMM_SIZE * 3 + CMP_REG_REG_SIZE +
8387                                                 BR_SMALL_SIZE + JUMP_REG_SIZE * 2;
8388                                 } else {
8389                                         if (vtable_is_32bit)
8390                                                 item->chunk_size += MOV_REG_IMM_32BIT_SIZE;
8391                                         else
8392                                                 item->chunk_size += MOV_REG_IMM_SIZE;
8393                                         item->chunk_size += JUMP_REG_SIZE;
8394                                         /* with assert below:
8395                                          * item->chunk_size += CMP_SIZE + BR_SMALL_SIZE + 1;
8396                                          */
8397 #ifdef __native_client_codegen__
8398                                         item->chunk_size += JUMP_MEMBASE_SIZE;
8399 #endif
8400                                 }
8401                         }
8402                 } else {
8403                         if (amd64_use_imm32 ((gint64)item->key))
8404                                 item->chunk_size += CMP_SIZE;
8405                         else
8406                                 item->chunk_size += MOV_REG_IMM_SIZE + CMP_REG_REG_SIZE;
8407                         item->chunk_size += BR_LARGE_SIZE;
8408                         imt_entries [item->check_target_idx]->compare_done = TRUE;
8409                 }
8410                 size += item->chunk_size;
8411         }
8412 #if defined(__native_client__) && defined(__native_client_codegen__)
8413         /* In Native Client, we don't re-use thunks, allocate from the */
8414         /* normal code manager paths. */
8415         code = mono_domain_code_reserve (domain, size);
8416 #else
8417         if (fail_tramp)
8418                 code = (guint8 *)mono_method_alloc_generic_virtual_thunk (domain, size);
8419         else
8420                 code = (guint8 *)mono_domain_code_reserve (domain, size);
8421 #endif
8422         start = code;
8423
8424         unwind_ops = mono_arch_get_cie_program ();
8425
8426         for (i = 0; i < count; ++i) {
8427                 MonoIMTCheckItem *item = imt_entries [i];
8428                 item->code_target = code;
8429                 if (item->is_equals) {
8430                         gboolean fail_case = !item->check_target_idx && fail_tramp;
8431
8432                         if (item->check_target_idx || fail_case) {
8433                                 if (!item->compare_done || fail_case) {
8434                                         if (amd64_use_imm32 ((gint64)item->key))
8435                                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8436                                         else {
8437                                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof(gpointer));
8438                                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8439                                         }
8440                                 }
8441                                 item->jmp_code = code;
8442                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8443                                 if (item->has_target_code) {
8444                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->value.target_code);
8445                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8446                                 } else {
8447                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8448                                         amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8449                                 }
8450
8451                                 if (fail_case) {
8452                                         amd64_patch (item->jmp_code, code);
8453                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, fail_tramp);
8454                                         amd64_jump_reg (code, MONO_ARCH_IMT_SCRATCH_REG);
8455                                         item->jmp_code = NULL;
8456                                 }
8457                         } else {
8458                                 /* enable the commented code to assert on wrong method */
8459 #if 0
8460                                 if (amd64_is_imm32 (item->key))
8461                                         amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof(gpointer));
8462                                 else {
8463                                         amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, item->key);
8464                                         amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8465                                 }
8466                                 item->jmp_code = code;
8467                                 amd64_branch8 (code, X86_CC_NE, 0, FALSE);
8468                                 /* See the comment below about R10 */
8469                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8470                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8471                                 amd64_patch (item->jmp_code, code);
8472                                 amd64_breakpoint (code);
8473                                 item->jmp_code = NULL;
8474 #else
8475                                 /* We're using R10 (MONO_ARCH_IMT_SCRATCH_REG) here because R11 (MONO_ARCH_IMT_REG)
8476                                    needs to be preserved.  R10 needs
8477                                    to be preserved for calls which
8478                                    require a runtime generic context,
8479                                    but interface calls don't. */
8480                                 amd64_mov_reg_imm (code, MONO_ARCH_IMT_SCRATCH_REG, & (vtable->vtable [item->value.vtable_slot]));
8481                                 amd64_jump_membase (code, MONO_ARCH_IMT_SCRATCH_REG, 0);
8482 #endif
8483                         }
8484                 } else {
8485                         if (amd64_use_imm32 ((gint64)item->key))
8486                                 amd64_alu_reg_imm_size (code, X86_CMP, MONO_ARCH_IMT_REG, (guint32)(gssize)item->key, sizeof (gpointer));
8487                         else {
8488                                 amd64_mov_reg_imm_size (code, MONO_ARCH_IMT_SCRATCH_REG, item->key, sizeof (gpointer));
8489                                 amd64_alu_reg_reg (code, X86_CMP, MONO_ARCH_IMT_REG, MONO_ARCH_IMT_SCRATCH_REG);
8490                         }
8491                         item->jmp_code = code;
8492                         if (x86_is_imm8 (imt_branch_distance (imt_entries, i, item->check_target_idx)))
8493                                 x86_branch8 (code, X86_CC_GE, 0, FALSE);
8494                         else
8495                                 x86_branch32 (code, X86_CC_GE, 0, FALSE);
8496                 }
8497                 g_assert (code - item->code_target <= item->chunk_size);
8498         }
8499         /* patch the branches to get to the target items */
8500         for (i = 0; i < count; ++i) {
8501                 MonoIMTCheckItem *item = imt_entries [i];
8502                 if (item->jmp_code) {
8503                         if (item->check_target_idx) {
8504                                 amd64_patch (item->jmp_code, imt_entries [item->check_target_idx]->code_target);
8505                         }
8506                 }
8507         }
8508
8509         if (!fail_tramp)
8510                 mono_stats.imt_thunks_size += code - start;
8511         g_assert (code - start <= size);
8512
8513         nacl_domain_code_validate(domain, &start, size, &code);
8514         mono_profiler_code_buffer_new (start, code - start, MONO_PROFILER_CODE_BUFFER_IMT_TRAMPOLINE, NULL);
8515
8516         mono_tramp_info_register (mono_tramp_info_create (NULL, start, code - start, NULL, unwind_ops), domain);
8517
8518         return start;
8519 }
8520
8521 MonoMethod*
8522 mono_arch_find_imt_method (mgreg_t *regs, guint8 *code)
8523 {
8524         return (MonoMethod*)regs [MONO_ARCH_IMT_REG];
8525 }
8526
8527 MonoVTable*
8528 mono_arch_find_static_call_vtable (mgreg_t *regs, guint8 *code)
8529 {
8530         return (MonoVTable*) regs [MONO_ARCH_RGCTX_REG];
8531 }
8532
8533 GSList*
8534 mono_arch_get_cie_program (void)
8535 {
8536         GSList *l = NULL;
8537
8538         mono_add_unwind_op_def_cfa (l, (guint8*)NULL, (guint8*)NULL, AMD64_RSP, 8);
8539         mono_add_unwind_op_offset (l, (guint8*)NULL, (guint8*)NULL, AMD64_RIP, -8);
8540
8541         return l;
8542 }
8543
8544 #ifndef DISABLE_JIT
8545
8546 MonoInst*
8547 mono_arch_emit_inst_for_method (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsig, MonoInst **args)
8548 {
8549         MonoInst *ins = NULL;
8550         int opcode = 0;
8551
8552         if (cmethod->klass == mono_defaults.math_class) {
8553                 if (strcmp (cmethod->name, "Sin") == 0) {
8554                         opcode = OP_SIN;
8555                 } else if (strcmp (cmethod->name, "Cos") == 0) {
8556                         opcode = OP_COS;
8557                 } else if (strcmp (cmethod->name, "Sqrt") == 0) {
8558                         opcode = OP_SQRT;
8559                 } else if (strcmp (cmethod->name, "Abs") == 0 && fsig->params [0]->type == MONO_TYPE_R8) {
8560                         opcode = OP_ABS;
8561                 }
8562
8563                 if (opcode && fsig->param_count == 1) {
8564                         MONO_INST_NEW (cfg, ins, opcode);
8565                         ins->type = STACK_R8;
8566                         ins->dreg = mono_alloc_freg (cfg);
8567                         ins->sreg1 = args [0]->dreg;
8568                         MONO_ADD_INS (cfg->cbb, ins);
8569                 }
8570
8571                 opcode = 0;
8572                 if (cfg->opt & MONO_OPT_CMOV) {
8573                         if (strcmp (cmethod->name, "Min") == 0) {
8574                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8575                                         opcode = OP_IMIN;
8576                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8577                                         opcode = OP_IMIN_UN;
8578                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8579                                         opcode = OP_LMIN;
8580                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8581                                         opcode = OP_LMIN_UN;
8582                         } else if (strcmp (cmethod->name, "Max") == 0) {
8583                                 if (fsig->params [0]->type == MONO_TYPE_I4)
8584                                         opcode = OP_IMAX;
8585                                 if (fsig->params [0]->type == MONO_TYPE_U4)
8586                                         opcode = OP_IMAX_UN;
8587                                 else if (fsig->params [0]->type == MONO_TYPE_I8)
8588                                         opcode = OP_LMAX;
8589                                 else if (fsig->params [0]->type == MONO_TYPE_U8)
8590                                         opcode = OP_LMAX_UN;
8591                         }
8592                 }
8593
8594                 if (opcode && fsig->param_count == 2) {
8595                         MONO_INST_NEW (cfg, ins, opcode);
8596                         ins->type = fsig->params [0]->type == MONO_TYPE_I4 ? STACK_I4 : STACK_I8;
8597                         ins->dreg = mono_alloc_ireg (cfg);
8598                         ins->sreg1 = args [0]->dreg;
8599                         ins->sreg2 = args [1]->dreg;
8600                         MONO_ADD_INS (cfg->cbb, ins);
8601                 }
8602
8603 #if 0
8604                 /* OP_FREM is not IEEE compatible */
8605                 else if (strcmp (cmethod->name, "IEEERemainder") == 0 && fsig->param_count == 2) {
8606                         MONO_INST_NEW (cfg, ins, OP_FREM);
8607                         ins->inst_i0 = args [0];
8608                         ins->inst_i1 = args [1];
8609                 }
8610 #endif
8611         }
8612
8613         return ins;
8614 }
8615 #endif
8616
8617 gboolean
8618 mono_arch_print_tree (MonoInst *tree, int arity)
8619 {
8620         return 0;
8621 }
8622
8623 mgreg_t
8624 mono_arch_context_get_int_reg (MonoContext *ctx, int reg)
8625 {
8626         return ctx->gregs [reg];
8627 }
8628
8629 void
8630 mono_arch_context_set_int_reg (MonoContext *ctx, int reg, mgreg_t val)
8631 {
8632         ctx->gregs [reg] = val;
8633 }
8634
8635 gpointer
8636 mono_arch_install_handler_block_guard (MonoJitInfo *ji, MonoJitExceptionInfo *clause, MonoContext *ctx, gpointer new_value)
8637 {
8638         gpointer *sp, old_value;
8639         char *bp;
8640
8641         /*Load the spvar*/
8642         bp = (char *)MONO_CONTEXT_GET_BP (ctx);
8643         sp = (gpointer *)*(gpointer*)(bp + clause->exvar_offset);
8644
8645         old_value = *sp;
8646         if (old_value < ji->code_start || (char*)old_value > ((char*)ji->code_start + ji->code_size))
8647                 return old_value;
8648
8649         *sp = new_value;
8650
8651         return old_value;
8652 }
8653
8654 /*
8655  * mono_arch_emit_load_aotconst:
8656  *
8657  *   Emit code to load the contents of the GOT slot identified by TRAMP_TYPE and
8658  * TARGET from the mscorlib GOT in full-aot code.
8659  * On AMD64, the result is placed into R11.
8660  */
8661 guint8*
8662 mono_arch_emit_load_aotconst (guint8 *start, guint8 *code, MonoJumpInfo **ji, MonoJumpInfoType tramp_type, gconstpointer target)
8663 {
8664         *ji = mono_patch_info_list_prepend (*ji, code - start, tramp_type, target);
8665         amd64_mov_reg_membase (code, AMD64_R11, AMD64_RIP, 0, 8);
8666
8667         return code;
8668 }
8669
8670 /*
8671  * mono_arch_get_trampolines:
8672  *
8673  *   Return a list of MonoTrampInfo structures describing arch specific trampolines
8674  * for AOT.
8675  */
8676 GSList *
8677 mono_arch_get_trampolines (gboolean aot)
8678 {
8679         return mono_amd64_get_exception_trampolines (aot);
8680 }
8681
8682 /* Soft Debug support */
8683 #ifdef MONO_ARCH_SOFT_DEBUG_SUPPORTED
8684
8685 /*
8686  * mono_arch_set_breakpoint:
8687  *
8688  *   Set a breakpoint at the native code corresponding to JI at NATIVE_OFFSET.
8689  * The location should contain code emitted by OP_SEQ_POINT.
8690  */
8691 void
8692 mono_arch_set_breakpoint (MonoJitInfo *ji, guint8 *ip)
8693 {
8694         guint8 *code = ip;
8695
8696         if (ji->from_aot) {
8697                 guint32 native_offset = ip - (guint8*)ji->code_start;
8698                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8699
8700                 g_assert (info->bp_addrs [native_offset] == 0);
8701                 info->bp_addrs [native_offset] = mini_get_breakpoint_trampoline ();
8702         } else {
8703                 /* ip points to a mov r11, 0 */
8704                 g_assert (code [0] == 0x41);
8705                 g_assert (code [1] == 0xbb);
8706                 amd64_mov_reg_imm (code, AMD64_R11, 1);
8707         }
8708 }
8709
8710 /*
8711  * mono_arch_clear_breakpoint:
8712  *
8713  *   Clear the breakpoint at IP.
8714  */
8715 void
8716 mono_arch_clear_breakpoint (MonoJitInfo *ji, guint8 *ip)
8717 {
8718         guint8 *code = ip;
8719
8720         if (ji->from_aot) {
8721                 guint32 native_offset = ip - (guint8*)ji->code_start;
8722                 SeqPointInfo *info = (SeqPointInfo *)mono_arch_get_seq_point_info (mono_domain_get (), (guint8 *)ji->code_start);
8723
8724                 info->bp_addrs [native_offset] = NULL;
8725         } else {
8726                 amd64_mov_reg_imm (code, AMD64_R11, 0);
8727         }
8728 }
8729
8730 gboolean
8731 mono_arch_is_breakpoint_event (void *info, void *sigctx)
8732 {
8733         /* We use soft breakpoints on amd64 */
8734         return FALSE;
8735 }
8736
8737 /*
8738  * mono_arch_skip_breakpoint:
8739  *
8740  *   Modify CTX so the ip is placed after the breakpoint instruction, so when
8741  * we resume, the instruction is not executed again.
8742  */
8743 void
8744 mono_arch_skip_breakpoint (MonoContext *ctx, MonoJitInfo *ji)
8745 {
8746         g_assert_not_reached ();
8747 }
8748
8749 /*
8750  * mono_arch_start_single_stepping:
8751  *
8752  *   Start single stepping.
8753  */
8754 void
8755 mono_arch_start_single_stepping (void)
8756 {
8757         ss_trampoline = mini_get_single_step_trampoline ();
8758 }
8759
8760 /*
8761  * mono_arch_stop_single_stepping:
8762  *
8763  *   Stop single stepping.
8764  */
8765 void
8766 mono_arch_stop_single_stepping (void)
8767 {
8768         ss_trampoline = NULL;
8769 }
8770
8771 /*
8772  * mono_arch_is_single_step_event:
8773  *
8774  *   Return whenever the machine state in SIGCTX corresponds to a single
8775  * step event.
8776  */
8777 gboolean
8778 mono_arch_is_single_step_event (void *info, void *sigctx)
8779 {
8780         /* We use soft breakpoints on amd64 */
8781         return FALSE;
8782 }
8783
8784 /*
8785  * mono_arch_skip_single_step:
8786  *
8787  *   Modify CTX so the ip is placed after the single step trigger instruction,
8788  * we resume, the instruction is not executed again.
8789  */
8790 void
8791 mono_arch_skip_single_step (MonoContext *ctx)
8792 {
8793         g_assert_not_reached ();
8794 }
8795
8796 /*
8797  * mono_arch_create_seq_point_info:
8798  *
8799  *   Return a pointer to a data structure which is used by the sequence
8800  * point implementation in AOTed code.
8801  */
8802 gpointer
8803 mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
8804 {
8805         SeqPointInfo *info;
8806         MonoJitInfo *ji;
8807
8808         // FIXME: Add a free function
8809
8810         mono_domain_lock (domain);
8811         info = (SeqPointInfo *)g_hash_table_lookup (domain_jit_info (domain)->arch_seq_points,
8812                                                                 code);
8813         mono_domain_unlock (domain);
8814
8815         if (!info) {
8816                 ji = mono_jit_info_table_find (domain, (char*)code);
8817                 g_assert (ji);
8818
8819                 // FIXME: Optimize the size
8820                 info = (SeqPointInfo *)g_malloc0 (sizeof (SeqPointInfo) + (ji->code_size * sizeof (gpointer)));
8821
8822                 info->ss_tramp_addr = &ss_trampoline;
8823
8824                 mono_domain_lock (domain);
8825                 g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,
8826                                                          code, info);
8827                 mono_domain_unlock (domain);
8828         }
8829
8830         return info;
8831 }
8832
8833 void
8834 mono_arch_init_lmf_ext (MonoLMFExt *ext, gpointer prev_lmf)
8835 {
8836         ext->lmf.previous_lmf = prev_lmf;
8837         /* Mark that this is a MonoLMFExt */
8838         ext->lmf.previous_lmf = (gpointer)(((gssize)ext->lmf.previous_lmf) | 2);
8839         ext->lmf.rsp = (gssize)ext;
8840 }
8841
8842 #endif
8843
8844 gboolean
8845 mono_arch_opcode_supported (int opcode)
8846 {
8847         switch (opcode) {
8848         case OP_ATOMIC_ADD_I4:
8849         case OP_ATOMIC_ADD_I8:
8850         case OP_ATOMIC_EXCHANGE_I4:
8851         case OP_ATOMIC_EXCHANGE_I8:
8852         case OP_ATOMIC_CAS_I4:
8853         case OP_ATOMIC_CAS_I8:
8854         case OP_ATOMIC_LOAD_I1:
8855         case OP_ATOMIC_LOAD_I2:
8856         case OP_ATOMIC_LOAD_I4:
8857         case OP_ATOMIC_LOAD_I8:
8858         case OP_ATOMIC_LOAD_U1:
8859         case OP_ATOMIC_LOAD_U2:
8860         case OP_ATOMIC_LOAD_U4:
8861         case OP_ATOMIC_LOAD_U8:
8862         case OP_ATOMIC_LOAD_R4:
8863         case OP_ATOMIC_LOAD_R8:
8864         case OP_ATOMIC_STORE_I1:
8865         case OP_ATOMIC_STORE_I2:
8866         case OP_ATOMIC_STORE_I4:
8867         case OP_ATOMIC_STORE_I8:
8868         case OP_ATOMIC_STORE_U1:
8869         case OP_ATOMIC_STORE_U2:
8870         case OP_ATOMIC_STORE_U4:
8871         case OP_ATOMIC_STORE_U8:
8872         case OP_ATOMIC_STORE_R4:
8873         case OP_ATOMIC_STORE_R8:
8874                 return TRUE;
8875         default:
8876                 return FALSE;
8877         }
8878 }
8879
8880 #if defined(ENABLE_GSHAREDVT) && defined(MONO_ARCH_GSHAREDVT_SUPPORTED)
8881
8882 #include "../../../mono-extensions/mono/mini/mini-amd64-gsharedvt.c"
8883
8884 #endif /* !ENABLE_GSHAREDVT */